WO2022001410A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2022001410A1
WO2022001410A1 PCT/CN2021/093627 CN2021093627W WO2022001410A1 WO 2022001410 A1 WO2022001410 A1 WO 2022001410A1 CN 2021093627 W CN2021093627 W CN 2021093627W WO 2022001410 A1 WO2022001410 A1 WO 2022001410A1
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WIPO (PCT)
Prior art keywords
electrode pattern
electrode
electrically connected
display substrate
pattern
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PCT/CN2021/093627
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English (en)
French (fr)
Inventor
周宏军
谭文
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to DE112021000234.1T priority Critical patent/DE112021000234T5/de
Priority to US17/773,077 priority patent/US20240147786A1/en
Publication of WO2022001410A1 publication Critical patent/WO2022001410A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • Embodiments of the present disclosure relate to a display substrate and a display device.
  • OLED display devices have the advantages of thin thickness, light weight, wide viewing angle, active light emission, continuously adjustable light emission color, low cost, fast response speed, low energy consumption, low driving voltage, and operating temperature. Due to the advantages of wide range, simple production process, high luminous efficiency and flexible display, it is more and more widely used in display fields such as mobile phones, tablet computers, and digital cameras.
  • At least one embodiment of the present disclosure provides a display substrate, the display substrate has a display area and a peripheral area at least partially surrounding the display area, and includes: a base substrate; wherein, the display area includes an array arranged on the a plurality of pixel units on the base substrate and a plurality of signal lines electrically connected to the plurality of pixel units respectively, the peripheral area includes at least one first electrode electrically connected to at least one of the plurality of signal lines pattern, and includes a second electrode pattern, the at least one first electrode pattern and the second electrode pattern at least partially overlap in a direction perpendicular to the board surface of the base substrate and are arranged in an insulating manner, the peripheral The region further includes a gate scanning driving circuit, the gate scanning driving circuit is configured to provide gate scanning signals to the plurality of pixel units, and in a direction parallel to the board surface of the base substrate, the at least one first An electrode pattern and the second electrode pattern are located between the gate scan driving circuit and the display area.
  • the orthographic projection of the at least one first electrode pattern on the base substrate is located at the orthographic projection of the second electrode pattern on the base substrate Inside.
  • the second electrode pattern is located on a side of the at least one first electrode pattern away from the base substrate.
  • At least one of the plurality of pixel units includes a pixel driving circuit located on the base substrate, and the pixel driving circuit includes a thin film transistor and a storage capacitor;
  • the thin film transistor includes an active layer, a gate electrode, a source electrode and a drain electrode, and the storage capacitor includes a first capacitor electrode and is opposite to the first capacitor electrode in a direction perpendicular to the board surface of the base substrate the second capacitor electrode;
  • the source electrode and the drain electrode are located on the side of the active layer away from the base substrate, the first electrode pattern, the gate electrode and the first capacitor electrode are the same layer arrangement, the second electrode pattern and the second capacitor electrode are arranged in the same layer.
  • the plurality of signal lines are disposed in the same layer as the source and drain electrodes of the thin film transistor, and the at least one first electrode pattern is connected to all the signal lines through a via structure. At least one of the plurality of signal lines is electrically connected.
  • the second electrode pattern is configured to receive a first voltage signal from a first voltage source.
  • the peripheral region further includes a power supply wiring pattern, the power supply wiring pattern is electrically connected to the first voltage source, and the second electrode pattern is connected to the power supply wiring pattern.
  • the power trace pattern is electrically connected to receive the first voltage signal through the power trace pattern.
  • the power supply wiring pattern is provided in the same layer as the source and drain electrodes of the thin film transistor, and the second electrode pattern is connected to the power supply through a via structure.
  • the trace patterns are electrically connected.
  • the display substrate provided by at least one embodiment of the present disclosure, in a direction parallel to the board surface of the base substrate, at least part of the second electrode pattern is electrically connected between the power supply wiring pattern and the Between the plurality of pixel units, the power supply wiring pattern provides the first voltage signal to at least part of the plurality of pixel units through the second electrode pattern.
  • the at least one first electrode pattern includes a plurality of first electrode patterns, and the plurality of first electrode patterns are arranged at intervals; A spacer pattern between two adjacent first electrode patterns and insulated from the first electrode patterns.
  • the spacer pattern is configured to receive a second voltage signal from a second voltage source different from the first voltage source.
  • the spacer pattern is electrically connected to the second electrode pattern to receive the first voltage signal from the first voltage source.
  • the spacer pattern is disposed in the same layer as the active layer of the thin film transistor.
  • the second electrode patterns are continuously arranged along the edge of the display area, and are respectively aligned with the The plurality of first electrode patterns at least partially overlap and are spaced and insulated.
  • the extending direction of at least a part of the edge of the display area intersects and is not perpendicular to the extending direction of the plurality of signal lines.
  • the display substrate further includes a first insulating layer located between the first electrode pattern and the second electrode pattern, and the first insulating layer has a Materials include silicon nitride or silicon oxynitride.
  • the plurality of pixel units include a first column of pixel units and a second column of pixel units, and the number of pixel units in the first column of pixel units is less than the number of pixel units in the first column of pixel units.
  • the number of pixel units in the second column of pixel units, the signal line electrically connected to the first column of pixel units is electrically connected to a first electrode pattern.
  • a signal line electrically connected to the second column of pixel units is electrically connected to another first electrode pattern, and the second electrode pattern is electrically connected to the first electrode pattern.
  • the compensation capacitance formed by the one first electrode pattern electrically connected to the signal line electrically connected to the column pixel unit is larger than the compensation capacitance formed by the second electrode pattern and the other one electrically connected to the signal line electrically connected to the second column pixel unit.
  • the first electrode pattern and the second electrode pattern have different lengths in the column direction, or the first electrode pattern and the second electrode pattern have different lengths in the column direction.
  • the lengths in the row direction are different.
  • the plurality of signal lines are scan lines or data lines.
  • a first end or a second end of at least one of the plurality of signal lines is electrically connected to a first electrode pattern, or one of the plurality of signal lines is electrically connected to a first electrode pattern.
  • the first end of at least one of the signal lines is electrically connected to one first electrode pattern, and the second end of at least one of the plurality of signal lines is electrically connected to another first electrode pattern.
  • At least one embodiment of the present disclosure further provides a display device including the display substrate described in any embodiment of the present disclosure.
  • FIG. 1A is a schematic plan view of a display substrate according to some embodiments of the present disclosure.
  • 1B is a schematic plan view of another display substrate provided by some embodiments of the present disclosure.
  • FIG. 2A is a schematic diagram of a compensation method for the display substrate shown in FIG. 1A according to some embodiments of the present disclosure
  • FIG. 2B is a schematic diagram of another compensation manner of the display substrate shown in FIG. 1A provided by some embodiments of the present disclosure
  • FIG. 2C is a schematic diagram of yet another compensation method for the display substrate shown in FIG. 1A provided by some embodiments of the present disclosure
  • FIG. 3 is a schematic diagram of a partial structure of a display substrate provided by some embodiments of the present disclosure.
  • FIG. 4 is a schematic diagram of a partial plane structure of a peripheral region of a display substrate according to some embodiments of the present disclosure
  • 5A is a schematic diagram of a partial cross-sectional structure of a peripheral region of a display substrate according to some embodiments of the present disclosure
  • 5B is a schematic diagram of a partial cross-sectional structure of a peripheral region of another display substrate according to some embodiments of the present disclosure
  • FIG. 6 is a schematic diagram of a partial cross-sectional structure of a display area and a partial cross-sectional structure of a peripheral area of a display substrate according to some embodiments of the present disclosure
  • FIG. 7 is an equivalent circuit diagram of a pixel driving circuit in a display substrate provided by some embodiments of the present disclosure.
  • FIGS. 8A-8E are schematic diagrams of various layers of a pixel driving circuit in a display substrate according to some embodiments of the present disclosure.
  • FIG. 9 is a schematic block diagram of a display device according to some embodiments of the present disclosure.
  • FIG. 10 is a schematic block diagram of another display device provided by some embodiments of the present disclosure.
  • the appearance or display area of electronic display products sometimes needs to be designed into irregular or special shapes.
  • the display area has an irregular or special shape, the number of pixel units included in different rows in the display area may be different, or the number of pixel units included in different columns in the display area may also be different. For example, taking the different number of pixel units included in different columns in the display area as an example, because the number of pixel units in different columns is different, the number of pixel units in different columns is used to provide, for example, data signals or other required pixel units in different columns.
  • the transmission loads on the multiple signal lines of the electrical signal may be different, resulting in inconsistent signal transmission effects (such as transmission speed) of the multiple signal lines, which in turn leads to a decrease in the brightness uniformity and consistency of the provided display screen, and may even be degraded. Display abnormal phenomenon occurs.
  • At least one embodiment of the present disclosure provides a display substrate having a display area and a peripheral area at least partially surrounding the display area, and including a base substrate.
  • the display area includes a plurality of pixel units arranged in an array on the base substrate and a plurality of signal lines respectively electrically connected to the plurality of pixel units;
  • the peripheral area includes at least one first one electrically connected to at least one of the plurality of signal lines an electrode pattern, and a second electrode pattern, the at least one first electrode pattern and the second electrode pattern at least partially overlap in a direction perpendicular to the board surface of the base substrate and are arranged at intervals;
  • the peripheral area also includes a gate scan drive The circuit, the gate scanning driving circuit is configured to provide gate scanning signals to a plurality of pixel units, and in a direction parallel to the board surface of the base substrate, at least one first electrode pattern and a second electrode pattern are located between the gate scanning driving circuit and the display between regions.
  • the first electrode pattern and the second electrode pattern are at least partially overlapped in a direction perpendicular to the board surface of the base substrate and are arranged in an insulating manner from each other.
  • Capacitance can be formed between the electrode patterns, so as to compensate the transmission load on the signal line electrically connected to the first electrode pattern, so as to improve the consistency of the signal transmission effect of multiple signal lines, thereby making the brightness uniformity of the display screen. And the consistency is improved, so as to reduce or avoid the abnormal or bad phenomenon of the display screen, and improve the display effect of the screen.
  • FIG. 1A is a schematic plan view of a display substrate according to some embodiments of the present disclosure.
  • the display substrate 10 has a display area 101 and a peripheral area 102 at least partially surrounding (eg, completely surrounding) the display area 101 .
  • the shape of the display area 101 of the display substrate 10 may be a circle, and the peripheral area 102 surrounds the display area 101 and has an approximate circular outline, so that the display substrate 10 has an approximately circular shape to satisfy users' different perceptions of The actual needs of the shape of the display substrate.
  • FIG. 1B is a schematic plan view of another display substrate provided by some embodiments of the present disclosure.
  • the display substrate 20 has a display area 201 and a peripheral area 202 at least partially surrounding (eg, completely surrounding) the display area 201 .
  • the shape of the display area 201 of the display substrate 20 may be a square with rounded corners
  • the peripheral area 202 surrounds the display area 201 and has the same outline as the display area 201 , thereby making the display substrate 20 a square with rounded corners.
  • the display substrate may also be in a regular shape such as an ellipse, a fan, a triangle, a rhombus, a pentagon, etc., or may also be in other suitable irregular shapes, which are not made in the embodiments of the present disclosure. limit.
  • the embodiment of the present disclosure takes the shape of the display substrate 10 shown in FIG. 1A as an example to describe the display substrate provided by the embodiment of the present disclosure, but this does not constitute a limitation to the embodiment of the present disclosure.
  • FIG. 2A is a schematic diagram of a compensation method of the display substrate shown in FIG. 1A provided by some embodiments of the present disclosure
  • FIG. 3 is a schematic diagram of a partial structure of a display substrate provided by some embodiments of the present disclosure.
  • FIG. 3 may correspond to The region REG1 shown in FIG. 2A.
  • the display substrate 10 includes a base substrate 100 .
  • the display area 101 includes a plurality of pixel units 110 arranged in an array on the base substrate 100 and a plurality of signal lines 120 electrically connected to the plurality of pixel units 110 respectively.
  • the peripheral region 102 includes at least one first electrode pattern 130 electrically connected to at least one of the plurality of signal lines 120 , and includes a second electrode pattern 140 .
  • the first electrode pattern 130 and the second electrode pattern 140 are at least partially overlapped in the direction perpendicular to the board surface of the base substrate 100 and are arranged at intervals to form a capacitor, so that the first electrode pattern 130 and the second electrode pattern can pass through the first electrode pattern 130 and the second electrode pattern.
  • the capacitance formed between 140 and the transmission load on the signal line 120 electrically connected to the first electrode pattern 130 (for example, the transmission load on the signal line 120 may refer to the transmission resistance of the signal line 120, or the signal line 120 and other
  • the capacitance formed between the traces) is compensated, so as to improve the consistency of the transmission load on the plurality of signal lines 120 in the display area 101 .
  • the signal transmission effect of the plurality of signal lines 120 in the display area 101 can be improved, and the brightness uniformity and consistency of the provided display screen can be improved, thereby reducing or avoiding the display abnormality or bad phenomenon of the display screen, and improving the screen display effect.
  • the signal line 120 may be a scan line, for example, for providing gate scan signals to the pixel unit 110, or may also be a data line, for example, for providing a data signal to the pixel unit 110, or also It can be a signal line for supplying the pixel unit 110 with other electrical signals required for realizing picture display.
  • the capacitance formed between the first electrode pattern 130 and the second electrode pattern 140 compensates the transmission load on the scan line electrically connected to the first electrode pattern 130, thereby improving the For example, the transmission effect of the gate scan signals transmitted on the scan lines improves the consistency of the transmission effects of the gate scan signals on the plurality of scan lines in the display area 101 .
  • the capacitance formed between the first electrode pattern 130 and the second electrode pattern 140 compensates the transmission load on the data line electrically connected to the first electrode pattern 130, thereby improving the For example, the transmission effect of the data signal transmitted on the data line improves the consistency of the transmission effect of the data signal on the multiple data lines in the display area 101 .
  • the peripheral area 102 further includes a gate scan driving circuit (Gate on array, GOA) 150 , and the gate scan driving circuit 150 is configured to provide gate scan signals to the plurality of pixel units 110 , for example, directly fabricated on the base substrate 100 by a semiconductor process.
  • GOA gate on array
  • the first electrode pattern 130 and the second electrode pattern 140 are located between the gate scan driving circuit 150 and the display area 101, thereby improving the space utilization of the peripheral area 102, The space required to be occupied by the first electrode pattern 130 and the second electrode pattern 140 in the display substrate 10 is reduced, thereby facilitating the realization of a narrow frame design of the display substrate 10 .
  • the gate scan driving circuit 150 may include a plurality of cascaded shift register units, for example, the output end of each shift register unit is electrically connected to a row of pixel units 110 in the display area 101 through gate lines, so as to form a row of pixel units 110.
  • a plurality of pixel units 110 in the pixel units 110 provide gate scan signals.
  • a plurality of pixel units 110 may be arranged in an array in the display area 101 , and the gate scan driving circuit 150 is configured to provide gate scan signals, eg, shifted row by row, to the rows of pixel units 110 arranged in an array in the display area 101 .
  • the shift register unit in the gate scan driving circuit 150 may have a 4T1C structure, that is, at least include four transistors and one capacitor to respectively implement functions such as signal input, signal output, register reset, etc., or may also include more Transistors and/or capacitors, such as sub-circuits for implementing functions such as pull-up node control, pull-down node control, noise reduction, etc., are added to achieve more stable input, output, and reset, which are not limited in the embodiments of the present disclosure.
  • the first electrode pattern 130 may be electrically connected between the corresponding data line and the data driving circuit, and the data driving circuit is used to respectively provide the plurality of columns of pixel units 110 in the display area 101 with each other.
  • Corresponding data signals thereby realizing the transmission of the data signals through the signal lines 120 and the first electrode patterns 130; for example, the first electrode patterns 130 also at least partially play the role of transmitting the data signals.
  • the data driving circuit may convert digital image data input from the timing controller into data signals according to a plurality of data control signals from the timing controller using the reference gamma voltage.
  • the data driving circuit may be implemented as a semiconductor chip, which is then mounted on a flexible printed circuit board and coupled to data lines on the display substrate by bonding.
  • FIG. 4 is a schematic diagram of a partial plane structure of a peripheral region of a display substrate according to some embodiments of the present disclosure.
  • FIG. 4 corresponds to the region REG2 shown in FIG. 3 .
  • 5A is a schematic diagram of a partial cross-sectional structure of a peripheral region of a display substrate provided by some embodiments of the disclosure.
  • FIG. 5A may be a schematic diagram of a partial cross-sectional structure of the display substrate 10 along the line AA' shown in FIG. 3 .
  • . 5B is a schematic diagram of a partial cross-sectional structure of a peripheral region of another display substrate provided by some embodiments of the present disclosure.
  • FIG. 5B may be a partial cross-sectional structure of the display substrate 10 along the line BB' shown in FIG. 3 .
  • the orthographic projection of the first electrode pattern 130 on the base substrate 100 is located within the orthographic projection of the second electrode pattern 140 on the base substrate 100 , that is, perpendicular to the substrate In the direction R1 of the board surface of the substrate 100 , the second electrode pattern 140 completely covers the first electrode pattern 130 , thereby increasing the first electrode pattern 130 and the second electrode pattern 140 in the direction perpendicular to the board surface of the base substrate 100
  • the overlapping area on R1 increases the capacitance of the compensation capacitor formed between the first electrode pattern 130 and the second electrode pattern 140 , so that a stable capacitance can be formed between the first electrode pattern 130 and the second electrode pattern 140 . In this way, the compensation effect for the transmission load of the signal lines 120 can be further improved, thereby improving the stability and consistency of the signal transmission effects of the plurality of signal lines 120 in the display area 101 .
  • a device in order to improve the electrical connection effect between the first electrode pattern 130 and the signal line 120 , a device may also be provided between the first electrode pattern 130 and the signal line 120 for realizing A connector for the electrical connection between the two.
  • the connection member may be located in the same layer as the first electrode pattern 130 or the signal line 120, or may be located in a layer different from the first electrode pattern 130 and the signal line 120, which is not limited in the embodiment of the present disclosure .
  • the first electrode pattern 130 extends in a straight line and is elongated; in other embodiments of the present disclosure, the first electrode pattern 130 may also be curved,
  • the shape of the first electrode pattern 130 can also be oval, square, zigzag, or other suitable regular or irregular shapes according to actual needs, which is not made in the embodiments of the present disclosure. limit.
  • the second electrode pattern 140 is located on the side of the first electrode pattern 130 away from the base substrate 100 , so that the second electrode pattern 140 can play an electric field shielding function, which can reduce or avoid Other structures or devices located on the side of the second electrode pattern 140 away from the base substrate 100 in the display substrate 10 interfere with the electrical signal transmitted on the first electrode pattern 130 , thereby improving the electrical connection with the first electrode pattern 130 .
  • the stability of the electrical signal transmitted on the signal line 120 is provided.
  • FIG. 6 is a schematic diagram of a partial cross-sectional structure of a display area and a partial cross-sectional structure of a peripheral area of a display substrate according to some embodiments of the present disclosure.
  • the cross-sectional structure of the display substrate 10 shown in FIG. 6 may include the cross-sectional structure shown in FIG. 5A .
  • the cross-sectional structure of the peripheral region 102 of the display substrate 10 or the partial cross-sectional structure of the peripheral region 102 of the display substrate 10 shown in FIG. A partial cross-sectional structure of the pixel driving circuit of the unit 110 .
  • At least one of the plurality of pixel units 110 includes a pixel driving circuit located on the base substrate 100 , and the pixel driving circuit includes a thin film transistor 160 and a storage capacitor 170.
  • the thin film transistor 160 includes an active layer 161 , a gate electrode 162 , a source electrode 163 and a drain electrode 164
  • the storage capacitor 170 includes a first capacitor electrode 171 and the first capacitor electrode 171 in a direction R1 perpendicular to the board surface of the base substrate 100 . on the opposite second capacitive electrode 172 .
  • the source electrode 163 and the drain electrode 164 are located on the side of the active layer 161 away from the base substrate 100 .
  • the first electrode pattern 130 , the gate 162 and the first capacitor electrode 171 are provided in the same layer, and the second electrode pattern 140 and the second capacitor electrode 172 are provided in the same layer. Therefore, by forming the first electrode pattern 130, the gate electrode 162 and the first capacitor electrode 171 in the same layer in the manufacturing process (for example, using the same material layer to form through a patterning process), the second electrode pattern 140 and the second capacitor electrode are formed in the same layer. 172 is formed in the same layer in the preparation process, which can simplify the preparation process of the display substrate 10 and reduce the preparation cost of the display substrate 10 , thereby facilitating mass production and application of the display substrate 10 .
  • “same layer arrangement” means that two functional layers or structural layers are formed in the same layer and with the same material in the hierarchical structure of the display substrate, that is, in the preparation process, the two functional layers or structural layers are formed in the same layer and with the same material.
  • the layer or the structure layer can be formed by the same material layer, and the required pattern and structure can be formed by the same patterning process, for example, the material layer can be formed by the patterning process after the material layer is formed first.
  • the display substrate 10 further includes a first insulating layer 1101 located between the first electrode pattern 130 and the second electrode pattern 140, and the material of the first insulating layer 1101 may include, for example, silicon nitride or silicon oxynitride, or may also include Other insulating materials with higher dielectric constants.
  • the first electrode pattern can be A compensation capacitor having a larger capacitance is formed between the 130 and the second electrode pattern 140, so that the size of the first electrode pattern 130 and the second electrode pattern 140 can be reduced. In this way, the space occupied by the first electrode pattern 130 and the second electrode pattern 140 in a plane parallel to the base substrate 100 can be further reduced, which is beneficial for the display substrate 10 to realize a narrow frame design.
  • the first insulating layer 1101 is located between the first electrode pattern 130 and the second electrode pattern 140, that is, between the first capacitor electrode 171 and the second capacitor electrode 172, so that the first insulating layer 1101 can Increasing the capacitance of the compensation capacitor formed between the first electrode pattern 130 and the second electrode pattern 140 can also increase the capacitance of the storage capacitor formed between the first capacitor electrode 171 and the second capacitor electrode 172 , thereby improving the display.
  • the overall performance of the substrate 10 improves the stability of the display substrate 10 .
  • the display substrate 10 further includes a buffer layer 1104 , a second insulating layer 1102 and a third insulating layer 1103 .
  • the buffer layer 1104 is located on the base substrate 100
  • the active layer 161 is located on the side of the buffer layer 1104 away from the base substrate 100
  • the second insulating layer 1102 is located on the side of the active layer 161 away from the base substrate 100
  • the first electrode pattern 130, the gate 162 and the first capacitor electrode 171 are located on the side of the second insulating layer 1102 away from the base substrate 100
  • the first insulating layer 1101 is located on the first electrode pattern 130, the gate 162 and the first capacitor electrode 171 away from the substrate
  • the second electrode pattern 140 and the second capacitor electrode 172 are located on the side of the first insulating layer 1101 away from the base substrate 100
  • the third insulating layer 1103 is located on the side of the second electrode pattern 140 and the second capacitor electrode 172 away from On one side of the base substrate 100 , the source
  • a plurality of signal lines 120 may be provided in the same layer as the source electrode 163 and the drain electrode 164 of the thin film transistor 160 , and the first electrode pattern 130 may pass through, for example, the first insulating layer 1101 and the third insulating layer 1103 .
  • the via structure is electrically connected to the signal line 120 , thereby realizing compensation for the transmission load of the signal line 120 .
  • the display substrate further includes a protective layer (not shown) on a side of the source electrode 163 and the drain electrode 164 away from the base substrate 100 and a light emitting element (not shown) disposed on a side of the protective layer away from the base substrate 100 ), the source electrode 163 or the drain electrode 164 is electrically connected to the light emitting element provided on the protective layer through the via hole in the protective layer.
  • the material of the active layer 161 may include polysilicon or an oxide semiconductor (eg, indium gallium zinc oxide).
  • the material of the gate electrode 162 may include metal materials or alloy materials, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum, and titanium, for example, the multi-layer structure is a multi-metal stack layer (such as titanium, aluminum, and titanium three layers). metal stack (Al/Ti/Al)).
  • the material of the source electrode 163 and the drain electrode 164 may include metal materials or alloy materials, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum and titanium, for example, the multi-layer structure may be a multi-metal laminate (such as titanium). , aluminum and titanium three-layer metal stack (Al/Ti/Al)).
  • the embodiments of the present disclosure do not specifically limit the materials of each structure or functional layer.
  • the buffer layer 1104 can not only prevent harmful substances in the base substrate 100 from invading the interior of the display substrate 10 , but also can increase the adhesion of the films in the display substrate 10 on the base substrate 100 .
  • the material of the buffer layer 1104 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • materials of one or more of the first insulating layer 1101 , the second insulating layer 1102 , the third insulating layer 1103 and the protective layer may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the materials of the first insulating layer 1101 , the second insulating layer 1102 , the third insulating layer 1103 , the buffer layer 1104 and the protective layer may be the same or different from each other, which is not limited by the embodiment of the present disclosure.
  • FIG. 6 shows an example in which the thin film transistor 160 is a top-gate thin film transistor, and in some other embodiments of the present disclosure, the thin film transistor 160 may also be a bottom-gate thin film transistor or other suitable thin film transistors. type of thin film transistor, which is not limited by the embodiments of the present disclosure.
  • the display substrate 10 further includes a first voltage source 181
  • the second electrode pattern 140 is configured to receive a first voltage signal from the first voltage source 181 , so that the The second electrode pattern 140 has a stable voltage, whereby the stability of the compensation capacitance formed between the first electrode pattern 130 and the second electrode pattern 140 can be improved, and the first voltage signal can further weaken or avoid the voltage of the display substrate 10
  • the first voltage signal may be a high-level voltage signal or a low-level voltage signal, which is not limited in the embodiment of the present disclosure.
  • the peripheral area 102 further includes a power trace pattern 182 .
  • the power trace pattern 182 is electrically connected to the first voltage source 181
  • the second electrode pattern 140 is electrically connected to the power trace pattern 182 to receive the first voltage signal through the power trace pattern 182 .
  • the layout structure of the display substrate 10 can be improved, thereby facilitating the realization of the narrow frame design of the display substrate 10 , and at the same time, the manufacturing process of the display substrate 10 can be simplified.
  • the power trace pattern 182 may be located between the first voltage source 181 and the second electrode pattern 140, or may also be located at the first voltage source 181 and the side of the second electrode pattern 140 away from the display area 101; or, in some examples, in the direction perpendicular to the board surface of the base substrate 100, the power trace pattern 182 may also be connected with the second electrode pattern 140 At least partially overlapping, which is not limited by the embodiments of the present disclosure.
  • the power supply wiring pattern 182 may be provided in the same layer as the source electrode 163 and the drain electrode 164 of the thin film transistor 160, the second electrode pattern 140 is electrically connected to the power supply wiring pattern 182 through a via structure passing through the third insulating layer 1103, for example, Thereby, the layout structure in the peripheral region 102 of the display substrate 10 is optimized.
  • At least a part (eg, all parts) of the second electrode pattern 140 is electrically connected between the power wiring pattern 182 and the plurality of pixel units 110, and the power wiring pattern 182 provides a first voltage signal to at least a part of the plurality of pixel units 110 through the second electrode pattern 140 .
  • the second electrode pattern 140 is used to form a compensation capacitance with the first electrode pattern 130 to compensate the transmission load on the signal line 120 electrically connected to the first electrode pattern 130, the second electrode pattern 140 can also be used for transmission
  • the power supply voltage signal (ie, the first voltage signal) used for display can further optimize the layout structure of the display substrate 10 , help the display substrate 10 to realize a narrow frame design, and also improve the stability of the display substrate 10 .
  • the second electrode pattern 140 may be electrically connected to a plurality of first power lines 183 in the display area 101 to transmit the first voltage signal provided by the first voltage source 181 through the first power lines 183 to the pixel unit 110 .
  • the first power line 183 may be disposed in the same layer as the source electrode 163 and the drain electrode 164 of the thin film transistor 160 , and the second electrode pattern 140 is electrically connected to the first power line 183 through a via structure passing through the third insulating layer 1103 .
  • the peripheral region 102 of the display substrate 10 includes a plurality of first electrode patterns 130 , and the plurality of first electrode patterns 130 are arranged at intervals.
  • the peripheral region 102 further includes a spacer pattern 190 located between two adjacent first electrode patterns 130 and insulated from the first electrode patterns 130.
  • the spacer pattern The 190 can reduce or avoid signal interference between adjacent first electrode patterns 130 and improve the stability of electrical signals transmitted on the first electrode patterns 130 .
  • the spacer pattern 190 may be configured to receive a second voltage signal from a second voltage source different from the first voltage source, whereby the spacer pattern 190 and the adjacent first electrode pattern 130 may be in a Capacitors are formed in a plane parallel to the surface of the base substrate 100 , thereby further improving the compensation effect for the transmission load on the signal lines 120 electrically connected to the first electrode pattern 130 , and further improving the plurality of signal lines 120 in the display area 101 .
  • the spacer pattern 190 may also be electrically connected with the second electrode pattern 140 to receive the first voltage signal from the first voltage source 181 , thereby connecting the spacer pattern 190 with the adjacent first electrode
  • the layout structure in the peripheral region 102 of the display substrate 10 can be further optimized, thereby helping the display substrate 10 to realize a narrow frame design.
  • the spacer patterns 190 may be electrically connected with the second electrode patterns 140 through the first power lines 183 .
  • the spacer pattern 190 may be disposed in the same layer as the active layer 161 of the thin film transistor 160, and be electrically connected to the first power line 183 through a via structure penetrating at least the first insulating layer 1101, the second insulating layer 1102 and the third insulating layer 1103 , and is further electrically connected to the second electrode pattern 140 .
  • the preparation process of the display substrate 10 can be further simplified, and the reduction of the display substrate 10 can be reduced. Therefore, it is beneficial to the mass production and application of the display substrate 10 .
  • the spacing pattern 190 extends in a straight line and is elongated; and in some other embodiments of the present disclosure, the spacing pattern 190 may also extend in a curved line, a zigzag line, or other suitable contours,
  • the shape of the spacer pattern 190 may also adopt, for example, an oval, square, zigzag or other suitable regular or irregular shapes according to actual needs, which is not limited in the embodiments of the present disclosure.
  • the spacer pattern 190 in the extending direction of the spacer pattern 190, includes opposite first ends and second ends, and the first end is opposite to the second end. The end is closer to the display area 101 .
  • the first end of the spacer pattern 190 may be electrically connected to the first power supply line 183 and further to the second electrode pattern 140 , for example, through a via structure penetrating at least the first insulating layer 1101 , the second insulating layer 1102 and the third insulating layer 1103 .
  • both the first end and the second end of the spacer pattern 190 may be electrically connected to the first power line 183 or the second electrode pattern 140 through the via structure to simultaneously receive the first voltage signal,
  • the stability of the first voltage signal transmitted on the spacer pattern 190 is improved, which is not limited in the embodiment of the present disclosure.
  • the peripheral area 102 provided with the spacer pattern 190 at least partially surrounds the display area 101 and is disposed along the edge of the display area 101 , the spacer at the same layer as the active layer 161 of the thin film transistor 160 is formed by setting the spacer
  • the pattern 190 can reduce or avoid excessive etching of the active layer near the edge portion of the display area 101 during the preparation process of the display substrate 10, thereby improving the etching uniformity of the boundary position of the display area 101 to achieve better etching. etching effect.
  • the second electrode patterns 140 may be continuously arranged along the edge of the display area 101 , and are respectively connected with the plurality of first electrode patterns 130 in the direction R1 perpendicular to the board surface of the base substrate 100 . At least partially overlapped and spaced apart, thereby improving the consistency and stability of the first voltage signal transmitted on the second electrode pattern 140 , thereby improving the separation between the second electrode pattern 140 and the plurality of first electrode patterns 130 .
  • the consistency and stability of the formed multiple compensation capacitors further improves the signal transmission effect of the signal line 120 electrically connected to the first electrode pattern 130 .
  • the continuously arranged second electrode patterns 140 also help to simplify the manufacturing process of the display substrate 10 and reduce the manufacturing cost of the display substrate 10 , thereby facilitating mass production and application of the display substrate 10 .
  • the second electrode patterns 140 may be continuously arranged along the edge of the display area 101 and in a stepped shape, that is, the electrodes at the upper and lower steps adjacent to each other The patterns are connected to each other to form a whole second electrode pattern 140 , thereby reducing the voltage drop when the first voltage signal is transmitted through the second electrode pattern 140 , thereby further improving the brightness uniformity and consistency of the display image.
  • the plurality of pixel units 110 includes a first column of pixel units 111 and a second column of pixel units 112 , and the number of pixel units 110 in the first column of pixel units 111 is less than that in the second column of pixel units 112
  • the number of pixel units 110 is equal to the number of pixel units 110
  • the signal line 120 electrically connected to the pixel unit 111 of the first column is electrically connected to a first electrode pattern 130 , so that the compensation formed between the first electrode pattern 130 and the second electrode pattern 140 is compensated.
  • the capacitor compensates the transmission load of the signal line 120 electrically connected to the pixel unit 111 in the first column, and enhances the signal transmission effect on the signal line 120, so that the signal transmission effect on the signal line 120 is the same as that of other signal lines 120 (for example, The signal transmission effect of the signal line 120 electrically connected to the pixel unit 112 of the second column is basically the same.
  • the signal line 120 that is electrically connected to the pixel unit 112 in the second column may also be electrically connected to another first electrode pattern 130
  • the second electrode pattern 140 is electrically connected to the signal line 120 that is electrically connected to the pixel unit 111 of the first column.
  • the compensation capacitance formed by one first electrode pattern 130 is larger than that formed by the second electrode pattern 140 and another first electrode pattern 130 electrically connected to the signal line 120 electrically connected to the pixel unit 112 of the second column.
  • the plurality of pixel units 110 further include a third column of pixel units 113, which may be based on the transmission load of the signal line 120 electrically connected to the third column of pixel units 113 and the first column of pixel units 111 and the second column of pixels.
  • the signal line 120 electrically connected to the unit 112 provides load compensation, so that the compensated load of the signal line 120 electrically connected to the pixel unit 111 of the first column and the pixel unit 112 of the second column is electrically connected to the pixel unit 113 of the third column.
  • the loads of the signal lines 120 in the display substrate 10 are basically the same, so that the loads of the signal lines 120 in the display substrate 10 that are electrically connected to the pixel units 110 in each column are basically the same, thereby improving the signal transmission effect of the signal lines 120 in the display area 101 consistency, and improve the display effect of the display screen.
  • the lengths of the first electrode patterns 130 and the second electrode patterns 140 in the column direction may be different, or the lengths of the first electrode patterns 130 and the second electrode patterns 140 in the row direction may be different.
  • the lengths of the pattern 130 and the second electrode pattern 140 in the column direction or the row direction to provide different load compensations. For example, taking the example of providing data signals to each column of pixel units 110 in the display area 101 through the signal lines 120, for a column that includes a small number of pixel units 110, it is necessary to connect the signal lines electrically connected to the pixel units 110 in the column.
  • the first electrode patterns 130 and the second electrode patterns 140 need to have larger lengths in the column or row direction, that is, the smaller the number of pixel units 110 included in one column,
  • the signal line 120 electrically connected to the pixel unit 110 of the column needs to be provided with a larger amount of load compensation. Therefore, the first electrode patterns 130 and the second electrode patterns 140 can be flexibly arranged in the peripheral area 102 , thereby further optimizing the layout structure in the peripheral area 102 of the display substrate 10 .
  • the first end or the second end of the signal line 120 may be electrically connected to one of the first electrode patterns 130 as shown in FIG. 2A or FIG. 2B , or the first end of the signal line 120 may be connected to a first electrode pattern 130 as shown in FIG. 2C .
  • the first electrode pattern 130 is electrically connected and the second end is electrically connected to another first electrode pattern 130 , that is, both ends of the signal line 120 are electrically connected to the two first electrode patterns 130 respectively, so as to improve the load compensation amount.
  • the embodiments of the present disclosure do not limit this.
  • the extension direction of at least part of the edge of the display area 101 of the display substrate 10 intersects with the extension direction of the signal line 120 and is not perpendicular, for example, it may be determined according to the actual needs of the user for the shape of the display substrate 10 . Designs are made to provide display substrates 10 with different shapes or profiles, not just a single square display substrate with right angles.
  • the display substrate provided by the embodiment of the present disclosure such as the display substrate 10 or the display substrate 20, may be an organic light emitting diode display substrate.
  • the display substrate provided by the embodiments of the present disclosure may also be a quantum dot light-emitting diode display substrate, an electronic paper display substrate, or other substrates with display functions, or other types of display substrates, which are not limited by the embodiments of the present disclosure.
  • FIG. 7 is an equivalent circuit diagram of a pixel driving circuit in a display substrate provided by some embodiments of the present disclosure
  • FIGS. 8A-8E are schematic diagrams of various layers of a pixel driving circuit in a display substrate provided by some embodiments of the present disclosure
  • the storage capacitor 170 shown in FIG. 6 may be the storage capacitor Cst in the pixel driving circuit 7120 shown in FIGS. 7 and 8A
  • the thin film transistor 160 shown in FIG. 6 may be the storage capacitor Cst shown in FIGS. 7 and 8A .
  • the specific structure of the pixel driving circuit 7120 shown in FIG. 7 and FIG. 8A is only an exemplary illustration, and embodiments of the present disclosure include but are not limited to this.
  • the pixel driving circuit 7120 includes a plurality of thin film transistors T1, T2, T3, T4, T5, T6 and T7, connected to the plurality of thin film transistors T1, T2, T3, T4, T5 , a plurality of signal lines of T6 and T7 (for example, including the signal line 120 in the above-mentioned embodiment) and the storage capacitor Cst, and the plurality of signal lines include a gate line GL, a light emission control line EM, an initialization line RL, a data line DL and a first The power supply line VDD (eg, the first power supply line 183 in the above embodiment).
  • VDD eg, the first power supply line 183 in the above embodiment
  • the gate lines GL may include a first gate line GLn and a second gate line GLn-1.
  • the first gate line GLn may be used for transmitting gate scan signals
  • the second gate line GLn-1 may be used for transmitting reset signals.
  • the lighting control line EM may be used to transmit lighting control signals.
  • the pixel driving circuit 7120 is a 7T1C pixel driving circuit.
  • the data line DL electrically connected to the first electrode pattern 130 is paired with the compensation capacitor Ccp formed between the first electrode pattern 130 and the second electrode pattern 140 The transmission load is compensated, thereby improving the compensation effect of the data signal transmitted on the data line DL.
  • the first power supply line VDD can be directly electrically connected to the power supply wiring pattern 182 in the above embodiment to receive the first voltage signal provided by the first voltage source 181, or can be electrically connected to the second wiring pattern in the above embodiment
  • the 140 is electrically connected to the power trace pattern 182 .
  • the embodiments of the present disclosure include but are not limited thereto, and the pixel driving circuit 7120 may also adopt other types of circuit structures, such as a 7T2C structure or a 9T2C structure, which are not limited by the embodiments of the present disclosure.
  • the first gate G1 of the first thin film transistor T1 is electrically connected to the third drain electrode D3 of the third thin film transistor T3 and the fourth drain electrode D4 of the fourth thin film transistor T4 .
  • the first source S1 of the first thin film transistor T1 is electrically connected to the second drain D2 of the second thin film transistor T2 and the fifth drain D5 of the fifth thin film transistor T5.
  • the first drain electrode D1 of the first thin film transistor T1 is electrically connected to the third source electrode S3 of the third thin film transistor T3 and the sixth source electrode S6 of the sixth thin film transistor T6.
  • the second gate G2 of the second thin film transistor T2 is configured to be electrically connected to the first gate line GLn to receive the gate scan signal
  • the second source S2 of the second thin film transistor T2 is configured
  • the second drain electrode D2 of the second thin film transistor T2 is electrically connected to the first source electrode S1 of the first thin film transistor T1.
  • the third gate G3 of the third thin film transistor T3 is configured to be electrically connected to the first gate line GLn, and the third source S3 of the third thin film transistor T3 is connected to the first gate line GLn of the third thin film transistor T1.
  • a drain electrode D1 is electrically connected, and the third drain electrode D3 of the third thin film transistor T3 is electrically connected to the first gate G1 of the first thin film transistor T1.
  • the fourth gate G4 of the fourth thin film transistor T4 is configured to be electrically connected to the second gate line GLn-1 to receive the reset signal, and the fourth source S4 of the fourth thin film transistor T4 is configured In order to be electrically connected to the initialization line RL to receive the initialization signal, the fourth drain electrode D4 of the fourth thin film transistor T4 is electrically connected to the first gate electrode G1 of the first thin film transistor T1.
  • the fifth gate G5 of the fifth thin film transistor T5 is configured to be electrically connected to the light emission control line EM to receive the light emission control signal
  • the fifth source S5 of the fifth thin film transistor T5 is configured to be connected to the light emission control line EM.
  • the first power line VDD is electrically connected to receive the first power signal
  • the fifth drain D5 of the fifth thin film transistor T5 is electrically connected to the first source S1 of the first thin film transistor T1.
  • the sixth gate G6 of the sixth thin film transistor T6 is configured to be electrically connected to the light emitting control line EM to receive the light emitting control signal, and the sixth source S6 of the sixth thin film transistor T6 is connected to the first thin film
  • the first drain D1 of the transistor T1 is electrically connected
  • the sixth drain D6 of the sixth thin film transistor T6 is electrically connected to the first display electrode (eg, the anode) of the light-emitting element.
  • the seventh gate G7 of the seventh thin film transistor T7 is configured to be electrically connected to the second gate line GLn-1 to receive the reset signal, and the seventh source S7 of the seventh thin film transistor T7 is connected to the light-emitting
  • the first display electrode (eg, anode) of the element is electrically connected
  • the seventh drain D7 of the seventh thin film transistor T7 is configured to be electrically connected to the initialization line RL to receive the initialization signal.
  • the seventh drain electrode D7 of the seventh thin film transistor T7 may be electrically connected to the initialization line RL by being connected to the fourth source electrode S4 of the fourth thin film transistor T4.
  • the storage capacitor Cst includes a first capacitor electrode CE1 and a second capacitor electrode CE2 (eg, the first capacitor electrode 171 and the second capacitor electrode 172 in the above embodiment).
  • the second capacitor electrode CE2 is electrically connected to the first power line VDD
  • the first capacitor electrode CE1 is electrically connected to the first gate G1 of the first thin film transistor T1 and the third drain D3 of the third thin film transistor T3.
  • the second display electrode (eg, the cathode) of the light-emitting element is electrically connected to the second power supply line VSS.
  • one of the first power supply line VDD and the second power supply line VSS is a power supply line for providing a high voltage
  • the other is a power supply line for providing a low voltage
  • the first power supply line VDD eg, the above-mentioned first power supply line 183 electrically connected to the first voltage source 181
  • the first voltage is a positive voltage
  • the second power line VSS provides a constant second voltage
  • the second voltage may be a negative voltage and so on.
  • the second voltage may be a ground voltage.
  • the above-mentioned reset signal and the above-mentioned initialization signal may be the same signal.
  • transistors can be divided into N-type transistors and P-type transistors.
  • the embodiments of the present disclosure take a P-type transistor (for example, a P-type MOS transistor) as an example for description. That is, in the description of the present disclosure, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, etc. may all be P type transistor.
  • the transistors in the embodiments of the present disclosure are not limited to P-type transistors, and those skilled in the art can also use N-type transistors (eg, N-type MOS transistors) to implement the functions of one or more transistors in the embodiments of the present disclosure according to actual needs. .
  • N-type transistors eg, N-type MOS transistors
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors, etc. .
  • the source and drain of the transistor may be symmetrical in structure, so the source and drain of the transistor may be indistinguishable in terms of physical structure.
  • the source and drain of all or part of the transistors are as required. are interchangeable.
  • FIG. 8A is a schematic diagram of the stacked positional relationship of the semiconductor layer, the first conductive layer, the second conductive layer and the third conductive layer of the pixel driving circuit 7120 .
  • FIG. 8B shows the semiconductor layers of the pixel driving circuit 7120.
  • the semiconductor layer may be formed by patterning a semiconductor material.
  • the semiconductor layer can be used to make the above-mentioned first thin film transistor T1, second thin film transistor T2, third thin film transistor T3, fourth thin film transistor T4, fifth thin film transistor T5, sixth thin film transistor T6 and seventh thin film transistor T7.
  • source layers, each active layer may include a source region, a drain region, and a channel region between the source and drain regions.
  • the semiconductor layer can be made of amorphous silicon, polysilicon, oxide semiconductor materials and the like. It should be noted that, the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the active layer 161 and the spacer patterns 190 in the above-described embodiments may be located in the above-described semiconductor layers.
  • a gate insulating layer (eg, the second insulating layer 1102 in the above embodiment, not shown in FIGS. 8A-8E ) is formed on the above-mentioned semiconductor layer for protection the above-mentioned semiconductor layer.
  • FIG. 8C shows the first conductive layer of the pixel driving circuit 7120.
  • the first conductive layer of the pixel driving circuit 7120 is disposed on the gate insulating layer so as to be insulated from the semiconductor layer shown in FIG. 8B.
  • the first conductive layer may include a first capacitor electrode CE1 of the storage capacitor Cst, a first gate line GLn, a second gate line GLn-1, a light emission control line EM, and a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T1, and a third thin film transistor T1.
  • the gates of the thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6 and the seventh thin film transistor T7 are the first gate line GLn, the second gate line GLn- 1.
  • the third thin film transistor T3 can be a thin film transistor with a double gate structure, and one gate of the third thin film transistor T3 can be the part overlapping the first gate line GLn and the semiconductor layer, the third thin film transistor T3
  • the other gate of the transistor T3 may be a protrusion protruding from the first gate line GLn; the gate of the first thin film transistor T1 may be the first capacitor electrode CE1.
  • the fourth thin film transistor T4 may be a thin film transistor with a double gate structure, and the two gates are respectively the overlapping portions of the second gate line GLn-1 and the semiconductor layer.
  • the first electrode pattern 130 , the gate electrode 162 and the first capacitive electrode 171 in the above-mentioned embodiment may be located in the above-mentioned first conductive layer.
  • a first interlayer insulating layer (eg, the first insulating layer 1101 in the above embodiment, not shown in FIGS. 8A-8E ) is formed on the above-mentioned first conductive layer. , used to protect the above-mentioned first conductive layer.
  • FIG. 8D shows the second conductive layer of the pixel driver circuit 7120.
  • the second conductive layer of the pixel driving circuit 7120 includes the second capacitor electrode CE2 of the storage capacitor Cst and the initialization line RL.
  • the second capacitor electrode CE2 and the first capacitor electrode CE1 at least partially overlap to form the storage capacitor Cst.
  • the second electrode pattern 140 and the second capacitive electrode 172 in the above-mentioned embodiment may be located in the above-mentioned second conductive layer.
  • the second conductive layer may further include a first light shielding portion 791 and a second light shielding portion 792 .
  • the orthographic projection of the first light shielding portion 791 on the base substrate 710 covers the active layer of the second thin film transistor T2, the active layer between the drain electrode of the third thin film transistor T3 and the drain electrode of the fourth thin film transistor T4, thereby The active layers of the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4 are prevented from being affected by external light.
  • the orthographic projection of the second light shielding portion 792 on the base substrate 710 covers the active layer between the two gates of the third thin film transistor T3, thereby preventing external light from affecting the active layer of the third thin film transistor T3.
  • the first light shielding portion 791 can be integrally formed with the second light shielding portion 792 of the adjacent pixel driving circuit, and is electrically connected to the first power line VDD through a via hole penetrating the second interlayer insulating layer.
  • a second interlayer insulating layer (eg, the third insulating layer 1103 in the above embodiment, not shown in FIGS. 8A-8E ) is formed on the above-mentioned second conductive layer. , used to protect the above-mentioned second conductive layer.
  • FIG. 8E shows the third conductive layer of the pixel driver circuit 7120.
  • the third conductive layer of the pixel driving circuit 7120 includes a data line DL (such as the signal line 120 in the above embodiment) and a first power supply line VDD (such as the first power supply line 183 in the above embodiment) ).
  • the data line DL passes through at least one via hole in the gate insulating layer, the first interlayer insulating layer and the second interlayer insulating layer and the source electrode of the second thin film transistor T2 in the semiconductor layer. Regions are connected.
  • the first power supply line VDD is connected to the source region of the semiconductor layer corresponding to the fifth thin film transistor T5 through at least one via hole in the gate insulating layer, the first interlayer insulating layer and the second interlayer insulating layer.
  • the first power supply line VDD is connected to the second capacitor electrode CE2 in the second conductive layer through at least one via hole in the second interlayer insulating layer.
  • the power supply wiring pattern 182, the signal line 120, the first power supply line 183, the source electrode 163 and the drain electrode 164 in the above-mentioned embodiment may be located in the above-mentioned third conductive layer.
  • the third conductive layer further includes a first connection part CP1, a second connection part CP2 and a third connection part CP3.
  • One end of the first connection part CP1 is connected to the drain region corresponding to the third thin film transistor T3 in the semiconductor layer through at least one via hole in the gate insulating layer, the first interlayer insulating layer and the second interlayer insulating layer.
  • the other end of the connection part CP1 is connected to the gate of the first thin film transistor T1 in the first conductive layer through at least one via hole in the first interlayer insulating layer and the second interlayer insulating layer.
  • connection part CP2 One end of the second connection part CP2 is connected to the initialization line RL through a via hole in the second interlayer insulating layer, and the other end of the second connection part CP2 is connected to the gate insulating layer, the first interlayer insulating layer and the second interlayer At least one via hole in the insulating layer is connected to the source region of the seventh thin film transistor T7 and the source region of the fourth thin film transistor T4 in the semiconductor layer.
  • the third connection part CP3 is connected to the drain region of the sixth thin film transistor T6 in the semiconductor layer through at least one via hole in the gate insulating layer, the first interlayer insulating layer and the second interlayer insulating layer.
  • a protective layer (not shown in FIGS. 8A-8E ) is formed on the above-mentioned third conductive layer to protect the above-mentioned third conductive layer.
  • the first display electrode e.g., the anode
  • the protective layer may be provided on the protective layer.
  • At least one embodiment of the present disclosure further provides a display device including the display substrate described in any embodiment of the present disclosure.
  • FIG. 9 is a schematic block diagram of a display device according to some embodiments of the present disclosure.
  • the display device 40 includes a display substrate 401 , and the display substrate 401 may be the display substrate provided in any embodiment of the present disclosure, for example, the display substrate 10 or the display substrate 20 described above.
  • FIG. 10 is a schematic block diagram of another display device provided by some embodiments of the present disclosure.
  • the display device 50 includes a display substrate 501 .
  • the display substrate 501 may be the display substrate provided in any embodiment of the present disclosure, for example, the display substrate 10 or the display substrate 20 described above.
  • the display device 50 further includes a data driver 510, a gate driver 520, a timing controller 530, a voltage source 540, and the like.
  • the gate driver 520 may include the gate scan driving circuit 150 in the above-mentioned embodiment of the display substrate 10, that is, it may be directly fabricated on the base substrate through a semiconductor process;
  • the voltage source 540 may include the above-mentioned embodiment of the display substrate 10
  • the first voltage source 181 in in , for example, can be implemented as a power management circuit.
  • a plurality of pixel units P (such as the pixel units 110 in the above-mentioned embodiment with respect to the display substrate 10 ) are arranged in an array in the display area of the display substrate 501 , and each pixel unit P receives data through the data line DL.
  • the data signal provided by the data driver 510 and the voltage signal provided by the voltage source 540 are received through the power line VDD.
  • the data line DL may include, for example, the signal line 120 in the above-mentioned embodiment about the display substrate 10 .
  • the power supply line VDD may include, for example, the first power supply line 183 in the above-described embodiment with respect to the display substrate 10 .
  • the data driver 510 converts the digital image data RGB input from the timing controller 530 into data signals according to the data control signal DCS provided from the timing controller 530 .
  • the data driver 510 converts the data signal into an analog voltage signal according to the data control signal DCS provided by the timing controller 530, performs processing such as operational amplification on the analog voltage signal, and then provides corresponding signals to each pixel unit P through the data line DL. data signal.
  • the data driver 510 may be implemented as a semiconductor chip.
  • the gate driver 520 is electrically connected to each pixel unit P through the scan line SL, so as to provide each pixel unit P with scan signals, respectively.
  • the gate driver 520 provides a gating signal according to a plurality of scan control signals GCS provided by the timing controller 530 .
  • the gate driver 520 may be implemented as a semiconductor chip, and may also be integrated in the display device 50 to form a GOA circuit, such as the gate scan driving circuit 150 in the above-described embodiments of the display substrate 10 .
  • the timing controller 530 is used to process the image data RGB input from the outside of the display device 50 , supply the processed image data RGB to the data driver 510 , and supply the data driver 510 and the gate driver 520 with the data control signal DCS and the scan control signal GCS , to control the data driver 510 and the gate driver 520 .
  • the timing controller 530 processes externally inputted image data RGB to match the size and resolution of the display device 50, and then provides the processed image data RGB to the data driver 510.
  • the timing controller 530 generates scan control signals GCS and data control signals DCS using synchronization signals SYNC (eg, dot clock DCLK, data enable signal DE, horizontal synchronization signal Hsync, and vertical synchronization signal Vsync) input from outside the display device 50 .
  • SYNC eg, dot clock DCLK, data enable signal DE, horizontal synchronization signal Hsync, and vertical synchronization signal Vsync
  • the timing controller 530 provides the generated data control signal DCS and scan control signal GCS to the data driver 510 and the gate driver 520, respectively, for the control of the data driver 510 and the gate driver 520.
  • the display device 40 and the display device 50 provided by the embodiments of the present disclosure may be organic light emitting diode display devices.
  • the display device 40 and the display device 50 provided in the embodiments of the present disclosure may also be devices with display functions such as quantum dot light-emitting diode display devices, electronic paper display devices, or other types of display devices, which are not made in the embodiments of the present disclosure. limit.
  • the display device 40 and the display device 50 provided by the embodiment of the present disclosure may be any display device with display function, such as a display substrate, a display panel, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator. products or components, which are not limited by the embodiments of the present disclosure.

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Abstract

一种显示基板及显示装置，该显示基板(10)具有显示区域(101)和至少部分围绕显示区域(101)的周边区域(102)，且包括衬底基板(100)；显示区域(101)包括阵列排布在衬底基板(100)上的多个像素单元(110)以及分别与多个像素单元(110)电连接的多条信号线(120)；周边区域(102)包括与多条信号线(120)中的至少一条电连接的至少一个第一电极图案(130)，以及包括第二电极图案(140)，至少一个第一电极图案(130)与第二电极图案(140)在垂直于衬底基板(100)的板面的方向上至少部分交叠且间隔绝缘设置；周边区域(102)还包括栅扫描驱动电路(150)，栅扫描驱动电路(150)配置为向多个像素单元(110)提供栅极扫描信号，在平行于衬底基板(100)的板面的方向上，至少一个第一电极图案(130)和第二电极图案(140)位于栅扫描驱动电路(150)和显示区域(101)之间。该显示基板可以补偿信号线的传输负载，从而改善信号传输效果。

Description

显示基板及显示装置
本申请要求于2020年6月30日递交的中国专利申请第202010621917.9号的优先权，该中国专利申请的全文以引入的方式并入以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示基板及显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)显示装置具有厚度薄、重量轻、宽视角、主动发光、发光颜色连续可调、成本低、响应速度快、能耗小、驱动电压低、工作温度范围宽、生产工艺简单、发光效率高及可柔性显示等优点，因此被越来越广泛地应用于手机、平板电脑、数码相机等显示领域。
发明内容
本公开至少一个实施例提供一种显示基板，该显示基板具有显示区域和至少部分围绕所述显示区域的周边区域，且包括：衬底基板；其中，所述显示区域包括阵列排布在所述衬底基板上的多个像素单元以及分别与所述多个像素单元电连接的多条信号线，所述周边区域包括与所述多条信号线中的至少一条电连接的至少一个第一电极图案，以及包括第二电极图案，所述至少一个第一电极图案与所述第二电极图案在垂直于所述衬底基板的板面的方向上至少部分交叠且间隔绝缘设置，所述周边区域还包括栅扫描驱动电路，所述栅扫描驱动电路配置为向所述多个像素单元提供栅极扫描信号，在平行于所述衬底基板的板面的方向上，所述至少一个第一电极图案和所述第二电极图案位于所述栅扫描驱动电路和所述显示区域之间。
例如，在本公开至少一个实施例提供的显示基板中，所述至少一个第一电极图案在所述衬底基板上的正投影位于所述第二电极图案在所述衬底基板上的正投影内。
例如，在本公开至少一个实施例提供的显示基板中，所述第二电极图案位于所述至少一个第一电极图案的远离所述衬底基板的一侧。
例如，在本公开至少一个实施例提供的显示基板中，所述多个像素单元中的至少一个包括位于所述衬底基板上的像素驱动电路，所述像素驱动电路包括薄膜晶体管和存储电容；所述薄膜晶体管包括有源层、栅极、源极和漏极，所述存储电容包括第一电容电极和与所述第一电容电极在垂直于所述衬底基板的板面的方向上相对的第二电容电极；所述源极和所述漏极位于所述有源层远离所述衬底基板的一侧，所述第一电极图案、所述栅极和所述第一电容电极同层设置，所述第二电极图案和所述第二电容电极同层设置。
例如，在本公开至少一个实施例提供的显示基板中，所述多条信号线与所述薄膜晶 体管的源极和漏极同层设置，所述至少一个第一电极图案通过过孔结构与所述多条信号线中的至少一条电连接。
例如，在本公开至少一个实施例提供的显示基板中，所述第二电极图案配置为从第一电压源接收第一电压信号。
例如，在本公开至少一个实施例提供的显示基板中，所述周边区域还包括电源走线图案，所述电源走线图案与所述第一电压源电连接，所述第二电极图案与所述电源走线图案电连接以通过所述电源走线图案接收所述第一电压信号。
例如，在本公开至少一个实施例提供的显示基板中，所述电源走线图案与所述薄膜晶体管的源极和漏极同层设置，所述第二电极图案通过过孔结构与所述电源走线图案电连接。
例如，在本公开至少一个实施例提供的显示基板中，在平行于所述衬底基板的板面的方向上，所述第二电极图案的至少部分电连接在所述电源走线图案和所述多个像素单元之间，所述电源走线图案通过所述第二电极图案向所述多个像素单元中的至少部分提供所述第一电压信号。
例如，在本公开至少一个实施例提供的显示基板中，所述至少一个第一电极图案包括多个第一电极图案，所述多个第一电极图案间隔设置；所述周边区域还包括位于相邻的两个第一电极图案之间且与所述第一电极图案彼此绝缘的间隔图案。
例如，在本公开至少一个实施例提供的显示基板中，所述间隔图案配置为从不同于所述第一电压源的第二电压源接收第二电压信号。
例如，在本公开至少一个实施例提供的显示基板中，所述间隔图案与所述第二电极图案电连接，以从所述第一电压源接收所述第一电压信号。
例如，在本公开至少一个实施例提供的显示基板中，所述间隔图案与所述薄膜晶体管的有源层同层设置。
例如，在本公开至少一个实施例提供的显示基板中，所述第二电极图案沿所述显示区域的边缘连续设置，且在垂直于所述衬底基板的板面的方向上分别与所述多个第一电极图案至少部分交叠且间隔绝缘设置。
例如，在本公开至少一个实施例提供的显示基板中，所述显示区域的至少部分边缘的延伸方向与所述多条信号线的延伸方向相交叉且不垂直。
例如，在本公开至少一个实施例提供的显示基板中，所述显示基板还包括位于所述第一电极图案和所述第二电极图案之间的第一绝缘层，所述第一绝缘层的材料包括氮化硅或氮氧化硅。
例如，在本公开至少一个实施例提供的显示基板中，所述多个像素单元包括第一列像素单元和第二列像素单元，所述第一列像素单元中的像素单元的数量少于所述第二列像素单元中的像素单元的数量，与所述第一列像素单元电连接的信号线与一个第一电极图案电连接。
例如，在本公开至少一个实施例提供的显示基板中，与所述第二列像素单元电连接 的信号线与另一个第一电极图案电连接，所述第二电极图案和与所述第一列像素单元电连接的信号线电连接的所述一个第一电极图案形成的补偿电容量大于所述第二电极图案和与所述第二列像素单元电连接的信号线电连接的所述另一个第一电极图案形成的补偿电容量。
例如，在本公开至少一个实施例提供的显示基板中，所述第一电极图案和所述第二电极图案在列方向上的长度不同，或所述第一电极图案和所述第二电极图案在行方向上的长度不同。
例如，在本公开至少一个实施例提供的显示基板中，所述多条信号线为扫描线或者数据线。
例如，在本公开至少一个实施例提供的显示基板中，所述多条信号线中的至少一条的第一端或第二端与一个第一电极图案电连接，或所述多条信号线中的至少一条的第一端与一个第一电极图案电连接，所述多条信号线中的至少一条的第二端与另一个第一电极图案电连接。
本公开至少一个实施例还提供一种显示装置，包括本公开任一实施例所述的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为本公开一些实施例提供的一种显示基板的平面示意图；
图1B为本公开一些实施例提供的另一种显示基板的平面示意图；
图2A为本公开一些实施例提供的一种图1A所示的显示基板的补偿方式的示意图；
图2B为本公开一些实施例提供的另一种图1A所示的显示基板的补偿方式的示意图；
图2C为本公开一些实施例提供的再一种图1A所示的显示基板的补偿方式的示意图；
图3为本公开一些实施例提供的一种显示基板的部分结构的示意图；
图4为本公开一些实施例提供的一种显示基板的周边区域的部分平面结构的示意图；
图5A为本公开一些实施例提供的一种显示基板的周边区域的部分截面结构的示意图；
图5B为本公开一些实施例提供的另一种显示基板的周边区域的部分截面结构的示意图；
图6为本公开一些实施例提供的一种显示基板的显示区域的部分截面结构和周边区域的部分截面结构的示意图；
图7为本公开一些实施例提供的一种显示基板中的像素驱动电路的等效电路图；
图8A-8E为本公开一些实施例提供的一种显示基板中的像素驱动电路的各层的示意 图；
图9为本公开一些实施例提供的一种显示装置的示意框图；以及
图10为本公开一些实施例提供的另一种显示装置的示意框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
目前，随着电子显示产品的不断普及，用户对电子显示产品的功能、外观的要求进一步提高。为了满足用户的不同实际需求，电子显示产品的外观或显示区域有时会需要被设计为不规则或特殊的形状。但是，由于显示区域具有不规则或特殊的形状，显示区域中不同行所包括的像素单元的个数可能不同，或者显示区域中不同列所包括的像素单元的个数也可能不同。例如，以显示区域中不同列所包括的像素单元的个数不同为例，由于不同列中像素单元的个数不同，用于向位于不同列中的像素单元提供例如数据信号或其他所需的电信号的多条信号线上的传输负载可能不同，从而导致多条信号线的信号传输效果(例如传输速度)不一致，进而导致提供的显示画面的亮度均匀性和一致性降低，甚至还可能会出现显示异常现象。
本公开至少一个实施例提供一种显示基板，该显示基板具有显示区域和至少部分围绕显示区域的周边区域，且包括衬底基板。显示区域包括阵列排布在衬底基板上的多个像素单元以及分别与多个像素单元电连接的多条信号线；周边区域包括与多条信号线中的至少一条电连接的至少一个第一电极图案，以及包括第二电极图案，该至少一个第一电极图案与第二电极图案在垂直于衬底基板的板面的方向上至少部分交叠且间隔绝缘设置；周边区域还包括栅扫描驱动电路，栅扫描驱动电路配置为向多个像素单元提供栅极扫描信号，在平行于衬底基板的板面的方向上，至少一个第一电极图案和第二电极图案位于栅扫描驱动电路和显示区域之间。
本公开上述实施例提供的显示基板通过使第一电极图案和第二电极图案在垂直于衬底基板的板面的方向上至少部分交叠且彼此间隔绝缘设置，使第一电极图案和第二电极图案之间可以形成电容，从而对与第一电极图案电连接的信号线上的传输负载进行补偿，以提升多条信号线的信号传输效果的一致性，由此使显示画面的亮度均匀性和一致性提升，从而减弱或避免显示画面出现显示异常或不良现象，改善画面的显示效果。
下面，将参考附图详细地说明本公开的一些实施例。应当注意的是，不同的附图中相同的附图标记将用于指代已描述的相同的元件。
图1A为本公开一些实施例提供的一种显示基板的平面示意图。如图1A所示，该显示基板10具有显示区域101和至少部分围绕(例如完全围绕)显示区域101的周边区域102。例如，显示基板10的显示区域101的形状可以为圆形，周边区域102围绕显示区域101且具有近似于圆形的轮廓，由此使显示基板10具有大致圆形的形状，以满足用户对不同形状的显示基板的实际需求。
需要说明的是，本公开实施例对显示基板的具体形状不作限制。例如，图1B为本公开一些实施例提供的另一种显示基板的平面示意图。如图1B所示，该显示基板20具有显示区域201和至少部分围绕(例如完全围绕)显示区域201的周边区域202。例如，显示基板20的显示区域201的形状可以为具有圆角的方形，周边区域202围绕显示区域201且具有与显示区域201相同的轮廓，由此使显示基板20呈具有圆角的方形。在本公开的其他一些实施例中，显示基板还可以为椭圆形、扇形、三角形、菱形、五边形等规则形状，或者也可以为其他适合的不规则形状，本公开的实施例对此不作限制。
下面，本公开的实施例以图1A所示的显示基板10的形状为例，对本公开实施例提供的显示基板进行说明，但这并不构成对本公开实施例的限制。
图2A为本公开一些实施例提供的一种图1A所示的显示基板的补偿方式的示意图；图3为本公开一些实施例提供的一种显示基板的部分结构的示意图，例如图3可以对应图2A中所示的区域REG1。
例如，如图1A、图2A和图3所示，显示基板10包括衬底基板100。显示区域101包括阵列排布在衬底基板100上的多个像素单元110以及分别与多个像素单元110电连接的多条信号线120。周边区域102包括与多条信号线120中的至少一条电连接的至少一个第一电极图案130，以及包括第二电极图案140。第一电极图案130与第二电极图案140在垂直于衬底基板100的板面的方向上至少部分交叠且间隔绝缘设置以形成电容，由此可以通过第一电极图案130与第二电极图案140之间形成的电容，对与第一电极图案130电连接的信号线120上的传输负载(例如，信号线120上的传输负载可以是指信号线120的传输电阻，或信号线120与其他走线之间形成的电容)进行补偿，以提升显示区域101中的多条信号线120上的传输负载的一致性。由此，可以改善显示区域101中的多条信号线120的信号传输效果，使提供的显示画面的亮度均匀性和一致性提升，由此减弱或避免显示画面出现显示异常或不良现象，改善画面的显示效果。
在本公开的一些实施例中，信号线120可以为扫描线，例如用于向像素单元110提 供栅极扫描信号，或者也可以为数据线，例如用于向像素单元110提供数据信号，或者也可以为用于向像素单元110提供实现画面显示所需的其他电信号的信号线。
例如，在信号线120为扫描线的情形，通过第一电极图案130和第二电极图案140之间形成的电容对与第一电极图案130电连接的扫描线上的传输负载进行补偿，从而改善扫描线上传输的例如栅极扫描信号的传输效果，提升显示区域101中多条扫描线上的栅极扫描信号的传输效果的一致性。
例如，在信号线120为数据线的情形，通过第一电极图案130和第二电极图案140之间形成的电容对与第一电极图案130电连接的数据线上的传输负载进行补偿，从而改善数据线上传输的例如数据信号的传输效果，提升显示区域101中多条数据线上的数据信号的传输效果的一致性。
本公开的如下实施例以信号线120为数据线为例进行说明，但需要说明的是，本公开的实施例包括但并不仅限于此。
例如，如图1A、图2A和图3所示，周边区域102还包括栅扫描驱动电路(Gate on array,GOA)150，栅扫描驱动电路150配置为向多个像素单元110提供栅极扫描信号，例如通过半导体工艺直接制备在衬底基板100上。在平行于衬底基板100的板面的方向上，第一电极图案130和第二电极图案140位于栅扫描驱动电路150和显示区域101之间，由此可以提升周边区域102的空间利用率，减小第一电极图案130和第二电极图案140在显示基板10中所需占据的空间，从而有利于显示基板10实现窄边框设计。
例如，栅扫描驱动电路150可以包括多个级联的移位寄存器单元，例如每个移位寄存器单元的输出端通过栅线与显示区域101中的一行像素单元110电连接，以用于为一行中的多个像素单元110提供栅极扫描信号。例如，多个像素单元110可以在显示区域101中阵列排布，栅扫描驱动电路150用于向显示区域101中阵列排布的多行像素单元110提供例如逐行移位的栅极扫描信号。
例如，上述栅扫描驱动电路150中的移位寄存器单元可以为4T1C结构，即至少包括四个晶体管和一个电容，以分别实现信号输入、信号输出、寄存器复位等功能，或者也可以包括更多的晶体管和/或电容，例如加入用于实现上拉节点控制、下拉节点控制、降噪等功能的子电路等，以实现更稳定地输入、输出以及复位，本公开的实施例对此不作限制。
例如，在信号线120为数据线的情形，第一电极图案130可以电连接在对应的数据线与数据驱动电路之间，数据驱动电路用于向显示区域101中的多列像素单元110分别提供相应的数据信号，由此通过信号线120和第一电极图案130实现数据信号的传输；例如，第一电极图案130还至少部分地起到了传输数据信号的作用。例如，数据驱动电路可以使用参考伽玛电压根据源自定时控制器的多个数据控制信号将从定时控制器输入的数字图像数据转换成数据信号。例如，数据驱动电路可以实现为半导体芯片，然后安装在柔性印刷电路板上并通过绑定方式耦接到显示基板上的数据线。
图4为本公开一些实施例提供的一种显示基板的周边区域的部分平面结构的示意图， 例如图4对应图3中所示的区域REG2。图5A为本公开一些实施例提供的一种显示基板的周边区域的部分截面结构的示意图，例如图5A可以为显示基板10沿图3中所示的A-A’线的部分截面结构的示意图。图5B为本公开一些实施例提供的另一种显示基板的周边区域的部分截面结构的示意图，例如图5B可以为显示基板10沿图3中所示的B-B’线的部分截面结构的示意图。
例如，结合图3-图5B所示，第一电极图案130在衬底基板100上的正投影位于第二电极图案140在衬底基板100上的正投影内，也即，在垂直于衬底基板100的板面的方向R1上，第二电极图案140完全覆盖第一电极图案130，由此通过提高第一电极图案130和第二电极图案140在垂直于衬底基板100的板面的方向R1上的交叠面积，提高第一电极图案130与第二电极图案140之间形成的补偿电容的电容量，使第一电极图案130和第二电极图案140之间可以形成稳定的电容。由此，可以进一步提升对信号线120的传输负载的补偿效果，进而提升显示区域101中多条信号线120的信号传输效果的稳定性和一致性。
需要说明的是，在本公开的一些实施例中，为了改善第一电极图案130与信号线120之间的电连接效果，还可以在第一电极图案130与信号线120之间设置用于实现二者电连接的连接件。例如，该连接件可以与第一电极图案130或信号线120位于同一层，也可以位于不同于第一电极图案130且不同于信号线120的一层中，本公开的实施例对此不作限制。
例如，在图3所示的一些实施例中，第一电极图案130呈直线型延伸且呈长条状；而在本公开的其他一些实施例中，第一电极图案130也可以呈曲线型、折线型或其他适合的轮廓延伸，并且第一电极图案130的形状也可以根据实际需要采用例如椭圆形、方形、锯齿形或其他适合的规则形状或不规则形状，本公开的实施例对此不作限制。
例如，结合图3-图5B所示，第二电极图案140位于第一电极图案130的远离衬底基板100的一侧，由此第二电极图案140可以起到电场屏蔽作用，可以减弱或避免显示基板10中位于第二电极图案140的远离衬底基板100的一侧的其他结构或器件等对第一电极图案130上传输的电信号的干扰，从而提升与第一电极图案130电连接的信号线120上传输的电信号的稳定性。
图6为本公开一些实施例提供的一种显示基板的显示区域的部分截面结构和周边区域的部分截面结构的示意图，例如图6所示的显示基板10的截面结构可以包括图5A所示的显示基板10的周边区域102的截面结构或图5B所示的显示基板10的周边区域102的部分截面结构，以及还包括显示基板10的显示区域101的部分截面结构，例如显示区域101中一个像素单元110的像素驱动电路的部分截面结构。
例如，结合图3-图6所示，多个像素单元110中的至少一个(例如每个像素单元110)包括位于衬底基板100上的像素驱动电路，像素驱动电路包括薄膜晶体管160和存储电容170。薄膜晶体管160包括有源层161、栅极162、源极163和漏极164，存储电容170包括第一电容电极171和与第一电容电极171在垂直于衬底基板100的板面的方向R1 上相对的第二电容电极172。源极163和漏极164位于有源层161远离衬底基板100的一侧。
例如，第一电极图案130、栅极162和第一电容电极171同层设置，第二电极图案140和第二电容电极172同层设置。由此，通过使第一电极图案130与栅极162和第一电容电极171在制备工艺中同层形成(例如采用同一材料层通过构图工艺形成)，使第二电极图案140与第二电容电极172在制备工艺中同层形成，可以简化显示基板10的制备工艺，降低显示基板10的制备成本，从而有利于显示基板10的大量生产及应用。
需要说明的是，在本公开的实施例中，“同层设置”为两个功能层或结构层在显示基板的层级结构中同层且同材料形成，即在制备工艺中，该两个功能层或结构层可以由同一个材料层形成，且可以通过同一构图工艺形成所需要的图案和结构，例如可以在先形成该材料层后，由该材料层经过构图工艺形成。
例如，显示基板10还包括位于第一电极图案130和第二电极图案140之间的第一绝缘层1101，第一绝缘层1101的材料可以包括例如氮化硅或氮氧化硅，或者也可以包括其他具有较高介电常数的绝缘材料。由此，通过采用较高介电常数的绝缘材料(例如氮化硅或氮氧化硅)作为第一电极图案130和第二电极图案140之间的第一绝缘层1101，可以使第一电极图案130和第二电极图案140之间形成具有较大电容量的补偿电容，从而可以减小第一电极图案130和第二电极图案140的大小。由此，可以进一步减少第一电极图案130和第二电极图案140在平行于衬底基板100的平面内所需占据的空间，有利于显示基板10实现窄边框设计。
例如，第一绝缘层1101位于第一电极图案130和第二电极图案140之间，也即，位于第一电容电极171和第二电容电极172之间，由此通过第一绝缘层1101既可以提升第一电极图案130和第二电极图案140之间形成的补偿电容的电容量，也可以提升第一电容电极171和第二电容电极172之间形成的例如存储电容的电容量，从而改善显示基板10的整体性能，提升显示基板10的稳定性。
例如，显示基板10还包括缓冲层1104、第二绝缘层1102和第三绝缘层1103。缓冲层1104位于衬底基板100上，有源层161位于缓冲层1104远离衬底基板100的一侧，第二绝缘层1102位于有源层161远离衬底基板100的一侧，第一电极图案130、栅极162和第一电容电极171位于第二绝缘层1102远离衬底基板100的一侧，第一绝缘层1101位于第一电极图案130、栅极162和第一电容电极171远离衬底基板100的一侧，第二电极图案140和第二电容电极172位于第一绝缘层1101远离衬底基板100的一侧，第三绝缘层1103位于第二电极图案140和第二电容电极172远离衬底基板100的一侧，源极163和漏极164位于第三绝缘层1103远离衬底基板100的一侧。
例如，如图6所示，多条信号线120可以与薄膜晶体管160的源极163和漏极164同层设置，第一电极图案130可以通过例如贯穿第一绝缘层1101和第三绝缘层1103的过孔结构与信号线120电连接，由此实现对信号线120的传输负载的补偿。
例如，显示基板还包括位于源极163和漏极164远离衬底基板100的一侧的保护层 (未示出)以及设置在保护层远离衬底基板100的一侧的发光元件(未示出)，源极163或漏极164通过位于保护层中的过孔与设置在保护层上的发光元件电连接。
例如，有源层161的材料可以包括多晶硅或氧化物半导体(例如，氧化铟镓锌)。栅极162的材料可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(例如钛、铝及钛三层金属叠层(Al/Ti/Al))。源极163及漏极164的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构可以为多金属层叠层(如钛、铝及钛三层金属叠层(Al/Ti/Al))。本公开的实施例对各结构或功能层的材料不作具体限定。
例如，缓冲层1104即可以防止衬底基板100中的有害物质侵入显示基板10的内部，又可以增加显示基板10中的膜层在衬底基板100上的附着力。例如，缓冲层1104的材料可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料。例如，第一绝缘层1101、第二绝缘层1102、第三绝缘层1103和保护层中的一种或多种的材料可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料。第一绝缘层1101、第二绝缘层1102、第三绝缘层1103、缓冲层1104和保护层的材料可以彼此相同，也可以彼此不相同，本公开的实施例对此不作限制。
需要说明的是，图6中示出了薄膜晶体管160为顶栅型薄膜晶体管的一种示例，而在本公开的其他一些实施例中，薄膜晶体管160也可以为底栅型薄膜晶体管或其他适合类型的薄膜晶体管，本公开的实施例对此不作限制。
需要说明的是，关于显示基板10的像素驱动电路的具体说明可以参考后文中关于图7和图8A-图8E所示的一种像素驱动电路的具体示例的内容，在此不再赘述。
在本公开的一些实施例中，如图3-图6所示，显示基板10还包括第一电压源181，第二电极图案140配置为从第一电压源181接收第一电压信号，从而使得第二电极图案140具有稳定的电压，由此可以提升第一电极图案130和第二电极图案140之间形成的补偿电容的稳定性，并且通过该第一电压信号进一步减弱或避免显示基板10的位于第二电极图案140远离衬底基板100的一侧的其他结构或器件对第一电极图案130上传输的电信号的干扰。例如，第一电压信号可以为高电平电压信号，也可以为低电平电压信号，本公开的实施例对此不作限制。
例如，如图3-图6所示，周边区域102还包括电源走线图案182。电源走线图案182与第一电压源181电连接，第二电极图案140与电源走线图案182电连接以通过电源走线图案182接收第一电压信号。由此，可以改善显示基板10的布局结构，从而有利于显示基板10实现窄边框设计，同时还可以简化显示基板10的制备工艺。
例如，在一些示例中，在平行于衬底基板100的板面的方向上，电源走线图案182可以位于第一电压源181与第二电极图案140之间，或者也可以位于第一电压源181和第二电极图案140的远离显示区域101的一侧；或者，在一些示例中，在垂直于衬底基板100的板面的方向上，电源走线图案182也可以与第二电极图案140至少部分交叠，本公开的实施例对此不作限制。
例如，电源走线图案182可以与薄膜晶体管160的源极163和漏极164同层设置， 第二电极图案140通过例如贯穿第三绝缘层1103的过孔结构与电源走线图案182电连接，由此优化显示基板10的周边区域102内的布局结构。
例如，在平行于衬底基板100的板面的方向上，第二电极图案140的至少部分(例如所有部分)电连接在电源走线图案182和多个像素单元110之间，电源走线图案182通过第二电极图案140向多个像素单元110中的至少部分提供第一电压信号。由此，在采用第二电极图案140与第一电极图案130形成补偿电容以补偿与第一电极图案130电连接的信号线120上的传输负载的同时，第二电极图案140还可以用于传输用于显示的电源电压信号(也即，第一电压信号)，从而可以进一步优化显示基板10的布局结构，有助于显示基板10实现窄边框设计，并且还可以提升显示基板10的稳定性。
例如，如图3所示，第二电极图案140可以与显示区域101中的多条第一电源线183电连接，以通过第一电源线183将第一电压源181提供的第一电压信号传输至像素单元110中。例如，第一电源线183可以与薄膜晶体管160的源极163和漏极164同层设置，第二电极图案140通过例如贯穿第三绝缘层1103的过孔结构与第一电源线183电连接。
例如，如图3-图6所示，显示基板10的周边区域102包括多个第一电极图案130，多个第一电极图案130间隔设置。例如，在平行于衬底基板100的板面的方向上，周边区域102还包括位于相邻的两个第一电极图案130之间且与第一电极图案130彼此绝缘的间隔图案190，间隔图案190可以减弱或避免相邻的第一电极图案130之间的信号干扰，提升第一电极图案130上传输的电信号的稳定性。
在本公开的一些实施例中，间隔图案190可以配置为从不同于第一电压源的第二电压源接收第二电压信号，由此可以使间隔图案190与相邻的第一电极图案130在平行于衬底基板100的板面的平面内形成电容，从而进一步提升对与第一电极图案130电连接的信号线120上的传输负载的补偿效果，进一步提升显示区域101中多条信号线120的信号传输效果的稳定性和一致性。
在本公开的一些实施例中，间隔图案190也可以与第二电极图案140电连接，以从第一电压源181接收第一电压信号，由此在使间隔图案190与相邻的第一电极图案130在平行于衬底基板100的板面的平面内形成电容的基础上，还可以进一步优化显示基板10的周边区域102内的布局结构，从而有助于显示基板10实现窄边框设计。
例如，如图3所示，间隔图案190可以通过第一电源线183与第二电极图案140电连接。间隔图案190可以与薄膜晶体管160的有源层161同层设置，并通过至少贯穿第一绝缘层1101、第二绝缘层1102和第三绝缘层1103的过孔结构与第一电源线183电连接，且进一步与第二电极图案140电连接。由此，通过使间隔图案190与薄膜晶体管160的有源层161在制备工艺中同层形成(例如采用同一材料层通过构图工艺形成)，可以进一步简化显示基板10的制备工艺，降低显示基板10的制备成本，从而有利于显示基板10的大量生产及应用。
在本公开的实施例中，间隔图案190呈直线型延伸且呈长条状；而在本公开的其他一些实施例中，间隔图案190也可以呈曲线型、折线型或其他适合的轮廓延伸，并且间 隔图案190的形状也可以根据实际需要采用例如椭圆形、方形、锯齿形或其他适合的规则形状或不规则形状，本公开的实施例对此不作限制。
例如，以图3-图6所示的长条形间隔图案190为例，在间隔图案190的延伸方向上，间隔图案190包括相对的第一端和第二端，第一端相对于第二端更加靠近显示区域101。间隔图案190的第一端可以例如通过至少贯穿第一绝缘层1101、第二绝缘层1102和第三绝缘层1103的过孔结构与第一电源线183电连接，且进一步与第二电极图案140电连接，从而接收第一电压信号；间隔图案190的第二端可以处于悬空状态进而不需要设置相应的过孔结构，从而减少显示基板10中所需设置的过孔，进一步简化显示基板10的制备工艺。或者，在本公开的其他一些示例中，间隔图案190的第一端和第二端可以均通过过孔结构与第一电源线183或第二电极图案140电连接以同时接收第一电压信号，从而提升间隔图案190上传输的第一电压信号的稳定性，本公开的实施例对此不作限制。
在本公开的一些实施例中，由于设置有间隔图案190的周边区域102至少部分围绕显示区域101且沿显示区域101的边缘设置，因此通过设置与薄膜晶体管160的有源层161同层的间隔图案190可以减弱或避免在显示基板10的制备过程中对显示区域101的靠近边缘部分的有源层的过度刻蚀，从而可以改善显示区域101的边界位置的刻蚀均一性，达到更好的刻蚀效果。
例如，如图3-图6所示，第二电极图案140可以沿显示区域101的边缘连续设置，且在垂直于衬底基板100的板面的方向R1上分别与多个第一电极图案130至少部分交叠且间隔绝缘设置，由此可以提升第二电极图案140上传输的第一电压信号的一致性和稳定性，从而提升第二电极图案140与多个第一电极图案130之间分别形成的多个补偿电容的一致性和稳定性，进而进一步改善与第一电极图案130电连接的信号线120的信号传输效果。同时，连续设置的第二电极图案140还有助于简化显示基板10的制备工艺，降低显示基板10的制备成本，从而有利于显示基板10的大批量生产及应用。
例如，以图2A所示的显示基板10的具体示例为例，第二电极图案140可以沿显示区域101的边缘连续设置且呈阶梯状，也即，彼此相邻的上下两级台阶处的电极图案彼此连接，从而形成一整片的第二电极图案140，由此可以降低第一电压信号通过第二电极图案140传输时的压降，从而进一步改善显示画面的亮度均匀性和一致性。
例如，如图2A所示，多个像素单元110包括第一列像素单元111和第二列像素单元112，第一列像素单元中111的像素单元110的数量少于第二列像素单元112中的像素单元110的数量，与第一列像素单元111电连接的信号线120与一个第一电极图案130电连接，由此通过该第一电极图案130与第二电极图案140之间形成的补偿电容对与第一列像素单元111电连接的信号线120的传输负载进行补偿，提升该信号线120上的信号传输效果，以使该信号线120上的信号传输效果与其他信号线120(例如与第二列像素单元112电连接的信号线120)的信号传输效果基本保持一致。
例如，与第二列像素单元112电连接的信号线120也可以与另一个第一电极图案130电连接，第二电极图案140和与第一列像素单元111电连接的信号线120电连接的一个 第一电极图案130形成的补偿电容量大于第二电极图案140和与第二列像素单元112电连接的信号线120电连接的另一个第一电极图案130形成的补偿电容量。由此，通过采用不同的补偿电容量分别对与第一列像素单元111电连接的信号线120的传输负载和与第二列像素单元112电连接的信号线120的传输负载进行补偿，可以提升与第一列像素单元111电连接的信号线120的信号传输效果和与第二列像素单元112电连接的信号线120的信号传输效果之间的一致性和稳定性。由此，可以提升显示区域101内多条信号线120的信号传输效果的一致性和稳定性，进而改善提供的显示画面的显示效果，减弱或避免显示画面出现显示异常或不良现象。
例如，多个像素单元110还包括第三列像素单元113，可以以与第三列像素单元113电连接的信号线120的传输负载为标准，为与第一列像素单元111和第二列像素单元112电连接的信号线120提供负载补偿，以使得补偿后的与第一列像素单元111和第二列像素单元112分别电连接的信号线120的负载和与第三列像素单元113电连接的信号线120的负载基本相同，从而使显示基板10中的与各列像素单元110电连接的信号线120的负载基本保持一致，从而提升显示区域101内的各条信号线120的信号传输效果的一致性，提高显示画面的显示效果。
例如，第一电极图案130和第二电极图案140在列方向上的长度可以不同，或第一电极图案130和第二电极图案140在行方向上的长度可以不同，例如，可以通过设计第一电极图案130和第二电极图案140在列方向上或行方向上的长度，以提供不同的负载补偿。例如，以通过信号线120向显示区域101中的各列像素单元110提供数据信号为例，对于包括的像素单元110的数量较少的一列，需要对与该列像素单元110电连接的信号线120提供较大的负载补偿量，因此，第一电极图案130和第二电极图案140在列方向或行方向上需要具有较大的长度，也即，一列中包括的像素单元110的数量越少，与该列像素单元110电连接的信号线120需要被提供越大的负载补偿量。由此使第一电极图案130和第二电极图案140可以在周边区域102内灵活设置，从而进一步优化显示基板10的周边区域102内的布局结构。
例如，在通过第一电极图案130和第二电极图案140之间形成的补偿电容对与第一电极图案130电连接的信号线120上的传输负载进行补偿时，根据所需的不同补偿量，可以如图2A或图2B中所示使信号线120的第一端或第二端与一个第一电极图案130电连接，也可以如图2C中所示使信号线120的第一端与一个第一电极图案130电连接且第二端与另一个第一电极图案130电连接，也即，使信号线120的两端分别与两个第一电极图案130电连接，以提高负载补偿量。本公开的实施例对此不作限制。
在本公开的一些实施例中，显示基板10的显示区域101的至少部分边缘的延伸方向与信号线120的延伸方向相交叉且不垂直，例如可以根据用户对显示基板10的形状的实际需求而进行设计以提供具有不同形状或轮廓的显示基板10，而不仅仅局限于单一的具有直角的方形显示基板。
例如，本公开实施例提供的显示基板，例如显示基板10或显示基板20可以为有机 发光二极管显示基板。
例如，本公开实施例提供的显示基板还可以为量子点发光二极管显示基板、电子纸显示基板等具有显示功能的基板或其他类型的显示基板，本公开的实施例对此不作限制。
图7为本公开一些实施例提供的一种显示基板中的像素驱动电路的等效电路图，图8A-8E为本公开一些实施例提供的一种显示基板中的像素驱动电路的各层的示意图。例如，图6中所示的存储电容170可以为图7和图8A中所示的像素驱动电路7120中的存储电容Cst，图6中所示的薄膜晶体管160可以为图7和图8A中所示的像素驱动电路7120中的多个薄膜晶体管T1、T2、T3、T4、T5、T6和T7中的至少一个。需要说明的是，图7和图8A中所示的像素驱动电路7120的具体结构只是示例性说明，本公开的实施例包括但并不仅限于此。
在一些实施例中，如图7所示，像素驱动电路7120包括多个薄膜晶体管T1、T2、T3、T4、T5、T6和T7、连接到多个薄膜晶体管T1、T2、T3、T4、T5、T6和T7的多个信号线(例如包括上述实施例中的信号线120)和存储电容Cst，多个信号线包括栅线GL、发光控制线EM、初始化线RL、数据线DL和第一电源线VDD(例如上述实施例中的第一电源线183)。栅线GL可包括第一栅线GLn和第二栅线GLn-1，例如第一栅线GLn可用于传输栅极扫描信号，第二栅线GLn-1可用于传输复位信号。发光控制线EM可用于传输发光控制信号。由此，像素驱动电路7120为7T1C的像素驱动电路。
例如，以上述实施例中的信号线120为数据线DL为例，通过第一电极图案130和第二电极图案140之间形成的补偿电容Ccp对与第一电极图案130电连接的数据线DL的传输负载进行补偿，从而改善数据线DL上传输的数据信号的补偿效果。
例如，第一电源线VDD可以与上述实施例中的电源走线图案182直接电连接以接收第一电压源181提供的第一电压信号，也可以通过与上述实施例中的第二走线图案140电连接进而与电源走线图案182电连接。
需要说明的是，本公开的实施例包括但并不限于此，像素驱动电路7120也可采用其他类型的电路结构，例如7T2C结构或者9T2C结构等，本公开的实施例对此不作限制。
例如，如图7所示，第一薄膜晶体管T1的第一栅极G1与第三薄膜晶体管T3的第三漏极D3和第四薄膜晶体管T4的第四漏极D4电连接。第一薄膜晶体管T1的第一源极S1与第二薄膜晶体管T2的第二漏极D2和第五薄膜晶体管T5的第五漏极D5电连接。第一薄膜晶体管T1的第一漏极D1与第三薄膜晶体管T3的第三源极S3和第六薄膜晶体管T6的第六源极S6电连接。
例如，如图7所示，第二薄膜晶体管T2的第二栅极G2被配置为与第一栅线GLn电连接以接收栅极扫描信号，第二薄膜晶体管T2的第二源极S2被配置为与数据线DL电连接以接收数据信号，第二薄膜晶体管T2的第二漏极D2与第一薄膜晶体管T1的第一源极S1电连接。
例如，如图7所示，第三薄膜晶体管T3的第三栅极G3被配置为与第一栅线GLn电连接，第三薄膜晶体管T3的第三源极S3与第一薄膜晶体管T1的第一漏电极D1电连 接，第三薄膜晶体管T3的第三漏极D3与第一薄膜晶体管T1的第一栅极G1电连接。
例如，如图7所示，第四薄膜晶体管T4的第四栅极G4被配置为与第二栅线GLn-1电连接以接收复位信号，第四薄膜晶体管T4的第四源极S4被配置为与初始化线RL电连接以接收初始化信号，第四薄膜晶体管T4的第四漏极D4与第一薄膜晶体管T1的第一栅极G1电连接。
例如，如图7所示，第五薄膜晶体管T5的第五栅极G5被配置为与发光控制线EM电连接以接收发光控制信号，第五薄膜晶体管T5的第五源极S5被配置为与第一电源线VDD电连接以接收第一电源信号，第五薄膜晶体管T5的第五漏极D5与第一薄膜晶体管T1的第一源极S1电连接。
例如，如图7所示，第六薄膜晶体管T6的第六栅极G6被配置为与发光控制线EM电连接以接收发光控制信号，第六薄膜晶体管T6的第六源极S6与第一薄膜晶体管T1的第一漏极D1电连接，第六薄膜晶体管T6的第六漏极D6与发光元件的第一显示电极(例如阳极)电连接。
例如，如图7所示，第七薄膜晶体管T7的第七栅极G7被配置为与第二栅线GLn-1电连接以接收复位信号，第七薄膜晶体管T7的第七源极S7与发光元件的第一显示电极(例如阳极)电连接，第七薄膜晶体管T7的第七漏极D7被配置为与初始化线RL电连接以接收初始化信号。例如，第七薄膜晶体管T7的第七漏极D7可以通过连接到第四薄膜晶体管T4的第四源极S4以实现与初始化线RL电连接。
例如，如图7所示，存储电容Cst包括第一电容电极CE1和第二电容电极CE2(例如上述实施例中的第一电容电极171和第二电容电极172)。第二电容电极CE2与第一电源线VDD电连接，第一电容电极CE1与第一薄膜晶体管T1的第一栅极G1和第三薄膜晶体管T3的第三漏极D3电连接。
例如，如图7所示，发光元件的第二显示电极(例如阴极)与第二电源线VSS电连接。
需要说明的是，第一电源线VDD和第二电源线VSS之一为提供高电压的电源线，另一个为提供低电压的电源线。在如图7所示的实施例中，第一电源线VDD(例如，与第一电压源181电连接的上述第一电源线183)提供恒定的第一电压(也即，上述第一电压信号)，第一电压为正电压；而第二电源线VSS提供恒定的第二电压，第二电压可以为负电压等。例如，在一些示例中，第二电压可以为接地电压。
需要说明的是，在一些实施例中，上述的复位信号和上述的初始化信号可以为同一信号。
需要说明的是，按照晶体管的特性，晶体管可以分为N型晶体管和P型晶体管，为了清楚起见，本公开的实施例以晶体管为P型晶体管(例如，P型MOS晶体管)为例进行说明，也就是说，在本公开的描述中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7等均可以为P型晶体管。然而本公开的实施例的晶体管不限于P型晶体管，本领域技术人员还可以根据 实际需要利用N型晶体管(例如，N型MOS晶体管)实现本公开的实施例中的一个或多个晶体管的功能。
需要说明的是，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的，本公开的实施例中全部或部分晶体管的源极和漏极根据需要是可以互换的。
例如，图8A为像素驱动电路7120的半导体层、第一导电层、第二导电层和第三导电层的层叠位置关系的示意图。
图8B示出了像素驱动电路7120的半导体层。如图8B所示，半导体层可采用半导体材料图案化形成。半导体层可用于制作上述的第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7的有源层，各有源层可包括源极区域、漏极区域以及源极区域和漏极区域之间的沟道区。例如，半导体层可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
例如，上述实施例中的有源层161和间隔图案190可以位于上述的半导体层中。
在本公开一些实施例提供的显示基板中，在上述的半导体层上形成有栅极绝缘层(例如上述实施例中的第二绝缘层1102，图8A-8E中未示出)，用于保护上述的半导体层。
图8C示出了像素驱动电路7120的第一导电层。例如，如图8C所示，像素驱动电路7120的第一导电层设置在栅极绝缘层上，从而与图8B所示的半导体层绝缘。第一导电层可包括存储电容Cst的第一电容电极CE1、第一栅线GLn、第二栅线GLn-1、发光控制线EM、以及第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7的栅极。如图8C所示，第二薄膜晶体管T2、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7的栅极为第一栅线GLn、第二栅线GLn-1与半导体层交叠的部分，第三薄膜晶体管T3可为双栅结构的薄膜晶体管，第三薄膜晶体管T3的一个栅极可为第一栅线GLn与半导体层交叠的部分，第三薄膜晶体管T3的另一个栅极可为从第一栅线GLn突出的突出部；第一薄膜晶体管T1的栅极可为第一电容电极CE1。第四薄膜晶体管T4可为双栅结构的薄膜晶体管，两个栅极分别为第二栅线GLn-1与半导体层交叠的部分。
例如，上述实施例中的第一电极图案130、栅极162和第一电容电极171可以位于上述的第一导电层中。
在本公开一些实施例提供的显示基板中，在上述的第一导电层上形成有第一层间绝缘层(例如上述实施例中的第一绝缘层1101，图8A-8E中未示出)，用于保护上述的第一导电层。
图8D示出了像素驱动电路7120的第二导电层。例如，如图8D所示，像素驱动电 路7120的第二导电层包括存储电容Cst的第二电容电极CE2和初始化线RL。第二电容电极CE2与第一电容电极CE1至少部分重叠以形成存储电容Cst。
例如，上述实施例中的第二电极图案140和第二电容电极172可以位于上述的第二导电层中。
在一些实施例中，第二导电层还可包括第一遮光部791和第二遮光部792。第一遮光部791在衬底基板710上的正投影覆盖第二薄膜晶体管T2的有源层、第三薄膜晶体管T3的漏极和第四薄膜晶体管T4的漏极之间的有源层，从而防止外界光线对第二薄膜晶体管T2、第三薄膜晶体管T3和第四薄膜晶体管T4的有源层产生影响。第二遮光部792在衬底基板710上的正投影覆盖第三薄膜晶体管T3的两个栅极之间的有源层，从而防止外界光线对第三薄膜晶体管T3的有源层产生影响。第一遮光部791可与相邻像素驱动电路的第二遮光部792为一体结构，并通过贯穿第二层间绝缘层的过孔与第一电源线VDD电连接。
在本公开一些实施例提供的显示基板中，在上述的第二导电层上形成有第二层间绝缘层(例如上述实施例中的第三绝缘层1103，图8A-8E中未示出)，用于保护上述的第二导电层。
图8E示出了像素驱动电路7120的第三导电层。例如，如图8E所示，像素驱动电路7120的第三导电层包括数据线DL(例如上述实施例中的信号线120)和第一电源线VDD(例如上述实施例中的第一电源线183)。结合图8A和图8E所示，数据线DL通过栅极绝缘层、第一层间绝缘层和第二层间绝缘层中的至少一个过孔与半导体层中的第二薄膜晶体管T2的源极区域相连。第一电源线VDD通过栅极绝缘层、第一层间绝缘层和第二层间绝缘层中的至少一个过孔与半导体层中对应第五薄膜晶体管T5的源极区域相连。第一电源线VDD通过第二层间绝缘层中的至少一个过孔与第二导电层中的第二电容电极CE2相连。
例如，上述实施例中的电源走线图案182、信号线120、第一电源线183、源极163和漏极164可以位于上述的第三导电层中。
例如，第三导电层还包括第一连接部CP1、第二连接部CP2和第三连接部CP3。第一连接部CP1的一端通过栅极绝缘层、第一层间绝缘层和第二层间绝缘层中的至少一个过孔与半导体层中对应第三薄膜晶体管T3的漏极区域相连，第一连接部CP1的另一端通过第一层间绝缘层和第二层间绝缘层中的至少一个过孔与第一导电层中的第一薄膜晶体管T1的栅极相连。第二连接部CP2的一端通过第二层间绝缘层中的一个过孔与初始化线RL相连，第二连接部CP2的另一端通过栅极绝缘层、第一层间绝缘层和第二层间绝缘层中的至少一个过孔与半导体层中的第七薄膜晶体管T7的源极区域和第四薄膜晶体管T4的源极区域相连。第三连接部CP3通过栅极绝缘层、第一层间绝缘层和第二层间绝缘层中的至少一个过孔与半导体层中的第六薄膜晶体管T6的漏极区域相连。
在本公开一些实施例提供的显示基板中，在上述的第三导电层上形成有保护层(图8A-8E中未示出)，用于保护上述的第三导电层。像素单元中的发光元件的第一显示电 极(例如阳极)可设置在保护层上。
本公开至少一个实施例还提供一种显示装置，该显示装置包括本公开任一实施例所述的显示基板。
图9为本公开一些实施例提供的一种显示装置的示意框图。例如，如图9所示，显示装置40包括显示基板401，显示基板401可以为本公开任一实施例提供的显示基板，例如可以为上述显示基板10或显示基板20。
图10为本公开一些实施例提供的另一种显示装置的示意框图。例如，如图10所示，显示装置50包括显示基板501，显示基板501可以为本公开任一实施例提供的显示基板，例如可以为上述显示基板10或显示基板20。
例如，如图10所示，显示装置50还包括数据驱动器510、栅极驱动器520、定时控制器530和电压源540等。例如，栅极驱动器520可以包括上述关于显示基板10的实施例中的栅扫描驱动电路150，即可以直接通过半导体工艺制备在衬底基板上；电压源540可以包括上述关于显示基板10的实施例中的第一电压源181，例如可以实现为电源管理电路。
例如，在一个示例中，多个像素单元P(例如上述关于显示基板10的实施例中的像素单元110)在显示基板501的显示区域中阵列排布，每个像素单元P通过数据线DL接收数据驱动器510提供的数据信号，且通过电源线VDD接收电压源540提供的电压信号。例如，在本公开实施例中的信号线为数据线的情形，数据线DL例如可以包括上述关于显示基板10的实施例中的信号线120。例如，电源线VDD例如可以包括上述关于显示基板10的实施例中的第一电源线183。
例如，数据驱动器510根据定时控制器530提供的数据控制信号DCS将从定时控制器530输入的数字图像数据RGB转换成数据信号。例如，数据驱动器510根据定时控制器530提供的数据控制信号DCS将该数据信号转换为模拟电压信号，并对模拟电压信号进行例如运算放大等处理后通过数据线DL向每个像素单元P提供对应的数据信号。例如，数据驱动器510可以实现为半导体芯片。
例如，栅极驱动器520通过扫描线SL与每个像素单元P电连接，以向每个像素单元P分别提供扫描信号。例如，栅极驱动器520根据定时控制器530提供的多个扫描控制信号GCS提供选通信号。例如，栅极驱动器520可以实现为半导体芯片，也可以集成在显示装置50中以构成GOA电路，例如上述关于显示基板10的实施例中的栅扫描驱动电路150。
例如，定时控制器530用于处理从显示装置50外部输入的图像数据RGB，向数据驱动器510提供处理的图像数据RGB以及向数据驱动器510和栅极驱动器520提供数据控制信号DCS和扫描控制信号GCS，以对数据驱动器510和栅极驱动器520进行控制。
例如，定时控制器530对外部输入的图像数据RGB进行处理以匹配显示装置50的大小和分辨率，然后向数据驱动器510提供处理后的图像数据RGB。定时控制器530使用从显示装置50外部输入的同步信号SYNC(例如点时钟DCLK、数据使能信号DE、 水平同步信号Hsync以及垂直同步信号Vsync)产生扫描控制信号GCS和数据控制信号DCS。定时控制器530分别向数据驱动器510和栅极驱动器520提供产生的数据控制信号DCS和扫描控制信号GCS，以用于数据驱动器510和栅极驱动器520的控制。
本公开实施例提供的显示装置40和显示装置50的结构、功能及技术效果等可以参考上述本公开实施例提供的显示基板10或显示基板20中的相应描述，在此不再赘述。
例如，本公开实施例提供的显示装置40和显示装置50可以为有机发光二极管显示装置。或者，本公开实施例提供的显示装置40和显示装置50还可以为量子点发光二极管显示装置、电子纸显示装置等具有显示功能的装置或其他类型的显示装置，本公开的实施例对此不作限制。
例如，本公开实施例提供的显示装置40和显示装置50可以为显示基板、显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开的实施例对此不作限制。
还有以下几点需要说明：
(1)本公开实施例的附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或第一基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (22)

  1. 一种显示基板，具有显示区域和至少部分围绕所述显示区域的周边区域，且包括：衬底基板；
    其中，所述显示区域包括阵列排布在所述衬底基板上的多个像素单元以及分别与所述多个像素单元电连接的多条信号线，
    所述周边区域包括与所述多条信号线中的至少一条电连接的至少一个第一电极图案，以及包括第二电极图案，
    所述至少一个第一电极图案与所述第二电极图案在垂直于所述衬底基板的板面的方向上至少部分交叠且间隔绝缘设置，
    所述周边区域还包括栅扫描驱动电路，所述栅扫描驱动电路配置为向所述多个像素单元提供栅极扫描信号，
    在平行于所述衬底基板的板面的方向上，所述至少一个第一电极图案和所述第二电极图案位于所述栅扫描驱动电路和所述显示区域之间。
  2. 根据权利要求1所述的显示基板，其中，所述至少一个第一电极图案在所述衬底基板上的正投影位于所述第二电极图案在所述衬底基板上的正投影内。
  3. 根据权利要求1或2所述的显示基板，其中，所述第二电极图案位于所述至少一个第一电极图案的远离所述衬底基板的一侧。
  4. 根据权利要求3所述的显示基板，其中，所述多个像素单元中的至少一个包括位于所述衬底基板上的像素驱动电路，所述像素驱动电路包括薄膜晶体管和存储电容；
    所述薄膜晶体管包括有源层、栅极、源极和漏极，所述存储电容包括第一电容电极和与所述第一电容电极在垂直于所述衬底基板的板面的方向上相对的第二电容电极；
    所述源极和所述漏极位于所述有源层远离所述衬底基板的一侧，
    所述第一电极图案、所述栅极和所述第一电容电极同层设置，所述第二电极图案和所述第二电容电极同层设置。
  5. 根据权利要求4所述的显示基板，其中，所述多条信号线与所述薄膜晶体管的源极和漏极同层设置，所述至少一个第一电极图案通过过孔结构与所述多条信号线中的至少一条电连接。
  6. 根据权利要求4或5所述的显示基板，其中，所述第二电极图案配置为从第一电压源接收第一电压信号。
  7. 根据权利要求6所述的显示基板，其中，所述周边区域还包括电源走线图案，
    所述电源走线图案与所述第一电压源电连接，所述第二电极图案与所述电源走线图案电连接以通过所述电源走线图案接收所述第一电压信号。
  8. 根据权利要求7所述的显示基板，其中，所述电源走线图案与所述薄膜晶体管的源极和漏极同层设置，
    所述第二电极图案通过过孔结构与所述电源走线图案电连接。
  9. 根据权利要求7或8所述的显示基板，其中，在平行于所述衬底基板的板面的方向上，所述第二电极图案的至少部分电连接在所述电源走线图案和所述多个像素单元之间，
    所述电源走线图案通过所述第二电极图案向所述多个像素单元中的至少部分提供所述第一电压信号。
  10. 根据权利要求6-9中任一项所述的显示基板，其中，所述至少一个第一电极图案包括多个第一电极图案，所述多个第一电极图案间隔设置；
    所述周边区域还包括位于相邻的两个第一电极图案之间且与所述第一电极图案彼此绝缘的间隔图案。
  11. 根据权利要求10所述的显示基板，其中，所述间隔图案配置为从不同于所述第一电压源的第二电压源接收第二电压信号。
  12. 根据权利要求10所述的显示基板，其中，所述间隔图案与所述第二电极图案电连接，以从所述第一电压源接收所述第一电压信号。
  13. 根据权利要求10-12中任一项所述的显示基板，其中，所述间隔图案与所述薄膜晶体管的有源层同层设置。
  14. 根据权利要求10-13中任一项所述的显示基板，其中，所述第二电极图案沿所述显示区域的边缘连续设置，且在垂直于所述衬底基板的板面的方向上分别与所述多个第一电极图案至少部分交叠且间隔绝缘设置。
  15. 根据权利要求1-14中任一项所述的显示基板，其中，所述显示区域的至少部分边缘的延伸方向与所述多条信号线的延伸方向相交叉且不垂直。
  16. 根据权利要求1-15中任一项所述的显示基板，其中，所述显示基板还包括位于所述第一电极图案和所述第二电极图案之间的第一绝缘层，
    所述第一绝缘层的材料包括氮化硅或氮氧化硅。
  17. 根据权利要求1-16中任一项所述的显示基板，其中，所述多个像素单元包括第一列像素单元和第二列像素单元，所述第一列像素单元中的像素单元的数量少于所述第二列像素单元中的像素单元的数量，与所述第一列像素单元电连接的信号线与一个第一电极图案电连接。
  18. 根据权利要求17所述的显示基板，其中，与所述第二列像素单元电连接的信号线与另一个第一电极图案电连接，
    所述第二电极图案和与所述第一列像素单元电连接的信号线电连接的所述一个第一电极图案形成的补偿电容量大于所述第二电极图案和与所述第二列像素单元电连接的信号线电连接的所述另一个第一电极图案形成的补偿电容量。
  19. 根据权利要求1-18中任一项所述的显示基板，其中，所述第一电极图案和所述第二电极图案在列方向上的长度不同，或
    所述第一电极图案和所述第二电极图案在行方向上的长度不同。
  20. 根据权利要求1-19中任一项所述的显示基板，其中，所述多条信号线为扫描线 或者数据线。
  21. 根据权利要求1-20中任一项所述的显示基板，其中，所述多条信号线中的至少一条的第一端或第二端与一个第一电极图案电连接，或
    所述多条信号线中的至少一条的第一端与一个第一电极图案电连接，所述多条信号线中的至少一条的第二端与另一个第一电极图案电连接。
  22. 一种显示装置，包括如权利要求1-21中任一项所述的显示基板。
PCT/CN2021/093627 2020-06-30 2021-05-13 显示基板及显示装置 WO2022001410A1 (zh)

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