WO2022226996A1 - 显示基板以及显示装置 - Google Patents

显示基板以及显示装置 Download PDF

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Publication number
WO2022226996A1
WO2022226996A1 PCT/CN2021/091475 CN2021091475W WO2022226996A1 WO 2022226996 A1 WO2022226996 A1 WO 2022226996A1 CN 2021091475 W CN2021091475 W CN 2021091475W WO 2022226996 A1 WO2022226996 A1 WO 2022226996A1
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WIPO (PCT)
Prior art keywords
pixel circuit
data line
data
display area
sub
Prior art date
Application number
PCT/CN2021/091475
Other languages
English (en)
French (fr)
Inventor
程羽雕
王彬艳
龙跃
黄炜赟
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180001035.5A priority Critical patent/CN115812236A/zh
Priority to US17/629,106 priority patent/US20230320145A1/en
Priority to PCT/CN2021/091475 priority patent/WO2022226996A1/zh
Priority to EP21938470.8A priority patent/EP4202909A4/en
Publication of WO2022226996A1 publication Critical patent/WO2022226996A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
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    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
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    • G09G2300/0408—Integration of the drivers onto the display substrate
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
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    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
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    • G09G2320/043—Preventing or counteracting the effects of ageing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors

Definitions

  • At least one embodiment of the present disclosure relates to a display substrate and a display device.
  • At least one embodiment of the present disclosure provides a display substrate and a display device.
  • At least one embodiment of the present disclosure provides a display substrate including a base substrate and a plurality of data lines on the base substrate.
  • the display substrate includes a first display area and a second display area, the first display area is located at the periphery of the second display area, and the first display area includes a plurality of first light-emitting elements, a plurality of first pixel circuits, a plurality of second pixel circuits and a plurality of third pixel circuits, the plurality of first pixel circuits are connected with the plurality of first light-emitting elements in a one-to-one correspondence, the second display area includes a plurality of second light-emitting elements, The plurality of second pixel circuits are connected to the plurality of second light-emitting elements in a one-to-one correspondence, and the third pixel circuits are dummy pixel circuits; the plurality of data lines do not pass through the second display area, wherein the The plurality of data lines include a plurality of first data lines and
  • the second pixel circuit is connected. In a direction perpendicular to the base substrate, parts of the plurality of third pixel circuits overlap with the plurality of second data lines, and in the third pixel circuits overlapping the second data lines At least part of the second data line is insulated from the second data line.
  • each of the third pixel circuits overlapping the second data line is provided insulated from the second data line.
  • each of the first data lines extends along a first direction, and an extension line among the plurality of first data lines is configured not to pass through the first data lines of the second display area
  • each of the second data lines is configured to transmit signals to N pixel circuits, and M ⁇ N, the N pixel circuits at least include the second pixel circuit.
  • the second data line includes a first sub data line and a second sub data line extending in the first direction, and connects the first sub data line and the second sub data line
  • the transition line of the sub-data line; the first sub-data line, the second sub-data line and the first data line are arranged in the same layer, and the first sub-data line is configured as the first pixel circuit connected, the second sub-data line is configured to be connected to the second pixel circuit.
  • the display substrate further includes: a plurality of traces extending along the first direction and not passing through the second display area.
  • the plurality of wirings and the plurality of first data lines are arranged in the same layer, and at least one data line is arranged between two adjacent wirings; along the direction perpendicular to the base substrate, each of the wirings Lines only overlap the third pixel circuit.
  • the plurality of traces includes a plurality of first traces, the number of the first traces is the same as the number of the second sub-data lines, and one of the first traces At least part of a second sub-data line is substantially located on the same straight line with a space therebetween; and the transfer area includes the plurality of transfer lines.
  • the transfer area includes a first transfer area located on one side of the second display area in the first direction, and the transfer line in the first transfer area intersects the first direction along the line extending in the second direction and located in a different layer from the first data line, the space is located on the side of the first transfer area away from the second display area, the first trace and at least part of the The third pixel circuits overlap.
  • the first trace line and the second sub-data line are configured to transmit different electrical signals.
  • the first trace is configured to transmit a power supply voltage signal.
  • the transfer area further includes a second transfer area located on the other side of the second display area in the first direction, and the second transfer area is located in the second transfer area. non-display areas other than the first display area and the second display area.
  • each of the patch lines in the second patch area includes a first patch cable and a second patch cable that are connected to each other and are arranged at different layers.
  • One of the two transition lines is connected to the second sub-data line, and is located on a different layer from the second sub-data line.
  • each of the second data lines two first sub-data lines are connected to the same second sub-data line, and the two first sub-data lines are respectively located in the second sub-data line.
  • the display area is on both sides of the first direction, and at least parts of the two first sub-data lines are substantially located on the same straight line.
  • one of the second sub-data lines extends along the first direction and overlaps with an orthographic projection of one of the traces on a straight line extending along the first direction.
  • the patch cord is located in a non-display area other than the first display area and the second display area.
  • each of the patch cords includes a first patch cord and a second patch cord that are connected to each other and provided at different layers, and one of the first patch cord and the second patch cord is connected to the The second sub data lines are connected and located at different layers from the second sub data lines.
  • the length of the second sub data line is not less than the length of the first data line whose extension line does not pass through the second display area among the plurality of first data lines.
  • the first sub-data line and one first data line are respectively located on both sides of the second display area in the first direction, and are substantially located on the same straight line.
  • the first sub data line and the first data line substantially on the same line are configured to transmit the same data signal.
  • the other one of the first jumper line and the second jumper line extends in a second direction intersecting the first direction, and is located at the second sub-data line same layer.
  • the second data line extends along the first direction, and the second data line is configured to be connected only to the second pixel circuit.
  • the plurality of pixel circuits included in the first display area are arranged in an array along the first direction and the second direction, and the plurality of second pixel circuits are located in the second display area on both sides of the second direction.
  • a column of pixel circuits where the second pixel circuits arranged along the first direction are located includes the third pixel circuit, and the third pixel circuit in the column of pixel circuits overlapping with the second data line.
  • the plurality of third pixel circuits include a plurality of third pixel circuit columns extending along the first direction and arranged along the second direction, and the plurality of third pixel circuit columns are At least part of the second display area is located on at least one side of the second display area in the first direction.
  • the plurality of third pixel circuit columns further include portions located on both sides of the second display area in the second direction.
  • the pixel circuit includes a data writing transistor, the data writing transistor includes a first electrode, a second electrode, and a gate, and a film layer where the first electrode of the data writing transistor is located An insulating layer is arranged between the film layer where the data line is located, and the first electrodes of the data writing transistors in the first pixel circuit and the second pixel circuit pass through via holes in the insulating layer connected to the data line, the first electrode of the data writing transistor and the second data line in at least part of the third pixel circuit overlapping the second data line are covered by the insulating layer insulation.
  • At least one embodiment of the present disclosure provides a display substrate including a base substrate, a plurality of pixel circuits on the base substrate, and a plurality of data lines.
  • the plurality of pixel circuits include a plurality of first type pixel circuits and a plurality of second type pixel circuits, the first type pixel circuits are electrically connected to the data lines, and the second type pixel circuits are connected to the data lines Insulation set.
  • the pixel circuit of the first type is electrically connected with the data line overlapping therewith, and the pixel circuit of the second type is insulated from the data line overlapping therewith.
  • the first type of pixel circuit is configured to drive a light-emitting element connected thereto to emit light
  • the second type of pixel circuit is a first dummy pixel circuit
  • the first-type pixel circuit includes a first pixel circuit and a second pixel circuit, and the first pixel circuit and the light-emitting element connected thereto are in a vertical direction perpendicular to the base substrate.
  • the first type pixel circuit further includes a second dummy pixel circuit.
  • the pixel circuits of the second type and part of the pixel circuits of the first type are located in the same column.
  • the second type pixel circuit and the second pixel circuit are located in the same column.
  • the pixel circuit includes a data writing transistor, the data writing transistor includes a first electrode, a second electrode, and a gate, and a film layer where the first electrode of the data writing transistor is located An insulating layer is arranged between the film layer where the data line is located, and the first electrode of the data writing transistor of the first type pixel circuit is connected to the corresponding data line through a via hole located in the insulating layer. connected; the first electrode of the data writing transistor of the second type pixel circuit is insulated from the data line by the insulating layer.
  • At least one embodiment of the present disclosure provides a display device including any of the above-mentioned display substrates.
  • FIG. 1 is a schematic partial plan view of a display substrate in a display device with an under-screen camera
  • FIG. 2 is a schematic partial plan structure diagram of a display substrate provided according to an example of an embodiment of the present disclosure
  • FIG. 3 is a partial enlarged structural schematic diagram of the display substrate shown in FIG. 2;
  • FIG. 4 is a schematic partial plan structure diagram of a display substrate provided according to another example of an embodiment of the present disclosure.
  • FIG. 5 is a partial enlarged structural schematic diagram of the display substrate shown in FIG. 4;
  • FIG. 6 is a schematic partial plan structure diagram of a display substrate provided according to another example of an embodiment of the present disclosure.
  • FIGS. 2 to 6 are equivalent diagrams of each pixel circuit in the display substrate shown in FIGS. 2 to 6;
  • FIG. 8 is a schematic partial plan structure diagram of a stacked structure of an active semiconductor layer, a first conductive layer, and a source-drain metal layer of a second pixel circuit according to an embodiment of the present disclosure
  • FIG. 9 is a partial planar structural schematic diagram of a stacked structure of an active semiconductor layer, a first conductive layer, a source-drain metal layer, and a second conductive layer of a second pixel circuit according to an embodiment of the present disclosure
  • Fig. 10 is a partial cross-sectional structural schematic diagram taken along AA' in the pixel circuit shown in Fig. 8;
  • FIG. 11 is a schematic partial plan structure diagram of a stacked structure of an active semiconductor layer, a first conductive layer, and a source-drain metal layer of a third pixel circuit according to an embodiment of the present disclosure
  • Fig. 12 is a partial cross-sectional structural schematic diagram taken along BB' in the pixel circuit shown in Fig. 11;
  • FIG. 13 is a schematic diagram of the display area of the display substrate shown in FIG. 2 and a second data line;
  • FIG. 14 is an enlarged view of the area E1 shown in FIG. 13;
  • FIG. 15 is an enlarged view of the area E2 shown in FIG. 13;
  • FIG. 16 is an enlarged view of the area E3 shown in FIG. 13;
  • FIG. 17 is an enlarged view of the area E4 shown in FIG. 13;
  • Fig. 18 is a partial structure including a partial enlarged view shown in Fig. 16;
  • FIG. 19 is a partial structure including a partial enlarged view shown in FIG. 17 .
  • Full display camera means that the front camera is located below the screen but does not affect the display function of the screen.
  • the screen above the camera can still display images normally. From the appearance point of view, the under-screen camera will not have any camera hole, which truly achieves the full-screen display effect.
  • FIG. 1 is a schematic partial plan view of a display substrate in a display device with an under-screen camera.
  • the display substrate includes a base substrate 10
  • the display substrate includes a first display area 11 for normal display and a second display area 12 for setting a camera.
  • the first display area 11 may be located on at least one side of the second display area 12 .
  • the first display area 11 surrounds the second display area 12
  • the second display area 12 is a light-transmitting display area
  • the first display area 11 is an opaque display area only for display.
  • the first display area 11 in the display substrate shown in FIG. 1 includes a first light-emitting element and a first pixel circuit for driving the first light-emitting element to emit light
  • the second display area 12 includes a second light-emitting element.
  • the second pixel circuit that emits light from the second light-emitting element is located in the first display area to improve the light transmittance of the second display area 12, that is, the light transmittance of the second display area 12 is improved by separating the light-emitting element and the pixel circuit. over rate.
  • the plurality of second pixel circuits may be distributed among the plurality of first pixel circuits at intervals.
  • the second light-emitting element may be connected to the second pixel circuit through a transparent wire.
  • the second display area 12 may be a hole area in which pixel circuits are not disposed in the entire display area.
  • the density of the light-emitting elements provided in the first display area 11 and the second display area 12 may be the same or different.
  • the display substrate includes a plurality of data lines 20 on the base substrate 10 .
  • the setting methods of the multiple data lines include two methods: winding in the second display area and winding outside the second display area. Due to the limitation of the space size of the second display area, The display substrate shown in FIG. 1 is designed according to a fully compressed pixel circuit scheme, and the data lines are arranged in a way of winding the data lines outside the second display area 12 .
  • the first display area includes a plurality of first pixel circuit columns and a plurality of second pixel circuit columns, and the second pixel circuit column where the second pixel circuits are located not only includes the second pixel circuit, but also includes a A dummy pixel circuit connected with elements; the first display area further includes a plurality of dummy pixel circuit columns, and at least one first pixel circuit column is arranged between two adjacent dummy pixel circuit columns.
  • the above fully compressed pixel circuit refers to compressing a plurality of pixel circuits in the overall display area in the X direction without reducing the pixel density of the overall display area (including the first display area and the second display area) (for example, The size of each pixel circuit along the X direction is reduced) to increase the number of pixel circuits arranged along the X direction, and the newly added column of pixel circuits includes a second column of pixel circuits for connecting with the second light-emitting elements of the second display area , and a column of dummy pixel circuits not connected to any light-emitting element.
  • the plurality of data lines 20 include a data line 21 connected only to the first pixel circuit and a data line 22 connected to at least the second pixel circuit.
  • the data line 21 is a data line extending in the Y direction.
  • each data line 20 can be driven by a single channel, and some data lines 20 are disconnected at the edge of the second display area 12 , that is, some data lines 20 include two parts of data lines 22 - 1 located on the upper and lower sides of the second display area 12 , the two parts of the data lines 22-1 are both connected to the first pixel circuit, and the two parts of the data lines 22-1 can be electrically connected through the transfer line 22-3 and the data line 22-2 connected to the second pixel circuit to achieve electrical connection.
  • the data line 22 includes, for example, five parts, and the five parts are the data line 22-1, the transfer line 22-3, the data line 22-2, the transfer line 22-3, and the data line 22-1 in sequence.
  • a1 to a5 represent the number of pixel circuits connected to the data lines at the corresponding positions in the figure.
  • the metal line where the data line 22-2 is located is disconnected into two parts at the side of the transition line 22-3 away from the second display area 12 , the metal line includes a data line 22-2 and a wiring 30, and a space 23 is set between the data line 22-2 and the wiring 30 to achieve insulation between the two.
  • the wiring 30 is connected to the dummy pixel circuit.
  • the traces 30 can be connected to the power supply voltage signal (VDD).
  • VDD power supply voltage signal
  • the number b of pixel circuits connected to the data line 22 is greater than the number a of pixel circuits connected to the data line 21, which will cause the load of the data line 22 to be too large, for example, when all the data lines input the same signal at the same time (ET lights up ), dark vertical stripes are prone to appear at the position of the second display area, which affects the display quality of the display device.
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • the display substrate includes a base substrate and a plurality of data lines on the base substrate.
  • the display substrate includes a first display area and a second display area, the first display area is located at the periphery of the second display area, and the first display area includes a plurality of first light-emitting elements, a plurality of first pixel circuits, and a plurality of second pixel circuits and a plurality of third pixel circuits, the plurality of first pixel circuits are connected with a plurality of first light-emitting elements in one-to-one correspondence, the second display area includes a plurality of second light-emitting elements, a plurality of second pixel circuits and a plurality of second light-emitting elements The elements are connected in one-to-one correspondence, and the third pixel circuit is a dummy pixel circuit; the multiple data lines do not pass through the second display area, and the multiple data lines include multiple first data
  • Each second data line is configured to be connected only to the first pixel circuit, and each of the second data lines is configured to be connected to at least the second pixel circuit.
  • parts of the plurality of third pixel circuits overlap with the plurality of second data lines, and at least part of the third pixel circuits overlapping with the second data lines are insulated from the second data lines .
  • the display substrate provided by the embodiments of the present disclosure, by setting at least part of the third pixel circuits overlapping the second data lines to not be connected to the second data lines, the number of pixel circuits connected to the second data lines can be reduced to reduce the number of pixel circuits connected to the second data lines. load, thereby alleviating the phenomenon of dark vertical stripes in the second display area and improving the display quality of the display substrate.
  • FIG. 2 is a schematic diagram of a partial plan structure of a display substrate provided according to an example of an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a partial enlarged structure of the display substrate shown in FIG. 2
  • the display substrate includes a base substrate 100 and a plurality of data lines 200 located on the base substrate 100 .
  • the display substrate includes a first display area 111 and a second display area 112 , and the first display area 111 is located at the periphery of the second display area 112 .
  • the first display area 111 surrounds the second display area 112 , that is, the second display area 112 may be surrounded by the first display area 111 .
  • the second display area 112 may also be set at other positions, and the setting position of the second display area 112 may be determined according to needs, for example, the second display area 112 may be located in the overall display area ( The top middle position of the display area including the first display area and the second display area) may also be located at the upper left corner or the upper right corner of the overall display area.
  • 2 schematically shows that the shape of the first display area 111 is a rectangle, and the shape of the second display area 112 is a circle, but not limited thereto, the shape of the second display area 112 may also be a regular shape such as a rectangle, an ellipse, etc. Or irregular shape, the shape of the first display area 111 may also be a regular shape such as a circle, a hexagon, or an irregular shape.
  • the first display area 110 includes a plurality of first light-emitting elements 111 , a plurality of first pixel circuits 112 , a plurality of second pixel circuits 113 and a plurality of third pixel circuits 114 .
  • a pixel circuit 112 is connected to a plurality of first light-emitting elements 111 in a one-to-one correspondence to drive the plurality of first light-emitting elements 111 to emit light;
  • the second display area 120 includes a plurality of second light-emitting elements 121, a plurality of second pixel circuits 113 and
  • the plurality of second light-emitting elements 121 are connected in one-to-one correspondence to drive the plurality of second light-emitting elements 121 to emit light
  • the third pixel circuit 114 is a dummy pixel circuit.
  • the above-mentioned dummy pixel circuit refers to a pixel circuit that is not connected to any light-emitting element.
  • the second display area is only provided with a transparent second light-emitting element, but not a non-transparent pixel circuit.
  • the second display area can be used as a camera area under the screen, which can not only have a high light transmittance to realize the camera function, but also Lighting can be achieved by connecting with pixel circuits in other areas, without affecting the display function of the screen.
  • the average distance between the first pixel circuit 112 and the first light-emitting element 111 connected thereto is smaller than that between the second pixel circuit 113 and the second light-emitting element 121 connected thereto average distance.
  • the average distance is, for example, the average value of the distances between the driving transistors of a column of pixel circuits and the centers of the light-emitting elements connected thereto.
  • the second pixel circuit 113 may be connected to the corresponding second light emitting element 121 through the transparent wire 400; neither the second pixel circuit 113 nor the third pixel circuit 114 overlaps the light emitting element.
  • the second pixel circuit 113 may only be located on both sides of the second display area 120 along the X direction, and the first pixel circuit 112 includes both the parts located on both sides of the second display area 120 along the X direction, and the second display area 120 on both sides of the second display area 120. Portions of both sides of the region 120 along the Y direction.
  • the pixel circuit column where the second pixel circuits 113 arranged along the first direction are located includes the third pixel circuit 114 , and the third pixel circuit 114 in the pixel circuit column overlaps or is electrically connected to the second data line 220 .
  • the pixel circuit column where the second pixel circuit 113 is located (for example, a plurality of pixel circuits arranged along the Y direction as one pixel circuit column) includes the third pixel circuit 114 in addition to the second pixel circuit 113 .
  • the number of pixel circuits included in the pixel circuit column where the second pixel circuit 113 is located can be the same as the pixel circuit column where the first pixel circuit 112 is located (except that the data lines connected to the pixel circuit column pass through the second display area)
  • the number of pixel circuits included in the pixel circuit columns other than the pixel circuit column of 120) is approximately the same.
  • the pixel circuit column where the first pixel circuit 112 is located only includes the first pixel circuit 112
  • the pixel circuit column where the second pixel circuit 113 is located includes the second pixel circuit 113 and the third pixel circuit 114 .
  • at least one first pixel circuit column may be disposed between two pixel circuit columns where adjacent second pixel circuits are located.
  • the plurality of pixel circuits included in the first display area 110 are arranged in an array along the first direction and the second direction, and the plurality of second pixel circuits 113 are located on both sides of the second display area 120 in the second direction.
  • the display substrate further includes a plurality of third pixel circuit columns (not shown in FIG. 2 and FIG. 3 , each third pixel circuit column includes only third pixel circuits), and at least one pixel circuit column is disposed between adjacent third pixel circuit columns The first pixel circuit column.
  • the third pixel circuit column includes parts distributed on both sides of the second display area 120 along the X direction, and the third pixel circuit column may also be distributed at another part on both sides of the second display area 120 along the Y direction.
  • the plurality of data lines 200 do not pass through the second display area 120 to prevent the light transmittance of the second display area 120 from being affected.
  • the setting methods of the multiple data lines include two methods: winding in the second display area and winding outside the second display area. Due to the limitation of the space size of the second display area,
  • the display substrate provided by the embodiment of the present disclosure is designed according to a fully compressed pixel circuit scheme, and the data lines are arranged in a way of winding the data lines outside the second display area 120 .
  • the plurality of data lines 200 include a plurality of first data lines 210 and a plurality of second data lines 220, each of the first data lines 210 is configured to be connected only to the first pixel circuit 112, and each of the second data lines 220 is configured to be at least Connected to the second pixel circuit 113 .
  • a plurality of first data lines 210 may be arranged between adjacent second data lines 220 .
  • FIGS. 2 and 3 there are 2 to 10 (FIG. 3 schematically shows 2 first data lines), which is not limited in this embodiment of the present disclosure, and can be set according to actual product requirements.
  • the plurality of second data lines 220 located on both sides of the second display area 120 in the X direction may be uniformly distributed, but not limited thereto.
  • the second data lines may be unevenly distributed, and the number of first data lines disposed between adjacent second data lines may be different.
  • portions of the plurality of third pixel circuits 114 overlap with the plurality of second data lines 220 (eg, overlap and connect with the second data lines).
  • the third pixel circuit can be electrically connected through a via hole vertical to the substrate), and at least a part of the third pixel circuit 114 overlapping the second data line 220 is insulated from the second data line 220 (for example, compared with the normal pixel circuit, At least part of the via holes used for the pixel circuit to be electrically connected to the data line are not provided with via holes and are isolated by an insulating layer, so that the pixel circuit cannot be electrically connected to the data line to realize the function of the pixel circuit).
  • Black dots are set between the data line 200 and the pixel circuit that overlaps it as shown in FIG. 3 to indicate that the two have a connection relationship.
  • No black dots are set between the data line 200 and the pixel circuit that overlaps it, which means that the two are insulated. That is, there is no connection relationship.
  • the display substrate provided by the embodiment of the present disclosure, by arranging at least part of the third pixel circuit overlapping the second data line to be insulated from the second data line, the number of pixel circuits connected to the second data line can be reduced to reduce the Therefore, when all the data lines input the same signal at the same time (ET lighting), the phenomenon of dark vertical stripes in the second display area can be alleviated, and the display quality of the display substrate can be improved.
  • the number of pixel circuits connected to the second data line is reduced to reduce the load, and the burden of the driver IC can also be reduced when each data line inputs a corresponding data signal (module lighting).
  • each third pixel circuit 114 overlapping the second data line 220 is insulated from the second data line 220 , that is, all the third pixel circuits overlapping the second data line 220 114 are not connected to the second data line 220, then the pixel circuits connected to the second data line 220 are all pixel circuits configured to drive the light-emitting element to emit light, thereby greatly reducing the number of pixel circuits connected to the second data line. , thereby reducing the load of the second data line.
  • each of the first data lines 210 extends along a first direction.
  • the first direction is schematically shown as the Y direction in the figures, but it is not limited to this, and may also be as shown in the figures. the X direction.
  • the first data lines 210 of the plurality of first data lines whose extension lines do not pass through the second display area 120 are configured to transmit data signals to the M first pixel circuits 112 , for example, the first data lines 210 may run through the first Display area 110 .
  • Each of the second data lines 220 is configured to transmit signals to N pixel circuits, and M ⁇ N, the N pixel circuits include at least the second pixel circuit.
  • the N pixel circuits here refer to the pixel circuits connected to the second data line 220, including the second pixel circuit connected to the second sub-data line and the first pixel circuit connected to the first sub-data line described later, or only A second pixel circuit is included.
  • the first data lines 210 only include data lines located on both sides of the second display area 120 in the X direction, then the second data lines 220 are not connected to the dummy pixel circuits , the number N of pixel circuits connected to the second data line 220 is not greater than the number M of pixel circuits connected to the first data line 210 .
  • the number N of pixel circuits connected to the second data line 220 is equal to the number M of the first pixel circuits 111 connected to the first data line 210 .
  • each of the second data lines 220 includes a first sub-data line 221 and a second sub-data line 222 extending in the first direction, and connects the first sub-data line 221 and the second sub-data line 221 The patch cord 223 of the data line 222 .
  • the first sub-data line 221 , the second sub-data line 222 and the first data line 210 are arranged in the same layer, and the first sub-data line 221 is configured to be connected to the first pixel circuit 112 , the second sub data line 222 is configured to be connected to the second pixel circuit 113 .
  • the first sub-data line 221 included in the second data line 220 is a data line extending to the edge of the second display area 120 .
  • the data lines 200 connected to the first pixel circuits 112 located on both sides of the second display area 120 in the X direction are the first data lines 210
  • the data lines 200 connected to the first pixel circuits 112 located in the second display area 120 in the Y direction are the first data lines 210 .
  • the data lines 200 connected to the first pixel circuits 112 on both sides of the direction are the first sub-data lines 221 of the second data lines 220
  • the data lines 200 connected to the second pixel circuits 113 are the second sub-data lines 220 of the second data lines 220 .
  • Sub data line 222 is the first sub-data lines 221 of the second data lines 220
  • the data lines 200 connected to the second pixel circuits 113 are the second sub-data lines 220 of the second data lines 220 .
  • FIG. 2 and FIG. 3 schematically show that the first sub-data line 221 in each second data line 220 includes two parts distributed on both sides of the second display area 120 in the Y direction, but not limited thereto,
  • the first sub-data lines included in each second data line may also be located only on one side of the second display area, for example, the first pixel circuit and The first sub data line.
  • the display substrate includes a transition area 2230 , a plurality of transition lines 223 are disposed in the transition area 2230 , and the transition area 2230 includes a side of the second display area 120 in the first direction.
  • the first transfer area 2231, the transfer area 2230 further includes a second transfer area 2232 located on the other side of the second display area 120 in the first direction.
  • the patch lines 223 in the first patch area 2231 extend in a second direction intersecting with the first direction.
  • 2 and 3 schematically show that the first direction and the second direction are perpendicular, but not limited thereto, the first direction and the second direction may not be perpendicular.
  • the jumper lines 223 in the first transfer area 2231 are located at different layers from the first sub-data lines 221.
  • the jumper lines 223 may be located in the first sub-data lines 221 away from the base substrate. 100 side.
  • the patch cords 223 in the second patch area 2232 may include a first patch cable 223-1 and a second patch cable 223-2 that are connected to each other and arranged at different layers.
  • One of the wiring 223-1 and the second transition wiring 223-2 is connected to the second sub data line 222, and is located on a different layer from the second sub data line 222.
  • each patch cord 223 includes two second patch cables 223-2, one first patch cable 223-1 connecting the two second patch cables 223-2, and two second patch cables 223 One of -2 is connected to the second sub data line 222 , and the other of the two second transfer lines 223 - 2 is connected to the first sub data line 221 .
  • the first patch cord 223-1 extends in the second direction
  • the second patch cord 223-2 extends in the first direction.
  • the first patch line 223-1 may be substantially parallel to the patch line 223 located in the first patch region 2231.
  • the second patch line 223-2 and the second sub-data line 222 are located on different layers.
  • the first transition line 223-1 may be located on the same layer as the second sub data line 222.
  • the embodiment of the present disclosure is not limited thereto, the first patch cord may be in a different layer from the second sub data line, and the second patch cord may be at the same layer as the second sub data line.
  • the second data line 220 includes five parts connected in sequence, such as a first sub-data line 221 , a patch cord 223 , a second sub-data line 222 , a patch cord 223 and a first sub-data line 222 .
  • the above-mentioned two first sub-data lines 221 are respectively connected to the same continuous second sub-data line 222 through two parts of the transition lines 223, and the two first sub-data lines 221 are respectively located in the second display area 120 in the first sub-data line 222.
  • the two first sub-data lines 221 are located on the same straight line.
  • the two data lines are located on the same straight line means that the two data lines are roughly located on the same straight line, for example, more than 50% of the two data lines are located on the same straight line, or the two data lines are offset in the second direction
  • the maximum distance is less than 5 microns, or 3 microns, etc.
  • data signals are loaded onto the first data lines 210 located on the left and right sides of the second display area 120 through a circuit board (not shown) located on the lower side of the first display area 110 to be supplied to the first data lines 210 connected to the M first pixel circuits 112; data signals are loaded onto the first sub-data lines 221 located on the lower side of the second display area 120 through the circuit board located on the lower side of the first display area 110 to be provided to the first sub-data line 221 located on the lower side of the second display area 120.
  • the first sub-data lines on both sides and the second sub-data lines connected to the two first sub-data lines transmit the same data signal, and this data signal transmission mode may be called single-channel driving.
  • the data lines in the display substrate shown in FIG. 2 are driven by a single channel.
  • reducing the number of pixel circuits connected to the second data line reduces the load, and also reduces the burden on the driver IC when each data line inputs a corresponding data signal (module lighting).
  • the first sub-data lines connected to the first pixel circuits are arranged on both sides of the second display area in the first direction.
  • the two parts of the first sub-data lines need to be electrically connected through the second sub-data lines and the two parts of the transfer lines, so the transfer area includes the first transfer area and the second transfer area respectively located on both sides of the second display area. access area.
  • the second transition area 2232 is located in a non-display area other than the first display area 110 and the second display area 112 to prevent the transition lines in the second transition area from affecting the display effect of the display substrate.
  • the distance between two adjacent first transition lines 223-1 in the second transition area 2232 may be smaller than the distance between two adjacent transition lines 223 in the first transition area 2231, so as to Minimize the size of the frame to achieve a narrow frame.
  • the third pixel circuit 114 includes two parts located on both sides of each second pixel circuit column extending along the first direction on both sides of the first direction, that is, the pixel circuit where the second pixel circuit 113 is located In a column, the third pixel circuit 114 includes two parts distributed on both sides of the second pixel circuit 113 .
  • the embodiment of the present disclosure is not limited thereto.
  • the third pixel circuit may only be located on the lower side of each second pixel circuit column, that is, the upper side of the second pixel circuit has no Set up the third pixel circuit.
  • the upper side and the lower side are, for example, two sides along the longitudinal direction of the entire display area, and the top position is, for example, one end away from the driving IC.
  • the shape of the first display area is a rectangle and the shape of the second display area is a circle
  • some first pixel circuits will also be arranged on the upper edge of the second display area, and the transition area will also include such as The first switching area and the second switching area shown in FIG.
  • the upper edge of the first display area can be connected with the second display area.
  • the upper edge of the area is flush, and the first pixel circuit is no longer set on the upper side of the second display area, then the transition area only includes the first transition area shown in FIG. 2, and the second transition area is omitted. Further realization of narrow bezels.
  • the display substrate further includes a plurality of traces 300 extending along the first direction, the traces 300 do not pass through the second display area 120 , and the traces 300 are the same as the data lines 200 .
  • Layers are arranged, and at least one data line 200 is arranged between two adjacent wirings 300 ; along the direction perpendicular to the base substrate 100 , each wiring 300 only overlaps with the third pixel circuit 114 .
  • each of the traces 300 is connected to the third pixel circuit 114 overlapped therewith.
  • the wiring in the embodiment of the present disclosure is a wiring that only overlaps with the dummy pixel circuit.
  • the traces 300 include first traces 310, the number of the first traces 310 is the same as the number of the second sub-data lines 222, and each of the first traces 310 and a second sub-data line 222 are substantially located on the same line and A gap 230 is set between the two, and the same line is, for example, a straight line extending substantially along the second direction, and may also have certain bends at certain positions, but the main body portion, for example, more than 50% is located on the same straight line.
  • at least part of each of the first traces 310 and one of the second sub-data lines 222 are located on the same line with a space 230 therebetween.
  • a second sub data line 222 and the first trace 310 on the same line may be two disconnected parts of a metal line, and the length of the second sub data line 222 is smaller than the length of the first data line 210 , the load of the second sub data line 222 can be reduced.
  • the interval 230 between the second sub data line 222 and the first wiring 310 is located on the side of the first transfer area 2231 away from the second display area 120 , then the first wiring 310 does not affect the data signal transmitted on the second sub data line 222 .
  • each of the first traces 310 is connected to the third sub-pixel 114 that overlaps with it, and is configured to transmit electrical signals.
  • the floating of the first wiring can be avoided.
  • the second sub data line 222 is configured to transmit the data signal data, and the electrical signal transmitted on the first trace 310 is different from the signal transmitted on the second sub data line 222 .
  • the first trace 310 is configured to transmit a power supply voltage signal.
  • a power supply voltage signal may be a constant positive voltage VDD, but it is not limited thereto, and may also be other electrical signals, such as a reset voltage signal.
  • the wiring 300 further includes a second wiring 320 extending along the first direction, and the second wiring 320 includes parts located on both sides of the second display area 120 in the X direction and parts located in the second display area 120 is part of at least one side in the Y direction.
  • the second traces 320 located on both sides of the second display area 120 in the X direction a plurality of first data lines 210 are disposed between two adjacent second traces 320, or two adjacent second traces
  • a plurality of second sub data lines 222 are disposed between the lines 320 .
  • a plurality of first sub-data lines 221 are disposed between two adjacent second wirings 320 .
  • a plurality of first sub-lines 320 are disposed between two adjacent second traces 320 of the second traces 320 on either side.
  • Data line 221. FIG. 2 does not show the second wirings located on both sides of the second display area 120 in the Y direction.
  • each of the second traces 320 can transmit power voltage signals.
  • a plurality of second wirings 320 may be connected to one connection line extending along the X direction.
  • the second traces located on one side of the second display area may also not transmit electrical signals, that is, they are floating.
  • FIG. 4 is a schematic partial plan structure diagram of a display substrate provided according to another example of an embodiment of the present disclosure
  • FIG. 5 is a partial enlarged structural schematic diagram of the display substrate shown in FIG. 4 .
  • the examples shown in FIGS. 4 and 5 are different from the examples shown in FIGS. 2 and 3 in that:
  • the first pixel circuit 112 is connected to the first data line 210 , and the first data line 210 is not connected to the second sub-data line 222 .
  • each of the second sub-data lines 222 extends along the first direction and overlaps with the orthographic projection of each of the traces 300 on the straight line extending along the first direction.
  • each of the second sub-data lines 222 is basically a data line 200 running through the first display area 110, and each of the second sub-data lines 222 is not located on the same straight line as any of the traces 300, that is, the traces 300 only include A portion of a display area 110 and another portion extending to the edge of the second display area 120 .
  • the first data lines 210 and the first pixel circuits 112 located on one side of the second display area 120 in the Y direction and the first data lines 112 located on both sides of the second display area 120 in the X direction The pixel circuit 112 is connected.
  • each of the first sub-data lines 221 and one of the first data lines 210 are respectively located on both sides of the second display area 120 in the first direction, and are located on the same straight line.
  • the data line 211 and the first data line 210 on the same line are configured to transmit the same data signal.
  • the number of the first pixel circuits 112 connected to the first data lines 210 located on both sides of the second display area 120 in the X direction is M
  • the number of the first pixel circuits 112 connected to the first data lines 210 located on both sides of the second display area 120 in the X direction is M
  • the number of the first pixel circuits 112 connected to the first data line 210 on one side in the Y direction is a1.
  • each second data line 220 includes a first sub-data line 221 , a second sub-data line 222 , and a transition line 223 connecting the first sub-data line 221 and the second sub-data line 222 .
  • the patch cord 223 is located in a non-display area other than the first display area 110 and the second display area 120 .
  • the second data line 220 includes three parts connected in sequence, for example, the second sub-data line 222 , the transition line 223 and the first sub-data line 221 .
  • the number of second pixel circuits 113 connected to the second sub data lines 222 is a2
  • the number of first pixel circuits 112 connected to the first sub data lines 221 is a3.
  • data signals are loaded onto the first data lines 210 located on the left and right sides of the second display area 120 through a circuit board (not shown) located on the lower side of the first display area 110 to be supplied to the first data lines 210 connected to the M first pixel circuits 112; data signals are loaded onto the first sub-data lines 221 located on the lower side of the second display area 120 through the circuit board located on the lower side of the first display area 110 to be provided to the first sub-data line 221 located on the lower side of the second display area 120.
  • the sub-data lines 221 are connected to the a1 first pixel circuits 112; the data signals are loaded onto the second sub-data lines 222 located on the left and right sides of the second display area 120 through the circuit board located on the lower side of the first display area 110, so as to Provided to a2 second pixel circuits 113 connected to the second sub-data line 222, and then the data signal is transmitted to the first sub-data line 221 located on the upper side of the second display area 120 through the transition line 223 to be provided to the A3 first pixel circuits 112 connected to the first sub-data lines 221 and located on the lower side of the second display area 120 and the first sub-data lines 210 and the first sub-data lines 221 located in the same line It is configured to transmit the same data signal, and the data signal transmission method can be called dual drive.
  • the number M of the first pixel circuits connected to the first data lines of the plurality of first data lines that do not pass through the extension lines in the second display area is (a1+a2+a3), and the extension lines pass through the first data lines in the second display area.
  • the number a1 of first pixel circuits connected to the first data line in the second display area is less than M
  • the number N of pixel circuits connected to the second data line is (a2+a3), and N is less than M.
  • the data lines in the display substrate shown in FIG. 4 are driven in two ways.
  • the number of pixel circuits connected in series on the second data lines can be reduced, so that M is greater than or equal to N, Therefore, the load of the second data line is reduced to a certain extent, and when all the data lines input the same signal at the same time (ET lighting), the phenomenon of dark vertical stripes at the position of the second display area can be alleviated.
  • the number of pixel circuits connected to the second data line is reduced to reduce the load, and the burden of the driver IC can also be reduced when each data line inputs a corresponding data signal (module lighting).
  • each second sub data line 222 is not less than the length of the first data line 210 whose extension line does not pass through the second display area 120 .
  • the second sub data lines 222 , part of the first data lines 120 and part of the wirings 300 all penetrate through the first display area 110 .
  • the second sub-data line with this length is only connected to the second pixel circuit, not connected to any dummy pixel circuit, and at the same time , the second sub-data line is not connected to the first sub-data line through an adapter line, which can reduce the capacitance generated by the second sub-data line.
  • each patch cord 223 includes a first patch cable 223-1 and a second patch cable 223-2 connected to each other and arranged at different layers, and the first patch cable 223-1 and the second patch cable 223-1.
  • One of the wires 223 - 2 is connected to the second sub data line 222 and is located on a different layer from the second sub data line 222 .
  • the other one of the first transfer line 223 - 1 and the second transfer line 223 - 2 extends in a second direction intersecting with the first direction, and is connected to the second sub data line 212 on the same floor.
  • FIG. 6 is a schematic partial plan structure diagram of a display substrate provided according to another example of an embodiment of the present disclosure. As shown in FIG. 6 , the example shown in FIG. 6 is different from the example shown in FIG. 5 in that each of the second data lines 220 extends in the first direction, and each of the second data lines 220 is configured to be only connected to the first The two pixel circuits 113 are connected. As shown in FIG. 6
  • the shapes of the second display area 120 and the first display area 110 are the same, and one side edge (eg, the upper side edge) of the second display area 120 is the same as one side edge (eg, the upper side edge) of the first display area 110 side edges) are flush with each other, so that the first pixel circuits 112 are distributed only on three sides of the second display area 120 .
  • the second display area 120 is provided with the first pixel circuit 112 on one side in the Y direction, and the first pixel circuit 112 is not provided on the other side in the Y direction, so the second data line 220 is only It only needs to be configured to provide a data signal to the second pixel circuit 113, and it is not necessary to provide a data signal to the first pixel circuit.
  • all the third pixel circuits 114 overlapping the second data line 220 may be insulated from the second data line 220, but not limited thereto, the third pixel circuits overlapping the second data line In the circuit, part of the third pixel circuit may be connected to the second data line, and another part of the third pixel circuit may be insulated from the second data line.
  • FIG. 7 is an equivalent diagram of each pixel circuit in the display substrate shown in FIGS. 2 to 6 .
  • the second pixel circuit 113 is configured to drive the second light-emitting element 121 to emit light.
  • the structures of other pixel circuits, such as the first pixel circuit and the third pixel circuit, are the same as those of the second pixel circuit, but the third pixel circuit is not connected to the light-emitting element.
  • the display substrate further includes reset power signal lines, scan signal lines, power signal lines, reset control signal lines and light emission control signal lines on the base substrate.
  • the second pixel circuit 113 includes a data writing transistor T4, a driving transistor T3, a threshold compensation transistor T2, and a first reset control transistor T7.
  • the first pole of the threshold compensation transistor T2 is connected to the first pole of the driving transistor T3, the second pole of the threshold compensation transistor T2 is connected to the gate of the driving transistor T3;
  • the first pole of the first reset control transistor T7 is connected to the reset power supply signal line Connected to receive the reset signal Vinit, the second pole of the first reset control transistor T7 is connected to the second light emitting element 121;
  • the first pole of the data writing transistor T4 is connected to the second pole of the driving transistor T3.
  • the second pixel circuit 113 further includes a storage capacitor C, a first light emission control transistor T6 , a second light emission control transistor T5 and a second reset transistor T1 .
  • the gate of the data writing transistor T4 is electrically connected to the scan signal line to receive the scan signal Gate; the first pole of the storage capacitor C is electrically connected to the power signal line, and the second pole of the storage capacitor C is electrically connected to the gate of the drive transistor T3
  • the gate of the threshold compensation transistor T2 is electrically connected to the scan signal line to receive the compensation control signal;
  • the gate of the first reset transistor T7 is electrically connected to the reset control signal line to receive the reset control signal Reset(N+1);
  • the second reset The first pole of the transistor T1 is electrically connected to the reset power signal line to receive the reset signal Vinit, the second pole of the second reset transistor T1 is electrically connected to the gate of the driving transistor T3, and the gate of the second reset transistor T1 is connected to the reset control signal
  • the line is electrically connected to receive the
  • the scan signal and the compensation control signal may be the same, that is, the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 may be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines.
  • the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 may also be electrically connected to different signal lines respectively, that is, the gate of the data writing transistor T3 is electrically connected to the first scanning signal line, and the threshold compensation transistor
  • the gate of T2 is electrically connected to the second scan signal line, and the signals transmitted by the first scan signal line and the second scan signal line may be the same or different, so that the gate of the data writing transistor T3 and the threshold compensation transistor T2 It can be controlled separately, increasing the flexibility of controlling the pixel circuit.
  • the light emission control signals input to the first light emission control transistor T6 and the second light emission control transistor T5 may be the same, that is, the gate of the first light emission control transistor T6 and the gate of the second light emission control transistor T5 may be electrically connected to the same One signal line to receive the same signal, reducing the number of signal lines.
  • the gate of the first light-emitting control transistor T6 and the gate of the second light-emitting control transistor T5 may also be electrically connected to different light-emitting control signal lines, respectively, and the signals transmitted by the different light-emitting control signal lines may be the same or different. .
  • the reset control signals input to the first reset transistor T7 and the second reset transistor T1 may be the same, that is, the gate of the first reset transistor T7 and the gate of the second reset transistor T1 may be electrically connected to the same signal line to To receive the same signal, reduce the number of signal lines.
  • the gate of the first reset transistor T7 and the gate of the second reset transistor T1 may also be electrically connected to different reset control signal lines, respectively.
  • the signals on different reset control signal lines may be the same or different.
  • the second reset transistor T1 when the display substrate is working, in the first stage of screen display, the second reset transistor T1 is turned on to initialize the voltage of the N1 node; in the second stage of screen display, data data passes through the data write transistor. T4, the driving transistor T3 and the threshold compensation transistor T2 are stored at the N1 node; in the third light-emitting stage, the second light-emitting control transistor T5, the driving transistor T3 and the first light-emitting control transistor T6 are all turned on, and the light-emitting element emits light in forward conduction.
  • the pixel circuit in addition to the 7T1C (ie, seven transistors and one capacitor) structure shown in FIG. 7 , the pixel circuit may also be a structure including other numbers of transistors, such as a 7T2C structure , 6T1C structure, 6T2C structure, 8T1C structure, or 9T2C structure, which is not limited in this embodiment of the present disclosure.
  • FIG. 8 is a schematic partial plan structure diagram of a stacked structure of an active semiconductor layer, a first conductive layer, and a source-drain metal layer of a second pixel circuit according to an embodiment of the present disclosure.
  • the active semiconductor layer 3100 may be formed by patterning a semiconductor material.
  • the active semiconductor layer 3100 can be used to fabricate the above-mentioned second reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, second light-emitting control transistor T5, first light-emitting control transistor T6 and first reset control transistor Active layer of T7.
  • the active semiconductor layer 3100 includes an active layer pattern (channel region) and a doping region pattern (source-drain doping region) of each transistor.
  • the active layer may include an integrally formed low-temperature polysilicon layer, and the source region and the drain region may be conductive by doping or the like to achieve electrical connection of each structure.
  • the active semiconductor layer of each transistor is an overall pattern formed of p-silicon, and each transistor in the same pixel circuit includes a pattern of doped regions (ie, source regions and drain regions) and an active layer pattern, and different transistors The active layers are separated by doping structures.
  • the active semiconductor layer 3100 can be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that, the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • FIG. 10 is a schematic diagram of a partial cross-sectional structure of the pixel circuit shown in FIG. 8 taken along AA'.
  • a gate insulating layer 71 is provided on the side of the active semiconductor layer 3100 away from the base substrate 100
  • a first conductive layer is provided on the side of the gate insulating layer 71 away from the active semiconductor layer 3100 3200 (ie gate metal layer).
  • the first conductive layer 3200 may include the second electrode CC2 of the capacitor C, the scan signal line 52 extending along the X direction, the reset control signal line 51, the light emission control signal line 53, and a second reset transistor T1, a threshold compensation transistor T2, and a driving transistor.
  • T3 the gates of the data writing transistor T4, the second light emitting control transistor T5, the first light emitting control transistor T6 and the first reset control transistor T7.
  • the gate of the data writing transistor T3 may be the portion where the scan signal line 52 overlaps with the active semiconductor layer 3100 ; the gate of the first light emission control transistor T6 may be the light emission control signal The first part where the line 53 overlaps with the active semiconductor layer 3100 , and the gate of the second light-emitting control transistor T5 may be the second part where the light-emitting control signal line 53 overlaps with the active semiconductor layer 3100 .
  • the gate of the second reset transistor T1 is the first portion where the reset control signal line 51 overlaps with the active semiconductor layer 3100
  • the gate of the first reset control transistor T7 is the second portion where the reset control signal line 51 overlaps with the active semiconductor layer 3100 . part.
  • the threshold compensation transistor T2 may be a thin film transistor having a double gate structure.
  • the gate of the driving transistor T1 can be the second electrode CC2 of the capacitor C. As shown in FIG.
  • each dotted rectangle in FIG. 8 shows each portion where the active semiconductor layer 3100 and the first conductive layer 3200 overlap, that is, the channel region.
  • the active semiconductor layers on both sides of each channel region are conductorized by processes such as ion doping to serve as the first and second electrodes of the respective transistors.
  • the source and drain of the transistor may be symmetrical in structure, so the source and drain of the transistor may be indistinguishable in physical structure.
  • one of the gate electrodes is directly described as the first electrode and the other electrode is the second electrode.
  • the first and second poles are interchangeable as required.
  • the scan signal lines 52 , the reset control signal lines 51 and the light emission control signal lines 53 are arranged in the Y direction.
  • the scan signal line 52 is located between the reset control signal line 51 and the light emission control signal line 53 .
  • the second electrode CC2 of the capacitor C ie, the gate of the driving transistor T1 ) is located between the scan signal line 52 and the light emission control signal line 53 .
  • a source-drain metal layer 3300 is disposed on the side of the first conductive layer 3200 away from the base substrate, and the source-drain metal layer 3300 includes the data line 200 and the power signal line 54 extending along the Y direction.
  • the source-drain metal layer 3300 further includes a first connection part 55 , a second connection part 56 , a third connection part 57 and a fourth connection part 58 .
  • FIGS. 9 and 10 are schematic partial plan structure diagram of a stacked structure of an active semiconductor layer, a first conductive layer, a source-drain metal layer, and a second conductive layer of a second pixel circuit according to an embodiment of the present disclosure.
  • the first insulating layer 72 is provided on the side of the first conductive layer 3200 away from the base substrate 100
  • the second conductive layer 3400 is provided on the side of the second insulating layer 72 away from the base substrate 100
  • the second insulating layer 73 is provided on the side of the second conductive layer 3400 away from the base substrate 100
  • the source-drain metal layer 3300 is provided on the side of the second insulating layer 73 away from the base substrate 100 .
  • the second conductive layer 3400 includes the first pole CC1 of the capacitor C and along the first reset power signal line 81 and the second reset power signal line 82 .
  • the first pole CC1 of the capacitor C and the second pole CC2 of the capacitor C at least partially overlap to form the capacitor C.
  • the second conductive layer 3400 further includes a plurality of covering parts S, and each threshold compensation transistor T2 includes two gate electrodes and an active semiconductor layer located between the orthographic projections of the two gate electrodes on the active semiconductor layer 3100 .
  • the cover portion S overlaps with the active semiconductor layer 3100 between the two gate electrodes.
  • the second sub data line 222 is written to data in the second pixel circuit through the via hole H1 penetrating the gate insulating layer 71 , the first insulating layer 72 and the second insulating layer 73 .
  • the second pole of the transistor T2 is electrically connected, so that the second sub-data line 222 inputs a data signal for the second pixel circuit.
  • the power signal line 54 is electrically connected to the first electrode of the second light emitting control transistor T5 through a via hole penetrating the gate insulating layer, the first insulating layer and the second insulating layer.
  • the power signal lines 54 and the data lines 200 are alternately arranged in the X direction.
  • the power signal line 54 is electrically connected to the first electrode CC1 of the capacitor C through a via hole penetrating the second insulating layer.
  • the above-mentioned second insulating layer is an interlayer insulating layer.
  • a dual-gate threshold compensation transistor can reduce leakage current.
  • the active semiconductor layer between the two channels of the double-gate threshold compensation transistor T2 is in a floating state when the threshold compensation transistor T2 is turned off, and is easily affected by the surrounding line voltage and jumps, which will affect The threshold value compensates for the leakage current of the transistor T2, thereby affecting the light-emitting brightness.
  • the cover part S is designed to form a capacitor with the active semiconductor layer between the two channels of the threshold compensation transistor T2, and the cover part S can be connected to To the power supply signal line 54 to obtain a constant voltage, the voltage of the active semiconductor layer in the floating state can be kept stable.
  • the covering portion S overlaps with the active semiconductor layer between the two channels of the double-gate threshold compensation transistor T2, which can also prevent the active semiconductor layer between the two gates from being illuminated to change the characteristics, such as preventing this part
  • the voltage of the active semiconductor layer is changed to prevent crosstalk.
  • the second electrode of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3 through the first connection part 55 , and the first end of the first connection part 55 penetrates through the gate insulating layer.
  • the via holes of the first insulating layer and the second insulating layer are connected to the second pole of the threshold compensation transistor T2, and the second end of the first connection part 55 is connected to the driving transistor through the via holes penetrating the first insulating layer and the second insulating layer.
  • the first connection portion 55 overlaps with the first pole CC1 of the capacitor C. As shown in FIG.
  • the first electrode of the second reset transistor T1 is electrically connected to the first reset power supply signal line 81 through the second connection portion 56 , and one end of the second connection portion 56 is connected to the gate insulating layer, the first insulating layer and the second insulating layer through the
  • the via hole is connected to the first electrode of the second reset transistor T1, and the other end of the second connection portion 56 is connected to the first reset power signal line 81 through the via hole penetrating the second insulating layer.
  • the first pole of the first reset transistor T7 is electrically connected to the second reset power supply signal line 82 through the third connection part 57, and one end of the third connection part 57 is connected through the gate insulating layer, the first insulating layer and the second insulating layer.
  • the via hole is connected to the first electrode of the first reset transistor T7, and the other end of the third connection portion 57 is connected to the second reset power signal line 82 through the via hole penetrating the second insulating layer. Since the second display area has a large ITO capacitance (that is, the capacitance generated by the transparent wiring connecting the second light-emitting element and the second pixel circuit and the overlapping conductive layers, source-drain metal layers, etc.), the first The anode voltage climbing process of the second light-emitting element becomes very slow. For low gray scales, the turn-on time of the second light-emitting element is greatly delayed.
  • the first reset power supply signal line and the second reset power supply signal line are used. It is respectively connected with the first reset transistor and the second reset transistor, and the voltage of the first reset power supply signal is appropriately increased, which can improve the uneven brightness of the gray scale in the low second display area.
  • the fourth connection portion 58 is connected to the second electrode of the first light emission control transistor T6 through a via hole penetrating the gate insulating layer, the first insulating layer and the second insulating layer.
  • the structures of the first pixel circuit and the second pixel circuit are the same, and the positional relationship and connection relationship between the first pixel circuit and the data line, scan line, reset control signal line, light emission control signal line and power supply signal line are the same.
  • the relationship between the second pixel circuit and the corresponding signal line is the same, and is not repeated here.
  • the structures of the third pixel circuit and the second pixel circuit are the same, and the positional relationship and connection relationship between the third pixel circuit and the wiring, scan line, reset control signal line, light emission control signal line and power supply signal line are the same as those of the third pixel circuit.
  • the relationship between the two pixel circuits and the corresponding signal lines is the same, which is not repeated here.
  • FIG. 11 is a partial planar structural schematic diagram of a stacked structure of an active semiconductor layer, a first conductive layer, and a source-drain metal layer of a third pixel circuit according to an embodiment of the present disclosure.
  • the third pixel circuit overlaps with the second sub data line 222
  • the third pixel circuit overlapping with the second sub data line 222 overlaps with the second sub data line 222 shown in FIG. 8 .
  • the difference of the second pixel circuit is that the third pixel circuit overlapping the second sub data line 222 is insulated from the second sub data line 222 .
  • FIG. 12 is a schematic diagram of a partial cross-sectional structure of the pixel circuit shown in FIG. 11 taken along BB'.
  • the gate insulating layer 71 , the first insulating layer 72 and the second insulating layer are provided between the second sub data line 222 and the second electrode of the data writing transistor T2 in the third pixel circuit.
  • the layers 73 are not provided with via holes, so that the second sub-data line 222 and the second electrode of the data writing transistor T2 located directly below the second sub-data line 222 are provided in isolation.
  • an insulating layer (including a gate insulating layer, a first insulating layer and a second insulating layer) is provided between the film layer where the first electrode of the data writing transistor is located and the film layer where the data line is located, and the first pixel circuit and the second insulating layer are The first electrodes of the data writing transistors in the two pixel circuits are connected to the data lines through vias located in the insulating layer, and the second electrodes of the data writing transistors in at least part of the third pixel circuit overlapping the second data lines One pole and the second data line are insulated by an insulating layer.
  • At least one insulating layer between the third pixel circuit and the film layer where the second data line is located may not be provided with any via holes in the corresponding region of the third pixel circuit.
  • all insulating layers between the third pixel circuit and the second data line may not be provided with any via holes in the corresponding regions of the third pixel circuit.
  • FIG. 13 is a schematic diagram of the display area and a second data line of the display substrate shown in FIG. 2
  • FIG. 14 is an enlarged view of the area E1 shown in FIG. 13
  • FIG. 15 is an enlarged view of the area E2 shown in FIG. 13
  • 16 is an enlarged view of the area E3 shown in FIG. 13
  • FIG. 17 is an enlarged view of the area E4 shown in FIG. 13
  • 14 to 16 are schematic plan views schematically showing the stacked structure of the source-drain metal layer and the third conductive layer. As shown in FIG. 13 to FIG.
  • the display substrate further includes a third conductive layer located on the side of the source-drain metal layer away from the base substrate, and the third conductive layer includes an adapter line 223 located in the display area, a shield electrode SE, and a fifth connection part 59 and the second patch cord 223-2 outside the display area.
  • the shielding electrode SE is connected to the power signal line 54, so that the voltage on the shielding electrode SE is stable, which can play a shielding role and prevent the transparent wiring connecting the second light-emitting element and the second pixel circuit from affecting the gate of the driving transistor and the second pixel circuit. the potential of a connection.
  • the orthographic projection of the first connection portion on the base substrate falls within the orthographic projection of the shield electrode SE on the base substrate.
  • a third insulating layer may be provided between the third conductive layer and the source-drain metal layer, and the fifth connection portion 59 may be connected to the fourth connection portion 58 through a via hole in the third insulating layer. connected to realize the connection with the second pole of the first light emission control transistor T6.
  • each light-emitting element includes a first electrode, a light-emitting layer, and a second electrode (all not shown) that are stacked in layers, the first electrode is located on the side of the light-emitting layer facing the substrate, and the first electrode passes through the fifth connection portion and the first electrode.
  • the four connecting parts are connected to the second pole of the first light-emitting control transistor T6.
  • the patch cord 223 connected to one of the first sub-data lines 221 may overlap the second connection part 56 and the third connection part 57 .
  • the transition line 223 may overlap the reset control signal line.
  • the first connecting wire 223-1 can be formed by patterning a source-drain metal layer to save the number of film layers
  • the second connecting wire 223-2 can be formed by patterning a third conductive layer
  • the second connecting wire 223-2 can be formed by patterning a third conductive layer.
  • the second transition wire 223-1 is respectively connected to the first sub-data line 221 and the first transition wire 223-1 through two via holes H2 in the third insulating layer.
  • the second patch cord may be disposed on the same layer as the first sub-data line (or the second sub-data line), and be the same signal line, and the first patch cord and the first sub-data line may be in different layers set up.
  • the third insulating layer further includes a plurality of via holes H3, so that the third insulating layer is etched more uniformly.
  • FIG. 18 is a partial structure including the partial enlarged view shown in FIG. 16
  • FIG. 19 is a partial structure including the partial enlarged view shown in FIG. 17
  • seven first data lines 210 may be arranged between two adjacent second sub-data lines 222
  • seven first sub-data lines 221 may be arranged between two adjacent wirings 300 .
  • the first sub-data lines 221 located on the upper side of the second display area are connected to the second sub-data lines 222 located on the left and right sides of the second display area through the first transition lines 223-1 and the second transition lines 223-2 .
  • the display substrate includes a base substrate 100 , a plurality of pixel circuits 1000 on the base substrate 100 , and a plurality of data lines 200 .
  • the plurality of pixel circuits 1000 include a plurality of first type pixel circuits 1001 and a plurality of second type pixel circuits 1002, the first type pixel circuits 1001 are electrically connected to the data lines 200, and the second type pixel circuits 1002 1002 is insulated from the data line 200 .
  • the display substrate provided by the embodiment of the present disclosure, by insulating the second-type pixel circuits from the data lines, the number of pixel circuits connected to the data lines can be reduced to reduce the load, thereby alleviating the phenomenon of dark vertical stripes in the display area and improving the display performance. Display quality of the substrate.
  • the first type pixel circuit 1001 is electrically connected to the overlapping data line 200
  • the second type pixel circuit 1002 is electrically connected to the overlapping data line 200 . insulation.
  • the first type pixel circuit 1001 is configured to drive a light-emitting element (eg, the first light-emitting element 111 or the second light-emitting element 121 ) connected thereto to emit light, and the first light-emitting element 111 or the second light-emitting element 121 is configured to emit light.
  • the two-type pixel circuit 1002 is a first dummy pixel circuit.
  • the first dummy pixel circuit is a pixel circuit not connected to any light-emitting element.
  • the first type pixel circuit 1001 includes a first pixel circuit 112 and a second pixel circuit 113, the first pixel circuit 112 and the light-emitting element (the first pixel circuit 112) connected thereto.
  • the light-emitting element 111) overlaps in the direction perpendicular to the base substrate 100, and the second pixel circuit 113 and the light-emitting element (second light-emitting element 121) connected thereto are perpendicular to the base substrate 100.
  • the directions do not overlap; the first type pixel circuit 1001 further includes a second dummy pixel circuit 1003 .
  • the second dummy pixel circuit 1003 is a pixel circuit that is not connected to any light-emitting element.
  • the second-type pixel circuits 1002 and part of the first-type pixel circuits 1002 are located in the same column.
  • the second type pixel circuit 1002 and the second pixel circuit 113 are located in the same column.
  • the pixel circuit 1000 includes a data writing transistor T4, the data writing transistor T4 includes a first electrode, a second electrode and a gate, and the data writing transistor T4 has a An insulating layer is provided between the film layer where the first electrode is located and the film layer where the data line 200 is located, and the first electrode of the data writing transistor T4 of the first type pixel circuit 1001 is located on the insulating layer (for example, The via hole H1 in the gate insulating layer 71, the first insulating layer 72 and the second insulating layer 73) is connected to the corresponding data line 200; the data writing transistor T4 of the second type pixel circuit 1002
  • the first electrode and the data line 200 are insulated by the insulating layer (eg, the gate insulating layer 71 , the first insulating layer 72 and the second insulating layer 73 ).
  • the first type of pixel circuit in this embodiment includes the first pixel circuit, the second pixel circuit and part of the third pixel circuit (the third pixel circuit connected to the wiring) in the above-mentioned embodiment, and the second type of pixel circuit includes another A part of the third pixel circuit (the pixel circuit that is not connected to the traces or the data lines).
  • the structures of the base substrate, data lines, pixel circuits, and light-emitting elements in the embodiments of the present disclosure have the same features as the structures of the base substrate, data lines, pixel circuits, and light-emitting elements in the above-mentioned embodiments, which will not be repeated here. .
  • Another embodiment of the present disclosure provides a display device including any of the above-mentioned display substrates.
  • the display device provided by the embodiment of the present disclosure may be an organic light emitting diode display device.
  • the display device provided by the embodiment of the present disclosure, by setting at least a part of the third pixel circuit overlapping the second data line to not be connected to the second data line, the number of pixel circuits connected to the second data line can be reduced. In order to reduce the load, the phenomenon of dark vertical stripes appearing in the second display area is alleviated, and the display quality of the display device is improved.
  • the display device may further include a cover plate on the display side of the display substrate.
  • the display device may further include a functional component located on a side of the base substrate away from the light-emitting element, and the functional component is directly opposite to the second display area.
  • functional components include camera modules (eg, front camera modules), 3D structured light modules (eg, 3D structured light sensors), time-of-flight 3D imaging modules (eg, time-of-flight sensors), infrared sensors At least one of a measurement module (eg, an infrared sensing sensor) and the like.
  • camera modules eg, front camera modules
  • 3D structured light modules eg, 3D structured light sensors
  • time-of-flight 3D imaging modules eg, time-of-flight sensors
  • infrared sensors At least one of a measurement module (eg, an infrared sensing sensor) and the like.
  • the front camera module is usually enabled when the user takes a selfie or makes a video call, and the pixel display area of the display device displays the image obtained by the selfie for the user to watch.
  • the front camera module includes, for example, a lens, an image sensor, an image processing chip, and the like.
  • the optical image generated by the scene through the lens is projected onto the surface of the image sensor (the image sensor includes CCD and CMOS) and converted into an electrical signal, which is converted into a digital image signal after analog-to-digital conversion by the image processing chip, and then sent to the processor for processing.
  • An image of the scene is output on the monitor.
  • 3D structured light sensors and Time of Flight (ToF) sensors can be used for face recognition to unlock display devices, etc.
  • the functional component 20 may only include a camera module to realize the function of taking a selfie or a video call; for example, the functional component 20 may further include a 3D structured light module or a time-of-flight 3D imaging module to realize face recognition unlocking, etc., This embodiment includes but is not limited to this.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a notebook computer, and a navigator with an under-screen camera, and this embodiment is not limited thereto.

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Abstract

一种显示基板以及显示装置。显示基板包括第一显示区和第二显示区，第一显示区位于第二显示区的周边，第一显示区包括第一发光元件、第一像素电路、第二像素电路以及第三像素电路，第一像素电路与第一发光元件连接；第二显示区包括第二发光元件，第二像素电路与第二发光元件连接，第三像素电路为虚设像素电路。显示基板还包括第一数据线和第二数据线，第一数据线被配置为与第一像素电路连接，第二数据线被配置为至少与第二像素电路连接。沿垂直于衬底基板的方向，与第二数据线交叠的第三像素电路的至少部分与第二数据线绝缘设置。通过减少第二数据线连接的像素电路的数量以降低负载，可以缓解第二显示区出现暗竖条纹的现象。

Description

显示基板以及显示装置 技术领域
本公开至少一个实施例涉及一种显示基板以及显示装置。
背景技术
随着人们对显示产品视觉效果的不断追求，窄边框甚至全屏显示成为当前有机发光二极管(OLED)显示产品发展的新趋势。前置摄像头是设计全面屏的关键，为了达到更高的屏占比，陆续出现了具有刘海屏、挖孔屏等屏幕的显示产品，这几种全面屏形态通过牺牲手机外观而提高了屏占比。由此，屏下摄像头的设计既能保证手机外观，又可以提高屏占比。
发明内容
本公开的至少一实施例提供一种显示基板以及显示装置。
本公开的至少一实施例提供一种显示基板，包括衬底基板以及位于衬底基板上的多条数据线。显示基板包括第一显示区和第二显示区，所述第一显示区位于所述第二显示区的周边，所述第一显示区包括多个第一发光元件、多个第一像素电路、多个第二像素电路以及多个第三像素电路，所述多个第一像素电路与所述多个第一发光元件一一对应连接，所述第二显示区包括多个第二发光元件，所述多个第二像素电路与所述多个第二发光元件一一对应连接，所述第三像素电路为虚设像素电路；多条数据线不经过所述第二显示区，其中，所述多条数据线包括多条第一数据线和多条第二数据线，各所述第一数据线被配置为与所述第一像素电路连接，各所述第二数据线被配置为至少与所述第二像素电路连接。沿垂直于所述衬底基板的方向，所述多个第三像素电路的部分与所述多条第二数据线交叠，与所述第二数据线交叠的所述第三像素电路中的至少部分与所述第二数据线绝缘设置。
例如，根据本公开的实施例，与所述第二数据线交叠的各所述第三像素电路与所述第二数据线绝缘设置。
例如，根据本公开的实施例，各所述第一数据线沿第一方向延伸，所述多条第一数据线中延长线不经过所述第二显示区的所述第一数据线被配置为给M个所述第一像素电路传输数据信号，各所述第二数据线被配置为给N个像素电路传输信号，且M≥N，所述N个像素电路至少包括所述第二像素电路。
例如，根据本公开的实施例，所述第二数据线包括沿所述第一方向延伸的第一子数据线和第二子数据线，以及连接所述第一子数据线和所述第二子数据线的转接线；所述第一子数据线、所述第二子数据线以及所述第一数据线同层设置，所述第一子数据线被配置为与所述第一像素电路连接，所述第二子数据线被配置为与所述第二像素电路连接。
例如，根据本公开的实施例，显示基板还包括：多条走线，沿所述第一方向延伸，且不经过所述第二显示区。所述多条走线与所述多条第一数据线同层设置，且相邻两条走线之间设置有至少一条数据线；沿垂直于所述衬底基板的方向，各所述走线仅与所述第三像素电路交叠。
例如，根据本公开的实施例，所述多条走线包括多条第一走线，所述第一走线的数量与所述第二子数据线的数量相同，一条所述第一走线与一条第二子数据线的至少部分大致位于同一直线上且两者之间设置有间隔；转接区，包括所述多条转接线。所述转接区包括位于所述第二显示区在所述第一方向的一侧的第一转接区，所述第一转接区中的所述转接线沿与所述第一方向相交的第二方向延伸且与所述第一数据线位于不同层，所述间隔位于所述第一转接区远离所述第二显示区的一侧，所述第一走线和至少部分所述第三像素电路交叠。
例如，根据本公开的实施例，所述第一走线上和所述第二子数据线被配置为传输不同的电信号。
例如，根据本公开的实施例，所述第一走线被配置为传输电源电压信号。
例如，根据本公开的实施例，所述转接区还包括位于所述第二显示区在所述第一方向的另一侧的第二转接区，所述第二转接区位于所述第一显示区和所述第二显示区以外的非显示区。
例如，根据本公开的实施例，所述第二转接区的各所述转接线包括彼此连接且不同层设置的第一转接线和第二转接线，所述第一转接线和所述第二转接线之一与所述第二子数据线连接，且与所述第二子数据线位于不同层。
例如，根据本公开的实施例，各所述第二数据线中，两条第一子数据线与同一条第二子数据线连接，所述两条第一子数据线分别位于所述第二显示区在所述第一方向的两侧，且所述两条第一子数据线的至少部分大致位于同一直线上。
例如，根据本公开的实施例，一所述第二子数据线沿所述第一方向延伸，且与一所述走线在沿所述第一方向延伸的直线上的正投影有交叠。
例如，根据本公开的实施例，所述转接线位于所述第一显示区和所述第二显示区以外的非显示区。
例如，根据本公开的实施例，各所述转接线包括彼此连接且不同层设置的第一转接线和第二转接线，所述第一转接线和所述第二转接线之一与所述第二子数据线连接，且与所述第二子数据线位于不同层。
例如，根据本公开的实施例，所述第二子数据线的长度不小于所述多条第一数据线中延长线不经过所述第二显示区的所述第一数据线的长度。
例如，根据本公开的实施例，所述第一子数据线与一条第一数据线分别位于所述第二显示区在所述第一方向的两侧，且大致位于同一直线上，各所述第一子数据线和与其大致位于同一直线上的所述第一数据线被配置为传输相同的数据信号。
例如，根据本公开的实施例，所述第一转接线和所述第二转接线中的另一个沿与所述第一方向相交的第二方向延伸，且与所述第二子数据线位于同一层。
例如，根据本公开的实施例，所述第二数据线沿所述第一方向延伸，且所述第二数据线被配置为仅与所述第二像素电路连接。
例如，根据本公开的实施例，所述第一显示区包括的多个像素电路沿所述第一方向和第二方向阵列排布，所述多个第二像素电路位于所述第二显示区在所述第二方向的两侧。
例如，根据本公开的实施例，沿所述第一方向排布的所述第二像素电路所在像素电路列包括所述第三像素电路，且所述像素电路列中的所述第三像素电路与所述第二数据线交叠。
例如，根据本公开的实施例，所述多个第三像素电路包括沿所述第一方向延伸且沿第二方向排列的多个第三像素电路列，所述多个第三像素电路列的至少部分位于所述第二显示区在所述第一方向的至少一侧。
例如，根据本公开的实施例，所述多个第三像素电路列还包括位于所述第二显示区在所述第二方向的两侧的部分。
例如，根据本公开的实施例，所述像素电路包括数据写入晶体管，所述数据写入晶体管包括第一极、第二极以及栅极，所述数据写入晶体管的第一极所在膜层与所述数据线所在膜层之间设置有绝缘层，所述第一像素电路和所述第二像素电路中的所述数据写入晶体管的第一极通过位于所述绝缘层中的过孔与所述数据线连接，与所述第二数据线交叠的所述第三像素电路中的至少部分中所述数据写入晶体管的第一极与所述第二数据线被所述绝缘层绝缘。
本公开至少一实施例提供一种显示基板，包括衬底基板、位于所述衬底基板上的多个像素电路以及多条数据线。所述多个像素电路包括多个第一类型像素电路和多个第二类型像素电路，所述第一类型像素电路与所述数据线电连接，所述第二类型像素电路与所述数据线绝缘设置。
例如，根据本公开的实施例，所述第一类型像素电路和与其交叠的所述数据线电连接，所述第二类型像素电路和与其交叠的所述数据线绝缘。
例如，根据本公开的实施例，所述第一类型像素电路的至少部分被配置为驱动与其连接的发光元件发光，所述第二类型像素电路为第一虚设像素电路。
例如，根据本公开的实施例，所述第一类型像素电路包括第一像素电路和第二像素电路，所述第一像素电路和与其连接的所述发光元件在垂直于所述衬底基板的方向有交叠，所述第二像素电路和与其连接的所述发光元件在垂直于所述衬底基板的方向没有交叠；所述第一类型像素电路还包括第二虚设像素电路。
例如，根据本公开的实施例，所述第二类型像素电路和部分所述第一类型像素电路位于同一列。
例如，根据本公开的实施例，所述第二类型像素电路和所述第二像素电路位于同一列。
例如，根据本公开的实施例，所述像素电路包括数据写入晶体管，所述数据写入晶体管包括第一极、第二极以及栅极，所述数据写入晶体管的第一极所在膜层与所述数据线所在膜层之间设置有绝缘层，所述第一类型像素电路的所述数据写入晶体管的第一极通过位于所述绝缘层中的过孔与相应的所述数据线连接；所述第二类型像素电路的所述数据写入晶体管的第一极与所述数据线被所述绝缘层绝缘。
本公开至少一实施例提供一种显示装置，包括上述任一显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种具有屏下摄像头的显示装置中的显示基板的局部平面结构示意图；
图2为根据本公开实施例的一示例提供的显示基板的局部平面结构示意图；
图3为图2所示的显示基板的局部放大结构示意图；
图4为根据本公开实施例的另一示例提供的显示基板的局部平面结构示意图；
图5为图4所示的显示基板的局部放大结构示意图；
图6为根据本公开实施例的另一示例提供的显示基板的局部平面结构示意图；
图7为图2至图6所示显示基板中各像素电路的等效图；
图8为根据本公开实施例提供的第二像素电路的有源半导体层、第一导电层以及源漏金属层的层叠结构的局部平面结构示意图；
图9为根据本公开实施例提供的第二像素电路的有源半导体层、第一导电层、源漏金属层以及第二导电层的层叠结构的局部平面结构示意图；
图10为图8所示像素电路中沿AA’所截的部分截面结构示意图；
图11为根据本公开实施例提供的第三像素电路的有源半导体层、第一导电层以及源漏金属层的层叠结构的局部平面结构示意图；
图12为图11所示像素电路中沿BB’所截的部分截面结构示意图；
图13为图2所示的显示基板的显示区和一条第二数据线的示意图；
图14为图13所示的区域E1的放大图；
图15为图13所示的区域E2的放大图；
图16为图13所示的区域E3的放大图；
图17为图13所示的区域E4的放大图；
图18为包括图16所示局部放大图的部分结构；以及
图19为包括图17所示局部放大图的部分结构。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附 图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
屏下摄像头(Full display camera，FDC)指前置摄像头位于屏幕下方但并不影响屏幕显示功能，不使用前置摄像头的时候，相机上方的屏幕仍可以正常显示图像。从外观上看，屏下摄像头不会有任何相机孔，真正的达到了全面屏显示效果。
图1为一种具有屏下摄像头的显示装置中的显示基板的局部平面结构示意图。如图1所示，显示基板包括衬底基板10，显示基板包括用于正常显示的第一显示区11以及用于设置摄像头的第二显示区12。该第一显示区11可以位于第二显示区12的至少一侧。例如，第一显示区11围绕第二显示区12，第二显示区12为透光显示区，第一显示区11为不透光仅用于显示的显示区。
图1所示显示基板中的第一显示区11包括第一发光元件以及驱动该第一发光元件发光的第一像素电路，第二显示区12包括第二发光元件，驱动第二显示区12中的第二发光元件发光的第二像素电路位于第一显示区以提高第二显示区12的光透过率，即通过发光元件和像素电路分离设置的方式来提高第二显示区12的光透过率。例如，多个第二像素电路可以间隔分布于多个第一像素电路之间。例如，第二发光元件可以通过透明走线与第二像素电路连接。例如，第二显示区12可以为整个显示区中没有设置像素电路的孔区。例如，第一显示区11和第二显示区12中设置的发光元件的密度可以相同，也可以不同。
如图1所示，显示基板包括位于衬底基板10上的多条数据线20。具有屏下摄像头的显示装置中，多条数据线的设置方式包括在第二显示区内绕线以及在第二显示区外绕线两种方式，由于受到第二显示区的空间大小的限制，图1所示显示基板根据全压缩像素电路方案设计，采用在第二显示区12外进行数据线绕线方式设置数据线。该显示基板中，第一显示区包括多个第一像素电路列和多个第二像素电路列，第二像素电路所在第二像素电路列除了包括第二像素电路外，还包括不与任何发光元件连接的虚设像素电路；第一显示区还包括多个虚设像素电路列，相邻两个虚设像素电路列之间设置至少一个第一像素电路列。上述全压缩像素电路指在不减少整体显示区(包括第一显示区和第二显示区)的像素密度的情况下，将整体显示区中的多个像素电路列在X方向上进行压缩(例如减小每个像素电路沿X方向的尺寸)以增加沿X方向排列的像素电路的数量，新增加的像素电路列包括用于与第二显示区的第二发光元件连接的第二像素电路列，以及不与任何发光元件连接的虚设像素电路列。
如图1所示，多条数据线20包括仅与第一像素电路连接的数据线21以及至少与第二像素电路连接的数据线22。数据线21为沿Y方向延伸的数据线。例如，各数据线20可以采用单路驱动，部分数据线20在第二显示区12的边缘断开，即部分数据线20包括位于第二显示区12上下两侧的两部分数据线22-1，这两部分数据线22-1均与第一像素电路连接，这两部分数据线22-1可以通过转接线22-3以及与第二像素电路连接的数据线22-2实现电连接，以使两部分数据线22-1传输相同的数据信号。由此，数据线22例如包括5部分，这5部分依次为数据线22-1、转接线22-3、数据线22-2、转接线22-3以及数据线22-1。上述两部分数据线22-1连接的第一像素电路的个数分别为a1和a3，数据线22-2连接的第二像素电路以及虚设像素电路的数量分别为a2以及(a4+a5)个，即数据线22连接的像素电路的数量为b，b＝a1+a2+a3+a4+a5。a1至a5表示图中对应位置的数据线连接的像素电路的数量。
在研究中，本申请的发明人发现：数据线21的延长线不经过第二显示区12，与数据线21连接的像素电路的数量为a(a＝a1+a2+a3)。为了降低与第二像素电路连接的数据线22-2的负载(data loading)，数据线22-2所在金属线在位于转接线22-3远离第二显示区12一侧处断开为两部分，该金属线包括数据线22-2以及走线30，数据线22-2与走线30之间设置有间隔23以实现两者的绝缘。走线30与虚设像素电路连接。为了避免走线30的浮置(floating)，可以将走线30接入电源电压信号(VDD)。然而，与上述数据线22连接的像素电路的数量b大于与数据线21连接的像素电路的数量a，会导致数据线22的负载偏大，例如在所有数据线同时输入相同信号时(ET点灯)，第二显示区位置处容易出现暗竖条纹，影响显示装置的显示质量。
本公开的实施例提供一种显示基板以及显示装置。显示基板包括衬底基板以及位于衬底基板上的多条数据线。显示基板包括第一显示区和第二显示区，第一显示区位于第二显示区的周边，第一显示区包括多个第一发光元件、多个第一像素电路、多个第二像素电路以及多个第三像素电路，多个第一像素电路与多个第一发光元件一一对应连接，第二显示区包括多个第二发光元件，多个第二像素电路与多个第二发光元件一一对应连接，第三像素电路为虚设像素电路；多条数据线不经过第二显示区，多条数据线包括多条第一数据线和多条第二数据线，各第一数据线被配置为仅与第一像素电路连接，各第二数据线被配置为至少与第二像素电路连接。沿垂直于衬底基板的方向，多个第三像素电路的部分与多条第二数据线交叠，与第二数据线交叠的第三像素电路中的至少部分与第二数据线绝缘设置。本公开实施例提供的显示基板中，通过将与第二数据线交叠的至少部分第三像素电路设置为与第二数据线不连接，可以减少第二数据线连接的像素电路的数量以降低负载，从而缓解第二显示区出现暗竖条纹的现象，提高显示基板的显示质量。
下面结合附图对本公开实施例提供的显示基板以及显示装置进行描述。
图2为根据本公开实施例的一示例提供的显示基板的局部平面结构示意图，图3为图2所示的显示基板的局部放大结构示意图。如图2和图3所示，显示基板包括衬底基板100 以及位于衬底基板100上的多条数据线200。显示基板包括第一显示区111和第二显示区112，第一显示区111位于第二显示区112的周边。例如，第一显示区111围绕第二显示区112，即第二显示区112可以被第一显示区111包围。当然，本公开实施例不限于此，第二显示区112也可以设置在其他位置处，第二显示区112的设置位置可根据需要而定，例如，第二显示区112可以位于整体显示区(包括第一显示区和第二显示区的显示区)的顶部正中间位置处，也可以位于整体显示区的左上角位置或右上角位置处。图2示意性的示出第一显示区111的形状为矩形，第二显示区112的形状为圆形，但不限于此，第二显示区112的形状还可以为矩形、椭圆形等规则形状或者不规则形状，第一显示区111的形状还可以为圆形、六边形等规则形状或者不规则形状。
如图2和图3所示，第一显示区110包括多个第一发光元件111、多个第一像素电路112、多个第二像素电路113以及多个第三像素电路114，多个第一像素电路112与多个第一发光元件111一一对应连接，以驱动多个第一发光元件111发光；第二显示区120包括多个第二发光元件121，多个第二像素电路113与多个第二发光元件121一一对应连接，以驱动多个第二发光元件121发光，第三像素电路114为虚设像素电路。上述虚设像素电路指不与任何发光元件连接的像素电路。第二显示区仅设置透明的第二发光元件，而没有设置非透明的像素电路，该第二显示区可以作为屏下摄像区，既可以具有较高的光透过率以实现摄像功能，又可以通过与其他区域的像素电路连接而实现发光，不影响屏幕的显示功能。
例如，沿垂直于衬底基板100的方向，至少部分第一像素电路112和与其连接的第一发光元件111交叠；第二像素电路113和与其连接的第二发光元件121没有交叠。或者，例如，沿垂直于衬底基板100的方向，第一像素电路112和与其连接的第一发光元件111之间的平均距离小于第二像素电路113和与其连接的第二发光元件121之间的平均距离。平均距离例如为一列像素电路的驱动晶体管到与其连接的发光元件中心之间的距离的平均值。例如，第二像素电路113可以通过透明走线400与相应的第二发光元件121连接；第二像素电路113和第三像素电路114均不与发光元件交叠。例如，第二像素电路113可以仅位于第二显示区120沿X方向的两侧，第一像素电路112既包括位于第二显示区120沿X方向的两侧的部分，又包括位于第二显示区120沿Y方向的两侧的部分。
例如，沿第一方向排布的第二像素电路113所在像素电路列包括第三像素电路114，且该像素电路列中的第三像素电路114与第二数据线220交叠或电连接。例如，第二像素电路113所在像素电路列(例如以沿Y方向排列的多个像素电路为一个像素电路列)除包括第二像素电路113外，还包括第三像素电路114。例如，为了保证像素电路的均匀性，第二像素电路113所在像素电路列包括的像素电路的数量可以与第一像素电路112所在像素电路列(除像素电路列连接的数据线经过第二显示区120的像素电路列以外的其他像素电路列)包括的像素电路的数量大致相同。但是第一像素电路112所在像素电路列中仅包括第一像素电路112，而第二像素电路113所在像素电路列包括第二像素电路113和第三像素电路114。例如，相邻第二像素电路所在两个像素电路列之间可以设置至少一个第一像素电路列。
例如，第一显示区110包括的多个像素电路沿第一方向和第二方向阵列排布，多个第二像素电路113位于第二显示区120在第二方向的两侧。
例如，显示基板还包括多个第三像素电路列(图2和图3没有示出，各第三像素电路列仅包括第三像素电路)，相邻第三像素电路列之间设置有至少一个第一像素电路列。例如，第三像素电路列包括分布在第二显示区120沿X方向的两侧的部分，第三像素电路列还可以分布在第二显示区120沿Y方向的两侧的另一部分。
如图2和图3所示，多条数据线200不经过第二显示区120以防止影响第二显示区120的透光率。具有屏下摄像头的显示装置中，多条数据线的设置方式包括在第二显示区内绕线以及在第二显示区外绕线两种方式，由于受到第二显示区的空间大小的限制，本公开实施例提供的显示基板根据全压缩像素电路方案设计，采用在第二显示区120外进行数据线绕线方式设置数据线。多条数据线200包括多条第一数据线210和多条第二数据线220，各第一数据线210被配置为仅与第一像素电路112连接，各第二数据线220被配置为至少与第二像素电路113连接。
例如，如图2和图3所示，位于第二显示区120在X方向两侧的多条第二数据线220中，相邻第二数据线220之间可以设置多条第一数据线210。例如2～10条(图3示意性的示出2条第一数据线)，本公开实施例对此不作限制，可根据实际产品需要进行设置。例如，位于第二显示区120在X方向两侧的多条第二数据线220可以均匀分布，但不限于此。例如，根据布线需求，第二数据线可以非均匀分布，相邻第二数据线之间设置的第一数据线的数量可以不同。
如图2和图3所示，沿垂直于衬底基板100的方向，多个第三像素电路114的部分与多条第二数据线220交叠(例如与第二数据线交叠且连接的第三像素电路可以通过垂直基板的过孔实现电连接)，与第二数据线220交叠的第三像素电路114中的至少部分与第二数据线220绝缘设置(例如相比正常像素电路，像素电路用于与数据线电连接的至少部分过孔处并不开设过孔，由绝缘层隔绝，而使得该像素电路并不能与该数据线电连接以实现像素电路的功能)。图3所示数据线200和与其交叠的像素电路之间设置黑点则表示两者具有连接关系，数据线200和与其交叠的像素电路之间没有设置黑点则表示两者绝缘设置，即没有连接关系。
本公开实施例提供的显示基板中，通过将与第二数据线交叠的至少部分第三像素电路设置为与第二数据线绝缘设置，可以减少第二数据线连接的像素电路的数量以降低负载，从而，在所有数据线同时输入相同信号时(ET点灯)，可以缓解第二显示区出现暗竖条纹的现象，提高显示基板的显示质量。此外，减少第二数据线连接的像素电路的数量以降低负载，还可以在每条数据线输入相应的数据信号(模组点灯)时，减轻驱动IC的负担。
例如，如图2和图3所示，与第二数据线220交叠的各第三像素电路114与第二数据线220绝缘设置，即与第二数据线220交叠的所有第三像素电路114均与第二数据线220不连接，则与第二数据线220连接的像素电路均为被配置为驱动发光元件发光的像素电路， 从而极大减少了第二数据线连接的像素电路的数量，进而降低了第二数据线的负载。
例如，如图2和图3所示，各第一数据线210沿第一方向延伸，例如图中示意性的示出第一方向为Y方向，但不限于此，也可以为图中所示的X方向。多条第一数据线中延长线不经过所述第二显示区120的第一数据线210被配置为给M个第一像素电路112传输数据信号，例如该第一数据线210可以贯穿第一显示区110。各第二数据线220被配置为给N个像素电路传输信号，且M≥N，所述N个像素电路至少包括第二像素电路。这里的N个像素电路指与第二数据线220连接的像素电路，包括后续描述的与第二子数据线连接的第二像素电路以及与第一子数据线连接的第一像素电路，或者仅包括第二像素电路。
例如，在图2和图3所示的示例中，第一数据线210仅包括位于第二显示区120在X方向的两侧的数据线，则在第二数据线220不与虚设像素电路连接时，与第二数据线220连接的像素电路的数量N不大于与第一数据线210连接的像素电路的数量M。例如，与第二数据线220连接的像素电路的数量N等于与第一数据线210连接的第一像素电路111的数量M。
例如，如图2和图3所示，各第二数据线220包括沿第一方向延伸的第一子数据线221和第二子数据线222，以及连接第一子数据线221和第二子数据线222的转接线223。
例如，如图2和图3所示，第一子数据线221、第二子数据线222以及第一数据线210同层设置，第一子数据线221被配置为与第一像素电路112连接，第二子数据线222被配置为与第二像素电路113连接。
例如，第二数据线220包括的第一子数据线221为延伸至第二显示区120边缘的数据线。图2和图3所示的示例中，与位于第二显示区120在X方向两侧的第一像素电路112连接的数据线200为第一数据线210，与位于第二显示区120在Y方向两侧的第一像素电路112连接的数据线200为第二数据线220中的第一子数据线221，与第二像素电路113连接的数据线200为第二数据线220中的第二子数据线222。
例如，图2和图3示意性的示出各第二数据线220中的第一子数据线221包括分布于第二显示区120在Y方向上的两侧的两部分，但不限于此，各第二数据线包括的第一子数据线也可以仅位于第二显示区的一侧，例如第二显示区的上方(以Y方向的箭头所指方向为向上)没有设置第一像素电路以及第一子数据线。
例如，如图2和图3所示，显示基板包括转接区2230，多条转接线223设置在转接区2230中，转接区2230包括位于第二显示区120在第一方向的一侧的第一转接区2231，转接区2230还包括位于第二显示区120在第一方向的另一侧的第二转接区2232。
例如，如图2和图3所示，第一转接区2231中的转接线223沿与第一方向相交的第二方向延伸。图中示意性的示出第二方向为X方向，但不限于此，第一方向和第二方向可以互换。图2和图3示意性的示出第一方向和第二方向垂直，但不限于此，第一方向和第二方向也可以不垂直。
例如，如图2和图3所示，第一转接区2231中的转接线223与第一子数据线221位于 不同层，例如，转接线223可以位于第一子数据线221远离衬底基板100的一侧。
例如，如图2和图3所示，第二转接区2232中的转接线223可以包括彼此连接且不同层设置的第一转接线223-1和第二转接线223-2，第一转接线223-1和第二转接线223-2之一与第二子数据线222连接，且与第二子数据线222位于不同层。
例如，如图3所示，各转接线223包括两条第二转接线223-2以及连接两条第二转接线223-2的一条第一转接线223-1，两条第二转接线223-2之一与第二子数据线222连接，两条第二转接线223-2的另一条与第一子数据线221连接。例如，第一转接线223-1沿第二方向延伸，第二转接线223-2沿第一方向延伸。例如，第一转接线223-1可以与位于第一转接区2231中的转接线223大致平行。
例如，第二转接线223-2与第二子数据线222位于不同层。例如，第一转接线223-1可以与第二子数据线222位于同一层。当然，本公开实施例不限于此，第一转接线可以与第二子数据线不同层，第二转接线可以与第二子数据线同层。
例如，如图2和图3所示，第二数据线220包括依次连接的五个部分，例如第一子数据线221、转接线223、第二子数据线222、转接线223以及第一子数据线221。例如，上述两条第一子数据线221分别通过两部分转接线223与同一条连续的第二子数据线222连接，这两条第一子数据线221分别位于第二显示区120在第一方向的两侧，且两条第一子数据线221位于同一直线上。本公开实施例中，两条数据线位于同一直线指这两条数据线大致位于同一直线，例如两条数据线的50％以上位于同一直线，或者这两条数据线在第二方向上偏移最大距离小于5微米，或者3微米等。
例如，数据信号通过位于第一显示区110下侧的电路板(未示出)加载到位于第二显示区120左右两侧的第一数据线210上，以提供到与该第一数据线210连接的M个第一像素电路112上；数据信号通过位于第一显示区110下侧的电路板加载到位于第二显示区120下侧的第一子数据线221上以提供到与该第一子数据线221连接的第一像素电路112；加载到位于第二显示区120下侧的第一子数据线221上数据信号通过第一条转接线223传输至第二子数据线222以提供到第二像素电路113中，然后该数据信号通过第二条转接线223传输至位于第二显示区120上侧的第一子数据线221以提供到第一像素电路112，则位于第二显示区两侧的第一子数据线以及与这两条第一子数据线连接的第二子数据线均传输相同的数据信号，该数据信号传输方式可以称为单路驱动。
如图2所示，上述两个第一子数据线221连接的第一像素电路112的数量分别为a1和a3，第二子数据线222连接的第二像素电路113的数量为a2，则与第二数据线220连接的像素电路的数量N等于a1+a2+a3，而与第一数据线210连接的第一像素电路111的数量M也等于a1+a2+a3，则M＝N。图2所示显示基板中的数据线为单路驱动，通过减少第二数据线连接的第三像素电路的数量，可以减少第二数据线上串联的像素电路的数量，使得M＝N，从而在一定程度上降低第二数据线的负载，进而在所有数据线同时输入相同信号时(ET点灯)，可以缓解第二显示区位置处出现暗竖条纹的现象。此外，减少第二数据线连接的像素 电路的数量以降低负载，还可以在每条数据线输入相应的数据信号(模组点灯)时，减轻驱动IC的负担。
由于第二显示区在第一方向的两侧均设置有第一像素电路，则第二显示区在第一方向的两侧均设置有与第一像素电路连接的第一子数据线，在单路驱动中，两部分第一子数据线需要通过第二子数据线以及两部分转接线实现电连接，因此转接区包括分别位于第二显示区两侧的第一转接区和第二转接区。
例如，第二转接区2232位于第一显示区110和第二显示区112以外的非显示区，以防止第二转接区内的转接线影响显示基板的显示效果。
例如，位于第二转接区2232中的相邻两条第一转接线223-1之间的距离可以小于位于第一转接区2231中的相邻两条转接线223之间的距离，以尽量减小边框的尺寸，实现窄边框。
例如，如图2和图3所示，第三像素电路114包括位于沿第一方向延伸的各第二像素电路列在第一方向的两侧的两部分，即第二像素电路113所在像素电路列中，第三像素电路114包括分布在第二像素电路113的两侧的两部分。
当然，本公开实施例不限于此，在第二显示区位于整体显示区顶部位置处时，第三像素电路可以仅位于各第二像素电路列的下侧，即第二像素电路的上侧没有设置第三像素电路。上侧和下侧例如为沿整个显示区域长边方向的两侧，顶部位置例如为远离驱动IC的一端。此时，在第一显示区的形状为矩形，第二显示区的形状为圆形时，该第二显示区的上侧边缘还会设置一些第一像素电路，则转接区还会包括如图2所示的第一转接区和第二转接区；在第一显示区的形状为矩形，第二显示区的形状也为矩形时，第一显示区的上边缘可以与第二显示区的上边缘齐平，此时第二显示区上侧不再设置第一像素电路，则转接区仅包括图2所示的第一转接区，省去了第二转接区，可以进一步实现窄边框。
例如，如图2和图3所示，显示基板还包括沿第一方向延伸的多条走线300，走线300不经过第二显示区120，多条走线300与多条数据线200同层设置，且相邻两条走线300之间设置有至少一条数据线200；沿垂直于衬底基板100的方向，各走线300仅与第三像素电路114交叠。例如，各走线300和与其交叠的第三像素电路114连接。本公开实施例中的走线为仅与虚设像素电路交叠的走线。
例如，走线300包括第一走线310，第一走线310的数量与第二子数据线222的数量相同，各第一走线310与一条第二子数据线222大致位于同一线上且两者之间设置有间隔230，该同一线例如为一大致沿第二方向延伸的直线，也可以在某些位置具有一定弯折，但主体部分例如50％以上位于同一直线上。例如，各第一走线310与一条第二子数据线222的至少部分位于同一线上且两者之间设置有间隔230。例如，一条第二子数据线222和与其位于同一线上的第一走线310可以为一条金属线中断开的两部分，则第二子数据线222的长度小于第一数据线210的长度，可以降低第二子数据线222的负载。
例如，如图2和图3所示，第二子数据线222与第一走线310之间的间隔230位于第 一转接区2231远离第二显示区120的一侧，则第一走线310不影响第二子数据线222上传输的数据信号。
例如，如图2和图3所示，各第一走线310和与其交叠的第三子像素114连接，且被配置为传输电信号。本公开实施例中，通过将第一走线和与第一走线交叠的第三像素电路进行连接，且第一走线上传输电信号，可以避免第一走线的浮置。
例如，第二子数据线222被配置为传输数据信号data，第一走线310上传输的电信号与第二子数据线222上传输的信号不同。
例如，第一走线310被配置为传输电源电压信号。例如，可以为恒定正电压VDD，但不限于此，也可以为其他电信号，例如复位电压信号。
例如，如图2所示，走线300还包括沿第一方向延伸的第二走线320，第二走线320包括位于第二显示区120在X方向两侧的部分以及位于第二显示区120在Y方向的至少一侧的部分。例如，位于第二显示区120在X方向两侧的第二走线320中，相邻两条第二走线320之间设置有多条第一数据线210，或者相邻两条第二走线320之间设置有多条第二子数据线222。位于第二显示区120在Y方向的至少一侧的第二走线320中，相邻两条第二走线320之间设置有多条第一子数据线221。例如，位于第二显示区120在Y方向的两侧的第二走线320中，任一侧的第二走线320中相邻两条第二走线320之间设置有多条第一子数据线221。图2没有示出位于第二显示区120在Y方向的两侧的第二走线。
例如，各第二走线320均可以传输电源电压信号。例如，多条第二走线320可以与沿X方向延伸的一条连接线连接。但不限于此，位于第二显示区一侧的第二走线也可以不传输电信号，即为浮置的。
图4为根据本公开实施例的另一示例提供的显示基板的局部平面结构示意图，图5为图4所示的显示基板的局部放大结构示意图。如图4和图5所示，图4和图5所示的示例与图2和图3所示的示例的不同之处在于：位于第二显示区120在第一方向上的至少一侧的第一像素电路112与第一数据线210连接，且该第一数据线210不与第二子数据线222连接。
例如，如图4和图5所示，各第二子数据线222沿第一方向延伸，且与各走线300在沿第一方向延伸的直线上的正投影有交叠。本示例中，各第二子数据线222基本为贯穿第一显示区110的数据线200，各第二子数据线222没有与任何走线300位于同一直线上，即走线300仅包括贯穿第一显示区110的部分以及延伸至第二显示区120的边缘的另一部分。
例如，如图4和图5所示，第一数据线210与位于第二显示区120在Y方向的一侧的第一像素电路112以及位于第二显示区120在X方向两侧的第一像素电路112连接。
例如，如图4和图5所示，各第一子数据线221与一条第一数据线210分别位于第二显示区120在第一方向的两侧，且位于同一直线上，各第一子数据线211和与其位于同一直线上的第一数据线210被配置为传输相同的数据信号。
例如，如图4和图5所示，与位于第二显示区120在X方向两侧的各第一数据线210 连接的第一像素电路112的数量为M，与位于第二显示区120在Y方向的一侧的第一数据线210连接的第一像素电路112的数量为a1。
例如，如图4和图5所示，各第二数据线220包括第一子数据线221、第二子数据线222以及连接第一子数据线221和第二子数据线222的转接线223。例如，转接线223位于第一显示区110和第二显示区120以外的非显示区。第二数据线220包括依次连接的三个部分，例如第二子数据线222、转接线223以及第一子数据线221。
例如，如图4和图5所示，与第二子数据线222连接的第二像素电路113的数量为a2，与第一子数据线221连接的第一像素电路112的数量为a3。
例如，数据信号通过位于第一显示区110下侧的电路板(未示出)加载到位于第二显示区120左右两侧的第一数据线210上，以提供到与该第一数据线210连接的M个第一像素电路112上；数据信号通过位于第一显示区110下侧的电路板加载到位于第二显示区120下侧的第一子数据线221上以提供到与该第一子数据线221连接的a1个第一像素电路112上；数据信号通过位于第一显示区110下侧的电路板加载到位于第二显示区120左右两侧的第二子数据线222上，以提供到与该第二子数据线222连接的a2个第二像素电路113中，然后该数据信号通过转接线223传输至位于第二显示区120上侧的第一子数据线221以提供到与第一子数据线221连接的a3个第一像素电路112上，且位于第二显示区120下侧的第一数据线210以及与该第一数据线210位于同一直线的第一子数据线221上被配置为传输相同的数据信号，该数据信号传输方式可以称为双路驱动。
在该双路驱动方式中，多条第一数据线中延长线不经过第二显示区的第一数据线上连接的第一像素电路的数量M为(a1+a2+a3)，延长线经过第二显示区的第一数据线上连接的第一像素电路的数量a1小于M，第二数据线上连接的像素电路的数量N为(a2+a3)，N小于M。图4所示显示基板中的数据线为双路驱动，通过减少第二数据线连接的第三像素电路的数量，可以减少第二数据线上串联的像素电路的数量，使得M大于等于N，从而在一定程度上降低第二数据线的负载，进而在所有数据线同时输入相同信号时(ET点灯)，可以缓解第二显示区位置处出现暗竖条纹的现象。此外，减少第二数据线连接的像素电路的数量以降低负载，还可以在每条数据线输入相应的数据信号(模组点灯)时，减轻驱动IC的负担。
例如，如图4和5所示，各第二子数据线222的长度不小于延长线不经过第二显示区120的第一数据线210的长度。例如，第二子数据线222、部分第一数据线120以及部分走线300均贯穿第一显示区110。
由于第二子数据线为与延长线不经过第二显示区的第一数据线的长度相同，而具有该长度的第二子数据线仅连接第二像素电路，不连接任何虚设像素电路，同时，第二子数据线不与第一子数据线通过转接线连接，可以降低第二子数据线产生的电容。
例如，如图4和图5所示，各转接线223包括彼此连接且不同层设置的第一转接线223-1和第二转接线223-2，第一转接线223-1和第二转接线223-2之一与第二子数据线222连接， 且与第二子数据线222位于不同层。
例如，如图4和图5所示，第一转接线223-1和第二转接线223-2中的另一个沿与第一方向相交的第二方向延伸，且与第二子数据线212位于同一层。
图6为根据本公开实施例的另一示例提供的显示基板的局部平面结构示意图。如图6所示，图6所示的示例与图5所示的示例的不同之处在于：各第二数据线220沿第一方向延伸，且各第二数据线220被配置为仅与第二像素电路113连接。如图6所示，第二显示区120和第一显示区110的形状相同，且第二显示区120的一侧边缘(例如上侧边缘)与第一显示区110的一侧边缘(例如上侧边缘)齐平，以使得第一像素电路112仅分布在第二显示区120的三侧。
例如，如图6所示，第二显示区120在Y方向的一侧设置有第一像素电路112，在Y方向的另一侧没有设置第一像素电路112，则第二数据线220仅被配置为给第二像素电路113提供数据信号即可，无需为第一像素电路提供数据信号。
例如，如图6所示，与第二数据线220交叠的所有第三像素电路114可以均与第二数据线220绝缘设置，但不限于此，与第二数据线交叠的第三像素电路中，也可以部分第三像素电路与第二数据线连接，另一部分第三像素电路与第二数据线绝缘设置。
例如，图7为图2至图6所示显示基板中各像素电路的等效图。以图7所示的像素电路为第二像素电路113为例，则第二像素电路113被配置为驱动第二发光元件121发光。其他像素电路，如第一像素电路和第三像素电路的结构与第二像素电路的结构相同，但是第三像素电路不与发光元件连接。例如，显示基板还包括位于衬底基板上的复位电源信号线、扫描信号线、电源信号线、复位控制信号线以及发光控制信号线。
例如，如图7所示，第二像素电路113包括数据写入晶体管T4、驱动晶体管T3、阈值补偿晶体管T2以及第一复位控制晶体管T7。阈值补偿晶体管T2的第一极与驱动晶体管T3的第一极连接，阈值补偿晶体管T2的第二极与驱动晶体管T3的栅极连接；第一复位控制晶体管T7的第一极与复位电源信号线连接以接收复位信号Vinit，第一复位控制晶体管T7的第二极与第二发光元件121连接；数据写入晶体管T4的第一极与驱动晶体管T3的第二极连接。例如，如图7所示，第二像素电路113还包括存储电容C、第一发光控制晶体管T6、第二发光控制晶体管T5和第二复位晶体管T1。数据写入晶体管T4的栅极与扫描信号线电连接以接收扫描信号Gate；存储电容C的第一极与电源信号线电连接，存储电容C的第二极与驱动晶体管T3的栅极电连接；阈值补偿晶体管T2的栅极与扫描信号线电连接以接收补偿控制信号；第一复位晶体管T7的栅极与复位控制信号线电连接以接收复位控制信号Reset(N+1)；第二复位晶体管T1的第一极与复位电源信号线电连接以接收复位信号Vinit，第二复位晶体管T1的第二极与驱动晶体管T3的栅极电连接，第二复位晶体管T1的栅极与复位控制信号线电连接以接收复位控制信号Reset(N)；第一发光控制晶体管T6的栅极与发光控制信号线电连接以接收发光控制信号EM；第二发光控制晶体管T5的第一极与电源信号线电连接以接收电源电压信号VDD，第二发光控制晶体管T5的第二极与驱动晶体管T3 的第二极电连接，第二发光控制晶体管T5的栅极与发光控制信号线电连接以接收发光控制信号EM，第二发光元件121的第一电极与电压端连接以接收信号VSS。上述电源信号线指输出电源电压信号VDD的信号线，可以与电压源连接以输出恒定的电压信号，例如正电压信号。
例如，扫描信号和补偿控制信号可以相同，即，数据写入晶体管T3的栅极和阈值补偿晶体管T2的栅极可以电连接到同一条信号线以接收相同的信号，减少信号线的数量。例如，数据写入晶体管T3的栅极和阈值补偿晶体管T2的栅极也可以分别电连接至不同的信号线，即数据写入晶体管T3的栅极电连接到第一扫描信号线，阈值补偿晶体管T2的栅极电连接到第二扫描信号线，而第一扫描信号线和第二扫描信号线传输的信号可以相同，也可以不同，从而使得数据写入晶体管T3的栅极和阈值补偿晶体管T2可以被分开单独控制，增加控制像素电路的灵活性。
例如，第一发光控制晶体管T6和第二发光控制晶体管T5被输入的发光控制信号可以相同，即，第一发光控制晶体管T6的栅极和第二发光控制晶体管T5的栅极可以电连接到同一条信号线以接收相同的信号，减少信号线的数量。例如，第一发光控制晶体管T6的栅极和第二发光控制晶体管T5的栅极也可以分别电连接至不同的发光控制信号线，而不同的发光控制信号线传输的信号可以相同，也可以不同。
例如，第一复位晶体管T7和第二复位晶体管T1被输入的复位控制信号可以相同，即，第一复位晶体管T7的栅极和第二复位晶体管T1的栅极可以电连接到同一条信号线以接收相同的信号，减少信号线的数量。例如，第一复位晶体管T7的栅极和第二复位晶体管T1的栅极也可以分别电连接至不同的复位控制信号线，此时，不同复位控制信号线上的信号可以相同也可以不相同。
例如，如图7所示，显示基板工作时，在画面显示的第一阶段，第二复位晶体管T1打开，使N1节点的电压初始化；在画面显示的第二阶段，data数据通过数据写入晶体管T4、驱动晶体管T3以及阈值补偿晶体管T2存储在N1节点；在第三发光阶段，第二发光控制晶体管T5、驱动晶体管T3以及第一发光控制晶体管T6均打开，发光元件正向导通发光。
需要说明的是，在本公开实施例中，像素电路除了可以为图7所示的7T1C(即七个晶体管和一个电容)结构之外，还可以为包括其他数量的晶体管的结构，如7T2C结构、6T1C结构、6T2C结构、8T1C结构或者9T2C结构，本公开实施例对此不作限定。
图8为根据本公开实施例提供的第二像素电路的有源半导体层、第一导电层以及源漏金属层的层叠结构的局部平面结构示意图。如图8所示，有源半导体层3100可采用半导体材料图案化形成。有源半导体层3100可用于制作上述的第二复位晶体管T1、阈值补偿晶体管T2、驱动晶体管T3、数据写入晶体管T4、第二发光控制晶体管T5、第一发光控制晶体管T6和第一复位控制晶体管T7的有源层。有源半导体层3100包括各晶体管的有源层图案(沟道区)和掺杂区图案(源漏掺杂区)。
例如，有源层可以包括一体形成的低温多晶硅层，源极区域和漏极区域可以通过掺杂 等进行导体化实现各结构的电连接。例如，各晶体管的有源半导体层为由p-硅形成的整体图案，且同一像素电路中的各晶体管包括掺杂区图案(即源极区域和漏极区域)和有源层图案，不同晶体管的有源层之间由掺杂结构隔开。
例如，有源半导体层3100可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
图10为图8所示像素电路中沿AA’所截的部分截面结构示意图。如图8和图10所示，有源半导体层3100远离衬底基板100的一侧设置有栅极绝缘层71，栅极绝缘层71远离有源半导体层3100的一侧设置有第一导电层3200(即栅极金属层)。第一导电层3200可以包括电容C的第二极CC2、沿X方向延伸的扫描信号线52、复位控制信号线51、发光控制信号线53以及第二复位晶体管T1、阈值补偿晶体管T2、驱动晶体管T3、数据写入晶体管T4、第二发光控制晶体管T5、第一发光控制晶体管T6和第一复位控制晶体管T7的栅极。
例如，如图8和图10所示，数据写入晶体管T3的栅极可以为扫描信号线52与有源半导体层3100交叠的部分；第一发光控制晶体管T6的栅极可以为发光控制信号线53与有源半导体层3100交叠的第一部分，第二发光控制晶体管T5的栅极可以为发光控制信号线53与有源半导体层3100交叠的第二部分。第二复位晶体管T1的栅极为复位控制信号线51与有源半导体层3100交叠的第一部分，第一复位控制晶体管T7的栅极为复位控制信号线51与有源半导体层3100交叠的第二部分。阈值补偿晶体管T2可为具有双栅结构的薄膜晶体管。如图8所示，驱动晶体管T1的栅极可为电容C的第二极CC2。
需要说明的是，图8中的各虚线矩形框示出了有源半导体层3100与第一导电层3200交叠的各个部分，即沟道区。作为各个晶体管的沟道区，在每个沟道区两侧的有源半导体层通过离子掺杂等工艺导体化作为各个晶体管的第一极和第二极。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本公开的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。
例如，如图8所示，扫描信号线52、复位控制信号线51和发光控制信号线53沿Y方向排布。扫描信号线52位于复位控制信号线51和发光控制信号线53之间。例如，电容C的第二极CC2(即驱动晶体管T1的栅极)位于扫描信号线52和发光控制信号线53之间。
例如，如图8所示，第一导电层3200远离衬底基板的一侧设置有源漏金属层3300，源漏金属层3300包括沿Y方向延伸的数据线200以及电源信号线54。源漏金属层3300还包括第一连接部55、第二连接部56、第三连接部57以及第四连接部58。
图9为根据本公开实施例提供的第二像素电路的有源半导体层、第一导电层、源漏金属层以及第二导电层的层叠结构的局部平面结构示意图。如图9和图10所示，第一导电层3200远离衬底基板100的一侧设置有第一绝缘层72，第二绝缘层72远离衬底基板100的一侧设置有第二导电层3400，第二导电层3400远离衬底基板100的一侧设置有第二绝缘层 73，第二绝缘层73远离衬底基板100的一侧设置有源漏金属层3300。
例如，如图9所示，第二导电层3400包括电容C的第一极CC1以及沿第一复位电源信号线81和第二复位电源信号线82。电容C的第一极CC1与电容C的第二极CC2至少部分重叠以形成电容C。
例如，第二导电层3400还包括多个覆盖部S，各阈值补偿晶体管T2包括两个栅极以及位于两个栅极在有源半导体层3100的正投影之间的有源半导体层。沿垂直于衬底基板的方向，覆盖部S与两个栅极之间的有源半导体层3100有交叠。
例如，如图8至图10所示，第二子数据线222通过贯穿栅极绝缘层71、第一绝缘层72和第二绝缘层73的过孔H1与第二像素电路中的数据写入晶体管T2的第二极电连接，以实现第二子数据线222为第二像素电路输入数据信号。
例如，如图8和图9所示，电源信号线54通过贯穿栅极绝缘层、第一绝缘层和第二绝缘层的过孔与第二发光控制晶体管T5的第一极电连接。电源信号线54和数据线200沿X方向交替设置。电源信号线54通过贯穿第二绝缘层的过孔与电容C的第一极CC1电连接。例如，上述第二绝缘层为层间绝缘层。
例如，双栅型阈值补偿晶体管可以减少漏电流。例如，双栅型阈值补偿晶体管T2的两段沟道之间的有源半导体层在阈值补偿晶体管T2关闭时处于浮置(floating)状态，易受周围线路电压的影响而跳变，从而会影响阈值补偿晶体管T2的漏电流，进而影响发光亮度。为了保持阈值补偿晶体管T2的两段沟道之间的有源半导体层电压稳定，设计覆盖部S与阈值补偿晶体管T2的两段沟道之间的有源半导体层形成电容，覆盖部S可以连接至电源信号线54以获得恒定电压，因此处于浮置状态的有源半导体层的电压可以保持稳定。覆盖部S与双栅型阈值补偿晶体管T2的两段沟道之间的有源半导体层交叠，还可以防止两个栅极之间的有源半导体层被光照而改变特性，例如防止该部分有源半导体层的电压发生变化，以防止产生串扰。
例如，如图8和图9所示，阈值补偿晶体管T2的第二极通过第一连接部55与驱动晶体管T3的栅极电连接，第一连接部55的第一端通过贯穿栅极绝缘层、第一绝缘层和第二绝缘层的过孔与阈值补偿晶体管T2的第二极连接，第一连接部55的第二端通过贯穿第一绝缘层和第二绝缘层的过孔与驱动晶体管T3的栅极连接。例如，第一连接部55与电容C的第一极CC1有交叠。第二复位晶体管T1的第一极通过第二连接部56与第一复位电源信号线81电连接，第二连接部56的一端通过贯穿栅极绝缘层、第一绝缘层和第二绝缘层的过孔与第二复位晶体管T1的第一极连接，第二连接部56的另一端通过贯穿第二绝缘层的过孔与第一复位电源信号线81连接。第一复位晶体管T7的第一极通过第三连接部57与第二复位电源信号线82电连接，第三连接部57的一端通过贯穿栅极绝缘层、第一绝缘层和第二绝缘层的过孔与第一复位晶体管T7的第一极连接，第三连接部57的另一端通过贯穿第二绝缘层的过孔与第二复位电源信号线82连接。由于第二显示区具有较大的ITO电容(即为连接第二发光元件和第二像素电路的透明走线和与其交叠的各导电层、源漏金属层等膜 层产生的电容)，第二发光元件的阳极电压爬升过程变得非常缓慢，对于低灰阶而言，第二发光元件的启亮时间大大延迟，本公开实施例中采用第一复位电源信号线和第二复位电源信号线分别与第一复位晶体管和第二复位晶体管连接，适当提高第一复位电源信号电压，可以改善低第二显示区灰阶亮度不均一的情况。
例如，如图8和图9所示，第四连接部58通过贯穿栅极绝缘层、第一绝缘层和第二绝缘层的过孔与第一发光控制晶体管T6的第二极连接。
需要注意的是，第一像素电路和第二像素电路的结构相同，且第一像素电路与数据线、扫描线、复位控制信号线、发光控制信号线以及电源信号线的位置关系和连接关系均与第二像素电路和相应的信号线之间的关系相同，在此不再赘述。同理，第三像素电路和第二像素电路的结构相同，且第三像素电路与走线、扫描线、复位控制信号线、发光控制信号线以及电源信号线的位置关系和连接关系均与第二像素电路和相应的信号线之间的关系相同，在此不再赘述。
例如，图11为根据本公开实施例提供的第三像素电路的有源半导体层、第一导电层以及源漏金属层的层叠结构的局部平面结构示意图。如图11所示，第三像素电路与第二子数据线222交叠，与第二子数据线222交叠的第三像素电路与图8所示的与第二子数据线222交叠的第二像素电路的不同之处在于与第二子数据线222交叠的第三像素电路和该第二子数据线222绝缘设置。
图12为图11所示像素电路中沿BB’所截的部分截面结构示意图。如图11和图12所示，第二子数据线222和第三像素电路中的数据写入晶体管T2的第二极之间设置的栅极绝缘层71、第一绝缘层72和第二绝缘层73均没有设置过孔，从而使得第二子数据线222和位于其正下方的数据写入晶体管T2的第二极绝缘设置。
由此，数据写入晶体管的第一极所在膜层与数据线所在膜层之间设置有绝缘层(包括栅极绝缘层、第一绝缘层以及第二绝缘层)，第一像素电路和第二像素电路中的数据写入晶体管的第一极通过位于绝缘层中的过孔与数据线连接，与第二数据线交叠的第三像素电路中的至少部分中的数据写入晶体管的第一极与第二数据线被绝缘层绝缘。
例如，第三像素电路和第二数据线所在膜层之间的至少一层绝缘层在第三像素电路对应区域可以不设置任何过孔。例如，第三像素电路和第二数据线之间的所有绝缘层在第三像素电路对应区域可以均不设置任何过孔。
例如，图13为图2所示的显示基板的显示区和一条第二数据线的示意图，图14为图13所示的区域E1的放大图，图15为图13所示的区域E2的放大图，图16为图13所示的区域E3的放大图，图17为图13所示的区域E4的放大图。图14至图16示意性的示出源漏金属层和第三导电层的层叠结构的平面示意图。如图13至图16所示，显示基板还包括位于源漏金属层远离衬底基板一侧的第三导电层，第三导电层包括位于显示区的转接线223、屏蔽电极SE、第五连接部59以及位于显示区以外的第二转接线223-2。
例如，屏蔽电极SE与电源信号线54连接，从而屏蔽电极SE上的电压稳定，可起到屏 蔽作用，避免连接第二发光元件和第二像素电路的透明走线影响驱动晶体管的栅极以及第一连接部的电位。第一连接部在衬底基板上的正投影落入屏蔽电极SE在衬底基板上的正投影内。
例如，如图13至图17所示，第三导电层与源漏金属层之间可以设置第三绝缘层，第五连接部59可以通过第三绝缘层中的过孔与第四连接部58连接以实现与第一发光控制晶体管T6的第二极连接。
例如，各发光元件包括层叠设置的第一电极、发光层以及第二电极(均未示出)，第一电极位于发光层面向衬底基板的一侧，第一电极通过第五连接部和第四连接部与第一发光控制晶体管T6的第二极连接。
例如，如图14和图15所示，与一条第一子数据线221连接的转接线223可以与第二连接部56和第三连接部57交叠。例如，在垂直与衬底基板的方向，该转接线223可以与复位控制信号线交叠。
例如，如图16和图17所示，第一转接线223-1可以由源漏金属层图案化形成以节省膜层数量，第二转接线223-2由第三导电层图案化形成，第二转接线223-1通过第三绝缘层中的两个过孔H2分别与第一子数据线221和第一转接线223-1连接。本公开实施例不限于此，第二转接线可以与第一子数据线(或第二子数据线)同层设置，且为同一条信号线，第一转接线与第一子数据线不同层设置。
例如，如图16和图17所示，第三绝缘层中还包括多个过孔H3，以使第三绝缘层被刻蚀的更加均匀。
例如，图18为包括图16所示局部放大图的部分结构，图19为包括图17所示局部放大图的部分结构。例如，如图16至图19所示，相邻两个第二子数据线222之间可以设置七条第一数据线210，相邻两条走线300之间可以设置七条第一子数据线221。例如，位于第二显示区上侧的第一子数据线221均通过第一转接线223-1和第二转接线223-2与位于第二显示区左右两侧的第二子数据线222连接。
本公开至少一实施例提供一种显示基板，如图2至图19所示，显示基板包括衬底基板100、位于衬底基板100上的多个像素电路1000以及多条数据线200。所述多个像素电路1000包括多个第一类型像素电路1001和多个第二类型像素电路1002，所述第一类型像素电路1001与所述数据线200电连接，所述第二类型像素电路1002与所述数据线200绝缘设置。本公开实施例提供的显示基板中，通过将第二类型像素电路与数据线绝缘设置，可以减少数据线连接的像素电路的数量以降低负载，从而缓解显示区出现暗竖条纹的现象，提高显示基板的显示质量。
例如，如图2至图19所示，所述第一类型像素电路1001和与其交叠的所述数据线200电连接，所述第二类型像素电路1002和与其交叠的所述数据线200绝缘。
例如，如图2至图19所示，所述第一类型像素电路1001的至少部分被配置为驱动与其连接的发光元件(例如第一发光元件111或者第二发光元件121)发光，所述第二类型像 素电路1002为第一虚设像素电路。第一虚设像素电路为不与任何发光元件连接的像素电路。
例如，如图2至图19所示，所述第一类型像素电路1001包括第一像素电路112和第二像素电路113，所述第一像素电路112和与其连接的所述发光元件(第一发光元件111)在垂直于所述衬底基板100的方向有交叠，所述第二像素电路113和与其连接的所述发光元件(第二发光元件121)在垂直于所述衬底基板100的方向没有交叠；所述第一类型像素电路1001还包括第二虚设像素电路1003。第二虚设像素电路1003为不与任何发光元件连接的像素电路。
例如，如图2至图19所示，所述第二类型像素电路1002和部分所述第一类型像素电路1002位于同一列。
例如，如图2至图19所示，所述第二类型像素电路1002和所述第二像素电路113位于同一列。
例如，如图2至图19所示，所述像素电路1000包括数据写入晶体管T4，所述数据写入晶体管T4包括第一极、第二极以及栅极，所述数据写入晶体管T4的第一极所在膜层与所述数据线200所在膜层之间设置有绝缘层，所述第一类型像素电路1001的所述数据写入晶体管T4的第一极通过位于所述绝缘层(例如栅极绝缘层71、第一绝缘层72和第二绝缘层73)中的过孔H1与相应的所述数据线200连接；所述第二类型像素电路1002的所述数据写入晶体管T4的第一极与所述数据线200被所述绝缘层(例如栅极绝缘层71、第一绝缘层72和第二绝缘层73)绝缘。
本实施例中的第一类型像素电路包括上述实施例中的第一像素电路、第二像素电路和部分第三像素电路(与走线连接的第三像素电路)，第二类型像素电路包括另一部分第三像素电路(与走线或数据线均不连接的像素电路)。本公开实施例中的衬底基板、数据线、像素电路以及发光元件等结构与上述实施例中的衬底基板、数据线、像素电路以及发光元件等结构具有相同的特征，在此不再赘述。
本公开另一实施例提供一种显示装置，该显示装置包括上述任一显示基板。
例如，本公开实施例提供的显示装置可以为有机发光二极管显示装置。
例如，本公开实施例提供的显示装置中，通过将与第二数据线交叠的至少部分第三像素电路设置为与第二数据线不连接，可以减少第二数据线连接的像素电路的数量以降低负载，从而缓解第二显示区出现暗竖条纹的现象，提高显示装置的显示质量。
例如，显示装置还可以包括位于显示基板显示侧的盖板。例如，显示装置还可以包括位于衬底基板远离发光元件一侧的功能部件，功能部件与第二显示区正对。
例如，功能部件包括相机模组(例如，前置摄像模组)、3D结构光模组(例如，3D结构光传感器)、飞行时间法3D成像模组(例如，飞行时间法传感器)、红外感测模组(例如，红外感测传感器)等至少之一。
例如，前置摄像模组通常在用户自拍或视频通话时启用，显示装置的像素显示区显示自拍所得到的图像供用户观看。前置摄像模组例如包括镜头、图像传感器、图像处理芯片 等。景物通过镜头生成的光学图像投射到图像传感器表面(图像传感器包括CCD和CMOS两种)变换为电信号，通过图像处理芯片模数转换后变为数字图像信号，再送到处理器中加工处理，在显示屏上输出该景物的图像。
例如，3D结构光传感器和飞行时间法(Time of Flight，ToF)传感器可以用于人脸识别以对显示装置进行解锁等。
例如，功能部件20可以仅包括相机模组以实现自拍或者视频通话的功能；例如，该功能部件20可以进一步包括3D结构光模组或者飞行时间法3D成像模组以实现人脸识别解锁等，本实施例包括但不限于此。
例如，该显示装置可以为具有屏下摄像头的手机、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产品或者部件，本实施例不限于此。
有以下几点需要说明：
(1)本公开的实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (31)

  1. 一种显示基板，包括：
    衬底基板，包括第一显示区和第二显示区，其中，所述第一显示区位于所述第二显示区的周边，所述第一显示区包括多个第一发光元件、多个第一像素电路、多个第二像素电路以及多个第三像素电路，所述多个第一像素电路与所述多个第一发光元件一一对应连接，所述第二显示区包括多个第二发光元件，所述多个第二像素电路与所述多个第二发光元件一一对应连接，所述第三像素电路为虚设像素电路；
    多条数据线，位于所述衬底基板上，且不经过所述第二显示区，其中，所述多条数据线包括多条第一数据线和多条第二数据线，各所述第一数据线被配置为与所述第一像素电路连接，各所述第二数据线被配置为至少与所述第二像素电路连接；
    其中，沿垂直于所述衬底基板的方向，所述多个第三像素电路的部分与所述多条第二数据线交叠，与所述第二数据线交叠的所述第三像素电路中的至少部分与所述第二数据线绝缘设置。
  2. 根据权利要求1所述的显示基板，其中，与所述第二数据线交叠的各所述第三像素电路与所述第二数据线绝缘设置。
  3. 根据权利要求1或2所述的显示基板，其中，各所述第一数据线沿第一方向延伸，所述多条第一数据线中延长线不经过所述第二显示区的所述第一数据线被配置为给M个所述第一像素电路传输数据信号，各所述第二数据线被配置为给N个像素电路传输信号，且M≥N，所述N个像素电路至少包括所述第二像素电路。
  4. 根据权利要求3所述的显示基板，其中，所述第二数据线包括沿所述第一方向延伸的第一子数据线和第二子数据线，以及连接所述第一子数据线和所述第二子数据线的转接线；
    所述第一子数据线、所述第二子数据线以及所述第一数据线同层设置，所述第一子数据线被配置为与所述第一像素电路连接，所述第二子数据线被配置为与所述第二像素电路连接。
  5. 根据权利要求4所述的显示基板，还包括：
    多条走线，沿所述第一方向延伸，且不经过所述第二显示区，
    其中，所述多条走线与所述多条第一数据线同层设置，且相邻两条走线之间设置有至少一条数据线；
    沿垂直于所述衬底基板的方向，所述走线仅与所述第三像素电路交叠。
  6. 根据权利要求5所述的显示基板，其中，所述多条走线包括多条第一走线，所述第一走线的数量与所述第二子数据线的数量相同，一条所述第一走线与一条第二子数据线的至少部分大致位于同一直线上且两者之间设置有间隔；
    转接区，包括所述多条转接线，
    其中，所述转接区包括位于所述第二显示区在所述第一方向的一侧的第一转接区，所述第一转接区中的所述转接线沿与所述第一方向相交的第二方向延伸且与所述第一数据线位于不同层，所述间隔位于所述第一转接区远离所述第二显示区的一侧，所述第一走线和至少部分所述第三像素电路交叠。
  7. 根据权利要求6所述的显示基板，其中，所述第一走线上和所述第二子数据线被配置为传输不同的电信号。
  8. 根据权利要求7所述的显示基板，其中，所述第一走线被配置为传输电源电压信号。
  9. 根据权利要求6-8任一项所述的显示基板，其中，所述转接区还包括位于所述第二显示区在所述第一方向的另一侧的第二转接区，所述第二转接区位于所述第一显示区和所述第二显示区以外的非显示区。
  10. 根据权利要求9所述的显示基板，其中，所述第二转接区的各所述转接线包括彼此连接且不同层设置的第一转接线和第二转接线，所述第一转接线和所述第二转接线之一与所述第二子数据线连接，且与所述第二子数据线位于不同层。
  11. 根据权利要求4-10任一项所述的显示基板，其中，所述第二数据线中，两条第一子数据线与同一条第二子数据线连接，所述两条第一子数据线分别位于所述第二显示区在所述第一方向的两侧，且所述两条第一子数据线的至少部分大致位于同一直线上。
  12. 根据权利要求5所述的显示基板，其中，一所述第二子数据线沿所述第一方向延伸，且与一所述走线在沿所述第一方向延伸的直线上的正投影有交叠。
  13. 根据权利要求12所述的显示基板，其中，所述转接线位于所述第一显示区和所述第二显示区以外的非显示区。
  14. 根据权利要求13所述的显示基板，其中，各所述转接线包括彼此连接且不同层设置的第一转接线和第二转接线，所述第一转接线和所述第二转接线之一与所述第二子数据线连接，且与所述第二子数据线位于不同层。
  15. 根据权利要求13所述的显示基板，其中，所述第二子数据线的长度不小于所述多条第一数据线中延长线不经过所述第二显示区的所述第一数据线的长度。
  16. 根据权利要求12-15任一项所述的显示基板，其中，所述第一子数据线与一条第一数据线分别位于所述第二显示区在所述第一方向的两侧，且大致位于同一直线上，各所述第一子数据线和与其位于大致同一直线上的所述第一数据线被配置为传输相同的数据信号。
  17. 根据权利要求7或14所述的显示基板，其中，所述第一转接线和所述第二转接线中的另一个沿与所述第一方向相交的第二方向延伸，且与所述第二子数据线位于同一层。
  18. 根据权利要求3-5任一项所述的显示基板，其中，所述第二数据线沿所述第一方向延伸，且所述第二数据线被配置为仅与所述第二像素电路连接。
  19. 根据权利要求3-18任一项所述的显示基板，其中，所述第一显示区包括的多个像素电路沿所述第一方向和第二方向阵列排布，所述多个第二像素电路位于所述第二显示区 在所述第二方向的两侧。
  20. 根据权利要求19所述的显示基板，其中，沿所述第一方向排布的所述第二像素电路所在像素电路列包括所述第三像素电路，且所述像素电路列中的所述第三像素电路与所述第二数据线交叠。
  21. 根据权利要求5-10、12-17任一项所述的显示基板，其中，所述多个第三像素电路包括沿所述第一方向延伸且沿第二方向排列的多个第三像素电路列，所述多个第三像素电路列的至少部分位于所述第二显示区在所述第一方向的至少一侧。
  22. 根据权利要求21所述的显示基板，其中，所述多个第三像素电路列还包括位于所述第二显示区在所述第二方向的两侧的部分。
  23. 根据权利要求1-22任一项所述的显示基板，其中，所述像素电路包括数据写入晶体管，所述数据写入晶体管包括第一极、第二极以及栅极，所述数据写入晶体管的第一极所在膜层与所述数据线所在膜层之间设置有绝缘层，所述第一像素电路和所述第二像素电路中的所述数据写入晶体管的第一极通过位于所述绝缘层中的过孔与所述数据线连接，与所述第二数据线交叠的所述第三像素电路中的至少部分中所述数据写入晶体管的第一极与所述第二数据线被所述绝缘层绝缘。
  24. 一种显示基板，包括：
    衬底基板；
    多个像素电路，位于所述衬底基板上；
    多条数据线，位于所述衬底基板上，
    其中，所述多个像素电路包括多个第一类型像素电路和多个第二类型像素电路，所述第一类型像素电路与所述数据线电连接，所述第二类型像素电路与所述数据线绝缘设置。
  25. 根据权利要求24所述的显示基板，其中，所述第一类型像素电路和与其交叠的所述数据线电连接，所述第二类型像素电路和与其交叠的所述数据线绝缘。
  26. 根据权利要求24或25所述的显示基板，其中，所述第一类型像素电路的至少部分被配置为驱动与其连接的发光元件发光，所述第二类型像素电路为第一虚设像素电路。
  27. 根据权利要求26所述的显示基板，其中，所述第一类型像素电路包括第一像素电路和第二像素电路，所述第一像素电路和与其连接的所述发光元件在垂直于所述衬底基板的方向有交叠，所述第二像素电路和与其连接的所述发光元件在垂直于所述衬底基板的方向没有交叠；
    所述第一类型像素电路还包括第二虚设像素电路。
  28. 根据权利要求27所述的显示基板，其中，所述第二类型像素电路和部分所述第一类型像素电路位于同一列。
  29. 根据权利要求28所述的显示基板，其中，所述第二类型像素电路和所述第二像素电路位于同一列。
  30. 根据权利要求24-29任一项所述的显示基板，其中，所述像素电路包括数据写入晶 体管，所述数据写入晶体管包括第一极、第二极以及栅极，所述数据写入晶体管的第一极所在膜层与所述数据线所在膜层之间设置有绝缘层，
    所述第一类型像素电路的所述数据写入晶体管的第一极通过位于所述绝缘层中的过孔与相应的所述数据线连接；所述第二类型像素电路的所述数据写入晶体管的第一极与所述数据线被所述绝缘层绝缘。
  31. 一种显示装置，包括权利要求1-30任一项所述的显示基板。
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