WO2024017060A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

Info

Publication number
WO2024017060A1
WO2024017060A1 PCT/CN2023/105766 CN2023105766W WO2024017060A1 WO 2024017060 A1 WO2024017060 A1 WO 2024017060A1 CN 2023105766 W CN2023105766 W CN 2023105766W WO 2024017060 A1 WO2024017060 A1 WO 2024017060A1
Authority
WO
WIPO (PCT)
Prior art keywords
area
frame area
lead
bus
power bus
Prior art date
Application number
PCT/CN2023/105766
Other languages
English (en)
French (fr)
Inventor
丁录科
袁粲
许程
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2024017060A1 publication Critical patent/WO2024017060A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/841—Self-supporting sealing arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.
  • OLEDs organic electroluminescent displays
  • an embodiment of the present disclosure provides a display substrate, including:
  • a base substrate includes a display area and a first frame area located on one side of the display area;
  • the first power bus is located at least in the first frame area.
  • the first power bus includes a first sub-bus, a second sub-bus and at least two connecting lines.
  • the first sub-bus is located in the second sub-bus. and the display area, and the first sub-bus is electrically connected to the second sub-bus through the at least two connection lines.
  • the first side The frame area includes at least one first binding area, the first binding area is used for binding the first circuit board;
  • the display substrate also includes a general reference line and at least one lead group located in the first frame area, and at least a second power bus located in the first frame area, and the lead group is electrically connected to the first circuit board.
  • the lead set includes a first lead, a second lead and a third lead, wherein the first lead is integrally provided with the first power bus, and the second lead is integrally provided with the second power bus , the third lead is integrally provided with the general reference line, and the orthographic projection of the third lead on the substrate is located between the orthographic projection of the first lead on the substrate and the third lead.
  • the two leads are between orthogonal projections on the base substrate.
  • the first frame area includes a plurality of the first binding areas arranged side by side, and a plurality of first binding areas located between the first binding areas.
  • a spacing area there are multiple lead wire groups, each of the lead wire groups is electrically connected to one end of the first circuit board adjacent to the spacing area, and the lead wire group extends in a direction close to the spacing area .
  • the above-mentioned display substrate provided by the embodiment of the present disclosure further includes a fan-out line located in the first frame area, and the fan-out line is connected between the display area and the first circuit board. , the fan-out line and the second lead are arranged in the same layer and with the same material.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure also includes a plurality of floating lines arranged in the same layer and with the same material as the fan-out line.
  • the plurality of floating lines are located on the fan-out line. and the second lead.
  • the line width and line spacing of each floating line gradually increase.
  • the substrate substrate further includes a second frame area opposite to the first frame area, and is connected to the first frame area respectively.
  • the third frame area and the fourth frame area of the second frame area the second frame area includes a second binding area, the second binding area is used to bind the second circuit board;
  • the first power bus is provided in the first frame area, the second frame area, the third frame area and the fourth frame area, and the first power bus in the second frame area is connected to the first power bus in the second frame area.
  • the second circuit board is electrically connected, the first power bus in the third frame area and the first power bus in the fourth frame area are electrically connected to the first circuit board, and the The first power buses of the second frame area, the third frame area and the fourth frame area are provided integrally.
  • the second power bus is also provided in the second frame area, and the second power bus is electrically connected to the second circuit board.
  • the display substrate also includes a power line located in the display area. One end of the power line is electrically connected to the second power bus in the first frame area, and the other end of the power line is connected to the second power bus. The second power bus in the frame area is electrically connected.
  • the above display substrate provided by the embodiment of the present disclosure further includes a plurality of fourth leads and a plurality of fifth leads located in the second frame area, wherein the plurality of fourth leads are connected to Between the first power bus and the second circuit board, the plurality of fifth leads are connected between the second power bus and the second circuit board, and each of the fourth leads is connected to the second circuit board.
  • the orthographic projection on the base substrate and the orthographic projection of each fifth lead on the base substrate are alternately arranged.
  • the third frame area and/or the fourth frame area include a third binding area arranged side by side with the first frame area, The third binding area is used to bind the third circuit board;
  • the display substrate includes: a main line, a plurality of branch lines, and a plurality of shift registers arranged in cascade, each of the branch lines having One end is electrically connected to one of the shift registers, and the other ends of all the branch lines are connected to the third circuit board through the main line.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure further includes two sixth leads, one end of the two sixth leads is integrally provided with both ends of the total reference line, and both The other ends of the sixth leads are respectively connected to the ends of the outermost two first circuit boards in the arrangement direction of each of the first binding areas away from the isolation area.
  • the first sub-bus in a direction away from the display area, the first sub-bus, the total reference line, the second power bus, the The second sub-bus is set in turn.
  • the layer where the second power bus is located is located between the layer where the general reference line is located and the layer where the first power bus is located.
  • an embodiment of the present disclosure provides a display device, including the above display substrate provided by an embodiment of the present disclosure.
  • Figure 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
  • Figure 2 is an enlarged schematic diagram of the M area in Figure 1;
  • Figure 3 is an enlarged schematic diagram of the N area in Figure 1;
  • FIG. 4 is a schematic structural diagram of a sub-pixel provided by an embodiment of the present disclosure.
  • OLED display devices With the upgrading of electronic products, medium-sized OLED display devices have gradually become a hot spot. This is because OLED display devices have advantages such as high contrast and self-illumination. Compared with small-sized screens, medium-sized display screens can provide users with Provide rich information, improve the efficiency of human-machine communication, and bring a better user experience.
  • the pixel circuits contained in them are also becoming more and more complex.
  • related technologies use 6T1C and similar internal compensation pixel circuits that can reduce resolution and increase refresh frequency.
  • Complex pixel circuits correspond to more manufacturing processes and more stringent process requirements. In actual product production, the probability of various defects is greatly increased. In order to ensure yield, maintenance processes are essential.
  • the power bus can provide power signals for pixel circuits and light-emitting devices to achieve screen display. Therefore, the yield of the power bus is particularly important.
  • an embodiment of the present disclosure provides a display substrate, as shown in Figure 1, including:
  • the base substrate 101 includes a display area AA and a first frame area BB 1 located on one side of the display area AA;
  • the first power bus 102 is located at least in the first frame area BB 1 .
  • the first power bus 102 includes a first sub-bus 21 , a second sub-bus 22 and at least two connecting lines 23 .
  • the first sub-bus 21 is located in the second sub-bus. 22 and the display area AA, and the first sub-bus 21 is electrically connected to the second sub-bus 22 through at least two connection lines 23 .
  • the first power bus 102 may be a high-level (VDD) power bus or a low-level (VSS) power bus.
  • the first power bus 102 is a low-level power bus as an example for description.
  • Each connection line 23 may be arranged in parallel between the first sub-bus 21 and the second sub-bus 22 , or each connection line 23 may be arranged in a cross-like mesh structure to connect between the first sub-bus 21 and the second sub-bus 22 .
  • the first power bus 102 is configured as a dual bus structure including a first sub-bus 21 and a second sub-bus 22, and at least two connecting lines 23 are used to connect the first sub-bus 102 to a dual-bus structure.
  • the bus 21 and the second sub-bus 22 are connected together, so that when the first sub-bus 21 is open, the disconnected first sub-bus 21 can still be connected through the connecting line 23 and the second sub-bus 22.
  • the second sub-bus 22 maintains normal signal transmission performance; in the case of a short circuit (short) between the first sub-bus 21 due to metal residue (Particle) and other components (such as the general reference line), the metal can be cut by laser cutting or other methods.
  • the first sub-bus 21 where the residue is located is disconnected from the first sub-bus 21 around the metal residue to solve the short circuit problem, and the disconnected first sub-bus 21 can still maintain normal operation through the connecting wire 23 and the second sub-bus 22 Signal transmission performance.
  • the signal transmission performance of the first power bus 102 can also be ensured. Therefore, the present disclosure improves the yield of the first power bus 102.
  • the first frame area BB 1 includes at least one first binding area BD 1 , and the first binding area BD 1 is used for Binding the first circuit board 103
  • the first circuit board 103 can be a chip on film (COF) with a chip (IC);
  • the display substrate can also include a general reference line 104 located in the first frame area BB 1 and At least one lead group 105, and at least the second power bus 106 located in the first frame area BB 1.
  • the first sub-bus 21, the total reference bus 21 and the total reference bus 21 can be arranged in sequence in the direction away from the display area AA.
  • the lead set 105 may be electrically connected to the first circuit board 103, and the lead set 105 may include a first lead 51, a second lead 52, and a third lead 53, wherein the first lead 51 is integrally provided with the first power bus 102, and the first lead 51 is integrated with the first power bus 102.
  • the second lead 52 is integrally provided with the second power bus 106
  • the third lead 53 is integrally provided with the total reference line 104.
  • the orthographic projection of the third lead 53 on the base substrate 101 is located at the orthogonal projection of the first lead 51 on the base substrate 101. The projection is between the orthographic projection of the second lead 52 on the base substrate 101 .
  • the line widths of the first lead 51 , the second lead 52 and the third lead 53 are all larger, but the larger line width results in a smaller distance between adjacent leads. Since the first lead 51 and the first power bus 102 are integrally provided, and the second lead 52 and the second power bus 106 are integrally provided, the first lead 51 and the first power bus 102 transmit the same electrical signal, and the second lead 52 and the second power bus 106 transmit the same electrical signal.
  • the second power bus 106 carries the same electrical signal.
  • the first power bus 102 and the second power bus 106 are respectively a low-level power bus and a high-level power bus.
  • the voltage difference between them Larger means that the voltage difference between the first lead 51 and the second lead 52 is larger. When the distance between the first lead 51 and the second lead 52 is small, there may be a high voltage breakdown between them. The insulation layer may cause a short circuit between the two.
  • the present disclosure uses the third lead 53 (which transmits the same electrical signal as the total reference line 104)
  • the orthographic projection on the base substrate 101 is located between the orthographic projection of the first lead 51 on the base substrate 101 and the orthographic projection of the second lead 52 on the base substrate 101, which can make the voltage difference between adjacent leads smaller. Small, thereby reducing the risk of short circuits caused by high voltage differences.
  • the first frame area BB 1 includes a plurality of first binding areas BD 1 arranged side by side, and a In the space S between the areas BD 1 , there are multiple lead groups 105.
  • Each lead group 105 is electrically connected to one end of the first circuit board 103 adjacent to the space S, and the lead group 105 faces the direction close to the space S. extend. Since the wiring space in and around the separation area S is large, in order to reduce power consumption, a lead group 105 with a larger line width can be set up in the wiring space, so that the lead group 105 and the first circuit board 103 are adjacent to the separation area S. one end, and ensure that the lead group 105 extends toward the direction close to the spacing area S.
  • the distance between 51 and the spacing area S decreases successively.
  • the first lead 51 is arranged close to the spacing area S
  • the second lead 52 is arranged away from the spacing area S.
  • the first power bus 102 is a low-level power line as an example.
  • the low-level power line is usually electrically connected to the cathode of the light-emitting device.
  • the low-level power line is in the same layer as the reflective anode.
  • the spacer area S and the space on the side close to the first power bus 102 can be fully utilized to lay the first lead line 51 with a larger line width (as shown in FIG. 2 ), thereby utilizing the first lead 51 to be electrically connected to the cathode, thereby achieving a stable connection between the first power bus 102 integrated with the first lead 51 and the cathode.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure also includes a fan-out line 107 located in the first frame area BB 1 , and the fan-out line 107 is connected to the display area.
  • a fan-out line 107 located in the first frame area BB 1 , and the fan-out line 107 is connected to the display area.
  • one end of the fan-out line 107 is integrally provided with the data line 108 of the display area AA, and the other end of the fan-out line 107 is electrically connected to the middle part of the first circuit board 103.
  • the fan-out line 107 and the second lead 52 can be provided in the same layer and with the same material.
  • the fan-out line 107 and the second lead 52 can be made of the material of the second source-drain metal layer (SD 2 ).
  • “same layer, same material” refers to a layer structure formed by using the same film-forming process to form a film layer for making a specific pattern, and then using the same mask to form a patterning process. That is, one patterning process corresponds to one mask (also called photomask).
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous.
  • These specific patterns may be at the same height or Have the same thickness, may be at different heights or have different thicknesses. It can be seen that when the fan-out line 107 and the second lead 52 are arranged in the same layer and with the same material, a mask process can be saved, the number of film layers can be reduced, and the production cost can be reduced.
  • the above-mentioned display substrate provided by the embodiments of the present disclosure may also include multiple floating lines 109 arranged in the same layer and with the same material as the fan-out lines 107 (that is, no signals are loaded thereon). ), a plurality of floating lines 109 are located between the fan-out line 107 and the second lead 52 .
  • the pattern design of the mask is sparse or has no pattern, a large area of photoresist will be developed, producing a high-density catalyst; when the mask has a dense pattern design, the photoresist development area will be smaller, resulting in a low-density catalyst. .
  • the catalyst density in the low-density area will gradually become higher due to the influence of the catalyst density in the high-density area, which affects the development process of the low-density area.
  • the patterns of the fan-out line 107 and the second lead 52 are dense, and the space between the fan-out line 107 and the second lead 52
  • the blank area (corresponding to the pattern-free area of the mask) is relatively large. During the development process, the catalyst density in this blank area will be greater than the catalyst density in the area where the fan-out line 107 is located and the area where the second lead 52 is located.
  • the fan-out line 107 Due to the penetration effect, the fan-out line 107 The catalyst density in the area where the fan-out wire 107 is located and the area where the second lead wire 52 is located will increase, causing over-development of the fan-out wire 107 and the second lead wire 52.
  • the thin fan-out wire 107 may be broken after being over-developed.
  • multiple floating lines 109 are provided between the fan-out line 107 and the second lead 52 to reduce the catalyst density difference during the development process and reduce the breakage probability of the fan-out line 107.
  • the line width and line spacing of each floating line 109 gradually increase. Increase, so that during the development process, in the direction from the fan-out line 107 to the second lead 52, the catalyst density has a gradual change trend without causing a sudden change in density, which can effectively improve the anti-breakage effect.
  • the minimum line width of the floating line 109 is greater than the line width of the fan-out line 107
  • the maximum line width of the floating line 109 is less than the line width of the second lead 52 .
  • the substrate substrate 101 may also include a second frame area BB 2 opposite to the first frame area BB 1 , and The third frame area BB 3 and the fourth frame area BB 4 respectively connect the first frame area BB 1 and the second frame area BB 2.
  • the second frame area BB 2 includes the second binding area BD 2 and the second binding area BD 2 is used to bind the second circuit board 110.
  • the second circuit board 110 is a flexible circuit board (FPC); the first power bus 101 is provided in the first frame area BB 1 , the second frame area BB 2 , The third frame area BB 3 and the fourth frame area BB 4 , the first power bus 102 of the second frame area BB 2 is electrically connected to the second circuit board 110, the first power bus 102 of the third frame area BB 3 , and the The first power bus 102 of the four-frame area BB 4 is electrically connected to the first circuit board 103, and the first power bus 102 of the second frame area BB 2 , the third frame area BB 3 and the fourth frame area BB 4 is integrally provided.
  • the display area AA of the display substrate includes a plurality of pixels arranged in an array.
  • FIG. 1 shows two pixels, and each pixel includes a red sub-pixel R, a green sub-pixel G and a blue sub-pixel B.
  • Each sub-pixel includes a light-emitting device, and the cathode of each light-emitting device is integrally arranged to form a planar electrode.
  • the planar electrode covers the frame area and is electrically connected to the first power bus 102 in the frame area.
  • the voltage drop on the cathode can be reduced and the uniformity of the signal on the cathode can be improved, which is beneficial to The uniform light emission of each light-emitting device enhances the uniformity of brightness. Since the voltage drop of the cathode is relatively large in medium and large-sized products, the bilateral power supply solution of the present disclosure is particularly suitable for medium- and large-sized products.
  • the second power bus 106 can also be provided in the second frame area BB 2 , and the second power bus 106 is connected to the second
  • the circuit board 110 is electrically connected; the display substrate also includes a power line 111 located in the display area AA.
  • One end of the source line 106 is electrically connected to the second power bus 106 in the first frame area BB 1 , and the other end of the power line 106 is electrically connected to the second power bus 106 in the second frame area BB 2 to reduce the voltage on the power line 111.
  • the voltage drop ensures that the power signal amplitude provided by the power line 111 to the pixel circuits contained in the sub-pixels in the same column is approximately the same, avoiding the impact of the voltage drop on the operating current provided by the pixel circuit to the light-emitting device, and enhancing brightness uniformity.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure may also include a plurality of fourth leads 112 and a plurality of fifth leads 113 located in the second frame area BB 2 , wherein , a plurality of fourth leads 112 are connected between the first power bus 102 and the second circuit board 110 , a plurality of fifth leads 113 are connected between the second power bus 106 and the second circuit board 110 , each fourth lead 112
  • the orthographic projection on the base substrate 101 and the orthographic projection of each fifth lead 113 on the base substrate 101 are alternately arranged, that is, the orthographic projection of the fourth lead 112 on the base substrate 101 and the orthographic projection of the fifth lead 113 on the base substrate 101 are alternately arranged.
  • the orthographic projections on 101 do not overlap each other. Since the fourth lead 112 can be integrally provided with the first power bus 102 and the fifth lead 113 can be integrally provided with the second power bus 106, the orthographic projection of the fourth lead 112 on the base substrate 101 and the fifth lead 113 are When the orthographic projections on the base substrate 101 do not overlap each other, it is equivalent to reducing the overlapping capacitance between the first power bus 102 and the second power bus 106, which can effectively prevent the first power bus 102 and the second power bus 106 from overlapping. Signals on the power bus 106 interfere with each other.
  • the third frame area BB 3 and/or the fourth frame area BB 4 include a third frame area BB 3 arranged side by side with the first frame area BB 1
  • the third binding area BD 3 is used to bind the third circuit board 114.
  • the third circuit board 114 is a flexible circuit board (FPC); in the third frame area BB 3 and /Or in the fourth frame area BB 4 , the display substrate includes: a main line 115, a plurality of branch lines 116, and a plurality of shift registers 117 arranged in cascade. One end of each branch line 116 corresponds to a shift register 117.
  • the other ends of all branch lines 116 are connected to the third circuit board 114 through the main line 115 .
  • Some of the electrical signals required by the multiple shift registers 117 (such as the low-voltage signal VGL, the high-voltage signal VGH, and the reset signal Total reset) are the same.
  • the present disclosure can use the main line 115 to transfer an electrical signal (such as the low-voltage signal) provided by the third circuit board 114 to signal VGL) is transmitted to multiple branch lines 116, so that the electrical signal is divided into multiple electrical signals (i.e., one ), and then transmitted to the corresponding shift register 117 through the branch line 116.
  • two sixth leads 118 may also be included.
  • One end of the two sixth leads 118 is connected to two ends of the total reference line 104 respectively.
  • the ends are integrally provided, and the other ends of the two sixth leads 118 are respectively connected to the ends of the outermost two first circuit boards 103 away from the isolation area S in the arrangement direction of each first binding area BD 1 to increase
  • the connection path between the main reference line 104 and each first circuit board 103 ensures that the reference signal provided by the first circuit board 103 can be transmitted to the main reference line 104 smoothly.
  • all reference lines 119 of display area AA are connected to the total reference line 104 .
  • the display substrate can also be provided with multiple auxiliary cathodes 120 extending longitudinally in the display area AA.
  • Each auxiliary cathode 120 can correspond to a column of light-emitting devices in the sub-pixels, and the auxiliary cathodes 120 and The cathode is electrically connected, and the auxiliary cathode 120 can effectively reduce the resistance of the cathode and reduce the voltage drop.
  • the auxiliary cathode 120 is located on the second source-drain metal layer (SD 2 ).
  • multiple initialization signal lines 121 can also be provided in the display area AA. Each initialization signal line 121 can initialize the pixel circuit of a column of sub-pixels to release residual charges and ensure that the pixel circuit is normal. Work.
  • the pixel circuit may include a driving transistor Td , a storage capacitor Cst , etc.
  • the gate g of the driving transistor Td is on the same layer as the first electrode plate C1 of the storage capacitor Cst .
  • the active layer a of the driving transistor T d is located between the layer where the gate g is located (i.e., the first gate metal layer GT 1 ) and the base substrate 101 , and the layer where the second electrode plate C 2 of the storage capacitor C st is located.
  • the light-emitting device further includes a light-emitting functional layer 124 and a cathode 125.
  • the light-emitting functional layer 124 includes but is not limited to a hole injection layer, a hole transport layer, an electron blocking layer, a luminescent material layer, a hole blocking layer, and an electron transport layer. and electron injection layer.
  • the display substrate may further include a buffer layer 126, a first insulating layer 127, a second insulating layer 128, The interlayer dielectric layer 129, the first planarization layer 130, the third insulating layer 131, the second planarization layer 132, the pixel definition layer 133 and so on.
  • Other essential components of the display substrate are understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used to limit the present disclosure.
  • the method for manufacturing the above-mentioned display substrate provided by the embodiment of the present disclosure may include the following steps:
  • a buffer layer 126 is formed on the base substrate 101.
  • the base substrate 101 can be 50 ⁇ m to 1000 ⁇ m thick Corning or Asahi glass, or quartz glass, etc.
  • the buffer layer 126 can be a single layer or a stacked layer.
  • the material of the buffer layer 126 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), etc.
  • the thickness of the buffer layer 126 may be 150 ⁇ m to 500 ⁇ m.
  • an amorphous silicon film with a thickness of 20 nm to 100 nm is formed on the buffer layer 126, and laser crystallization is used to change the amorphous silicon film into a polysilicon film, and patterning is performed to form an active layer a made of polysilicon; optionally , the active layer a may be the active layer of each transistor in the pixel circuit or the shift register 117 .
  • a first insulating layer 127 is formed on the active layer a.
  • the first insulating layer 127 can be a single layer or a stacked structure.
  • the material of the first insulating layer 127 can include silicon oxide (SiO x ), nitride Silicon (SiN x ), silicon oxynitride (SiO x N y ), etc., the thickness of the first insulating layer 127 may be 100 nm to 200 nm.
  • the fourth step is to form a first gate metal film on the first insulating layer 127, pattern the first gate metal film and form a first gate metal layer GT 1 including the gate electrode g and the first electrode plate C 1 ; optional
  • the gate g may be the gate of each transistor in the pixel circuit or the shift register 117 .
  • the fifth step is to form a second insulating layer 128 on the first gate metal layer GT 1 .
  • the second insulating layer 128 may be a single layer or a stacked structure.
  • the material of the second insulating layer 128 may include silicon oxide (SiO x ). , silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), etc., the thickness of the second insulating layer 128 may be 100 nm to 200 nm.
  • a second gate metal film is formed on the second insulating layer 128 , and the second gate metal film is patterned to form a second gate metal layer GT 2 including the second electrode plate C 2 and the initialization signal line 121 .
  • an interlayer dielectric layer 129 with via holes is formed on the second gate metal layer GT 2 , and during the formation of the interlayer dielectric layer 129 , the first insulating layer 127 and the second insulating layer can be formed simultaneously.
  • a via hole is formed in 128 that is connected to the via hole, so that the subsequently produced source electrode s/drain electrode d passes through the first insulating layer. 127.
  • Via-hole contact connection between the second insulating layer 128 and the interlayer dielectric layer 129; at the same time, the gate electrode g and the second gate electrode between the source electrode s/drain electrode and the first gate metal layer GT 1 can also be obtained.
  • the interlayer dielectric layer 129 can be a single layer or a stacked structure, and the material of the interlayer dielectric layer 129 can include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), etc.
  • a first source-drain metal film is formed on the interlayer dielectric layer 129, and the first source-drain metal film is patterned to form a source electrode s, a drain electrode d, a reference line 119, a general reference line 104, a
  • the material of 1 can be aluminum (Al), molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), etc., with a thickness of 200nm to 1000nm.
  • the first source and drain metal layer SD 1 can be made of titanium metal.
  • the third insulating layer 130 is formed on the first flat layer 129.
  • the first flat layer 129 and the third The third insulating layer 130 has a via hole for connecting the transfer electrode 122 and the drain d of the driving transistor T d ; optionally, the third insulating layer 130 can be a single layer or a stacked layer structure.
  • Materials may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), etc.
  • a second source-drain metal film is formed on the third insulating layer 130, and the second source-drain metal film is patterned to form a transfer electrode 122, a second power bus 106, and an integrated structure with the second power bus 106.
  • the second source and drain metal layer Layer SD 2 may be a stacked structure composed of titanium metal layer/aluminum metal layer/titanium metal layer.
  • a second planar layer 129 with a thickness of 1.5 ⁇ m to 3 ⁇ m is formed on the second source-drain metal layer SD 2 .
  • the second planar layer 129 includes a via hole for connecting the transfer electrode 122 and the anode 123 .
  • the anode 123 of the light-emitting device is formed on the second flat layer.
  • the anode 123 can be an inverse Radiation-type anode, its materials may include aluminum (Al), molybdenum (Mo), copper (Cu), silver (Ag), indium tin oxide (ITO), etc., for example, the anode 123 has an indium tin oxide layer/silver metal layer/ In a three-layer structure composed of indium tin oxide layers, the thickness of the anode 123 is 70 nm to 200 nm; optionally, while forming the anode 123, the first power bus 102, the first lead 51, and the fourth lead 112 can be formed.
  • a pixel defining layer 133 with a pixel opening is formed on the layer where the anode 123 is located.
  • the pixel opening exposes the anode 123, and the pixel defining layer 133 also has a path connecting the first power bus 102 and the subsequently fabricated cathode 125. hole; optionally, the thickness of the pixel defining layer 133 is 1.5 ⁇ m ⁇ 2.0 ⁇ m.
  • Step 14 Form a light-emitting functional layer 124 at the pixel opening.
  • the light-emitting functional layer 124 includes but is not limited to a hole injection layer, a hole transport layer, an electron blocking layer, a luminescent material layer, a hole blocking layer, an electron transport layer, and electron injection layer.
  • a cathode 125 is formed on the entire surface of the light-emitting functional layer 124 , and the cathode is electrically connected to the first power bus 102 .
  • an embodiment of the present disclosure provides a display device, including the above-mentioned display substrate provided by the embodiment of the present disclosure. Since the principle of solving the problem of the display device is similar to the principle of solving the problem of the above-mentioned display substrate, the present disclosure implements
  • the display device provided by the embodiments of the present disclosure, reference may be made to the implementation of the above-mentioned display substrate provided by the embodiments of the present disclosure, and repeated details will not be described again.
  • the above-mentioned display device provided by the embodiment of the present disclosure can be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any other device with A product or component that displays functionality.
  • the above-mentioned display device provided by the embodiment of the present disclosure may include but is not limited to: a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a control chip and other components.
  • the control chip is a central processing unit, a digital signal processor, a system on chip (SoC), etc.
  • control chip may also include a memory, a power module, etc., and realize power supply and signal input and output functions through additional wires, signal lines, etc.
  • control chip may also include hardware circuits and computer executable codes.
  • Hardware circuits may include conventional very large scale integration (VLSI) circuits or gate arrays as well as existing semiconductors such as logic chips, transistors, or other discrete components; hardware circuits may also include field programmable gate arrays, programmable array logic, Can Programming logic devices, etc.
  • VLSI very large scale integration
  • programmable gate arrays programmable array logic
  • Can Programming logic devices etc.
  • the above structure does not constitute a limitation on the above display device provided by the embodiment of the present disclosure.
  • the above display device provided by the embodiment of the present disclosure may include more or less of the above. components, or combinations of certain components, or different arrangements of components.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

本公开提供的显示基板及显示装置，包括衬底基板，该衬底基板包括显示区、以及位于显示区一侧的第一边框区；第一电源总线，至少位于第一边框区，第一电源总线包括第一子总线、第二子总线和至少两条连接线，第一子总线位于第二子总线与显示区之间，且第一子总线通过至少两条连接线与第二子总线电连接。

Description

显示基板及显示装置
相关申请的交叉引用
本申请要求在2022年07月22日提交中国专利局、申请号为202210871553.9、申请名称为“显示基板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及显示装置。
背景技术
近年来，有机电致发光显示器(OLED)作为一种新型的平板显示逐渐受到更多的关注。由于其具有主动发光、发光亮度高、分辨率高、视角广、响应速度快、厚度小、低能耗、可柔性化、使用温度范围广、构造及制程较简单等优异特性等特点，应用前景广阔。
发明内容
本公开实施例提供的显示基板及显示装置，具体方案如下：
一方面，本公开实施例提供的一种显示基板，包括：
衬底基板，所述衬底基板包括显示区、以及位于所述显示区一侧的第一边框区；
第一电源总线，至少位于所述第一边框区，所述第一电源总线包括第一子总线、第二子总线和至少两条连接线，所述第一子总线位于所述第二子总线与所述显示区之间，且所述第一子总线通过所述至少两条连接线与所述第二子总线电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第一边 框区包括至少一个第一绑定区，所述第一绑定区用于绑定第一电路板；
所述显示基板还包括位于所述第一边框区的总参考线和至少一个引线组，以及至少位于所述第一边框区的第二电源总线，所述引线组与所述第一电路板电连接，所述引线组包括第一引线、第二引线和第三引线，其中，所述第一引线与所述第一电源总线一体设置，所述第二引线与所述第二电源总线一体设置，所述第三引线与所述总参考线一体设置，所述第三引线在所述衬底基板上的正投影位于所述第一引线在所述衬底基板上的正投影与所述第二引线在所述衬底基板上的正投影之间。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第一边框区包括并排设置的多个所述第一绑定区、以及位于所述第一绑定区之间的间隔区，所述引线组为多个，每个所述引线组与所述第一电路板邻接所述间隔区的一个端部电连接，且所述引线组朝向靠近所述间隔区的方向延伸。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第二引线与所述间隔区的距离、所述第三引线与所述间隔区的距离、以及所述第一引线与所述间隔区的距离依次减小。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述第一边框区的扇出线，所述扇出线连接在所述显示区与所述第一电路板之间，所述扇出线与所述第二引线同层、同材料设置。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括与所述扇出线同层、同材料设置的多条浮空线，所述多条浮空线位于所述扇出线与所述第二引线之间。
在一些实施例中，在本公开实施例提供的上述显示基板中，在由所述扇出线指向所述第二引线的方向上，各所述浮空线的线宽、线距逐渐增大。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述衬底基板还包括与所述第一边框区相对而置的第二边框区，以及分别连接所述第一边框区、所述第二边框区的第三边框区和第四边框区，所述第二边框区包括第二绑定区，所述第二绑定区用于绑定第二电路板；
所述第一电源总线设置于所述第一边框区、所述第二边框区、所述第三边框区和所述第四边框区，所述第二边框区的所述第一电源总线与所述第二电路板电连接，所述第三边框区的所述第一电源总线、以及所述第四边框区的所述第一电源总线与所述第一电路板电连接，且所述第二边框区、所述第三边框区和所述第四边框区的第一电源总线一体设置。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第二电源总线还设置于所述第二边框区，且所述第二电源总线与所述第二电路板电连接；
所述显示基板还包括位于所述显示区的电源线，所述电源线的一端与所述第一边框区的所述第二电源总线电连接，所述电源线的另一端与所述第二边框区的所述第二电源总线电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述第二边框区的多条第四引线和多条第五引线，其中，所述多条第四引线连接在所述第一电源总线与所述第二电路板之间，所述多条第五引线连接在所述第二电源总线与所述第二电路板之间，各所述第四引线在所述衬底基板上的正投影与各所述第五引线在所述衬底基板上的正投影交替设置。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第三边框区和/或所述第四边框区包括与所述第一边框区并排设置的第三绑定区，所述第三绑定区用于绑定第三电路板；
在所述第三边框区和/或所述第四边框区内，所述显示基板包括：主干线、多条分支线、以及级联设置的多个移位寄存器，每条所述分支线的一端与一个所述移位寄存器对应电连接，全部所述分支线的另一端通过所述主干线连接至所述第三电路板。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括两条第六引线，两条所述第六引线的一端分别与所述总参考线的两端一体设置，且两条所述第六引线的另一端分别连接至在各所述第一绑定区的排列方向上的最外侧两个所述第一电路板远离所述隔离区的端部。
在一些实施例中，在本公开实施例提供的上述显示基板中，在远离所述显示区的方向上，所述第一子总线、所述总参考线、所述第二电源总线、所述第二子总线依次设置。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第二电源总线所在层位于所述总参考线所在层与所述第一电源总线所在层之间。
另一方面，本公开实施例提供了一种显示装置，包括本公开实施例提供的上述显示基板。
附图说明
图1为本公开实施例提供的显示基板的结构示意图；
图2为图1中M区的放大示意图；
图3为图1中N区的放大示意图；
图4为本公开实施例提供的一个子像素的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。为了保持本公开实施例的以下说明清楚且简明，本公开省略了已知功能和已知部件的详细说明。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表 示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
随着电子产品的更新换代，中尺寸的OLED显示装置渐成热点，这是由于OLED显示装置具有高对比度、自发光等优势，且相较于小尺寸屏幕，中尺寸的显示屏幕能给使用者提供丰富的信息，提高人机交流的效率，带来更好的使用体验。
针对中尺寸OLED显示装置越来越复杂的性能要求，其所含像素电路也越来越复杂，例如相关技术中采用了可降分辨率提高刷新频率的6T1C及类似内部补偿像素电路。复杂的像素电路对应的制作工艺流程更多，工艺要求更为严格，实际产品制作中，各种不良概率都大大增加，为了保证良率，维修工序必不可少。电源总线可为像素电路和发光器件提供电源信号，以实现画面显示，因此，电源总线的良率尤为重要。
基于此，本公开实施例提供的一种显示基板，如图1所示，包括：
衬底基板101，该衬底基板101包括显示区AA、以及位于显示区AA一侧的第一边框区BB1；
第一电源总线102，至少位于第一边框区BB1，第一电源总线102包括第一子总线21、第二子总线22和至少两条连接线23，第一子总线21位于第二子总线22与显示区AA之间，且第一子总线21通过至少两条连接线23与第二子总线22电连接。可选地，第一电源总线102可以为高电平(VDD)电源总线或低电平(VSS)电源总线，本公开中以第一电源总线102是低电平电源总线为例进行说明。各连接线23可以平行设置在第一子总线21与第二子总线22之间，或者，各连接线23交叉设置成网状结构连接在第一子总线21与第二子总线22之间。
在本公开实施例提供的上述显示基板中，通过将第一电源总线102设置为包括第一子总线21和第二子总线22的双总线结构，并采用至少两条连接线23将第一子总线21与第二子总线22连接在一起，使得在第一子总线21出现断路(Open)的情况下，断开的第一子总线21仍可通过连接线23、第 二子总线22保持正常的信号传输性能；在第一子总线21因金属残留(Particle)与其他元件(例如总参考线)之间发生短路(short)的情况下，可通过激光切割等方式将金属残留所在位置的第一子总线21与金属残留周围的第一子总线21断开来解决短路问题，并且断开的第一子总线21仍可通过连接线23、第二子总线22保持正常的信号传输性能。同理，在第二子总线22、连接线23发生断路或与其他元件发生短路的情况下，也可以保证第一电源总线102的信号传输性能。因此，本公开提高了第一电源总线102的良率。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图1所示，第一边框区BB1包括至少一个第一绑定区BD1，第一绑定区BD1用于绑定第一电路板103，可选地，第一电路板103可以为具有芯片(IC)的覆晶薄膜(COF)；显示基板还可以包括位于第一边框区BB1的总参考线104和至少一个引线组105，以及至少位于第一边框区BB1的第二电源总线106，可选地，为便于布线，可以在远离显示区AA的方向上，依次设置第一子总线21、总参考线104、第二电源总线106、第二子总线22；第二电源总线106所在层(例如第二源漏金属层SD2)位于总参考线104所在层(例如第一源漏金属层SD1)与第一电源总线102所在层(例如阳极所在层)之间。引线组105可以与第一电路板103电连接，且引线组105可以包括第一引线51、第二引线52和第三引线53，其中，第一引线51与第一电源总线102一体设置，第二引线52与第二电源总线106一体设置，第三引线53与总参考线104一体设置，第三引线53在衬底基板101上的正投影位于第一引线51在衬底基板101上的正投影与第二引线52在衬底基板101上的正投影之间。
结合图2可见，为降低功耗，第一引线51、第二引线52和第三引线53的线宽均较大，但较大的线宽导致相邻引线之间的距离较小。由于第一引线51与第一电源总线102一体设置，第二引线52与第二电源总线106一体设置，因此，第一引线51与第一电源总线102传输相同的电信号，第二引线52与第二电源总线106传输相同的电信号。在本公开中第一电源总线102和第二电源总线106分别为低电平电源总线和高电平电源总线，二者之间的电压差 较大，相当于第一引线51与第二引线52之间的电压差较大，在第一引线51与第二引线52之间距离较小的情况下，可能存在高压击穿二者之间的绝缘层而导致二者短接的风险。考虑到总参考线104的电压值在第一电源总线102的电压值与第二电源总线106的电压值之间，因此本公开将第三引线53(与总参考线104传输相同的电信号)在衬底基板101上的正投影位于第一引线51在衬底基板101上的正投影与第二引线52在衬底基板101上的正投影之间，可以使得相邻引线间的电压差较小，由此降低了因高压差导致的短接风险。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图1所示，第一边框区BB1包括并排设置的多个第一绑定区BD1、以及位于第一绑定区BD1之间的间隔区S，引线组105为多个，每个引线组105与第一电路板103邻接间隔区S的一个端部电连接，且引线组105朝向靠近间隔区S的方向延伸。由于在间隔区S及其附近的布线空间较大，因此为降低功耗，可在该布线空间内设置线宽较大的引线组105，使得引线组105与第一电路板103邻接间隔区S的一个端部，并保证引线组105朝向靠近间隔区S的方向延伸。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图1所示，第二引线52与间隔区S的距离、第三引线53与间隔区S的距离、以及第一引线51与间隔区S的距离依次减小，换句话所，就是第一引线51靠近间隔区S设置，第二引线52远离间隔区S设置。本公开中以第一电源总线102为低电平电源线为例进行说明，而低电平电源线通常与发光器件的阴极电连接，可选地，低电平电源线与反射型阳极同层、同材料设置，并通过贯穿像素界定层(PDL)的过孔与阴极电连接。为实现稳定的电连接效果，需保证低电平电源线的线宽较大。本公开中第一引线51靠近间隔区S设置的情况下，可充分利用间隔区S及其靠近第一电源总线102一侧的空间布设线宽较大的第一引线51(如图2所示)，从而利用第一引线51与阴极电连接，实现与第一引线51一体设置的第一电源总线102与阴极的稳定连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图1和图3所示，还包括位于第一边框区BB1的扇出线107，扇出线107连接在显示区 AA与第一电路板103之间，可选地，扇出线107的一端与显示区AA的数据线108一体设置，扇出线107的另一端与第一电路板103的中间部电连接。
在一些实施例中，扇出线107与第二引线52可以同层、同材料设置，可选地，扇出线107与第二引线52可采用第二源漏金属层(SD2)的材料制备。在本公开中，“同层、同材料”指的是采用同一成膜工艺形成用于制作特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。即一次构图工艺对应一道掩模板(mask，也称光罩)。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而所形成层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形可能处于相同的高度或者具有相同的厚度、也可能处于不同的高度或者具有不同的厚度。可见，将扇出线107与第二引线52同层、同材料设置的情况下，可节约一道掩膜工艺，减少膜层数量，降低生产成本。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图3所示，还可以包括与扇出线107同层、同材料设置的多条浮空线109(即未加载任何信号)，多条浮空线109位于扇出线107与第二引线52之间。掩膜版的图案设计稀疏或者无图案设计时，会有大面积的感光胶显影，产生高密度的催化剂；而掩膜版的图案设计密集时，感光胶显影面积较小，产生低密度的催化剂。由于渗透作用，低密度区的催化剂密度受高密度区催化剂密度的影响会逐渐变高，影响了低密度区的显影过程。由图3可以看出，在不设置浮空线109的情况下，扇出线107和第二引线52的图案(对应掩膜版的图案设计区)密集，扇出线107与第二引线52之间的空白区(对应掩膜版的无图案区)较大，显影过程中该空白区的催化剂密度会大于扇出线107所在区和第二引线52所在区的催化剂密度，由于渗透作用，扇出线107所在区和第二引线52所在区的催化剂密度会增大，从而对扇出线107和第二引线52造成过度显影，而较细的扇出线107被过度显影后可能产生断线。本公开中通过在扇出线107与第二引线52之间设置多条浮空线109，可减小显影过程中的催化剂密度差异，降低扇出线107的断线概率。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图3所示，在由扇出线107指向第二引线52的方向上，各浮空线109的线宽、线距逐渐增大，使得显影过程中，在由扇出线107指向第二引线52的方向上，催化剂密度具有渐变的趋势，而不至于发生密度突变，可有效提高防断线的效果。可选地，浮空线109的最小线宽大于扇出线107的线宽，浮空线109的最大线宽小于第二引线52的线宽。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图1所示，衬底基板101还可以包括与第一边框区BB1相对而置的第二边框区BB2，以及分别连接第一边框区BB1、第二边框区BB2的第三边框区BB3和第四边框区BB4，第二边框区BB2包括第二绑定区BD2，第二绑定区BD2用于绑定第二电路板110，可选地，第二电路板110为柔性电路板(FPC)；第一电源总线101设置于第一边框区BB1、第二边框区BB2、第三边框区BB3和第四边框区BB4，第二边框区BB2的第一电源总线102与第二电路板110电连接，第三边框区BB3的第一电源总线102、以及第四边框区BB4的第一电源总线102与第一电路板103电连接，且第二边框区BB2、第三边框区BB3和第四边框区BB4的第一电源总线102一体设置。显示基板的显示区AA内包括阵列排布的多个像素，例如图1示出了两个像素，每个像素包括红色子像素R、绿色子像素G和蓝色子像素B。在每个子像素内包括一个发光器件，各发光器件的阴极一体设置形成面状电极，该面状电极覆盖至边框区，并在边框区与第一电源总线102电连接。通过在第一边框区BB1、第二边框区BB2内分别对第一电源总线102进行供电(即双边供电)，可减小阴极上的压降，提高阴极上信号的均匀性，进而利于各发光器件的均匀出光，增强亮度均一性。因中大尺寸产品中，阴极的压降较大，故本公开的双边供电方案尤其适用于中大尺寸产品。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图1所示，第二电源总线106还可以设置于所第二边框区BB2，且第二电源总线106与第二电路板110电连接；显示基板还包括位于显示区AA的电源线111，第二电 源线106的一端与第一边框区BB1的第二电源总线106电连接，电源线106的另一端与第二边框区BB2的第二电源总线106电连接，以降低电源线111上的压降，保证电源线111为同列子像素所含像素电路提供的电源信号幅值大致相同，避免压降对像素电路提给发光器件的工作电流的影响，增强亮度均一性。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图1所示，还可以包括位于第二边框区BB2的多条第四引线112和多条第五引线113，其中，多条第四引线112连接在第一电源总线102与第二电路板110之间，多条第五引线113连接在第二电源总线106与第二电路板110之间，各第四引线112在衬底基板101上的正投影与各第五引线113在衬底基板101上的正投影交替设置，即第四引线112在衬底基板101上的正投影与第五引线113在衬底基板101上的正投影互不交叠。因第四引线112可与第一电源总线102一体设置，第五引线113可与第二电源总线106一体设置，故在第四引线112在衬底基板101上的正投影与第五引线113在衬底基板101上的正投影互不交叠的情况下，相当于减小了第一电源总线102与第二电源总线106之间的交叠电容，可有效防止第一电源总线102与第二电源总线106上的信号相互干扰。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图1所示，第三边框区BB3和/或第四边框区BB4包括与第一边框区BB1并排设置的第三绑定区BD3，第三绑定区BD3用于绑定第三电路板114，可选地，第三电路板114为柔性电路板(FPC)；在第三边框区BB3和/或第四边框区BB4内，显示基板包括：主干线115、多条分支线116、以及级联设置的多个移位寄存器117，每条分支线116的一端与一个移位寄存器117对应电连接，全部分支线116的另一端通过主干线115连接至第三电路板114。多个移位寄存器117所需的部分电信号(例如低压信号VGL、高压信号VGH、复位信号Total reset)相同，本公开通过主干线115可将第三电路板114提供的一个电信号(例如低压信号VGL)传输至多个分支线116，使得该电信号分为多个电信号(即一 分多)，进而由分支线116传输至对应的移位寄存器117，这样避免了第三电路板114分别通过不同引脚(pin)为各移位寄存器117提供相同的电信号，由此，可简化电路板114的结构，利于降低成本。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图1所示，还可以包括两条第六引线118，两条第六引线118的一端分别与总参考线104的两端一体设置，且两条第六引线118的另一端分别连接至在各第一绑定区BD1的排列方向上的最外侧两个第一电路板103远离隔离区S的端部，以增加总参考线104与各第一电路板103的连接路径，保证第一电路板103提供的参考信号可顺利传输至总参考线104。可选地，显示区AA的全部参考线119连接至总参考线104。
在一些实施例中，如图1所示，显示基板还可以在显示区AA内设置纵向延伸的多个辅助阴极120，每条辅助阴极120可以对应一列子像素内发光器件，且辅助阴极120与阴极电连接，辅助阴极120可有效降低阴极的电阻，减小压降。可选地，辅助阴极120位于第二源漏金属层(SD2)。可选地，如图1所示，在显示区AA内还可以设置多个初始化信号线121，每个初始化信号线121可以对一列子像素的像素电路进行初始化来释放残留电荷，保证像素电路正常工作。
在一些实施例中，如图4所示，像素电路可以包括驱动晶体管Td、存储电容Cst等，驱动晶体管Td的栅极g与存储电容Cst的第一电极板C1同层、同材料设置，驱动晶体管Td的有源层a位于栅极g所在层(即第一栅金属层GT1)与衬底基板101之间，存储电容Cst的第二电极板C2所在层(即第二栅金属层GT2)位于驱动晶体管Td的源极s/漏极d所在层(即第一源漏金属层SD1)与栅极g所在层之间，驱动晶体管Td的漏极d可以通过第二源漏金属层(SD2)转接电极122与发光器件的阳极123电连接。可选地，发光器件还包括发光功能层124和阴极125，发光功能层124包括但不限于空穴注入层、空穴传输层、电子阻挡层、发光材料层、空穴阻挡层、电子传输层和电子注入层。可选地，显示基板还可以包括缓冲层126、第一绝缘层127、第二绝缘层128、 层间介电层129、第一平坦层130、第三绝缘层131、第二平坦层132和像素界定层133等。对于显示基板的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
可选地，本公开实施例提供的上述显示基板的制作方法可以包括以下步骤：
第一步，在衬底基板101上形成缓冲层126，可选地，衬底基板101可以为50μm～1000μm厚的康宁或旭硝子玻璃、或石英玻璃等，缓冲层126可以为单层或叠层结构，缓冲层126的材料可以包括氧化硅(SiOx)、氮化硅(SiNx)、氮氧化硅(SiOxNy)等，缓冲层126的厚度可为150μm～500μm。
第二步，在缓冲层126上形成厚度为20nm～100nm的非晶硅薄膜，并采用激光晶化方式将非晶硅薄膜变成多晶硅薄膜，构图形成多晶硅材质的有源层a；可选地，有源层a可以为像素电路、移位寄存器117中各晶体管的有源层。
第三步，在有源层a上形成在第一绝缘层127，第一绝缘层127可以为单层或叠层结构，第一绝缘层127的材料可以包括氧化硅(SiOx)、氮化硅(SiNx)、氮氧化硅(SiOxNy)等，第一绝缘层127的厚度可为100nm～200nm。
第四步，在第一绝缘层127上形成第一栅金属膜，并对第一栅金属膜构图后形成包括栅极g和第一电极板C1的第一栅金属层GT1；可选地，该栅极g可以为像素电路、移位寄存器117中各晶体管的栅极。
第五步，在第一栅金属层GT1上形成在第二绝缘层128，第二绝缘层128可以为单层或叠层结构，第二绝缘层128的材料可以包括氧化硅(SiOx)、氮化硅(SiNx)、氮氧化硅(SiOxNy)等，第二绝缘层128的厚度可为100nm～200nm。
第六步，在第二绝缘层128上形成第二栅金属膜，并对第二栅金属膜构图后形成包括第二电极板C2和初始化信号线121的第二栅金属层GT2。
第七步，在第二栅金属层GT2上形成具有过孔的层间介电层129，且在形成层间介电层129的过程中可同时在第一绝缘层127和第二绝缘层128中形成与该过孔导通的通孔，使得后续制作的源极s/漏极d通过贯穿第一绝缘层 127、第二绝缘层128和层间介电层129的过孔接触连接；与此同时，还可以得到源极s/漏极d与第一栅金属层GT1的栅极g、第二栅金属层GT2的第二电极板C2连接的过孔；可选地，层间介电层129可以为单层或叠层结构，层间介电层129的材料可以包括氧化硅(SiOx)、氮化硅(SiNx)、氮氧化硅(SiOxNy)等。
第八步，在层间介电层129上形成第一源漏金属膜，并对第一源漏金属膜构图后形成包括源极s、漏极d、参考线119、总参考线104、第三引线53、第六引线118、主干线115、分支线116、以及包括栅线(Gate line)的横向信号线的第一源漏金属层SD1；可选地，第一源漏金属层SD1的材料可以为铝(Al)、钼(Mo)、铬(Cr)、铜(Cu)、钛(Ti)等，厚度为200nm～1000nm，第一源漏金属层SD1可为由钛金属层/铝金属层/钛金属层构成的叠层结构；可选地，源极s、漏极d可以为像素电路、移位寄存器117中各晶体管的栅极。
第九步，在第一源漏金属层SD1上形成厚度为1.5μm～3μm的第一平坦层129之后，在第一平坦层129上形成第三绝缘层130，第一平坦层129和第三绝缘层130中具有用于连接转接电极122与驱动晶体管Td的漏极d的过孔；可选地，第三绝缘层130可以为单层或叠层结构，第三绝缘层130的材料可以包括氧化硅(SiOx)、氮化硅(SiNx)、氮氧化硅(SiOxNy)等。
第十步，在第三绝缘层130上形成第二源漏金属膜，并对第二源漏金属膜构图后形成包括转接电极122、第二电源总线106、与第二电源总线106一体设置的第二引线52、第五引线113、浮空线109、辅助电极120、扇出线107、以及包括数据线108和电源线111等纵向信号线的第二源漏金属层SD2；可选地，第二源漏金属层SD2的材料可以为铝(Al)、钼(Mo)、铬(Cr)、铜(Cu)、钛(Ti)等，厚度为200nm～1000nm，第二源漏金属层SD2可为由钛金属层/铝金属层/钛金属层构成的叠层结构。
第十一步，在第二源漏金属层SD2上形成厚度为1.5μm～3μm的第二平坦层129，第二平坦层129包括用于连接转接电极122与阳极123的过孔。
第十二步，在第二平坦层上形成发光器件的阳极123，该阳极123可为反 射型阳极，其材料可包括铝(Al)、钼(Mo)、铜(Cu)、银(Ag)和氧化铟锡(ITO)等，例如阳极123具有由氧化铟锡层/银金属层/氧化铟锡层构成的三叠层结构，阳极123的厚度为70nm～200nm；可选地，在形成阳极123的同时，可形成第一电源总线102、第一引线51、第四引线112。
第十三步，在阳极123所在层上形成具有像素开口的像素界定层133，像素开口暴露出阳极123，并且，像素界定层133还具有连接第一电源总线102与后续制作的阴极125的过孔；可选地，像素界定层133的厚度为1.5μm～2.0μm。
第十四步，在像素开口处形成发光功能层124，发光功能层124包括但不限于空穴注入层、空穴传输层、电子阻挡层、发光材料层、空穴阻挡层、电子传输层和电子注入层。
第十五步，在发光功能层124上形成整面设置的阴极125，阴极与第一电源总线102电连接。
基于同一发明构思，本公开实施例提供了一种显示装置，包括本公开实施例提供的上述显示基板，由于该显示装置解决问题的原理与上述显示基板解决问题的原理相似，因此，本公开实施例提供的该显示装置的实施可以参见本公开实施例提供的上述显示基板的实施，重复之处不再赘述。
在一些实施例中，本公开实施例提供的上述显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、智能手表、健身腕带、个人数字助理等任何具有显示功能的产品或部件。且本公开实施例提供的上述显示装置可以包括但不限于：射频单元、网络模块、音频输出&输入单元、传感器、显示单元、用户输入单元、接口单元以及控制芯片等部件。可选地，控制芯片为中央处理器、数字信号处理器、系统芯片(SoC)等。例如，控制芯片还可以包括存储器，还可以包括电源模块等，且通过另外设置的导线、信号线等实现供电以及信号输入输出功能。例如，控制芯片还可以包括硬件电路以及计算机可执行代码等。硬件电路可以包括常规的超大规模集成(VLSI)电路或者门阵列以及诸如逻辑芯片、晶体管之类的现有半导体或者其它分立的元件；硬件电路还可以包括现场可编程门阵列、可编程阵列逻辑、可 编程逻辑设备等。另外，本领域技术人员可以理解的是，上述结构并不构成对本公开实施例提供的上述显示装置的限定，换言之，在本公开实施例提供的上述显示装置中可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。
尽管本公开已描述了优选实施例，但应当理解的是，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (15)

  1. 一种显示基板，其中，包括：
    衬底基板，所述衬底基板包括显示区、以及位于所述显示区一侧的第一边框区；
    第一电源总线，至少位于所述第一边框区，所述第一电源总线包括第一子总线、第二子总线和至少两条连接线，所述第一子总线位于所述第二子总线与所述显示区之间，且所述第一子总线通过所述至少两条连接线与所述第二子总线电连接。
  2. 如权利要求1所述的显示基板，其中，所述第一边框区包括至少一个第一绑定区，所述第一绑定区用于绑定第一电路板；
    所述显示基板还包括位于所述第一边框区的总参考线和至少一个引线组，以及至少位于所述第一边框区的第二电源总线，所述引线组与所述第一电路板电连接，所述引线组包括第一引线、第二引线和第三引线，其中，所述第一引线与所述第一电源总线一体设置，所述第二引线与所述第二电源总线一体设置，所述第三引线与所述总参考线一体设置，所述第三引线在所述衬底基板上的正投影位于所述第一引线在所述衬底基板上的正投影与所述第二引线在所述衬底基板上的正投影之间。
  3. 如权利要求2所述的显示基板，其中，所述第一边框区包括并排设置的多个所述第一绑定区、以及位于所述第一绑定区之间的间隔区，所述引线组为多个，每个所述引线组与所述第一电路板邻接所述间隔区的一个端部电连接，且所述引线组朝向靠近所述间隔区的方向延伸。
  4. 如权利要求3所述的显示基板，其中，所述第二引线与所述间隔区的距离、所述第三引线与所述间隔区的距离、以及所述第一引线与所述间隔区的距离依次减小。
  5. 如权利要求4所述的显示基板，其中，还包括位于所述第一边框区的扇出线，所述扇出线连接在所述显示区与所述第一电路板之间，所述扇出线 与所述第二引线同层、同材料设置。
  6. 如权利要求5所述的显示基板，其中，还包括与所述扇出线同层、同材料设置的多条浮空线，所述多条浮空线位于所述扇出线与所述第二引线之间。
  7. 如权利要求6所述的显示基板，其中，在由所述扇出线指向所述第二引线的方向上，各所述浮空线的线宽、线距逐渐增大。
  8. 如权利要求3～7任一项所述的显示基板，其中，所述衬底基板还包括与所述第一边框区相对而置的第二边框区，以及分别连接所述第一边框区、所述第二边框区的第三边框区和第四边框区，所述第二边框区包括第二绑定区，所述第二绑定区用于绑定第二电路板；
    所述第一电源总线设置于所述第一边框区、所述第二边框区、所述第三边框区和所述第四边框区，所述第二边框区的所述第一电源总线与所述第二电路板电连接，所述第三边框区的所述第一电源总线、以及所述第四边框区的所述第一电源总线与所述第一电路板电连接，且所述第二边框区、所述第三边框区和所述第四边框区的第一电源总线一体设置。
  9. 如权利要求8所述的显示基板，其中，所述第二电源总线还设置于所述第二边框区，且所述第二电源总线与所述第二电路板电连接；
    所述显示基板还包括位于所述显示区的电源线，所述电源线的一端与所述第一边框区的所述第二电源总线电连接，所述电源线的另一端与所述第二边框区的所述第二电源总线电连接。
  10. 如权利要求9所述的显示基板，其中，还包括位于所述第二边框区的多条第四引线和多条第五引线，其中，所述多条第四引线连接在所述第一电源总线与所述第二电路板之间，所述多条第五引线连接在所述第二电源总线与所述第二电路板之间，各所述第四引线在所述衬底基板上的正投影与各所述第五引线在所述衬底基板上的正投影交替设置。
  11. 如权利要求8～10任一项所述的显示基板，其中，所述第三边框区和/或所述第四边框区包括与所述第一边框区并排设置的第三绑定区，所述第三 绑定区用于绑定第三电路板；
    在所述第三边框区和/或所述第四边框区内，所述显示基板包括：主干线、多条分支线、以及级联设置的多个移位寄存器，每条所述分支线的一端与一个所述移位寄存器对应电连接，全部所述分支线的另一端通过所述主干线连接至所述第三电路板。
  12. 如权利要求3～11任一项所述的显示基板，其中，还包括两条第六引线，两条所述第六引线的一端分别与所述总参考线的两端一体设置，且两条所述第六引线的另一端分别连接至在各所述第一绑定区的排列方向上的最外侧两个所述第一电路板远离所述隔离区的端部。
  13. 如权利要求2～12任一项所述的显示基板，其中，在远离所述显示区的方向上，所述第一子总线、所述总参考线、所述第二电源总线、所述第二子总线依次设置。
  14. 如权利要求2～13任一项所述的显示基板，其中，所述第二电源总线所在层位于所述总参考线所在层与所述第一电源总线所在层之间。
  15. 一种显示装置，其中，包括如权利要求1～14任一项所述的显示基板。
PCT/CN2023/105766 2022-07-22 2023-07-04 显示基板及显示装置 WO2024017060A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210871553.9A CN115172428A (zh) 2022-07-22 2022-07-22 显示基板及显示装置
CN202210871553.9 2022-07-22

Publications (1)

Publication Number Publication Date
WO2024017060A1 true WO2024017060A1 (zh) 2024-01-25

Family

ID=83497154

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/105766 WO2024017060A1 (zh) 2022-07-22 2023-07-04 显示基板及显示装置

Country Status (2)

Country Link
CN (1) CN115172428A (zh)
WO (1) WO2024017060A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115172428A (zh) * 2022-07-22 2022-10-11 合肥京东方卓印科技有限公司 显示基板及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210375202A1 (en) * 2019-10-14 2021-12-02 Chengdu Boe Optoelectronics Technology Co., Ltd. Array substrate and display device
WO2021248489A1 (zh) * 2020-06-12 2021-12-16 京东方科技集团股份有限公司 显示基板及显示装置
WO2022061543A1 (zh) * 2020-09-22 2022-03-31 京东方科技集团股份有限公司 显示基板及显示装置
CN114582923A (zh) * 2020-11-30 2022-06-03 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN115172428A (zh) * 2022-07-22 2022-10-11 合肥京东方卓印科技有限公司 显示基板及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210375202A1 (en) * 2019-10-14 2021-12-02 Chengdu Boe Optoelectronics Technology Co., Ltd. Array substrate and display device
WO2021248489A1 (zh) * 2020-06-12 2021-12-16 京东方科技集团股份有限公司 显示基板及显示装置
WO2022061543A1 (zh) * 2020-09-22 2022-03-31 京东方科技集团股份有限公司 显示基板及显示装置
CN114582923A (zh) * 2020-11-30 2022-06-03 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN115172428A (zh) * 2022-07-22 2022-10-11 合肥京东方卓印科技有限公司 显示基板及显示装置

Also Published As

Publication number Publication date
CN115172428A (zh) 2022-10-11

Similar Documents

Publication Publication Date Title
US10978545B2 (en) Display substrate and manufacturing thereof, and display device
WO2023241490A1 (zh) 显示基板和显示装置
KR102443121B1 (ko) 디스플레이 패널 및 그 제조 방법 및 디스플레이 디바이스
WO2021237725A1 (zh) 显示基板和显示装置
WO2024012329A1 (zh) 显示基板及显示装置
WO2023206339A1 (zh) 显示基板及显示装置
WO2024017060A1 (zh) 显示基板及显示装置
KR20230015871A (ko) 디스플레이 패널 및 디스플레이 장치
WO2024027669A1 (zh) 显示基板及其制备方法、显示装置
WO2024114073A1 (zh) 显示基板及显示装置
WO2022160491A1 (zh) 显示基板及其制备方法、显示装置
US11997903B2 (en) Display substrate and preparation method thereof, and display apparatus
WO2024046040A1 (zh) 显示面板和显示装置
WO2023226897A1 (zh) 显示面板和电子设备
EP4203053A1 (en) Display substrate and preparation method therefor, and display apparatus
WO2023159353A1 (zh) 显示基板及其制备方法、显示装置
WO2023159561A1 (zh) 显示基板和显示装置
WO2024020750A1 (zh) 显示基板及显示装置
WO2023205997A1 (zh) 显示基板及其制备方法、显示装置
WO2022193315A1 (zh) 触控显示基板及其制备方法、触控显示装置
WO2022227478A1 (zh) 一种显示基板及其制作方法、显示装置
WO2023023979A1 (zh) 显示基板和显示装置
WO2023184163A1 (zh) 显示基板及显示装置
WO2024036629A1 (zh) 显示基板及其驱动方法、显示装置
WO2023159511A1 (zh) 显示基板及其制备方法、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23842125

Country of ref document: EP

Kind code of ref document: A1