WO2024060127A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2024060127A1
WO2024060127A1 PCT/CN2022/120502 CN2022120502W WO2024060127A1 WO 2024060127 A1 WO2024060127 A1 WO 2024060127A1 CN 2022120502 W CN2022120502 W CN 2022120502W WO 2024060127 A1 WO2024060127 A1 WO 2024060127A1
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Prior art keywords
conductive layer
electrode
layer
electrically connected
conductive
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PCT/CN2022/120502
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English (en)
French (fr)
Inventor
杨中流
李正坤
青海刚
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280003243.3A priority Critical patent/CN118077331A/zh
Priority to PCT/CN2022/120502 priority patent/WO2024060127A1/zh
Publication of WO2024060127A1 publication Critical patent/WO2024060127A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate and a display device.
  • OLED organic light emitting diode display devices
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • an embodiment of the present disclosure provides a display substrate, including:
  • a substrate including a display area and a peripheral area surrounding the display area
  • the driving function layer is located on one side of the substrate and includes: a plurality of pixel driving circuits located in the display area and arranged in an array along a first direction and a second direction. The first direction and the second direction intersect;
  • a first conductive layer located on a side of the driving function layer away from the substrate, includes a plurality of first power lines for providing a first operating voltage to the pixel driving circuit;
  • the first planarization layer and the second conductive layer are both located between the driving function layer and the first conductive layer.
  • the first planarization layer is located between the first conductive layer and the second conductive layer.
  • the second conductive layer includes a plurality of first conductive patterns. The first conductive patterns are electrically connected to the corresponding first power lines through first via holes on the first planarization layer and form a parallel connection. .
  • the first power line extends along the second direction, and the first conductive pattern extends along the second direction;
  • An orthographic projection of the first conductive pattern on the substrate at least partially overlaps an orthographic projection of the first power line on the substrate.
  • the first conductive layer further includes a first peripheral power line located in the peripheral area and used to transmit the first operating voltage
  • the second conductive layer further includes a second conductive pattern located in the peripheral area;
  • the second conductive pattern is electrically connected to the first peripheral power line through a second via hole on the first planarization layer and forms a parallel connection.
  • the driving function layer includes a plurality of gate lines extending along the first direction, and the pixel driving circuit is electrically connected to the corresponding gate lines;
  • the driving functional layer includes a third conductive layer, the third conductive layer is located on a side of the second conductive layer close to the substrate, and the third conductive layer includes the gate line;
  • the first conductive layer also includes: a fourth power line located in the peripheral area and used to provide a second operating voltage to the pixel driving circuit; and/or the third conductive layer includes: located in the peripheral area area, and a fifth power line used to provide a second operating voltage to the pixel driving circuit;
  • the second conductive layer also includes: a plurality of third conductive patterns, the third conductive patterns are electrically connected to the corresponding fourth power supply line and/or the fifth power supply line and formed in parallel.
  • the driving function layer includes a plurality of gate lines extending along the first direction, and the pixel driving circuit is electrically connected to the corresponding gate lines;
  • the driving functional layer includes a third conductive layer, the third conductive layer is located on a side of the second conductive layer close to the substrate, and the third conductive layer includes the gate line;
  • the third conductive layer further includes: a plurality of second power lines for transmitting the first operating voltage, the second power lines extending along the first direction;
  • the display substrate also includes:
  • the passivation layer is located between the second conductive layer and the third conductive layer, and the first conductive pattern is electrically connected to the corresponding second power line through a third via hole on the passivation layer.
  • the driving function layer further includes: a fourth conductive layer located on the side of the third conductive layer close to the substrate and a fifth conductive layer located on the side of the fourth conductive layer close to the substrate. layer;
  • the pixel driving circuit includes a driving transistor and a storage capacitor.
  • the first plate of the storage capacitor is electrically connected to the first power line.
  • the second plate of the storage capacitor is electrically connected to the control electrode of the driving transistor. ;
  • the first plate of the storage capacitor is located on the fourth conductive layer, the second plate of the storage capacitor and the control electrode of the driving transistor are located on the fifth conductive layer;
  • the display substrate also includes:
  • An interlayer insulating layer is located between the third conductive layer and the fourth conductive layer.
  • the fourth conductive layer further includes: a plurality of third power lines for transmitting the first operating voltage, the third power lines being connected to the first plate of the storage capacitor, and extending along the first direction;
  • the third power line is electrically connected to the corresponding second power line through a fourth via hole on the interlayer insulation layer.
  • the pixel driving circuit further includes: a first reset transistor, a control electrode of the first reset transistor is electrically connected to the first reset control signal line, and a first electrode of the first reset transistor is electrically connected to the first reset control signal line.
  • a reset voltage transmission line is electrically connected, and the second electrode of the first reset transistor is electrically connected to the control electrode of the driving transistor;
  • the first reset voltage transmission line is located on the fourth conductive layer and extends along the first direction;
  • the first conductive layer further includes: a reset voltage connection line, the reset voltage connection line is located in the first conductive layer and extends along the second direction;
  • the first reset voltage transmission lines corresponding to two adjacent pixel driving circuits in the second direction are electrically connected through the reset voltage connection line.
  • the third conductive layer further includes: a first transfer electrode, and both ends of the first reset voltage transmission line are electrically connected to the corresponding reset voltage connection line through the first transfer electrode. connect;
  • Both ends of the first reset voltage transmission line are electrically connected to the corresponding first transfer electrodes through fifth via holes on the passivation layer;
  • the second conductive layer further includes a fourth conductive pattern.
  • An orthographic projection of the fourth conductive pattern on the substrate covers the portion of the first transfer electrode exposed by the fifth via hole. Orthographic projection on the base.
  • the orthographic projection of the first power line corresponding to the storage capacitor on the substrate covers the orthographic projection of the first reset transistor corresponding to the storage capacitor on the substrate.
  • the first conductive layer further includes a plurality of data lines extending along the second direction;
  • the pixel driving circuit further includes a data writing transistor, a control electrode of the data writing transistor is electrically connected to the corresponding gate line, and a first electrode of the data writing transistor is electrically connected to the corresponding data line, so The second pole of the data writing transistor is electrically connected to the first pole of the driving transistor.
  • the third conductive layer further includes: a second transfer electrode, and the data line is electrically connected to the corresponding first electrode of the data writing transistor through the second transfer electrode;
  • the data line is electrically connected to the corresponding second transfer electrode through a sixth via hole on the passivation layer;
  • the second conductive layer further includes a fifth conductive pattern, and an orthographic projection of the fifth conductive pattern on the substrate covers an orthographic projection of a portion of the second switching electrode exposed by the sixth via hole on the substrate.
  • the display substrate further comprises a light emitting element, the light emitting element is located on a side of the first conductive layer away from the substrate, and the light emitting element comprises: a first electrode, a light emitting layer, and a second electrode sequentially arranged in a direction away from the first conductive layer;
  • the pixel driving circuit also includes: a second light-emitting control transistor, a control electrode of the second light-emitting control transistor is electrically connected to the light-emitting control signal line, and a first electrode of the second light-emitting control transistor is connected to the second electrode of the driving transistor. Electrically connected, the second electrode of the second light emitting control transistor is electrically connected to the first electrode;
  • the third conductive layer further includes: a third transfer electrode, the second electrode of the second light emission control transistor is electrically connected to the corresponding first electrode through the third transfer electrode;
  • the first electrode is electrically connected to the corresponding third transfer electrode through a seventh via hole on the passivation layer;
  • the second conductive layer also includes a sixth conductive pattern.
  • An orthographic projection of the sixth conductive pattern on the substrate covers the portion of the third transfer electrode exposed by the seventh via hole. Orthographic projection on the base.
  • the first conductive layer further includes: a fourth transfer electrode, the first electrode is electrically connected to the corresponding third transfer electrode through the fourth transfer electrode;
  • the fourth transfer electrode is in contact with the corresponding sixth conductive pattern through the via hole on the first planarization layer;
  • the sixth conductive pattern is in contact with the corresponding third transfer electrode through the corresponding seventh via hole.
  • an embodiment of the present disclosure provides a display device, comprising the display substrate described in the first aspect.
  • FIG. 1 is a layout of a pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 3 is a schematic circuit structure diagram of a pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic plan view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 5 is a layout of an active semiconductor layer adopted by an embodiment of the present disclosure.
  • FIG. 6 is a layout of a fifth conductive layer provided by an embodiment of the present disclosure.
  • FIG. 7 is a layout of a fourth conductive layer provided by an embodiment of the present disclosure.
  • FIG. 8 is a layout of a third conductive layer provided by an embodiment of the present disclosure.
  • Figure 9 is a layout of a passivation layer provided by an embodiment of the present disclosure.
  • Figure 10 is a layout of a second conductive layer provided by an embodiment of the present disclosure.
  • Figure 11 is a layout of a first conductive layer provided by an embodiment of the present disclosure.
  • Substrate 1 driving function layer 2, pixel definition layer PDL, light-emitting element EL, first electrode 31, second planarization layer PLN2, first conductive layer CL1, first planarization layer PLN1, second conductive layer CL2, passivation layer PVX, third conductive layer CL3, interlayer insulating layer ILD, fourth conductive layer CL4, second insulating layer GI2, fifth conductive layer CL5, first insulating layer GI1, and active semiconductor layer 4;
  • the transistors involved in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same or similar characteristics. Since the source and drain of the transistor are symmetrical, there is no difference between their source and drain. of. In the embodiment of the present disclosure, in order to distinguish the source electrode and the drain electrode of the transistor, one electrode is called the first electrode and the other electrode is called the second electrode; the gate electrode of the transistor is called the control electrode. In addition, transistors can be divided into N-type and P-type according to their characteristics. When a P-type transistor is used, the first pole is the drain of the P-type transistor, and the second pole is the source of the P-type transistor. The reverse is true for the N-type.
  • the N-type transistor is turned on when a high-level signal is applied to its control electrode and is turned off when a low-level signal is applied to its control electrode.
  • the P-type transistor is turned on when a low-level signal is applied to its control electrode and is turned off when a low-level signal is applied to its control electrode. It is cut off when a high level signal is applied to the pole.
  • the transistor is a P-type transistor as an example for exemplary description.
  • OLED display devices have become the most commonly used display devices. They have many advantages such as self-illumination, fast response speed and wide viewing angle, so they have been widely used. For display devices, brightness uniformity is an important factor affecting the display effect. Currently, long-range uniformity (LRU) is used in this field to evaluate the performance of display devices.
  • LRU long-range uniformity
  • each pixel includes a light-emitting device.
  • the light-emitting device includes an anode, a light-emitting layer and a cathode.
  • the anode is electrically connected to the driver chip and is used to provide the anode voltage Vdd for the light-emitting device.
  • the cathode is used to provide Cathode voltage Vss.
  • IR Drop voltage drop
  • the anode voltage Vdd actually obtained by the light-emitting device is lower, and the cross-voltage Vds of the light-emitting device is lower.
  • the cross voltage refers to the difference between the anode voltage Vdd and the cathode voltage Vss of the OLED.
  • the cross-voltage the lower the brightness of the OLED. This results in the lower the brightness of the pixels farther away from the driver chip, resulting in brightness differences at different positions on the display substrate.
  • the LRU of the display substrate is low and the display effect is not good.
  • the cross-voltage between the driving near-end and the driving far-end is larger, so it is more likely to occur due to the voltage drop in the Vdd line. resulting in poor display.
  • the pixels at the far end of the driving chip need to reach a certain brightness under a bright screen, it is necessary to increase the amplitude of Vdd to ensure the brightness, which will inevitably bring about new problems of increased power consumption.
  • the light-emitting material consumption of the light-emitting layer in the light-emitting device is different, which can easily cause the problem of differences in the life span of the display substrate.
  • embodiments of the present disclosure provide a display substrate that can reduce voltage drop differences in display devices and improve brightness uniformity.
  • FIG. 1 is a layout of a pixel driving circuit provided by an embodiment of the disclosure.
  • FIG. 2 is a schematic structural diagram of a display substrate provided by an embodiment of the disclosure.
  • FIG. 3 is a circuit diagram of a pixel driving circuit provided by an embodiment of the disclosure. Structural diagram
  • FIG. 4 is a schematic planar structural diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG. 5 is a layout of an active semiconductor layer provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 7 is a layout of a fourth conductive layer provided by an embodiment of the present disclosure.
  • Figure 8 is a layout of a third conductive layer provided by an embodiment of the present disclosure.
  • Figure 9 is a layout of the third conductive layer provided by an embodiment of the present disclosure.
  • a layout of a passivation layer is provided.
  • FIG. 10 is a layout of a second conductive layer provided by an embodiment of the present disclosure.
  • FIG. 11 is a layout of a first conductive layer provided by an embodiment of the present disclosure.
  • the display substrate includes: a substrate 1, a driving function layer 2, a first conductive layer CL1, a first planarization layer PLN1, and a second conductive layer CL2. in:
  • the substrate 1 includes a display area AA and a peripheral area NA surrounding the display area AA.
  • the driving function layer 2 is located on one side of the substrate 1 and includes a plurality of pixel driving circuits located in the display area AA and arranged in an array along a first direction and a second direction, where the first direction intersects with the second direction.
  • the first conductive layer CL1 is located on a side of the driving function layer 2 away from the substrate 1, and includes a plurality of first power lines vdd1 for providing a first operating voltage to the pixel driving circuit.
  • the first planarization layer PLN1 and the second conductive layer CL2 are both located between the driving function layer 2 and the first conductive layer CL1.
  • the first planarization layer PLN1 is located between the first conductive layer CL1 and the second conductive layer CL2.
  • the second conductive layer CL2 includes a plurality of first conductive patterns a1.
  • the first conductive patterns a1 are electrically connected and formed with the corresponding first power line vdd1 through a first via hole (not shown in the figure) on the first planarization layer PLN1. in parallel.
  • the first conductive layer CL1 includes a plurality of first power lines vdd1.
  • the first power lines vdd1 are used to provide a first operating voltage to the pixel driving circuit.
  • the above-mentioned first operating voltage is the anode voltage.
  • the second conductive layer CL2 includes a plurality of first conductive patterns a1, and the first conductive patterns a1 are connected in parallel with the first power line vdd1, which is equivalent to the first conductive patterns a1 and the first power line vdd1 jointly serving as a Vdd wiring.
  • the equivalent resistance at the first power line vdd1 can be reduced, thereby improving the voltage drop problem of the vdd wiring, which is beneficial to improving the brightness uniformity of the display substrate.
  • the pixel driving circuit provided in the embodiment of the present disclosure can adopt the 7T1C (7 transistors and 1 capacitor) situation shown in Figure 3.
  • Figure 3 only serves an illustrative purpose, and it will not influence the present invention.
  • the disclosed technical solution has limitations.
  • the pixel driving circuit can also adopt other structures of transistors, such as 7T2C structure, 6T1C structure, 6T2C structure or 9T2C structure.
  • the embodiments of the present disclosure are not limited to this.
  • the first power line vdd1 extends along the second direction, and the first conductive pattern a1 extends along the second direction; the orthogonal projection of the first conductive pattern a1 on the substrate 1 is consistent with the first power supply line vdd1.
  • the orthographic projections of line vdd1 on substrate 1 at least partially overlap.
  • the orthographic projection of the first conductive pattern a1 on the substrate 1 and the orthographic projection of the first power line vdd1 on the substrate 1 may completely overlap, or the orthographic projection of the first conductive pattern a1 on the substrate 1 may be
  • the front projection coverage of a power line vdd1 on the substrate 1 only needs to ensure that the first conductive pattern a1 and the first power line vdd1 are connected in parallel to reduce the overall voltage drop of the Vdd line.
  • the projection relationship between the two There are no limitations in the embodiments of this disclosure.
  • the first conductive layer CL1 also includes a first peripheral power line vdd4 located in the peripheral area NA and used to transmit the first operating voltage;
  • the second conductive layer CL2 also includes a first peripheral power line vdd4 located in the peripheral area
  • the second conductive pattern a2 of NA; the second conductive pattern a2 is electrically connected to the first peripheral power line vdd4 through the second via hole on the first planarization layer PLN1 and forms a parallel connection.
  • the first power line vdd1 and the first peripheral power line vdd4 are arranged on the same layer (both are located on the first conductive layer CL1).
  • the first peripheral power line vdd4 may be disposed on opposite sides of the display area AA in the second direction, and both ends of the first power line vdd1 may respectively extend to the peripheral area NA to connect to the first peripheral power supply line.
  • the line vdd4 is connected.
  • arranging the second conductive pattern a2 in parallel with the first peripheral power line vdd4 in the second conductive layer CL2 can reduce the equivalent resistance at the first peripheral power line vdd4, thereby improving the voltage drop problem of the vdd line. It is beneficial to improve the brightness uniformity of the display substrate.
  • the driving functional layer includes a plurality of gate lines Gate extending along the first direction, and the pixel driving circuit is electrically connected to the corresponding gate lines Gate.
  • the driving functional layer 2 It includes a third conductive layer CL3.
  • the third conductive layer CL3 is located on a side of the second conductive layer CL2 close to the substrate 1.
  • the third conductive layer CL3 includes a gate line Gate.
  • the first conductive layer CL1 also includes: a fourth power supply line vss1 located in the peripheral area NA and used to provide the second operating voltage to the pixel driving circuit; and/or the third conductive layer CL3 includes: located in the peripheral area NA and used for The fifth power line vss2 provides the second operating voltage to the pixel driving circuit.
  • the second conductive layer CL2 also includes: a plurality of third conductive patterns a3. The third conductive patterns a3 are electrically connected to the corresponding fourth power supply line vss1 and/or the fifth power supply line vss2 in parallel.
  • the second operating voltage provided by the fourth power line vss1 and/or the fifth power line vss2 to the pixel driving circuit may be the cathode voltage Vss
  • the second conductive layer CL2 also includes a plurality of third conductive patterns a3.
  • the three conductive pattern a3 can be connected in parallel with the fourth power supply line vss1 through the via hole on the first planarization layer PLN1 to reduce the voltage drop of the Vss line.
  • the third conductive layer CL3 includes the fifth power line vss2, the third conductive pattern a3 and the fifth power line vss2 are connected in parallel, that is, the fourth power line vss1, the third conductive pattern a3 and the fifth power line vss2 All are connected in parallel to further reduce the voltage drop of the Vss line.
  • the display substrate further includes a passivation layer PVX.
  • the passivation layer PVX is located between the second conductive layer CL2 and the third conductive layer CL3. Therefore, the third conductive pattern a3 located on the second conductive layer CL2 and The fifth power line vss2 on the third conductive layer CL3 is connected through the via hole on the passivation layer PVX and formed in parallel.
  • the orthographic projections of the fourth power line vss1 in the first conductive layer CL1, the third conductive pattern a3 in the second conductive layer CL2, and the fifth power line vss2 in the third conductive layer CL3 on the substrate 1 respectively They may completely overlap, or they may at least partially overlap, and this is not limited in the embodiment of the present disclosure.
  • the equivalent resistance at the Vss trace can be effectively reduced.
  • the line width of the fourth power line vss1/fifth power line vss2 can be appropriately reduced, which is beneficial to the narrow frame design of the product.
  • the power lines used to provide/transmit the first operating voltage VDD and the power lines used to provide/transmit the second operating voltage VSS in the embodiment of the present disclosure can be connected to the peripheral area NA.
  • the bonding area NA1 in the bonding area NA1 is provided with multiple connection terminals (usually pads).
  • the third conductive layer CL3 also includes: a plurality of second power lines vdd2 for transmitting the first operating voltage, and the second power lines vdd2 extend along the first direction,
  • the first conductive pattern a1 is electrically connected to the corresponding second power line vdd2 through the third via hole k3 on the passivation layer PVX.
  • the second power line vdd2 has the same function as the first power line vdd1 and the first conductive pattern a1, which are to transmit the first operating voltage to the pixel driving circuit, but the extension direction of the second power line vdd2 is The first direction intersects the extending direction of the first power line vdd1/the first conductive pattern a1.
  • the vdd wiring formed by the second power line vdd2, the first power line vdd1, and the first conductive pattern a1 for transmitting the first operating voltage has a grid structure. Through this design, the entire vdd wiring can be made equal The effective resistance is reduced, and at the same time it can also improve the uniformity of the voltage loaded at various locations on the vdd trace.
  • the driving function layer 2 also includes: an active semiconductor layer 4 , a first insulating layer GI1 , a fifth conductive layer CL5 , and a second insulating layer GI2 that are sequentially arranged in a direction away from the substrate 1 , the fourth conductive layer CL4 and the interlayer insulating layer ILD, wherein the fourth conductive layer CL4 is located on the side of the interlayer insulating layer ILD away from the third conductive layer CL3.
  • the active semiconductor includes the active region pattern (also called the channel region) and the source-drain doping region pattern (including the source region and the drain region) of each transistor in the pixel driving circuit.
  • the active semiconductor layer 4 may include an integrally formed low-temperature polysilicon layer, wherein the source region and the drain region of each transistor may be conductorized by doping, etc. to realize the electrical connection of each structure. That is, the active region pattern and the source-drain doping region pattern of each transistor in each pixel driving circuit are an integral pattern formed by p-silicon, and the active layer patterns of different transistors may be separated by doping structures.
  • the active semiconductor layer 4 can be made of amorphous silicon, polysilicon, oxide semiconductor materials, etc.
  • the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the pixel drive circuit also includes a drive transistor T3 and a storage capacitor C.
  • the first plate C_1 of the storage capacitor C is electrically connected to the first power line vdd1
  • the second pole of the storage capacitor C Board C_2 is electrically connected to the control electrode of drive transistor T3.
  • the first plate C_1 of the storage capacitor C is located on the fourth conductive layer CL4, and the control electrode of the driving transistor T3 and the second plate C_1 of the storage capacitor C are located on the fifth conductive layer CL5.
  • the fourth conductive layer CL4 also includes: a plurality of third power lines vdd3 for transmitting the first operating voltage, the third power line vdd3 being connected to the first electrode plate C_1 of the storage capacitor C and extending along the first direction; the third power line vdd3 being electrically connected to the corresponding second power line vdd2 through a fourth via hole (not shown in the figure) on the interlayer insulating layer ILD, and being connected in parallel with the second power line vdd2, thereby reducing the equivalent resistance at the second power line vdd2.
  • the first power line vdd1 and the first conductive pattern a1 form a double-layer vdd line extending along the second direction
  • the second power line vdd2 and the third power line vdd3 form a double-layer vdd line extending along the first direction
  • the third power line vdd3 is electrically connected to the second power line vdd2, so that the vdd wiring with a grid structure is formed on the display substrate, which is beneficial to reducing the voltage drop on the vdd wiring.
  • the pixel driving circuit also includes: a first reset transistor T1.
  • the control electrode of the first reset transistor T1 is electrically connected to the first reset control signal line Reset1.
  • the first electrode of the first reset transistor T1 is electrically connected to the first reset control signal line Reset1.
  • the first reset voltage transmission line Vinit1 is electrically connected, and the second electrode of the first reset transistor T1 is electrically connected with the control electrode of the driving transistor T3.
  • a reset voltage connection line L1 is provided on the first conductive layer CL1, and the reset voltage connection line L1 is connected to the first reset voltage transmission line Vinit1 configured by two adjacent pixel driving circuits in the second direction.
  • the first reset voltage transmission line Vinit1 is located on the fourth conductive layer CL4 and extends along the first direction
  • the reset voltage connection line L1 is located on the first conductive layer CL1 and extends along the second direction; first The reset voltage transmission line Vinit1 is electrically connected to the reset voltage connection line L1.
  • the conductive pattern formed in each film layer structure of the display substrate is formed through an etching process, that is, after glue coating, exposure, and development, the conductive pattern is etched with an etching solution to form the conductive pattern.
  • the third conductive layer CL3 is located on the side of the second conductive layer CL2 close to the substrate 1, and there is a passivation layer PVX between them. During the substrate manufacturing process, the third conductive layer CL3 will be formed first and then the third conductive layer CL3 will be formed. The second conductive layer CL2.
  • the materials of the third conductive layer CL3 and the second conductive layer CL2 are both metal materials.
  • the etching liquid will penetrate into the third conductive layer through the via holes in the passivation layer PVX. layer CL3 to cause mistaken etching of the conductive patterns (such as the second power line vdd2, the first and second electrodes of each transistor, etc.) in the third conductive layer CL3, resulting in product defects.
  • the third conductive layer CL3 also includes: a first transfer electrode b1, and the first reset voltage transmission line Vinit1 is connected to the corresponding reset voltage connection line through the first transfer electrode b1. L1 electrical connection.
  • the first reset voltage transmission line Vinit1 is electrically connected to the corresponding first transfer electrode b1 through the fifth via hole k5 on the passivation layer PVX.
  • the second conductive layer CL2 also includes a fourth conductive pattern a4.
  • the orthographic projection of the fourth conductive pattern a4 on the substrate 1 covers the orthographic projection of the portion of the first transfer electrode b1 exposed by the fifth via hole k5 on the substrate 1.
  • the first reset voltage transmission line Vinit1 is located on the fourth conductive layer CL4, the reset voltage connection line L1 is located on the first conductive layer CL1, and between the first conductive layer CL1 and the fourth conductive layer CL4 includes: along the direction close to the substrate 1
  • the fourth conductive pattern a4 on the second conductive layer CL2 is connected to the first transfer electrode b1 on the third conductive layer CL3 through the fifth via k5 on the passivation layer PVX.
  • the first transfer electrode b1 on the conductive layer CL3 is connected to the first reset voltage transmission line Vinit1 on the fourth conductive layer CL4 through the via hole on the interlayer insulating layer ILD.
  • the first reset transistor T1 is located in the fifth conductive layer CL5, and its second electrode is also electrically connected to the second plate C_2 of the storage capacitor C, and is connected to the first plate C_1 of the storage capacitor C.
  • the first power line vdd1 then the orthographic projection of the first power line vdd1 corresponding to the storage capacitor C on the substrate covers the orthographic projection of the first reset transistor T1 corresponding to the storage capacitor C on the substrate.
  • the first conductive layer CL1 further includes a plurality of data lines Data extending along the second direction.
  • the pixel driving circuit also includes a data writing transistor T4.
  • the control electrode of the data writing transistor T4 is electrically connected to the corresponding gate line Gate.
  • the first electrode of the data writing transistor T4 is electrically connected to the corresponding data line Data.
  • connection, the second pole of the data writing transistor T4 is electrically connected to the first pole of the driving transistor T3.
  • the third conductive layer CL3 further includes: a second transfer electrode b2, through which the data line Data is electrically connected to the first electrode of the corresponding data writing transistor T4; and the data line Data is electrically connected to the corresponding second transfer electrode b2 through the sixth via k6 on the passivation layer PVX.
  • the second conductive layer CL2 also includes a fifth conductive pattern a5.
  • the orthographic projection of the fifth conductive pattern a5 on the substrate 1 covers the orthographic projection of the portion of the second transfer electrode b2 exposed by the sixth via hole k6 on the substrate 1.
  • the data line Data is located on the first conductive layer CL1
  • the first electrode of the data writing transistor T4 is located on the fifth conductive layer CL5.
  • Between the first conductive layer CL1 and the fifth conductive layer CL5 includes: along the direction close to the substrate 1
  • the data line Data located on the first conductive layer CL1 passes through the via hole on the first planarization layer PLN1 and the second conductive layer CL2 on the second conductive layer CL2.
  • the fifth conductive pattern a5 is connected to the second transfer electrode b2 on the third conductive layer CL3 through the sixth via k6 on the passivation layer PVX.
  • the second transfer electrode b2 of CL3 is connected to the conductive pattern on the fourth conductive layer CL4 through the via hole on the interlayer insulating layer ILD, and the conductive pattern on the fourth conductive layer CL4 is connected to the conductive pattern on the fourth conductive layer CL4 through the via hole on the second insulating layer GI2.
  • the first pole of data writing transistor T4 is connected.
  • the display substrate further includes a light-emitting element EL.
  • the light-emitting element EL is located on a side of the first conductive layer CL1 away from the substrate 1.
  • the light-emitting element EL includes: first electrodes sequentially arranged in a direction away from the first conductive layer CL1. 31.
  • the display substrate also includes a second planarization layer PLN2 and a pixel definition layer PDL located on the side of the first planarization layer PLN1 away from the substrate 1, and the pixel definition layer PDL is located on the second planarization layer PLN2 away from the first planarization layer.
  • a pixel opening is provided on the pixel definition layer PDL.
  • the pixel opening exposes at least a part of the first electrode 31, and the light-emitting layer is disposed in the pixel opening.
  • the first electrode 31 may be an anode
  • the second electrode 32 may be a cathode
  • the above-mentioned light-emitting layer may include a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer and an electron injection layer stacked in sequence. layer.
  • the light-emitting device is a top-emitting light-emitting device.
  • the first electrode 31 can be a reflective electrode made of metal material
  • the second electrode can be a transparent conductive material (for example, indium tin oxide). ) made of transparent electrodes.
  • the third conductive layer CL3 also includes: a third transfer electrode b3, and the second electrode of the second reset transistor T7 is connected to the corresponding first electrode 31 through the third transfer electrode b3. Electrical connection; the first electrode 31 is electrically connected to the corresponding third transfer electrode b3 through the seventh via hole k7 on the passivation layer PVX.
  • the second conductive layer CL2 also includes a sixth conductive pattern a6.
  • the orthographic projection of the sixth conductive pattern a6 on the substrate 1 covers the orthographic projection of the portion of the third transfer electrode b3 exposed by the seventh via hole k7 on the substrate 1.
  • the pixel driving circuit also includes a second light-emitting control transistor T6.
  • the control electrode of the second light-emitting control transistor T6 is electrically connected to the light-emitting control signal line EM.
  • the first electrode of the second light-emitting control transistor T6 is connected to the first electrode of the driving transistor T3.
  • the two poles are electrically connected, and the second pole of the second light emission control transistor T6 is electrically connected to the first electrode 31 of the light emitting element EL.
  • the second electrode of the second reset transistor T7 is electrically connected to the second electrode of the second light-emitting control transistor T6.
  • the second electrode of the second reset transistor T7 can be electrically connected through The third transfer electrode b3 on the three conductive layer CL3 is realized; further, the structure located on the active semiconductor layer 4 is electrically connected to the first electrode 31 through the third transfer electrode b3, thereby realizing the third transfer electrode of the second light emitting control transistor T6.
  • the pixel driving circuit further includes a second reset transistor T7, the control electrode of the second reset transistor T7 is electrically connected to the second reset control signal line Reset2, the first electrode of the second reset transistor T7 is electrically connected to the second reset voltage transmission line Vinit2, and the second electrode of the second reset transistor T7 is electrically connected to the first electrode 31.
  • the source region and the drain region of the transistor in the pixel driving circuit can be made conductive by doping or the like in the active semiconductor layer 4 to realize the electrical connection of each structure. Then the second electrode of the second reset transistor T7 and the second electrode of the second light emitting control transistor T6 can be connected as an integrated structure in the active semiconductor layer 4.
  • the first conductive layer CL1 also includes: a fourth transfer electrode b4, the first electrode 31 is electrically connected to the corresponding third transfer electrode b3 through the fourth transfer electrode b4;
  • the fourth transfer electrode b4 is in contact with the corresponding sixth conductive pattern a6 through the via hole on the first planarization layer PLN1;
  • the sixth conductive pattern a6 is in contact with the corresponding third transfer electrode b3 through the corresponding seventh via hole k7 contact each other, so that the second electrode of the second reset transistor T7 is electrically connected to the first electrode 31 .
  • the material of the conductive pattern on the first conductive layer CL1 and the material of the conductive pattern on the second conductive layer CL2 are both metal materials, and the first planarization layer located between the first conductive layer CL1 and the second conductive layer CL2 Multiple vias are included on PLN1.
  • the second conductive layer CL2 is The conductive pattern on the conductive layer CL2 causes mistaken etching, and it is necessary to set a conductive pattern in the first conductive layer CL1 at a position corresponding to the via hole on the first planarization layer PLN1.
  • the orthographic projection of the fourth transfer electrode b4 on the substrate 1 covers the orthographic projection of the sixth conductive pattern a6 on the substrate 1 to prevent the etching liquid from penetrating through the via hole on the first planarization layer PLN1
  • the second conductive layer CL2 causes false over-engraving of the sixth conductive pattern a6 in the second conductive layer CL2.
  • the display substrate includes a plurality of light-emitting elements EL, and each light-emitting element EL has a corresponding pixel driving circuit.
  • the first conductive layer CL1 is provided
  • the connection line L2 is used to connect the second electrode of the second light-emitting control transistor and the first electrode of the corresponding light-emitting element EL.
  • the pixel driving circuit further includes: a threshold compensation transistor T2 and a first light emission control transistor T5.
  • the control electrode of the first light-emitting control transistor T5 is electrically connected to the light-emitting control signal line EM
  • the first electrode of the first light-emitting control transistor T5 is electrically connected to the operating voltage transmission line
  • the second electrode of the first light-emitting control transistor T5 is electrically connected to the driving transistor.
  • the first electrode of T3 is electrically connected, and the above-mentioned operating voltage transmission line provides the first operating voltage;
  • the threshold compensation transistor T2 can be a thin film transistor with a double-gate structure, and the first control electrode of the threshold compensation transistor T2 can be the gate line Gate and the active semiconductor.
  • the second control electrode of the threshold compensation transistor T2 can be a protruding portion protruding from the gate line Gate and the portion overlapping the active semiconductor layer 4; the control electrode of the driving transistor T3 can be in contact with the storage capacitor C.
  • the second plate C_1 has the same structure.
  • the part of the active semiconductor layer 4 within the dotted rectangular frame indicated by Tna represents the active area pattern of the transistor Tn, 1 ⁇ n ⁇ 7 and n is a positive integer.
  • the part within the dotted rectangular frame indicated by T1a represents the active area pattern of the first reset transistor T1.
  • the active area pattern and source-drain doping area of each transistor in the same pixel driving circuit are provided integrally.
  • an embodiment of the present disclosure also provides a display device, which includes the display substrate in the previous embodiment; for the description of the display substrate, please refer to the content in the previous embodiment, and will not be described again here.
  • the display device in the embodiment of the present disclosure can be any product or component with a display function, such as a flexible wearable device, a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc.
  • a display function such as a flexible wearable device, a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc.
  • Other essential components of the display device should be understood by ordinary technicians in the field, and will not be repeated here, nor should they be used as limitations on the present invention.
  • the display device may also include multiple types of display devices, such as organic electroluminescent display devices (for example, OLED display devices, QLED display devices), mini diode (Mini LED) display devices, which are not limited here.
  • organic electroluminescent display devices for example, OLED display devices, QLED display devices
  • mini diode (Mini LED) display devices which are not limited here.

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Abstract

本公开实施例提供一种显示基板和显示装置，其中显示基板包括：基底，包括显示区和围绕显示区的周边区；驱动功能层，位于基底的一侧，包括：位于显示区且沿第一方向、第二方向呈阵列排布的多个像素驱动电路，第一方向与第二方向相交；第一导电层，位于驱动功能层远离基底的一侧，包括用于向像素驱动电路提供第一工作电压的多条第一电源线；第一平坦化层和第二导电层，均位于驱动功能层与第一导电层之间，第一平坦化层位于第一导电层和第二导电层之间，第二导电层包括多个第一导电图案，第一导电图案通过第一平坦化层上的第一过孔与对应的第一电源线电连接且形成并联。

Description

显示基板和显示装置 技术领域
本公开涉及显示技术领域，具体涉及一种显示基板和显示装置。
背景技术
随着显示行业的快速发展，有机发光二极管显示装置(Organic Light Emitting Display，OLED)作为目前最常用的显示器件，在显示技术领域得到极大关注及发展。
近年来，显示产品不断进行更新迭代，显示装置的尺寸也逐渐增大，伴随而来的是显示装置的长程均一性较差。因此，如果在满足显示装置具有大尺寸、窄边框以及低功耗需求的同时，提高显示装置的长程均一性，成为目前亟待解决的问题。
发明内容
本公开实施例提供一种显示基板和显示装置。
第一方面，本公开实施例提供一种显示基板，包括：
基底，包括显示区和围绕所述显示区的周边区；
驱动功能层，位于所述基底的一侧，包括：位于所述显示区且沿第一方向、第二方向呈阵列排布的多个像素驱动电路，所述第一方向与所述第二方向相交；
第一导电层，位于所述驱动功能层远离所述基底的一侧，包括用于向所述像素驱动电路提供第一工作电压的多条第一电源线；
第一平坦化层和第二导电层，均位于所述驱动功能层与所述第一导电层之间，所述第一平坦化层位于所述第一导电层和所述第二导电层之 间，所述第二导电层包括多个第一导电图案，所述第一导电图案通过所述第一平坦化层上的第一过孔与对应的所述第一电源线电连接且形成并联。
在一些实施例中，所述第一电源线沿所述第二方向延伸，所述第一导电图案沿所述第二方向延伸；
所述第一导电图案在所述基底上的正投影与所述第一电源线在所述基底上的正投影至少部分交叠。
在一些实施例中，所述第一导电层还包括位于所述周边区，且用于传输所述第一工作电压的第一周边电源线；
所述第二导电层还包括位于所述周边区的第二导电图案；
所述第二导电图案通过所述第一平坦化层上的第二过孔与所述第一周边电源线电连接且形成并联。
所述驱动功能层包括多条沿第一方向延伸的栅线，所述像素驱动电路与对应的栅线电连接；
所述驱动功能层包括第三导电层，所述第三导电层位于所述第二导电层靠近所述基底的一侧，所述第三导电层包括所述栅线；
所述第一导电层还包括：位于所述周边区且用于向所述像素驱动电路提供第二工作电压的第四电源线；和/或，所述第三导电层包括：位于所述周边区，且用于向所述像素驱动电路提供第二工作电压的第五电源线；
所述第二导电层还包括：多个第三导电图案，所述第三导电图案与对应的第四电源线和/或第五电源线电连接且形成并联。
在一些实施例中，所述驱动功能层包括多条沿第一方向延伸的栅线，所述像素驱动电路与对应的栅线电连接；
所述驱动功能层包括第三导电层，所述第三导电层位于所述第二导电层靠近所述基底的一侧，所述第三导电层包括所述栅线；
所述第三导电层还包括：用于传输所述第一工作电压的多条第二电源线，所述第二电源线沿所述第一方向延伸；
所述显示基板还包括：
钝化层，位于所述第二导电层和所述第三导电层之间，所述第一导电图案通过所述钝化层上的第三过孔与对应的所述第二电源线电连接。
在一些实施例中，所述驱动功能层还包括：位于所述第三导电层靠近所述基底一侧的第四导电层和位于所述第四导电层靠近所述基底一侧的第五导电层；
所述像素驱动电路包括驱动晶体管和存储电容，所述存储电容的第一极板与所述第一电源线电连接，所述存储电容的第二极板与所述驱动晶体管的控制极电连接；
所述存储电容的第一极板位于所述第四导电层，所述存储电容的第二极板和所述驱动晶体管的控制极位于所述第五导电层；
所述显示基板还包括：
层间绝缘层，位于所述第三导电层和所述第四导电层之间。
在一些实施例中，所述第四导电层还包括：用于传输所述第一工作电压的多条第三电源线，所述第三电源线与所述存储电容的第一极板相连，且沿所述第一方向延伸；
所述第三电源线通过所述层间绝缘层上的第四过孔与对应的所述第二电源线电连接。
在一些实施例中，所述像素驱动电路还包括：第一复位晶体管，所述第一复位晶体管的控制极与第一复位控制信号线电连接，所述第一复位晶体管的第一极与第一复位电压传输线电连接，所述第一复位晶体管的第二极与所述驱动晶体管的控制极电连接；
所述第一复位电压传输线位于所述第四导电层，且沿所述第一方向延伸；
所述第一导电层还包括：复位电压连接线，所述复位电压连接线位于所述第一导电层，且沿所述第二方向延伸；
在所述第二方向上相邻的两个像素驱动电路所对应的所述第一复位电压传输线通过所述复位电压连接线电连接。
在一些实施例中，所述第三导电层还包括：第一转接电极，所述第一复位电压传输线的两端分别通过所述第一转接电极与对应的所述复位电压连接线电连接；
所述第一复位电压传输线的两端分别通过所述钝化层上的第五过孔与对应的所述第一转接电极电连接；
所述第二导电层还包括第四导电图案，所述第四导电图案在所述基底上的正投影，覆盖所述第一转接电极被所述第五过孔所暴露的部分在所述基底上的正投影。
在一些实施例中，所述存储电容对应的所述第一电源线在所述基底上的正投影，覆盖所述存储电容对应的所述第一复位晶体管在所述基底上的正投影。
在一些实施例中，所述第一导电层还包括多条沿所述第二方向延伸的数据线；
所述像素驱动电路还包括数据写入晶体管，所述数据写入晶体管的控制极与对应的所述栅线电连接，所述数据写入晶体管的第一极与对应的数据线电连接，所述数据写入晶体管的第二极与所述驱动晶体管的第一极电连接。
在一些实施例中，所述第三导电层还包括：第二转接电极，所述数据线通过所述第二转接电极与对应的所述数据写入晶体管的第一极电连接；
所述数据线通过所述钝化层上的第六过孔与对应的所述第二转接电极电连接；
所述第二导电层还包括第五导电图案，所述第五导电图案在所述基底上的正投影，覆盖所述第二转接电极被所述第六过孔所暴露的部分在所述基底上的正投影。
在一些实施例中，所述显示基板还包括发光元件，所述发光元件位于所述第一导电层远离所述基底的一侧，所述发光元件包括：沿远离所述第一导电层的方向依次设置有第一电极、发光层和第二电极；
所述像素驱动电路还包括：第二发光控制晶体管，所述第二发光控制晶体管的控制极与发光控制信号线电连接，第二发光控制晶体管的第一极与所述驱动晶体管的第二极电连接，第二发光控制晶体管的第二极与所述第一电极电连接；
所述第三导电层还包括：第三转接电极，所述第二发光控制晶体管的第二极通过所述第三转接电极与对应的所述第一电极电连接；
所述第一电极通过所述钝化层上的第七过孔与对应的所述第三转接电极电连接；
所述第二导电层还包括第六导电图案，所述第六导电图案在所述基底上的正投影，覆盖所述第三转接电极被所述第七过孔所暴露的部分在所述基底上的正投影。
在一些实施例中，所述第一导电层还包括：第四转接电极，所述第一电极通过所述第四转接电极与对应的所述第三转接电极电连接；
所述第四转接电极通过所述第一平坦化层上的过孔与对应的第六导电图案相接触；
所述第六导电图案通过对应的所述第七过孔与对应的所述第三转接电极相接触
第二方面，本公开实施例提供一种显示装置，包括第一方面所述的显示基板。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1为本公开实施例提供的一种像素驱动电路的版图。
图2为本公开实施例提供的一种显示基板的结构示意图。
图3为本公开实施例提供的一种像素驱动电路的电路结构示意图。
图4为本公开实施例提供的一种显示基板的平面结构示意图。
图5为本公开实施例通过的一种有源半导体层的版图。
图6为本公开实施例提供的一种第五导电层的版图。
图7为本公开实施例提供的一种第四导电层的版图。
图8为本公开实施例提供的一种第三导电层的版图。
图9为本公开实施例提供的一种钝化层的版图。
图10为本公开实施例提供的一种第二导电层的版图。
图11为本公开实施例提供的一种第一导电层的版图。
附图标记说明：
显示区AA、周边区NA；
基底1、驱动功能层2、像素界定层PDL、发光元件EL、第一电极31、第二平坦化层PLN2、第一导电层CL1、第一平坦化层PLN1、第二导电层CL2、钝化层PVX、第三导电层CL3、层间绝缘层ILD、第四导电层CL4、第二绝缘层GI2、第五导电层CL5、第一绝缘层GI1、有源半导体层4；
第一导电图案a1、第二导电图案a2、第三导电图案a3、第四导电图案a4、第五导电图案a5、第六导电图案a6；第一转接电极b1、第二转接电极b2、第三转接电极b3、第四转接电极b4；
第一电源线vdd1、第二电源线vdd2、第三电源线vdd3、第四电源 线vss1、第五电源线vss2、第一周边电源线vdd4；
数据线Data、栅线Gate、复位电压连接线L1、第一复位电压传输线Vinit1、第二复位电压传输线Vinit2、第一复位控制信号线Reset1、第二复位控制信号线Reset2、连接线L2；
第三过孔k3、第五过孔k5、第六过孔k6、第七过孔k7；
第一复位晶体管T1、阈值补偿晶体管T2、驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6、第二复位晶体管T7、存储电容C、第一极板C_1、第二极板C_2。
具体实施方式
以下结合附图对本公开的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本公开，并不用于限制本公开。
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，本公开实施例使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、 “右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开实施例中所涉及的晶体管可以为薄膜晶体管、场效应管或其他具有相同、类似特性的器件，由于晶体管的源极和漏极是对称的，所以其源极、漏极是没有区别的。在本公开实施例中，为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极；晶体管的栅极称为控制极。此外按照晶体管的特性区分可以将晶体管分为N型和P型，当采用P型晶体管时，第一极为P型晶体管的漏极，第二极为P型晶体管的源极，N型相反。N型晶体管在其控制极施加有高电平信号时而导通且在其控制极施加有低电平信号时而截止，P型晶体管在其控制极施加有低电平信号时而导通且在其控制极施加有高电平信号时而截止。在本公开实施例中，以晶体管为P型晶体管为例进行示例性描述。
随着显示技术的发展，OLED显示装置已成为最常用的显示器件，其具有自发光、响应速度快宽视角等诸多优点，因此得到了广泛的应用。对于显示装置而言，亮度均匀性是影响其显示效果的重要因素，目前本领域中使用长程均一性(Long Range Uniformity，LRU)对显示装置的性能进行评价。
相关技术中，在OLED显示装置中，每个像素包括一个发光器件，发光器件包括阳极、发光层和阴极，其中阳极与驱动芯片电连接，用于为发光器件提供阳极电压Vdd，阴极用于提供阴极电压Vss。但由于与阳极连接的Vdd走线具有一定的电阻率，导致其存在一定的压降(IR Drop)，且距离驱动芯片端口越远压降越大。因此，距离驱动芯片越远的像素中，发光器件实际获得的阳极电压Vdd越低，发光器件的跨压Vds越低。其中，跨压是指OLED的阳极电压Vdd与阴极电压Vss的差值。而在相同的数据电压即相同灰阶下，跨压越低则OLED的亮度越低，由此导致距离驱动芯片越远的像素的亮度越低，从而在显示基板的不同位 置上存在亮度差异，显示基板的LRU较低，显示效果不好。
对于大尺寸和高分辨率的显示基板来说，像素阵列排布的行数更多，则驱动近端和驱动远端的跨压更大，因此也更容易出现由于Vdd走线存在压降而导致的显示不良现象。
另外，当在高亮画面下驱动芯片远端的像素需要达到一定的亮度时，势必需要通过增大Vdd的幅值来保证亮度，这必然带来功耗增加的新问题。同时，发光器件中发光层的发光材料消耗不同，容易引发显示基板寿命区块差异性问题。
为了解决上述技术问题中的至少一个，本公开实施例提供一种显示基板，能够降低显示装置中的压降差异，提升亮度均一性。
图1为本公开实施例提供的一种像素驱动电路的版图，图2为本公开实施例提供的一种显示基板的结构示意图，图3为本公开实施例提供的一种像素驱动电路的电路结构示意图，图4为本公开实施例提供的一种显示基板的平面结构示意图，图5为本公开实施例通过的一种有源半导体层的版图，图6为本公开实施例提供的一种第五导电层的版图，图7为本公开实施例提供的一种第四导电层的版图，图8为本公开实施例提供的一种第三导电层的版图，图9为本公开实施例提供的一种钝化层的版图，图10为本公开实施例提供的一种第二导电层的版图，图11为本公开实施例提供的一种第一导电层的版图。
如图1-图4、图10、图11所示，显示基板包括：基底1、驱动功能层2、第一导电层CL1、第一平坦化层PLN1和第二导电层CL2。其中：
基底1，包括显示区AA和围绕显示区AA的周边区NA。
驱动功能层2，位于基底1的一侧，包括：位于显示区AA且沿第一方向、第二方向呈阵列排布的多个像素驱动电路，第一方向与第二方向相交。
第一导电层CL1，位于驱动功能层2远离基底1的一侧，包括用于 向像素驱动电路提供第一工作电压的多条第一电源线vdd1。
第一平坦化层PLN1和第二导电层CL2，均位于驱动功能层2与第一导电层CL1之间，第一平坦化层PLN1位于第一导电层CL1和第二导电层CL2之间，第二导电层CL2包括多个第一导电图案a1，第一导电图案a1通过第一平坦化层PLN1上的第一过孔(图中未示出)与对应的第一电源线vdd1电连接且形成并联。
本公开实施例提供的显示基板中，第一导电层CL1中包括多条第一电源线vdd1，第一电源线vdd1用于向像素驱动电路提供第一工作电压，上述第一工作电压为阳极电压Vdd；第二导电层CL2中包括多个第一导电图案a1，第一导电图案a1与第一电源线vdd1并联，相当于第一导电图案a1和第一电源线vdd1共同作为Vdd走线。进一步地，通过并联的方式，可降低第一电源线vdd1处的等效电阻，从而能够改善vdd走线的压降问题，有利于提高显示基板的亮度均一性。
需要说明的是，在本公开实施例中所提供的像素驱动电路可采用图3中所示7T1C(7个晶体管和1个电容)的情况，图3仅起到示例性作用，其不会对本公开的技术方案产生限制，像素驱动电路还可以采用其他数量的晶体管的结构，如7T2C结构、6T1C结构、6T2C结构或者9T2C结构，本公开实施例对此不作限定。
在一些实施例中，如图11所示，第一电源线vdd1沿第二方向延伸，第一导电图案a1沿第二方向延伸；第一导电图案a1在基底1上的正投影与第一电源线vdd1在基底1上的正投影至少部分交叠。
可选地，第一导电图案a1在基底1上的正投影与第一电源线vdd1在基底1上的正投影可以完全重合，或者，第一导电图案a1在基底1上的正投影可以被第一电源线vdd1在基底1上的正投影覆盖，只要能保证第一导电图案a1和第一电源线vdd1形成并联以能够降低Vdd走线的整体压降即可，至于二者的投影关系，在本公开实施例中不作限定。
在一些实施例中，如图4所示，第一导电层CL1还包括位于周边区NA，且用于传输第一工作电压的第一周边电源线vdd4；第二导电层CL2还包括位于周边区NA的第二导电图案a2；第二导电图案a2通过第一平坦化层PLN1上的第二过孔与第一周边电源线vdd4电连接且形成并联。在本公开实施例中，第一电源线vdd1和第一周边电源线vdd4同层设置(均位于第一导电层CL1)。
在一些实施例中，第一周边电源线vdd4的可以设置在显示区AA在第二方向上的相对两侧，第一电源线vdd1的两端可以分别延伸至周边区NA以于第一周边电源线vdd4相连。通过设置上述第一周边电源线vdd4，可使得各条第一电源线vdd1的端部电压保持一致，有利于提升各条第一电源线vdd1上所加载电压的均一性。
同时，在第二导电层CL2中设置与第一周边电源线vdd4并联的第二导电图案a2，可降低第一周边电源线vdd4处的等效电阻，从而能够改善vdd走线的压降问题，有利于提高显示基板的亮度均一性。
在一些实施例中，如图2、图3、图8所示，驱动功能层包括多条沿第一方向延伸的栅线Gate，像素驱动电路与对应的栅线Gate电连接，驱动功能层2包括第三导电层CL3，第三导电层CL3位于第二导电层CL2靠近基底1的一侧，第三导电层CL3包括栅线Gate。
第一导电层CL1还包括：位于周边区NA，且用于向像素驱动电路提供第二工作电压的第四电源线vss1；和/或，第三导电层CL3包括：位于周边区NA且用于向像素驱动电路提供第二工作电压的第五电源线vss2。第二导电层CL2还包括：多个第三导电图案a3，第三导电图案a3与对应的第四电源线vss1和/或第五电源线vss2电连接且形成并联。
另外，上述第四电源线vss1和/或第五电源线vss2向像素驱动电路提供的第二工作电压可以是阴极电压Vss，则第二导电层CL2中还包括多个第三导电图案a3，第三导电图案a3可以通过第一平坦化层PLN1 上的过孔与第四电源线vss1形成并联，以降低Vss走线的压降。在第三导电层CL3中包括有第五电源线vss2的情况下，第三导电图案a3与第五电源线vss2形成并联，即第四电源线vss1、第三导电图案a3和第五电源线vss2均形成并联，进一步降低Vss走线的压降。
如图2所示，显示基板还包括钝化层PVX，钝化层PVX位于第二导电层CL2和第三导电层CL3之间，因此位于第二导电层CL2上的第三导电图案a3和位于第三导电层CL3上的第五电源线vss2，通过钝化层PVX上的过孔连接并形成并联。
可选地，第一导电层CL1中的第四电源线vss1、第二导电层CL2中的第三导电图案a3和第三导电层CL3中的第五电源线vss2分别在基底1上的正投影可以完全重合，或者两两之间至少部分交叠，本公开实施例对此不作限定。在本公开实施例中，通过在第二导电层中设置第三导电图案a3，可有效降低Vss走线处的等效电阻。在vss走线处等效电阻不变的情况下，则第四电源线vss1/第五电源线vss2的线宽可以适当减小，因此有利于产品的窄边框设计。
另外，需要说明的是，如图4所示，本公开实施例中用于提供/传输第一工作电压VDD和用于提供/传输第二工作电压VSS的电源线，可连接至位于周边区NA中的绑定区NA1，绑定区NA1上设置有多个连接端子(一般为焊盘)。
在一些实施例中，如图8、图9所示，第三导电层CL3还包括：用于传输第一工作电压的多条第二电源线vdd2，第二电源线vdd2沿第一方向延伸，第一导电图案a1通过钝化层PVX上的第三过孔k3与对应的第二电源线vdd2电连接。
在本公开实施例中，第二电源线vdd2与第一电源线vdd1、第一导电图案a1的作用相同，均为向像素驱动电路传输第一工作电压，但第二电源线vdd2的延伸方向为第一方向，与第一电源线vdd1/第一导电图案 a1的延伸方向相交。此时，第二电源线vdd2、第一电源线vdd1、第一导电图案a1所形成的用于传输第一工作电压的vdd走线为网格结构，通过该设计可使得vdd走线的整体等效电阻降低，同时还能提升vdd走线上各位置所加载电压的均一性。
在一些实施例中，如图2所示，驱动功能层2还包括：沿远离基底1方向依次设置的有源半导体层4、第一绝缘层GI1、第五导电层CL5、第二绝缘层GI2、第四导电层CL4和层间绝缘层ILD，其中，第四导电层CL4位于层间绝缘层ILD远离上述第三导电层CL3的一侧。
如图5所示，需要说明的是，有源半导体中包括像素驱动电路中各晶体管的有源区图形(也称为沟道区)和源漏掺杂区图形(包括源极区和漏极区)。有源半导体层4可以包括一体形成的低温多晶硅层，其中各晶体管的源极区域和漏极区域可以通过掺杂等进行导体化实现各结构的电连接。也就是每个像素驱动电路内各晶体管的有源区图形和源漏掺杂区图形为由p-硅形成的整体图案，且不同晶体管的有源层图形之间可由掺杂结构隔开。
例如，有源半导体层4可采用非晶硅、多晶硅、氧化物半导体材料等制作。上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
如图3、图6和图7所示，像素驱动电路还包括驱动晶体管T3和存储电容C，存储电容C的第一极板C_1与第一电源线vdd1电连接，存储电容C的第二极板C_2与驱动晶体管T3的控制极电连接。
存储电容C的第一极板C_1位于第四导电层CL4，驱动晶体管T3的控制极和存储电容C的第二极板C_1位于第五导电层CL5。
第四导电层CL4还包括：用于传输第一工作电压的多条第三电源线vdd3，第三电源线vdd3与存储电容C的第一极板C_1相连，且沿第一方向延伸；第三电源线vdd3通过层间绝缘层ILD上的第四过孔(图中 未示出)与对应的第二电源线vdd2电连接，并与第二电源线vdd2形成并联，从而能够降低第二电源线vdd2处的等效电阻。
基于此，第一电源线vdd1和第一导电图案a1形成沿第二方向延伸的双层vdd走线，第二电源线vdd2和第三电源线vdd3形成沿第一方向延伸的双层vdd走线，且第三电源线vdd3与第二电源线vdd2电连接，使显示基板上形成网格结构的vdd走线，有利于减小vdd走线上的压降。
如图3、图6所示，像素驱动电路还包括：第一复位晶体管T1，第一复位晶体管T1的控制极与第一复位控制信号线Reset1电连接，第一复位晶体管T1的第一极与第一复位电压传输线Vinit1电连接，第一复位晶体管T1的第二极与驱动晶体管T3的控制极电连接。
在一些实施中，在第一导电层CL1上设置复位电压连接线L1，复位电压连接线L1连接第二方向上相邻两个像素驱动电路所配置的第一复位电压传输线Vinit1。通过设置上述复位电压连接线L1，可有效提升相邻第一复位电压传输线Vinit1上所加载电压的均一性。
如图7、图11所示，第一复位电压传输线Vinit1位于第四导电层CL4，且沿第一方向延伸，复位电压连接线L1位于第一导电层CL1，且沿第二方向延伸；第一复位电压传输线Vinit1与复位电压连接线L1电连接。
应当理解的是，在显示基板中每一膜层结构中所形成的导电图案，是通过刻蚀工艺形成的，即在涂胶、曝光、显影后通过刻蚀液进行刻蚀，以形成导电图案。参见图2，第三导电层CL3位于第二导电层CL2靠近基底1的一侧，且二者之间有钝化层PVX，在基板制作过程中，会先形成第三导电层CL3再形成第二导电层CL2。
一般地，第三导电层CL3和第二导电层CL2的材料均为金属材料，在通过刻蚀工艺对第二导电层CL3进行图案化过程中所使用的刻蚀液，在接触到第三导电层CL3中的材料薄膜时会对第三导电层CL3中的材料 薄膜产生刻蚀作用。在实际工艺过程中，由于钝化层PVX中存在多个过孔，则在形成第二导电层CL2中的导电图案时，刻蚀液会通过钝化层PVX上的过孔渗到第三导电层CL3，以对第三导电层CL3中的导电图案(例如第二电源线vdd2、各晶体管的第一极和第二极等)造成误刻蚀，从而会出现产品不良。
为了克服刻蚀液通过钝化层PVX上的过孔对第三导电层CL3中的导电图案造成误刻蚀的问题，需要在第二导电层CL2中形成导电图案，以遮挡钝化层PVX上形成有过孔、且该过孔暴露出第三导电层CL3上导电图案的位置。
在一些实施例中，如图9、图10所示，第三导电层CL3还包括：第一转接电极b1，第一复位电压传输线Vinit1通过第一转接电极b1与对应的复位电压连接线L1电连接。第一复位电压传输线Vinit1通过钝化层PVX上的第五过孔k5与对应的第一转接电极b1电连接。
第二导电层CL2还包括第四导电图案a4，第四导电图案a4在基底1上的正投影，覆盖第一转接电极b1被第五过孔k5所暴露的部分在基底1上的正投影，以避免刻蚀液通过钝化层PVX上的第五过孔k5渗到第三导电层CL3，对第三导电层CL3中的第一转接电极b1造成误刻蚀。
具体地，第一复位电压传输线Vinit1位于第四导电层CL4，复位电压连接线L1位于第一导电层CL1，在第一导电层CL1和第四导电层CL4之间包括：沿靠近基底1方向的第一平坦化层PLN1、第二导电层CL2、钝化层PVX、第三导电层CL3和层间绝缘层ILD。因此，为了使第一复位电压传输线Vinit1和对应的复位电压连接线L1连接，位于第一导电层CL1的复位电压连接线L1通过第一平坦化层PLN1上的过孔与第二导电层CL2上的第四导电图案a4连接，第二导电层CL2上的第四导电图案a4通过钝化层PVX上的第五过孔k5与第三导电层CL3上的第一转接电极b1连接，第三导电层CL3上的第一转接电极b1通过层间绝缘 层ILD上的过孔与第四导电层CL4上的第一复位电压传输线Vinit1连接。
如图3、图6所示，第一复位晶体管T1位于第五导电层CL5，其第二极还与存储电容C的第二极板C_2电连接，并且存储电容C的第一极板C_1连接第一电源线vdd1，则与存储电容C对应的第一电源线vdd1在基底上的正投影，覆盖与存储电容C对应的第一复位晶体管T1在基底上的正投影。
在一些实施例中，如图6、图11所示，第一导电层CL1还包括多条沿第二方向延伸的数据线Data。如图3所示，像素驱动电路还包括数据写入晶体管T4，数据写入晶体管T4的控制极与对应的栅线Gate电连接，数据写入晶体管T4的第一极与对应的数据线Data电连接，数据写入晶体管T4的第二极与驱动晶体管T3的第一极电连接。
在一些实施例中，第三导电层CL3还包括：第二转接电极b2，数据线Data通过第二转接电极b2与对应的数据写入晶体管T4的第一极电连接；数据线Data通过钝化层PVX上的第六过孔k6与对应的第二转接电极b2电连接。
第二导电层CL2还包括第五导电图案a5，第五导电图案a5在基底1上的正投影，覆盖第二转接电极b2被第六过孔k6所暴露的部分在基底1上的正投影，以避免刻蚀液通过钝化层PVX上的第六过孔k6渗到第三导电层CL3，对第三导电层CL3中的第二转接电极b2造成误刻蚀。
具体地，数据线Data位于第一导电层CL1，数据写入晶体管T4的第一极位于第五导电层CL5，在第一导电层CL1和第五导电层CL5之间包括：沿靠近基底1方向的第一平坦化层PLN1、第二导电层CL2、钝化层PVX、第三导电层CL3、层间绝缘层ILD、第四导电层CL4和第二绝缘层GI2。因此，为了实现数据线Data与数据写入晶体管T4的第一极电连接，位于第一导电层CL1的数据线Data通过第一平坦化层PLN1上的过孔与第二导电层CL2上的第五导电图案a5连接，第二导电层CL2 上的第五导电图案a5通过钝化层PVX上的第六过孔k6与第三导电层CL3上的第二转接电极b2连接，第三导电层CL3的第二转接电极b2通过层间绝缘层ILD上的过孔与第四导电层CL4上的导电图案连接，第四导电层CL4上的导电图案通过第二绝缘层GI2上的过孔与数据写入晶体管T4的第一极连接。
如图2所示，显示基板还包括发光元件EL，发光元件EL位于第一导电层CL1远离基底1的一侧，发光元件EL包括：沿远离第一导电层CL1的方向依次设置有第一电极31、发光层33和第二电极32。具体地，显示基板上还包括位于第一平坦化层PLN1远离基底1一侧的第二平坦化层PLN2和像素界定层PDL，且像素界定层PDL位于第二平坦化层PLN2远离第一平坦化层PLN1的一侧，像素界定层PDL上设置有像素开口，像素开口暴露出第一电极31的至少一部分，发光层设置在像素开口中。在一个示例中，第一电极31可以为阳极，第二电极32可以为阴极，上述发光层可以包括依次叠置的：空穴注入层、空穴传输层、发光层、电子传输层和电子注入层。
需要说明的是，本公开实施例中发光器件为顶发光型发光器件，可选地，第一电极31可以为金属材料制作的反射电极，第二电极可以为透明导电材料(例如，氧化铟锡)制作的透明电极。
在一些实施例中，如图10所示，第三导电层CL3还包括：第三转接电极b3，第二复位晶体管T7的第二极通过第三转接电极b3与对应的第一电极31电连接；第一电极31通过钝化层PVX上的第七过孔k7与对应的第三转接电极b3电连接。
第二导电层CL2还包括第六导电图案a6，第六导电图案a6在基底1上的正投影，覆盖第三转接电极b3被第七过孔k7所暴露的部分在基底1上的正投影，以避免刻蚀液通过钝化层PVX上的第七过孔k7渗到第三导电层CL3，对第三导电层CL3中的第三转接电极b3造成误刻蚀， 从而保证显示基板的显示效果。
参见图3，像素驱动电路还包括第二发光控制晶体管T6，第二发光控制晶体管T6的控制极与发光控制信号线EM电连接，第二发光控制晶体管T6的第一极与驱动晶体管T3的第二极电连接，第二发光控制晶体管T6的第二极与发光元件EL的第一电极31电连接。同时，第二复位晶体管T7的第二极与第二发光控制晶体管T6的第二极电连接，则为了使第二发光控制晶体管T6的第二极与第一电极31电连接，可以通过位于第三导电层CL3上的第三转接电极b3实现；进一步地，位于有源半导体层4的结构通过第三转接电极b3与第一电极31电连接，从而实现第二发光控制晶体管T6的第二极与第一电极31的连接。
如图1、图3所示，像素驱动电路还包括第二复位晶体管T7，第二复位晶体管T7的控制极与第二复位控制信号线Reset2电连接，第二复位晶体管T7的第一极与第二复位电压传输线Vinit2电连接，第二复位晶体管T7的第二极与第一电极31电连接。可选地，像素驱动电路中晶体管的源极区域和漏极区域，可以在有源半导体层4通过掺杂等进行导体化实现各结构的电连接。则第二复位晶体管T7的第二极与第二发光控制晶体管T6的第二极可以在有源半导体层4中连为一体结构。
在一些实施例中，如图2所示，第一导电层CL1还包括：第四转接电极b4，第一电极31通过第四转接电极b4与对应的第三转接电极b3电连接；第四转接电极b4通过第一平坦化层PLN1上的过孔与对应的第六导电图案a6相接触；第六导电图案a6通过对应的第七过孔k7与对应的第三转接电极b3相接触，从而使第二复位晶体管T7的第二极与第一电极31电连接。
一般地，第一导电层CL1上导电图案的材料与第二导电层CL2上导电图案的材料均为金属材料，且位于第一导电层CL1和第二导电层CL2之间的第一平坦化层PLN1上包括多个过孔。在制备第一导电层CL1时， 为了防止用于刻蚀第一导电层CL1中导电图案的刻蚀液，通过第一平坦化层PLN1上的过孔渗到第二导电层CL2，对第二导电层CL2上的导电图案造成误刻蚀，需要在第一导电层CL1中对应于第一平坦化层PLN1上过孔的位置设置导电图案。
在一个示例中，第四转接电极b4在基底1上的正投影覆盖第六导电图案a6在基底1上的正投影，以避免刻蚀液通过第一平坦化层PLN1上的过孔渗到第二导电层CL2，对第二导电层CL2中的第六导电图案a6造成误过刻。
另外，显示基板上包括多个发光元件EL，每一发光元件EL均有与其对应的像素驱动电路。当发光元件EL的第一电极所在区域在基底上的投影位置，与对应像素驱动电路中第二发光控制晶体管的第二极在基底上的投影位置距离较远时，第一导电层CL1中设置连接线L2，用于连接第二发光控制晶体管的第二极和对应发光元件EL的第一电极。
在一些实施例中，如图3所示，像素驱动电路中还包括：阈值补偿晶体管T2和第一发光控制晶体管T5。其中，第一发光控制晶体管T5的控制极与发光控制信号线EM电连接，第一发光控制晶体管T5的第一极与工作电压传输线电连接，第一发光控制晶体管T5的第二极与驱动晶体管T3的第一极电连接，上述工作电压传输线提供第一工作电压；阈值补偿晶体管T2可为双栅结构的薄膜晶体管，阈值补偿晶体管T2的第一个控制极可为栅线Gate与有源半导体层4交叠的部分，阈值补偿晶体管T2的第二个控制极可为从栅线Gate突出的突出部与有源半导体层4交叠的部分；驱动晶体管T3的控制极可以与存储电容C的第二极板C_1为同一结构。
如图5所示，有源半导体层4在Tna所指虚线矩形框内的部分表示晶体管Tn的有源区图形，1≤n≤7且n为正整数，示例性地，有源半导体层4在T1a所指虚线矩形框内的部分表示第一复位晶体管T1的有源 区图形，同一像素驱动电路中的各晶体管的有源区图形和源漏掺杂区一体设置。
基于同一发明构思，本公开实施例还提供了一种显示装置，该显示装置包括前面实施例中的显示基板；对于该显示基板的描述可参见前面实施例中的内容，此处不再赘述。
需要说明的是，本公开实施例中显示装置可以为柔性可穿戴设备、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。
进一步地，显示装置还可以包括多种类型的显示装置，例如有机电致发光显示装置(例如，OLED显示装置、QLED显示装置)、迷你二极管(Mini LED)显示装置，在此不做限定。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (15)

  1. 一种显示基板，其中，包括：
    基底，包括显示区和围绕所述显示区的周边区；
    驱动功能层，位于所述基底的一侧，包括：位于所述显示区且沿第一方向、第二方向呈阵列排布的多个像素驱动电路，所述第一方向与所述第二方向相交；
    第一导电层，位于所述驱动功能层远离所述基底的一侧，包括用于向所述像素驱动电路提供第一工作电压的多条第一电源线；
    第一平坦化层和第二导电层，均位于所述驱动功能层与所述第一导电层之间，所述第一平坦化层位于所述第一导电层和所述第二导电层之间，所述第二导电层包括多个第一导电图案，所述第一导电图案通过所述第一平坦化层上的第一过孔与对应的所述第一电源线电连接且形成并联。
  2. 根据权利要求1所述的显示基板，其中，所述第一电源线沿所述第二方向延伸，所述第一导电图案沿所述第二方向延伸；
    所述第一导电图案在所述基底上的正投影与所述第一电源线在所述基底上的正投影至少部分交叠。
  3. 根据权利要求1或2所述的显示基板，其中，所述第一导电层还包括位于所述周边区，且用于传输所述第一工作电压的第一周边电源线；
    所述第二导电层还包括位于所述周边区的第二导电图案；
    所述第二导电图案通过所述第一平坦化层上的第二过孔与所述第一周边电源线电连接且形成并联。
  4. 根据权利要求1至3中任一所述的显示基板，其中，所述驱动功 能层包括多条沿第一方向延伸的栅线，所述像素驱动电路与对应的栅线电连接；
    所述驱动功能层包括第三导电层，所述第三导电层位于所述第二导电层靠近所述基底的一侧，所述第三导电层包括所述栅线；
    所述第一导电层还包括：位于所述周边区且用于向所述像素驱动电路提供第二工作电压的第四电源线；和/或，所述第三导电层包括：位于所述周边区，且用于向所述像素驱动电路提供第二工作电压的第五电源线；
    所述第二导电层还包括：多个第三导电图案，所述第三导电图案与对应的第四电源线和/或第五电源线电连接且形成并联。
  5. 根据权利要求1至4中任一所述的显示基板，其中，所述驱动功能层包括多条沿第一方向延伸的栅线，所述像素驱动电路与对应的栅线电连接；
    所述驱动功能层包括第三导电层，所述第三导电层位于所述第二导电层靠近所述基底的一侧，所述第三导电层包括所述栅线；
    所述第三导电层还包括：用于传输所述第一工作电压的多条第二电源线，所述第二电源线沿所述第一方向延伸；
    所述显示基板还包括：
    钝化层，位于所述第二导电层和所述第三导电层之间，所述第一导电图案通过所述钝化层上的第三过孔与对应的所述第二电源线电连接。
  6. 根据权利要求5所述的显示基板，其中，所述驱动功能层还包括：位于所述第三导电层靠近所述基底一侧的第四导电层和位于所述第四导电层靠近所述基底一侧的第五导电层；
    所述像素驱动电路包括驱动晶体管和存储电容，所述存储电容的第 一极板与所述第一电源线电连接，所述存储电容的第二极板与所述驱动晶体管的控制极电连接；
    所述存储电容的第一极板位于所述第四导电层，所述存储电容的第二极板和所述驱动晶体管的控制极位于所述第五导电层；
    所述显示基板还包括：
    层间绝缘层，位于所述第三导电层和所述第四导电层之间。
  7. 根据权利要求6所述的显示基板，其中，所述第四导电层还包括：用于传输所述第一工作电压的多条第三电源线，所述第三电源线与所述存储电容的第一极板相连，且沿所述第一方向延伸；
    所述第三电源线通过所述层间绝缘层上的第四过孔与对应的所述第二电源线电连接。
  8. 根据权利要求6或7所述的显示基板，其中，所述像素驱动电路还包括：第一复位晶体管，所述第一复位晶体管的控制极与第一复位控制信号线电连接，所述第一复位晶体管的第一极与第一复位电压传输线电连接，所述第一复位晶体管的第二极与所述存储电容的第二极板电连接；
    所述第一复位电压传输线位于所述第四导电层，且沿所述第一方向延伸；
    所述第一导电层还包括：复位电压连接线，所述复位电压连接线位于所述第一导电层，且沿所述第二方向延伸；
    在所述第二方向上相邻的两个像素驱动电路所对应的所述第一复位电压传输线通过所述复位电压连接线电连接。
  9. 根据权利要求8所述的显示基板，其中，所述第三导电层还包括： 第一转接电极，所述第一复位电压传输线的两端分别通过所述第一转接电极与对应的所述复位电压连接线电连接；
    所述第一复位电压传输线的两端分别通过所述钝化层上的第五过孔与对应的所述第一转接电极电连接；
    所述第二导电层还包括第四导电图案，所述第四导电图案在所述基底上的正投影，覆盖所述第一转接电极被所述第五过孔所暴露的部分在所述基底上的正投影。
  10. 根据权利要求8所述的显示基板，其中，所述存储电容对应的所述第一电源线在所述基底上的正投影，覆盖所述存储电容对应的所述第一复位晶体管在所述基底上的正投影。
  11. 根据权利要求6至10中任一所述的显示基板，其中，所述第一导电层还包括多条沿所述第二方向延伸的数据线；
    所述像素驱动电路还包括数据写入晶体管，所述数据写入晶体管的控制极与对应的所述栅线电连接，所述数据写入晶体管的第一极与对应的数据线电连接，所述数据写入晶体管的第二极与所述驱动晶体管的第一极电连接。
  12. 根据权利要求11所述的显示基板，其中，所述第三导电层还包括：第二转接电极，所述数据线通过所述第二转接电极与对应的所述数据写入晶体管的第一极电连接；
    所述数据线通过所述钝化层上的第六过孔与对应的所述第二转接电极电连接；
    所述第二导电层还包括第五导电图案，所述第五导电图案在所述基底上的正投影，覆盖所述第二转接电极被所述第六过孔所暴露的部分在 所述基底上的正投影。
  13. 根据权利要求6至12任意一项所述的显示基板，其中，所述显示基板还包括发光元件，所述发光元件位于所述第一导电层远离所述基底的一侧，所述发光元件包括：沿远离所述第一导电层的方向依次设置有第一电极、发光层和第二电极；
    所述像素驱动电路还包括：第二发光控制晶体管，所述第二发光控制晶体管的控制极与发光控制信号线电连接，第二发光控制晶体管的第一极与所述驱动晶体管的第二极电连接，第二发光控制晶体管的第二极与所述第一电极电连接；
    所述第三导电层还包括：第三转接电极，所述第二发光控制晶体管的第二极通过所述第三转接电极与对应的所述第一电极电连接；
    所述第一电极通过所述钝化层上的第七过孔与对应的所述第三转接电极电连接；
    所述第二导电层还包括第六导电图案，所述第六导电图案在所述基底上的正投影，覆盖所述第三转接电极被所述第七过孔所暴露的部分在所述基底上的正投影。
  14. 根据权利要求13所述的显示基板，其中，所述第一导电层还包括：第四转接电极，所述第一电极通过所述第四转接电极与对应的所述第三转接电极电连接；
    所述第四转接电极通过所述第一平坦化层上的过孔与对应的第六导电图案相接触；
    所述第六导电图案通过对应的所述第七过孔与对应的所述第三转接电极相接触。
  15. 一种显示装置，其中，包括权利要求1-14中任意一项所述的显示基板。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10741626B1 (en) * 2019-02-28 2020-08-11 Shanghai Tianma Micro-electronics Co., Ltd. Display panels and display devices
CN113707704A (zh) * 2021-09-02 2021-11-26 京东方科技集团股份有限公司 显示基板和显示装置
WO2021249152A1 (zh) * 2020-06-10 2021-12-16 京东方科技集团股份有限公司 显示基板及显示装置
CN114361228A (zh) * 2022-01-04 2022-04-15 京东方科技集团股份有限公司 显示基板和显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10741626B1 (en) * 2019-02-28 2020-08-11 Shanghai Tianma Micro-electronics Co., Ltd. Display panels and display devices
WO2021249152A1 (zh) * 2020-06-10 2021-12-16 京东方科技集团股份有限公司 显示基板及显示装置
CN113707704A (zh) * 2021-09-02 2021-11-26 京东方科技集团股份有限公司 显示基板和显示装置
CN114361228A (zh) * 2022-01-04 2022-04-15 京东方科技集团股份有限公司 显示基板和显示装置

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