WO2024113102A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2024113102A1
WO2024113102A1 PCT/CN2022/134711 CN2022134711W WO2024113102A1 WO 2024113102 A1 WO2024113102 A1 WO 2024113102A1 CN 2022134711 W CN2022134711 W CN 2022134711W WO 2024113102 A1 WO2024113102 A1 WO 2024113102A1
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WO
WIPO (PCT)
Prior art keywords
base substrate
electrically connected
layer
display substrate
drain
Prior art date
Application number
PCT/CN2022/134711
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English (en)
French (fr)
Inventor
韩影
徐攀
张星
吕广爽
赵冬辉
罗程远
许程
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280004658.2A priority Critical patent/CN118414704A/zh
Priority to PCT/CN2022/134711 priority patent/WO2024113102A1/zh
Priority to PCT/CN2023/095874 priority patent/WO2024113713A1/zh
Priority to PCT/CN2023/095842 priority patent/WO2024113710A1/zh
Priority to CN202380009183.0A priority patent/CN118435261A/zh
Priority to CN202380009188.3A priority patent/CN118476325A/zh
Priority to CN202380009189.8A priority patent/CN118414904A/zh
Priority to PCT/CN2023/095841 priority patent/WO2024113709A1/zh
Priority to PCT/CN2023/095870 priority patent/WO2024113712A1/zh
Priority to CN202380009187.9A priority patent/CN118414655A/zh
Publication of WO2024113102A1 publication Critical patent/WO2024113102A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • Embodiments of the present disclosure relate to a display substrate and a display device.
  • Ultra-high resolution display technology can improve the display effect of the display screen and can also be applied to a variety of special displays, such as 3D display.
  • 3D display the existing display pixels are divided into multiple viewing angles (Views), each View displays object information at different angles, and with microlenses, 3D display can be achieved. The more Views there are, the better the 3D display effect is. The more Views there are, the higher the resolution is, the smaller the sub-pixel size is, and the lower the pixel aperture ratio is. The aperture ratio directly affects the life of the display device.
  • At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate, a pixel driving circuit layer, a first planarization layer, a first metal layer, a second planarization layer, a plurality of first electrodes and a pixel defining layer;
  • the pixel driving circuit layer is arranged on the base substrate, including a plurality of pixel driving circuits
  • the first planarization layer is arranged on a side of the pixel driving circuit layer away from the base substrate, including a plurality of first via holes respectively exposing output ends of the plurality of pixel driving circuits
  • the first metal layer is arranged on a side of the first planarization layer away from the base substrate, including a plurality of data lines extending along a first direction and a plurality of connecting electrodes, the plurality of connecting electrodes are respectively electrically connected to the output ends of the plurality of pixel driving circuits through the first via holes
  • the second planarization layer is arranged on the A side of the first metal layer away from the base substrate
  • the display substrate provided by at least one embodiment of the present disclosure also includes: a plurality of data connection lines, which are electrically connected to the plurality of data lines and the plurality of pixel driving circuits, respectively, wherein the plurality of data lines are electrically connected to the plurality of data connection lines through a plurality of third vias, respectively, and the orthographic projections of the plurality of third vias on the base substrate at least partially overlap with the orthographic projections of the plurality of pixel openings on the base substrate, respectively.
  • the orthographic projections of the plurality of first via holes on the base substrate are respectively located within the orthographic projections of the plurality of pixel openings on the base substrate.
  • the orthographic projections of the plurality of first via holes on the base substrate are respectively located within the orthographic projections of the plurality of second defining walls on the base substrate.
  • the orthographic projections of the plurality of second via holes on the base substrate are respectively located within the orthographic projections of the plurality of second defining walls on the base substrate.
  • the height of the plurality of first defining walls is smaller than the height of the plurality of second defining walls.
  • the display substrate provided by at least one embodiment of the present disclosure also includes: a light-emitting material layer, which is at least arranged in the multiple pixel openings, including multiple rows of light-emitting materials of different colors, wherein the multiple rows of light-emitting materials extend along the second direction and are separated by the multiple second defining walls.
  • a light-emitting material layer which is at least arranged in the multiple pixel openings, including multiple rows of light-emitting materials of different colors, wherein the multiple rows of light-emitting materials extend along the second direction and are separated by the multiple second defining walls.
  • each of the multiple pixel driving circuits includes a first thin film transistor and a first storage capacitor
  • the first thin film transistor includes a first gate, a first source and a first drain
  • the first storage capacitor includes a first capacitor electrode and a second capacitor electrode
  • the first gate is electrically connected to the first scanning signal line
  • the first source is electrically connected to one of the multiple data lines
  • the first drain is electrically connected to the first capacitor electrode
  • the second capacitor electrode is electrically connected to one of the multiple first electrodes.
  • the first gate electrode and the first capacitor electrode are arranged on the same layer on the base substrate
  • the display substrate also includes a gate insulating layer arranged on the side of the first gate electrode and the first capacitor electrode away from the base substrate
  • the second capacitor electrode is arranged on the side of the gate insulating layer away from the base substrate
  • the display substrate also includes an interlayer insulating layer arranged on the side of the second capacitor electrode away from the base substrate
  • the first source electrode and the first drain electrode are arranged on the side of the interlayer insulating layer away from the base substrate
  • the first planarization layer is arranged on the side of the first source electrode and the first drain electrode away from the base substrate.
  • the plurality of data connection lines are arranged in the same layer as the first source electrode and the first drain electrode.
  • the first scanning signal line is arranged in the same layer as the first source and the first drain.
  • the first scanning signal line is electrically connected to the first gate through a fourth via hole, and the orthographic projection of the fourth via hole on the base substrate is located within the orthographic projection of the multiple pixel openings on the base substrate.
  • each of the multiple pixel driving circuits also includes a second thin film transistor, the second thin film transistor includes a second gate, a second source and a second drain, the second gate is electrically connected to the second scanning signal line, the second source is electrically connected to the first drain and the first capacitor electrode, and the second drain is electrically connected to the reference voltage line.
  • the reference voltage line is disposed in the first metal layer and extends along the first direction.
  • the display substrate provided by at least one embodiment of the present disclosure further includes: a reference voltage connection line, which is electrically connected to the reference voltage line and the second drain respectively, wherein the reference voltage connection line is arranged in the same layer as the first source and the first drain.
  • the reference voltage connection line is electrically connected to the reference voltage line through a fifth via, and the orthographic projection of the fifth via on the base substrate at least partially overlaps with the orthographic projection of the multiple first defining layers on the base substrate.
  • each of the multiple pixel driving circuits also includes a third thin film transistor, the third thin film transistor includes a third gate, a third source and a third drain, the third gate is electrically connected to the third scanning signal line, the third source is electrically connected to the second capacitor electrode and one of the multiple first electrodes, and the third drain is electrically connected to the reset voltage line.
  • the reset voltage line is disposed in the first metal layer and extends along the first direction.
  • the display substrate provided by at least one embodiment of the present disclosure further includes: a reset voltage connection line, which is electrically connected to the reset voltage line and the third drain respectively, wherein the reset voltage connection line is arranged in the same layer as the first source and the first drain.
  • the reset voltage connection line is electrically connected to the reset voltage line through a sixth via hole, and the orthographic projection of the sixth via hole on the base substrate at least partially overlaps with the orthographic projection of the multiple second defining layers on the base substrate.
  • each of the plurality of pixel driving circuits further includes a fourth thin film transistor and a fifth thin film transistor
  • the fourth thin film transistor includes a fourth gate, a fourth source and a fourth drain
  • the fifth thin film transistor includes a fifth gate, a fifth source and a fifth drain
  • the fourth gate is electrically connected to the light emitting control line
  • the fourth source is electrically connected to the fifth drain
  • the fourth drain is electrically connected to the first power line
  • the fifth gate is electrically connected to the first drain and the first capacitor electrode
  • the fifth source is electrically connected to the second capacitor electrode and one of the plurality of first electrodes.
  • the first power line is disposed on the first metal layer and extends along the first direction.
  • the display substrate provided by at least one embodiment of the present disclosure further includes: a first power connection line, which is electrically connected to the first power line and the fourth drain respectively, wherein the first power connection line is arranged on the same layer as the first source and the first drain.
  • the first power connection line is electrically connected to the first power line through a seventh via hole, and the orthographic projection of the seventh via hole on the base substrate at least partially overlaps with the orthographic projection of the multiple first defining layers on the base substrate.
  • the display substrate provided by at least one embodiment of the present disclosure also includes multiple sub-pixels, wherein at least one of the sub-pixels includes N pixel driving circuits located in the same row, and the N pixel driving circuits correspond to N viewing angles, where N is a positive integer greater than 1.
  • M columns of pixel driving circuits constitute a repeating unit, and the M columns of pixel driving circuits of at least one of the repeating units share a reset voltage line and a reference voltage line, and M is a positive integer greater than 1.
  • At least one embodiment of the present disclosure provides a display device, which includes the display substrate provided by an embodiment of the present disclosure.
  • FIG1 is a partial cross-sectional schematic diagram of a display substrate provided by at least one embodiment of the present disclosure
  • FIG2 is another partial cross-sectional schematic diagram of a display substrate provided by at least one embodiment of the present disclosure
  • FIG3 is a partial plan view of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG4 is a partial plan view of a pixel defining layer of a display substrate provided by at least one embodiment of the present disclosure
  • FIG5 is a pixel circuit diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • 6 to 16 are plan views of various functional layers of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 17 is a plan view schematically showing the stacking of functional layers of a display substrate provided in at least one embodiment of the present disclosure.
  • the display pixels are divided into multiple Views, each View displays object information at different angles, and 3D display can be achieved with microlenses.
  • the size of the aperture ratio directly affects the life of the display device.
  • the lower the pixel aperture ratio is, the smaller the intrinsic capacitance of the OLED light emitting device is, and the greater the grayscale loss in the data writing stage is.
  • the size of the step difference at the bottom of the OLED light emitting device directly affects the light emitting performance of the OLED light emitting device. Therefore, how to comprehensively consider the above-mentioned various factors and design a display substrate that can achieve ultra-high resolution is the main research topic of technicians in this field.
  • At least one embodiment of the present disclosure provides a display substrate and a display device, wherein the display substrate includes a base substrate, a pixel driving circuit layer, a first planarization layer, a first metal layer, a second planarization layer, a plurality of first electrodes and a pixel defining layer; the pixel driving circuit layer is arranged on the base substrate, including a plurality of pixel driving circuits, the first planarization layer is arranged on a side of the pixel driving circuit layer away from the base substrate, including a plurality of first via holes respectively exposing output ends of the plurality of pixel driving circuits, the first metal layer is arranged on a side of the first planarization layer away from the base substrate, including a plurality of data lines extending along a first direction and a plurality of connecting electrodes, the plurality of connecting electrodes are respectively electrically connected to the output ends of the plurality of pixel driving circuits through the plurality of first via holes
  • the second planarization layer is arranged on a side of the
  • the above-mentioned display substrate provided by the embodiment of the present disclosure can make the vias connecting the multiple data lines with other circuits evenly distributed on the multiple first defining walls by at least partially overlapping at least part of the multiple data lines with the multiple first defining walls. This can ensure the uniformity of the bottom of the light-emitting device while expanding the pixel aperture ratio, which helps to improve the display uniformity of the display substrate and achieve high resolution.
  • the present disclosure provides a display substrate, and Figures 1 and 2 respectively show cross-sectional schematic diagrams of different positions of the display substrate, and Figure 3 shows a partial planar schematic diagram of the display substrate, for example, a planar schematic diagram of two adjacent pixel driving circuits.
  • the display substrate includes a base substrate 101, a pixel driving circuit layer D, a first planarization layer PLN1, a first metal layer M1, a second planarization layer PLN2, a plurality of first electrodes E1, and a pixel defining layer PDL.
  • the pixel driving circuit layer D is arranged on the base substrate 101, including multiple pixel driving circuits, such as 2T1C (i.e., including two thin film transistors and a storage capacitor), 3T1C, 5T1C, 5T2C, 7T1C, 8T2C or 9T2C pixel driving circuits, etc., which will be described in detail later.
  • 2T1C i.e., including two thin film transistors and a storage capacitor
  • the first planarization layer PLN1 is disposed on a side of the pixel driving circuit layer D away from the base substrate 101 and is used to planarize the pixel driving circuit layer D.
  • the first planarization layer PLN1 includes a plurality of first via holes V1 respectively exposing output ends of a plurality of pixel driving circuits.
  • the first metal layer M1 is arranged on a side of the first planarization layer PLN1 away from the base substrate 101, and includes a plurality of data lines Data extending along a first direction (vertical direction in FIG. 3 ) and a plurality of connecting electrodes CL.
  • the plurality of connecting electrodes CL are electrically connected to the output ends of a plurality of pixel driving circuits D through first via holes V1, respectively.
  • the second planarization layer PLN2 is disposed on a side of the first metal layer M1 away from the base substrate 101 , and includes a plurality of second via holes V2 exposing a plurality of connection electrodes CL.
  • the plurality of first electrodes E1 are disposed on a side of the second planarization layer PLN2 away from the base substrate 101 and are electrically connected to the plurality of connection electrodes CL through the plurality of second via holes V2 , so as to be electrically connected to the output ends of the plurality of pixel driving circuits.
  • the pixel defining layer PDL is arranged on a side of the multiple first electrodes E1 away from the base substrate 101.
  • Figure 4 shows a plan schematic diagram of the pixel defining layer PDL.
  • the pixel defining layer PDL includes a plurality of first defining walls PDL1 extending along a first direction (vertical direction in the figure) and a plurality of second defining walls PDL2 extending along a second direction.
  • the plurality of first defining walls PDL1 and the plurality of second defining walls PDL2 define a plurality of pixel openings PO.
  • the first direction is different from the second direction. For example, the first direction is perpendicular to the second direction.
  • the dotted box shows the stacking position of the first defining wall PDL1 and the second defining wall PDL2.
  • the orthographic projections of at least part of the multiple data lines Data on the base substrate 101 overlap at least partially with the orthographic projections of the multiple first defining walls PDL1 on the base substrate 101.
  • the first defining wall PDL1 and the data line Data extend in the same direction, that is, the first direction, and the two overlap at least partially, for example, mostly, in a direction perpendicular to the base substrate 101 .
  • the display substrate further includes a plurality of data connection lines Data1, and the plurality of data connection lines Data1 are electrically connected to the plurality of data lines Data and the plurality of pixel driving circuits D, respectively, so as to electrically connect the plurality of data lines Data and the plurality of pixel driving circuits D.
  • the plurality of data lines Data and the plurality of data connection lines Data1 are respectively arranged in different metal layers, and the plurality of data lines Data are electrically connected to the plurality of data connection lines Data1 through a plurality of third vias V3, respectively.
  • the orthographic projections of the plurality of third vias V3 on the base substrate 101 are at least partially overlapped with the orthographic projections of the plurality of pixel openings PO on the base substrate 101, respectively.
  • the orthographic projections of the plurality of third via holes V3 on the substrate 101 also overlap at least partially with the orthographic projections of the plurality of first delimiting walls PDL1 on the substrate 101, respectively.
  • the orthographic projections of the plurality of third via holes V3 on the substrate 101 also overlap at least partially with the orthographic projections of the plurality of pixel openings PO on the substrate 101.
  • the opening range of the plurality of pixel openings PO extends beyond the plurality of third via holes Data1, thereby having a larger opening area, thereby improving the sub-pixel opening ratio;
  • a second planarizing layer PLN2 is also provided on the first planarizing layer PLN1, and the second planarizing layer PLN2 can also play a planarizing role on the first planarizing layer PLN1, thereby making the bottom of the pixel opening PO relatively flat;
  • each pixel opening PO on the display substrate adopts such a design, so that the flatness of the bottom of each pixel opening PO is substantially the same, thereby also improving the light emission uniformity of the display substrate.
  • the orthographic projections of the plurality of first via holes V1 on the base substrate 101 are respectively located within the orthographic projections of the plurality of pixel openings PO on the base substrate 101. That is, the opening ranges of the plurality of pixel openings PO extend beyond the plurality of first via holes V1 to have a larger opening area, thereby improving the sub-pixel opening ratio.
  • the orthographic projections of the plurality of first via holes V1 on the base substrate 101 may also be respectively located within the orthographic projections of the plurality of second defining walls PDL2 on the base substrate 101 to increase the flatness of the bottom of the pixel opening PO.
  • the orthographic projections of the plurality of second via holes V2 on the base substrate 101 are respectively located within the orthographic projections of the plurality of second defining walls PDL2 on the base substrate 101. That is, the plurality of second via holes V2 will not be exposed by the plurality of pixel openings PO. Since the plurality of second via holes V2 are formed in the second planarization layer PLN2, and the second planarization layer PLN2 no longer has a planarization layer, the second via holes V2 are relatively uneven.
  • the flatness of the bottom of the plurality of pixel openings PO can be improved, which is beneficial to improving the light uniformity of the display substrate.
  • the height of the plurality of first delimiting walls PDL1 is less than the height of the plurality of second delimiting walls PDL2.
  • the first delimiting walls PDL1 are about 1.0 micrometers higher than the second delimiting walls PDL2.
  • the height of the second delimiting walls PDL2 may be about 1.2 micrometers to 2.0 micrometers, such as 1.5 micrometers
  • the height of the first delimiting walls PDL1 may be about 0.2 micrometers to 1.0 micrometers, such as 0.5 micrometers, etc.
  • the display substrate also includes a light-emitting material layer E2.
  • the light-emitting material layer E2 is at least arranged in a plurality of pixel openings PO, including a plurality of light-emitting material rows of different colors.
  • Three rows of light-emitting material rows P1/P2/P3 are shown in Figure 4 as an example.
  • the plurality of light-emitting material rows P1/P2/P3 extend along a second direction (horizontal direction in the figure) and are spaced apart by a plurality of second defining walls PDL2.
  • the luminescent materials of the plurality of luminescent material rows P1/P2/P3 are different, so that different colors of light can be emitted.
  • the luminescent material row P1 uses a red luminescent material R, so it can emit red light
  • the luminescent material row P2 uses a green luminescent material G, so it can emit green light
  • the luminescent material row P3 uses a blue luminescent material B, so it can emit blue light.
  • the plurality of luminescent material rows P1/P2/P3 are separated by a second defining wall PDL2 with a relatively high height, so as to prevent the luminescent materials of different colors from flowing into each other and causing crosstalk during the preparation process of the display substrate, for example, when printing the luminescent materials of the plurality of luminescent material rows P1/P2/P3.
  • a plurality of pixel openings PO corresponding to each luminescent material row P1/P2/P3 are spaced apart by a first defining wall PDL1 of relatively low height.
  • the luminescent material between different pixel openings PO of each luminescent material row P1/P2/P3 can flow and eventually reach a balance. After the luminescent material is dried, it can be at least uniformly formed in each pixel opening PO.
  • the display substrate further includes a second electrode layer E3 disposed on a side of the light-emitting material layer E2 away from the base substrate 101.
  • the first electrode E1, the light-emitting material layer E2, and the second electrode layer E3 constitute a light-emitting device EL, such as an organic light-emitting device (OLED).
  • the second electrode layer E3 may be an electrode layer formed on the entire surface of the display substrate, that is, the second electrode layers E3 of a plurality of light-emitting devices EL are continuously disposed.
  • the display substrate further includes an encapsulation layer EN disposed on the side of the second electrode layer E3 away from the base substrate 101.
  • the encapsulation layer EN may be a composite encapsulation layer including a stack of multiple organic encapsulation layers and inorganic encapsulation layers to provide a better encapsulation effect for the display substrate.
  • the display substrate includes a plurality of sub-pixels, at least one sub-pixel (e.g., each sub-pixel) includes N pixel driving circuits located in the same row, and the N pixel driving circuits correspond to N viewing angles, where N is a positive integer greater than 1.
  • FIG3 shows two sub-pixels, i.e., two viewing angles, as an example.
  • each pixel driving circuit is connected to a light emitting device EL to drive the light emitting device EL.
  • the light emitting device EL corresponding to the required viewing angle among the N viewing angles of each sub-pixel is driven and lit by the corresponding pixel driving circuit to perform corresponding display.
  • the pixel driving circuit can adopt a 5T2C pixel driving circuit, that is, including five thin film transistors and two capacitors.
  • FIG5 shows a circuit diagram of the 5T2C pixel driving circuit.
  • each pixel driving circuit includes a first thin film transistor T1 and a first storage capacitor Cst
  • the first thin film transistor T1 includes a first gate T1g, a first source T1s and a first drain T1d
  • the first storage capacitor Cst includes a first capacitor electrode C1 and a second capacitor electrode C2
  • the first gate T1g is electrically connected to the first scan signal line G1
  • the first source T1s is electrically connected to one of the multiple data lines Data
  • the first drain T1d is electrically connected to the first capacitor electrode C1
  • the second capacitor electrode C2 is electrically connected to one of the multiple first electrodes E1.
  • each pixel driving circuit also includes a second thin film transistor T2, the second thin film transistor T2 includes a second gate T2g, a second source T2s and a second drain T2d, the second gate T2g is electrically connected to the second scanning signal line G2, the second source T2s is electrically connected to the first drain T1d and the first capacitor electrode C1, and the second drain T2d is electrically connected to the reference voltage line Vref.
  • the second thin film transistor T2 includes a second gate T2g, a second source T2s and a second drain T2d
  • the second gate T2g is electrically connected to the second scanning signal line G2
  • the second source T2s is electrically connected to the first drain T1d and the first capacitor electrode C1
  • the second drain T2d is electrically connected to the reference voltage line Vref.
  • each pixel driving circuit also includes a third thin film transistor T3, the third thin film transistor T3 includes a third gate T3g, a third source T3s and a third drain T3d, the third gate T3g is electrically connected to the third scanning signal line G3, the third source T3s is electrically connected to the second capacitor electrode C2 and one of the plurality of first electrodes E1, and the third drain T3d is electrically connected to the reset voltage line Vini.
  • each pixel driving circuit also includes a fourth thin film transistor T4 and a fifth thin film transistor T5, the fourth thin film transistor T4 includes a fourth gate T4g, a fourth source T4s and a fourth drain T4d, the fifth thin film transistor T5 includes a fifth gate T5g, a fifth source T5s and a fifth drain T5d, the fourth gate T4g is electrically connected to the light emitting control line EM, the fourth source T4s is electrically connected to the fifth drain T5d, the fourth drain T4d is electrically connected to the first power line VDD, the fifth gate T5g is electrically connected to the first drain T1d and the first capacitor electrode C1, and the fifth source T5s is electrically connected to the second capacitor electrode C2 and one of the multiple first electrodes E1.
  • the fourth thin film transistor T4 includes a fourth gate T4g, a fourth source T4s and a fourth drain T4d
  • the fifth thin film transistor T5 includes a fifth gate T5g, a fifth source T5s
  • the second electrode layers E3 of the plurality of light emitting devices EL are connected to the second power line VSS.
  • the first electrode E1 and the second electrode layer E2 of the light emitting device EL also form a second storage capacitor Coled, which is also an intrinsic capacitor of the light emitting device EL.
  • the first power line VDD is a power line providing a high level voltage on the display substrate
  • the second power line VSS is a power line providing a ground level voltage.
  • the second power line VSS can also provide a ground voltage.
  • the source and drain of each transistor are symmetrical in structure, and their functions and connection methods can be interchanged.
  • the gate electrodes of the first to fifth thin film transistors T1 to T5 are respectively arranged in the same layer, and the source electrodes and drain electrodes of the first to fifth thin film transistors T1 to T5 are respectively arranged in the same layer.
  • “same-layer arrangement” means that two (or more) functional layers or structural layers are in the same layer and are formed of the same material in the hierarchical structure of the display substrate, that is, in the preparation process, the two (or more) functional layers or structural layers can be formed by the same material layer, and the required patterns and structures can be formed by the same composition process.
  • the first gate electrode T1g to the fifth gate electrode T5g (the third gate electrode T3g is shown in the figure) and the first capacitor electrode C1 are arranged on the same layer on the base substrate 101, for example, the first gate metal layer 103 arranged on the display substrate;
  • the display substrate further includes a gate insulating layer GI2 arranged on the side of the first gate electrode T1g to the fifth gate electrode T5g and the first capacitor electrode C1 away from the base substrate 101, and the second capacitor electrode C2 is arranged on the side of the gate insulating layer GI2 away from the base substrate 101 on one side of the interlayer insulating layer IDL, for example, a second gate metal layer 104 is arranged on the display substrate;
  • the display substrate also includes an interlayer insulating layer IDL arranged on the side of the second capacitor electrode C2 away from the base substrate 101, the first source T1s to the fifth source T5s and the first drain T1d to the fifth drain T5d are
  • the first transistor T1 to the fifth transistor T5 further include the first active layer T1a to the fifth active layer T5a, respectively, and the first active layer T1a to the fifth active layer T5a are respectively arranged on the side of the first gate electrode T1g to the fifth gate electrode T5g close to the substrate 101 (as shown in the figure) or the side away from the substrate 101, such as the semiconductor layer 102 arranged on the display substrate, to form a top-gate or bottom-gate thin film transistor.
  • the display substrate further includes another gate insulating layer GI1 arranged on the side of the first active layer T1a to the fifth active layer T5a away from the substrate 101 to insulate the semiconductor layer 102 and the first gate metal layer 103.
  • the display substrate may also include a first passivation layer PVX1 arranged on the side of the first metal layer M1 close to the base substrate 101 and a second passivation layer PVX2 arranged on the side of the first metal layer M1 away from the base substrate 101.
  • the first passivation layer PVX1 and the second passivation layer PVX2 may, for example, be made of inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride.
  • the plurality of data connection lines Data1 are disposed in the same layer as the first to fifth source electrodes T1s to T5s and the first to fifth drain electrodes T1d to T5d, that is, disposed in the first source-drain metal layer 105 .
  • the first scan signal line G1 is disposed in the same layer as the first source electrode T1s to the fifth source electrode T5s and the first drain electrode T1d to the fifth drain electrode T5d, that is, disposed in the first source-drain metal layer 105 .
  • the first scan signal line G1 includes a first scan signal line G11 for providing a first scan signal to an odd-numbered column pixel driving circuit and a first scan signal line G12 for providing a first scan signal to an even-numbered column pixel driving circuit, and the first scan signal line G11 and the first scan signal line G12 are adjacently arranged.
  • the first scanning signal line G1 is electrically connected to the first gate T1g through the fourth via hole V4, and the orthographic projection of the fourth via hole V4 on the base substrate 101 is located within the orthographic projection of the plurality of pixel openings PO on the base substrate 101.
  • the range of the plurality of pixel openings PO extends beyond the fourth via hole V4 to have a larger opening area and improve the opening ratio.
  • the reference voltage line Vref is disposed in the first metal layer M1 and extends along a first direction, that is, the same as the extending direction of the data line Data, which will be described in detail later.
  • the display substrate also includes a reference voltage connection line Vref1, which is electrically connected to the reference voltage line Vref and the second drain T2s respectively to electrically connect the reference voltage line Vref and the second drain T2s.
  • the reference voltage connection line Vref1 is arranged in the same layer as the first source T1s to the fifth source T5s and the first drain T1d to the fifth drain T5d, that is, it is arranged in the first source and drain metal layer 105.
  • the reference voltage connection line Vref1 is electrically connected to the reference voltage line Vref through the fifth via hole V5 (refer to FIG. 11, which will be described in detail later), and the orthographic projection of the fifth via hole V5 on the base substrate 101 at least partially overlaps with the orthographic projections of the plurality of first defining layers PDL1 on the base substrate 101.
  • the orthographic projection of the fifth via hole V5 on the base substrate 101 also at least partially overlaps with the orthographic projections of the plurality of pixel openings PO on the base substrate 101.
  • the range of the plurality of pixel openings PO extends beyond the fifth via hole V5 to have a larger opening area and improve the aperture ratio.
  • the reset voltage line Vini is disposed in the first metal layer M1 and extends along a first direction, that is, the same as the extending direction of the data line Data, which will be described in detail later.
  • the display substrate also includes a reset voltage connection line Vini1, which is electrically connected to the reset voltage line Vini and the third drain T3d respectively to electrically connect the reset voltage line Vini and the third drain T3d.
  • the reset voltage connection line Vini is arranged in the same layer as the first source T1s to the fifth source T5s and the first drain T1d to the fifth drain T5d, that is, arranged in the first source-drain metal layer 105.
  • the reset voltage connection line Vini1 is electrically connected to the reset voltage line Vini through a sixth via hole V6 (refer to FIG. 11, which will be described in detail later), and the orthographic projection of the sixth via hole V6 on the base substrate 101 at least partially overlaps with the orthographic projections of the plurality of second defining layers PDL2 on the base substrate 101.
  • the orthographic projection of the sixth via hole V6 on the base substrate 101 is located within the orthographic projections of the plurality of second defining layers PDL2 on the base substrate 101, so as not to be exposed by the plurality of pixel openings PO.
  • the first power line VDD is disposed in the first metal layer M1 and extends along a first direction, which is the same as the extending direction of the data line Data, which will be described in detail later.
  • the display substrate further includes a first power connection line VDD1, and the first power connection line VDD1 is electrically connected to the first power line VDD and the fourth drain T4d, respectively, so as to electrically connect the first power line VDD and the fourth drain T4d.
  • the first power connection line VDD1 is arranged in the same layer as the first source T1s to the fifth source T5s and the first drain T1d to the fifth drain T5d, that is, arranged in the first source-drain metal layer 105.
  • the first power connection line VDD1 is electrically connected to the first power line VDD through the seventh via V7, and the orthographic projection of the seventh via V7 on the base substrate 101 at least partially overlaps with the orthographic projections of the plurality of first defining layers PDL1 on the base substrate 101.
  • the orthographic projection of the seventh via V7 on the base substrate 101 also at least partially overlaps with the orthographic projections of the plurality of pixel openings PO on the base substrate 101.
  • the range of the plurality of pixel openings PO extends beyond the seventh via V7 to have a larger opening area and improve the aperture ratio.
  • FIG. 6 to FIG. 16 respectively show the planar schematic diagrams of each functional layer of the display substrate.
  • Each functional layer of the display substrate will be introduced below in conjunction with FIG. 6 to FIG. 16 .
  • each sub-pixel of the display substrate includes 11 pixel driving circuits corresponding to 11 viewing angles (views), that is, the above N is 11.
  • M columns of pixel driving circuits constitute a repeating unit, and the M columns of pixel driving circuits of at least one (e.g., each) repeating unit share a reset voltage line and a reference voltage line, and M is a positive integer greater than 1.
  • M is taken as an example for description.
  • FIG. 6 to FIG. 16 show a repeating unit of a display substrate, that is, 24 views, as an example.
  • At least partial structures of two adjacent pixel driving circuits in the same row are symmetrically arranged.
  • Figure 6 shows a semiconductor layer 102 of a display substrate, and the semiconductor layer 102 includes active layers of multiple transistors, for example, a first active layer T1a of a first transistor T1, a second active layer T2a of a second transistor T2, a third active layer T3a of a third transistor T3, a fourth active layer T4a of a fourth transistor T4, and a fifth active layer T5a of a fifth transistor T5.
  • patterns of the semiconductor layers 102 of two adjacent pixel driving circuits in the same row are symmetrically arranged.
  • Fig. 7 shows a schematic plan view of the first gate metal layer 103 of the display substrate.
  • the first gate metal layer 103 includes a first gate T1g of the first transistor T1, a second gate T2g of the second transistor T2, a third gate T3g of the third transistor T3, a fourth gate T4g of the fourth transistor T4, and a fifth gate T5g of the fifth transistor T5.
  • the first gate T1g is electrically connected to the first scanning signal line G1, and therefore can also serve as a part of the first scanning signal line G1;
  • the second gate T2g is electrically connected to the second scanning signal line G2, and therefore can also serve as a part of the second scanning signal line G2;
  • the third gate T3g is electrically connected to the third scanning signal line G3, and therefore can also serve as a part of the third scanning signal line G3;
  • the fourth gate T4g is electrically connected to the light emitting control signal line EM, and therefore can also serve as a part of the light emitting control signal line EM;
  • the fifth gate T5g for example, can also serve as the first capacitor electrode C1.
  • the patterns of the first gate metal layers 103 of two adjacent pixel driving circuits in the same row are mostly symmetrically arranged.
  • Fig. 8 shows a schematic plan view of the second gate metal layer 104 of the display substrate.
  • the second gate metal layer 104 includes a second capacitor electrode C2 of the first storage capacitor Cst, and the second capacitor electrode C2 overlaps with the first capacitor electrode C1 to form the first storage capacitor Cst.
  • the patterns of the second gate metal layers 104 of two adjacent pixel driving circuits in the same row are symmetrically arranged.
  • Fig. 9 shows a schematic plan view of an interlayer insulating layer IDL of a display substrate.
  • the interlayer insulating layer IDL includes a plurality of via holes, such as a fourth via hole V4 for connecting the first scanning signal line G1 and the first gate T1g, a via hole VT2 for connecting the second scanning signal line G2 and the second gate T2g, a via hole VT3 for connecting the third scanning signal line G3 and the third gate T3g, a via hole VT4 for connecting the light emitting control signal line EM and the fourth gate T4g, and the like.
  • via holes such as a fourth via hole V4 for connecting the first scanning signal line G1 and the first gate T1g, a via hole VT2 for connecting the second scanning signal line G2 and the second gate T2g, a via hole VT3 for connecting the third scanning signal line G3 and the third gate T3g, a via hole VT4 for connecting the light emitting control signal line EM and the fourth gate T4g,
  • Fig. 10 shows a schematic plan view of the first source-drain metal layer 105 of the display substrate.
  • the first source-drain metal layer 105 includes a reference voltage connection line Vref1, a reset voltage connection line Vini1, a first power connection line VDD1, a data connection line Data1, a first scan signal line G1, a second scan signal line G2, a third scan signal line G3, a light emitting control signal line EM, and first sources T1s to fifth sources T5s and first drains T1d to fifth drains T5d of first transistors T1 to T5.
  • the first scan signal line G1 is electrically connected to the first gate T1g through the fourth via V4
  • the second scan signal line G2 is electrically connected to the second gate T2g through the via VT2
  • the third scan signal line G3 is electrically connected to the third gate T3g through the via VT3
  • the light emitting control signal line EM is electrically connected to the fourth gate T4g through the via VT4.
  • the reference voltage connection line Vref1, the reset voltage connection line Vini1, the first power connection line VDD1, and the data connection line Data1 will be electrically connected to the corresponding signal lines through the via holes in the first planarization layer PLN1 behind.
  • the patterns of the first source-drain metal layers 105 of two adjacent pixel driving circuits in the same row are mostly symmetrically arranged.
  • Fig. 11 shows a schematic planar view of the first planarization layer PLN1 of the display substrate.
  • the first planarization layer PLN1 includes a plurality of vias, such as a third via V3 for connecting the data line Data with the data connection line Data1, a fifth via V5 for connecting the reference voltage connection line Vref1 with the reference voltage line Vref, a sixth via V6 for electrically connecting the reset voltage connection line Vini1 with the reset voltage line Vini, a seventh via V7 for electrically connecting the first power connection line VDD1 with the first power line VDD, and a first via V1 exposing the output end of the pixel driving circuit D.
  • a third via V3 for connecting the data line Data with the data connection line Data1
  • a fifth via V5 for connecting the reference voltage connection line Vref1 with the reference voltage line Vref
  • a sixth via V6 for electrically connecting the reset voltage connection line Vini1 with the reset voltage line Vini
  • a seventh via V7 for electrically connecting
  • Fig. 12 shows a schematic plan view of a first metal layer M1 of a display substrate.
  • the first metal layer M1 is also a second source-drain metal layer of the display substrate.
  • the first metal layer M1 includes a data line Data, a reference voltage line Vref, a first power line VDD, a reset voltage line Vini, and a connection electrode CL.
  • the data line Data, the reference voltage line Vref, the first power line VDD, and the reset voltage line Vini are respectively extended along the first direction (vertical direction in the figure), and a column of connecting electrodes CL is set between every two of the data line Data, the reference voltage line Vref, the first power line VDD, and the reset voltage line Vini.
  • the first power lines VDD and the data lines Data are alternately arranged.
  • every two adjacent columns of pixel driving circuits or every two adjacent views share one data line Data
  • every 24 adjacent columns of pixel driving circuits or every 24 views share 10 first power lines VDD.
  • every 24 adjacent columns of sub-pixels or every 24 views share one reference voltage line Vref
  • every 24 adjacent columns of sub-pixels or every 24 views share one reset voltage line Vini.
  • each sub-pixel includes 11 pixel driving circuits, corresponding to 11 viewing angles (View). Since every two adjacent columns of pixel driving circuits or every two adjacent views share a data line Data, if the difference between the reference voltage line Vref and the reset voltage line Vini is ignored, every 12 columns of pixel driving circuits can constitute a repeating unit, and multiple repeating units are arranged in sequence on the substrate 101; considering the connection relationship between the reference voltage line Vref and the reset voltage line Vini and the difference in the electrical signals provided, in a strict sense, every 24 columns of pixel driving circuits can constitute a repeating unit, and multiple repeating units are arranged in sequence on the substrate 101; at this time, every 24 columns of pixel driving circuits share a reference voltage line Vref and a reset voltage line Vini.
  • patterns of the first metal layers M1 of two adjacent pixel driving circuits in the same row are mostly symmetrically arranged.
  • the data connection line Data1, the reference voltage connection line Vref1, the reset voltage connection line Vini1 and the first power connection line VDD1 extend respectively along the second direction (the horizontal direction in the figure) to introduce the electrical signals transmitted by the data line Data, the reference voltage line Vref, the first power line VDD and the reset voltage line Vini into each pixel driving circuit of each row.
  • a schematic plan view of the second planarization layer PLN2 of the display substrate is shown in Fig. 13.
  • the second planarization layer PLN2 includes a plurality of second via holes V2 exposing the connection electrodes CL, and the plurality of second via holes V2 respectively expose the plurality of connection electrodes CL.
  • a schematic plan view of a plurality of first electrodes of a display substrate is shown in Fig. 14.
  • a plurality of first electrodes E1 are arranged at intervals, for example, in a rectangular shape, and the plurality of first electrodes E1 are electrically connected to a plurality of connection electrodes CL through a plurality of second via holes V2.
  • FIG15 shows a schematic plan view of a pixel defining layer PDL of a display substrate.
  • the pixel defining layer PDL includes a plurality of first defining walls PDL1 extending along a first direction and a plurality of second defining walls PDL2 extending along a second direction to define a plurality of pixel openings PO.
  • the plurality of pixel openings PO respectively expose a plurality of first electrodes E1 so that the light emitting material layer E2 is formed in the plurality of pixel openings PO and contacts the plurality of first electrodes E1.
  • Fig. 16 shows a schematic plan view of the light-emitting material layer E2 of the display substrate.
  • the light-emitting material layer E2 includes a plurality of light-emitting material rows
  • Fig. 16 shows three light-emitting material rows P1/P2/P3 as an example.
  • the plurality of light-emitting material rows P1/P2/P3 extend along the second direction (horizontal direction in the figure), and the light-emitting materials of the plurality of light-emitting material rows are different and are separated by a plurality of second defining walls PDL2.
  • the light emitting material layer E2 also has structures such as a second electrode layer E3 and an encapsulation layer EN. These structures can be formed on the entire surface of the display substrate, that is, formed into a continuous sheet, which will not be described in detail here.
  • FIG17 is a stack of the functional layers in FIGS. 6 to 16 , wherein the dotted-line frame portion is the portion shown in FIG3 .
  • the substrate substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate may include, but is not limited to, one or more of glass and quartz
  • the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked, and the materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate.
  • PI polyimide
  • PET polyethylene terephthalate
  • SiNx silicon nitride
  • SiOx silicon oxide
  • the material of the semiconductor layer 102 can be a semiconductor material such as metal oxide, such as amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO) or amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene.
  • metal oxide such as amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO) or amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene.
  • the first gate metal layer 103, the second gate metal layer 104, the first source-drain metal layer 105 and the first metal layer M1 can be made of metal materials, such as any one or more of titanium (Ti), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • metal materials such as any one or more of titanium (Ti), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb)
  • AlNd aluminum-neodymium alloy
  • MoNb molybdenum-niobium alloy
  • the gate insulating layer GI1, the gate insulating layer GI2 and the interlayer insulating layer IDL may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer.
  • first planar layer PLN1 and the second planar layer PLN2 may be made of organic materials, such as polyimide, resin, and the like.
  • the first electrode E1 of the light-emitting device EL can be made of transparent metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), gallium zinc oxide (GZO), or a stack of transparent metal oxides and metals (such as silver), and the material of the second electrode E3 can be made of metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).
  • transparent metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), gallium zinc oxide (GZO), or a stack of transparent metal oxides and metals (such as silver)
  • the material of the second electrode E3 can be made of metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).
  • the encapsulation layer EN may be a laminate of organic and inorganic materials, the organic material may be polyimide, resin, etc., and the inorganic material may be silicon oxide (SiOx), silicon nitride (SiNx) or silicon oxynitride (SiON), etc.
  • the embodiments of the present disclosure do not limit the specific materials of the above functional layers.
  • At least one embodiment of the present disclosure provides a display device, which includes a display substrate provided in an embodiment of the present disclosure.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

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Abstract

一种显示基板和显示装置，该显示基板包括衬底基板(101)、像素驱动电路层(D)、第一平坦化层(PLN1)、第一金属层(M1)、第二平坦化层(PLN2)、多个第一电极(E1)和像素界定层(PDL)；像素驱动电路层(D)包括多个像素驱动电路，第一平坦化层(PLN1)包括分别暴露多个像素驱动电路的输出端的多个第一过孔(V1)，第一金属层(M1)包括沿第一方向延伸的多个数据线(Data)以及多个连接电极(CL)，多个连接电极(CL)分别通过第一过孔(V1)与多个像素驱动电路的输出端电连接，第二平坦化层(PLN2)包括暴露多个连接电极(CL)的多个第二过孔(V2)，多个第一电极(E1)分别通过多个第二过孔(V2)与多个连接电极(CL)电连接，像素界定层(PDL)包括沿第一方向延伸的多个第一界定墙(PDL1)以及沿第二方向延伸的多个第二界定墙(PDL2)，多个第一界定墙(PDL1)和多个第二界定墙(PDL2)限定出多个像素开口(PO)，多个数据线(Data)中的至少部分在衬底基板(101)上的正投影分别与多个第一界定墙(PDL1)在衬底基板(101)上的正投影至少部分交叠。该显示基板具有更高的开口率，因此具有更好的显示效果。

Description

显示基板和显示装置 技术领域
本公开的实施例涉及一种显示基板和显示装置。
背景技术
超高分辨率显示技术可以提升显示屏的显示效果，还可以应用于多种特殊显示中，例如3D显示。3D显示中将现有的显示像素分为多个视角(View)，每个View显示不同角度的物信息，搭配微透镜，可以实现3D显示。View数目越多，3D显示效果越好，而View数目越多，相当于分辨率越高，子像素尺寸越小，像素开口率越低，而开口率的大小直接影响显示器件的寿命。
发明内容
本公开至少一实施例提供一种显示基板，该显示基板包括衬底基板、像素驱动电路层、第一平坦化层、第一金属层、第二平坦化层、多个第一电极和像素界定层；像素驱动电路层设置在所述衬底基板上，包括多个像素驱动电路，第一平坦化层设置在所述像素驱动电路层的远离所述衬底基板的一侧，包括分别暴露所述多个像素驱动电路的输出端的多个第一过孔，第一金属层设置在所述第一平坦化层的远离所述衬底基板的一侧，包括沿第一方向延伸的多个数据线以及多个连接电极，所述多个连接电极分别通过所述第一过孔与所述多个像素驱动电路的输出端电连接，第二平坦化层，设置在所述第一金属层的远离所述衬底基板的一侧，包括暴露所述多个连接电极的多个第二过孔，多个第一电极设置在所述第二平坦化层的远离所述衬底基板的一侧，分别通过所述多个第二过孔与所述多个连接电极电连接，像素界定层设置在所述多个第一电极的远离所述衬底基板的一侧，包括沿所述第一方向延伸的多个第一界定墙以及沿第二方向延伸的多个第二界定墙，所述多个第一界定墙和所述多个第二界定墙限定出多个像素开口，所述第一方向不同于所述第二方向，其中，所述多个数据线中的至少部分在所述衬底基板上的正投影分别与所述多个第一界定墙在所述衬底基板上的正投影至少部分交 叠。
例如，本公开至少一实施例提供的显示基板还包括：多条数据连接线，分别与所述多个数据线和所述多个像素驱动电路电连接，其中，所述多个数据线分别通过多个第三过孔与所述多条数据连接线电连接，所述多个第三过孔在所述衬底基板上的正投影分别与所述多个像素开口在所述衬底基板上的正投影至少部分交叠。
例如，本公开至少一实施例提供的显示基板中，所述多个第一过孔在所述衬底基板上的正投影分别位于所述多个像素开口在所述衬底基板上的正投影内。
例如，本公开至少一实施例提供的显示基板中，所述多个第一过孔在所述衬底基板上的正投影分别位于所述多个第二界定墙在所述衬底基板上的正投影内。
例如，本公开至少一实施例提供的显示基板中，所述多个第二过孔在所述衬底基板上的正投影分别位于所述多个第二界定墙在所述衬底基板上的正投影内。
例如，本公开至少一实施例提供的显示基板中，在垂直于所衬底基板的方向上，所述多个第一界定墙的高度小于所述多个第二界定墙的高度。
例如，本公开至少一实施例提供的显示基板还包括：发光材料层，至少设置在所述多个像素开口中，包括不同颜色的多个发光材料行，其中，所述多个发光材料行沿所述第二方向延伸，且被所述多个第二界定墙间隔。
例如，本公开至少一实施例提供的显示基板中，所述多个像素驱动电路的每个包括第一薄膜晶体管和第一存储电容，所述第一薄膜晶体管包括第一栅极、第一源极和第一漏极，所述第一存储电容包括第一电容电极和第二电容电极，所述第一栅极与第一扫描信号线电连接，所述第一源极与所述多个数据线中的一个电连接，所述第一漏极与所述第一电容电极电连接，所述第二电容电极与所述多个第一电极中的一个电连接。
例如，本公开至少一实施例提供的显示基板中，所述第一栅极和所述第一电容电极同层设置在所述衬底基板上，所述显示基板还包括设置 在所述第一栅极和所述第一电容电极远离所述衬底基板一侧的栅绝缘层，所述第二电容电极设置在所述栅绝缘层的远离所述衬底基板的一侧，所述显示基板还包括设置在所述第二电容电极远离所述衬底基板一侧的层间绝缘层，所述第一源极和所述第一漏极设置在所述层间绝缘层的远离所述衬底基板的一侧，所述第一平坦化层设置在所述第一源极和所述第一漏极的远离所述衬底基板的一侧。
例如，本公开至少一实施例提供的显示基板中，所述多条数据连接线与所述第一源极和所述第一漏极同层设置。
例如，本公开至少一实施例提供的显示基板中，所述第一扫描信号线与所述第一源极和所述第一漏极同层设置。
例如，本公开至少一实施例提供的显示基板中，所述第一扫描信号线与所述第一栅极通过第四过孔电连接，所述第四过孔在所述衬底基板上的正投影位于所述多个像素开口在所述衬底基板上的正投影内。
例如，本公开至少一实施例提供的显示基板中，所述多个像素驱动电路的每个还包括第二薄膜晶体管，所述第二薄膜晶体管包括第二栅极、第二源极和第二漏极，所述第二栅极与第二扫描信号线电连接，所述第二源极与所述第一漏极和所述第一电容电极电连接，所述第二漏极与参考电压线电连接。
例如，本公开至少一实施例提供的显示基板中，所述参考电压线设置在所述第一金属层，且沿所述第一方向延伸。
例如，本公开至少一实施例提供的显示基板还包括：参考电压连接线，分别与所述参考电压线和所述第二漏极电连接，其中，所述参考电压连接线与所述第一源极和所述第一漏极同层设置。
例如，本公开至少一实施例提供的显示基板中，所述参考电压连接线与所述参考电压线通过第五过孔电连接，所述第五过孔在所述衬底基板上的正投影与所述多个第一界定层在所述衬底基板上的正投影至少部分交叠。
例如，本公开至少一实施例提供的显示基板中，所述多个像素驱动电路的每个还包括第三薄膜晶体管，所述第三薄膜晶体管包括第三栅极、第三源极和第三漏极，所述第三栅极与第三扫描信号线电连接，所述第三源极与所述第二电容电极和所述多个第一电极中的一个电连接， 所述第三漏极与复位电压线电连接。
例如，本公开至少一实施例提供的显示基板中，所述复位电压线设置在所述第一金属层，且沿所述第一方向延伸。
例如，本公开至少一实施例提供的显示基板还包括：复位电压连接线，分别与所述复位电压线和所述第三漏极电连接，其中，所述复位电压连接线与所述第一源极和所述第一漏极同层设置。
例如，本公开至少一实施例提供的显示基板中，所述复位电压连接线与所述复位电压线通过第六过孔电连接，所述第六过孔在所述衬底基板上的正投影与所述多个第二界定层在所述衬底基板上的正投影至少部分交叠。
例如，本公开至少一实施例提供的显示基板中，所述多个像素驱动电路的每个还包括第四薄膜晶体管和第五薄膜晶体管，所述第四薄膜晶体管包括第四栅极、第四源极和第四漏极，所述第五薄膜晶体管包括第五栅极、第五源极和第五漏极，所述第四栅极与发光控制线电连接，所述第四源极与所述第五漏极电连接，所述第四漏极与第一电源线电连接，所述第五栅极与所述第一漏极和所述第一电容电极电连接，所述第五源极与所述第二电容电极和所述多个第一电极中的一个电连接。
例如，本公开至少一实施例提供的显示基板中，所述第一电源线设置在所述第一金属层，且沿所述第一方向延伸。
例如，本公开至少一实施例提供的显示基板还包括：第一电源连接线，分别与所述第一电源线和所述第四漏极电连接，其中，所述第一电源连接线与所述第一源极和所述第一漏极同层设置。
例如，本公开至少一实施例提供的显示基板中，所述第一电源连接线与所述第一电源线通过第七过孔电连接，所述第七过孔在所述衬底基板上的正投影与所述多个第一界定层在所述衬底基板上的正投影至少部分交叠。
例如，本公开至少一实施例提供的显示基板还包括多个子像素，其中，至少一个所述子像素包括位于同一行的N个像素驱动电路，所述N个像素驱动电路对应N个视角，N为大于1的正整数。
例如，本公开至少一实施例提供的显示基板中，M列像素驱动电路构成一个重复单元，至少一个所述重复单元的M列像素驱动电路共用 一个复位电压线和一个参考电压线，M为大于1的正整数。
本公开至少一实施例提供一种显示装置，该显示装置包括本公开实施例提供的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开至少一实施例提供的显示基板的部分截面示意图；
图2为本公开至少一实施例提供的显示基板的另一部分截面示意图；
图3为本公开至少一实施例提供的显示基板的部分平面示意图；
图4为本公开至少一实施例提供的显示基板的像素界定层的部分平面示意图；
图5为本公开至少一实施例提供的显示基板的像素电路图；
图6-图16为本公开至少一实施例提供的显示基板的各个功能层的平面示意图；以及
图17为本公开至少一实施例提供的显示基板的各个功能层叠层的平面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他 元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
如前面所述，3D显示中将显示像素分为多个View，每个View显示不同角度的物信息，搭配微透镜，可以实现3D显示，View数目越多，3D显示效果越好，而View数目越多，相当于分辨率越高，子像素尺寸越小，像素开口率越低。开口率的大小直接影响显示器件的寿命。另外，对于有机发光二极管(OLED)显示装置的内部补偿像素电路，像素开口率越低，OLED发光器件的本征电容越小，其写数据阶段灰阶损失越大。此外，对于打印OLED发光器件的发光层的工艺，OLED发光器件底部段差的大小直接影响OLED发光器件的发光性能。因此，如何综合考虑上述各种因素，设计出可以实现超高分辨率的显示基板，是本领域技术人员主要研究的课题。
本公开至少一实施例提供一种显示基板和显示装置，该显示基板包括衬底基板、像素驱动电路层、第一平坦化层、第一金属层、第二平坦化层、多个第一电极和像素界定层；像素驱动电路层设置在衬底基板上，包括多个像素驱动电路，第一平坦化层设置在像素驱动电路层的远离衬底基板的一侧，包括分别暴露多个像素驱动电路的输出端的多个第一过孔，第一金属层设置在第一平坦化层的远离衬底基板的一侧，包括沿第一方向延伸的多个数据线以及多个连接电极，多个连接电极分别通过多个第一过孔与多个像素驱动电路的输出端电连接，第二平坦化层设置在第一金属层的远离衬底基板的一侧，包括暴露多个连接电极的多个第二过孔，多个第一电极设置在第二平坦化层的远离衬底基板的一侧，分别通过多个第二过孔与多个连接电极电连接，像素界定层设置在多个第一电极的远离衬底基板的一侧，包括沿第一方向延伸的多个第一界定墙以及沿第二方向延伸的多个第二界定墙，多个第一界定墙和多个第二界定墙限定出多个像素开口，第一方向不同于第二方向；多个数据线中的至少部分在衬底基板上的正投影分别与多个第一界定墙在衬底基板上的正投影至少部分交叠。
本公开实施例提供的上述显示基板通过将多个数据线中的至少部分与多个第一界定墙至少部分交叠设置，可以使多个数据线与其他电路 连接的过孔均匀分布在多个第一界定墙处，由此可以在扩大像素开口率的同时，保证发光器件底部的均匀性，有助于提高显示基板的显示均匀性并实现高分辨率。
下面，通过几个具体的实施例来详细说明本公开实施例提供的显示基板以及显示装置。
本公开至少一实施例提供一种显示基板，图1和图2分别示出了该显示基板不同位置的截面示意图，图3示出了该显示基板的部分平面示意图，例如示出了相邻的两个像素驱动电路的平面示意图。如图1-图3所示，该显示基板包括衬底基板101、像素驱动电路层D、第一平坦化层PLN1、第一金属层M1、第二平坦化层PLN2、多个第一电极E1和像素界定层PDL等结构。
像素驱动电路层D设置在衬底基板101上，包括多个像素驱动电路，例如2T1C(即包括两个薄膜晶体管和一个存储电容)、3T1C、5T1C、5T2C、7T1C、8T2C或者9T2C像素驱动电路等，稍后详细描述。
第一平坦化层PLN1设置在像素驱动电路层D的远离衬底基板101的一侧，用于平坦化像素驱动电路层D，第一平坦化层PLN1包括分别暴露多个像素驱动电路的输出端的多个第一过孔V1。
第一金属层M1设置在第一平坦化层PLN1的远离衬底基板101的一侧，包括沿第一方向(图3中的竖直方向)延伸的多个数据线Data以及多个连接电极CL，多个连接电极CL分别通过第一过孔V1与多个像素驱动电路D的输出端电连接。
第二平坦化层PLN2设置在第一金属层M1的远离衬底基板101的一侧，包括暴露多个连接电极CL的多个第二过孔V2。
多个第一电极E1设置在第二平坦化层PLN2的远离衬底基板101的一侧，分别通过多个第二过孔V2与多个连接电极CL电连接，以与多个像素驱动电路的输出端电连接。
像素界定层PDL设置在多个第一电极E1的远离衬底基板101的一侧，图4示出了像素界定层PDL的平面示意图，如图4所示，像素界定层PDL包括沿第一方向(图中的竖直方向)延伸的多个第一界定墙PDL1以及沿第二方向延伸的多个第二界定墙PDL2，多个第一界定墙PDL1和多个第二界定墙PDL2限定出多个像素开口PO，第一方向不同 于第二方向，例如，第一方向垂直于第二方向。
在图3中，虚线框示出了第一界定墙PDL1和第二界定墙PDL2的叠层位置，如图3所示，多个数据线Data中的至少部分在衬底基板101上的正投影分别与多个第一界定墙PDL1在衬底基板101上的正投影至少部分交叠。
也即，在本公开的实施例中，第一界定墙PDL1和数据线Data沿相同的方向，也即上述第一方向延伸，二者在垂直于衬底基板101的方向上至少部分交叠，例如大部分交叠。
例如，在一些实施例中，如图3所示，显示基板还包括多条数据连接线Data1，多条数据连接线Data1分别与多个数据线Data和多个像素驱动电路D电连接，以将多个数据线Data和多个像素驱动电路D电连接。例如，多个数据线Data与多条数据连接线Data1分别设置在不同的金属层中，多个数据线Data分别通过多个第三过孔V3与多条数据连接线Data1电连接。例如，多个第三过孔V3在衬底基板101上的正投影分别与多个像素开口PO在衬底基板101上的正投影至少部分交叠。
例如，多个第三过孔V3在衬底基板101上的正投影也分别与多个第一界定墙PDL1在衬底基板101上的正投影至少部分交叠，但是由于第一界定墙PDL1的宽度较窄，因此多个第三过孔V3在衬底基板101上的正投影也会与多个像素开口PO在衬底基板101上的正投影至少部分交叠。也即，多个像素开口PO的开口范围延伸至多个第三过孔Data1之外，从而具有较大的开口面积，由此可以提高子像素开口率；另一方面，第一平坦化层PLN1上还设置有第二平坦化层PLN2，第二平坦化层PLN2也可以对第一平坦化层PLN1起到平坦化的作用，使得像素开口PO的底部较为平坦；再一方面，显示基板上的每个像素开口PO均采用这样的设计，使得每个像素开口PO的底部平坦性基本相同，由此还可以提高显示基板的发光均匀性。
例如，在一些实施例中，多个第一过孔V1在衬底基板101上的正投影分别位于多个像素开口PO在衬底基板101上的正投影内。也即，多个像素开口PO的开口范围延伸至多个第一过孔V1之外，以具有较大的开口面积，提高子像素开口率。
例如，在另一些实施例中，多个第一过孔V1在衬底基板101上的 正投影也可以分别位于多个第二界定墙PDL2在衬底基板101上的正投影内，以增加像素开口PO的底部平坦性。
例如，在一些实施例中，多个第二过孔V2在衬底基板101上的正投影分别位于多个第二界定墙PDL2在衬底基板101上的正投影内。也即，多个第二过孔V2不会被多个像素开口PO暴露。由于多个第二过孔V2形成在第二平坦化层PLN2中，第二平坦化层PLN2上不再具有平坦化层，因此第二过孔V2处相对不平坦，通过将多个第二过孔V2设置在多个第二界定墙PDL2下，不被多个像素开口PO暴露，可以提高多个像素开口PO底部的平坦性，有利于提高显示基板的出光均匀性。
例如，在一些实施例中，在垂直于衬底基板101的方向上，多个第一界定墙PDL1的高度小于多个第二界定墙PDL2的高度。例如，在一些示例中，第一界定墙PDL1高于第二界定墙PDL2约1.0微米。例如，第二界定墙PDL2的高度可以为约1.2微米-2.0微米，例如1.5微米，第一界定墙PDL1的高度可以为约0.2微米-1.0微米，例如0.5微米等。
例如，在一些实施例中，显示基板还包括发光材料层E2，参考图1和图4，发光材料层E2至少设置在多个像素开口PO中，包括不同颜色的多个发光材料行，在图4中示出三行发光材料行P1/P2/P3作为示例，多个发光材料行P1/P2/P3沿第二方向(图中的水平方向)延伸，且被多个第二界定墙PDL2间隔。
例如，多个发光材料行P1/P2/P3的发光材料不同，从而可发出不同颜色的光。例如，在一些示例中，发光材料行P1采用红色发光材料R，因此可发出红光；发光材料行P2采用绿色发光材料G，因此可发出绿光；发光材料行P3采用蓝色发光材料B，因此可发出蓝光。在第一方向上，多个发光材料行P1/P2/P3采用高度较高的第二界定墙PDL2间隔开，以防止在显示基板的制备过程中，例如在打印多个发光材料行P1/P2/P3的发光材料时，不同颜色的发光材料之间相互流动，发生串扰。在第二方向上，每个发光材料行P1/P2/P3对应的多个像素开口PO之间采用高度较低的第一界定墙PDL1间隔，在显示基板的制备过程中，例如在打印每个发光材料行P1/P2/P3的发光材料时，每个发光材料行P1/P2/P3的不同像素开口PO之间的发光材料可以流动，最终达到平衡，待发光材料干燥后，可至少均匀形成在每个像素开口PO内。
例如，参考图1，显示基板还包括设置在发光材料层E2的远离衬底基板101一侧的第二电极层E3。例如，第一电极E1、发光材料层E2和第二电极层E3组成发光器件EL，例如有机发光器件(OLED)。例如，第二电极层E3可以是在显示基板上整面形成的电极层，也即，多个发光器件EL的第二电极层E3连续设置。
例如，参考图1，显示基板还包括设置在第二电极层E3的远离衬底基板101一侧的封装层EN。例如，封装层EN可以为复合封装层，包括多个有机封装层和无机封装层的叠层，以对显示基板提供更好的封装效果。
例如，在一些实施例中，显示基板包括多个子像素，至少一个子像素(例如每个子像素)包括位于同一行的N个像素驱动电路，N个像素驱动电路对应N个视角，N为大于1的正整数。图3中示出了两个子像素，也即2个视角作为示例。
例如，每个像素驱动电路连接一个发光器件EL，以驱动该发光器件EL。例如，在进行例如3D显示时，每个子像素的N个视角中所需要的视角对应的发光器件EL被相应的像素驱动电路驱动点亮，以进行相应地显示。例如，在一些实施例中，像素驱动电路可以采用5T2C像素驱动电路，也即包括五个薄膜晶体管和两个电容。图5示出了该5T2C像素驱动电路的电路图。
例如，在一些实施例中，如图5所示，每个像素驱动电路包括第一薄膜晶体管T1和第一存储电容Cst，第一薄膜晶体管T1包括第一栅极T1g、第一源极T1s和第一漏极T1d，第一存储电容Cst包括第一电容电极C1和第二电容电极C2，第一栅极T1g与第一扫描信号线G1电连接，第一源极T1s与多个数据线Data中的一个电连接，第一漏极T1d与第一电容电极C1电连接，第二电容电极C2与多个第一电极E1中的一个电连接。
例如，每个像素驱动电路还包括第二薄膜晶体管T2，第二薄膜晶体管T2包括第二栅极T2g、第二源极T2s和第二漏极T2d，第二栅极T2g与第二扫描信号线G2电连接，第二源极T2s与第一漏极T1d和第一电容电极C1电连接，第二漏极T2d与参考电压线Vref电连接。
例如，每个像素驱动电路的还包括第三薄膜晶体管T3，第三薄膜 晶体管T3包括第三栅极T3g、第三源极T3s和第三漏极T3d，第三栅极T3g与第三扫描信号线G3电连接，第三源极T3s与第二电容电极C2和多个第一电极E1中的一个电连接，第三漏极T3d与复位电压线Vini电连接。
例如，每个像素驱动电路还包括第四薄膜晶体管T4和第五薄膜晶体管T5，第四薄膜晶体管T4包括第四栅极T4g、第四源极T4s和第四漏极T4d，第五薄膜晶体管T5包括第五栅极T5g、第五源极T5s和第五漏极T5d，第四栅极T4g与发光控制线EM电连接，第四源极T4s与第五漏极T5d电连接，第四漏极T4d与第一电源线VDD电连接，第五栅极T5g与第一漏极T1d和第一电容电极C1电连接，第五源极T5s与第二电容电极C2和多个第一电极E1中的一个电连接。
例如，多个发光器件EL的第二电极层E3连接至第二电源线VSS。发光器件EL的第一电极E1和第二电极层E2还形成了第二存储电容Coled，第二存储电容Coled也是发光器件EL的本征电容。
例如，在一些实施例中，第一电源线VDD为显示基板上提供高电平电压的电源线，第二电源线VSS为提供地电平电压的电源线，例如，在一些示例中，第二电源线VSS也可以提供接地电压。
例如，在本公开的实施例中，每个晶体管的源极和漏极在结构上是对称的，二者的功能和连接方式可以互换。
例如，在显示基板的叠层结构中，第一薄膜晶体管T1～第五薄膜晶体管T5的栅极分别同层设置，第一薄膜晶体管T1～第五薄膜晶体管T5的源极和漏极分别同层设置。
需要注意的是，在本公开的实施例中，“同层设置”为两个(或更多个)功能层或结构层在显示基板的层级结构中同层且同材料形成，即在制备工艺中，该两个(或更多个)功能层或结构层可以由同一个材料层形成，且可以通过同一构图工艺形成所需要的图案和结构。
例如，参考图1和图2，第一栅极T1g～第五栅极T5g(图中示出了第三栅极T3g)和第一电容电极C1同层设置在衬底基板101上，例如设置在显示基板上的第一栅金属层103；显示基板还包括设置在第一栅极T1g～第五栅极T5g和第一电容电极C1远离衬底基板101一侧的栅绝缘层GI2，第二电容电极C2设置在栅绝缘层GI2的远离衬底基板101 的一侧，例如设置在显示基板上的第二栅金属层104；显示基板还包括设置在第二电容电极C2远离衬底基板101一侧的层间绝缘层IDL，第一源极T1s～第五源极T5s和第一漏极T1d～第五漏极T5d设置在层间绝缘层IDL的远离衬底基板101的一侧，例如设置在显示基板上的第一源漏电极层105；第一平坦化层PDL1设置在第一源极T1s～第五源极T5s和第一漏极T1d～第五漏极T5d的远离衬底基板101的一侧。
例如，参考图1和图2，第一晶体管T1～第五晶体管T5还分别包括第一有源层T1a～第五有源层T5a，第一有源层T1a～第五有源层T5a分别设置在第一栅极T1g～第五栅极T5g的靠近衬底基板101的一侧(图中示出的情况)或者远离衬底基板101的一侧，例如设置在显示基板上的半导体层102，以形成顶栅型或者底栅型薄膜晶体管。例如，显示基板还包括设置在第一有源层T1a～第五有源层T5a的远离衬底基板101一侧的另一栅绝缘层GI1，以绝缘半导体层102和第一栅金属层103。
例如，在一些实施例中，参考图1和图2，显示基板还可以包括设置在第一金属层M1的靠近衬底基板101一侧的第一钝化层PVX1和设置在第一金属层M1的远离衬底基板101一侧的第二钝化层PVX2，第一钝化层PVX1和第二钝化层PVX2例如可以采用无机绝缘材料，例如氧化硅、氮化硅或者氮氧化硅等。
例如，在一些实施例中，多条数据连接线Data1与第一源极T1s～第五源极T5s和第一漏极T1d～第五漏极T5d同层设置，也即设置在第一源漏金属层105。
例如，在一些实施例中，第一扫描信号线G1与第一源极T1s～第五源极T5s和第一漏极T1d～第五漏极T5d同层设置，也即设置在第一源漏金属层105。
例如，在一些实施例中，第一扫描信号线G1包括为奇数列像素驱动电路提供第一扫描信号的第一扫描信号线G11和为偶数列像素驱动电路提供第一扫描信号的第一扫描信号线G12，第一扫描信号线G11和第一扫描信号线G12相邻设置。
例如，参考图3，第一扫描信号线G1与第一栅极T1g通过第四过孔V4电连接，第四过孔V4在衬底基板101上的正投影位于多个像素开口PO在衬底基板101上的正投影内。由此，多个像素开口PO的范 围延伸至第四过孔V4之外，以具有较大的开口面积，提高开口率。
例如，在一些实施例中，参考电压线Vref设置在第一金属层M1，且沿第一方向延伸，也即与数据线Data的延伸方向相同，稍后详细介绍。
例如，参考图3，显示基板还包括参考电压连接线Vref1，参考电压连接线Vref1分别与参考电压线Vref和第二漏极T2s电连接，以将参考电压线Vref和第二漏极T2s电连接，例如，参考电压连接线Vref1与第一源极T1s～第五源极T5s和第一漏极T1d～第五漏极T5d同层设置，也即设置在第一源漏金属层105。
例如，参考电压连接线Vref1与参考电压线Vref通过第五过孔V5电连接(参考图11，稍后详细介绍)，第五过孔V5在衬底基板101上的正投影与多个第一界定层PDL1在衬底基板101上的正投影至少部分交叠。例如，在一些实施例中，第五过孔V5在衬底基板101上的正投影也与多个像素开口PO在衬底基板101上的正投影至少部分交叠。由此，多个像素开口PO的范围延伸至第五过孔V5之外，以具有较大的开口面积，提高开口率。
例如，在一些实施例中，复位电压线Vini设置在第一金属层M1，且沿第一方向延伸，也即与数据线Data的延伸方向相同，稍后详细介绍。
例如，参考图3，显示基板还包括复位电压连接线Vini1，复位电压连接线Vini1分别与复位电压线Vini和第三漏极T3d电连接，以将复位电压线Vini和第三漏极T3d电连接，复位电压连接线Vini与第一源极T1s～第五源极T5s和第一漏极T1d～第五漏极T5d同层设置，也即设置在第一源漏金属层105。
例如，复位电压连接线Vini1与复位电压线Vini通过第六过孔V6(参考图11，稍后详细介绍)电连接，第六过孔V6在衬底基板101上的正投影与多个第二界定层PDL2在衬底基板101上的正投影至少部分交叠。例如，在一些实施例中，第六过孔V6在衬底基板101上的正投影位于多个第二界定层PDL2在衬底基板101上的正投影内，从而不被多个像素开口PO暴露。
例如，在一些实施例中，第一电源线VDD设置在第一金属层M1， 且沿第一方向延伸，也即与数据线Data的延伸方向相同，稍后详细介绍。
例如，参考图3，显示基板还包括第一电源连接线VDD1，第一电源连接线VDD1分别与第一电源线VDD和第四漏极T4d电连接，以将第一电源线VDD和第四漏极T4d电连接。例如，第一电源连接线VDD1与第一源极T1s～第五源极T5s和第一漏极T1d～第五漏极T5d同层设置，也即设置在第一源漏金属层105。
例如，第一电源连接线VDD1与第一电源线VDD通过第七过孔V7电连接，第七过孔V7在衬底基板101上的正投影与多个第一界定层PDL1在衬底基板101上的正投影至少部分交叠。例如，第七过孔V7在衬底基板101上的正投影还与多个像素开口PO在衬底基板101上的正投影至少部分交叠。由此，多个像素开口PO的范围延伸至第七过孔V7之外，以具有较大的开口面积，提高开口率。
例如，图6-图16分别示出了该显示基板每一功能层的平面示意图，下面结合图6-图16对显示基板的每一功能层进行介绍。
例如，在下面的实施例中，以显示基板的每个子像素包括11个像素驱动电路，对应11个视角(view)，也即上述N为11为例进行介绍。
例如，在像素驱动电路的排列中，M列像素驱动电路构成一个重复单元，至少一个(例如每个)重复单元的M列像素驱动电路共用一个复位电压线和一个参考电压线，M为大于1的正整数。在下面的实施例中，以M为24为例进行介绍。图6-图16示出了显示基板的一个重复单元，也即24个视角(view)，作为示例。
例如，在一些实施例中，如图6-图16所示，位于同一行的相邻的两个像素驱动电路的至少部分结构对称设置。
例如，图6示出了显示基板的半导体层102，半导体层102包括多个晶体管的有源层，例如包括第一晶体管T1的第一有源层T1a、第二晶体管T2的第二有源层T2a、第三晶体管T3的第三有源层T3a、第四晶体管T4的第四有源层T4a以及第五晶体管T5的第五有源层T5a。
例如，位于同一行的相邻的两个像素驱动电路的半导体层102的图案对称设置。
例如，图7示出了显示基板的第一栅金属层103的平面示意图。第一栅金属层103包括第一晶体管T1的第一栅极T1g、第二晶体管T2的第二栅极T2g、第三晶体管T3的第三栅极T3g、第四晶体管T4的第四栅极T4g以及第五晶体管T5的第五栅极T5g。
例如，第一栅极T1g与第一扫描信号线G1电连接，因此也可以作为第一扫描信号线G1的一部分；第二栅极T2g与第二扫描信号线G2电连接，因此也可以作为第二扫描信号线G2的一部分；第三栅极T3g与第三扫描信号线G3电连接，因此也可以作为第三扫描信号线G3的一部分；第四栅极T4g与发光控制信号线EM电连接，因此也可以作为发光控制信号线EM的一部分；第五栅极T5g例如同时可以作为第一电容电极C1。
例如，位于同一行的相邻的两个像素驱动电路的第一栅金属层103的图案大部分对称设置。
例如，图8示出了显示基板的第二栅金属层104的平面示意图。第二栅金属层104包括第一存储电容Cst的第二电容电极C2，第二电容电极C2与第一电容电极C1交叠设置，以构成第一存储电容Cst。
例如，位于同一行的相邻的两个像素驱动电路的第二栅金属层104的图案对称设置。
例如，图9示出了显示基板的层间绝缘层IDL的平面示意图。层间绝缘层IDL包括多个过孔，例如用于连接第一扫描信号线G1与第一栅极T1g的第四过孔V4、用于连接第二扫描信号线G2与第二栅极T2g的过孔VT2、用于连接第三扫描信号线G3与第三栅极T3g的过孔VT3、用于连接发光控制信号线EM与第四栅极T4g的过孔VT4等等。
例如，图10示出了显示基板的第一源漏金属层105的平面示意图。第一源漏金属层105包括参考电压连接线Vref1、复位电压连接线Vini1、第一电源连接线VDD1、数据连接线Data1、第一扫描信号线G1、第二扫描信号线G2、第三扫描信号线G3、发光控制信号线EM以及第一晶体管T1～第五晶体管T5的第一源极T1s～第五源极T5s和第一漏极T1d～第五漏极T5d。
例如，第一扫描信号线G1通过第四过孔V4与第一栅极T1g电连接，第二扫描信号线G2通过过孔VT2与第二栅极T2g电连接，第三 扫描信号线G3通过过孔VT3与第三栅极T3g电连接，发光控制信号线EM通过过孔VT4与第四栅极T4g电连接。
例如，参考电压连接线Vref1、复位电压连接线Vini1、第一电源连接线VDD1、数据连接线Data1将通过后面的第一平坦化层PLN1中的过孔与相应的信号线电连接。
例如，位于同一行的相邻的两个像素驱动电路的第一源漏金属层105的图案大部分对称设置。
例如，图11示出了显示基板的第一平坦化层PLN1的平面示意图。第一平坦化层PLN1包括多个过孔，例如用于数据线Data与数据连接线Data1连接的第三过孔V3、用于参考电压连接线Vref1与参考电压线Vref连接的第五过孔V5、用于复位电压连接线Vini1与复位电压线Vini电连接的第六过孔V6、用于第一电源连接线VDD1与第一电源线VDD电连接的第七过孔V7以及暴露像素驱动电路D的输出端的第一过孔V1。
例如，图12示出了显示基板的第一金属层M1的平面示意图。第一金属层M1也是显示基板的第二源漏金属层。第一金属层M1包括数据线Data、参考电压线Vref、第一电源线VDD、复位电压线Vini以及连接电极CL。
例如，数据线Data、参考电压线Vref、第一电源线VDD、复位电压线Vini分别沿第一方向(图中的竖直方向延伸)，且数据线Data、参考电压线Vref、第一电源线VDD、复位电压线Vini中的每两个之间设置一列连接电极CL。
例如，如图12所示，在至少部分列像素驱动电路中，第一电源线VDD和数据线Data交替排列。例如，每相邻的两列像素驱动电路或者每相邻的两个view共用一个数据线Data，每相邻的24列像素驱动电路或者每24个view共用10个第一电源线VDD。例如，每相邻的24列子像素或者每24个view共用一个参考电压线Vref，每相邻的24列子像素或者每24个view共用一个复位电压线Vini。
也即，在图6-图16示出的实施例中，每个子像素包括11个像素驱动电路，对应11个视角(View)，由于每相邻的两列像素驱动电路或者每相邻的两个view共用一个数据线Data，若忽略参考电压线Vref 和复位电压线Vini的不同，每12列像素驱动电路可以构成一个重复单元，多个重复单元在衬底基板101上依次排列；考虑到参考电压线Vref和复位电压线Vini的连接关系以及提供的电信号的不同，在严格意义上，每24列像素驱动电路可以构成一个重复单元，多个重复单元在衬底基板101上依次排列；此时，每24列像素驱动电路共用一个参考电压线Vref以及一个复位电压线Vini。
例如，位于同一行的相邻的两个像素驱动电路的第一金属层M1的图案大部分对称设置。
例如，参考图10，数据连接线Data1、参考电压连接线Vref1、复位电压连接线Vini1和第一电源连接线VDD1分别沿第二方向(图中的水平方向)延伸，以将数据线Data、参考电压线Vref、第一电源线VDD、复位电压线Vini传输的电信号分别引入至各行的每个像素驱动电路。
例如，图13示出了显示基板的第二平坦化层PLN2的平面示意图。如图13所示，第二平坦化层PLN2包括暴露连接电极CL的多个第二过孔V2，多个第二过孔V2分别暴露多个连接电极CL。
例如，图14示出了显示基板的多个第一电极的平面示意图。如图14所示，多个第一电极E1间隔设置，例如呈矩形，多个第一电极E1分别通过多个第二过孔V2与多个连接电极CL电连接。
例如，图15示出了显示基板的像素界定层PDL的平面示意图。如图15所示，像素界定层PDL包括沿第一方向延伸的多个第一界定墙PDL1以及沿第二方向延伸的多个第二界定墙PDL2，以限定出多个像素开口PO。多个像素开口PO分别暴露多个第一电极E1，以便发光材料层E2形成在多个像素开口PO中，并与多个第一电极E1接触。
例如，图16示出了显示基板的发光材料层E2的平面示意图。如图16所示，发光材料层E2包括多个发光材料行，图16中示出三行发光材料行P1/P2/P3作为示例，多个发光材料行P1/P2/P3沿第二方向(图中的水平方向)延伸，多个发光材料行的发光材料不同，且被多个第二界定墙PDL2间隔。
例如，发光材料层E2上还具有第二电极层E3以及封装层EN等结构，这些结构可以在显示基板上整面形成，也即形成为连续的片状，这里不再赘述。
例如，图17为图6-图16中各个功能层的叠层，其中的虚线框部分为图3示出的部分。
例如，在本公开的实施例中，衬底基板101可以是柔性基底，或者可以是刚性基底。刚性衬底可以包括但不限于玻璃、石英中的一种或多种，柔性衬底可以包括但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。例如，在一些示例中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力。
例如，半导体层102的材料可以采用金属氧化物等半导体材料，例如采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)或者非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料。
例如，第一栅金属层103、第二栅金属层104、第一源漏金属层105和第一金属层M1可以采用金属材料，如钛(Ti)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
例如，栅绝缘层GI1、栅绝缘层GI2和层间绝缘层IDL可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。
例如，第一平坦层PLN1和第二平坦层PLN2可以采用有机材料，如聚酰亚胺、树脂等。
例如，发光器件EL的第一电极E1可以采用氧化铟锡(ITO)、氧化铟锌(IZO)、氧化镓锌(GZO)等透明金属氧化物，或者采用透明金属氧化物与金属(例如银)的叠层，第二电极E3的材料可以采用锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料。
例如，封装层EN可以采用有机材料与无机材料的叠层，有机材料可以选用聚酰亚胺、树脂等，无机材料可以选用硅氧化物(SiOx)、硅氮化物(SiNx)或者氮氧化硅(SiON)等。本公开的实施例对上述各功能层的具体材料不作限定。
本公开至少一实施例提供一种显示装置，该显示装置包括本公开实施例提供的显示基板。例如，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
还有以下几点需要说明：
(1)本公开实施例的附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (21)

  1. 一种显示基板，包括：
    衬底基板，
    像素驱动电路层，设置在所述衬底基板上，包括多个像素驱动电路，
    第一平坦化层，设置在所述像素驱动电路层的远离所述衬底基板的一侧，包括分别暴露所述多个像素驱动电路的输出端的多个第一过孔，
    第一金属层，设置在所述第一平坦化层的远离所述衬底基板的一侧，包括沿第一方向延伸的多个数据线以及多个连接电极，所述多个连接电极分别通过所述第一过孔与所述多个像素驱动电路的输出端电连接，
    第二平坦化层，设置在所述第一金属层的远离所述衬底基板的一侧，包括暴露所述多个连接电极的多个第二过孔，
    多个第一电极，设置在所述第二平坦化层的远离所述衬底基板的一侧，分别通过所述多个第二过孔与所述多个连接电极电连接，
    像素界定层，设置在所述多个第一电极的远离所述衬底基板的一侧，包括沿所述第一方向延伸的多个第一界定墙以及沿第二方向延伸的多个第二界定墙，所述多个第一界定墙和所述多个第二界定墙限定出多个像素开口，所述第一方向不同于所述第二方向，
    其中，所述多个数据线中的至少部分在所述衬底基板上的正投影分别与所述多个第一界定墙在所述衬底基板上的正投影至少部分交叠。
  2. 根据权利要求1所述的显示基板，还包括：
    多条数据连接线，分别与所述多个数据线和所述多个像素驱动电路电连接，
    其中，所述多个数据线分别通过多个第三过孔与所述多条数据连接线电连接，所述多个第三过孔在所述衬底基板上的正投影分别与所述多个像素开口在所述衬底基板上的正投影至少部分交叠。
  3. 根据权利要求1或2所述的显示基板，其中，所述多个第一过孔在所述衬底基板上的正投影分别位于所述多个像素开口在所述衬底基板上的正投影内。
  4. 根据权利要求1或2所述的显示基板，其中，所述多个第一过孔在所述衬底基板上的正投影分别位于所述多个第二界定墙在所述衬底基板上的正投影内。
  5. 根据权利要求1-4任一所述的显示基板，其中，所述多个第二过孔在所述衬底基板上的正投影分别位于所述多个第二界定墙在所述衬底基板上的正投影内。
  6. 根据权利要求1-5任一所述的显示基板，其中，在垂直于所衬底基板的方向上，所述多个第一界定墙的高度小于所述多个第二界定墙的高度。
  7. 根据权利要求1-6任一所述的显示基板，还包括：
    发光材料层，至少设置在所述多个像素开口中，包括不同颜色的多个发光材料行，
    其中，所述多个发光材料行沿所述第二方向延伸，且被所述多个第二界定墙间隔。
  8. 根据权利要求2所述的显示基板，其中，所述多个像素驱动电路的每个包括第一薄膜晶体管和第一存储电容，所述第一薄膜晶体管包括第一栅极、第一源极和第一漏极，所述第一存储电容包括第一电容电极和第二电容电极，
    所述第一栅极与第一扫描信号线电连接，
    所述第一源极与所述多个数据线中的一个电连接，
    所述第一漏极与所述第一电容电极电连接，
    所述第二电容电极与所述多个第一电极中的一个电连接。
  9. 根据权利要求8所述的显示基板，其中，所述第一栅极和所述第一电容电极同层设置在所述衬底基板上，
    所述显示基板还包括设置在所述第一栅极和所述第一电容电极远离所述衬底基板一侧的栅绝缘层，
    所述第二电容电极设置在所述栅绝缘层的远离所述衬底基板的一侧，
    所述显示基板还包括设置在所述第二电容电极远离所述衬底基板一侧的层间绝缘层，
    所述第一源极和所述第一漏极设置在所述层间绝缘层的远离所述衬底基板的一侧，
    所述第一平坦化层设置在所述第一源极和所述第一漏极的远离 所述衬底基板的一侧。
  10. 根据权利要求9所述的显示基板，其中，所述多条数据连接线与所述第一源极和所述第一漏极同层设置；
    所述第一扫描信号线与所述第一源极和所述第一漏极同层设置。
  11. 根据权利要求10所述的显示基板，其中，所述第一扫描信号线与所述第一栅极通过第四过孔电连接，
    所述第四过孔在所述衬底基板上的正投影位于所述多个像素开口在所述衬底基板上的正投影内。
  12. 根据权利要求9-11任一所述的显示基板，其中，所述多个像素驱动电路的每个还包括第二薄膜晶体管，所述第二薄膜晶体管包括第二栅极、第二源极和第二漏极，
    所述第二栅极与第二扫描信号线电连接，
    所述第二源极与所述第一漏极和所述第一电容电极电连接，
    所述第二漏极与参考电压线电连接；
    所述参考电压线设置在所述第一金属层，且沿所述第一方向延伸。
  13. 根据权利要求12所述的显示基板，还包括：
    参考电压连接线，分别与所述参考电压线和所述第二漏极电连接，
    其中，所述参考电压连接线与所述第一源极和所述第一漏极同层设置；
    所述参考电压连接线与所述参考电压线通过第五过孔电连接，
    所述第五过孔在所述衬底基板上的正投影与所述多个第一界定层在所述衬底基板上的正投影至少部分交叠。
  14. 根据权利要求12或13所述的显示基板，其中，所述多个像素驱动电路的每个还包括第三薄膜晶体管，所述第三薄膜晶体管包括第三栅极、第三源极和第三漏极，
    所述第三栅极与第三扫描信号线电连接，
    所述第三源极与所述第二电容电极和所述多个第一电极中的一个电连接，
    所述第三漏极与复位电压线电连接；
    所述复位电压线设置在所述第一金属层，且沿所述第一方向延伸。
  15. 根据权利要求14所述的显示基板，还包括：
    复位电压连接线，分别与所述复位电压线和所述第三漏极电连接，
    其中，所述复位电压连接线与所述第一源极和所述第一漏极同层设置；
    所述复位电压连接线与所述复位电压线通过第六过孔电连接，
    所述第六过孔在所述衬底基板上的正投影与所述多个第二界定层在所述衬底基板上的正投影至少部分交叠。
  16. 根据权利要求14或15所述的显示基板，其中，所述多个像素驱动电路的每个还包括第四薄膜晶体管和第五薄膜晶体管，所述第四薄膜晶体管包括第四栅极、第四源极和第四漏极，所述第五薄膜晶体管包括第五栅极、第五源极和第五漏极，
    所述第四栅极与发光控制线电连接，
    所述第四源极与所述第五漏极电连接，
    所述第四漏极与第一电源线电连接，
    所述第五栅极与所述第一漏极和所述第一电容电极电连接，
    所述第五源极与所述第二电容电极和所述多个第一电极中的一个电连接；
    所述第一电源线设置在所述第一金属层，且沿所述第一方向延伸。
  17. 根据权利要求16所述的显示基板，还包括：
    第一电源连接线，分别与所述第一电源线和所述第四漏极电连接，
    其中，所述第一电源连接线与所述第一源极和所述第一漏极同层设置；
    所述第一电源连接线与所述第一电源线通过第七过孔电连接，
    所述第七过孔在所述衬底基板上的正投影与所述多个第一界定层在所述衬底基板上的正投影至少部分交叠。
  18. 根据权利要求1-17任一所述的显示基板，其中，位于同一行的相邻的两个像素驱动电路的至少部分结构对称设置。
  19. 根据权利要求1-18任一所述的显示基板，还包括多个子像素，
    其中，至少一个所述子像素包括位于同一行的N个像素驱动电路，所述N个像素驱动电路对应N个视角，N为大于1的正整数。
  20. 根据权利要求19所述的显示基板，其中，M列像素驱动电路构成一个重复单元，至少一个所述重复单元的M列像素驱动电路共用一个复位电压线和一个参考电压线，M为大于1的正整数。
  21. 一种显示装置，包括权利要求1-20任一所述的显示基板。
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