WO2022094839A1 - 显示基板及其检测方法、制备方法、显示装置 - Google Patents

显示基板及其检测方法、制备方法、显示装置 Download PDF

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Publication number
WO2022094839A1
WO2022094839A1 PCT/CN2020/126692 CN2020126692W WO2022094839A1 WO 2022094839 A1 WO2022094839 A1 WO 2022094839A1 CN 2020126692 W CN2020126692 W CN 2020126692W WO 2022094839 A1 WO2022094839 A1 WO 2022094839A1
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Prior art keywords
electrode
transistor
detection
control
sub
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PCT/CN2020/126692
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English (en)
French (fr)
Inventor
徐飞
李京勇
洪俊
王颜彬
田文红
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to CN202080002646.7A priority Critical patent/CN114730543B/zh
Priority to US17/428,643 priority patent/US11817023B2/en
Priority to PCT/CN2020/126692 priority patent/WO2022094839A1/zh
Publication of WO2022094839A1 publication Critical patent/WO2022094839A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0294—Details of sampling or holding circuits arranged for use in a driver for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • This article relates to, but is not limited to, the field of display technology, especially a display substrate and its detection method, preparation method, and display device.
  • Micro-OLED Micro Organic Light-Emitting Diode
  • silicon-based OLED is a microdisplay developed in recent years, and silicon-based OLED is one of them.
  • Silicon-based OLEDs can not only realize active addressing of pixels, but also realize the preparation of various functional circuits including timing control (TCON, Timer Control) circuits, overcurrent protection (OCP, Over Current Protection) circuits on a silicon-based substrate. , which is conducive to reducing the volume of the system and achieving light weight.
  • Silicon-based OLEDs are fabricated using mature complementary metal-oxide-semiconductor (CMOS, Complementary Metal Oxide Semiconductor) integrated circuit processes. They have the advantages of small size, high resolution (PPI), and high refresh rate, and are widely used in virtual reality (VR, Virtual Reality) or Augmented Reality (AR, Augmented Reality) near-eye display field.
  • CMOS complementary metal-oxide-semiconductor
  • Embodiments of the present disclosure provide a display substrate, a detection method, a preparation method, and a display device thereof.
  • an embodiment of the present disclosure provides a display substrate, including: a base substrate, the base substrate including a display area and a peripheral area located on at least one side of the display area.
  • the display area is provided with a plurality of sub-pixels, and at least one sub-pixel of the plurality of sub-pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element.
  • the peripheral area includes a detection area, the detection area is provided with at least one detection electrode, and the at least one detection electrode is electrically connected to the first electrode of the light-emitting element and the pixel circuit through a detection lead wire, so as to be in the detection stage , and detect the electrical properties of the light-emitting element through the detection electrode.
  • the at least one detection electrode is electrically connected to a detection circuit provided on the peripheral region, or the at least one detection electrode is electrically connected to a detection circuit provided on an external circuit board.
  • the detection circuit includes: a first control unit, a second control unit and a storage unit.
  • the first control unit is respectively connected to the detection electrode, the first control terminal and the first node, and is configured to supply power to the detection electrode through the first node under the control of the first control terminal.
  • the second control unit is respectively connected to the second control terminal, the first signal terminal and the first node, and is configured to charge the first node through the first signal terminal under the control of the second control terminal , or collect the voltage of the first node through the first signal terminal.
  • the storage unit is connected to the first node and the first power supply terminal respectively, and is configured to store the voltage of the first node.
  • the first control unit includes: a fourth transistor, a control electrode of the fourth transistor is connected to the first control terminal, and a first electrode of the fourth transistor is connected to the detection electrode , the second pole of the fourth transistor is connected to the first node.
  • the second control unit includes: a fifth transistor, the control electrode of the fifth transistor is connected to the second control terminal, the first electrode of the fifth transistor is connected to the first signal terminal, and the first electrode of the fifth transistor is connected to the first signal terminal.
  • a diode is connected to the first node.
  • the storage unit includes: a second storage capacitor, a first pole of the second storage capacitor is connected to the first node, and a second pole of the second storage capacitor is connected to a first power supply terminal.
  • the spacing between adjacent detection electrodes in the detection region ranges from 40 microns to 85 microns.
  • the peripheral area further includes: a binding area on one side of the display area, and the detection area is located between the display area and the binding area.
  • the distance between the detection area and the display area may range from 350 microns to 530 microns, and the distance between the detection area and the binding area may range from 350 microns to 530 microns. 530 microns.
  • the line width of the detection lead line ranges from 3.5 microns to 35 microns.
  • the display area is rectangular, the display area is divided into nine rectangular sub-areas in the form of 3*3, the detection area includes a plurality of detection electrodes, the plurality of detection electrodes are connected with the The center positions of the nine rectangular sub-regions are connected to the first poles of the light-emitting elements of the sub-pixels at the vertex positions.
  • the display substrate at least includes: an N-1 th conductive layer and an N th conductive layer disposed in sequence away from the base substrate, N is a positive integer.
  • the N-1th conductive layer at least includes: a detection lead wire extending from the display area to the detection area, and the detection lead wire is electrically connected to a pixel circuit corresponding to the light-emitting element.
  • the Nth conductive layer at least includes: the first pole of the light-emitting element located in the display area, and the detection electrode located in the detection area; the first end of the detection lead wire and the first pole of the light-emitting element connected, and the second end of the detection lead wire is connected to the detection electrode.
  • the pixel circuit includes a driving subcircuit, a voltage transmission subcircuit, and a data writing subcircuit.
  • the driving sub-circuit includes: a control terminal, a first terminal and a second terminal.
  • the voltage transmission sub-circuit is configured to apply the first power supply voltage provided by the first power supply line to the first terminal of the driving sub-circuit in response to the lighting control signal.
  • the data writing subcircuit is configured to write a data signal to the control terminal of the driving subcircuit and store the written data signal in response to the first scan signal and the second scan signal.
  • the driving sub-circuit is configured to drive the light-emitting element to emit light under the control of the control terminal and the first terminal of the driving sub-circuit.
  • the driving sub-circuit includes: a driving transistor
  • the data writing sub-circuit includes: a first transistor, a second transistor and a first storage capacitor
  • the voltage transmission sub-circuit includes: a third transistor.
  • the control electrode of the drive transistor is connected to the control end of the drive sub-circuit
  • the first electrode of the drive transistor is connected to the first end of the drive sub-circuit
  • the second electrode of the drive transistor is connected to the drive sub-circuit A second end of the subcircuit is connected.
  • the control electrode of the first transistor is connected to the first scan signal line
  • the first electrode of the first transistor is connected to the data line
  • the second electrode of the first transistor is connected to the control electrode of the driving transistor.
  • the control electrode of the second transistor is connected to the second scan signal line, the first electrode of the second transistor is connected to the data line, and the second electrode of the second transistor is connected to the control electrode of the driving transistor .
  • the control electrode of the third transistor is connected to the light-emitting control line, the first electrode of the third transistor is connected to the first power supply line, and the second electrode of the third transistor is connected to the first electrode of the driving transistor.
  • the first electrode of the first storage capacitor is connected to the control electrode of the driving transistor, and the second electrode of the first storage capacitor is connected to the second power line.
  • the first electrode of the light-emitting element is connected to the second electrode of the driving transistor, and the second electrode of the light-emitting element is connected to the third power supply line.
  • the pixel circuit includes a driving subcircuit, a voltage transmission subcircuit, and a data writing subcircuit.
  • the driving sub-circuit includes: a control terminal, a first terminal and a second terminal.
  • the voltage transfer subcircuit is configured to apply a reset voltage and a first power supply voltage to the first terminals of the drive subcircuit, respectively, in response to the transfer control signal.
  • the data writing subcircuit is configured to write a data signal to the control terminal of the driving subcircuit and store the written data signal in response to the first scan signal and the second scan signal.
  • the driving sub-circuit is configured to drive the light-emitting element to emit light under the control of the control terminal and the first terminal of the driving sub-circuit.
  • the peripheral region is provided with a voltage control circuit, the voltage control circuit is connected to the pixel circuit; the voltage control circuit is configured to provide a reset voltage to a voltage transfer sub-circuit of the pixel circuit in response to a reset control signal, and A first supply voltage is provided to the voltage transfer subcircuit in response to the lighting control signal.
  • the driving subcircuit includes a driving transistor
  • the data writing subcircuit includes a first transistor, a second transistor and a first storage capacitor
  • the voltage transmission subcircuit includes a third transistor
  • the voltage control circuit includes: a sixth transistor and a seventh transistor.
  • the control electrode of the drive transistor is connected to the control end of the drive sub-circuit, the first electrode of the drive transistor is connected to the first end of the drive sub-circuit, and the second electrode of the drive transistor is connected to the drive sub-circuit A second end of the subcircuit is connected.
  • the control electrode of the first transistor is connected to the first scan signal line, the first electrode of the first transistor is connected to the data line, and the second electrode of the first transistor is connected to the control electrode of the driving transistor.
  • the control electrode of the second transistor is connected to the second scan signal line, the first electrode of the second transistor is connected to the data line, and the second electrode of the second transistor is connected to the control electrode of the driving transistor .
  • the control electrode of the third transistor is connected to the transmission control line, the first electrode of the third transistor is connected to the second electrode of the sixth transistor and the first electrode of the seventh transistor, and the third transistor
  • the second pole of the drive transistor is connected to the first pole of the drive transistor.
  • the first electrode of the first storage capacitor is connected to the control electrode of the driving transistor, and the second electrode of the first storage capacitor is connected to the second power line.
  • the control electrode of the sixth transistor is connected to the reset control line, the first electrode of the sixth transistor is connected to the reset voltage line, the control electrode of the seventh transistor is connected to the light-emitting control line, and the first electrode of the seventh transistor is connected to the light-emitting control line.
  • the second pole is connected to the first power line.
  • the first electrode of the light-emitting element is connected to the second electrode of the driving transistor, and the second electrode of the light-emitting element is connected to the third power supply line.
  • the first transistor is a first semiconductor type MOS transistor
  • the second transistor, the third transistor and the driving transistor are all second semiconductor type MOS transistors
  • the first The doping types of the semiconductor type and the second semiconductor type are opposite.
  • the display substrate in a direction perpendicular to the base substrate, includes: an active layer, a first conductive layer, a second conductive layer, an active layer, a first conductive layer, a second conductive layer, The third conductive layer, the fourth conductive layer, the fifth conductive layer, the sixth conductive layer, the seventh conductive layer, and the eighth conductive layer.
  • the active layer includes at least: active regions of a plurality of transistors of the pixel circuit.
  • the first conductive layer includes at least: control electrodes of a plurality of transistors of the pixel circuit.
  • the second conductive layer at least includes: first and second electrodes of a plurality of transistors of the pixel circuit, the first power supply line, the second power supply line, the light-emitting control line and the data line .
  • the third conductive layer at least includes: a first transfer electrode used to connect the second electrode of the first transistor, the second electrode of the second transistor and the control electrode of the driving transistor, and used to connect the control electrode of the first transistor and the control electrode of the driving transistor.
  • the second transfer electrode of the first scan signal line is used for connecting the control electrode of the second transistor and the third transfer electrode of the second scan signal line.
  • the fourth conductive layer at least includes: the first scan signal line, the second scan signal line, and a first pole and a second pole of the first sub-capacitor.
  • the fifth conductive layer at least includes: the first pole of the second sub-capacitor.
  • the sixth conductive layer at least includes: the second pole of the second sub-capacitor; the first sub-capacitor and the second sub-capacitor are connected in parallel to form the first storage capacitor.
  • the seventh conductive layer at least includes: a fourth transfer electrode for connecting the first pole of the first sub-capacitor of the first storage capacitor and the second pole of the second sub-capacitor; A detection lead line extending to the detection area; the first end of the detection lead line is connected with the second pole of the driving transistor.
  • the eighth conductive layer at least includes: the first pole of the light-emitting element located in the display area, and the detection electrode located in the detection area; the first pole of the light-emitting element and the first end of the detection lead wire connected, the detection electrode is connected with the second end of the detection lead wire.
  • implementations of the present disclosure provide a display device including the display substrate as described above.
  • an embodiment of the present disclosure provides a method for fabricating a display substrate, including: providing a base substrate, the base substrate including a display area and a peripheral area on at least one side of the display area;
  • the base substrate forms a plurality of sub-pixels, at least one detection electrode and detection lead lines.
  • the plurality of sub-pixels are disposed in the display area, and at least one sub-pixel of the plurality of sub-pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element.
  • the peripheral area includes a detection area, the at least one detection electrode is arranged in the detection area, and the at least one detection electrode is electrically connected to the first electrode of the light-emitting element and the pixel circuit through a detection lead wire, so as to In the detection stage, the electrical properties of the light-emitting element are detected through the detection electrodes.
  • an embodiment of the present disclosure provides a method for detecting a display substrate.
  • the display substrate includes: a base substrate including a display area and a peripheral area located on at least one side of the display area.
  • the display area is provided with a plurality of sub-pixels, and at least one sub-pixel of the plurality of sub-pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element.
  • the detection area is provided with at least one detection electrode, and the at least one detection electrode is electrically connected to the first electrode of the light-emitting element and the pixel circuit through a detection lead wire.
  • the peripheral area includes a detection area, the at least one detection electrode is electrically connected to a detection circuit, and the detection circuit includes: a first control unit, a second control unit, and a storage unit.
  • the first control unit is respectively connected with the detection electrode, the first control terminal and the first node;
  • the second control unit is respectively connected with the second control terminal, the first signal terminal and the first node;
  • the The storage unit is connected to the first node and the first power terminal respectively.
  • the detection method includes: in the first sub-stage of the detection stage, under the control of the first control terminal of the detection circuit, disconnecting the connection between the detection electrode and the first node, and under the control of the second control terminal, through the first signal
  • the terminal charges the first node; in the second sub-phase of the detection stage, under the control of the second control terminal, the connection between the first signal terminal and the first node is disconnected, and under the control of the first control terminal, the The detection electrode is powered; in the third sub-stage of the detection stage, under the control of the first control terminal of the detection circuit, the connection between the detection electrode and the first node is disconnected, and under the control of the second control terminal, the first signal terminal is collected through the first signal terminal.
  • the voltage of a node, and the electrical performance of the light-emitting element is determined according to the voltage collected from the first signal terminal.
  • the determining the electrical performance of the light-emitting element according to the voltage collected from the first signal terminal includes at least one of the following:
  • the average current of the light-emitting element is calculated according to the voltage sampled from the first signal terminal in the third sub-phase; according to the collected voltage and the calculated average current, calculate the equivalent resistance of the light-emitting element; according to the equivalent resistance of the light-emitting element, determine whether the light-emitting element is in a weak short-circuit and weak-off state;
  • the critical turn-on voltage of the light-emitting element is determined according to the voltage sampled from the first signal terminal in the third sub-phase.
  • FIG. 1 is a schematic plan view of a display substrate according to at least one embodiment of the disclosure
  • FIG. 2 is a schematic diagram of the positions of sub-pixels in a display area connected to detection electrodes of a display substrate according to at least one embodiment of the disclosure
  • FIG. 3 is a schematic diagram of a pixel circuit and a detection circuit of a display substrate according to at least one embodiment of the disclosure
  • FIG. 4 is an equivalent circuit diagram of a pixel circuit of a display substrate according to at least one embodiment of the disclosure.
  • FIG. 5 is an equivalent circuit diagram of a detection circuit of a display substrate according to at least one embodiment of the disclosure.
  • FIG. 6 is a working timing diagram of the pixel circuit provided in FIG. 5;
  • Fig. 7 is the working sequence diagram of the detection circuit provided by Fig. 5;
  • FIG. 8 is a schematic diagram of the volt-ampere characteristics of a light-emitting element
  • FIG. 9 is a schematic diagram of a pixel circuit and a detection circuit of a display substrate according to at least one embodiment of the disclosure.
  • FIG. 10 is an equivalent circuit diagram of a pixel circuit and a detection circuit of a display substrate according to at least one embodiment of the disclosure
  • FIG. 11 is a schematic diagram of a display substrate after forming an active layer and a first conductive layer in at least one embodiment of the disclosure
  • Figure 12 is a schematic cross-sectional view in the direction of R-R in Figure 11;
  • FIG. 13 is a schematic diagram of a display substrate after forming a second conductive layer according to at least one embodiment of the disclosure
  • Figure 14 is a schematic cross-sectional view in the direction R-R in Figure 13;
  • FIG. 15 is a schematic diagram of a display substrate after forming a third conductive layer in at least one embodiment of the disclosure.
  • FIG. 16 is a schematic cross-sectional view in the direction of Q-Q in FIG. 15;
  • FIG. 17 is a schematic diagram of a display substrate after forming a fourth conductive layer according to at least one embodiment of the present disclosure.
  • FIG. 18 is a schematic cross-sectional view along the O-O direction in FIG. 17;
  • FIG. 19 is a schematic diagram of a display substrate after forming a fifth conductive layer according to at least one embodiment of the disclosure.
  • FIG. 20 is a schematic diagram of a display substrate after forming a sixth conductive layer in at least one embodiment of the disclosure
  • 21 is a schematic diagram of a display substrate after forming a seventh conductive layer according to at least one embodiment of the disclosure.
  • Figure 22 is a schematic cross-sectional view in the P-P direction in Figure 21;
  • FIG. 23 is a schematic plan view of a display substrate after forming an eighth insulating layer according to at least one embodiment of the disclosure.
  • FIG. 24 is a schematic plan view of a display substrate after forming an eighth conductive layer according to at least one embodiment of the disclosure.
  • FIG. 25 is a schematic diagram of a display device according to at least one embodiment of the disclosure.
  • ordinal numbers such as “first”, “second”, and “third” are set to avoid confusion of constituent elements, rather than to limit the quantity.
  • "Plurality” in this disclosure means a quantity of two or more.
  • the terms “installed”, “connected” and “connected” should be construed broadly unless otherwise expressly specified and limited. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed should be construed broadly unless otherwise expressly specified and limited. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in the present disclosure, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrically connected includes the case where constituent elements are connected together by elements having some electrical function.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having some electrical function” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having one or more functions, and the like.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus can include a state in which the angle is -5° or more and 5° or less.
  • perpendicular refers to a state in which the angle formed by two straight lines is 80° or more and 100° or less, and therefore can include a state in which an angle of 85° or more and 95° or less is included.
  • film and “layer” are interchangeable.
  • conductive layer may be replaced by “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • thickness refers to the height of the surface away from the substrate from the surface near the substrate in a direction perpendicular to the plane of the substrate.
  • Micro OLED (Micro OLED) displays typically have a size of less than 3 inches and involve a combination of organic light emitting diode (OLED) technology and CMOS technology, where OLED arrays are fabricated on a silicon-based substrate including CMOS circuits.
  • OLED organic light emitting diode
  • CMOS complementary metal-oxide-semiconductor
  • the current design of micro OLED displays is difficult to monitor the electrical characteristics of the OLED (for example, the critical on-voltage of the OLED, the magnitude of the leakage current, the existence of weak shorts and weak breaks, etc.), and it is difficult to find the poor electrical characteristics of the OLED devices in the factory test , and these defects will gradually increase with the increase of use time and the impact of the environment, resulting in progressive defects, and even some defects will seriously affect the customer experience.
  • At least one embodiment of the present disclosure provides a display substrate, including: a base substrate, the base substrate including a display area and a peripheral area located on at least one side of the display area.
  • the display area is provided with a plurality of sub-pixels, and at least one sub-pixel in the plurality of sub-pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element.
  • the peripheral area includes a detection area, and the detection area is provided with at least one detection electrode, and the at least one detection electrode is electrically connected with the first electrode of the light-emitting element and the pixel circuit through the detection lead wire, so that in the detection stage, the detection electrode detects the light-emitting element through the detection electrode. electrical properties.
  • the display substrate provided in this embodiment can detect the electrical performance of the light-emitting element in the display area by connecting the first electrode of the light-emitting element located in the display area and the pixel circuit and the detection electrode located in the peripheral area through the detection lead, so as to provide Provides support for poor resolution of display substrates.
  • the at least one detection electrode is electrically connected to a detection circuit provided in a peripheral area, or the at least one detection electrode is electrically connected to a detection circuit provided on an external circuit board.
  • the detection circuit is provided in the non-display area other than the display area.
  • the detection electrode disposed in the detection region of the peripheral region is directly electrically connected to the first electrode of the light emitting element and the pixel circuit. That is, the detection electrodes and the pixel circuits are directly electrically connected through the detection lead wires, and no other transistors are connected therebetween.
  • the detection electrode arranged in the detection area is equivalent to a signal terminal of the pixel circuit and the light-emitting element, so that the electrical performance of the light-emitting element can be detected by connecting the signal terminal through the detection circuit arranged on the external circuit board.
  • the detection circuit includes: a first control unit, a second control unit, and a storage unit.
  • the first control unit is respectively connected to the detection electrode, the first control terminal and the first node, and is configured to supply power to the detection electrode through the first node under the control of the first control terminal.
  • the second control unit is connected to the second control terminal, the first signal terminal and the first node respectively, and is configured to charge the first node through the first signal terminal under the control of the second control terminal, or to charge the first node through the first signal terminal Collect the voltage of the first node.
  • the storage unit is connected to the first node and the first power terminal respectively, and is configured to store the voltage of the first node.
  • the first control unit includes: a fourth transistor.
  • the control electrode of the fourth transistor is connected to the first control terminal, the first electrode of the fourth transistor is connected to the detection electrode, and the second electrode of the fourth transistor is connected to the first node.
  • the second control unit includes: a fifth transistor.
  • the control electrode of the fifth transistor is connected to the second control end, the first electrode of the fifth transistor is connected to the first signal end, and the second electrode of the fifth transistor is connected to the first node.
  • the storage unit includes: a second storage capacitor. The first pole of the second storage capacitor is connected to the first node, and the second pole of the second storage capacitor is connected to the first power supply terminal.
  • this embodiment does not limit this.
  • the spacing between adjacent detection electrodes within the detection region may range from 40 microns to 85 microns.
  • the spacing between adjacent detection electrodes in the detection area may be 50 microns, or alternatively, may be 70 microns. However, this embodiment does not limit this.
  • the peripheral area further includes: a binding area on one side of the display area.
  • the detection area is located between the display area and the binding area.
  • the distance between the detection area and the display area is in the range of 350 microns to 530 microns, and the distance between the detection area and the binding area is in the range of 350 microns to 530 microns.
  • the detection area is located between the display area and the binding area, and the distance between the detection area and the display area is 440 microns, and the distance between the detection area and the binding area is 440 microns.
  • this embodiment does not limit this.
  • the distance between the detection area and the display area and the distance between the detection area and the binding area may be different.
  • the line width of the detection pinout ranges from 3.5 microns to 35 microns.
  • the line width of the detection pinout may be 35 microns.
  • this embodiment does not limit this.
  • the display area is rectangular, and the display area is divided into nine rectangular sub-areas in the form of 3*3.
  • the detection area includes a plurality of detection electrodes.
  • the plurality of detection electrodes are connected to the first electrodes of the light-emitting elements of the sub-pixels at the center positions and the vertex positions of the nine rectangular sub-regions. For example, if the number of detection electrodes in the detection area is 25, and the nine rectangular sub-areas include 9 center positions and 16 vertex positions in total, then the 25 detection electrodes correspond to the first of the light-emitting elements of the sub-pixels corresponding to the above 25 positions.
  • the poles are connected in one-to-one correspondence.
  • the present embodiment does not limit the number and position of the sub-pixels connected to the detection electrodes.
  • the display substrate in a direction perpendicular to the base substrate, the display substrate at least includes: an N-1 th conductive layer and an N th conductive layer disposed in sequence along the direction away from the base substrate, where N is a positive integer.
  • the N-1th conductive layer at least includes: a detection lead wire extending from the display area to the detection area, and the detection lead wire is electrically connected to the pixel circuit corresponding to the light-emitting element.
  • the Nth conductive layer at least includes: the first electrode of the light-emitting element located in the display area, and the detection electrode located in the detection area. The first end of the detection lead wire is connected to the first electrode of the light-emitting element, and the second end of the detection lead wire is connected to the detection electrode.
  • the detection electrode and the first electrode of the light-emitting element are arranged in the same layer, and are connected through detection lead wires arranged in different layers.
  • the pixel circuit includes a driving subcircuit, a voltage transmission subcircuit, and a data writing subcircuit.
  • the driving sub-circuit includes: a control terminal, a first terminal and a second terminal.
  • the voltage transmission sub-circuit is configured to apply the first power supply voltage provided by the first power supply line to the first terminal of the driving sub-circuit in response to the lighting control signal.
  • the data writing subcircuit is configured to write the data signal to the control terminal of the driving subcircuit and store the written data signal in response to the first scan signal and the second scan signal.
  • the driving sub-circuit is configured to drive the light-emitting element to emit light under the control of the control terminal and the first terminal of the driving sub-circuit.
  • the driving subcircuit includes: a driving transistor.
  • the data writing subcircuit includes: a first transistor, a second transistor and a first storage capacitor.
  • the voltage transfer subcircuit includes: a third transistor.
  • the control electrode of the drive transistor is connected to the control end of the drive subcircuit, the first electrode of the drive transistor is connected to the first end of the drive subcircuit, and the second electrode of the drive transistor is connected to the second end of the drive subcircuit.
  • the control electrode of the first transistor is connected to the first scan signal line, the first electrode of the first transistor is connected to the data line, and the second electrode of the first transistor is connected to the control electrode of the driving transistor.
  • the control electrode of the second transistor is connected to the second scan signal line, the first electrode of the second transistor is connected to the data line, and the second electrode of the second transistor is connected to the control electrode of the driving transistor.
  • the control electrode of the third transistor is connected to the light-emitting control line, the first electrode of the third transistor is connected to the first power supply line, and the second electrode of the third transistor is connected to the first electrode of the driving transistor.
  • the first electrode of the first storage capacitor is connected to the control electrode of the driving transistor, and the second electrode of the first storage capacitor is connected to the second power line.
  • the first electrode of the light-emitting element is connected to the second electrode of the driving transistor, and the second electrode of the light-emitting element is connected to the third power supply line.
  • the first transistor is a first semiconductor type metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor, MOS) transistor
  • the second transistor, the third transistor and the driving transistor are all second semiconductor type MOS transistors
  • the doping types of the first semiconductor type and the second semiconductor type are opposite.
  • the first transistor is a P-type transistor
  • the second transistor, the third transistor and the driving transistor are all N-type transistors.
  • this embodiment does not limit this.
  • the display substrate in a direction perpendicular to the base substrate, includes: an active layer, a first conductive layer, a second conductive layer, a third conductive layer, a first conductive layer, a Four conductive layers, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, and an eighth conductive layer.
  • the active layer includes at least: active regions of a plurality of transistors of the pixel circuit.
  • the first conductive layer at least includes: control electrodes of a plurality of transistors of the pixel circuit.
  • the second conductive layer at least includes: first and second electrodes of a plurality of transistors of the pixel circuit, a first power supply line, a second power supply line, a light-emitting control line and a data line.
  • the third conductive layer at least includes: a first transfer electrode for connecting the second electrode of the first transistor, the second electrode of the second transistor and the control electrode of the driving transistor, and the control electrode of the first transistor and the first transfer electrode
  • the second transfer electrode of the scan signal line is used for connecting the control electrode of the second transistor and the third transfer electrode of the second scan signal line.
  • the fourth conductive layer at least includes: a first scan signal line, a second scan signal line, a first electrode and a second electrode that form a first parallel capacitor of the first storage capacitor.
  • the fifth conductive layer includes at least: a first pole forming a second parallel capacitor of the first storage capacitor.
  • the sixth conductive layer includes at least: a second pole forming a second parallel capacitor of the first storage capacitor.
  • the seventh conductive layer at least includes: a fourth transfer electrode for connecting the first pole of the first parallel capacitor of the first storage capacitor and the second pole of the second parallel capacitor, and a detection lead extending from the display area to the detection area .
  • the first end of the detection lead wire is connected to the second electrode of the driving transistor.
  • the eighth conductive layer at least includes: the first electrode of the light-emitting element located in the display area, and the detection electrode located in the detection area.
  • the first pole of the light-emitting element is connected to the first end of the detection lead wire, and the detection electrode is connected to the second end of the detection lead wire.
  • the pixel circuit includes a driving subcircuit, a voltage transfer subcircuit, and a data writing subcircuit.
  • the driving sub-circuit includes: a control terminal, a first terminal and a second terminal.
  • the voltage transfer subcircuit is configured to apply the reset voltage and the first power supply voltage to the first terminals of the drive subcircuit, respectively, in response to the transfer control signal.
  • the data writing subcircuit is configured to write the data signal to the control terminal of the driving subcircuit and store the written data signal in response to the first scan signal and the second scan signal.
  • the driving sub-circuit is configured to drive the light-emitting element to emit light under the control of the control terminal and the first terminal of the driving sub-circuit.
  • the peripheral area is provided with a voltage control circuit, and the voltage control circuit is connected with the pixel circuit.
  • the voltage control circuit is configured to provide a reset voltage to the voltage transfer subcircuit of the pixel circuit in response to the reset control signal, and to provide a first supply voltage to the voltage transfer subcircuit in response to the light emission control signal.
  • the driving subcircuit includes a driving transistor
  • the data writing subcircuit includes a first transistor, a second transistor and a first storage capacitor
  • the voltage transmission subcircuit includes a third transistor.
  • the voltage control circuit includes: a sixth transistor and a seventh transistor.
  • the control electrode of the drive transistor is connected to the control end of the drive subcircuit, the first electrode of the drive transistor is connected to the first end of the drive subcircuit, and the second electrode of the drive transistor is connected to the second end of the drive subcircuit.
  • the control electrode of the first transistor is connected to the first scan signal line, the first electrode of the first transistor is connected to the data line, and the second electrode of the first transistor is connected to the control electrode of the driving transistor.
  • the control electrode of the second transistor is connected to the second scan signal line, the first electrode of the second transistor is connected to the data line, and the second electrode of the second transistor is connected to the control electrode of the driving transistor.
  • the control electrode of the third transistor is connected to the transmission control line, the first electrode of the third transistor is connected to the second electrode of the sixth transistor and the first electrode of the seventh transistor, and the second electrode of the third transistor is connected to the first electrode of the driving transistor pole connection.
  • the first electrode of the first storage capacitor is connected to the control electrode of the driving transistor, and the second electrode of the first storage capacitor is connected to the second power line.
  • the control electrode of the sixth transistor is connected to the reset control line, and the first electrode of the sixth transistor is connected to the reset voltage line.
  • the control electrode of the seventh transistor is connected to the light-emitting control line, and the second electrode of the seventh transistor is connected to the first power line.
  • the first electrode of the light-emitting element is connected to the second electrode of the driving transistor, and the second electrode of the light-emitting element is connected to the third power supply line.
  • the display substrate may be a silicon-based OLED display substrate, which may be applied in a virtual reality device or an enhanced display device, or may be other types of display substrates.
  • the embodiments of the present disclosure are not limited thereto.
  • FIG. 1 is a schematic plan view of a display substrate according to at least one embodiment of the disclosure.
  • the display substrate includes: a base substrate 10 .
  • the base substrate 10 may be a silicon-based base substrate, which may be a bulk silicon substrate or a silicon-on-insulator (SOI, Silicon-On-Insulator) substrate.
  • the base substrate 10 includes a display area 100 and a peripheral area 101 located around the display area 100 .
  • the peripheral area 101 includes a binding area 103 located on one side of the display area 100 , and a detection area 102 located between the display area 100 and the binding area 103 .
  • the display area 100 is provided with a plurality of sub-pixels, a plurality of scan lines and a plurality of data lines distributed in an array.
  • At least one subpixel includes a light emitting element and a pixel circuit for driving the light emitting element.
  • a plurality of scan lines and a plurality of data lines cross each other to define a plurality of pixel regions distributed in an array in the display area 100 , and a pixel circuit of a sub-pixel is arranged in at least one pixel region.
  • the pixel circuit may be fabricated on the base substrate by a silicon semiconductor process (eg, CMOS process), and the light-emitting element may be fabricated on the base substrate having the pixel circuit.
  • the pixel circuit is, for example, a conventional pixel circuit, such as 2T1C (ie, two transistors and one capacitor) pixel circuit, 4T2C, 5T1C, 7T1C and other nTmC (n, m are positive integers) pixel circuits.
  • the pixel circuit may further include a compensation subcircuit, the compensation subcircuit may include an internal compensation subcircuit or an external compensation subcircuit, and the compensation subcircuit may include a transistor, a capacitor, and the like.
  • the pixel circuit may further include: a reset sub-circuit, a light-emitting control sub-circuit, and the like.
  • this embodiment does not limit this.
  • the peripheral region 101 is provided with gate driving circuits and data driving circuits.
  • the gate driving circuit is connected with the pixel circuit through the scan line to provide at least one scan signal
  • the data drive circuit is connected with the pixel circuit through the data line to provide the data signal.
  • the peripheral region 101 may further be provided with a control circuit configured to control the data driving circuit to apply the data signal, and to control the gate driving circuit to apply the scan signal.
  • a control circuit is a timing control circuit, which can take a variety of forms, including, for example, a memory and a processor, the memory including executable code that the processor executes to control the data drive circuit to apply data signals and control gates
  • the pole drive circuit applies the scan signal.
  • this embodiment does not limit this.
  • gate driving circuits and data driving circuits may be formed in a display area corresponding to the display substrate, and not necessarily in peripheral areas around the periphery.
  • the detection region 102 is provided with a plurality of detection electrodes. At least one detection electrode may be connected to the light-emitting element of the corresponding sub-pixel in the display area 100 through a detection lead wire. A plurality of detection electrodes may be arranged regularly, eg, in an array. A plurality of detection electrodes can be configured to be bonded and connected to a flexible printed circuit board (FPC, Flexible Printed Circuit). However, this embodiment does not limit this.
  • FPC Flexible Printed Circuit
  • the bonding area 103 is provided with pad components.
  • the pad assembly includes a plurality of strip-shaped bonding electrodes arranged at intervals, and can be configured to be bonded and connected to the flexible circuit board.
  • this embodiment does not limit this.
  • FIG. 2 is a schematic diagram of the positions of sub-pixels in a display region connected to detection electrodes of a display substrate according to at least one embodiment of the disclosure.
  • the rectangular display area may be divided into nine rectangular sub-areas in the form of 3*3, and the sub-pixels located at the center position and vertex position of each rectangular sub-area are selected as the detection position of the electrical performance .
  • a total of 25 sub-pixels PA can be selected (including sub-pixels corresponding to 9 central positions of the nine rectangular sub-regions and 16 vertex positions corresponding to the sub-pixels) sub-pixels) as the detection position.
  • the detection area may include at least 25 detection electrodes, and the selected 25 sub-pixels PA may be connected to the detection electrodes in the detection area in one-to-one correspondence, so as to detect the electrical properties of the light-emitting elements of these sub-pixels PA through the detection electrodes.
  • the detection area includes a plurality of detection electrodes, and all sub-pixels in the display area may be connected to the plurality of detection electrodes in the detection area in a one-to-one correspondence, or all sub-pixels in a certain sub-area of the display area are It can be connected to a plurality of detection electrodes in the detection area in a one-to-one correspondence.
  • FIG. 3 is a schematic diagram of a pixel circuit and a detection circuit of a display substrate according to at least one embodiment of the disclosure.
  • the pixel circuit and the light-emitting element of the present exemplary embodiment are located in the display area 100 , and the detection circuit is located in a peripheral area of at least one side of the display area 100 .
  • the detection circuit may be provided within the detection area of the peripheral area, or the detection circuit may be provided on an external circuit board. However, this embodiment does not limit this.
  • the pixel circuit of this exemplary embodiment may include: a driving sub-circuit, a voltage transmission sub-circuit and a data writing sub-circuit.
  • the driving sub-circuit includes: a control terminal, a first terminal and a second terminal.
  • the voltage transmission sub-circuit is configured to apply the first power supply voltage provided by the first power supply line to the first terminal of the driving sub-circuit in response to the lighting control signal.
  • the data writing subcircuit is configured to write a data signal to the control terminal of the driving subcircuit and store the written data signal in response to the first scan signal and the second scan signal.
  • the driving sub-circuit is configured to drive the light-emitting element to emit light under the control of the control terminal and the first terminal of the driving sub-circuit.
  • FIG. 4 is an equivalent circuit diagram of a pixel circuit of a display substrate according to at least one embodiment of the disclosure.
  • the driving sub-circuit may include: a driving transistor M0 .
  • the data writing sub-circuit may include: a first transistor M1, a second transistor M2 and a first storage capacitor C1.
  • the voltage transfer subcircuit includes a third transistor M3.
  • the control electrode of the drive transistor M0 is connected to the first electrode of the first storage capacitor C1, the second electrode of the first transistor M1, and the second electrode of the second transistor M2, and the first electrode of the drive transistor M0 is connected to the third electrode of the third transistor M3.
  • the second electrode is connected, and the second electrode of the driving transistor M0 is connected to the first electrode of the light-emitting element EL.
  • the control electrode of the first transistor M1 is connected to the first scan signal line SL1, and the first electrode of the first transistor M1 is connected to the data line DL.
  • the control electrode of the second transistor M2 is connected to the second scan signal line SL2, and the first electrode of the second transistor M2 is connected to the data line DL.
  • the control electrode of the third transistor M3 is connected to the light-emitting control line EM, and the first electrode of the third transistor M3 is connected to the first power line ELVDD.
  • the second pole of the first storage capacitor C1 is connected to the second power supply line VSS.
  • the second pole of the light-emitting element EL is connected to the third power supply line Vcom.
  • FIG. 4 illustrates an exemplary structure of a pixel circuit. Those skilled in the art can easily understand that the implementation manner of the pixel circuit is not limited to this, as long as its function can be realized.
  • the symbol SL1 may represent both the first scan signal line and the level of the first scan signal provided by the first scan signal line.
  • the symbol SL2 can represent both the second scan signal line and the level of the second scan signal provided by the second scan signal line;
  • the symbol DL can represent both the data line and the level of the data signal provided by the data line.
  • the symbol EM can represent both the lighting control line and the level of the lighting control signal provided by the lighting control line;
  • the symbol ELVDD can represent both the first power supply line and the first power supply voltage provided by the first power supply line;
  • the symbol VSS It can represent both the second power supply line and the second power supply voltage provided by the second power supply line;
  • the symbol Vcom can represent both the third power supply line and the third power supply voltage provided by the third power supply line.
  • the driving transistor M0 is configured to drive the light-emitting element EL to emit light under the control of the control electrode and the first electrode of the driving transistor M0.
  • the light emitting element EL emits light of different degrees under the control of the driving transistor M0.
  • the first transistor M1 is configured to write the data signal supplied from the data line DL to the control electrode of the driving transistor M0 in response to the first scan signal supplied from the first scan signal line SL1.
  • the second transistor M2 is configured to write the data signal provided by the data line DL to the control electrode of the driving transistor M0 in response to the second scan signal provided by the second scan signal line SL2.
  • the third transistor M3 is configured to apply the first power supply voltage provided by the first power supply line ELVDD to the first electrode of the driving transistor M0 in response to the light emission control signal provided by the light emission control line EM.
  • the first storage capacitor C1 is configured to store a data signal written to the gate of the driving transistor M0.
  • the first power supply voltage provided by the first power supply line ELVDD may be a high-level voltage, for example, the first power supply voltage may be 5V.
  • the second power supply voltage provided by the second power supply line VSS may be a low level voltage.
  • the second power supply voltage provided by the second power supply line VSS may be a negative voltage or a ground voltage (generally 0V).
  • the third power supply voltage provided by the third power supply line Vcom may be a low level voltage.
  • the second power supply voltage provided by the second power supply line VSS and the third power supply voltage provided by the third power supply line Vcom may be the same, for example, both are ground voltages.
  • the light emitting element EL may be an OLED.
  • the light emitting element EL may be an OLED with a top emission structure or a bottom emission structure, and may emit red light, green light, blue light, or white light, and the like.
  • the light emitting element EL may be a micro OLED.
  • this embodiment does not limit this.
  • the first electrode of the light-emitting element EL is the anode of the OLED, and the second electrode is the cathode of the OLED; or, the first electrode may be the cathode of the OLED, and the second electrode may be the anode of the OLED.
  • the first transistor M1 may be a P-type MOS transistor
  • the second transistor M2 the third transistor M3 and the driving transistor M0 may be an N-type MOS transistor.
  • this embodiment does not limit this.
  • the types of the first transistor M1 and the second transistor M2 may be the same, which may be designed and determined according to actual conditions.
  • the first transistor M1 and the second transistor M2 may constitute a transmission gate switch having complementary characteristics.
  • the first scan signal supplied to the first transistor M1 and the second scan signal supplied to the second transistor M2 can be made to be mutually inverse signals, so that the first transistor M1 and the second scan signal can be guaranteed
  • One of the two transistors M2 is always on at the same time, so that the data signal can be transmitted to the first storage capacitor C1 without voltage loss, thereby improving the reliability and stability of the pixel circuit.
  • the first pole of the light emitting element EL may be connected to a detection circuit through a detection lead line TL and a detection electrode (not shown) located in the peripheral area.
  • the detection electrodes are arranged in the detection area of the display substrate, and the detection circuit can be arranged in the detection area of the display substrate; or, the detection electrodes are arranged in the detection area of the display substrate, and the detection circuit can be arranged on an external circuit board.
  • the detection circuit of this exemplary embodiment includes: a first control unit, a second control unit, and a storage unit. The first control unit is respectively connected to the detection electrode, the first control terminal Vt1 and the first node N1.
  • the detection electrodes are connected to the first electrodes of the light emitting elements EL in the display area 100 through the detection lead lines TL.
  • the second control unit is respectively connected to the second control terminal Vt2, the first signal terminal V0 and the first node N1.
  • the memory cells are respectively connected to the first node N1 and the first power supply terminal (eg, providing the second power supply voltage VSS).
  • the first control unit is configured to supply power to the detection electrode through the first node N1 under the control of the first control terminal Vt1.
  • the second control unit is configured to charge the first node N1 through the first signal terminal V0 under the control of the second control terminal Vt2, or collect the voltage of the first node N1 through the first signal terminal V0.
  • the memory cell is configured to store the voltage of the first node N1.
  • the first node N1 does not necessarily represent an actual component, but represents a junction of related circuit connections in the circuit diagram.
  • the symbol Vt1 represents both the first control terminal and the level of the first control signal provided by the first control terminal; similarly, the symbol Vt2 represents both the second control terminal and the level of the second control signal provided by the second control terminal.
  • the symbol V0 represents both the first signal terminal and the level of the first input signal provided by the first signal terminal; the symbol C2 represents both the second storage capacitor and the capacitance value of the second storage capacitor.
  • the first control unit includes a fourth transistor M4
  • the second control unit includes a fifth transistor M5
  • the storage unit includes a second storage capacitor C2 .
  • the control electrode of the fourth transistor M4 is connected to the first control terminal Vt1, the first electrode of the fourth transistor M4 is connected to the detection electrode, and the second electrode of the fourth transistor M4 is connected to the first node N1.
  • the control electrode of the fifth transistor M5 is connected to the second control terminal Vt2, the first electrode of the fifth transistor M5 is connected to the first signal terminal V0, and the second electrode of the fifth transistor M5 is connected to the first node N1.
  • the first pole of the second storage capacitor C2 is connected to the first node N1, and the second pole of the second storage capacitor C2 is connected to the first power supply terminal.
  • FIG. 5 shows an exemplary structure of the detection circuit, and those skilled in the art can easily understand that the implementation of the detection circuit is not limited to this, as long as its function can be realized.
  • FIG. 6 is an operation timing diagram of the pixel circuit provided in FIG. 5 .
  • the working process of the pixel circuit will be described by taking the first transistor M1 of the pixel circuit as a P-type transistor and the other transistors of the pixel circuit as N-type transistors as an example. As shown in FIG.
  • the pixel circuit involved in this embodiment includes: three switch transistors (including a first transistor M1 , a second transistor M2 and a third transistor M3 ), a drive transistor (including a drive transistor M0 ), and a capacitor unit (including the first storage capacitor C1), four signal input terminals (including the data line DL, the first scan signal line SL1, the second scan signal line SL2 and the light emission control line EM), and three power supply terminals (including the first power supply line ELVDD, a second power supply line VSS, and a third power supply line Vcom).
  • the first power supply line ELVDD provides a high-level voltage
  • the second power supply line VSS and the third power supply line Vcom provide a low-level voltage, such as ground voltages.
  • the pixel circuit in FIG. 5 operates and the detection circuit does not.
  • the display process of each frame of image includes a data writing phase PH11 and a light-emitting phase PH12.
  • a low-level signal is input to the first scan signal line SL1
  • a high-level signal is input to the second scan signal line SL2
  • both the first transistor M1 and the second transistor M2 are turned on to control the driving transistor M0.
  • the data signal provided by the data line DL is input to the pole, and the first storage capacitor C1 is charged.
  • a low-level signal is input to the light-emitting control line EM, and the third transistor M3 is turned off.
  • a high-level signal is input to the first scan signal line SL1
  • a low-level signal is input to the second scan signal line SL2
  • both the first transistor M1 and the second transistor M2 are turned off.
  • a high-level signal is input to the light-emitting control line EM
  • the third transistor M3 is turned on
  • the first power supply voltage input by the first power supply line ELVDD is supplied to the first electrode of the driving transistor M0.
  • the drive transistor M0 is a source follower device.
  • the driving transistor M0 operates in the sub-threshold region, and controls the voltage of the first electrode of the light-emitting element EL in a source-following manner, thereby controlling the light-emitting state of the light-emitting element EL.
  • FIG. 7 is a working timing diagram of the detection circuit provided in FIG. 5 .
  • the operation process of the detection circuit will be described by taking as an example that the fourth transistor M4 and the fifth transistor M5 of the detection circuit are N-type transistors.
  • the detection circuit involved in this embodiment includes: two switch transistors (including a fourth transistor M4 and a fifth transistor M5 ), a capacitor unit (including a second storage capacitor C2 ), three signal input terminals ( It includes a first control terminal Vt1, a second control terminal Vt2 and a first signal terminal V0), a signal output terminal (including the first signal terminal V0), and a power supply terminal (including the first power supply terminal).
  • the first signal terminal V0 serves as both a signal output terminal and a signal input terminal.
  • the first power supply terminal provides a negative voltage (eg, -3.5V) or a ground voltage.
  • the pixel circuit in FIG. 5 does not operate and the detection circuit operates.
  • the detection process of at least one sub-pixel includes the following stages.
  • the first control terminal Vt1 inputs a low-level signal
  • the second control terminal Vt2 inputs a high-level signal
  • the first signal terminal V0 inputs a high-level signal (for example, a high-level DC signal )
  • the fourth transistor M4 is turned off
  • the fifth transistor M5 is turned on.
  • the connection between the first node N1 and the light-emitting element EL is disconnected, and the high-level DC signal provided by the first signal terminal V0 can charge the second storage capacitor C2 until the high-level VGH is charged.
  • a high-level signal is input to the first control terminal Vt1
  • a low-level signal is input to the second control terminal Vt2
  • the fourth transistor M4 is turned on
  • the fifth transistor M5 is turned off.
  • the first node N1 and the light-emitting element EL are turned on
  • the second storage capacitor C2 can rapidly discharge the light-emitting element EL of the pixel circuit, and the light-emitting element EL emits light and gradually becomes darker.
  • the scan duration of the second sub-phase may be determined according to the turn-on voltage of the light-emitting element EL. For example, if the light-on voltage of the light-emitting element is 4V, and the voltage provided by the first power supply terminal is -3.5V, the time required for the second storage capacitor C2 to discharge to 0.5V can be set as the scanning time.
  • the discharge duration of the second sub-phase when detecting the average current and equivalent resistance of the light-emitting element, can be controlled to be less than or equal to the scanning duration; when detecting the critical turn-on voltage of the light-emitting element, the second sub-phase can be controlled The discharge duration is longer than the scan duration.
  • a low-level signal is input to the first control terminal Vt1
  • a high-level signal is input to the second control terminal Vt2
  • the fourth transistor M4 is turned off
  • the fifth transistor M5 is turned on.
  • the connection between the first node N1 and the light-emitting element EL is disconnected, the first node N1 is connected to the first signal terminal V0, and the voltage of the second storage capacitor C2 is sampled through the first signal terminal V0.
  • the light-emitting element when the current is greater than 10-4eA, the light-emitting element is in the weak short state, and when the current is less than 10-11eA and greater than 10-13eA, the light-emitting element emits light The element is in a weak off state.
  • the range of the equivalent resistance R of the light-emitting element is as follows: R ⁇ Vth/(Ion*100); when the light-emitting element is in the weak short state, the equivalent resistance of the light-emitting element is as follows: The range of R is as follows: Vth/Ioff>R>Vth/(Ioff*100).
  • the threshold voltage Vth of the light-emitting element is 9.5V
  • the equivalent resistance R of the light-emitting element is less than 95 kiloohms (K ⁇ )
  • the equivalent resistance of the light-emitting element is in the following range: 95000000 trillion
  • ohm (M ⁇ )>R>95000M ⁇ the light-emitting element is in a weak off state.
  • the equivalent resistance of the light-emitting element can be calculated through the voltage sampled in the third sub-stage, and then whether the light-emitting element is in a weak-off or weak-short state can be detected according to the equivalent resistance of the light-emitting element.
  • a fourth sub-phase PH24 of the detection phase may be entered.
  • the first control terminal Vt1 is input with a low level signal
  • the second control terminal Vt2 is input with a high level signal
  • the fourth transistor M4 is turned off
  • the fifth transistor M5 is turned on.
  • the connection between the first node N1 and the light-emitting element EL is disconnected, the first node N1 and the first signal terminal V0 are turned on, the first signal terminal V0 provides a ground voltage, and the second signal terminal V0 is connected to the second The storage capacitor C2 is discharged and reset.
  • the first sub-phase may be repeated, eg, to re-detect the electrical properties of the light-emitting element; or, after the fourth sub-phase PH24, the detection phase may be exited Enter the display stage.
  • this embodiment is not limited to this.
  • the detection circuit is connected to the light-emitting elements of the sub-pixels in the display area through the detection electrodes provided in the detection area through the detection lead lines, and can monitor the electrical properties of the light-emitting elements of the sub-pixels at different positions in the display area. The performance is tested to support the poor resolution of the display substrate.
  • the pixel circuit of this exemplary embodiment includes: a driving sub-circuit, a voltage transmission sub-circuit and a data writing sub-circuit.
  • the driving sub-circuit includes: a control terminal, a first terminal and a second terminal.
  • the voltage transfer subcircuit is configured to apply a reset voltage and a first power supply voltage to the first terminals of the driving subcircuit, respectively, in response to the transfer control signal.
  • the data writing subcircuit is configured to write the data signal to the control terminal of the driving subcircuit and store the written data signal in response to the first scan signal and the second scan signal.
  • the driving sub-circuit is configured to drive the light-emitting element to emit light under the control of the control terminal and the first terminal of the driving sub-circuit.
  • the peripheral area is provided with a voltage control circuit, and the voltage control circuit is connected with the pixel circuit.
  • the voltage control circuit is configured to provide a reset voltage to the voltage transfer subcircuit of the pixel circuit in response to the reset control signal, and to provide a first supply voltage to the voltage transfer subcircuit in response to the light emission control signal.
  • the driving sub-circuit includes: a driving transistor M0 .
  • the data writing sub-circuit includes a first transistor M1, a second transistor M2 and a first storage capacitor C1.
  • the voltage transmission sub-circuit includes: a third transistor M3.
  • the voltage control circuit includes: a sixth transistor M6 and a seventh transistor M7.
  • the control terminal of the driving transistor M0 is connected to the control terminal of the driving sub-circuit, the first terminal of the driving transistor M0 is connected to the first terminal of the driving sub-circuit, and the second terminal of the driving transistor M0 is connected to the second terminal of the driving sub-circuit.
  • the control electrode of the first transistor M1 is connected to the first scan signal line SL1, the first electrode of the first transistor M1 is connected to the data line D1, and the second electrode of the first transistor M1 is connected to the control electrode of the driving transistor M0.
  • the control electrode of the second transistor M2 is connected to the second scan signal line SL2, the first electrode of the second transistor M2 is connected to the data line DL, and the second electrode of the second transistor M2 is connected to the control electrode of the driving transistor M0.
  • the control electrode of the third transistor M3 is connected to the transmission control line VT, the first electrode of the third transistor M3 is connected to the second electrode of the sixth transistor M6 and the first electrode of the seventh transistor M7, and the second electrode of the third transistor M3 connected to the first pole of the driving transistor M0.
  • the first electrode of the first storage capacitor C1 is connected to the control electrode of the driving transistor M0, and the second electrode of the first storage capacitor C1 is connected to the second power supply line VSS.
  • the control electrode of the sixth transistor M6 is connected to the reset control line RS, and the first electrode of the sixth transistor M6 is connected to the reset voltage line Vinit.
  • the control electrode of the seventh transistor M7 is connected to the light emitting control line EM, and the second electrode of the seventh transistor M7 is connected to the first power line ELVDD.
  • the first electrode of the light-emitting element EL is connected to the second electrode of the driving transistor M0, and the second electrode of the light-emitting element EL is connected to the third power supply line Vcom.
  • the first transistor M1 and the seventh transistor M7 are P-type transistors
  • the driving transistor M0 , the second transistor M2 , the third transistor M3 and the sixth transistor M6 are N-type transistors.
  • this embodiment does not limit this.
  • the operation process of the pixel circuit is described by taking the first transistor M1 of the pixel circuit and the seventh transistor M7 of the voltage control circuit as P-type transistors, and the remaining transistors of the pixel circuit as N-type transistors.
  • the pixel circuit in FIG. 10 works, and the detection circuit does not work.
  • the display process of each frame of image includes a reset stage, a data writing stage, a light-emitting stage and a non-light-emitting stage.
  • the reset control line RS inputs a high-level signal, and the sixth transistor M6 is turned on; the transmission control line VT inputs a high-level signal, and the third transistor M3 is turned on; the light-emitting control line EM inputs a high-level signal, and the seventh Transistor M7 is turned off.
  • a high-level signal is input to the first scan signal line SL1, a low-level signal is input to the second scan signal line SL2, and both the first transistor M1 and the second transistor M2 are turned off.
  • the light-emitting element EL is reset with a low potential (eg, ground voltage) supplied from the reset voltage line Vinit.
  • a low-level signal is input to the first scan signal line SL1
  • a high-level signal is input to the second scan signal line SL2
  • the first transistor M1 and the second transistor M2 are both turned on, and the control electrode of the driving transistor M0
  • the data signal provided by the data line DL is input, and the first storage capacitor C1 is charged.
  • the reset control line RS is input with a low level signal
  • the sixth transistor M6 is turned off
  • the light emission control line EM is input with a high level signal
  • the seventh transistor M7 is turned off.
  • a low-level signal is input to the transmission control line VT, and the third transistor M3 is turned off.
  • a high-level signal is input to the first scan signal line SL1
  • a low-level signal is input to the second scan signal line SL2
  • both the first transistor M1 and the second transistor M2 are turned off.
  • the light-emitting control line EM inputs a low-level signal
  • the seventh transistor M7 is turned on
  • the reset control line RS inputs a low-level signal
  • the sixth transistor M6 is turned off.
  • a high-level signal is input to the transmission control line VT, and the third transistor M3 is turned on.
  • the first power supply voltage supplied from the first power supply line ELVDD is applied to the first electrode of the driving transistor M0 through the sixth transistor M6 and the third transistor M3.
  • a low-level signal is input to the transmission control line VT, and the third transistor M3 is turned off, so that the first power supply voltage cannot be applied to the first electrode of the driving transistor M0, so that the light-emitting element EL stops emitting light.
  • FIG. 9 and FIG. 10 The structures and working modes of the detection circuits in FIG. 9 and FIG. 10 can be referred to the descriptions of the foregoing embodiments, so they will not be repeated here.
  • the technical solution of this embodiment is described below by taking an example of a preparation process of a display substrate.
  • the "patterning process” mentioned in this embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, developing, etching, and stripping photoresist, and is a known mature preparation process.
  • the deposition can use known processes such as sputtering, evaporation, and chemical vapor deposition, the coating can use a known coating process, and the etching can use a known method, which is not limited herein.
  • thin film refers to a layer of thin film produced by depositing or coating a certain material on a substrate.
  • the "thin film” may also be referred to as a "layer”. If the "thin film” needs a patterning process or a photolithography process in the whole manufacturing process, it is called a "thin film” before the patterning process, and a “layer” after the patterning process.
  • a “layer” after a patterning process or a photolithography process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process.
  • the sub-pixels provided in the display area have pixel circuits as shown in FIG. 5 , and the detection area is provided with detection electrodes connected to the sub-pixels through detection lead lines as an example for description.
  • the detection circuit is provided on the external circuit board, and the detection circuit is connected to the light-emitting element of the corresponding sub-pixel in the display area through the detection electrode and the detection lead wire.
  • the first transistor M1 of the pixel circuit in the display area is a P-type transistor
  • the second transistor M2 , the third transistor M3 and the driving transistor M0 are N-type transistors.
  • the manufacturing process of the display substrate of the present exemplary embodiment may include the following steps.
  • a silicon-based base substrate is provided, for example, the material of which is P-type single crystal silicon.
  • N-type transistors eg, driving transistors
  • the P-type substrate acts as a channel region of the N-type transistor, which is beneficial to take advantage of the high speed of NMOS devices and improve circuit performance.
  • N-type doping is performed on the P-type silicon-based substrate to form an N-type well region WL1, which serves as the substrate of the first transistor M1 (ie, the P-type transistor).
  • a first insulating layer 501 is formed on the aforementioned base substrate 10 , and then a first conductive layer is formed on the first insulating layer 501 through a patterning process, as shown in FIGS. 11 and 12 .
  • a first insulating layer is formed on the base substrate by a thermal oxidation method, and the material of the first insulating layer can be silicon nitride, oxide or oxynitride; then, a first conductive material is formed on the first insulating layer layer, and performing a photolithography process on the first conductive material layer to form a first conductive layer.
  • the material of the first conductive layer may be polysilicon material.
  • the first insulating layer 501 may be referred to as a gate insulating layer.
  • the first conductive layer at least includes: the control electrode 113 of the first transistor M1 , the control electrode 123 of the second transistor M2 , the control electrode 133 of the third transistor M3 and the control electrode 143 of the driving transistor M0 .
  • the base substrate on which the first conductive layer is formed is heavily doped to form doped regions on the base substrate for electrical connection.
  • the doped regions for electrical connection include: the source region 110S and the drain region 110D of the active region 110 of the first transistor M1 , the source of the active region 120 of the second transistor M2 The electrode and drain regions, the source and drain regions of the active region 130 of the third transistor M3, the source region 140S and the drain region 140D of the active region 140 of the driving transistor M0, and the N-type well region WL1 The first contact region 301 and the second contact region 302 in the P-type substrate.
  • the active region 140 of the driving transistor M0 extends along the first direction X
  • the active region 110 of the first transistor M1 the active region 120 of the second transistor M2 and the active region 130 of the third transistor M3 extend along the second direction Y
  • the first direction X is perpendicular to the second direction Y.
  • the first transistor M1, the second transistor M2 and the third transistor M3 are sequentially arranged along the first direction X
  • the first transistor M1, the second transistor M2 and the third transistor M3 are arranged along the second direction Y on the side of the driving transistor M0. side.
  • N-type doping and P-type doping may be performed, respectively, for example, to form source and drain regions of N-type transistors and source and drain regions of P-type transistors.
  • a barrier layer may be formed to shield the region that is not subjected to N-type doping; during the P-type doping process, a barrier layer may be formed to shield the region that is not subjected to P-type doping.
  • the barrier layer may be a silicon nitride, oxide or oxynitride, or may be a photoresist material. After the doping process is completed, the barrier layer can remain in the display substrate, or can also be removed.
  • the N-type doping process may be, for example, an ion implantation process, and the doping element may be, for example, boron element.
  • the P-type doping process may be, for example, an ion implantation process, and the doping element may be phosphorus, for example.
  • the second insulating layer and the second conductive layer are sequentially formed on the base substrate.
  • the second insulating layer 502 is formed on the above-mentioned base substrate 10 , and then the second conductive layer is formed on the second insulating layer 502 , as shown in FIGS. 13 and 14 .
  • the material of the second conductive layer 502 may be a metal material.
  • the second conductive layer 502 may also be referred to as a first metal layer.
  • a plurality of via holes are formed on the second insulating layer 502 , and the plurality of via holes at least include: a first via hole V1 to a tenth via hole V10 . Both the first insulating layer 501 and the second insulating layer 502 in the plurality of vias are removed.
  • the second conductive layer at least includes: a first power line ELVDD, a fourth power line VDD, a ground line GND, a light-emitting control line EM, a data line DL, the first electrode 111 of the first transistor M1 and the second pole 112, the first pole 121 and the second pole 122 of the second transistor M2, the first pole 131 and the second pole 132 of the third transistor M3, the first pole 141 and the second pole 142 of the driving transistor M0.
  • both the second power supply line VSS and the third power supply line Vcom provide a ground voltage, that is, both the second power supply voltage and the third power supply voltage may be provided by the grounding line GND.
  • the second electrode 112 of the first transistor M1 and the second electrode 122 of the second transistor M2 are integrally formed.
  • the first electrode 111 of the first transistor M1 , the first electrode 121 of the second transistor M2 and the data line DL are integrally formed.
  • the first electrode 131 of the third transistor M3 is integrated with the first power line ELVDD, and the second electrode 132 of the third transistor M3 is integrated with the first electrode 141 of the driving transistor M0 .
  • the fourth power line VDD provides a high-level voltage, eg, 5V.
  • the first electrode 111 of the first transistor M1 is electrically connected to the source region 110S of the active region 110 of the first transistor M1 through the first via V1
  • the second electrode 112 of the first transistor M2 is electrically connected to the drain region 110D of the active region 110 of the first transistor M1 through the second via hole V2.
  • the first electrode 121 of the second transistor M2 is electrically connected to the drain region of the active region 110 of the second transistor M2 through the third via V3, and the second electrode 122 of the second transistor M2 is electrically connected to the second transistor M2 through the fourth via V4.
  • the drain region of the active region 110 of the transistor M2 is electrically connected.
  • the first electrode 131 of the third transistor M3 is electrically connected to the source region of the active region 130 of the third transistor M3 through the fifth via V5
  • the second electrode 132 of the third transistor M3 is electrically connected to the third transistor M3 through the sixth via V6
  • the drain region of the active region 130 of the transistor M3 is electrically connected.
  • the first electrode 141 of the driving transistor M0 is electrically connected to the drain region 140D of the active region 140 of the driving transistor M0 through the seventh via V7
  • the second electrode 142 of the driving transistor M0 is electrically connected to the drain region 140D of the driving transistor M0 through the eighth via V8.
  • the source region 140S of the active region 140 is electrically connected.
  • the orthographic projection of the first power line ELVDD on the base substrate is located in the orthographic projection of the fourth power line VDD on the base substrate and the data line DL on the base substrate between the orthographic projections of , the orthographic projection of the light-emitting control line EM on the base substrate is located on the side of the orthographic projection of the fourth power supply line VDD on the base substrate away from the first power supply line ELVDD.
  • the partial extension directions of the first power line ELVDD, the fourth power line VDD, the data line DL and the light emission control line EM are parallel to the first direction X.
  • the fourth power supply line VDD extends along the first direction X, there is a bending region; in addition, the light emitting control line EM also has a bending region when extending along the first direction X, and the fourth power supply line VDD is connected to the lighting control line EM.
  • the bending directions of the wires EM are different.
  • the fourth power line VDD is connected to the first contact region 301 through the ninth via V9
  • the ground line GND is connected to the second contact region 302 through the tenth via V10 .
  • Connecting the first contact region 301 through the fourth power line VDD can bias the N-type well region WL1 where the first transistor M1 is located. type substrate for biasing.
  • the parasitic PN junction between the two can be reversely biased, so as to electrically isolate the device and reduce the interference of the device. The parasitic effect between them improves the stability of the circuit.
  • a third insulating layer 503 and a third conductive layer are sequentially formed on the base substrate 10 on which the aforementioned structure is formed, as shown in FIGS. 15 and 16 .
  • a plurality of via holes are provided on the third insulating layer 503, and the plurality of via holes at least include: an eleventh via hole V11 exposing the second electrode 112 of the first transistor M1, a first via hole V11 exposing the control electrode 140 of the driving transistor M0 Twelve via holes V12, a thirteenth via hole V13 exposing the gate electrode 113 of the first transistor M1, and a fourteenth via hole V14 exposing the gate electrode 123 of the second transistor M2.
  • the third conductive layer at least includes: a first transfer electrode 401 , a second transfer electrode 402 and a third transfer electrode 403 .
  • the extending directions of the first transfer electrodes 401, the second transfer electrodes 402 and the third transfer electrodes 403 are parallel to the second direction Y.
  • the first transfer electrode 401 is connected to the second electrode 112 of the first transistor M1 through the eleventh via V11, and is connected to the control electrode 143 of the driving transistor M0 through the twelfth via V12, so as to realize the second electrode of the first transistor M1.
  • the second transfer electrode 402 is connected to the control electrode 113 of the first transistor M1 through the thirteenth via V13.
  • the third transfer electrode 403 is connected to the control electrode 123 of the second transistor M2 through the fourteenth via V14.
  • a fourth insulating layer and a fourth conductive layer are formed on the base substrate in sequence.
  • a fourth insulating layer 504 and a fourth conductive layer are sequentially formed on the base substrate 10 forming the aforementioned structure, as shown in FIGS. 17 and 18 .
  • a plurality of via holes are provided on the fourth insulating layer 504 , and the plurality of via holes at least include: a fifteenth via hole V15 exposing the control electrode 143 of the driving transistor M0 , and a sixteenth via hole V15 exposing the second transfer electrode 402 .
  • the hole V16 and the seventeenth via hole V17 exposing the third via electrode 403 .
  • the fourth conductive layer includes at least a first scan signal line SL1 , a second scan signal line SL2 , and a first electrode 201 and a second electrode 202 .
  • the first electrode 201 includes a plurality of strip electrodes
  • the second electrode 202 includes a plurality of strip electrodes
  • the plurality of strip electrodes of the first electrode 201 and the plurality of strip electrodes of the second electrode 202 are alternately arranged with each other, and the first The first electrode 201 and the second electrode 202 and the space therebetween form a first sub-capacitor.
  • the first electrode 201 serves as the first electrode of the first sub-capacitor
  • the second electrode 202 serves as the second electrode of the first sub-capacitor.
  • the first sub-capacitor is a part of the first storage capacitor C1, and the first sub-capacitor and the second sub-capacitor hereinafter are connected in parallel to form the first storage capacitor C1.
  • the orthographic projection of the second scan signal line SL2 on the base substrate at least partially overlaps with the orthographic projection of the data line DL on the base substrate.
  • the data line DL can be prevented from occupying additional layout area, thereby further reducing the size of the display substrate
  • the occupied layout area is more conducive to achieving high PPI.
  • the orthographic projection of the first power supply line ELVDD on the base substrate is located at the orthographic projection of the second scanning signal line SL2 on the base substrate and the orthographic projection of the light emission control line EM on the base substrate between orthographic projections. Since the first power supply voltage transmitted by the first power supply line ELVDD is a DC signal, and the second scan signal transmitted by the second scan signal line SL2 and the light-emitting control signal transmitted by the light-emitting control line EM are both transition signals, the above arrangement is adopted. The method can effectively shield the mutual interference between the second scanning signal and the light-emitting control signal.
  • a fifth insulating layer 505 , a fifth conductive layer, a sixth insulating layer 506 , a sixth conductive layer, a seventh insulating layer 507 and a seventh conductive layer are sequentially formed on the base substrate on which the aforementioned structures are formed layers, as shown in Figures 19 to 22.
  • the fifth conductive layer includes at least a third electrode 203 , for example, the third electrode 203 is a planar electrode, and the third electrode 203 serves as the first electrode of the second sub-capacitor.
  • the sixth conductive layer includes at least a fourth electrode 204 , for example, the fourth electrode 204 is a planar electrode, and the fourth electrode 204 serves as the second pole of the second sub-capacitor.
  • the third electrode 203 and the fourth electrode 204 and the spaced portion therebetween form the second sub-capacitor C12.
  • the seventh insulating layer at least includes: an eighteenth via hole V18 exposing the fourth electrode 204, a nineteenth via hole V19 exposing the first electrode 201, and exposing the driving transistor M0.
  • the seventh conductive layer at least includes: the fourth transfer electrode 205 and the detection lead line TL.
  • the fourth transfer electrode 205 is connected to the fourth electrode 204 through the eighteenth via hole V18, and is connected to the first electrode 201 through the nineteenth via hole V19 to realize the control electrode 143 of the driving transistor 140 and the first sub-capacitor.
  • the second electrode 202 and the third electrode 203 are configured to receive a second supply voltage, eg, a ground voltage.
  • the detection lead line TL is connected to the second pole 142 of the driving transistor M0 through the twentieth via hole V20 .
  • the detection lead lines TL extend from the display area to the detection area so as to be electrically connected to the detection electrodes in the detection area.
  • an eighth insulating layer and an eighth conductive layer are sequentially formed on the base substrate on which the aforementioned structure is formed, as shown in FIG. 23 and FIG. 24 .
  • the planar structures of the display area and the detection area are illustrated in FIGS. 23 and 24 .
  • the eighth insulating layer of the display region 100 is provided with at least a plurality of twenty-first via holes V21
  • the eighth insulating layer of the detection region 102 is provided with at least a plurality of twenty-second via holes V22 .
  • the eighth insulating layer in the plurality of twenty-first via holes V21 and twenty-second via holes V22 is removed.
  • the twenty-first via hole V21 in the display area 100 corresponds to the twenty-second via hole V22 in the detection area 102 in one-to-one correspondence.
  • the twenty-first via hole V21 exposes the first end of the detection lead line TL in the display area 100
  • the twenty-second via hole V22 exposes the second end of the detection lead line TL in the detection area 102 .
  • the projections of the twenty-first via V21 and the twenty-second via V22 on the base substrate may be rectangles. However, this embodiment does not limit this.
  • the projected shapes of the twenty-first via hole and the twenty-second via hole on the base substrate may be the same or different, for example, both may be circular, oval, or square.
  • the plurality of twenty-second via holes V22 may be arranged in an array, for example, may be arranged in two rows. However, this embodiment does not limit this.
  • the distance a between two adjacent twenty-first via holes V21 may range from 2330 micrometers to 3500 micrometers, for example, the distance a Can be 2915 microns.
  • the distance b between two adjacent twenty-first via holes V21 may be in the range of 1330 micrometers to 2000 micrometers, for example, the distance b may be 1656 micrometers.
  • this embodiment does not limit this.
  • the detection lead line TL may be formed by connecting a plurality of straight line segments.
  • the detection lead line in the display area may extend to the Detection area.
  • the detection lead line can be formed by connecting straight line segments and curved line segments.
  • the line width of the detection pinout may range from 3.5 micrometers to 35 micrometers, for example, it may be 35 micrometers. However, this embodiment does not limit this.
  • the eighth conductive layer at least includes: the first electrode 601 of the light-emitting element located in the display area 100 , the detection electrode 602 located in the detection area 102 , and the bonding area located in the binding area 103 .
  • Fixed electrode (not shown).
  • the first pole 601 of the light-emitting element may be an anode, and the first poles 601 may be hexagonal and regularly arranged.
  • the first electrode 601 in the display area 100 is connected to the first end of the detection lead TL through the twenty-first via V21, and the detection electrode 602 in the detection area 102 is connected to the detection lead TL through the twenty-second via V22.
  • the second end is connected to realize electrical connection between the detection electrode 602 and the light-emitting element and the pixel circuit corresponding to the light-emitting element through the detection lead line TL.
  • a plurality of detection electrodes 602 are regularly arranged in the detection area 102 .
  • At least one detection electrode 602 may be square, for example, the side length c of the detection electrode 602 may range from 55 micrometers to 85 micrometers, for example, the side length c is 70 micrometers.
  • the distance e between two adjacent detection electrodes 602 may range from 40 micrometers to 60 micrometers, for example, the distance e may be 50 micrometers.
  • the distance f between two adjacent detection electrodes 602 may range from 55 micrometers to 85 micrometers, for example, the distance f may be 70 micrometers.
  • the detection electrodes may be rectangular or circular, or the like.
  • the distance d1 between the display area 100 and the detection area 102 may range from 350 ⁇ m to 530 ⁇ m, for example, the distance d1 may be 440 ⁇ m .
  • the distance d2 between the detection area 102 and the binding area 103 may range from 350 micrometers to 530 micrometers, for example, the distance d2 may be 440 micrometers.
  • the spacing d1 may be equal to the spacing d2. However, this embodiment does not limit this.
  • a pixel definition film is coated on the substrate on which the aforementioned structure is formed, and a pixel definition layer (PDL, Pixel Define Layer) pattern is formed by masking, exposing and developing processes, and the pixel definition layer is formed on the display.
  • PDL Pixel Define Layer
  • the pixel-defining layer in the sub-pixels is formed with pixel openings exposing the anodes.
  • a light-emitting functional layer is formed in the pixel opening formed above, and the light-emitting functional layer is connected to the anode of the light-emitting element.
  • a cathode film is deposited, and the cathode film is patterned through a patterning process to form a cathode pattern, and the cathodes are respectively connected to the light-emitting functional layer and the third power supply line Vcom.
  • an encapsulation layer is formed on the cathode, and the encapsulation layer may include a laminated structure of inorganic material/organic material/inorganic material.
  • the pixel definition layer may employ inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON).
  • the anode can be made of transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the cathode can be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or any one or more of the above metals alloy.
  • the anode can be made of a reflective material such as metal, and the cathode can be made of a transparent conductive material.
  • the pixel circuit can be a 3T1C or 7T1C design.
  • the first electrode of the first storage capacitor and the control electrode of the driving transistor may be formed in the same layer and integrally formed, and the second electrode of the first storage capacitor may be formed in the base substrate.
  • the detection circuit may be arranged in the detection area.
  • the embodiments of the present disclosure do not make any limitation here.
  • the preparation process of the embodiment of the present disclosure can be realized by using the current mature preparation equipment, and can be well compatible with the existing preparation process.
  • the process is simple to implement, easy to implement, high in production efficiency, low in production cost and high in yield.
  • the light-emitting elements of the sub-pixels in the display area are connected to the detection electrodes in the detection area through the detection lead wires, and are connected to the detection circuit through the detection electrodes, and the detection circuit realizes the detection of the electrical properties of the light-emitting elements, thereby Provides support for failure analysis of display substrates.
  • At least one embodiment of the present disclosure further provides a method for fabricating a display substrate, including: providing a base substrate, the base substrate including a display area and a peripheral area on one side of the display area. A plurality of sub-pixels, at least one detection electrode and detection lead lines are formed on the base substrate. Wherein, a plurality of sub-pixels are arranged in the display area, and at least one sub-pixel in the plurality of sub-pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element.
  • the peripheral area includes a detection area, at least one detection electrode is arranged in the detection area, and the at least one detection electrode is electrically connected with the first pole of the light-emitting element and the corresponding pixel circuit through the detection lead wire, so as to detect the light-emitting element through the detection electrode in the detection stage. electrical properties.
  • forming a plurality of sub-pixels, at least one detection electrode and a detection lead wire on the base substrate includes: forming an active layer, a first conductive layer, a second conductive layer, a first conductive layer, a first conductive layer, a first conductive layer on the base substrate in sequence Three conductive layers, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, and an eighth conductive layer.
  • the active layer includes at least: active regions of a plurality of transistors of the pixel circuit.
  • the first conductive layer at least includes: control electrodes of a plurality of transistors of the pixel circuit.
  • the second conductive layer at least includes: first and second electrodes of a plurality of transistors of the pixel circuit, a first power supply line, a second power supply line, a light-emitting control line and a data line.
  • the third conductive layer at least includes: a first transfer electrode for connecting the second electrode of the first transistor, the second electrode of the second transistor and the control electrode of the driving transistor, and the control electrode of the first transistor and the first transfer electrode
  • the second transfer electrode of the scan signal line is used for connecting the control electrode of the second transistor and the third transfer electrode of the second scan signal line.
  • the fourth conductive layer at least includes: a first scan signal line, a second scan signal line, a first pole and a second pole of the first sub-capacitor.
  • the fifth conductive layer includes at least: the first pole of the second sub-capacitor.
  • the sixth conductive layer at least includes: the second pole of the second sub-capacitor; the first sub-capacitor and the second sub-capacitor are connected in parallel to form a first storage capacitor.
  • the seventh conductive layer at least includes: a fourth transfer electrode for connecting the first pole of the first parallel sub-capacitor of the first storage capacitor and the second pole of the second parallel sub-capacitor, a detection electrode extending from the display area to the detection area Lead wire; the first end of the detection lead wire is connected with the second pole of the driving transistor.
  • the eighth conductive layer at least includes: the first electrode of the light-emitting element located in the display area, and the detection electrode located in the detection area.
  • the first pole of the light-emitting element is connected to the first end of the detection lead wire, and the detection electrode is connected to the second end of the detection lead wire.
  • At least one embodiment of the present disclosure provides a method for detecting a display substrate.
  • the display substrate includes: a base substrate, and the base substrate includes a display area and a peripheral area on one side of the display area.
  • the display area is provided with a plurality of sub-pixels, and at least one sub-pixel of the plurality of sub-pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element.
  • the peripheral area includes a detection area, the detection area is provided with at least one detection electrode, and the at least one detection electrode is electrically connected to the first electrode of the light-emitting element and the pixel circuit through the detection lead wire.
  • At least one detection electrode is electrically connected to a detection circuit
  • the detection circuit includes: a first control unit, a second control unit and a storage unit.
  • the first control unit is respectively connected with the detection electrode, the first control terminal and the first node.
  • the second control unit is respectively connected with the second control terminal, the first signal terminal and the first node.
  • the storage unit is connected to the first node and the first power terminal respectively.
  • the detection method includes: in the first sub-stage of the detection stage, under the control of the first control terminal of the detection circuit, disconnecting the connection between the detection electrode and the first node, and under the control of the second control terminal, the first signal terminal is sent to the first node through the first signal terminal.
  • One node is charged; in the second sub-stage of the detection stage, under the control of the second control terminal of the detection circuit, the connection between the first signal terminal and the first node is disconnected, and under the control of the first control terminal, the first node is connected to the The detection electrode is powered; in the third sub-stage of the detection stage, under the control of the first control terminal of the detection circuit, the connection between the detection electrode and the first node is disconnected, and under the control of the second control terminal, the first signal terminal is collected through the first signal terminal.
  • the voltage of a node is determined according to the voltage collected from the first signal terminal to determine the electrical performance of the light-emitting element.
  • the electrical properties of the light-emitting element are determined according to the voltage collected from the first signal terminal, including at least one of the following:
  • the average current of the light-emitting element is calculated according to the voltage sampled from the first signal terminal in the third sub-stage; the equivalent resistance of the light-emitting element is calculated according to the collected voltage and the calculated average current ; According to the equivalent resistance of the light-emitting element, determine whether the light-emitting element is in a weak short and weak state;
  • the critical turn-on voltage of the light-emitting element is determined according to the voltage sampled from the first signal terminal in the third sub-phase.
  • FIG. 25 is a schematic diagram of a display device according to at least one embodiment of the disclosure.
  • this embodiment provides a display device 91 including: a display substrate 910 .
  • the display substrate 910 is the display substrate provided in the foregoing embodiments.
  • the display substrate 910 may be a micro OLED display substrate.
  • the display device 91 may be: OLED panel, OLED TV, mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, navigator, and any other product or component with display function. However, this embodiment does not limit this.

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Abstract

一种显示基板，包括：衬底基板，衬底基板包括显示区域以及位于显示区域至少一侧的外围区域。显示区域设置有多个子像素，多个子像素中的至少一个子像素包括发光元件和用于驱动所述发光元件的像素电路。外围区域包括检测区域，检测区域设置有至少一个检测电极，至少一个检测电极通过检测引出线与发光元件的第一极和像素电路电连接，以在检测阶段，通过检测电极检测发光元件的电学性能。

Description

显示基板及其检测方法、制备方法、显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及其检测方法、制备方法、显示装置。
背景技术
微型有机发光二极管(Micro-OLED，Micro Organic Light-Emitting Diode)是近年来发展起来的微型显示器，硅基OLED是其中一种。硅基OLED不仅可以实现像素的有源寻址，并且可以实现在硅基衬底上制备包括时序控制(TCON，Timer Control)电路、过电流保护(OCP，Over Current Protection)电路等多种功能电路，有利于减小系统体积，实现轻量化。硅基OLED采用成熟的互补金属氧化物半导体(CMOS，Complementary Metal Oxide Semiconductor)集成电路工艺制备，具有体积小、高分辨率(PPI)、高刷新率等优点，广泛应用在虚拟现实(VR，Virtual Reality)或增强现实(AR，Augmented Reality)近眼显示领域中。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板及其检测方法、制备方法、显示装置。
一方面，本公开实施例提供一种显示基板，包括：衬底基板，所述衬底基板包括显示区域以及位于所述显示区域至少一侧的外围区域。所述显示区域设置有多个子像素，所述多个子像素中的至少一个子像素包括发光元件和用于驱动所述发光元件的像素电路。所述外围区域包括检测区域，所述检测区域设置有至少一个检测电极，所述至少一个检测电极通过检测引出线与所述发光元件的第一极和所述像素电路电连接，以在检测阶段，通过所述检测电极检测所述发光元件的电学性能。
在一些示例性实施方式中，所述至少一个检测电极与设置在所述外围区域的检测电路电连接，或者，所述至少一个检测电极与设置在外部电路板上的检测电路电连接。
在一些示例性实施方式中，所述检测电路包括：第一控制单元、第二控制单元和存储单元。所述第一控制单元，分别与所述检测电极、第一控制端和第一节点连接，配置为在所述第一控制端的控制下，通过所述第一节点向所述检测电极供电。所述第二控制单元，分别与第二控制端、第一信号端和第一节点连接，配置为在所述第二控制端的控制下，通过所述第一信号端向所述第一节点充电，或者，通过所述第一信号端采集所述第一节点的电压。所述存储单元，分别与所述第一节点和第一电源端连接，配置为存储所述第一节点的电压。
在一些示例性实施方式中，所述第一控制单元包括：第四晶体管，所述第四晶体管的控制极与第一控制端连接，所述第四晶体管的第一极与所述检测电极连接，所述第四晶体管的第二极与所述第一节点连接。所述第二控制单元包括：第五晶体管，所述第五晶体管的控制极与第二控制端连接，所述第五晶体管的第一极与第一信号端连接，所述第五晶体管的第二极与所述第一节点连接。所述存储单元包括：第二存储电容，所述第二存储电容的第一极与所述第一节点连接，所述第二存储电容的第二极与第一电源端连接。
在一些示例性实施方式中，所述检测区域内的相邻检测电极之间的间距范围为40微米至85微米。
在一些示例性实施方式中，所述外围区域还包括：位于所述显示区域一侧的绑定区域，所述检测区域位于所述显示区域和绑定区域之间。
在一些示例性实施方式中，所述检测区域与所述显示区域之间的间距范围可以为350微米至530微米，所述检测区域与所述绑定区域之间的间距范围可以为350微米至530微米。
在一些示例性实施方式中，所述检测引出线的线宽范围为3.5微米至35微米。
在一些示例性实施方式中，所述显示区域为矩形，所述显示区域被划分 为3*3形式的九个矩形子区域，所述检测区域包括多个检测电极，所述多个检测电极与所述九个矩形子区域的中心位置和顶点位置的子像素的发光元件的第一极连接。
在一些示例性实施方式中，在垂直于所述衬底基板的方向上，所述显示基板至少包括：沿着远离所述衬底基板依次设置的第N-1导电层和第N导电层，N为正整数。所述第N-1导电层至少包括：从所述显示区域延伸到所述检测区域的检测引出线，所述检测引出线与所述发光元件对应的像素电路电连接。所述第N导电层至少包括：位于所述显示区域的发光元件的第一极、以及位于所述检测区域的检测电极；所述检测引出线的第一端与所述发光元件的第一极连接，所述检测引出线的第二端与所述检测电极连接。
在一些示例性实施方式中，所述像素电路包括：驱动子电路、电压传输子电路和数据写入子电路。所述驱动子电路包括：控制端、第一端和第二端。所述电压传输子电路配置为响应于发光控制信号，将第一电源线提供的第一电源电压施加到所述驱动子电路的第一端。所述数据写入子电路配置为响应于第一扫描信号和第二扫描信号，将数据信号写入所述驱动子电路的控制端并存储写入的所述数据信号。所述驱动子电路配置为在所述驱动子电路的控制端和第一端的控制下，驱动发光元件发光。
在一些示例性实施方式中，所述驱动子电路包括：驱动晶体管，所述数据写入子电路包括：第一晶体管、第二晶体管和第一存储电容，所述电压传输子电路包括：第三晶体管。所述驱动晶体管的控制极与所述驱动子电路的控制端连接，所述驱动晶体管的第一极与所述驱动子电路的第一端连接，所述驱动晶体管的第二极与所述驱动子电路的第二端连接。所述第一晶体管的控制极与第一扫描信号线连接，所述第一晶体管的第一极与数据线连接，所述第一晶体管的第二极与所述驱动晶体管的控制极连接。所述第二晶体管的控制极与第二扫描信号线连接，所述第二晶体管的第一极与所述数据线连接，所述第二晶体管的第二极与所述驱动晶体管的控制极连接。所述第三晶体管的控制极与发光控制线连接，所述第三晶体管的第一极与第一电源线连接，所述第三晶体管的第二极与所述驱动晶体管的第一极连接。所述第一存储电容的第一极与所述驱动晶体管的控制极连接，所述第一存储电容的第二极与 第二电源线连接。所述发光元件的第一极与所述驱动晶体管的第二极连接，所述发光元件的第二极与第三电源线连接。
在一些示例性实施方式中，所述像素电路包括：驱动子电路、电压传输子电路和数据写入子电路。所述驱动子电路包括：控制端、第一端和第二端。所述电压传输子电路配置为响应于传输控制信号，将复位电压和第一电源电压分别施加到所述驱动子电路的第一端。所述数据写入子电路配置为响应于第一扫描信号和第二扫描信号，将数据信号写入所述驱动子电路的控制端并存储写入的所述数据信号。所述驱动子电路配置为在所述驱动子电路的控制端和第一端的控制下，驱动发光元件发光。所述外围区域设置有电压控制电路，所述电压控制电路与所述像素电路连接；所述电压控制电路配置为响应于复位控制信号，向所述像素电路的电压传输子电路提供复位电压，以及响应于发光控制信号，向所述电压传输子电路提供第一电源电压。
在一些示例性实施方式中，所述驱动子电路包括：驱动晶体管，所述数据写入子电路包括第一晶体管、第二晶体管和第一存储电容，所述电压传输子电路包括：第三晶体管。所述电压控制电路包括：第六晶体管和第七晶体管。所述驱动晶体管的控制极与所述驱动子电路的控制端连接，所述驱动晶体管的第一极与所述驱动子电路的第一端连接，所述驱动晶体管的第二极与所述驱动子电路的第二端连接。所述第一晶体管的控制极与第一扫描信号线连接，所述第一晶体管的第一极与数据线连接，所述第一晶体管的第二极与所述驱动晶体管的控制极连接。所述第二晶体管的控制极与第二扫描信号线连接，所述第二晶体管的第一极与所述数据线连接，所述第二晶体管的第二极与所述驱动晶体管的控制极连接。所述第三晶体管的控制极与传输控制线连接，所述第三晶体管的第一极与所述第六晶体管的第二极以及所述第七晶体管的第一极连接，所述第三晶体管的第二极与所述驱动晶体管的第一极连接。所述第一存储电容的第一极与所述驱动晶体管的控制极连接，所述第一存储电容的第二极与第二电源线连接。所述第六晶体管的控制极与复位控制线连接，所述第六晶体管的第一极与复位电压线连接，所述第七晶体管的控制极与发光控制线连接，所述第七晶体管的第二极与第一电源线连接。所述发光元件的第一极与所述驱动晶体管的第二极连接，所述发光元件的第二极 与第三电源线连接。
在一些示例性实施方式中，所述第一晶体管为第一半导体型MOS晶体管，所述第二晶体管、所述第三晶体管和所述驱动晶体管均为第二半导体型MOS晶体管，所述第一半导体型和所述第二半导体型的掺杂类型相反。
在一些示例性实施方式中，在垂直于所述衬底基板的方向上，所述显示基板包括：依次设置在所述衬底基板上的有源层、第一导电层、第二导电层、第三导电层、第四导电层、第五导电层、第六导电层、第七导电层和第八导电层。所述有源层至少包括：所述像素电路的多个晶体管的有源区。所述第一导电层至少包括：所述像素电路的多个晶体管的控制极。所述第二导电层至少包括：所述像素电路的多个晶体管的第一极和第二极、所述第一电源线、所述第二电源线、所述发光控制线和所述数据线。所述第三导电层至少包括：用于连接第一晶体管的第二极、第二晶体管的第二极和驱动晶体管的控制极的第一转接电极，用于连接第一晶体管的控制极和第一扫描信号线的第二转接电极，用于连接第二晶体管的控制极和第二扫描信号线的第三转接电极。所述第四导电层至少包括：所述第一扫描信号线、所述第二扫描信号线、第一子电容的第一极和第二极。所述第五导电层至少包括：第二子电容的第一极。所述第六导电层至少包括：第二子电容的第二极；所述第一子电容和第二子电容并联形成所述第一存储电容。所述第七导电层至少包括：用于连接所述第一存储电容的第一子电容的第一极和所述第二子电容的第二极的第四转接电极、从所述显示区域延伸到所述检测区域的检测引出线；所述检测引出线的第一端与所述驱动晶体管的第二极连接。所述第八导电层至少包括：位于所述显示区域的发光元件的第一极、以及位于所述检测区域的检测电极；所述发光元件的第一极与所述检测引出线的第一端连接，所述检测电极与所述检测引出线的第二端连接。
另一方面，本公开实施提供一种显示装置，包括如上所述的显示基板。
另一方面，本公开实施例提供一种显示基板的制备方法，包括：提供一衬底基板，所述衬底基板包括显示区域以及位于所述显示区域至少一侧的外围区域；在所述衬底基板形成多个子像素、至少一个检测电极以及检测引出线。所述多个子像素设置在所述显示区域，所述多个子像素中的至少一个子 像素包括发光元件和用于驱动所述发光元件的像素电路。所述外围区域包括检测区域，所述至少一个检测电极设置在所述检测区域，所述至少一个检测电极通过检测引出线与所述发光元件的第一极和所述像素电路电连接，以在检测阶段，通过所述检测电极检测所述发光元件的电学性能。
另一方面，本公开实施例提供一种显示基板的检测方法。所述显示基板包括：衬底基板，所述衬底基板包括显示区域以及位于所述显示区域至少一侧的外围区域。所述显示区域设置有多个子像素，所述多个子像素中的至少一个子像素包括发光元件和用于驱动所述发光元件的像素电路。所述检测区域设置有至少一个检测电极，所述至少一个检测电极通过检测引出线与所述发光元件的第一极和所述像素电路电连接。所述外围区域包括检测区域，所述至少一个检测电极与检测电路电连接，所述检测电路包括：第一控制单元、第二控制单元和存储单元。所述第一控制单元，分别与所述检测电极、第一控制端和第一节点连接；所述第二控制单元，分别与第二控制端、第一信号端和第一节点连接；所述存储单元，分别与所述第一节点和第一电源端连接。所述检测方法，包括：在检测阶段的第一子阶段，在检测电路的第一控制端的控制下，断开检测电极和第一节点的连接，在第二控制端的控制下，通过第一信号端向第一节点充电；在检测阶段的第二子阶段，在第二控制端的控制下，断开第一信号端和第一节点的连接，在第一控制端的控制下，通过第一节点向检测电极供电；在检测阶段的第三子阶段，在检测电路的第一控制端的控制下，断开检测电极和第一节点的连接，在第二控制端的控制下，通过第一信号端采集第一节点的电压，并根据从第一信号端采集到的电压，确定所述发光元件的电学性能。
在一些示例性实施方式中，所述根据从第一信号端采集到的电压，确定所述发光元件的电学性能，包括以下至少之一：
在所述发光元件处于发光状态时，根据第三子阶段从第一信号端采样得到的电压，计算所述发光元件的平均电流；根据采集得到的所述电压和计算得到的平均电流，计算出所述发光元件的等效电阻；根据所述发光元件的等效电阻，确定所述发光元件是否处于弱短弱断状态；
在所述发光元件处于熄灭状态时，根据第三子阶段从第一信号端采样得 到的电压，确定所述发光元件的临界导通电压。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开至少一实施例的显示基板的平面示意图；
图2为本公开至少一实施例的显示基板的检测电极连接的显示区域内的子像素的位置示意图；
图3为本公开至少一实施例的显示基板的像素电路和检测电路的示意图；
图4为本公开至少一实施例的显示基板的像素电路的等效电路图；
图5为本公开至少一实施例的显示基板的检测电路的等效电路图；
图6为图5提供的像素电路的工作时序图；
图7为图5提供的检测电路的工作时序图；
图8为一种发光元件的伏安特性的示意图；
图9为本公开至少一实施例的显示基板的像素电路和检测电路的示意图；
图10为本公开至少一实施例的显示基板的像素电路和检测电路的等效电路图；
图11为本公开至少一实施例中形成有源层和第一导电层后的显示基板的示意图；
图12为图11中R-R方向的剖面示意图；
图13为本公开至少一实施例中形成第二导电层后的显示基板的示意图；
图14为图13中R-R方向的剖面示意图；
图15为本公开至少一实施例中形成第三导电层后的显示基板的示意图；
图16为图15中Q-Q方向的剖面示意图；
图17为本公开至少一实施例中形成第四导电层后的显示基板的示意图；
图18为图17中O-O方向的剖面示意图；
图19为本公开至少一实施例中形成第五导电层后的显示基板的示意图；
图20为本公开至少一实施例中形成第六导电层后的显示基板的示意图；
图21为本公开至少一实施例中形成第七导电层后的显示基板的示意图；
图22为图21中P-P方向的剖面示意图；
图23为本公开至少一实施例中形成第八绝缘层后的显示基板的平面示意图；
图24为本公开至少一实施例中形成第八导电层后的显示基板的平面示意图；
图25为本公开至少一实施例的显示装置的示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为一种或多种形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本公开中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个或两个以上的数量。
在本公开中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本公开中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本公开中，沟道区域是指电流主要流过的区域。
在本公开中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本公开中，“源电极”和“漏电极”可以互相调换。
在本公开中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有一种或多种功能的元件等。
在本公开中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，可以包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，可以包括85°以上且95°以下的角度的状态。
在本公开中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
在本公开中，“厚度”指垂直于基底的平面方向上，远离基底的表面距离靠近基底表面的高度。
微型OLED(Micro OLED)显示器通常具有小于3英寸的尺寸，涉及有机发光二极管(OLED)技术和CMOS技术的结合，将OLED阵列制备在包括CMOS电路的硅基基板上。目前微型OLED显示器的设计难以实现对OLED的电学特性(例如，OLED的临界导通电压、漏电流大小、是否存在弱短弱断等)进行监控，难以在出厂测试中发现OLED器件的电学特性不良，而这些不良随着使用时间的增加和环境的影响会逐渐增大，导致出现进行性不良，甚至有些不良会严重影响客户体验。
本公开至少一实施例提供一种显示基板，包括：衬底基板，所述衬底基板包括显示区域以及位于显示区域至少一侧的外围区域。显示区域设置有多个子像素，多个子像素中的至少一个子像素包括发光元件和用于驱动发光元件的像素电路。外围区域包括检测区域，检测区域设置有至少一个检测电极，所述至少一个检测电极通过检测引出线与发光元件的第一极和像素电路电连接，以在检测阶段，通过检测电极检测发光元件的电学性能。
本实施例提供的显示基板，通过检测引出线连接位于显示区域的发光元件的第一极和像素电路以及位于外围区域的检测电极，可以对显示区域内的发光元件的电学性能进行检测，从而给显示基板的不良解析提供支持。
在一些示例性实施方式中，所述至少一个检测电极与设置在外围区域的检测电路电连接，或者，所述至少一个检测电极与设置在外部电路板上的检测电路电连接。换言之，检测电路设置在显示区域以外的非显示区域。
在一些示例性实施方式中，设置在外围区域的检测区域的检测电极与发光元件的第一极和像素电路直接电连接。即，检测电极与像素电路之间通过检测引出线直接电连接，中间没有连接其他晶体管。设置在检测区域的检测 电极相当于像素电路和发光元件的一个信号引出端，从而可以通过设置在外部电路板上的检测电路连接该信号引出端，来检测发光元件的电学性能。
在一些示例性实施方式中，检测电路包括：第一控制单元、第二控制单元和存储单元。第一控制单元，分别与检测电极、第一控制端和第一节点连接，配置为在第一控制端的控制下，通过第一节点向检测电极供电。第二控制单元，分别与第二控制端、第一信号端和第一节点连接，配置为在第二控制端的控制下，通过第一信号端向第一节点充电，或者，通过第一信号端采集第一节点的电压。存储单元，分别与第一节点和第一电源端连接，配置为存储第一节点的电压。
在一些示例性实施方式中，第一控制单元包括：第四晶体管。第四晶体管的控制极与第一控制端连接，第四晶体管的第一极与检测电极连接，第四晶体管的第二极与第一节点连接。第二控制单元包括：第五晶体管。第五晶体管的控制极与第二控制端连接，第五晶体管的第一极与第一信号端连接，第五晶体管的第二极与第一节点连接。存储单元包括：第二存储电容。第二存储电容的第一极与第一节点连接，第二存储电容的第二极与第一电源端连接。然而，本实施例对此并不限定。
在一些示例性实施方式中，检测区域内的相邻检测电极之间的间距范围可以为40微米至85微米。例如，检测区域内的相邻检测电极之间的间距可以为50微米，或者，可以为70微米。然而，本实施例对此并不限定。
在一些示例性实施方式中，外围区域还包括：位于显示区域一侧的绑定区域。检测区域位于显示区域和绑定区域之间。
在一些示例性实施方式中，检测区域与显示区域之间的间距范围为350微米至530微米，检测区域与绑定区域之间的间距范围为350微米至530微米。例如，检测区域位于显示区域和绑定区域之间，且检测区域与显示区域之间的间距为440微米，检测区域与绑定区域之间的间距为440微米。然而，本实施例对此并不限定。例如，检测区域与显示区域之间的间距和检测区域与绑定区域之间的间距可以不同。
在一些示例性实施方式中，检测引出线的线宽范围为3.5微米至35微米。例如，检测引出线的线宽可以为35微米。然而，本实施例对此并不限定。
在一些示例性实施方式中，显示区域为矩形，显示区域被划分为3*3形式的九个矩形子区域。检测区域包括多个检测电极。多个检测电极与九个矩形子区域的中心位置和顶点位置的子像素的发光元件的第一极连接。例如，检测区域的检测电极的数目为25个，九个矩形子区域一共包括9个中心位置和16个顶点位置，则25个检测电极与上述25个位置对应的子像素的发光元件的第一极一一对应连接。然而，本实施例对于检测电极连接的子像素的数目和位置并不限定。
在一些示例性实施方式中，在垂直于衬底基板的方向上，显示基板至少包括：沿着远离衬底基板依次设置的第N-1导电层和第N导电层，N为正整数。第N-1导电层至少包括：从显示区域延伸到检测区域的检测引出线，检测引出线与发光元件对应的像素电路电连接。第N导电层至少包括：位于显示区域的发光元件的第一极、以及位于检测区域的检测电极。检测引出线的第一端与发光元件的第一极连接，检测引出线的第二端与检测电极连接。在本示例性实施方式中，检测电极与发光元件的第一极同层设置，并通过异层设置的检测引出线进行连接。
在一些示例性实施方式中，像素电路包括：驱动子电路、电压传输子电路和数据写入子电路。驱动子电路包括：控制端、第一端和第二端。电压传输子电路配置为响应于发光控制信号，将第一电源线提供的第一电源电压施加到驱动子电路的第一端。数据写入子电路配置为响应于第一扫描信号和第二扫描信号，将数据信号写入驱动子电路的控制端并存储写入的数据信号。驱动子电路配置为在驱动子电路的控制端和第一端的控制下，驱动发光元件发光。
在一些示例性实施方式中，驱动子电路包括：驱动晶体管。数据写入子电路包括：第一晶体管、第二晶体管和第一存储电容。电压传输子电路包括：第三晶体管。驱动晶体管的控制极与驱动子电路的控制端连接，驱动晶体管的第一极与驱动子电路的第一端连接，驱动晶体管的第二极与驱动子电路的第二端连接。第一晶体管的控制极与第一扫描信号线连接，第一晶体管的第一极与数据线连接，第一晶体管的第二极与驱动晶体管的控制极连接。第二晶体管的控制极与第二扫描信号线连接，第二晶体管的第一极与数据线连接， 第二晶体管的第二极与驱动晶体管的控制极连接。第三晶体管的控制极与发光控制线连接，第三晶体管的第一极与第一电源线连接，第三晶体管的第二极与驱动晶体管的第一极连接。第一存储电容的第一极与驱动晶体管的控制极连接，第一存储电容的第二极与第二电源线连接。发光元件的第一极与驱动晶体管的第二极连接，发光元件的第二极与第三电源线连接。
在一些示例性实施方式中，第一晶体管为第一半导体型金属氧化物半导体场效应管(Metal Oxide Semiconductor，MOS)晶体管，第二晶体管、第三晶体管和驱动晶体管均为第二半导体型MOS晶体管，第一半导体型和第二半导体型的掺杂类型相反。例如，第一晶体管为P型晶体管，第二晶体管、第三晶体管和驱动晶体管均为N型晶体管。然而，本实施例对此并不限定。
在一些示例性实施方式中，在垂直于衬底基板的方向上，显示基板包括：依次设置在衬底基板上的有源层、第一导电层、第二导电层、第三导电层、第四导电层、第五导电层、第六导电层、第七导电层和第八导电层。有源层至少包括：像素电路的多个晶体管的有源区。第一导电层至少包括：像素电路的多个晶体管的控制极。第二导电层至少包括：像素电路的多个晶体管的第一极和第二极、第一电源线、第二电源线、发光控制线和数据线。第三导电层至少包括：用于连接第一晶体管的第二极、第二晶体管的第二极和驱动晶体管的控制极的第一转接电极，用于连接第一晶体管的控制极和第一扫描信号线的第二转接电极，用于连接第二晶体管的控制极和第二扫描信号线的第三转接电极。第四导电层至少包括：第一扫描信号线、第二扫描信号线、形成第一存储电容的第一并联电容的第一电极和第二电极。第五导电层至少包括：形成第一存储电容的第二并联电容的第一极。第六导电层至少包括：形成第一存储电容的第二并联电容的第二极。第七导电层至少包括：用于连接第一存储电容的第一并联电容的第一极和第二并联电容的第二极的第四转接电极、从显示区域延伸到检测区域的检测引出线。检测引出线的第一端与驱动晶体管的第二极连接。第八导电层至少包括：位于显示区域的发光元件的第一极、以及位于检测区域的检测电极。发光元件的第一极与检测引出线的第一端连接，检测电极与检测引出线的第二端连接。
在一些示例性实施方式中，像素电路包括：驱动子电路、电压传输子电 路和数据写入子电路。驱动子电路包括：控制端、第一端和第二端。电压传输子电路配置为响应于传输控制信号，将复位电压和第一电源电压分别施加到驱动子电路的第一端。数据写入子电路配置为响应于第一扫描信号和第二扫描信号，将数据信号写入驱动子电路的控制端并存储写入的数据信号。驱动子电路配置为在驱动子电路的控制端和第一端的控制下，驱动发光元件发光。外围区域设置有电压控制电路，电压控制电路与像素电路连接。电压控制电路配置为响应于复位控制信号，向像素电路的电压传输子电路提供复位电压，以及响应于发光控制信号，向电压传输子电路提供第一电源电压。
在一些示例性实施方式中，驱动子电路包括：驱动晶体管，数据写入子电路包括第一晶体管、第二晶体管和第一存储电容，电压传输子电路包括：第三晶体管。电压控制电路包括：第六晶体管和第七晶体管。驱动晶体管的控制极与驱动子电路的控制端连接，驱动晶体管的第一极与驱动子电路的第一端连接，驱动晶体管的第二极与驱动子电路的第二端连接。第一晶体管的控制极与第一扫描信号线连接，第一晶体管的第一极与数据线连接，第一晶体管的第二极与驱动晶体管的控制极连接。第二晶体管的控制极与第二扫描信号线连接，第二晶体管的第一极与数据线连接，第二晶体管的第二极与驱动晶体管的控制极连接。第三晶体管的控制极与传输控制线连接，第三晶体管的第一极与第六晶体管的第二极以及第七晶体管的第一极连接，第三晶体管的第二极与驱动晶体管的第一极连接。第一存储电容的第一极与驱动晶体管的控制极连接，第一存储电容的第二极与第二电源线连接。第六晶体管的控制极与复位控制线连接，第六晶体管的第一极与复位电压线连接。第七晶体管的控制极与发光控制线连接，第七晶体管的第二极与第一电源线连接。发光元件的第一极与驱动晶体管的第二极连接，发光元件的第二极与第三电源线连接。
下面结合附图对本公开实施例及其示例进行详细说明。
本公开至少一实施例提供一种显示基板，例如，该显示基板可以为硅基OLED显示基板，可以应用在虚拟现实设备或增强显示设备中，或者，可以是其他类型的显示基板。本公开实施例对此并不限定。
图1为本公开至少一实施例的显示基板的平面示意图。如图1所示，显 示基板包括：衬底基板10。在一些示例中，衬底基板10可以为硅基衬底基板，该硅基衬底基板可以为体硅基板或者绝缘层上硅(SOI，Silicon-On-Insulator)基板。如图1所示，衬底基板10包括：显示区域100、位于显示区域100周边的外围区域101。外围区域101包括：位于显示区域100一侧的绑定区域103、以及位于显示区域100和绑定区域103之间的检测区域102。
在一些示例性实施方式中，显示区域100设置有阵列分布的多个子像素、多条扫描线和多条数据线。至少一个子像素包括发光元件和用于驱动发光元件的像素电路。多条扫描线和多条数据线彼此交叉在显示区域100中定义出阵列分布的多个像素区，至少一个像素区中设置一个子像素的像素电路。像素电路可以通过硅半导体工艺(例如CMOS工艺)制备在衬底基板上，而发光元件制备在具有像素电路的衬底基板上。像素电路例如为常规的像素电路，例如为2T1C(即两个晶体管和一个电容)像素电路、4T2C、5T1C、7T1C等nTmC(n、m为正整数)像素电路。在不同的实施例中，像素电路还可以进一步包括补偿子电路，补偿子电路可以包括内部补偿子电路或外部补偿子电路，补偿子电路可以包括晶体管、电容等。例如，根据需要，像素电路还可以进一步包括：复位子电路、发光控制子电路等。然而，本实施例对此并不限定。
在一些示例性实施方式中，外围区域101设置有栅极驱动电路和数据驱动电路。栅极驱动电路通过扫描线与像素电路连接以提供至少一种扫描信号，数据驱动电路通过数据线与像素电路连接以提供数据信号。例如，外围区域101还可以设置有控制电路，配置为控制数据驱动电路施加数据信号，以及控制栅极驱动电路施加扫描信号。控制电路的一个示例为时序控制电路，控制电路可以为多种形式，例如，包括存储器和处理器，存储器包括可执行代码，处理器运行该可执行代码以控制数据驱动电路施加数据信号以及控制栅极驱动电路施加扫描信号。然而，本实施例对此并不限定。在一些示例中，由于硅基电路可以实现较高的精度，栅极驱动电路和数据驱动电路可以形成在对应于显示基板的显示区域中，而并不一定位于周边的外围区域。
在一些示例性实施方式中，检测区域102设置有多个检测电极。至少一 个检测电极可以通过检测引出线与显示区域100内对应的子像素的发光元件连接。多个检测电极可以规则排布，例如，阵列排布。多个检测电极可以配置为与柔性线路板(FPC，Flexible Printed Circuit)绑定连接。然而，本实施例对此并不限定。
在一些示例性实施方式中，绑定区域103设置有焊盘组件。例如，焊盘组件包括多个间隔设置的条形的绑定电极，可以配置为与柔性线路板绑定连接。然而，本实施例对此并不限定。
图2为本公开至少一实施例的显示基板的检测电极连接的显示区域内的子像素的位置示意图。在一些示例性实施方式中，可以将矩形的显示区域划分为3*3形式的九个矩形子区域，选取位于每个矩形子区域的中心位置和顶点位置的子像素，作为电学性能的检测位置。如图2所示，由于相邻矩形子区域的顶点位置存在重合，因此，一共可以选取到25个子像素PA(包括九个矩形子区域的9个中心位置对应的子像素以及16个顶点位置对应的子像素)作为检测位置。例如，检测区域可以至少包括25个检测电极，选取的25个子像素PA可以与检测区域内的检测电极一一对应连接，以便通过检测电极检测这些子像素PA的发光元件的电学性能。然而，本实施例对此并不限定。在一些示例中，检测区域包括多个检测电极，显示区域内的所有子像素均可以与检测区域的多个检测电极一一对应连接，或者，显示区域的某一子区域内的全部子像素均可以与检测区域的多个检测电极一一对应连接。
图3为本公开至少一实施例的显示基板的像素电路和检测电路的示意图。本示例性实施例的像素电路和发光元件位于显示区域100，检测电路位于显示区域100至少一侧的外围区域。在一些示例中，检测电路可以设置在外围区域的检测区域内，或者，检测电路可以设置在外部电路板上。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图3所示，本示例性实施例的像素电路可以包括：驱动子电路、电压传输子电路和数据写入子电路。驱动子电路包括：控制端、第一端和第二端。电压传输子电路配置为响应于发光控制信号，将第一电源线提供的第一电源电压施加到驱动子电路的第一端。数据写入子电路配置为响应于第一扫描信号和第二扫描信号，将数据信号写入驱动子电路 的控制端并存储写入的数据信号。驱动子电路配置为在驱动子电路的控制端和第一端的控制下，驱动发光元件发光。
图4为本公开至少一实施例的显示基板的像素电路的等效电路图。如图4所示，在一些示例性实施方式中，驱动子电路可以包括：驱动晶体管M0。数据写入子电路可以包括：第一晶体管M1、第二晶体管M2和第一存储电容C1。电压传输子电路包括第三晶体管M3。驱动晶体管M0的控制极与第一存储电容C1的第一极、第一晶体管M1的第二极、以及第二晶体管M2的第二极连接，驱动晶体管M0的第一极与第三晶体管M3的第二极连接，驱动晶体管M0的第二极与发光元件EL的第一极连接。第一晶体管M1的控制极与第一扫描信号线SL1连接，第一晶体管M1的第一极与数据线DL连接。第二晶体管M2的控制极与第二扫描信号线SL2连接，第二晶体管M2的第一极与数据线DL连接。第三晶体管M3的控制极与发光控制线EM连接，第三晶体管M3的第一极与第一电源线ELVDD连接。第一存储电容C1的第二极与第二电源线VSS连接。发光元件EL的第二极与第三电源线Vcom连接。
图4示意出了像素电路的示例性结构，本领域技术人员容易理解的是，像素电路的实现方式并不限于此，只要能够实现其功能即可。
在本公开实施例中，符号SL1既可以表示第一扫描信号线又可以表示第一扫描信号线提供的第一扫描信号的电平。同样地，符号SL2既可以表示第二扫描信号线又可以表示第二扫描信号线提供的第二扫描信号的电平；符号DL既可以表示数据线又可以表示数据线提供的数据信号的电平；符号EM既可以表示发光控制线又可以表示发光控制线提供的发光控制信号的电平；符号ELVDD既可以表示第一电源线，也可以表示第一电源线提供的第一电源电压；符号VSS既可以表示第二电源线，也可以表示第二电源线提供的第二电源电压；符号Vcom既可以表示第三电源线，也可以表示第三电源线提供的第三电源电压。
在一些示例性实施方式中，驱动晶体管M0配置为在驱动晶体管M0的控制极和第一极的控制下，驱动发光元件EL发光。发光元件EL在驱动晶体管M0的控制下发出不同程度的光。第一晶体管M1配置为响应于第一扫描 信号线SL1提供的第一扫描信号，将数据线DL提供的数据信号写入驱动晶体管M0的控制极。第二晶体管M2配置为响应于第二扫描信号线SL2提供的第二扫描信号，将数据线DL提供的数据信号写入驱动晶体管M0的控制极。第三晶体管M3配置为响应于发光控制线EM提供的发光控制信号，将第一电源线ELVDD提供的第一电源电压施加到驱动晶体管M0的第一极。第一存储电容C1配置为存储写入驱动晶体管M0的控制极的数据信号。
在一些示例性实施方式中，第一电源线ELVDD提供的第一电源电压可以为高电平电压，例如，第一电源电压可以为5V。第二电源线VSS提供的第二电源电压可以为低电平电压。例如，第二电源线VSS提供的第二电源电压可以为负电压或接地电压(一般为0V)。第三电源线Vcom提供的第三电源电压可以为低电平电压。例如，第二电源线VSS提供的第二电源电压和第三电源线Vcom提供的第三电源电压可以相同，例如均为接地电压。
在一些示例性实施方式中，发光元件EL可以为OLED。例如，发光元件EL可以为顶发射结构或底发射结构的OLED，可以发出红光、绿光、蓝光或白光等。例如，发光元件EL可以为微型OLED。然而，本实施例对此并不限定。例如，发光元件EL的第一极为OLED的阳极，第二极为OLED的阴极；或者，第一极可以为OLED的阴极，第二极可以为OLED的阳极。
在一些示例性实施方式中，第一晶体管M1可以采用P型MOS晶体管，第二晶体管M2、第三晶体管M3以及驱动晶体管M0可以采用N型MOS晶体管。然而，本实施例对此并不限定。在一些示例中，第一晶体管M1与第二晶体管M2的类型可以相同，可以根据实际情况来设计确定。
在本示例性实施例中，由于第一晶体管M1和第二晶体管M2采用具有相反半导体型的MOS晶体管，所以第一晶体管M1和第二晶体管M2可以构成具有互补特性的传输门开关。在这种情形中，例如，可以使得提供至第一晶体管M1的第一扫描信号和提供至第二晶体管M2的第二扫描信号彼此互为反相信号，这样就可以保证第一晶体管M1和第二晶体管M2在同一时刻总有一个处于导通状态，从而可以没有电压损失地将数据信号传输至第一存储电容C1，从而可以提高像素电路的可靠性和稳定性。
在一些示例性实施方式中，如图4所示，发光元件EL的第一极可以通 过检测引出线TL和位于外围区域的检测电极(图未示)与检测电路连接。例如，检测电极设置在显示基板的检测区域，检测电路可以设置在显示基板的检测区域；或者，检测电极设置在显示基板的检测区域，检测电路可以设置在外部电路板上。如图3和图4所示，本示例性实施例的检测电路包括：第一控制单元、第二控制单元和存储单元。第一控制单元分别与检测电极、第一控制端Vt1和第一节点N1连接。检测电极通过检测引出线TL与显示区域100的发光元件EL的第一极连接。第二控制单元分别与第二控制端Vt2、第一信号端V0和第一节点N1连接。存储单元分别与第一节点N1和第一电源端(例如提供第二电源电压VSS)连接。其中，第一控制单元配置为在第一控制端Vt1的控制下，通过第一节点N1向检测电极供电。第二控制单元配置为在第二控制端Vt2的控制下，通过第一信号端V0向第一节点N1充电，或者，通过第一信号端V0采集第一节点N1的电压。存储单元配置为存储第一节点N1的电压。
在本示例性实施方式中，第一节点N1并非一定表示实际存在的部件，而是表示电路图中相关电路连接的汇合点。而且，符号Vt1既表示第一控制端又表示第一控制端提供的第一控制信号的电平；同样地，符号Vt2既表示第二控制端又表示第二控制端提供的第二控制信号的电平；符号V0既表示第一信号端又表示第一信号端提供的第一输入信号的电平；符号C2既表示第二存储电容又表示第二存储电容的电容值。
图5为本公开至少一实施例的显示基板的检测电路的等效电路图。在一些示例性实施方式中，如图5所示，第一控制单元包括第四晶体管M4，第二控制单元包括第五晶体管M5，存储单元包括第二存储电容C2。第四晶体管M4的控制极与第一控制端Vt1连接，第四晶体管M4的第一极与检测电极连接，第四晶体管M4的第二极与第一节点N1连接。第五晶体管M5的控制极与第二控制端Vt2连接，第五晶体管M5的第一极与第一信号端V0连接，第五晶体管M5的第二极与第一节点N1连接。第二存储电容C2的第一极与第一节点N1连接，第二存储电容C2的第二极与第一电源端连接。
图5示意出了检测电路的示例性结构，本领域技术人员容易理解的是，检测电路的实现方式并不限于此，只要能够实现其功能即可。
图6为图5提供的像素电路的工作时序图。以像素电路的第一晶体管M1为P型晶体管，像素电路的其余晶体管为N型晶体管为例对像素电路的工作过程进行说明。如图5所示，本实施例涉及的像素电路包括：三个开关晶体管(包括第一晶体管M1、第二晶体管M2和第三晶体管M3)、一个驱动晶体管(包括驱动晶体管M0)、一个电容单元(包括第一存储电容C1)、四个信号输入端(包括数据线DL、第一扫描信号线SL1、第二扫描信号线SL2和发光控制线EM)、以及三个电源端(包括第一电源线ELVDD、第二电源线VSS和第三电源线Vcom)。例如，第一电源线ELVDD提供高电平电压，第二电源线VSS和第三电源线Vcom提供低电平电压，例如均提供接地电压。
在一些示例中，在子像素的显示阶段，图5中的像素电路工作，检测电路不工作。每一帧图像的显示过程包括数据写入阶段PH11以及发光阶段PH12。
在数据写入阶段PH11，第一扫描信号线SL1输入低电平信号，第二扫描信号线SL2输入高电平信号，第一晶体管M1和第二晶体管M2均导通，向驱动晶体管M0的控制极输入数据线DL提供的数据信号，并对第一存储电容C1进行充电。发光控制线EM输入低电平信号，第三晶体管M3截止。
在发光阶段PH12，第一扫描信号线SL1输入高电平信号，第二扫描信号线SL2输入低电平信号，第一晶体管M1和第二晶体管M2均截止。发光控制线EM输入高电平信号，第三晶体管M3导通，向驱动晶体管M0的第一极提供第一电源线ELVDD输入的第一电源电压。驱动晶体管M0为源极跟随器件。在发光元件EL的发光过程中，驱动晶体管M0工作在亚阈值区域，以源跟随形式控制发光元件EL的第一极的电压，从而控制发光元件EL的发光状态。
图7为图5提供的检测电路的工作时序图。以检测电路的第四晶体管M4和第五晶体管M5为N型晶体管为例对检测电路的工作过程进行说明。如图5所示，本实施例涉及的检测电路包括：两个开关晶体管(包括第四晶体管M4和第五晶体管M5)、一个电容单元(包括第二存储电容C2)、三个信号输入端(包括第一控制端Vt1、第二控制端Vt2和第一信号端V0)、 一个信号输出端(包括第一信号端V0)、一个电源端(包括第一电源端)。其中，第一信号端V0既作为信号输出端又作为信号输入端。例如，第一电源端提供负电压(例如，-3.5V)或接地电压。
在一些示例中，在子像素的检测阶段，图5中的像素电路不工作，检测电路工作。如图7所示，至少一个子像素的检测过程包括以下阶段。
在检测阶段的第一子阶段PH21，第一控制端Vt1输入低电平信号，第二控制端Vt2输入高电平信号，第一信号端V0输入高电平信号(例如，高电平直流信号)，第四晶体管M4截止，第五晶体管M5导通。在本阶段，第一节点N1与发光元件EL之间的连接断开，第一信号端V0提供的高电平直流信号可以给第二存储电容C2充电，直至充到高电平VGH。
在检测阶段的第二子阶段PH22，第一控制端Vt1输入高电平信号，第二控制端Vt2输入低电平信号，第四晶体管M4导通，第五晶体管M5截止。在本阶段，第一节点N1与发光元件EL之间导通，第二存储电容C2可以给像素电路的发光元件EL快速放电，发光元件EL发光并逐渐变暗。
在一些示例中，随着第二存储电容C2放电时长的增加，第二存储电容C2给发光元件EL提供的电压逐渐降低，直至降低到发光元件EL的临界导通电压以下，发光元件EL逐渐变暗直至不再发光。在一些示例中，可以根据发光元件EL的起亮电压确定第二子阶段的扫描时长。例如，发光元件的起亮电压为4V，第一电源端提供的电压为-3.5V，则可以设定第二存储电容C2放电至0.5V所需的时长为扫描时长。在一些示例中，在检测发光元件的平均电流和等效电阻时，可以控制第二子阶段的放电时长小于或等于扫描时长；在检测发光元件的临界导通电压时，可以控制第二子阶段的放电时长大于扫描时长。
在检测阶段的第三子阶段PH23，第一控制端Vt1输入低电平信号，第二控制端Vt2输入高电平信号，第四晶体管M4截止，第五晶体管M5导通。在本阶段，第一节点N1与发光元件EL之间的连接断开，第一节点N1与第一信号端V0导通，通过第一信号端V0对第二存储电容C2的电压进行采样。
在一些示例中，在第二子阶段的发光元件EL仍处于发光状态时，切换至第三子阶段，并通过第一信号端V0采样到第二存储电容C2的电压，记为 Vc1，然后可以计算出发光元件EL的平均电流Iavg＝(VGH-Vc1)*C2/t，t表示第二子阶段PH22的放电时长，C2表示第二存储电容的电容值，VGH表示在第一子阶段将第二存储电容充至的高电压。然后，可以计算出发光元件EL的等效电阻R＝Vc1/Iavg。
在一些示例中，在第二子阶段的发光元件EL处于完全熄灭状态时，切换至第三子阶段，并通过第一信号端V0采样到第二存储电容C2的电压，记为Vc2，此时，可以计算出发光元件EL的临界导通电压(即阈值电压)Vth＝Vc2。
图8为一种发光元件的伏安(V-A)特性的示意图。如图8所示，将发光元件的关态电流Ioff到开态电流Ion的区间近似定义为线性区进行计算，开态电流Ion＝10-6eA，即为最大电流Imax，关态电流Ioff＝10-13eA。在一些示例中，以两个数量级的幅度为例定义弱短弱断状态，则当电流大于10-4eA时，发光元件处于弱短状态，当电流小于10-11eA且大于10-13eA时，发光元件处于弱断状态。基于以上结果，可以计算得到发光元件处于弱短状态时，发光元件的等效电阻R的范围如下：R<Vth/(Ion*100)；发光元件处于弱短状态时，发光元件的等效电阻R的范围如下：Vth/Ioff>R>Vth/(Ioff*100)。例如，发光元件的阈值电压Vth为9.5V，则在发光元件的等效电阻R<95千欧(KΩ)时，发光元件处于弱短状态；在发光元件的等效电阻处于以下范围：95000000兆欧(MΩ)>R>95000MΩ时，发光元件处于弱断状态。基于此，通过第三子阶段采样到的电压，可以计算发光元件的等效电阻，然后根据发光元件的等效电阻可以检测发光元件是否处于弱断弱短状态。
在一些示例性实施方式中，在检测阶段的第三子阶段PH23之后，可以进入检测阶段的第四子阶段PH24。在第四子阶段PH24，第一控制端Vt1输入低电平信号，第二控制端Vt2输入高电平信号，第四晶体管M4截止，第五晶体管M5导通。在本阶段，第一节点N1与发光元件EL之间的连接断开，第一节点N1与第一信号端V0导通，第一信号端V0提供接地电压，通过第一信号端V0对第二存储电容C2进行放电复位。
在一些示例性实施方式中，在检测阶段的第四子阶段PH24之后，可以重复第一子阶段，例如，重新检测发光元件的电学性能；或者，在第四子阶段PH24之后，可以退出检测阶段进入显示阶段。然而，本实施例对此并不 限定。
本示例性实施方式提供的显示基板中，检测电路通过检测区域设置的检测电极经由检测引出线与显示区域的子像素的发光元件连接，可以对显示区域内不同位置的子像素的发光元件的电学性能进行检测，从而给显示基板的不良解析提供支持。
图9为本公开至少一实施例的显示基板的像素电路和检测电路的示意图。在一些示例性实施方式中，如图9所示，本示例性实施例的像素电路包括：驱动子电路、电压传输子电路和数据写入子电路。驱动子电路包括：控制端、第一端和第二端。电压传输子电路配置为响应于传输控制信号，将复位电压和第一电源电压分别施加到所述驱动子电路的第一端。数据写入子电路配置为响应于第一扫描信号和第二扫描信号，将数据信号写入驱动子电路的控制端并存储写入的数据信号。驱动子电路配置为在驱动子电路的控制端和第一端的控制下，驱动发光元件发光。外围区域设置有电压控制电路，电压控制电路与像素电路连接。电压控制电路配置为响应于复位控制信号，向像素电路的电压传输子电路提供复位电压，以及响应于发光控制信号，向电压传输子电路提供第一电源电压。
图10为本公开至少一实施例的显示基板的像素电路和检测电路的等效电路图。在一些示例性实施方式中，如图10所示，驱动子电路包括：驱动晶体管M0。数据写入子电路包括第一晶体管M1、第二晶体管M2和第一存储电容C1。电压传输子电路包括：第三晶体管M3。电压控制电路包括：第六晶体管M6和第七晶体管M7。驱动晶体管M0的控制极与驱动子电路的控制端连接，驱动晶体管M0的第一极与驱动子电路的第一端连接，驱动晶体管M0的第二极与驱动子电路的第二端连接。第一晶体管M1的控制极与第一扫描信号线SL1连接，第一晶体管M1的第一极与数据线Dl连接，第一晶体管M1的第二极与驱动晶体管M0的控制极连接。第二晶体管M2的控制极与第二扫描信号线SL2连接，第二晶体管M2的第一极与数据线DL连接，第二晶体管M2的第二极与驱动晶体管M0的控制极连接。第三晶体管M3的控制极与传输控制线VT连接，第三晶体管M3的第一极与第六晶体管M6的第二极以及第七晶体管M7的第一极连接，第三晶体管M3的第二极与驱 动晶体管M0的第一极连接。第一存储电容C1的第一极与驱动晶体管M0的控制极连接，第一存储电容C1的第二极与第二电源线VSS连接。第六晶体管M6的控制极与复位控制线RS连接，第六晶体管M6的第一极与复位电压线Vinit连接。第七晶体管M7的控制极与发光控制线EM连接，第七晶体管M7的第二极与第一电源线ELVDD连接。发光元件EL的第一极与驱动晶体管M0的第二极连接，发光元件EL的第二极与第三电源线Vcom连接。
在一些示例性实施方式中，第一晶体管M1和第七晶体管M7为P型晶体管，驱动晶体管M0、第二晶体管M2、第三晶体管M3及第六晶体管M6为N型晶体管。然而，本实施例对此并不限定。
在一些示例性实施方式中，以像素电路的第一晶体管M1和电压控制电路的第七晶体管M7为P型晶体管，像素电路的其余晶体管为N型晶体管为例对像素电路的工作过程进行说明。例如，子像素的显示阶段，图10中的像素电路工作，检测电路不工作。每一帧图像的显示过程包括复位阶段、数据写入阶段、发光阶段以及非发光阶段。
在复位阶段，复位控制线RS输入高电平信号，第六晶体管M6导通；传输控制线VT输入高电平信号，第三晶体管M3导通；发光控制线EM输入高电平信号，第七晶体管M7截止。第一扫描信号线SL1输入高电平信号，第二扫描信号线SL2输入低电平信号，第一晶体管M1和第二晶体管M2均截止。在复位阶段，利用复位电压线Vinit提供的低电位(例如，接地电压)对发光元件EL进行复位。
在数据写入阶段，第一扫描信号线SL1输入低电平信号，第二扫描信号线SL2输入高电平信号，第一晶体管M1和第二晶体管M2均导通，向驱动晶体管M0的控制极输入数据线DL提供的数据信号，并对第一存储电容C1进行充电。复位控制线RS输入低电平信号，第六晶体管M6截止，发光控制线EM输入高电平信号，第七晶体管M7截止。传输控制线VT输入低电平信号，第三晶体管M3截止。
在发光阶段，第一扫描信号线SL1输入高电平信号，第二扫描信号线SL2输入低电平信号，第一晶体管M1和第二晶体管M2均截止。发光控制线EM输入低电平信号，第七晶体管M7导通，复位控制线RS输入低电平信号， 第六晶体管M6截止。传输控制线VT输入高电平信号，第三晶体管M3导通。通过第六晶体管M6和第三晶体管M3将第一电源线ELVDD提供的第一电源电压施加到驱动晶体管M0的第一极。
在非发光阶段，传输控制线VT输入低电平信号，第三晶体管M3截止，使第一电源电压不能被施加到驱动晶体管M0的第一极，以使发光元件EL停止发光。
图9和图10中的检测电路的结构和工作方式可以参照前述实施例的说明，故于此不再赘述。
下面通过显示基板的制备过程的示例说明本实施例的技术方案。本实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，是已知的成熟的制备工艺。沉积可采用溅射、蒸镀、化学气相沉积等已知工艺，涂覆可采用已知的涂覆工艺，刻蚀可采用已知的方法，在此不做限定。在本实施例的描述中，需要理解的是，“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺或光刻工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”还需构图工艺或光刻工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺或光刻工艺后的“层”中包含至少一个“图案”。本公开中所说的“A和B同层设置”是指，A和B通过同一次构图工艺同时形成。
在一些示例性实施方式中，以显示区域设置的子像素具有如图5所示的像素电路、检测区域设置有通过检测引出线与子像素连接的检测电极为例进行说明。在本示例中，检测电路设置在外部电路板上，检测电路通过检测电极和检测引出线与显示区域内对应的子像素的发光元件连接。下面以显示区域内的像素电路的第一晶体管M1为P型晶体管，第二晶体管M2、第三晶体管M3以及驱动晶体管M0为N型晶体管为例进行说明。
本示例性实施例的显示基板的制备过程可以包括以下步骤。
(1)、在衬底基板上形成有源层和第一导电层。
在一些示例性实施方式中，提供硅基衬底基板，例如其材料为P型单晶 硅。N型晶体管(例如驱动晶体管)可以直接在P型衬底上制作，也即该P型衬底充当该N型晶体管的沟道区，有利于发挥NMOS器件高速的优势，提高了电路性能。如图11所示，在P型硅基衬底基板上进行N型掺杂，形成N型阱区WL1，以作为第一晶体管M1(即P型晶体管)的衬底。
在一些示例性实施方式中，在上述衬底基板10上形成第一绝缘层501，接着通过构图工艺在第一绝缘层501上形成第一导电层，如图11和图12所示。例如，通过热氧化法在衬底基板上形成第一绝缘层，第一绝缘层的材料可以为硅的氮化物、氧化物或氮氧化物；然后，在第一绝缘层上形成第一导电材料层，对该第一导电材料层进行光刻工艺形成第一导电层。第一导电层的材料可以为多晶硅材料。第一绝缘层501可以称为栅绝缘层。如图11所示，第一导电层至少包括：第一晶体管M1的控制极113、第二晶体管M2的控制极123、第三晶体管M3的控制极133和驱动晶体管M0的控制极143。
在一些示例性实施方式中，对形成第一导电层的衬底基板进行重掺杂，以在衬底基板上形成用于电连接的掺杂区域。如图11和图12所示，用于电连接的掺杂区域包括：第一晶体管M1的有源区110的源极区110S和漏极区110D、第二晶体管M2的有源区120的源极区和漏极区、第三晶体管M3的有源区130的源极区和漏极区、驱动晶体管M0的有源区140的源极区140S和漏极区140D、N型阱区WL1内的第一接触区301、P型衬底内的第二接触区302。驱动晶体管M0的有源区140沿第一方向X延伸，第一晶体管M1的有源区110、第二晶体管M2的有源区120和第三晶体管M3的有源区130沿第二方向Y延伸，且第一方向X垂直于第二方向Y。第一晶体管M1、第二晶体管M2和第三晶体管M3沿着第一方向X依次排布，第一晶体管M1、第二晶体管M2和第三晶体管M3沿第二方向Y排布在驱动晶体管M0的一侧。
例如，在掺杂过程中，可以分别进行N型掺杂和P型掺杂，例如以形成N型晶体管的源极区和漏极区以及P型晶体管的源极区和漏极区。在进行N型掺杂工艺时，可以形成阻挡层将不进行N型掺杂的区域遮挡；在进行P型掺杂工艺时，可以形成阻挡层将不进行P型掺杂的区域遮挡。阻挡层可以是硅的氮化物、氧化物或者氮氧化物，或者可以是光刻胶材料。待掺杂工艺结 束后，该阻挡层可以保留在显示基板中，或者也可以去除。该N型掺杂工艺例如可以为离子注入工艺，掺杂元素例如可以是硼元素。该P型掺杂工艺例如可以为离子注入工艺，掺杂元素例如可以是磷元素。
(2)、在衬底基板上依次形成第二绝缘层和第二导电层。
在一些示例性实施方式中，在上述衬底基板10上形成第二绝缘层502，接着在第二绝缘层502上形成第二导电层，如图13和图14所示。第二导电层502的材料可以为金属材料。第二导电层502还可以称为第一金属层。第二绝缘层502上开设有多个过孔，多个过孔至少包括：第一过孔V1至第十过孔V10。多个过孔内的第一绝缘层501和第二绝缘层502均被去除。
如图13所示，第二导电层至少包括：第一电源线ELVDD、第四电源线VDD、接地线GND、发光控制线EM、数据线DL、第一晶体管M1的第一极111和第二极112、第二晶体管M2的第一极121和第二极122、第三晶体管M3的第一极131和第二极132、驱动晶体管M0的第一极141和第二极142。在本示例中，第二电源线VSS和第三电源线Vcom均提供接地电压，即第二电源电压和第三电源电压均可以由接地线GND提供。第一晶体管M1的第二极112和第二晶体管M2的第二极122为一体结构。第一晶体管M1的第一极111、第二晶体管M2的第一极121和数据线DL为一体结构。第三晶体管M3的第一极131与第一电源线ELVDD为一体结构，第三晶体管M3的第二极132与驱动晶体管M0的第一极141与一体结构。第四电源线VDD提供高电平电压，例如，5V。
在一些示例性实施方式中，如图13和图14所示，第一晶体管M1的第一极111通过第一过孔V1与第一晶体管M1的有源区110的源极区110S电连接，第一晶体管M2的第二极112通过第二过孔V2与第一晶体管M1的有源区110的漏极区110D电连接。第二晶体管M2的第一极121通过第三过孔V3与第二晶体管M2的有源区110的漏极区电连接，第二晶体管M2的第二极122通过第四过孔V4与第二晶体管M2的有源区110的漏极区电连接。第三晶体管M3的第一极131通过第五过孔V5与第三晶体管M3的有源区130的源极区电连接，第三晶体管M3的第二极132通过第六过孔V6与第三晶体管M3的有源区130的漏极区电连接。驱动晶体管M0的第一极141通 过第七过孔V7与驱动晶体管M0的有源区140的漏极区140D电连接，驱动晶体管M0的第二极142通过第八过孔V8与驱动晶体管M0的有源区140的源极区140S电连接。
在一些示例性实施方式中，如图13所示，第一电源线ELVDD在衬底基板上的正投影位于第四电源线VDD在衬底基板上的正投影和数据线DL在衬底基板上的正投影之间，发光控制线EM在衬底基板上的正投影位于第四电源线VDD在衬底基板上的正投影远离第一电源线ELVDD的一侧。第一电源线ELVDD、第四电源线VDD、数据线DL和发光控制线EM的部分延伸方向平行于第一方向X。第四电源线VDD在沿第一方向X延伸时，有一个弯折区域；另外，发光控制线EM在沿第一方向X延伸时，也有一个弯折区域，且第四电源线VDD与发光控制线EM的弯折方向不同。采用这种走线方式可以给第一晶体管M1的第二极112留出布局空间。
在一些示例性实施方式中，如图13所示，第四电源线VDD通过第九过孔V9与第一接触区301连接，接地线GND通过第十过孔V10与第二接触区302连接。通过第四电源线VDD连接第一接触区301，可以对第一晶体管M1所在的N型阱区WL1进行偏置，通过接地线GND连接第二接触区302，可以对第二晶体管M2所在的P型衬底进行偏置。在本示例中，通过将P型衬底进行低压偏置，N型阱区301进行高压偏置，可以使得二者之间的寄生PN结反偏，对器件进行电性隔离，并降低器件之间的寄生效应，提高电路的稳定性。
(3)、在衬底基板上依次形成第三绝缘层和第三导电层。
在一些示例性实施方式中，在形成前述结构的衬底基板10上依次形成第三绝缘层503和第三导电层，如图15和图16所示。第三绝缘层503上设置有多个过孔，多个过孔至少包括：暴露出第一晶体管M1的第二极112的第十一过孔V11、暴露出驱动晶体管M0的控制极140的第十二过孔V12、暴露出第一晶体管M1的控制极113的第十三过孔V13、暴露出第二晶体管M2的控制极123的第十四过孔V14。
如图15所示，第三导电层至少包括：第一转接电极401、第二转接电极402和第三转接电极403。第一转接电极401、第二转接电极402和第三转接 电极403的延伸方向平行于第二方向Y。第一转接电极401通过第十一过孔V11与第一晶体管M1的第二极112连接，通过第十二过孔V12与驱动晶体管M0的控制极143连接，实现第一晶体管M1的第二极112、第二晶体管M2的第二极122和驱动晶体管M0的控制极143之间的电性连接。第二转接电极402通过第十三过孔V13与第一晶体管M1的控制极113连接。第三转接电极403通过第十四过孔V14与第二晶体管M2的控制极123连接。
(4)、在衬底基板上依次形成第四绝缘层和第四导电层。
在一些示例性实施方式中，在形成前述结构的衬底基板10上依次形成第四绝缘层504和第四导电层，如图17和图18所示。第四绝缘层504上设置有多个过孔，多个过孔至少包括：暴露出驱动晶体管M0的控制极143的第十五过孔V15、暴露出第二转接电极402的第十六过孔V16和暴露出第三转接电极403的第十七过孔V17。第四导电层至少包括：第一扫描信号线SL1、第二扫描信号线SL2、以及第一电极201和第二电极202。第一电极201包括多个条状电极，第二电极202包括多个条状电极，第一电极201的多个条状电极和第二电极202的多个条状电极相互交替排布，且第一电极201和第二电极202以及之间的间隔部分形成第一子电容。第一电极201作为第一子电容的第一极，第二电极202作为第一子电容的第二极。例如，第一子电容为第一存储电容C1的一部分，第一子电容和下文中的第二子电容并联从而形成第一存储电容C1。
在一些示例性实施方式中，如图17所示，第二扫描信号线SL2在衬底基板的正投影与数据线DL在衬底基板的正投影至少部分重叠。本示例性实施方式中，通过使得第二扫描信号线SL2与数据线DL在垂直于衬底基板的方向上重叠，可以使得该数据线DL不占用额外的布局面积，从而可以进一步减小显示基板所占用的布局面积，更有利于实现高PPI。
在一些示例性实施方式中，如图17所示，第一电源线ELVDD在衬底基板的正投影位于第二扫描信号线SL2在衬底基板的正投影和发光控制线EM在衬底基板的正投影之间。由于第一电源线ELVDD传输的第一电源电压为直流信号，而第二扫描信号线SL2传输的第二扫描信号以及发光控制线EM传输的发光控制信号均为跳变信号，所以采用上述排布方式可以有效屏蔽第 二扫描信号与发光控制信号之间的相互干扰。
(5)、在衬底基板上依次形成第五绝缘层、第五导电层、第六绝缘层、第六导电层、第七绝缘层和第七导电层。
在一些示例性实施方式中，在形成前述结构的衬底基板上依次形成第五绝缘层505、第五导电层、第六绝缘层506、第六导电层、第七绝缘层507和第七导电层，如图19至图22所示。
如图19所示，第五导电层至少包括第三电极203，例如，第三电极203为一个面状电极，第三电极203充当第二子电容的第一极。
如图20所示，第六导电层至少包括第四电极204，例如，第四电极204为一个面状电极，第四电极204充当第二子电容的第二极。第三电极203和第四电极204以及之间的间隔部分形成第二子电容C12。
如图21和图22所示，第七绝缘层至少包括：暴露出第四电极204的第十八过孔V18、暴露出第一电极201的第十九过孔V19、暴露出驱动晶体管M0的第二极142的第二十过孔V20。第七导电层至少包括：第四转接电极205以及检测引出线TL。第四转接电极205通过第十八过孔V18与第四电极204连接，通过第十九过孔V19与第一电极201连接，实现驱动晶体管140的控制极143、第一子电容的第一极和第二子电容的第二极之间的电性连接。第二电极202和第三电极203被配置为接收第二电源电压，例如，接地电压。
如图21和图22所示，检测引出线TL通过第二十过孔V20与驱动晶体管M0的第二极142连接。检测引出线TL从显示区域延伸到检测区域，以便与检测区域内的检测电极电连接。
(6)、在衬底基板上形成第八绝缘层和第八导电层。
在一些示例性实施方式中，在形成前述结构的衬底基板上依次形成第八绝缘层和第八导电层，如图23和图24所示。图23和图24中示意了显示区域和检测区域的平面结构。如图23所示，显示区域100的第八绝缘层至少设置有多个第二十一过孔V21，检测区域102的第八绝缘层至少设置有多个第二十二过孔V22。多个第二十一过孔V21和第二十二过孔V22内的第八绝缘层被去掉。显示区域100内的第二十一过孔V21和检测区域102内的第二十 二过孔V22一一对应。第二十一过孔V21暴露出检测引出线TL在显示区域100内的第一端，第二十二过孔V22暴露出检测引出线TL在检测区域102内的第二端。在一些示例中，如图23所示，第二十一过孔V21和第二十二过孔V22在衬底基板上的投影可以为矩形。然而，本实施例对此并不限定。例如，第二十一过孔和第二十二过孔在衬底基板上的投影的形状可以相同或不同，例如可以均为圆形或椭圆形或正方形。
在一些示例性实施方式中，在检测区域102内，多个第二十二过孔V22可以按照阵列排布，例如，可以排布为两行。然而，本实施例对此并不限定。
在一些示例性实施方式中，在显示区域100内，沿第一方向X，相邻两个第二十一过孔V21之间的间距a的范围可以为2330微米至3500微米，例如，间距a可以为2915微米。沿第二方向Y，相邻两个第二十一过孔V21之间的间距b的范围可以为1330微米至2000微米，例如，间距b可以为1656微米。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图23所示，检测引出线TL可以由多个直线段连接形成，例如显示区域内的检测引出线可以按照避免影响显示区域的显示效果的排布方式延伸至检测区域。然而，本实施例对此并不限定。例如，检测引出线可以由直线段和曲线段连接形成。在一些示例中，检测引出线的线宽范围可以为3.5微米至35微米，例如可以为35微米。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图24所示，第八导电层至少包括：位于显示区域100的发光元件的第一极601、位于检测区域102的检测电极602以及位于绑定区域103的绑定电极(图未示)。发光元件的第一极601可以为阳极，第一极601可以呈六边形，且规则排布。显示区域100内的第一极601通过第二十一过孔V21与检测引出线TL的第一端连接，检测区域102内的检测电极602通过第二十二过孔V22与检测引出线TL的第二端连接，从而通过检测引出线TL实现检测电极602与发光元件以及发光元件对应的像素电路之间的电性连接。
在一些示例性实施方式中，如图24所示，在检测区域102内规则排布多个检测电极602。至少一个检测电极602可以呈正方形，例如，检测电极602 的边长c的范围可以55微米至85微米，例如边长c为70微米。在检测区域102内，沿第一方向X，相邻两个检测电极602之间的间距e的范围可以为40微米至60微米，例如间距e可以为50微米。沿第二方向Y，相邻两个检测电极602之间的间距f的范围可以为55微米至85微米，例如，间距f可以为70微米。然而，本实施例对此并不限定。例如，检测电极可以为矩形或圆形等。
在一些示例性实施方式中，如图24所示，沿第二方向Y，显示区域100与检测区域102之间的间距d1的范围可以为350微米至530微米，例如，间距d1可以为440微米。检测区域102与绑定区域103之间的间距d2的范围可以为350微米至530微米，例如间距d2可以为440微米。例如，间距d1可以等于间距d2。然而，本实施例对此并不限定。
(7)、在衬底基板上依次形成像素定义层、发光功能层、阴极以及封装层。
在一些示例性实施方式中，在形成前述结构的衬底基底上涂覆像素定义薄膜，通过掩膜、曝光和显影工艺形成像素定义层(PDL，Pixel Define Layer)图案，像素定义层形成在显示区域的子像素中，子像素中的像素定义层形成有暴露出阳极的像素开口。随后，在前述形成的像素开口内形成发光功能层，发光功能层层与发光元件的阳极连接。随后，沉积阴极薄膜，通过构图工艺对阴极薄膜进行构图，形成阴极图案，阴极分别与发光功能层和第三电源线Vcom连接。随后，在阴极上形成封装层，封装层可以包括无机材料/有机材料/无机材料的叠层结构。
在一些示例中，像素定义层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)或氮氧化硅(SiON)等无机材料。阳极可以采用氧化铟锡(ITO)或氧化铟锌(IZO)等透明导电材料。阴极可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或更多种，或采用上述金属中任意一种或多种制成的合金。然而，本实施例对此并不限定。例如，阳极可以采用金属等反射材料，阴极可以采用透明导电材料。
本公开实施例所示结构及其制备过程仅仅是一种示例性说明。在一些示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。 例如，像素电路可以是3T1C或7T1C设计。再如，第一存储电容的第一极可以与驱动晶体管的控制极同层且一体形成，第一存储电容的第二极可以形成在衬底基板中。又如，检测电路可以设置在检测区域。然而，本公开实施例在此不做任何限定。
本公开实施例的制备工艺利用目前成熟的制备设备即可实现，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本实施例提供的显示基板中，显示区域的子像素的发光元件通过检测引出线和检测区域的检测电极连接，通过检测电极与检测电路连接，通过检测电路实现发光元件的电学性能的检测，从而对显示基板的不良解析提供支持。
本公开至少一实施例还提供一种显示基板的制备方法，包括：提供一衬底基板，衬底基板包括显示区域以及位于显示区域一侧的外围区域。在衬底基板形成多个子像素、至少一个检测电极以及检测引出线。其中，多个子像素设置在显示区域，多个子像素中的至少一个子像素包括发光元件和用于驱动所述发光元件的像素电路。外围区域包括检测区域，至少一个检测电极设置在检测区域，至少一个检测电极通过检测引出线与发光元件的第一极和对应的像素电路电连接，以在检测阶段，通过检测电极检测发光元件的电学性能。
在一些示例性实施方式中，在衬底基板形成多个子像素、至少一个检测电极以及检测引出线，包括：依次在衬底基板上形成有源层、第一导电层、第二导电层、第三导电层、第四导电层、第五导电层、第六导电层、第七导电层和第八导电层。有源层至少包括：像素电路的多个晶体管的有源区。第一导电层至少包括：像素电路的多个晶体管的控制极。第二导电层至少包括：像素电路的多个晶体管的第一极和第二极、第一电源线、第二电源线、发光控制线和数据线。第三导电层至少包括：用于连接第一晶体管的第二极、第二晶体管的第二极和驱动晶体管的控制极的第一转接电极，用于连接第一晶体管的控制极和第一扫描信号线的第二转接电极，用于连接第二晶体管的控制极和第二扫描信号线的第三转接电极。第四导电层至少包括：第一扫描信号线、第二扫描信号线、第一子电容的第一极和第二极。第五导电层至少包 括：第二子电容的第一极。第六导电层至少包括：第二子电容的第二极；第一子电容和第二子电容并联形成第一存储电容。第七导电层至少包括：用于连接第一存储电容的第一并联子电容的第一极和第二并联子电容的第二极的第四转接电极、从显示区域延伸到检测区域的检测引出线；检测引出线的第一端与驱动晶体管的第二极连接。第八导电层至少包括：位于显示区域的发光元件的第一极、以及位于检测区域的检测电极。发光元件的第一极与检测引出线的第一端连接，检测电极与检测引出线的第二端连接。
关于本实施例的制备方法可以参照前述实施例的说明，故于此不再赘述。
本公开至少一实施例提供一种显示基板的检测方法。显示基板包括：衬底基板，衬底基板包括显示区域以及位于显示区域一侧的外围区域。显示区域设置有多个子像素，多个子像素中的至少一个子像素包括发光元件和用于驱动所述发光元件的像素电路。外围区域包括检测区域，检测区域设置有至少一个检测电极，至少一个检测电极通过检测引出线与发光元件的第一极和像素电路电连接。至少一个检测电极与检测电路电连接，检测电路包括：第一控制单元、第二控制单元和存储单元。第一控制单元，分别与检测电极、第一控制端和第一节点连接。第二控制单元，分别与第二控制端、第一信号端和第一节点连接。存储单元，分别与第一节点和第一电源端连接。检测方法包括：在检测阶段的第一子阶段，在检测电路的第一控制端的控制下，断开检测电极和第一节点的连接，在第二控制端的控制下，通过第一信号端向第一节点充电；在检测阶段的第二子阶段，在检测电路的第二控制端的控制下，断开第一信号端和第一节点的连接，在第一控制端的控制下，通过第一节点向检测电极供电；在检测阶段的第三子阶段，在检测电路的第一控制端的控制下，断开检测电极和第一节点的连接，在第二控制端的控制下，通过第一信号端采集第一节点的电压，并根据从第一信号端采集到的电压，确定发光元件的电学性能。
在一些示例性实施方式中，根据从第一信号端采集到的电压，确定发光元件的电学性能，包括以下至少之一：
在发光元件处于发光状态时，根据第三子阶段从第一信号端采样得到的电压，计算发光元件的平均电流；根据采集得到的电压和计算得到的平均电 流，计算出发光元件的等效电阻；根据发光元件的等效电阻，确定发光元件是否处于弱短弱断状态；
在发光元件处于熄灭状态时，根据第三子阶段从第一信号端采样得到的电压，确定发光元件的临界导通电压。
关于本实施例的检测方法可以参照前述实施例的说明，故于此不再赘述。
图25为本公开至少一实施例的显示装置的示意图。如图25所示，本实施例提供一种显示装置91，包括：显示基板910。显示基板910为前述实施例提供的显示基板。其中，显示基板910可以为微型OLED显示基板。显示装置91可以为：OLED面板、OLED电视、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。然而，本实施例对此并不限定。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (20)

  1. 一种显示基板，包括：
    衬底基板，所述衬底基板包括显示区域以及位于所述显示区域至少一侧的外围区域；
    所述显示区域设置有多个子像素，所述多个子像素中的至少一个子像素包括发光元件和用于驱动所述发光元件的像素电路；
    所述外围区域包括检测区域，所述检测区域设置有至少一个检测电极，所述至少一个检测电极通过检测引出线与所述发光元件的第一极和所述像素电路电连接，以在检测阶段，通过所述检测电极检测所述发光元件的电学性能。
  2. 根据权利要求1所述的显示基板，其中，所述至少一个检测电极与设置在所述外围区域的检测电路电连接，或者，所述至少一个检测电极与设置在外部电路板上的检测电路电连接。
  3. 根据权利要求2所述的显示基板，其中，所述检测电路包括：第一控制单元、第二控制单元和存储单元；
    所述第一控制单元，分别与所述检测电极、第一控制端和第一节点连接，配置为在所述第一控制端的控制下，通过所述第一节点向所述检测电极供电；
    所述第二控制单元，分别与第二控制端、第一信号端和第一节点连接，配置为在所述第二控制端的控制下，通过所述第一信号端向所述第一节点充电，或者，通过所述第一信号端采集所述第一节点的电压；
    所述存储单元，分别与所述第一节点和第一电源端连接，配置为存储所述第一节点的电压。
  4. 根据权利要求3所述的显示基板，其中，所述第一控制单元包括：第四晶体管，所述第四晶体管的控制极与第一控制端连接，所述第四晶体管的第一极与所述检测电极连接，所述第四晶体管的第二极与所述第一节点连接；
    所述第二控制单元包括：第五晶体管，所述第五晶体管的控制极与第二控制端连接，所述第五晶体管的第一极与第一信号端连接，所述第五晶体管的第二极与所述第一节点连接；
    所述存储单元包括：第二存储电容，所述第二存储电容的第一极与所述第一节点连接，所述第二存储电容的第二极与第一电源端连接。
  5. 根据权利要求1所述的显示基板，其中，所述检测区域内的相邻检测电极之间的间距范围为40微米至85微米。
  6. 根据权利要求1所述的显示基板，其中，所述外围区域还包括：位于所述显示区域一侧的绑定区域，所述检测区域位于所述显示区域和绑定区域之间。
  7. 根据权利要求6所述的显示基板，其中，所述检测区域与所述显示区域之间的间距范围可以为350微米至530微米，所述检测区域与所述绑定区域之间的间距范围可以为350微米至530微米。
  8. 根据权利要求1所述的显示基板，其中，所述检测引出线的线宽范围为3.5微米至35微米。
  9. 根据权利要求1所述的显示基板，其中，所述显示区域为矩形，所述显示区域被划分为3*3形式的九个矩形子区域，所述检测区域包括多个检测电极，所述多个检测电极与所述九个矩形子区域的中心位置和顶点位置的子像素的发光元件的第一极连接。
  10. 根据权利要求1所述的显示基板，其中，在垂直于所述衬底基板的方向上，所述显示基板至少包括：沿着远离所述衬底基板依次设置的第N-1导电层和第N导电层，N为正整数；
    所述第N-1导电层至少包括：从所述显示区域延伸到所述检测区域的检测引出线，所述检测引出线与所述发光元件对应的像素电路电连接；
    所述第N导电层至少包括：位于所述显示区域的发光元件的第一极、以及位于所述检测区域的检测电极；所述检测引出线的第一端与所述发光元件的第一极连接，所述检测引出线的第二端与所述检测电极连接。
  11. 根据权利要求1至10中任一项所述的显示基板，其中，所述像素电路包括：驱动子电路、电压传输子电路和数据写入子电路；
    所述驱动子电路包括：控制端、第一端和第二端；
    所述电压传输子电路配置为响应于发光控制信号，将第一电源线提供的 第一电源电压施加到所述驱动子电路的第一端；
    所述数据写入子电路配置为响应于第一扫描信号和第二扫描信号，将数据信号写入所述驱动子电路的控制端并存储写入的所述数据信号；
    所述驱动子电路配置为在所述驱动子电路的控制端和第一端的控制下，驱动发光元件发光。
  12. 根据权利要求11所述的显示基板，其中，所述驱动子电路包括：驱动晶体管，所述数据写入子电路包括：第一晶体管、第二晶体管和第一存储电容，所述电压传输子电路包括：第三晶体管；
    所述驱动晶体管的控制极与所述驱动子电路的控制端连接，所述驱动晶体管的第一极与所述驱动子电路的第一端连接，所述驱动晶体管的第二极与所述驱动子电路的第二端连接；
    所述第一晶体管的控制极与第一扫描信号线连接，所述第一晶体管的第一极与数据线连接，所述第一晶体管的第二极与所述驱动晶体管的控制极连接；
    所述第二晶体管的控制极与第二扫描信号线连接，所述第二晶体管的第一极与所述数据线连接，所述第二晶体管的第二极与所述驱动晶体管的控制极连接；
    所述第三晶体管的控制极与发光控制线连接，所述第三晶体管的第一极与第一电源线连接，所述第三晶体管的第二极与所述驱动晶体管的第一极连接；
    所述第一存储电容的第一极与所述驱动晶体管的控制极连接，所述第一存储电容的第二极与第二电源线连接；
    所述发光元件的第一极与所述驱动晶体管的第二极连接，所述发光元件的第二极与第三电源线连接。
  13. 根据权利要求1至10中任一项所述的显示基板，其中，所述像素电路包括：驱动子电路、电压传输子电路和数据写入子电路；
    所述驱动子电路包括：控制端、第一端和第二端；
    所述电压传输子电路配置为响应于传输控制信号，将复位电压和第一电 源电压分别施加到所述驱动子电路的第一端；
    所述数据写入子电路配置为响应于第一扫描信号和第二扫描信号，将数据信号写入所述驱动子电路的控制端并存储写入的所述数据信号；
    所述驱动子电路配置为在所述驱动子电路的控制端和第一端的控制下，驱动发光元件发光；
    所述外围区域设置有电压控制电路，所述电压控制电路与所述像素电路连接；所述电压控制电路配置为响应于复位控制信号，向所述像素电路的电压传输子电路提供复位电压，以及响应于发光控制信号，向所述像素电路的电压传输子电路提供第一电源电压。
  14. 根据权利要求13所述的显示基板，其中，所述驱动子电路包括：驱动晶体管，所述数据写入子电路包括第一晶体管、第二晶体管和第一存储电容，所述电压传输子电路包括：第三晶体管；所述电压控制电路包括：第六晶体管和第七晶体管；
    所述驱动晶体管的控制极与所述驱动子电路的控制端连接，所述驱动晶体管的第一极与所述驱动子电路的第一端连接，所述驱动晶体管的第二极与所述驱动子电路的第二端连接；
    所述第一晶体管的控制极与第一扫描信号线连接，所述第一晶体管的第一极与数据线连接，所述第一晶体管的第二极与所述驱动晶体管的控制极连接；
    所述第二晶体管的控制极与第二扫描信号线连接，所述第二晶体管的第一极与所述数据线连接，所述第二晶体管的第二极与所述驱动晶体管的控制极连接；
    所述第三晶体管的控制极与传输控制线连接，所述第三晶体管的第一极与所述第六晶体管的第二极以及所述第七晶体管的第一极连接，所述第三晶体管的第二极与所述驱动晶体管的第一极连接；
    所述第一存储电容的第一极与所述驱动晶体管的控制极连接，所述第一存储电容的第二极与第二电源线连接；
    所述第六晶体管的控制极与复位控制线连接，所述第六晶体管的第一极 与复位电压线连接，所述第七晶体管的控制极与发光控制线连接，所述第七晶体管的第二极与第一电源线连接；
    所述发光元件的第一极与所述驱动晶体管的第二极连接，所述发光元件的第二极与第三电源线连接。
  15. 根据权利要求12或14所述的显示基板，其中，所述第一晶体管为第一半导体型MOS晶体管，所述第二晶体管、所述第三晶体管和所述驱动晶体管均为第二半导体型MOS晶体管，所述第一半导体型和所述第二半导体型的掺杂类型相反。
  16. 根据权利要求12所述的显示基板，其中，在垂直于所述衬底基板的方向上，所述显示基板包括：依次设置在所述衬底基板上的有源层、第一导电层、第二导电层、第三导电层、第四导电层、第五导电层、第六导电层、第七导电层和第八导电层；
    所述有源层至少包括：所述像素电路的多个晶体管的有源区；
    所述第一导电层至少包括：所述像素电路的多个晶体管的控制极；
    所述第二导电层至少包括：所述像素电路的多个晶体管的第一极和第二极、所述第一电源线、所述第二电源线、所述发光控制线和所述数据线；
    所述第三导电层至少包括：用于连接第一晶体管的第二极、第二晶体管的第二极和驱动晶体管的控制极的第一转接电极，用于连接第一晶体管的控制极和第一扫描信号线的第二转接电极，用于连接第二晶体管的控制极和第二扫描信号线的第三转接电极；
    所述第四导电层至少包括：所述第一扫描信号线、所述第二扫描信号线、第一子电容的第一极和第二极；
    所述第五导电层至少包括：第二子电容的第一极；
    所述第六导电层至少包括：第二子电容的第二极；所述第一子电容和第二子电容并联形成所述第一存储电容；
    所述第七导电层至少包括：用于连接所述第一存储电容的第一子电容的第一极和所述第二子电容的第二极的第四转接电极、从所述显示区域延伸到所述检测区域的检测引出线；所述检测引出线的第一端与所述驱动晶体管的 第二极连接；
    所述第八导电层至少包括：位于所述显示区域的发光元件的第一极、以及位于所述检测区域的检测电极；所述发光元件的第一极与所述检测引出线的第一端连接，所述检测电极与所述检测引出线的第二端连接。
  17. 一种显示装置，包括如权利要求1至16中任一项所述的显示基板。
  18. 一种显示基板的制备方法，包括：
    提供一衬底基板，所述衬底基板包括显示区域以及位于所述显示区域至少一侧的外围区域；
    在所述衬底基板形成多个子像素、至少一个检测电极以及检测引出线；所述多个子像素设置在所述显示区域，所述多个子像素中的至少一个子像素包括发光元件和用于驱动所述发光元件的像素电路；所述外围区域包括检测区域，所述至少一个检测电极设置在所述检测区域，所述至少一个检测电极通过检测引出线与所述发光元件的第一极和所述像素电路电连接，以在检测阶段，通过所述检测电极检测所述发光元件的电学性能。
  19. 一种显示基板的检测方法，所述显示基板包括：衬底基板，所述衬底基板包括显示区域以及位于所述显示区域至少一侧的外围区域；所述显示区域设置有多个子像素，所述多个子像素中的至少一个子像素包括发光元件和用于驱动所述发光元件的像素电路；所述外围区域包括检测区域，所述检测区域设置有至少一个检测电极，所述至少一个检测电极通过检测引出线与所述发光元件的第一极和所述像素电路电连接；所述至少一个检测电极与检测电路电连接，所述检测电路包括：第一控制单元、第二控制单元和存储单元；所述第一控制单元，分别与所述检测电极、第一控制端和第一节点连接，所述第二控制单元，分别与第二控制端、第一信号端和第一节点连接，所述存储单元，分别与所述第一节点和第一电源端连接；
    所述检测方法，包括：
    在检测阶段的第一子阶段，在检测电路的第一控制端的控制下，断开检测电极和第一节点的连接，在第二控制端的控制下，通过第一信号端向第一节点充电；
    在检测阶段的第二子阶段，在检测电路的第二控制端的控制下，断开第一信号端和第一节点的连接，在第一控制端的控制下，通过第一节点向检测电极供电；
    在检测阶段的第三子阶段，在检测电路的第一控制端的控制下，断开检测电极和第一节点的连接，在第二控制端的控制下，通过第一信号端采集第一节点的电压，并根据从第一信号端采集到的电压，确定所述发光元件的电学性能。
  20. 根据权利要求19所述的检测方法，其中，所述根据从第一信号端采集到的电压，确定所述发光元件的电学性能，包括以下至少之一：
    在所述发光元件处于发光状态时，根据第三子阶段从第一信号端采样得到的电压，计算所述发光元件的平均电流；根据采集得到的所述电压和计算得到的平均电流，计算出所述发光元件的等效电阻；根据所述发光元件的等效电阻，确定所述发光元件是否处于弱短弱断状态；
    在所述发光元件处于熄灭状态时，根据第三子阶段从第一信号端采样得到的电压，确定所述发光元件的临界导通电压。
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