WO2022204922A1 - 显示基板及其制作方法以及显示装置 - Google Patents

显示基板及其制作方法以及显示装置 Download PDF

Info

Publication number
WO2022204922A1
WO2022204922A1 PCT/CN2021/083857 CN2021083857W WO2022204922A1 WO 2022204922 A1 WO2022204922 A1 WO 2022204922A1 CN 2021083857 W CN2021083857 W CN 2021083857W WO 2022204922 A1 WO2022204922 A1 WO 2022204922A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
electrode
transistor
gate
driving transistor
Prior art date
Application number
PCT/CN2021/083857
Other languages
English (en)
French (fr)
Inventor
程磊磊
许程
刘杰
徐纯洁
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to DE112021001975.9T priority Critical patent/DE112021001975T5/de
Priority to PCT/CN2021/083857 priority patent/WO2022204922A1/zh
Priority to CN202180000658.0A priority patent/CN115485852A/zh
Priority to US17/764,706 priority patent/US20230337466A1/en
Publication of WO2022204922A1 publication Critical patent/WO2022204922A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L2029/42388—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor characterised by the shape of the insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00

Definitions

  • At least one embodiment of the present disclosure relates to a display substrate, a method for fabricating the same, and a display device.
  • organic light emitting diode (OLED) display panels have the characteristics of self-luminescence, high contrast ratio, low energy consumption, wide viewing angle, fast response speed, can be used for flexible panels, wide operating temperature range, simple manufacturing, etc. Prospects.
  • At least one embodiment of the present disclosure provides a display substrate, the display substrate includes a base substrate, and the base substrate is provided with a plurality of pixels arranged in an array; at least some of the pixels in the plurality of pixels include a plurality of sub-pixels, and the At least some of the sub-pixels include a light-emitting element and a pixel circuit that drives the light-emitting element to emit light, the pixel circuit includes a storage capacitor, a driving transistor and a data writing transistor, the driving transistor includes an active layer, a gate , a first pole and a second pole, the data writing transistor includes an active layer, a gate, a first pole and a second pole; the first pole of the driving transistor is configured to receive a first power supply voltage, the driving The second electrode of the transistor is connected to the light-emitting device to be configured to control the light-emitting device to emit light; at least some of the sub-pixels in the plurality of sub-pixels include a first via hole, and the first electrode of the
  • the gate of the driving transistor includes a main body part and an extension part connected to the main body part, and the orthographic projection of the main body part on the base substrate is the same as that of the main body part.
  • the orthographic projection of the active layer of the driving transistor on the base substrate overlaps, the extension portion extends from the main body portion, and the extension portion is connected to the data writing transistor through the first via hole.
  • the first electrode is electrically connected to the active layer of the data writing transistor.
  • the first electrode of the data writing transistor includes a first conductive portion and a second conductive portion stacked on each other in a direction perpendicular to the base substrate, so The second conductive part is located on the side of the first conductive part away from the base substrate; the gate of the driving transistor is located on the side of the first conductive part close to the second conductive part and is connected to the side of the first conductive part.
  • the first conductive parts are spaced apart, and the second conductive parts are in contact with the gate electrodes of the driving transistors and the first conductive parts through the first via holes; the display substrate further includes a connection part, for example, In the display substrate provided in at least one embodiment of the present disclosure, the extension portion overlaps in a direction perpendicular to the base substrate, and the first conductive portion is connected to the active layer of the data writing transistor as All-in-one structure.
  • the material of the second conductive portion and the material of the connection portion include the same semiconductor material, and the semiconductor material included in the first conductive portion is conductorized .
  • the first conductive portion includes:
  • first sub-portion located on a first side of the extension portion, wherein the second conductive portion is in direct contact with the first sub-portion on the first side through the first via hole;
  • the second conductive portion extends from a first side of the extension portion in the first via hole to the extension portion to contact at least a portion of an upper surface of the extension portion remote from the base substrate.
  • the first conductive portion further includes:
  • the second sub-portion is located on a second side of the extension portion, wherein the second side is opposite to the first side, and the second conductive portion is located at the first via hole from the first side of the extension portion
  • the middle portion extends across the extension portion to extend to a second side of the extension portion, and the second conductive portion directly contacts the second sub-portion at the second side through the first via hole.
  • the display substrate provided by at least one embodiment of the present disclosure further includes:
  • a gate insulating layer located between the gate of the driving transistor and the active layer of the driving transistor, and the gate of the driving transistor is located on the side of the gate insulating layer away from the base substrate;
  • a first insulating layer located on a side of the gate of the driving transistor away from the base substrate, wherein the first via penetrates the gate insulating layer and the first insulating layer;
  • the gate insulating layer includes an upper surface and a side surface intersecting with the upper surface of the gate insulating layer, and the side surface of the extension part is located near the extension part in the angle between the side surface of the extension part and the plane where the upper surface of the extension part is located.
  • the angle is the first included angle
  • the included angle between the side surface of the gate insulating layer and the plane where the upper surface of the extension portion is located is the second included angle
  • the included angle close to the extension portion is the second included angle
  • the second conductive portion comprising a middle part in direct contact with the extension part, the included angle between the side surface of the middle part and the plane where the upper surface of the extension part is located is the third included angle;
  • the first included angle is greater than the second included angle, or the first included angle is greater than the third included angle and the third included angle is greater than the second included angle.
  • the storage capacitor includes:
  • the second capacitor electrode is at least partially in the same layer as the first electrode of the driving transistor and has an integrated structure
  • the first capacitor electrode is insulated from the second capacitor electrode and is in the same layer as the active layer of the driving transistor and has an integrated structure, wherein the second capacitor electrode and the first capacitor electrode constitute the storage capacitor the two plates of the first capacitor.
  • the display substrate provided by at least one embodiment of the present disclosure further includes:
  • An opaque light-shielding layer wherein the active layer of the driving transistor is located in the orthographic projection of the light-shielding layer on the base substrate, and the light-shielding layer is electrically connected to the second capacitor electrode of the first capacitor. connected, and the light shielding layer is insulated from the first capacitor electrode of the first capacitor and at least partially overlapped in the direction perpendicular to the base substrate to serve as the third capacitor electrode of the storage capacitor, the first capacitor electrode
  • the three capacitor electrodes and the first capacitor electrode constitute two pole plates of a second capacitor of the storage capacitor, and the second capacitor is connected in parallel with the first capacitor.
  • the first electrode of the driving transistor is located on a side of the active layer of the driving transistor away from the base substrate, and the light shielding layer is located on the driving transistor.
  • the side of the active layer of the transistor close to the base substrate.
  • the second conductive portion and the first electrode of the driving transistor are in the same layer and made of the same material.
  • the display substrate provided by at least one embodiment of the present disclosure further includes:
  • a signal line comprising a first layer, a second layer and a third layer stacked in sequence perpendicular to the base substrate and along a direction away from the base substrate, wherein the first layer and the second layer Spaced apart, the signal line further includes a signal line via through which the third layer is electrically connected to the second layer and the first layer.
  • the first layer is the same layer as the active layer of the driving transistor
  • the second layer is the same layer and the same material as the gate electrode of the driving transistor
  • the third layer is the same layer and the same material as the first electrode of the driving transistor.
  • the first layer includes:
  • a first conductor part located on the first side of the second layer, wherein the third layer is in direct contact with the first conductor part through the signal line via on the first side of the second layer;
  • the third layer extends from the first side of the first conductor portion in the signal line via to the second side of the first conductor portion to be away from the base substrate with the second layer at least part of the upper surface of the contact.
  • the third layer is directly connected to an upper surface of the second layer away from the base substrate and a side surface of the second layer that intersects with the upper surface thereof. contact, and the third layer is in direct contact with the first layer.
  • the first layer further includes:
  • the second conductor part is located on the second side of the second layer in the line width direction of the signal line, wherein the second side of the second layer is opposite to the first side of the second layer, so
  • the third layer extends across the second layer from the first side of the second layer in the signal line via in the line width direction of the signal line to extend to the second layer of the second layer.
  • the third layer is in direct contact with the second conductor portion through the signal line via hole.
  • the first layer further includes:
  • the semiconductor portion overlaps the second layer in a direction perpendicular to the base substrate, is in the same layer as the active layer of the driving transistor, and forms an integral structure with the first conductor portion.
  • the display substrate provided by at least one embodiment of the present disclosure further includes:
  • a data line connected to the second electrode of the data writing transistor and configured to provide a data signal to the data writing transistor, wherein the signal line includes the data line.
  • the display substrate provided by at least one embodiment of the present disclosure further includes:
  • a first power supply line configured to provide a first power supply voltage to a first electrode of the driving transistor, wherein the signal line includes the first power supply line.
  • At least one embodiment of the present disclosure further provides a display device, where the display device includes any one of the display substrates provided in the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure further provides a method for fabricating a display substrate, the fabrication method comprising: providing a base substrate; forming a plurality of pixels on the base substrate, wherein at least some of the pixels in the plurality of pixels include a plurality of pixels.
  • each of the plurality of sub-pixels includes a light-emitting element and a pixel circuit that drives the light-emitting element to emit light
  • the pixel circuit includes a light-emitting device, a storage capacitor, a driving transistor and a data writing transistor, the driving transistor and all
  • Each of the data writing transistors includes an active layer, a gate, a first electrode and a second electrode; the first electrode of the driving transistor is configured to receive a first power supply voltage, and the second electrode of the driving transistor is connected to the light-emitting device connections configured to control the light emitting device to emit light; and forming a first via hole in at least a portion of the sub-pixels in the plurality of sub-pixels, wherein a first electrode of the data writing transistor passes through the first via hole The hole is electrically connected to the gate of the driving transistor and the active layer of the data writing transistor.
  • At least one embodiment of the present disclosure further provides a method for fabricating a display substrate, comprising: forming a semiconductor layer; forming a gate insulating layer covering the semiconductor layer on a side of the semiconductor layer away from the base substrate; forming a gate conductive layer on a side of the gate insulating layer away from the base substrate; patterning the gate conductive layer through a patterning process to form the gate of the driving transistor; using the gate of the driving transistor as the The etching barrier layer performs a patterning process on the gate insulating layer to expose a portion of the semiconductor layer, wherein the semiconductor layer includes a portion shielded by the gate insulating layer and a portion not shielded by the gate insulating layer; and conducting conductive processing on the portion of the semiconductor layer that is not shielded by the gate insulating layer to form a first conductive portion, and the portion shielded by the gate insulating layer is not conductive to constitute the active layer and the driving transistor.
  • connection part wherein the gate of the driving transistor includes a main body part and an extension part connected to the main body part, the projection of the main body part overlaps with the projection of the active layer of the driving transistor, the extension part is The main body portion extends, and the extension portion is electrically connected to the gate of the driving transistor and the active layer of the data writing transistor through the first via hole; the connection portion is perpendicular to the extension portion overlapping in the direction of the base substrate, and connecting the first conductive part and the active layer of the data writing transistor into an integrated structure.
  • forming the first via hole includes: forming an active layer of the driving transistor and an active layer of the data writing transistor Then, a first insulating layer is formed on the side of the gate of the driving transistor away from the base substrate, wherein the first insulating layer covers the gate of the driving transistor and the gate of the data writing transistor.
  • the manufacturing method further includes: forming a second conductive portion on a side of the gate of the driving transistor away from the base substrate, wherein the second conductive portion passes through the first conductive portion
  • the via hole is electrically connected to the gate electrode of the driving transistor and the first conductive portion, and the first conductive portion and the second conductive portion constitute a first electrode of the data writing transistor.
  • At least one embodiment of the present disclosure further provides a method for fabricating a display substrate, further comprising: forming a signal line, including forming a first stack in a direction perpendicular to the base substrate and in a direction away from the base substrate. layer, a second layer, and a third layer, wherein the first layer is spaced apart from the third layer, the signal line further includes a signal line via through which the third layer passes in electrical connection with the second layer and the first layer.
  • a method for fabricating a display substrate is further provided, wherein the first layer and the active layer of the driving transistor pass through a portion of the semiconductor layer that is not shielded by the gate insulating layer
  • the same conductorization treatment process is performed at the same time to form; the second layer and the gate of the driving transistor are simultaneously formed by performing the same patterning process on the gate conductive layer; the third layer and the gate of the driving transistor are simultaneously formed;
  • One pole is simultaneously formed by performing the same patterning process on the same film layer.
  • FIG. 1 is a schematic diagram of a display substrate provided by at least one embodiment of the present disclosure
  • 2A is a circuit diagram of a pixel of a display substrate provided by at least one embodiment of the present disclosure
  • 2B-2D are signal timing diagrams of a driving method of a pixel circuit provided by an embodiment of the present disclosure
  • 3A is a schematic structural diagram of a sub-pixel of a display substrate according to at least one embodiment of the present disclosure
  • Figure 3B is a sectional view of Figure 2A along section line I-I';
  • Figure 3C is another cross-sectional view of Figure 2A along section line I-I';
  • FIG. 4A is a schematic plan view of a first conductive layer in a display substrate according to at least one embodiment of the present disclosure
  • 4B is a schematic plan view of a semiconductor layer in a display substrate provided by at least one embodiment of the present disclosure
  • 4C is a schematic plan view of a second conductive layer in a display substrate provided by at least one embodiment of the present disclosure
  • 4D is a schematic plan view of a third conductive layer in a display substrate according to at least one embodiment of the present disclosure
  • 4E is a schematic plan view of a first electrode in a display substrate provided by at least one embodiment of the present disclosure
  • 4F is a schematic plan view of stacking a first conductive layer and a semiconductor layer in a display substrate according to at least one embodiment of the present disclosure
  • 4G is a schematic plan view of a stack of a first conductive layer, a semiconductor layer and a second conductive layer in a display substrate according to at least one embodiment of the present disclosure
  • 4H is a schematic plan view of a stack of a first conductive layer, a semiconductor layer, a second conductive layer and a third conductive layer in a display substrate according to at least one embodiment of the present disclosure
  • Figure 5 is a cross-sectional view of Figure 3A along section line A-A';
  • FIG. 6 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • At least one embodiment of the present disclosure provides a display substrate, the display substrate includes a base substrate, and the base substrate is provided with a plurality of pixels arranged in an array; at least some of the pixels in the plurality of pixels include a plurality of sub-pixels, so At least part of the sub-pixels in the plurality of sub-pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light, the pixel circuit includes a storage capacitor, a driving transistor and a data writing transistor, the driving transistor includes an active layer, a gate A pole, a first pole and a second pole, the data writing transistor includes an active layer, a gate, a first pole and a second pole; the first pole of the driving transistor is configured to receive a first power supply voltage, the The second electrode of the driving transistor is connected to the light emitting device to be configured to control the light emitting device to emit light; at least some of the sub-pixels in the plurality of sub-pixels include a first via hole, and
  • the first electrode of the data writing transistor is electrically connected to the gate of the driving transistor and the active layer of the data writing transistor through only the first via hole, and is connected to other connection methods.
  • the contact resistance of the connection position is obviously reduced, the signal transmission efficiency is improved, and at the same time, the manufacturing process of the display substrate is simplified.
  • FIG. 1 is a schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • the display substrate 10 includes a plurality of pixels 100 arranged in an array, at least some of the pixels 100 of the plurality of pixels 100 include a plurality of sub-pixels, and at least some of the sub-pixels of the plurality of sub-pixels include light-emitting elements and driving light-emitting elements
  • a pixel circuit with light-emitting elements, the pixel circuit includes a storage capacitor, a driving transistor and a data writing transistor, the driving transistor includes an active layer, a gate, a first electrode and a second electrode, and the data writing transistor includes an active layer, a gate pole, first pole and second pole.
  • the first electrode of the driving transistor is configured to receive the first power supply voltage
  • the second electrode of the driving transistor is connected to the light emitting device to be configured to control the light emitting device to emit light.
  • some pixels in the plurality of pixels 100 are dummy pixels 101.
  • the dummy pixels 1000 do not participate in the display operation.
  • Each dummy pixel 1000 includes a plurality of dummy sub-pixels, but does not include sub-pixels for display driving.
  • the display substrate 10 is an organic light emitting diode (OLED) display substrate
  • the light emitting element is an OLED.
  • the display substrate 10 may further include a plurality of scan lines and a plurality of data lines for providing scan signals (control signals) and data signals for the plurality of sub-pixels, so as to drive the plurality of sub-pixels.
  • the display substrate 10 may further include power lines, detection lines, and the like.
  • the pixel circuit includes a driving sub-circuit for driving the light-emitting element to emit light and a detection sub-circuit for detecting the electrical characteristics of the sub-pixel to realize external compensation.
  • the embodiments of the present disclosure do not limit the specific structure of the pixel circuit.
  • FIG. 2A shows a schematic diagram of a 3T1C pixel circuit for the display substrate.
  • the pixel circuit of the display substrate provided by the embodiment of the present disclosure is not limited to be a 3T1C pixel circuit.
  • the structure of the display substrate is described by taking the pixel circuit of the display substrate 10 as an example of a 3T1C pixel circuit.
  • the pixel circuit may further include a compensation circuit, a reset circuit, and the like, which are not limited in the embodiments of the present disclosure.
  • the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor Cst.
  • the first transistor T1 is the driving transistor described in the present application
  • the second transistor T2 is the data writing transistor described in the present application.
  • the first electrode of the second transistor T2 is electrically connected to the first capacitor electrode Ca of the storage capacitor Cst and the gate of the first transistor T1, the second electrode of the second transistor T2 is configured to receive the data signal DT, and the second transistor T2 is configured to The data signal DT is written into the gate of the first transistor T1 and the storage capacitor Cst in response to the first control signal G1; the first electrode of the first transistor T1 is electrically connected to the second capacitor electrode Cb of the storage capacitor Cst, and is configured as Electrically connected to the first electrode of the light-emitting element, the second electrode of the first transistor T1 is configured to receive a first power supply voltage V1 (eg, a high power supply voltage VDD), and the first transistor T1 is configured to be at the gate of the first transistor T1.
  • V1 eg, a high power supply voltage VDD
  • the current used to drive the light-emitting element is controlled under the control of the voltage; the first electrode of the third transistor T3 is electrically connected to the first electrode of the first transistor T1 and the second capacitor electrode Cb of the storage capacitor Cst, and the second electrode of the third transistor T3
  • the electrode is configured to be connected to the detection line 230 to be connected to the external detection circuit 21, and the third transistor T3 is configured to detect the electrical characteristic of the sub-pixel to which it belongs in response to the second control signal G2 to realize external compensation; the electrical characteristic includes, for example, the first transistor The threshold voltage and/or carrier mobility of T1, or the threshold voltage, driving current, etc. of the light-emitting element.
  • the external detection circuit 21 is, for example, a conventional circuit including a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), and the like, which will not be repeated in the embodiments of the present disclosure.
  • the storage capacitor Cst shown in FIG. 2A further includes a third capacitor electrode Cc, the third capacitor electrode Cc is located on the side of the first capacitor electrode Ca away from the second capacitor electrode Cb and passes through the second capacitor electrode Cb as shown in FIG. 3A .
  • the No. 7 via holes shown are electrically connected to each other to form a parallel capacitor structure, increasing the capacitance value of the storage capacitor Cst.
  • the third capacitor electrode Cc, the second capacitor electrode Cb, and the first capacitor electrode Ca all overlap with each other.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors, field effect transistors, or other switching devices with the same characteristics, and the thin film transistors are used as examples for description in the embodiments of the present disclosure.
  • the source and drain of the transistor used here may be symmetrical in structure, so the source and drain of the transistor may be indistinguishable in structure.
  • one pole is directly described as the first pole, and the other pole is the second pole.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the turn-on voltage is a low-level voltage (eg, 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (eg, 5V, 10V, or other suitable voltages) );
  • the turn-on voltage is a high-level voltage (eg, 5V, 10V, or other suitable voltages)
  • the turn-off voltage is a low-level voltage (eg, 0V, -5V, -10V or other suitable voltages) voltage).
  • the transistor in FIG. 2A is an N-type transistor as an example for illustration, but this is not a limitation of the present disclosure.
  • FIG. 2A shows the working principle of the pixel circuit shown in FIG. 2A , wherein FIG. 2B shows the signal timing diagram of the pixel circuit in the display process, and FIG. 2C and FIG. 2D show The signal timing diagram of the pixel circuit in the detection process is shown.
  • the display process of each frame of image includes data writing and resetting phase 1 and light-emitting phase 2 .
  • Figure 2B shows the timing waveforms of the various signals in each stage.
  • a working process of the 3T1C pixel circuit includes: in data writing and resetting stage 1, the first control signal G1 and the second control signal G2 are both turn-on signals, the second transistor T2 and the third transistor T3 are turned on, and the data signal DT is transmitted to the gate of the first transistor T1 through the second transistor T2, the first switch K1 is turned off, and the analog-to-digital converter writes to the first electrode of the light-emitting element (eg, the anode of the OLED) through the detection line 230 and the third transistor T3
  • the reset signal, the first transistor T1 is turned on and generates a driving current to charge the first electrode of the light-emitting element to the working voltage; in the light-emitting stage 2, the first control signal G1 and the second control signal G2 are both off
  • FIG. 2C shows a signal timing diagram of the pixel circuit when the threshold voltage is detected.
  • a working process of the 3T1C pixel circuit includes: the first control signal G1 and the second control signal G2 are both turn-on signals, the second transistor T2 and the third transistor T3 are turned on, and the data signal DT is transmitted to the second transistor T2 through the second transistor T2.
  • FIG. 2D shows a signal timing diagram of the pixel circuit when the carrier mobility is detected.
  • a working process of the 3T1C pixel circuit includes: in the first stage, the first control signal G1 and the second control signal G2 are both turn-on signals, the second transistor T2 and the third transistor T3 are turned on, and the data signal DT is passed through the second
  • the transistor T2 is transmitted to the gate of the first transistor T1; the first switch K1 is turned off, and the analog-to-digital converter writes a reset signal to the first electrode (node S) of the light-emitting element through the detection line 230 and the third transistor T3; at the second In the stage, the first control signal G1 is an off signal, the second control signal G1 is an on signal, the second transistor T2 is turned off, the third transistor T3 is turned on, and the first switch K1 and the second switch K2 are turned off to detect The line 230 is floating; due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cs
  • the electrical characteristics of the first transistor T1 can be obtained and a corresponding compensation algorithm can be implemented.
  • the display substrate 10 may further include a data driving circuit and a scan driving circuit (not shown).
  • the data driving circuit is configured to issue a data signal, such as the above-mentioned data signal DT, as required (eg, an image signal input to the display device); the pixel circuit of each sub-pixel is further configured to receive the data signal and apply the data signal to the first the gate of the transistor.
  • the scan driving circuit is configured to output various scan signals, for example, including the above-mentioned first control signal G1 and second control signal G2, which are, for example, an integrated circuit chip (IC) or a gate driving circuit (GOA) directly fabricated on the display substrate .
  • IC integrated circuit chip
  • GOA gate driving circuit
  • the display substrate 10 further includes a control circuit.
  • the control circuit is configured to control the data driving circuit to apply the data signal, and to control the gate driving circuit to apply the scan signal.
  • An example of the control circuit is a timing control circuit (T-con).
  • the control circuit may be in various forms, including, for example, a processor and a memory, the memory including executable code that the processor executes to execute the detection method described above.
  • a processor may be a central processing unit (CPU) or other form of processing device having data processing capabilities and/or instruction execution capabilities, such as may include a microprocessor, programmable logic controller (PLC), or the like.
  • CPU central processing unit
  • PLC programmable logic controller
  • memory may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory.
  • Volatile memory may include, for example, random access memory (RAM) and/or cache memory, among others.
  • Non-volatile memory may include, for example, read only memory (ROM), hard disk, flash memory, and the like.
  • One or more computer program instructions may be stored on a computer-readable storage medium, and a processor may execute the functions desired by the program instructions.
  • Various application programs and various data can also be stored in the computer-readable storage medium, for example, the electrical characteristic parameters obtained in the above detection method, and the like.
  • the display substrate 10 includes a base substrate 101 , and a plurality of sub-pixels P1/P2/P3 are located on the base substrate 101 superior.
  • a plurality of sub-pixels P1/P2/P3 are distributed along the first direction D1 and the second direction D2 as a pixel array, the pixel array includes a plurality of pixel columns and a plurality of pixel rows, the column direction of the pixel array is the first direction D1, the row The direction is the second direction D2, and the first direction D1 and the second direction D2 intersect, for example, orthogonal.
  • each pixel row is divided into a plurality of pixel units, each of which is configured to emit full-color light.
  • One pixel cell is exemplarily shown in FIG. 3A, and implementations of the present disclosure are not limited to this layout;
  • FIG. 3B shows a cross-sectional view of FIG. 3A along section line I-I'. As shown in FIG.
  • the pixel unit includes a first sub-pixel P1, a second sub-pixel P2 and a third sub-pixel P3 arranged in sequence along the second direction D2, the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P1
  • the three sub-pixels P3 are respectively used to emit light of three primary colors (RGB); for example, the first sub-pixel P1 is a red sub-pixel, the second sub-pixel P2 is a blue sub-pixel, and the third sub-pixel P3 is a green sub-pixel .
  • FIG. 4A is a schematic plan view of a first conductive layer in a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 4B is a schematic plan view of a semiconductor layer in a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 4C is at least one embodiment of the present disclosure.
  • FIG. 4D is a schematic plan view of a third conductive layer in a display substrate provided by at least one embodiment of the disclosure
  • FIG. 4E is provided by at least one embodiment of the disclosure
  • FIG. 4F is a schematic plan view of the stacking of the first conductive layer and the semiconductor layer in the display substrate provided by at least one embodiment of the present disclosure
  • FIG. 4F is a schematic plan view of the stacking of the first conductive layer and the semiconductor layer in the display substrate provided by at least one embodiment of the present disclosure
  • FIG. 4F is a schematic plan view of the stacking of the first conductive layer and the
  • FIG. 4G is provided by at least one embodiment of the present disclosure.
  • FIG. 4H is the first conductive layer, the semiconductor layer, the second conductive layer and the first conductive layer in the display substrate provided by at least one embodiment of the present disclosure.
  • Schematic plan view of a three-conducting layer stack. 3A-3B and FIGS. 4A-4H the display substrate 10 includes a first conductive layer 501 , a second insulating layer 202 , a semiconductor layer 104 , a gate insulating layer 200 , and a second conductive layer 501 , which are sequentially arranged on the base substrate 101 .
  • layer 502 , first insulating layer 201 , third conductive layer 503 and fourth conductive layer 504 are sequentially arranged on the base substrate 101 .
  • T1g, T1s, T1d, T1a are used to represent the gate, first electrode, second electrode and active layer of the first transistor T1 respectively
  • T2g, T2s, T2d, T2a are used to represent the first transistor T1, respectively.
  • the gate, the first electrode, the second electrode and the active layer of the two transistors T2 are represented by T3g, T3s, T3d and T3a, respectively
  • the gate, the first electrode, the second electrode and the active layer of the third transistor T3 are represented by Ca, Cb, and Cc represent the first capacitance electrode Ca, the second capacitance electrode Cb, and the third capacitance electrode Cc of the storage capacitance Cst, respectively.
  • the “same layer arrangement” referred to in the present disclosure refers to two (or more than two) structures formed by the same deposition process and patterned by the same patterning process. Can be the same or different.
  • the “integrated structure” in the present disclosure refers to a structure in which two (or more than two) structures are formed by the same deposition process and patterned by the same patterning process and are connected to each other, and their materials may be the same or different. .
  • the first conductive layer 501 includes a light shielding layer 170 , and the orthographic projection of the light shielding layer 170 on the base substrate 101 covers the active layer T1a of the first transistor T1 on the base substrate Orthographic projection on 101.
  • the first transistor T1 is used as a driving transistor of the pixel circuit, and the stability of its electrical characteristics is very important for the light-emitting characteristics of the light-emitting element.
  • the light shielding layer 170 is an opaque layer, which can prevent light from entering the active layer of the first transistor T1 from the back of the base substrate 101 to cause a shift in the threshold voltage of the first transistor T1, thereby avoiding affecting the corresponding luminous properties of the light-emitting element.
  • the light shielding layer 170 is made of an opaque conductive material, such as a metal or metal alloy material. This arrangement can alleviate the back channel phenomenon caused by the trapped charges of the base substrate 101 .
  • the semiconductor layer 104 includes an active layer T1a of the first transistor T1, an active layer T2a of the second transistor T2, and an active layer T3a of the third transistor T3.
  • the semiconductor layer 104 further includes a first capacitor electrode Ca of the storage capacitor Cst, and the first capacitor electrode Ca is obtained from the semiconductor layer 104 through conducting treatment; that is, the first capacitor electrode Ca and the first transistor T1 have a The active layer T1a, the active layer T2a of the second transistor, and the active layer T3a of the third transistor are arranged in the same layer.
  • the second conductive layer 502 includes the gate T1g of the first transistor T1, the gate T2g of the second transistor T2, and the gate T3g of the third transistor T3.
  • the display substrate 10 adopts a self-alignment process, and uses the second conductive layer 502 as a mask to conduct conductorization treatment (eg, doping treatment) on the semiconductor layer 104, so that the semiconductor layer 104 is not covered by the second conductive layer 502.
  • the covered part is conductorized, so as to obtain the first capacitor electrode Ca, and the parts of the active layer of each transistor located on both sides of the channel region are conductorized to form a first electrode contact region and a second electrode contact region, respectively,
  • the first electrode contact area and the second electrode contact area are used for electrical connection with the first electrode and the second electrode of the transistor, respectively.
  • the third conductive layer 503 includes a first electrode T1s and a second electrode T1d of the first transistor T1, a first electrode T2s and a second electrode T2d of the second transistor T2, and a first electrode T1s and a second electrode T2d of the second transistor T2.
  • the third conductive layer 503 further includes a second capacitor electrode Cb of the storage capacitor Cst.
  • the second capacitor electrode Cb and the second electrode T1d of the first transistor T1 are provided in the same layer and are connected to each other as a whole.
  • the first capacitor electrode Ca and the second capacitor electrode Cb overlap each other in a direction perpendicular to the base substrate 101 to form a storage capacitor Cst.
  • each sub-pixel further includes a light-emitting element 125 , for example, the light-emitting element is an organic light-emitting diode, including a first electrode 123 , a light-emitting layer 124 and a second electrode 122 that are stacked in sequence.
  • the light emitting element 125 is of a top emission structure
  • the first electrode 122 is reflective
  • the second electrode 122 is transmissive or semi-transmissive.
  • the first electrode 122 is a material with a high work function to serve as an anode, such as an ITO/Ag/ITO stack structure;
  • the second electrode 122 is a material with a low work function to serve as a cathode, such as a semi-transmissive metal or metal alloy material , such as Ag/Mg alloy materials.
  • the fourth conductive layer 504 includes the first electrode 123 .
  • each sub-pixel further includes a light-emitting element 125 , for example, the light-emitting element is an organic light-emitting diode, including a first electrode 123 , a light-emitting layer 124 and a second electrode 122 that are stacked in sequence.
  • the light-emitting element 125 is a top emission structure
  • the first electrode is reflective
  • the second electrode 122 is transmissive or semi-transmissive.
  • the first electrode 122 is a material with a high work function to serve as an anode, such as an ITO/Ag/ITO stack structure;
  • the second electrode 122 is a material with a low work function to serve as a cathode, such as a semi-transmissive metal or metal alloy material , such as Ag/Mg alloy materials.
  • the display substrate 10 further includes a third insulating layer 203 and a fourth insulating layer 204 located between the third conductive layer 503 and the first electrode 123 of the light-emitting element.
  • the third insulating layer 203 is a passivation layer, such as an inorganic insulating layer, such as silicon oxide, silicon nitride, silicon oxynitride and other silicon oxides, silicon nitrides or silicon oxynitrides;
  • the insulating layer 204 is an organic insulating material, such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA) and other organic insulating materials.
  • the fourth insulating layer 204 is a planarization layer.
  • the display substrate 10 further includes a pixel defining layer 206 located on the first electrode 123 of the light emitting element 125, and the pixel defining layer 206 is an organic insulating material, such as polyimide (PI), acrylate, epoxy resin, Organic insulating materials such as polymethyl methacrylate (PMMA).
  • PI polyimide
  • PMMA polymethyl methacrylate
  • the first electrode 123 of the light-emitting element 125 is electrically connected to the first electrode T1s of the first transistor T1 and the second capacitor electrode Cb through a No. 8 via hole, for example, the No. 8 via hole penetrates through the third insulating layer 203 and the fourth insulating layer 204.
  • the light-emitting element OLED in each sub-pixel is configured to emit white light
  • the display substrate 10 further includes a color filter layer
  • the white light is emitted through the color filter layer to realize full-color display.
  • the light-emitting layer 124 can be formed on the entire surface by an Open Mask combined with an evaporation process, so as to avoid using a fine metal mask (Fine Metal Mask, FMM) to pattern the light-emitting layer, thereby avoiding the limitation of the display due to the limited precision of the FMM.
  • FMM Fine Metal Mask
  • the light emitting element of the display substrate 10 may adopt a bottom emission structure.
  • the color filter layer is located on the side of the first electrode of the light-emitting element close to the base substrate 101 , for example, between the third insulating layer 203 and the fourth insulating layer 204 .
  • the color filter layer includes a plurality of color filter portions 190 respectively corresponding to a plurality of sub-pixels except the white sub-pixel, that is, the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 respectively correspond to a color filter portion 190, the light emitted by the light-emitting elements of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 is emitted through the color filter portion 190 to form display light.
  • each sub-pixel includes a first via hole V0, the first electrode T2s of the data writing transistor T2 passes through the first via hole V0 and the gate T1g of the driving transistor T1 and the active gate of the data writing transistor T2.
  • Layer T2a is electrically connected. It should be noted that the entire first via hole V0 is a through hole.
  • the first electrode T2s of the data writing transistor T2 passes through only the first via hole V0 and the gate T1g of the driving transistor T1 and the gate electrode T1g of the data writing transistor T1.
  • the electrical connection of the source layer compared with other connection methods, obviously reduces the contact resistance of the connection position, improves the signal transmission efficiency, and simplifies the manufacturing process of the display substrate.
  • connection 720 is also shown in Figure 4B.
  • the gate T1g of the driving transistor T1 includes a main body part 181 and an extension part 180 connected to the main body part 181 .
  • the orthographic projection of the main body part 181 on the base substrate 101 corresponds to the active layer of the driving transistor.
  • the orthographic projection of T1a on the base substrate 101 overlaps, and the extension portion 180 extends from the body portion 181.
  • the extension portion 180 is connected to the first electrode T2s of the data writing transistor T2 and the active electrode of the data writing transistor through the first via V0.
  • Layer T2a is electrically connected.
  • the first via hole V0 includes a first region V1 and a second region V2 that communicate with each other; for example, the first electrode T2s of the data writing transistor T2 communicates with the data through the first region V1 and the second region V2 of the first via hole V0, respectively.
  • the first electrode T2s of the writing transistor T2 is in direct contact for electrical connection; the extension 180 is connected to the first electrode contact region T2a1 of the active layer T2a of the second transistor T2 through the first region V1 of the first via hole V0, as shown in the figure 4B, the first electrode contact region T2a1 is in direct contact with the active layer T2a of the second transistor T2 for electrical connection, so that the extension portion 180 is electrically connected to the active layer T2a of the data writing transistor through the first via V0.
  • the first electrode T2s of the data writing transistor T2 includes a first conductive part 111 and a second conductive part 112 stacked on each other in a direction perpendicular to the base substrate 101 , and the second conductive part 112 is located in The side of the first conductive portion 111 away from the base substrate 101; the gate T1g of the driving transistor T1 is located on the side of the first conductive portion 111 close to the second conductive portion 112 and is spaced apart from the first conductive portion 111.
  • the conductive portion 112 is in contact with the gate T1g of the driving transistor T1 and the first conductive portion 111 through the first via hole V0 to reduce contact resistance.
  • the display substrate 10 further includes a connection portion 720, which overlaps the extension portion 180 in a direction perpendicular to the base substrate 101, and connects the first conductive portion 111 to the active layer T2a (eg, the second transistor) of the data writing transistor T2.
  • the channel region T2a0) of T2 is connected into an integral structure.
  • the connection part 720 is in contact with the first conductive part 111, and the connection part 720 is connected to the channel region T2a0 of the second transistor T2 via the first electrode contact region T2a1.
  • the first conductive portion 111 and the active layer T2a of the data writing transistor T2 are connected as an integral structure here means that there is no gap between the two and no other layers or structures, but the materials of the two are different.
  • the first conductive portion 111 and the first electrode contact region T2a1 belong to the semiconductor layer 104 and are not covered by the second conductive layer.
  • the part covered by 502 is conductive
  • the connection part 720 and the channel region T2a0 of the second transistor T2 belong to the part covered by the second conductive layer 502 and are not conductive, so that the first conductive part 111 and the data writing transistor T2
  • the materials of the active layer T2a are different. In this way, the mask for forming the active layer through the patterning process can be saved, and the manufacturing process can be simplified.
  • the material of the second conductive portion 112 and the material of the connection portion 180 include the same semiconductor material, and the semiconductor material included in the first conductive portion 111 is conductive.
  • the semiconducting process may be a plasma treatment process for the semiconductor layer using plasma, or a doping process, etc.
  • the specific process type may refer to conventional techniques in the art, which are not limited in the present disclosure.
  • the above-mentioned semiconductor material is IGZO.
  • the surface of IGZO is treated with a gas containing H+, so that the oxygen in IGZO is combined with H+, and the IGZO not covered by the second conductive layer is made conductive with the continuous reaction with the conductor gas.
  • the first conductive portion 111 includes a first sub-portion S1 , and the first sub-portion S1 is located on the first side of the extension portion 180 ; the second conductive portion 112 passes through the first The via hole V0 is in direct contact with the first sub-section S1.
  • the second conductive portion 112 extends from the first side of the extension portion 180 to the extension portion 180 in the first via hole V0 to contact at least a portion of the upper surface of the extension portion 180 away from the base substrate 101 .
  • the second conductive portion 112 is in contact with a position of the upper surface of the extension portion 180 over the entire width in the first direction D1. In this way, the contact resistance of the electrical connection between the first conductive part 111 , the extension part 180 and the second conductive part 112 can be further reduced, and the signal transmission efficiency can be improved.
  • the first conductive portion 111 further includes a second sub-portion S2, the second sub-portion S2 is located on the second side of the extension portion 180, and the second side of the extension portion 180 is opposite to the first side of the extension portion 180; the second conductive portion 112 extends across the extension 180 from the first side of the extension 180 in the first via V0 to extend to the second side of the extension 180 , and the second conductive portion 112 passes through the second side of the extension 180 .
  • a via hole V0 is in direct contact with the second sub-portion S2, so as to further reduce the contact resistance of the electrical connection between the first conductive portion 111, the extension portion 180 and the second conductive portion 112, and improve the signal transmission efficiency.
  • the gate insulating layer 200 is located between the gate T1g of the driving transistor T1 and the active layer T1a of the driving transistor T1, and the gate T1g of the driving transistor T1 is located on the side of the gate insulating layer 200 away from the base substrate 101; the second The insulating layer 202 is located on the side of the gate T1g of the driving transistor T1 away from the base substrate 101 , and the first via V0 penetrates through the gate insulating layer 200 and the second insulating layer 202 .
  • the extension part 180 includes a side surface intersecting with the upper surface, and the second conductive part 112 also covers the side surface of the extension part and is in contact with the side surface of the extension part 180; the gate insulating layer 200 includes the upper surface and the upper surface of the gate insulating layer.
  • the side surfaces where the surfaces intersect, the included angle between the side surface of the extension portion 180 and the plane where the upper surface of the extension portion 180 is located is the first included angle ⁇ 1, and the included angle close to the extension portion 180 is the first angle ⁇ 1.
  • FIG. 3C is another cross-sectional view of FIG. 2A along the section line II′. In the embodiment shown in FIG.
  • the second conductive portion 112 includes a middle portion 800 that is in direct contact with the extension portion 180 .
  • the included angle close to the extension portion 180 is the third included angle ⁇ 3
  • the first included angle ⁇ 1 is greater than the third included angle ⁇ 3
  • the third included angle ⁇ 3 is greater than
  • the second included angle ⁇ 2, that is, the second included angle ⁇ 2 is the smallest, facilitates the adhesion of the layer above the gate insulating layer 200 thereon, and the length of the second conductive portion 112 in the first direction is relative to the extension portion 180 below it.
  • the length in the first direction is large, so its resistance is large, and the third angle ⁇ 3 is smaller than the first angle ⁇ 1, so that the thickness of the second conductive portion 112 in the direction perpendicular to the substrate can be made larger, which is beneficial to The resistance of the second conductive portion 112 is reduced, and the angular relationship in FIG. 3B is more conducive to the stability of the structure.
  • the second capacitor electrode Cb is at least partially in the same layer as the first electrode T1s of the driving transistor T1 and has an integrated structure; the first capacitor electrode Ca is insulated from the second capacitor electrode Cb and is connected to the drive transistor T1.
  • the active layer T1g of the transistor T1 is in the same layer and has an integrated structure, and the second capacitor electrode Cb and the first capacitor electrode Ca constitute the two plates of the first capacitor C1 of the storage capacitor Cst.
  • the projection of the active layer of the driving transistor is located in the orthographic projection of the opaque light shielding layer 170 on the base substrate 101, the light shielding layer 170 is electrically connected to the second capacitance electrode Cb of the first capacitor, and the light shielding layer 170 is insulated from the first capacitor electrode Ca of the first capacitor and at least partially overlapped in the direction perpendicular to the base substrate 101 to serve as the third capacitor electrode Cc of the storage capacitor Cst, the third capacitor electrode Cc and the first capacitor electrode Ca
  • the two pole plates of the second capacitor C2 that constitute the storage capacitor Cst are connected in parallel with the first capacitor to increase the charge storage capacity of the capacitor and better realize the compensation function of the storage capacitor.
  • the third capacitor electrode Cc is located on the side of the first capacitor electrode Ca away from the second capacitor electrode Cb, and is electrically connected to the second capacitor electrode Cb through the No. 7 via hole shown in FIG. 3A to form a parallel capacitor structure, thereby increasing the storage capacity. Capacitance value of capacitor Cst.
  • the first electrode T1s of the driving transistor T1 is located on the side of the active layer T1a of the driving transistor T1 away from the base substrate 101, and the light shielding layer 170 is located on the side of the active layer T1a of the driving transistor T1 close to the base substrate 101 .
  • the second conductive portion 112 and the first electrode T1s of the driving transistor T1 are in the same layer and made of the same material; both are located in the third conductive layer 503 and can be formed by performing the same patterning process on the same film layer, which is conducive to simplifying the display substrate. Craftsmanship.
  • the display substrate 10 further includes signal lines. As shown in FIG. 3A , for example, the display substrate 10 further includes a plurality of signal lines extending along the first direction D1.
  • the signal lines may include data lines DL, power lines (for example, a first power supply providing a high power supply voltage VDD) line 240 or the second power line 250 for supplying the ground power supply voltage VSS), the detection line 230 or the auxiliary electrode line, and the like. As shown in FIG.
  • each second portion 152 intersects with at least one data line in a direction perpendicular to the base substrate 101, thereby defining a plurality of first hollow regions arranged along the second direction D2; Both of the two portions 162 cross at least one data line in a direction perpendicular to the base substrate 101 , thereby defining a plurality of second hollow regions arranged along the second direction D2 .
  • the yield of the device can be effectively improved.
  • the position where the signal lines cross is prone to short-circuit failure due to electrostatic breakdown of parasitic capacitance.
  • the channel can be cut off (for example, by laser cutting), The circuit structure can still work normally through the other channel.
  • the plurality of signal lines include a plurality of data lines DL, and the plurality of data lines DL are connected to each column of sub-pixels in the sub-pixel array in a one-to-one correspondence to provide data signals for the sub-pixels.
  • the plurality of data lines are divided into a plurality of data line groups corresponding to the plurality of pixel units in the pixel row.
  • each data line group includes a first sub-pixel The first data line DL1 connected to P1, the second data line DL2 connected to the second subpixel P2, and the third data line DL3 connected to the third subpixel P3.
  • the data lines DL1-DL3 connected to the pixel unit are located between the first sub-pixel P1 and the third sub-pixel P3. This setup can provide space for the setup of the detection and power lines.
  • the display substrate 10 further includes a plurality of detection lines 230 extending along the first direction D1, the detection lines 230 are used to connect with the detection sub-circuits (such as the third transistor T3) in the sub-pixel 100, and Connect this detection subcircuit to an external detection circuit.
  • the detection sub-circuits such as the third transistor T3
  • Connect this detection subcircuit to an external detection circuit.
  • at least one column of sub-pixels is spaced between each detection line 230 and any one of the plurality of data lines DL; that is, the detection line 230 is not directly adjacent to any data line DL.
  • FIG. 3A the display substrate 10 further includes a plurality of detection lines 230 extending along the first direction D1, the detection lines 230 are used to connect with the detection sub-circuits (such as the third transistor T3) in the sub-pixel 100, and Connect this detection subcircuit to an external detection circuit.
  • at least one column of sub-pixels is spaced between each detection line 230 and any one of the plurality of data lines
  • the first data line DL1 and the second data line DL2 are located between the first sub-pixel P1 and the second sub-pixel P2, and the third data line DL3 is located in the second sub-pixel Between P2 and the third sub-pixel P3, the detection line 230 is located on the side of the third sub-pixel P3 away from the first sub-pixel P1 of the second sub-pixel P2.
  • the signal delay on the data line caused by the resistance-capacitance load caused by the data line directly adjacent to the detection line is avoided, and the problem of uneven display caused by the delay is further avoided.
  • the signal transmitted on the data line DL is usually a high-frequency signal
  • setting the detection line 230 and the data line DL to not be directly adjacent to each other can prevent the detection line 230 from receiving high-frequency signal crosstalk during the external compensation charging and sampling process, thereby affecting the Sampling accuracy.
  • the three sub-pixels in the pixel unit share a detection line 230, and the detection line 230 is connected to the third transistor T3 in the three sub-pixels through the detection portion 231 extending along the second direction D2, respectively.
  • Diode T3d is electrically connected.
  • the detection line 230 is electrically connected to the detection part 231 through the via hole 12
  • the detection part 231 is electrically connected to the second electrode T3d of the third transistor T3 through the No. 10 via hole.
  • the first electrode T3s of the third transistor T3 is electrically connected to the first electrode contact region T3a1 of the third transistor T3 through the No. 6 via hole
  • the second electrode T3d of the third transistor T3 is electrically connected to the third transistor T3 through the No. 5 via hole.
  • the second pole contact region T3a2 is electrically connected.
  • the third transistor T3 and the second capacitor electrode Cb are provided in the same layer and connected as an integral structure.
  • the display substrate 10 further includes a plurality of first power supply lines 240 extending along the first direction D1, the plurality of first power supply lines 240 are configured to provide a first power supply voltage for a plurality of sub-pixels, the The power supply voltage is, for example, the high power supply voltage VDD.
  • the first power line 240 is, for example, located in the third conductive layer 503 .
  • at least one pixel column is spaced between each of the plurality of first power lines 240 and any one of the plurality of data lines; that is, the first power line 240 is not connected to any data line DL directly adjacent.
  • any one of the first power lines 240 and the detection part 231 do not overlap in the direction perpendicular to the base substrate 101 , that is, the first power line 240 is disposed at the interval corresponding to the adjacent detection parts 231 .
  • This arrangement reduces the overlap of the signal lines, thereby effectively reducing the parasitic capacitance between the signal lines and the signal delay caused thereby.
  • the first power line 240 is electrically connected to the second electrode T1d of the first transistor T1 of the directly adjacent sub-pixel (for example, the first sub-pixel P1 ) through the No. 3 via hole, for example, the power supply The line is integrated with the second electrode T1d of the first transistor T1.
  • the first power supply line 240 is electrically connected to the second electrode T1d of the first transistor T1 of the sub-pixel that is not directly adjacent to the first power supply line 240 through the connection electrode 241 .
  • the connection electrode 241 is electrically connected to the second electrode T1d of the first transistor T1 of the second sub-pixel or the fourth sub-pixel through the 11th via hole.
  • Fig. 5 is a cross-sectional view along section line A-A' of Fig. 3A.
  • the signal line when the signal line is the first power supply line that provides the high power supply voltage VDD, the signal line, that is, the first power supply line 240 includes stacking lines perpendicular to the base substrate 101 and in a direction away from the base substrate 101 in sequence.
  • the first layer 2401, the second layer 2402 and the third layer 2403, the first layer 2401 and the second layer 2402 are spaced apart; the first power line 240 also includes a signal line via V3, and the third layer 2403 passes through the signal line via hole V3 is electrically connected to the second layer 2402 and the first layer 2401 .
  • the first layer 2401 , the second layer 2402 and the third layer 2403 of the signal line are connected in parallel, which reduces the resistance of the signal line;
  • the via hole V3 is electrically connected to the second layer 2402 and the third layer 2403.
  • the contact resistance of the connection position is obviously reduced, and the transmission efficiency of the signal in the signal line is improved.
  • the manufacturing process of the display substrate is simplified.
  • the first layer 2401 is the same layer as the active layer T1a of the driving transistor T1
  • the second layer 2402 is the same layer and material as the gate electrode T1g of the driving transistor T1
  • the third layer 2403 is the same as the first electrode T1s of the driving transistor T1 layer and the same material.
  • the first layer 2401 further includes a semiconductor portion A3 that overlaps with the second layer 2402 in a direction perpendicular to the base substrate 101, is the same layer as the active layer T1a of the driving transistor T1, and is the same as the first conductor portion 111 constitutes an integral structure.
  • the first layer 2401 and the semiconductor portion A3 shielded by the second layer 2402 are simultaneously formed; at the same time, the same patterning process can be used to form the second layer.
  • the layer 2402 and the gate T1g of the driving transistor T1 are formed by the same patterning process to form the third layer 2403 and the first electrode T1s of the driving transistor T1 to simplify the process.
  • the first layer 2401 is located in the semiconductor layer 104
  • the second layer 2402 is located in the second conductive layer 502
  • the third layer 2403 is located in the third conductive layer 503 . In this way, in the case of reducing the resistance of the signal line, the structure and manufacturing process of the display substrate are greatly simplified.
  • the first layer 2401 includes a first conductor portion A1 , which is located on the first side of the second layer 2402 ; the third layer 2403 passes the signal line on the first side of the second layer 2402
  • the via V3 is in direct contact with the first conductor portion A1; the third layer 2403 extends from the first side of the first conductor portion A1 in the signal line via V3 to the second side of the first conductor portion A1 to contact the second layer 2402
  • At least part of the upper surface of the substrate 101 away from the base is in contact. In this way, the contact resistance of the electrical connection between the first conductor portion A1 , the second layer 2402 and the third layer 2403 can be further reduced, and the signal transmission efficiency can be improved.
  • the third layer 2403 is in direct contact with the upper surface of the second layer 2402 away from the base substrate 101 and the side surface of the second layer 2402 intersecting with the upper surface thereof, and the third layer 2403 is in direct contact with the first
  • the layers 2401 are in direct contact to further reduce the contact resistance of the electrical connection between the first layer 2401 such as the first conductor portion A1 , the second layer 2402 and the third layer 2403 , and improve the signal transmission efficiency.
  • the first layer 2401 further includes a second conductor portion A2 , the second conductor portion A2 is located on the second side of the second layer 2402 in the line width direction of the signal line, and the second conductor portion A2 of the second layer 2402 side is opposite to the first side of the second layer 2402; the third layer 2403 extends across the second layer 2402 from the first side of the second layer 2402 in the signal line via V3 in the line width direction of the signal line to extend to the second layer 2402.
  • the third layer 2403 is in direct contact with the second conductor portion A2 through the signal line via V3 on the second side of the second layer 2402, so as to increase the size of the third layer 2403, the second layer 2402 and the second conductor portion A2.
  • the contact area of the first layer 2401 reduces the contact resistance between the third layer 2403 and the second layer 2402 and between the third layer 2403 and the first layer 2401 .
  • the signal line via V3 includes a first portion V31 and a second portion V32 that communicate with each other.
  • the third layer 2403 is in direct contact with the first conductor portion A1 through the first portion V31 of the signal line via V3 on the first side of the second layer 2402; the third layer 2403 passes through the signal line via on the second side of the second layer 2402
  • the second portion V32 of V3 is in direct contact with the second conductor portion A2.
  • FIG. 3A and FIG. 3B take the signal line as the first power supply line for supplying the first power supply voltage to the first electrode T1s of the driving transistor T1 as an example.
  • the signal line may further include a data line DT connected to the second pole T2d of the data writing transistor T2 and configured to provide a data signal to the data writing transistor T2.
  • one or more signal line vias V3 may be provided on one signal line.
  • one first power line 240 for example, the first power line 240 may be provided with four signal line vias V3 .
  • the above-mentioned signal lines further include detection lines 230, and one detection line 230 may include one or more signal line vias V3.
  • the above-mentioned signal line further includes a second power line 250, and the second power line 250 provides a low voltage VSS for the light emitting device.
  • a second power line 250 may include one or more signal line vias V3.
  • the second power line 250 is located in the third conductive layer 503, and is connected to the second electrode 122 such as the cathode through the 13-gauge hole.
  • the second power line 250 is connected to the second electrode layer through a 14-gauge hole to form a double-layer wiring, thereby reducing the resistance of the second power line 250 ; for example, a second power line 250 includes Multiple 14-gauge holes.
  • the detection line 230 is connected to the second electrode layer through a 15-gauge hole to form a double-layered trace, thereby reducing the resistance of the detection line 230; for example, one detection line 230 includes a plurality of 15-gauge holes.
  • At least one embodiment of the present disclosure further provides a display panel including any one of the above display substrates 10 .
  • the above-mentioned display substrate 10 provided in at least one embodiment of the present disclosure may include the light-emitting element 125 or may not include the light-emitting element 125 , that is, the light-emitting element 125 may be formed in a panel factory after the display substrate 10 is completed.
  • the display panel provided by the embodiment of the present disclosure further includes the light-emitting element 125 in addition to the display substrate 10 .
  • the display panel is an OLED display panel
  • the display substrate 10 included in the display panel is an OLED display substrate.
  • At least one embodiment of the present disclosure further provides a display device 30.
  • the display device 30 includes any of the above-mentioned display substrates 10 or display panels 20.
  • the display device in this embodiment may be: a display, an OLED Panels, OLED TVs, electronic paper, mobile phones, tablet computers, notebook computers, digital photo frames, navigators and other products or components with display functions.
  • At least one embodiment of the present disclosure also provides a method for fabricating the above-mentioned display substrate.
  • a manufacturing method includes: providing a base substrate; forming a plurality of pixels on the base substrate, wherein at least some of the pixels in the plurality of pixels include a plurality of sub-pixels, and each of the plurality of sub-pixels includes a light-emitting element and a driver
  • the pixel circuit in which the light-emitting element emits light, the pixel circuit includes a light-emitting device, a storage capacitor, a driving transistor and a data writing transistor, each of the driving transistor and the data writing transistor includes an active layer, a gate, a a first electrode and a second electrode; a first electrode of the drive transistor is configured to receive a first power supply voltage, and a second electrode of the drive transistor is connected to a light emitting device to be configured to control the light emitting device to emit light; and A first via hole is formed in at least some of the sub-pixels, wherein the first
  • a method for manufacturing a display substrate includes: forming a semiconductor layer; forming a gate insulating layer covering the semiconductor layer on a side of the semiconductor layer away from the base substrate; A gate conductive layer is formed on one side of the base substrate; the gate conductive layer is patterned by a patterning process to form the gate of the driving transistor; the gate insulating layer is formed by using the gate of the driving transistor as an etching barrier layer.
  • the semiconductor layer includes a portion shielded by the gate insulating layer and a portion not shielded by the gate insulating layer; and a portion of the semiconductor layer not shielded by the gate insulating layer
  • the part shielded by the insulating layer is subjected to conducting treatment to form a first conductive part, and the part shielded by the gate insulating layer is not conductive to form the active layer and the connection part of the driving transistor, wherein the gate of the driving transistor is not conductive.
  • the pole includes a main body part and an extension part connected to the main body part, the projection of the main body part overlaps the projection of the active layer of the driving transistor, the extension part extends from the main body part, the extension part passes through the first via hole is electrically connected to the gate of the driving transistor and the active layer of the data writing transistor; the connection portion and the extension portion overlap in a direction perpendicular to the base substrate, And the first conductive part is connected with the active layer of the data writing transistor into an integrated structure.
  • forming the first via hole includes: after forming the active layer of the driving transistor and the active layer of the data writing transistor, forming a gate of the driving transistor at a position away from the base substrate forming a first insulating layer on the side, wherein the first insulating layer covers the gate electrode of the driving transistor, the gate electrode of the data writing transistor, and the gate insulating layer; and performing patterning on the first insulating layer process to form the first via hole, wherein the first via hole exposes at least part of the gate of the driving transistor and at least part of the first conductive part; the manufacturing method further includes: in the driving transistor A second conductive portion is formed on a side of the gate away from the base substrate, wherein the second conductive portion is electrically connected to the gate of the driving transistor and the first conductive portion through the first via hole , the first conductive portion and the second conductive portion constitute the first electrode of the data writing transistor. Therefore, the first electrode of the data writing transistor is electrically connected to the gate of the driving transistor and the active layer of the data writing transistor.
  • the method for manufacturing a display substrate further includes: forming a signal line, including forming a first layer, a second layer and a third layer that are stacked in sequence in a direction perpendicular to the base substrate and in a direction away from the base substrate, The first layer is spaced apart from the third layer, the signal line further includes a signal line via hole, and the third layer is connected to the second layer and the third layer through the signal line via hole.
  • a signal line including forming a first layer, a second layer and a third layer that are stacked in sequence in a direction perpendicular to the base substrate and in a direction away from the base substrate, The first layer is spaced apart from the third layer, the signal line further includes a signal line via hole, and the third layer is connected to the second layer and the third layer through the signal line via hole.
  • the first layer and the active layer of the driving transistor are formed at the same time through the same conductorization process through the portion of the semiconductor layer that is not shielded by the gate insulating layer; the second layer and the The gate of the driving transistor is simultaneously formed by performing the same patterning process on the gate conductive layer; the third layer and the first electrode of the driving transistor are simultaneously formed by performing the same patterning process on the same film layer.
  • FIGS. 4A-4D and taking the case of two pixels, each pixel including three sub-pixels as an example, the manufacturing method of the display substrate provided by the embodiment of the present disclosure will be exemplarily described.
  • the present disclosure will The embodiment is not limited to this.
  • Figures 3A-3B and Figures 4A-4D show two pixels of the display substrate, and each pixel includes three sub-pixels.
  • Figures 4A-4D respectively show the first conductive layer, Patterns of the semiconductor layer, the second conductive layer, and the third conductive layer.
  • the manufacturing method includes the following steps S1-S5.
  • Step S1 forming a first conductive material layer, and performing a patterning process on the first conductive material layer to form the first conductive layer 501 as shown in FIG. 4A , that is, the light shielding layer 170 and the third capacitor electrode Cc of the storage capacitor Cst .
  • This patterning process also forms the detection portion 231 and the connection electrode 241 insulated from each other.
  • Step S2 forming a second insulating layer 202 on the first conductive layer 501 and forming a semiconductor material layer on the first insulating layer, and performing a patterning process on the semiconductor material layer to form the semiconductor layer 104 shown in FIG. 4B , that is, the active layer T1a of the first transistor T1, the active layer T2a of the second transistor T2, and the active layer T3a of the third transistor T3 are formed spaced apart from each other.
  • the semiconductor material layer is patterned, the first layer 2401 of the signal line shown in FIG. 5 is formed through the same patterning process, so as to simplify the manufacturing process of the display substrate.
  • Step S3 forming a gate insulating layer 200 on the semiconductor layer 104 and forming a second conductive material layer on the second insulating layer, and performing a patterning process on the second conductive material layer to form a second conductive layer as shown in FIG. 4C 502, that is, the gate T1g of the first transistor T1, the gate T2g of the second transistor T2 and the gate T3g of the third transistor T3 are formed which are insulated from each other.
  • FIG. 4C also shows extension 180 .
  • the second layer 2402 of the signal line shown in FIG. 5 is formed in the second conductive layer 502 using the same patterning process, that is, the second layer and the gate of the driving transistor pass through
  • the gate conductive layer is simultaneously formed by the same patterning process, so as to simplify the manufacturing process of the display substrate.
  • the second conductive layer 502 further includes the first scan line 150 and the second scan line 160 which are insulated from each other.
  • the line widths of the first scan lines 150 and the second scan lines 160 are in the range of 5-15 microns.
  • the first scan line 150 is integrated with the gate T2g of the second transistor T2 of the corresponding row of sub-pixels, and the second scan line 160 is respectively connected to the gate T3g of the third transistor T3 of the corresponding row of sub-pixels. an integrated structure.
  • Step S4 adopting a self-alignment process, using the second conductive layer 502 as a mask to conduct conductorization treatment (eg plasma treatment, doping treatment, etc.) on the semiconductor layer 204, so that the semiconductor layer 204 is not covered by the second conductive layer
  • the part covered by the conductive layer 502 is conductive, so as to obtain the first capacitor electrode Ca, and the part of the active layer of each transistor located on both sides of the channel region is conductive to form the first electrode contact region and the second electrode respectively.
  • a contact area, the first electrode contact area and the second electrode contact area are respectively used for electrical connection with the first electrode and the second electrode of the transistor.
  • connection 720 is also shown in Figure 4B.
  • the semiconductor layer 204 is subjected to conducting treatment using the second conductive layer 502 as a mask, the first conductor portion A1, the second conductor portion A2 and the semiconductor portion A3 shown in FIG. 5 are simultaneously formed, that is, the first layer and the The active layer of the driving transistor is simultaneously formed through the same conductorization process on the part of the semiconductor layer that is not shielded by the gate insulating layer, so as to simplify the manufacturing process of the display substrate.
  • an etching process is performed on the gate insulating layer 200 before conducting the conductorization treatment on the semiconductor layer 104, so that the entire area of the gate insulating layer 200 not covered by the second conductive layer 502 is etched, that is, the second insulating layer
  • the layer 103 coincides with the second conductive layer 502 in a direction perpendicular to the base substrate 101 .
  • the implanted ions may not be blocked by the gate insulating layer 200 when the semiconductor layer 204 is conductively treated by ion implantation in the region not covered by the second conductive layer 202 .
  • Step S5 forming a first insulating layer 201 on the second conductive layer 502, forming a third conductive material layer on the first insulating layer 201, and performing a patterning process on the third conductive material layer to form as shown in FIG. 4D
  • the third conductive layer 503, that is, the first electrode T1s and the second electrode T1d of the first transistor T1, the first electrode T2s and the second electrode T2d of the second transistor T2, and the first electrode T3s and the second electrode of the third transistor T3 are formed.
  • the second pole T3d When the third conductive material layer is patterned, the third layer 2403 shown in FIG. 5 is formed simultaneously by the same patterning process, that is, the third layer and the first electrode of the driving transistor are simultaneously formed by performing the same patterning process on the same film layer. , to simplify the manufacturing process of the display substrate.
  • the third conductive layer 503 further includes the data line DL, the detection line 230 and the first power line 240 which are insulated from each other.
  • the line width of the data line DL is in the range of 5-15 ⁇ m
  • the line width of the detection line 230 is in the range of 5-30 ⁇ m
  • the line width of the first power line 240 is in the range of 5-30 ⁇ m.
  • the first power supply line 240 and the second electrode T1 d of the first transistor T1 in the sub-pixel directly adjacent thereto have an integrated structure.
  • each data line 110 and the second electrode T2d of the second transistor T2 in the sub-pixel connected thereto are integrated.
  • the materials of the semiconductor material layer include but are not limited to silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials (hexathiophene, etc.) , polythiophene, etc.).
  • silicon-based materials amorphous silicon a-Si, polycrystalline silicon p-Si, etc.
  • metal oxide semiconductors IGZO, ZnO, AZO, IZTO, etc.
  • organic materials hexathiophene, etc.
  • the first conductive material layer is a light-shielding conductive material, such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) and An alloy material composed of the above metals.
  • the first conductive material layer may be a molybdenum-titanium alloy, eg, with a thickness of 50-100 nanometers.
  • materials of the second conductive material layer and the third conductive material layer may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) ) and alloy materials composed of the above metals; or conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), etc.
  • the second conductive material layer is a laminated structure of molybdenum-titanium alloy and copper, for example, the thickness of the molybdenum-titanium alloy is 30-50 nanometers, and the thickness of copper is 300-400 nanometers.
  • the third conductive material layer is a laminated structure of molybdenum-titanium alloy and copper, for example, the thickness of the molybdenum-titanium alloy is 30-50 nanometers, and the thickness of copper is 400-700 nanometers.
  • the materials of the semiconductor material layer include but are not limited to silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials (hexathiophene, etc.) , polythiophene, etc.).
  • silicon-based materials amorphous silicon a-Si, polycrystalline silicon p-Si, etc.
  • metal oxide semiconductors IGZO, ZnO, AZO, IZTO, etc.
  • organic materials hexathiophene, etc.
  • the material of the semiconductor material layer is indium gallium zinc oxide, and the thickness is 30-50 nanometers.
  • the second insulating layer 202, the gate insulating layer 200, and the first insulating layer 201 are, for example, inorganic insulating layers, such as silicon oxides such as silicon oxide, silicon nitride, and silicon oxynitride, silicon nitrides, or silicon oxynitrides. materials, or aluminum oxide, titanium nitride, etc., including metal oxynitride insulating materials.
  • these insulating layers may also be organic materials, such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA), etc., which are not limited in the embodiment of the present disclosure.
  • the material of the second insulating layer 202 is silicon oxide, and the thickness is 300-500 nanometers.
  • the material of the gate insulating layer 200 is silicon oxide, and the thickness is 100-160 nanometers.
  • the material of the third insulating layer is silicon oxide, and the thickness is 400-600 nanometers.
  • a third insulating layer 203 , a color filter layer and a fourth insulating layer 204 may be formed in sequence on the third conductive layer 503 , and the first electrode of the light-emitting element may be formed on the fourth insulating layer 204 123, then the pixel defining layer 206 is formed on the first electrode 123, and the light emitting layer 124 and the second electrode 122 are formed in sequence, thus forming the display substrate 10 as shown in FIG. 3A.
  • forming the color filter layer may include first forming a red color filter layer and performing a patterning process on the red color filter layer to form a color filter portion corresponding to the red sub-pixels, and then forming a green color filter layer and patterning the green color filter layer The process forms a color filter portion corresponding to the green sub-pixel, and then forms a blue color film layer and performs a patterning process on the blue color film layer to form a color filter portion corresponding to the blue sub-pixel.
  • the thicknesses of the red color filter layer, the green color filter layer and the blue color filter layer are respectively 2000-3000 nanometers, that is, the thickness of each color filter part is 2000-3000 nanometers.
  • a light shielding portion can be formed between adjacent sub-pixels by overlapping the color filter portions to avoid cross-coloring.
  • the above-mentioned patterning process may adopt a conventional photolithography process, for example, including steps of photoresist coating, exposure, development, drying, and etching.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种显示基板及其制作方法以及显示装置。该显示基板(10)包括呈阵列排布的多个像素(100)；至少部分像素(100)包括多个子像素，至少部分子像素包括发光元件和驱动发光元件发光的像素电路，像素电路包括存储电容(Cst)、驱动晶体管(T1)和数据写入晶体管(T2)，驱动晶体管(T1)包括有源层(T1a)、栅极(T1g)、第一极(T1s)和第二极(T1d)，数据写入晶体管(T2)包括有源层(T2a)、栅极(T2g)、第一极(T2s)和第二极(T2d)；驱动晶体管(T1)的第一极(T1s)接收第一电源电压，驱动晶体管(T1)的第二极(T1d)与发光器件连接以控制发光器件发光；至少部分子像素包括第一过孔(V0)，数据写入晶体管(T2)的第一极(T2s)通过第一过孔(V0)与驱动晶体管(T1)的栅极(T1g)以及数据写入晶体管(T2)的有源层(T1a)电连接，以减小数据写入晶体管(T2)的第一极(T2s)与驱动晶体管(T1)的栅极(T1g)和数据写入晶体管(T2)的有源层(T2a)连接位置的电阻，提高信号传输效率，并简化制作工艺。

Description

显示基板及其制作方法以及显示装置 技术领域
本公开至少一实施例涉及一种显示基板及其制作方法以及显示装置。
背景技术
在显示领域，有机发光二极管(OLED)显示面板具有自发光、对比度高、能耗低、视角广、响应速度快、可用于挠曲性面板、使用温度范围广、制造简单等特点，具有广阔的发展前景。
发明内容
本公开至少一实施例提供一种显示基板，显示基板包括衬底基板，衬底基板设置有呈阵列排布的多个像素；所述多个像素中的至少部分像素包括多个子像素，所述多个子像素中的至少部分子像素包括发光元件和驱动所述发光元件发光的像素电路，所述像素电路包括存储电容、驱动晶体管和数据写入晶体管，所述驱动晶体管包括有源层、栅极、第一极和第二极，所述数据写入晶体管包括有源层、栅极、第一极和第二极；所述驱动晶体管的第一极配置为接收第一电源电压，所述驱动晶体管的第二极与发光器件连接以配置为控制所述发光器件发光；所述多个子像素中的至少部分子像素包括第一过孔，所述数据写入晶体管的第一极通过所述第一过孔与所述驱动晶体管的栅极以及所述数据写入晶体管的有源层电连接。
例如，本公开至少一实施例提供的显示基板中，所述驱动晶体管的栅极包括主体部和与所述主体部连接的延伸部，所述主体部在所述衬底基板上的正投影与所述驱动晶体管的有源层在所述衬底基板上的正投影重叠，所述延伸部自所述主体部延伸，所述延伸部通过所述第一过孔与所述数据写入晶体管的第一极和以及所述数据写入晶体管的有源层电连接。
例如，本公开至少一实施例提供的显示基板中，所述数据写入晶体管的第一极包括在垂直于所述衬底基板的方向上彼此堆叠的第一导电部和第二导电部，所述第二导电部位于所述第一导电部的远离所述衬底基板的一侧；所述驱动晶体管的栅极位于所述第一导电部的靠近所述第二导电部的一侧且与所述第一导电部间隔开，所述第二导电部通过所述第一过孔与所述驱动晶体管的栅极以及所述第一导电部接触；所述显示基板还包括连接部，例如，本公开至少一实施例提供的显示基板中，与所述延伸部在垂直于所述衬底基板的方向重叠，且将所述第一导电部与所述数据写入晶体管的有源层连接为一体结构。
例如，本公开至少一实施例提供的显示基板中，所述第二导电部的材料和所述连接部的材料包括相同的半导体材料，并且所述第一导电部所包括的半导体材料被导体化。
例如，本公开至少一实施例提供的显示基板中，所述第一导电部包括：
第一子部，位于所述延伸部的第一侧，其中，所述第二导电部在所述第一侧通过所述第一过孔与所述第一子部直接进接触；
所述第二导电部从所述延伸部的第一侧在所述第一过孔中延伸至所述延伸部以与所述延伸部的远离所述衬底基板的上表面的至少部分接触。
例如，本公开至少一实施例提供的显示基板中，所述第一导电部还包括：
第二子部，位于所述延伸部的第二侧，其中，所述第二侧与第一侧相对，所述第二导电部从所述延伸部的第一侧在所述第一过孔中延伸跨过所述延伸部以延伸至所述延伸部的第二侧，所述第二导电部在所述第二侧通过所述第一过孔与所述第二子部直接接触。
例如，本公开至少一实施例提供的显示基板还包括：
栅绝缘层，位于所述驱动晶体管的栅极与所述驱动晶体管的有源层之间，所述驱动晶体管的栅极位于所述栅绝缘层的远离所述衬底基板的一侧；
第一绝缘层，位于所述驱动晶体管的栅极的远离所述衬底基板的一侧，其中，所述第一过孔贯穿所述栅绝缘层和所述第一绝缘层；
栅绝缘层包括上表面和与所述栅绝缘层的上表面相交的侧表面，所述延伸部的侧表面与所述延伸部的上表面所在的平面的夹角中靠近所述延伸部的夹角为第一夹角，所述栅绝缘层的侧表面与所述延伸部的上表面所在的平面的夹角中靠近所述延伸部的夹角为第二夹角，所述第二导电部包括与所述延伸部直接接触的中间部分，所述中间部分的侧表面与所述延伸部的上表面所在的平面的夹角中靠近所述延伸部的夹角为第三夹角；
所述第一夹角大于所述第二夹角，或者，所述第一夹角大于所述第三夹角且所述第三夹角大于所述第二夹角。
例如，本公开至少一实施例提供的显示基板中，所述存储电容包括：
第二电容电极，至少部分与所述驱动晶体管的第一极同层且为一体结构；以及
第一电容电极，与所述第二电容电极绝缘且与所述驱动晶体管的有源层同层且为一体结构，其中，所述第二电容电极和所述第一电容电极构成所述存储电容的第一电容的两个极板。
例如，本公开至少一实施例提供的显示基板还包括：
不透光的遮光层，其中，所述驱动晶体管的有源层位于所述遮光层在所述衬底基板上的正投影内，所述遮光层与所述第一电容的第二电容电极电连接，并且，所述遮光层与所述第一电容的第一电容电极绝缘且在垂直于所述衬底基板的方向上至少部分重叠以作为所述存储电容的第三电容电极，所述第三电容电极与所述第一电容电极构成所述存储电容的第二电容的两个极板，所述第二电容与所述第一电容并联。
例如，本公开至少一实施例提供的显示基板中，所述驱动晶体管的第一极位于所述驱动晶体管的有源层的远离所述衬底基板的一侧，所述遮光层位于所述驱动晶体管的有源层的靠近所述衬底基板的一侧。
例如，本公开至少一实施例提供的显示基板中，所述第二导电部与所述驱动晶体管的第一极同层且材料相同。
例如，本公开至少一实施例提供的显示基板还包括：
信号线，包括在垂直于所述衬底基板且沿远离所述衬底基板的方向依次堆叠的第一层、第二层和第三层，其中，所述第一层与所述第二层间隔开，所述信号线还包括信号线过孔，所述第三层通过所述信号线过孔与所述第二层和所述第一层电连接。
例如，本公开至少一实施例提供的显示基板中，所述第一层与所述驱动晶体管的有源层同层，所述第二层与所述驱动晶体管的栅极同层且材料相同，所述第三层与所述驱动晶体管的第一极同层且材料相同。
例如，本公开至少一实施例提供的显示基板中，所述第一层包括：
第一导体部，位于所述第二层的第一侧，其中，所述第三层在所述第二层的第一侧通过所述信号线过孔与所述第一导体部直接接触；所述第三层从所述第一导体部的第一侧在所述信号线过孔中延伸至所述第一导体部的第二侧以与所述第二层的远离所述衬底基板的上表面的至少部分接触。
例如，本公开至少一实施例提供的显示基板中，所述第三层与所述第二层的远离所述衬底基板的上表面和所述第二层的与其上表面相交的侧表面直接接触，且所述第三层与所述第一层直接接触。
例如，本公开至少一实施例提供的显示基板中，所述第一层还包括：
第二导体部，位于所述第二层在所述信号线的线宽方向上的第二侧，其中，所述第二层的第二侧与所述第二层的第一侧相对，所述第三层从所述第二层的第一侧在所述信号线过孔中沿所述信号线的线宽方向延伸跨过所述第二层以延伸至所述第二层的第二侧，所述第三层在所述第二层的第二侧通过所述信号线过孔与所述第二导体部直接接触。
例如，本公开至少一实施例提供的显示基板中，所述第一层还包括：
半导体部，在垂直于所述衬底基板的方向上与所述第二层重叠，与所述驱动晶体管的有源层同层，且与所述第一导体部构成一体结构。
例如，本公开至少一实施例提供的显示基板中，还包括：
数据线，与所述数据写入晶体管的第二极连接且配置为给所述数据写入晶体管提供数据信号，其中，所述信号线包括所述数据线。
例如，本公开至少一实施例提供的显示基板中，还包括：
第一电源线，配置为给所述驱动晶体管的第一极提供第一电源电压，其中，所述信号线包括所述第一电源线。
本公开至少一实施例还提供一种显示装置，该显示装置包括本公开实施例提供的任意一种的显示基板。
本公开至少一实施例还提供一种显示基板的制作方法，该制作方法包括：提供衬底基板；在衬底基板上形成多个像素，其中，所述多个像素中的至少部分像素包括多个子像素， 所述多个子像素的每个包括发光元件和驱动所述发光元件发光的像素电路，所述像素电路包括发光器件、存储电容、驱动晶体管和数据写入晶体管，所述驱动晶体管和所述数据写入晶体管的每个包括有源层、栅极、第一极和第二极；所述驱动晶体管的第一极配置为接收第一电源电压，所述驱动晶体管的第二极与发光器件连接以配置为控制所述发光器件发光；以及在所述多个子像素中的至少部分子像素中形成第一过孔，其中，所述数据写入晶体管的第一极通过所述第一过孔与所述驱动晶体管的栅极以及所述数据写入晶体管的有源层电连接。
例如，本公开至少一实施例还提供一种显示基板的制作方法包括：形成半导体层；在所述半导体层的远离所述衬底基板的一侧形成覆盖所述半导体层的栅绝缘层；在所述栅绝缘层的远离所述衬底基板的一侧形成栅导电层；通过构图工艺对所述栅导电层进行构图以形成所述驱动晶体管的栅极；以所述驱动晶体管的栅极作为刻蚀阻挡层对所述栅绝缘层执行构图工艺，以暴露部分所述半导体层，其中，所述半导体层包括被所述栅绝缘层遮挡的部分和未被所述栅绝缘层遮挡的部分；以及对所述半导体层的未被栅绝缘层遮挡的部分进行导体化处理以形成第一导电部，被所述栅绝缘层遮挡的部分未被导体化以构成所述驱动晶体管的有源层和连接部，其中，述驱动晶体管的栅极包括主体部和与所述主体部连接的延伸部，所述主体部的投影与所述驱动晶体管的有源层的投影重叠，所述延伸部自所述主体部延伸，所述延伸部通过所述第一过孔与所述驱动晶体管的栅极和以及所述数据写入晶体管的有源层电连接；所述连接部与所述延伸部在垂直于所述衬底基板的方向重叠，且将所述第一导电部与所述数据写入晶体管的有源层连接为一体结构。
例如，在本公开至少一实施例还提供一种显示基板的制作方法中，形成所述第一过孔包括：在形成所述驱动晶体管的有源层和所述数据写入晶体管的有源层之后，在所述驱动晶体管的栅极的远离所述衬底基板的一侧形成第一绝缘层，其中，所述第一绝缘层覆盖所述驱动晶体管的栅极、所述数据写入晶体管的栅极和所述栅绝缘层；以及对所述第一绝缘层执行构图工艺以形成所述第一过孔，其中，所述第一过孔暴露所述驱动晶体管的栅极至少部分以及所述第一导电部的至少部分；制作方法还包括：在所述驱动晶体管的栅极的远离所述衬底基板的一侧形成第二导电部，其中，所述第二导电部通过所述第一过孔与所述驱动晶体管的栅极以及所述第一导电部电连接，所述第一导电部与所述第二导电部构成所述数据写入晶体管的第一极。
例如，本公开至少一实施例还提供一种显示基板的制作方法还包括：形成信号线，包括形成在垂直于所述衬底基板且沿远离所述衬底基板的方向上依次堆叠的第一层、第二层和第三层，其中，所述第一层与所述第三层间隔开，所述信号线还包括信号线过孔，所述第三层通过所述信号线过孔与所述第二层和所述第一层电连接。
例如，在本公开至少一实施例还提供一种显示基板的制作方法中，所述第一层与所述驱动晶体管的有源层通过所述半导体层的未被所述栅绝缘层遮挡的部分进行同一所述导体化处理工艺同时形成；所述第二层与所述驱动晶体管的栅极通过对所述栅导电层进行同一 构图工艺同时形成；所述第三层与所述驱动晶体管的第一极通过对同一膜层执行同一构图工艺同时形成。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本公开至少一实施例提供的显示基板的示意图；
图2A为本公开至少一实施例提供的显示基板的像素电路图；
图2B-图2D为本公开实施例提供的像素电路的驱动方法的信号时序图；
图3A为本公开至少一实施例提供的一种显示基板的子像素的结构示意图；
图3B为图2A沿剖面线I-I’的一种剖视图；
图3C为图2A沿剖面线I-I’的另一种剖视图；
图4A为本公开至少一实施例提供的显示基板中的第一导电层的平面示意图；
图4B为本公开至少一实施例提供的显示基板中的半导体层的平面示意图；
图4C为本公开至少一实施例提供的显示基板中的第二导电层的平面示意图；
图4D为本公开至少一实施例提供的显示基板中的第三导电层的平面示意图；
图4E为本公开至少一实施例提供的显示基板中的第一电极的平面示意图；
图4F为本公开至少一实施例提供的显示基板中的第一导电层与半导体层堆叠的平面示意图；
图4G为本公开至少一实施例提供的显示基板中的第一导电层、半导体层与第二导电层堆叠的平面示意图；
图4H为本公开至少一实施例提供的显示基板中的第一导电层、半导体层、第二导电层与第三导电层堆叠的平面示意图；
图5为图3A沿剖面线A-A’的剖视图；
图6为本公开至少一实施例提供的显示装置的示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现 在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开中的附图并不是严格按实际比例绘制，显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，各个结构的具体地尺寸和数量可根据实际需要进行确定。本公开中所描述的附图仅是结构示意图。
本公开至少一实施例提供一种显示基板，该显示基板包括衬底基板，衬底基板设置有呈阵列排布的多个像素；所述多个像素中的至少部分像素包括多个子像素，所述多个子像素中的至少部分子像素包括发光元件和驱动所述发光元件发光的像素电路，所述像素电路包括存储电容、驱动晶体管和数据写入晶体管，所述驱动晶体管包括有源层、栅极、第一极和第二极，所述数据写入晶体管包括有源层、栅极、第一极和第二极；所述驱动晶体管的第一极配置为接收第一电源电压，所述驱动晶体管的第二极与发光器件连接以配置为控制所述发光器件发光；所述多个子像素中的至少部分子像素包括第一过孔，所述数据写入晶体管的第一极通过所述第一过孔与所述驱动晶体管的栅极以及所述数据写入晶体管的有源层电连接。
本公开实施例提供的显示基板中，数据写入晶体管的第一极通过仅第一过孔这一个过孔与驱动晶体管的栅极以及数据写入晶体管的有源层电连接，与其他连接方式相比，明显减小了该连接位置的接触电阻，提高了信号传输效率，同时，简化了显示基板制作工艺。
示例性地，图1为本公开至少一实施例提供的显示基板的示意图。如图1所示，显示基板10包括呈阵列排布的多个像素100，多个像素100中的至少部分像素100包括多个子像素，多个子像素中的至少部分子像素包括发光元件和驱动发光元件发光的像素电路，像素电路包括存储电容、驱动晶体管和数据写入晶体管，驱动晶体管包括有源层、栅极、第一极和第二极，所述数据写入晶体管包括有源层、栅极、第一极和第二极。驱动晶体管的第一极配置为接收第一电源电压，驱动晶体管的第二极与发光器件连接以配置为控制发光器件发光。例如多个像素100中的部分像素为虚拟像素(dummy pixel)101，虚拟像素1000不参与显示工作，每个虚拟像素1000包括多个虚拟子像素，而不包含发挥显示驱动作用的子像素。例如，该显示基板10是有机发光二极管(OLED)显示基板，该发光元件为OLED。该显示基板10还可以包括多条扫描线、多条数据线以用于为该多个子像素提供扫描信号(控制信号)和数据信号，从而驱动该多个子像素。根据需要，该显示基板10还可以进一步包括电源线、检测线等。
该像素电路包括用于驱动发光元件发光的驱动子电路和用于检测该子像素电特性以实现外部补偿的检测子电路。本公开实施例对于该像素电路的具体结构不作限制。
例如，图2A示出了一种用于该显示基板的一种3T1C像素电路的示意图。本公开实施例提供的显示基板的像素电路也不限于是3T1C像素电路，本实施例以显示基板10的像素电路为3T1C像素电路为例对显示基板的结构进行说明。根据需要，该像素电路还可以进 一步包括补偿电路、复位电路等，本公开的实施例对此不作限制。
参照图2A，该像素电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容Cst。第一晶体管T1即本申请所述的驱动晶体管，第二晶体管T2即本申请所述的数据写入晶体管。第二晶体管T2的第一极与存储电容Cst的第一电容电极Ca和第一晶体管T1的栅极电连接，第二晶体管T2的第二极配置为接收数据信号DT，第二晶体管T2配置为响应于第一控制信号G1将该数据信号DT写入第一晶体管T1的栅极和存储电容Cst；第一晶体管T1的第一极与存储电容Cst的第二电容电极Cb电连接，并配置为与发光元件的第一电极电连接，第一晶体管T1的第二极配置为接收第一电源电压V1(例如为高电源电压VDD)，第一晶体管T1配置为在第一晶体管T1的栅极的电压的控制下控制用于驱动发光元件的电流；第三晶体管T3的第一极与第一晶体管T1的第一极以及存储电容Cst的第二电容电极Cb电连接，第三晶体管T3的第二极配置为与检测线230连接以连到外部检测电路21，第三晶体管T3配置为响应于第二控制信号G2检测所属的子像素的电特性以实现外部补偿；该电特性例如包括第一晶体管T1的阈值电压和/或载流子迁移率，或者发光元件的阈值电压、驱动电流等。该外部检测电路21例如为包括数模转换器(DAC)和模数转换器(ADC)等的常规电路，本公开的实施例对此不作赘述。
例如，图2A所示的存储电容Cst还包括第三电容电极Cc，该第三电容电极Cc位于第一电容电极Ca远离第二电容电极Cb的一侧且与第二电容电极Cb通过图3A所示的7号过孔彼此电连接从而形成并联电容的结构，增大存储电容Cst的电容值。例如，在垂直于衬底基板101的方向上，该第三电容电极Cc、第二电容电极Cb、第一电容电极Ca三者均彼此重叠。
本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)，关闭电压为高电平电压(例如，5V、10V或其他合适的电压)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)。需要说明的是，在下面的描述中均以图2A中的晶体管为N型晶体管为例进行说明，然而不作为对本公开的限制。
下面结合图2B-图2D所示的信号时序图对图2A所示的像素电路的工作原理进行说明，其中图2B示出了该像素电路在显示过程的信号时序图，图2C和图2D示出了该像素电路在检测过程的信号时序图。
例如，如图2B所示，每一帧图像的显示过程包括数据写入和复位阶段1以及发光阶段2。图2B示出了每个阶段中各个信号的时序波形。该3T1C像素电路的一种工作过程包 括：在数据写入和复位阶段1，第一控制信号G1和第二控制信号G2均为开启信号，第二晶体管T2和第三晶体管T3导通，数据信号DT经第二晶体管T2传输至第一晶体管T1的栅极，第一开关K1关闭，模数转换器通过检测线230及第三晶体管T3向发光元件的第一电极(例如OLED的阳极)写入复位信号，第一晶体管T1导通并产生驱动电流将发光元件的第一电极充电至工作电压；在发光阶段2，第一控制信号G1和第二控制信号G2均为关闭信号，由于存储电容Cst的自举效应，存储电容Cst两端的电压保持不变，第一晶体管T1工作在饱和状态且电流不变，并驱动发光元件发光。
例如，图2C示出了该像素电路在进行阈值电压的检测时的信号时序图。该3T1C像素电路的一种工作过程包括：第一控制信号G1和第二控制信号G2均为开启信号，第二晶体管T2和第三晶体管T3导通，数据信号DT经第二晶体管T2传输至第一晶体管T1的栅极；第一开关K1关闭，模数转换器通过检测线230及第三晶体管T3向发光元件的第一电极(节点S)写入复位信号，第一晶体管T1导通并对节点S进行充电直至第一晶体管截止，数模转换器对检测线230上的电压取样即可得到第一晶体管T1的阈值电压。该过程例如可以在显示装置关机时进行。
例如，图2D示出了该像素电路在进行载流子迁移率的检测时的信号时序图。该3T1C像素电路的一种工作过程包括：在第一阶段，第一控制信号G1和第二控制信号G2均为开启信号，第二晶体管T2和第三晶体管T3导通，数据信号DT经第二晶体管T2传输至第一晶体管T1的栅极；第一开关K1关闭，模数转换器通过检测线230及第三晶体管T3向发光元件的第一电极(节点S)写入复位信号；在第二阶段，第一控制信号G1为关闭信号，第二控制信号G1为开启信号，第二晶体管T2关断，第三晶体管T3导通，并将第一开关K1、第二开关K2断开以将检测线230浮置；由于存储电容Cst的自举效应，存储电容Cst两端的电压保持不变，第一晶体管T1工作在饱和状态且电流不变并驱动发光元件发光，然后数模转换器对检测线230上的电压取样，并结合发光电流的大小和持续时间可以计算出第一晶体管T1中的载流子迁移率。例如，该过程可以在显示阶段之间的消隐阶段进行。
通过上述检测可以得到第一晶体管T1的电特性并实现相应的补偿算法。
例如，显示基板10还可以包括数据驱动电路和扫描驱动电路(未示出)。数据驱动电路配置为根据需要(例如输入显示装置的图像信号)可发出数据信号，例如上述数据信号DT；每个子像素的像素电路还配置为接收该数据信号并将该数据信号施加至该第一晶体管的栅极。扫描驱动电路配置为输出各种扫描信号，例如包括上述第一控制信号G1和第二控制信号G2，其例如为集成电路芯片(IC)或者为直接制备在显示基板上的栅驱动电路(GOA)。
例如，显示基板10还包括控制电路。例如，控制电路配置为控制数据驱动电路施加数据信号，以及控制栅极驱动电路施加扫描信号。该控制电路的一个示例为时序控制电路(T-con)。控制电路可以为各种形式，例如包括处理器和存储器，存储器包括可执行代码， 处理器运行该可执行代码以执行上述检测方法。
例如，处理器可以是中央处理单元(CPU)或者具有数据处理能力和/或指令执行能力的其它形式的处理装置，例如可以包括微处理器、可编程逻辑控制器(PLC)等。
例如，存储器可以包括一个或多个计算机程序产品，所述计算机程序产品可以包括各种形式的计算机可读存储介质，例如易失性存储器和/或非易失性存储器。易失性存储器例如可以包括随机存取存储器(RAM)和/或高速缓冲存储器(cache)等。非易失性存储器例如可以包括只读存储器(ROM)、硬盘、闪存等。在计算机可读存储介质上可以存储一个或多个计算机程序指令，处理器可以运行该程序指令期望的功能。在计算机可读存储介质中还可以存储各种应用程序和各种数据，例如在上述检测方法中获取的电特性参数等。
图3A为本公开至少一个实施例提供的显示基板10的子像素的示意图，如图3A所示，该显示基板10包括衬底基板101，多个子像素P1/P2/P3位于该衬底基板101上。多个子像素P1/P2/P3沿第一方向D1和第二方向D2分布为像素阵列，该像素阵列包括多个像素列和多个像素行，该像素阵列的列方向为第一方向D1，行方向为第二方向D2，第一方向D1与第二方向D2交叉，例如正交。
例如，每个像素行的子像素被划分为多个像素单元，每个像素单元配置为发出全彩光。图3A中示例性地示出了一个像素单元，本公开的实施不限于此布局；图3B示出了图3A沿剖面线I-I’的剖视图。如图3A所示，该像素单元包括沿第二方向D2依次布置的第一子像素P1、第二子像素P2和第三子像素P3，该第一子像素P1、第二子像素P2和第三子像素P3分别用于发出三种基本色(RGB)的光；例如，第一子像素P1为红色子像素，第二子像素P2为蓝色子像素，第三子像素P3为绿色子像素。
图4A为本公开至少一实施例提供的显示基板中的第一导电层的平面示意图；图4B为本公开至少一实施例提供的显示基板中的半导体层的平面示意图；图4C为本公开至少一实施例提供的显示基板中的第二导电层的平面示意图；图4D为本公开至少一实施例提供的显示基板中的第三导电层的平面示意图；图4E为本公开至少一实施例提供的显示基板中的第一电极的平面示意图；图4F为本公开至少一实施例提供的显示基板中的第一导电层与半导体层堆叠的平面示意图；图4G为本公开至少一实施例提供的显示基板中的第一导电层、半导体层与第二导电层堆叠的平面示意图；图4H为本公开至少一实施例提供的显示基板中的第一导电层、半导体层、第二导电层与第三导电层堆叠的平面示意图。结合参考图3A-3B以及图4A-4H，该显示基板10包括依次设置在衬底基板101上的第一导电层501、第二绝缘层202、半导体层104、栅绝缘层200、第二导电层502、第一绝缘层201、第三导电层503和第四导电层504。
以下将对图3A所示的显示基板10中子像素的具体结构进行说明。为了方便说明，在以下的描述中用T1g、T1s、T1d、T1a分别表示第一晶体管T1的栅极、第一极、第二极和有源层，用T2g、T2s、T2d、T2a分别表示第二晶体管T2的栅极、第一极、第二极和有源层，用T3g、T3s、T3d、T3a分别表示第三晶体管T3的栅极、第一极、第二极和有源层， 用Ca、Cb和Cc分别表示存储电容Cst的第一电容电极Ca、第二电容电极Cb和第三电容电极Cc。
需要说明的是，本公开中所称的“同层设置”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的结构，它们的材料可以相同或不同。本公开中的“一体的结构”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的彼此连接的结构，它们的材料可以相同或不同。
例如，结合参考图3A-3B和图4A，该第一导电层501包括遮光层170，该遮光层170在衬底基板101上的正投影覆盖第一晶体管T1的有源层T1a在衬底基板101上的正投影。第一晶体管T1作为像素电路的驱动晶体管，其电特性的稳定对于发光元件的发光特性非常重要。该遮光层170为不透光层，可以避免光线从衬底基板101的背面射入第一晶体管T1的有源层而引起第一晶体管T1的阈值电压的漂移，从而避免影响与之连接的对应的发光元件的发光特性。
例如，该遮光层170为不透光的导电材料，例如为金属或金属合金材料。这种设置可以缓解衬底基板101由于捕获电荷所导致的背沟道现象。
例如，结合参考图3A-3B和图4B，该半导体层104包括第一晶体管T1的有源层T1a、第二晶体管T2的有源层T2a和第三晶体管T3的有源层T3a。
例如，该半导体层104还包括该存储电容Cst的第一电容电极Ca，该第一电容电极Ca由该半导体层104经导体化处理得到；也即第一电容电极Ca与第一晶体管T1的有源层T1a、第二晶体管的有源层T2a及所述第三晶体管的有源层T3a同层设置。
例如，结合参考图3A-3B和图4C，该第二导电层502包括第一晶体管T1的栅极T1g、第二晶体管T2的栅极T2g和第三晶体管T3的栅极T3g。
例如，该显示基板10采用自对准工艺，利用第二导电层502作为掩膜对该半导体层104进行导体化处理(例如掺杂处理)，使得该半导体层104未被该第二导电层502覆盖的部分被导体化，从而得到该第一电容电极Ca，并使得各晶体管的有源层位于沟道区两侧的部分被导体化而形成分别第一极接触区及第二极接触区，该第一极接触区和第二极接触区分别用于与该晶体管的第一极和第二极电连接。
例如，结合参考图3A-3B和图4D，该第三导电层503包括第一晶体管T1的第一极T1s和第二极T1d、第二晶体管T2的第一极T2s和第二极T2d以及第三晶体管T3的第一极T3s和第二极T3d。
例如，该第三导电层503还包括存储电容Cst的第二电容电极Cb。例如，如图3B所示，该第二电容电极Cb与第一晶体管T1的第二极T1d同层设置且彼此连接为一体的结构。如图3B所示，该第一电容电极Ca和第二电容电极Cb在垂直于衬底基板101的方向上彼此重叠形成存储电容Cst。
例如，如图3B所示，每个子像素还包括发光元件125，例如，该发光元件为有机发光二极管，包括依次层叠设置的第一电极123、发光层124和第二电极122。例如，该 发光元件125为顶发射结构，第一电极具有反射性而第二电极122具有透射性或半透射性。例如，第一电极为高功函数的材料以充当阳极，例如为ITO/Ag/ITO叠层结构；第二电极122为低功函数的材料以充当阴极，例如为半透射的金属或金属合金材料，例如为Ag/Mg合金材料。结合参考图3A-3B和图4E，第四导电层504包括第一电极123。
例如，参考图3A-3B，每个子像素还包括发光元件125，例如，该发光元件为有机发光二极管，包括依次层叠设置的第一电极123、发光层124和第二电极122。例如，该发光元件125为顶发射结构，第一电极具有反射性而第二电极122具有透射性或半透射性。例如，第一电极为高功函数的材料以充当阳极，例如为ITO/Ag/ITO叠层结构；第二电极122为低功函数的材料以充当阴极，例如为半透射的金属或金属合金材料，例如为Ag/Mg合金材料。
例如，如图3B所示，该显示基板10还包括位于第三导电层503与发光元件的第一电极123之间的第三绝缘层203和第四绝缘层204。例如，该第三绝缘层203为钝化层，例如为无机绝缘层，例如氧化硅、氮化硅、氮氧化硅等硅的氧化物、硅的氮化物或硅的氮氧化物；该第四绝缘层204为有机绝缘材料，例如为聚酰亚胺(PI)、丙烯酸酯、环氧树脂、聚甲基丙烯酸甲酯(PMMA)等有机绝缘材料。例如，第四绝缘层204为平坦化层。
例如，显示基板10还包括位于发光元件125的第一电极123上的像素界定层206，该像素界定层206为有机绝缘材料，例如为聚酰亚胺(PI)、丙烯酸酯、环氧树脂、聚甲基丙烯酸甲酯(PMMA)等有机绝缘材料。该发光元件125的第一电极123通过8号过孔与第一晶体管T1的第一极T1s以及第二电容电极Cb电连接，该8号过孔例如贯穿第三绝缘层203和第四绝缘层204。
例如，每个子像素中的发光元件OLED均配置为发白光，该显示基板10还包括彩膜层，白光透过彩膜层射出实现全彩显示。例如，该发光层124可以通过Open Mask结合蒸镀工艺整面形成，这样例如避免使用精细金属掩模(Fine Metal Mask，FMM)对发光层进行构图工艺，从而避免了FMM精度有限而限制了显示基板的分辨率。
例如，本公开的一些实施例提供的显示基板10的发光元件可以采用底发射结构。例如，如图3A-3B所示，彩膜层位于发光元件的第一电极靠近衬底基板101的一侧，例如位于第三绝缘层203和第四绝缘层204之间。彩膜层包括分别对应于除白色子像素之外多个子像素的多个彩膜部190，也即该第一子像素P1、第二子像素P2和第三子像素P3分别对应一个彩膜部190，该第一子像素P1、第二子像素P2和第三子像素P3的发光元件发出的光经过该彩膜部190射出形成显示光。
例如图3A所示的子像素均是参与显示的子像素，而未示出虚拟像素，虚拟像素可根据实际需要在显示基板的适当位置设置。结合图3A和图3B，每个子像素包括第一过孔V0，数据写入晶体管T2的第一极T2s通过第一过孔V0与驱动晶体管T1的栅极T1g以及数据写入晶体管T2的有源层T2a电连接。需要说明的是，第一过孔V0整个是贯通的孔。从而，在本公开实施例提供的显示基板10中，数据写入晶体管T2的第一极T2s通过仅第 一过孔V0这一个过孔与驱动晶体管T1的栅极T1g以及数据写入晶体管的有源层电连接，与其他连接方式相比，明显减小了该连接位置的接触电阻，提高了信号传输效率，简化了显示基板制作工艺。
图4B中示出了第一晶体管T1的有源层T1a的第一极接触区T1a1和第二极接触区T1a2、第二晶体管T2的有源层T2a的第一极接触区T2a1和第二极接触区T2a2、以及第三晶体管T3的有源层T3a的第一极接触区T3a1和第二极接触区T3a2。图4B中还示出了连接部720。
例如，结合图3A和图3B，驱动晶体管T1的栅极T1g包括主体部181和与主体部181连接的延伸部180，主体部181在衬底基板101上的正投影与驱动晶体管的有源层T1a在衬底基板101上的正投影重叠，延伸部180自主体部181延伸，延伸部180通过第一过孔V0与数据写入晶体管T2的第一极T2s和以及数据写入晶体管的有源层T2a电连接。第一过孔V0包括彼此连通的第一区域V1和第二区域V2；例如，数据写入晶体管T2的第一极T2s通过第一过孔V0的第一区域V1和第二区域V2分别与数据写入晶体管T2的第一极T2s直接接触以电连接；延伸部180通过第一过孔V0的第一区域V1与第二晶体管T2的有源层T2a的第一极接触区T2a1连接，如图4B，该第一极接触区T2a1与第二晶体管T2的有源层T2a直接接触以电连接，从而使得延伸部180通过第一过孔V0与数据写入晶体管的有源层T2a电连接。
例如，如图3B所示，数据写入晶体管T2的第一极T2s包括在垂直于衬底基板101的方向上彼此堆叠的第一导电部111和第二导电部112，第二导电部112位于第一导电部111的远离衬底基板101的一侧；驱动晶体管T1的栅极T1g位于第一导电部111的靠近第二导电部112的一侧且与第一导电部111间隔开，第二导电部112通过第一过孔V0与驱动晶体管T1的栅极T1g以及第一导电部111接触，以减小接触电阻。显示基板10还包括连接部720，连接部720与延伸部180在垂直于衬底基板101的方向重叠，且将第一导电部111与数据写入晶体管T2的有源层T2a(例如第二晶体管T2的沟道区T2a0)连接为一体结构。例如，连接部720与第一导电部111接触，连接部720经由第一极接触区T2a1与第二晶体管T2的沟道区T2a0。
需要说明的是，这里的第一导电部111与数据写入晶体管T2的有源层T2a连接为一体结构是指这两者之间不存在缝隙且不存在其他层或结构，但两者的材料不同。例如，如之前所述，利用第二导电层502作为掩膜对半导体层104进行导体化处理的过程中，第一导电部111和第一极接触区T2a1属于半导体层104未被第二导电层502覆盖的部分而被导体化，连接部720和第二晶体管T2的沟道区T2a0属于被第二导电层502覆盖的部分而未被导体化，从而第一导电部111与数据写入晶体管T2的有源层T2a的材料不同。如此，能够节省通过构图工艺形成有源层的掩膜，简化制作工艺。从而，第二导电部112的材料和连接部180的材料包括相同的半导体材料，并且第一导电部111所包括的半导体材料被导体化。
例如，该半导体化工艺可以为采用等离子体对半导体层进行等离子体处理工艺，或者采用掺杂工艺等，具体地工艺类型可参考本领域常规技术，本公开对此不作限定。例如上述半导体材料为IGZO。例如采用含H+的气体对IGZO表面进行处理，使IGZO中的氧与H+结合，随着和导体化气体的不断反应而使未被第二导电层覆盖的IGZO导体化。
例如，如图3B所示，第一导电部111包括第一子部S1，第一子部S1位于延伸部180的第一侧；第二导电部112在延伸部180的第一侧通过第一过孔V0与第一子部S1直接进接触。第二导电部112从延伸部180的第一侧在第一过孔V0中延伸至延伸部180以与延伸部180的远离衬底基板101的上表面的至少部分接触。例如，第二导电部112与延伸部180的上表面的在第一方向D1上的整个宽度上的位置接触。如此，能够进一步减小第一导电部111、延伸部180和第二导电部112之间电连接的接触电阻，提高信号传输效率。
例如，第一导电部111还包括第二子部S2，第二子部S2位于延伸部180的第二侧，延伸部180的第二侧与延伸部180的第一侧相对；第二导电部112从延伸部180的第一侧在所述第一过孔V0中延伸跨过延伸部180以延伸至延伸部180的第二侧，第二导电部112在延伸部180的第二侧通过第一过孔V0与第二子部S2直接接触，以能够进一步减小第一导电部111、延伸部180和第二导电部112之间电连接的接触电阻，提高信号传输效率。
例如，栅绝缘层200位于驱动晶体管T1的栅极T1g与驱动晶体管T1的有源层T1a之间，驱动晶体管T1的栅极T1g位于栅绝缘层200的远离衬底基板101的一侧；第二绝缘层202位于驱动晶体管T1的栅极T1g的远离衬底基板101的一侧，第一过孔V0贯穿栅绝缘层200和第二绝缘层202。
参考图3B中的区域D的放大示意图。延伸部180包括与上表面相交的侧表面，第二导电部112还覆盖延伸部的侧表面且与延伸部180的侧表面接触；栅绝缘层200包括上表面和与所述栅绝缘层的上表面相交的侧表面，延伸部180的侧表面的与延伸部180的上表面所在的平面的夹角中靠近延伸部180的夹角为第一夹角θ1，栅绝缘层200的侧表面与延伸部180的上表面所在的平面的夹角中靠近延伸部180的夹角为第二夹角θ2；例如，第一夹角θ1小于第二夹角θ2，即延伸部180的侧表面的坡角小于栅绝缘层200的侧表面的坡角，有利于增大第二导电部112与延伸部180接触的可靠性，从而保证两者电连接的可靠性和电连接的稳定。又例如，图3C为图2A沿剖面线I-I’的另一种剖视图，在图3C所示的实施例中，第二导电部112包括与延伸部180直接接触的中间部分800，中间部分800的侧表面与延伸部180的上表面所在的平面的夹角中靠近延伸部180的夹角为第三夹角θ3，第一夹角θ1大于第三夹角θ3且第三夹角θ3大于第二夹角θ2，即第二夹角θ2最小，利于栅绝缘层200上方的层在其上方的附着，并且，第二导电部112在第一方向上的长度相对于其下方的延伸部180在第一方向上的长度大，从而其电阻较大，第三夹角θ3小于第一夹角θ1可以使得第二导电部112的在垂直于衬底基板方向上的厚度做得更大，利于减小第二导电部112的电阻，并且，图3B的角度关系更加有利于结构的稳定。
例如，示意性地，如图3B所示，第二电容电极Cb至少部分与驱动晶体管T1的第一 极T1s同层且为一体结构；第一电容电极Ca与第二电容电极Cb绝缘且与驱动晶体管T1的有源层T1g同层且为一体结构，第二电容电极Cb和第一电容电极Ca构成存储电容Cst的第一电容C1的两个极板。
例如，驱动晶体管的有源层的投影位于不透光的遮光层170的在衬底基板101上的正投影内，遮光层170与第一电容的第二电容电极Cb电连接，并且，遮光层170与第一电容的第一电容电极Ca绝缘且在垂直于衬底基板101的方向上至少部分重叠，以作为存储电容Cst的第三电容电极Cc，第三电容电极Cc与第一电容电极Ca构成存储电容Cst的第二电容C2的两个极板，第二电容与第一电容并联，以增大电容的电荷存储容量，更好地实现存储电容的补偿作用。第三电容电极Cc位于第一电容电极Ca远离第二电容电极Cb的一侧且与第二电容电极Cb通过图3A所示的7号过孔彼此电连接从而形成并联电容的结构，增大存储电容Cst的电容值。
例如，驱动晶体管T1的第一极T1s位于驱动晶体管T1的有源层T1a的远离衬底基板101的一侧，遮光层170位于驱动晶体管T1的有源层T1a的靠近衬底基板101的一侧。
例如，第二导电部112与驱动晶体管T1的第一极T1s同层且材料相同；两者均位于第三导电层503，可通过对同一膜层进行同一构图工艺形成，有利于简化显示基板的制作工艺。
例如，显示基板10还包括信号线。如图3A所示，例如，该显示基板10还包括沿第一方向D1延伸的多条信号线，例如，该信号线可以包括数据线DL、电源线(例如提供高电源电压VDD的第一电源线240或提供地电源电压VSS的第二电源线250)、检测线230或辅助电极线等。如图3A所示，每个第二部分152均与至少一条数据线在垂直于衬底基板101的方向上交叉，从而定义出沿第二方向D2布置的多个第一镂空区；每个第二部分162均与至少一条数据线在垂直于衬底基板101的方向上交叉，从而定义出沿第二方向D2布置的多个第二镂空区。
通过将扫描线与信号线交叉的部分设置为环状结构，也即双通道结构，可以有效提高器件的良率。例如，信号线交叉的位置容易因寄生电容发生静电击穿而导致短路不良，在检测过程中当检测到该环状结构的一个通道发生短路不良，可以将该通道切除(例如通过激光切割)，电路结构仍可以通过另一个通道进行正常工作。
例如，如图3A所示，该多条信号线包括多条数据线DL，该多条数据线DL与该子像素阵列中的每一列子像素一一对应连接以为子像素提供数据信号。对于一个像素行，该多条数据线被划分为与该像素行中的多个像素单元一一对应的多个数据线组，如图3A所示，每个数据线组包括与第一子像素P1连接的第一数据线DL1、与第二子像素P2连接的第二数据线DL2以及与第三子像素P3连接的第三数据线DL3。对于每个像素单元，与该像素单元对应连接的数据线DL1-DL3均位于第一子像素P1与第三子像素P3之间。这种设置可以为检测线和电源线的设置提供空间。
例如，如图3A所示，显示基板10还包括沿第一方向D1延伸的多条检测线230，该 检测线230用于与子像素100中检测子电路(如第三晶体管T3)连接，并将该检测子电路连接到外部检测电路。例如，每条检测线230与多条数据线DL中的任意一条之间间隔有至少一列子像素；也即，该检测线230不与任一数据线DL直接相邻。例如，如图3A所示，对于每个像素单元，第一数据线DL1与第二数据线DL2位于第一子像素P1与第二子像素P2之间，第三数据线DL3位于第二子像素P2与第三子像素P3之间，检测线230位于第三子像素P3的远离第二子像素P2第一子像素P1的一侧。
通过这种设置，避免数据线因与该检测线直接相邻而引起阻容负载造成数据线上的信号延迟，进一步避免了该延迟导致的显示不均等不良问题。此外，由于数据线DL上传输的信号通常为高频信号，将检测线230与数据线DL设置为不直接相邻可以避免检测线230在外部补偿充电采样过程中收到高频信号串扰从而影响采样精度。
例如，如图3A所示，该像素单元中的三个子像素共用一条检测线230，该检测线230通过沿第二方向D2延伸的检测部231分别与三个子像素中的第三晶体管T3的第二极T3d电连接。该检测线230通过过孔12与检测部231电连接，该检测部231通过10号过孔与第三晶体管T3的第二极T3d电连接。该第三晶体管T3的第一极T3s通过6号过孔与第三晶体管T3的第一极接触区T3a1电连接，第三晶体管T3的第二极T3d通过5号过孔与第三晶体管T3的第二极接触区T3a2电连接。
例如，该第三晶体管T3与第二电容电极Cb同层设置且连接为一体的结构。
例如，如图3A所示，该显示基板10还包括沿第一方向D1延伸的多条第一电源线240，该多条第一电源线240配置为为多个子像素提供第一电源电压，该电源电压例如为高电源电压VDD。该第一电源线240例如位于第三导电层503中。如图3A所示，该多条第一电源线240的每条与多条数据线中的任意一条之间间隔有至少一个像素列；也即，第一电源线240不与任一数据线DL直接相邻。通过这种设置，避免数据线因与电源线直接相邻而引起阻容负载造成数据线上的信号延迟，进一步避免了该延迟导致的色偏、显示不均等不良问题。
例如，任一第一电源线240与检测部231在垂直于衬底基板101的方向上不交叠，也即该第一电源线240对应于相邻的检测部231的间隔处设置。这种设置方式降低了信号线的交叠从而有效降低信号线之间的寄生电容以及由此引起的信号延迟。
例如，如图3B所示，该第一电源线240通过3号过孔与直接相邻的子像素(例如第一子像素P1)的第一晶体管T1的第二极T1d电连接，例如该电源线与该第一晶体管T1的第二极T1d为一体的结构。例如，该第一电源线240通过连接电极241与和该第一电源线240不直接相邻的子像素的第一晶体管T1的第二极T1d电连接。例如，该连接电极241通过11号过孔与第二子像素或第四子像素的第一晶体管T1的第二极T1d电连接。
图5为图3A沿剖面线A-A’的剖视图。如图5所示，在信号线为提供高电源电压VDD的第一电源线时，信号线即第一电源线240包括在垂直于衬底基板101且沿远离衬底基板101的方向依次堆叠的第一层2401、第二层2402和第三层2403，第一层2401与第二层2402 间隔开；该第一电源线240还包括信号线过孔V3，第三层2403通过信号线过孔V3与第二层2402和第一层2401电连接。如此，本公开实施例提供的显示基板中，信号线的第一层2401、第二层2402和第三层2403并联，减小了信号线的电阻；并且，第三层2403通过仅信号线过孔V3这一个过孔与第二层2402和第三层2403电连接，与其他连接方式相比，明显减小了该连接位置的接触电阻，提高了信号在信号线中的传输效率，同时，简化了显示基板制作工艺。
例如，第一层2401与驱动晶体管T1的有源层T1a同层，第二层2402与驱动晶体管T1的栅极T1g同层且材料相同，第三层2403与驱动晶体管T1的第一极T1s同层且材料相同。例如，第一层2401还包括半导体部A3，半导体部A3在垂直于衬底基板101的方向上与第二层2402重叠，与驱动晶体管T1的有源层T1a同层，且与第一导体部111构成一体结构。例如，在上述以第二导电层502为掩膜对半导体层进行导体化工艺中，同时形成第一层2401和被第二层2402遮挡的半导体部A3；同时，可利用同一构图工艺形成第二层2402与驱动晶体管T1的栅极T1g，利用同一构图工艺形成第三层2403与驱动晶体管T1的第一极T1s，以简化工艺。例如，第一层2401位于半导体层104，第二层2402位于第二导电层502，第三层2403位于第三导电层503。如此，在上述减小信号线的电阻的情况下，大大简化了显示基板的结构以及制作工艺。
例如，如图5所示，第一层2401包括第一导体部A1，第一导体部A1位于第二层2402的第一侧；第三层2403在第二层2402的第一侧通过信号线过孔V3与第一导体部A1直接接触；第三层2403从第一导体部A1的第一侧在信号线过孔V3中延伸至第一导体部A1的第二侧以与第二层2402的远离衬底基板101的上表面的至少部分接触。如此，能够进一步减小第一导体部A1、第二层2402和第三层2403之间电连接的接触电阻，提高信号传输效率。
例如，如图5所示，第三层2403与第二层2402的远离衬底基板101的上表面和第二层2402的与其上表面相交的侧表面直接接触，且第三层2403与第一层2401直接接触，以进一步减小第一层2401例如第一导体部A1、第二层2402和第三层2403之间电连接的接触电阻，提高信号传输效率。
例如，如图5所示，第一层2401还包括第二导体部A2，第二导体部A2位于第二层2402在信号线的线宽方向上的第二侧，第二层2402的第二侧与第二层2402的第一侧相对；第三层2403从第二层2402的第一侧在信号线过孔V3中沿信号线的线宽方向延伸跨过第二层2402以延伸至第二层2402的第二侧，第三层2403在第二层2402的第二侧通过信号线过孔V3与第二导体部A2直接接触，以增大第三层2403与第二层2402以及第一层2401的接触面积，减小第三层2403与第二层2402以及第三层2403与第一层2401之间的接触电阻。
例如，信号线过孔V3包括彼此连通的第一部分V31和第二部分V32。第三层2403在第二层2402的第一侧通过信号线过孔V3的第一部分V31与第一导体部A1直接接触； 第三层2403在第二层2402的第二侧通过信号线过孔V3的第二部分V32与第二导体部A2直接接触。
图3A和图3B以信号线为为给驱动晶体管T1的第一极T1s提供第一电源电压的第一电源线为例。在一些实施例中，信号线还可以包括数据线DT，数据线DT与数据写入晶体管T2的第二极T2d连接且配置为给数据写入晶体管T2提供数据信号。
例如，如图3A所示，一条信号线上可以设有一个或多个信号线过孔V3。例如图3A所示的示例中，一条第一电源线240例如第一电源线240上可以设有四个信号线过孔V3。
例如，在一些实施例中，上述信号线还包括检测线230，一条检测线230可以包括一个或多个信号线过孔V3。
例如，在一些实施例中，上述信号线还包括第二电源线250，第二电源线250为发光器件提供低电压VSS。一条第二电源线250可以包括一个或多个信号线过孔V3。
结合图3A-3B和图4D，第二电源线250位于第三导电层503，且通过13号孔连接到第二电极122例如阴极。
例如，如图3A所示，第二电源线250过14号孔连接至第二电极层，以形成双层走线，从而减小第二电源线250的电阻；例如一条第二电源线250包括多个14号孔。类似地，检测线230通过15号孔连接至第二电极层，以形成双层走线，从而减小检测线230的电阻；例如一条检测线230包括多个15号孔。
本公开至少一实施例还提供一种显示面板，包括以上任一显示基板10。需要说明的是，本公开至少一实施例提供的上述显示基板10可以包括发光元件125，也可以不包括发光元件125，也即该发光元件125可以在显示基板10完成后在面板厂形成。在该显示基板10本身不包括发光元件125的情形下，本公开实施例提供的显示面板除了包括显示基板10之外，还进一步包括发光元件125。
例如，该显示面板为OLED显示面板，相应地其包括的显示基板10为OLED显示基板。
本公开的至少一实施例还提供一种显示装置30，如图6所示，该显示装置30包括上述任一显示基板10或显示面板20，本实施例中的显示装置可以为：显示器、OLED面板、OLED电视、电子纸、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开的至少一实施例还提供上述显示基板的制作方法。制作方法，包括：提供衬底基板；在衬底基板上形成多个像素，其中，所述多个像素中的至少部分像素包括多个子像素，所述多个子像素的每个包括发光元件和驱动所述发光元件发光的像素电路，所述像素电路包括发光器件、存储电容、驱动晶体管和数据写入晶体管，所述驱动晶体管和所述数据写入晶体管的每个包括有源层、栅极、第一极和第二极；所述驱动晶体管的第一极配置为接收第一电源电压，所述驱动晶体管的第二极与发光器件连接以配置为控制所述发光器件发光；以及在所述多个子像素中的至少部分子像素中形成第一过孔，其中，所述数据写 入晶体管的第一极通过所述第一过孔与所述驱动晶体管的栅极以及所述数据写入晶体管的有源层电连接。
例如，显示基板的制作方法包括：形成半导体层；在所述半导体层的远离所述衬底基板的一侧形成覆盖所述半导体层的栅绝缘层；在所述栅绝缘层的远离所述衬底基板的一侧形成栅导电层；通过构图工艺对所述栅导电层进行构图以形成所述驱动晶体管的栅极；以所述驱动晶体管的栅极作为刻蚀阻挡层对所述栅绝缘层执行构图工艺，以暴露部分所述半导体层，其中，所述半导体层包括被所述栅绝缘层遮挡的部分和未被所述栅绝缘层遮挡的部分；以及对所述半导体层的未被栅绝缘层遮挡的部分进行导体化处理以形成第一导电部，被所述栅绝缘层遮挡的部分未被导体化以构成所述驱动晶体管的有源层和连接部，其中，述驱动晶体管的栅极包括主体部和与所述主体部连接的延伸部，所述主体部的投影与所述驱动晶体管的有源层的投影重叠，所述延伸部自所述主体部延伸，所述延伸部通过所述第一过孔与所述驱动晶体管的栅极和以及所述数据写入晶体管的有源层电连接；所述连接部与所述延伸部在垂直于所述衬底基板的方向重叠，且将所述第一导电部与所述数据写入晶体管的有源层连接为一体结构。
例如，上述形成第一过孔包括：在形成所述驱动晶体管的有源层和所述数据写入晶体管的有源层之后，在所述驱动晶体管的栅极的远离所述衬底基板的一侧形成第一绝缘层，其中，所述第一绝缘层覆盖所述驱动晶体管的栅极、所述数据写入晶体管的栅极和所述栅绝缘层；以及对所述第一绝缘层执行构图工艺以形成所述第一过孔，其中，所述第一过孔暴露所述驱动晶体管的栅极至少部分以及所述第一导电部的至少部分；制作方法还包括：在所述驱动晶体管的栅极的远离所述衬底基板的一侧形成第二导电部，其中，所述第二导电部通过所述第一过孔与所述驱动晶体管的栅极以及所述第一导电部电连接，所述第一导电部与所述第二导电部构成所述数据写入晶体管的第一极。从而，使得数据写入晶体管的第一极通过第一过孔与所述驱动晶体管的栅极以及数据写入晶体管的有源层电连接。
例如，显示基板的制作方法还包括：形成信号线，包括形成在垂直于所述衬底基板且沿远离所述衬底基板的方向上依次堆叠的第一层、第二层和第三层，其中，所述第一层与所述第三层间隔开，所述信号线还包括信号线过孔，所述第三层通过所述信号线过孔与所述第二层和所述第一层电连接。
例如，所述第一层与所述驱动晶体管的有源层通过所述半导体层的未被所述栅绝缘层遮挡的部分进行同一所述导体化处理工艺同时形成；所述第二层与所述驱动晶体管的栅极通过对所述栅导电层进行同一构图工艺同时形成；所述第三层与所述驱动晶体管的第一极通过对同一膜层执行同一构图工艺同时形成。
以下将结合图3A-3B和图4A-图4D、并以两个像素，每个像素包括三个子像素的情形为例对本公开实施例提供的显示基板的制作方法进行实例性说明，然而本公开实施例并不限于此。图3A-3B和图4A-图4D示出了显示基板的两个像素，每个像素包括三个子像素的情形，例如图4A-图4D分别示出了共六个子像素中第一导电层、半导体层、第二导电 层、第三导电层的图案。
例如，该制作方法包括如下步骤S1-S5。
步骤S1：形成第一导电材料层，并对该第一导电材料层进行构图工艺从而形成如图4A所示的第一导电层501，也即遮光层170以及存储电容Cst的第三电容电极Cc。该构图工艺还形成彼此绝缘的检测部231和连接电极241。
步骤S2：在该第一导电层501上形成第二绝缘层202并在该第一绝缘层上形成半导体材料层，并对该半导体材料层进行构图工艺从而形成如图4B所示的半导体层104，也即形成彼此间隔的第一晶体管T1的有源层T1a、第二晶体管T2的有源层T2a和第三晶体管T3的有源层T3a。例如，在对该半导体材料层进行构图工艺时，通过同一构图工艺形成图5所示的信号线的第一层2401，以简化显示基板的制作工艺。
步骤S3：在该半导体层104上形成栅绝缘层200并在该第二绝缘层上形成第二导电材料层，对该第二导电材料层进行构图工艺形成如图4C所示的第二导电层502，也即形成彼此绝缘的第一晶体管T1的栅极T1g、第二晶体管T2的栅极T2g和第三晶体管T3的栅极T3g。图4C还示出了延伸部180。例如，在对第二导电材料层进行构图工艺时，利用同一构图工艺在第二导电层502中形成图5所示的信号线的第二层2402，即第二层与驱动晶体管的栅极通过对栅导电层进行同一构图工艺同时形成，以简化显示基板的制作工艺。
例如，如图4C所示，该第二导电层502还包括彼此绝缘的第一扫描线150和第二扫描线160。
例如，该第一扫描线150和第二扫描线160的线宽范围为5-15微米。
例如，该第一扫描线150与对应的一行子像素的第二晶体管T2的栅极T2g为一体的结构，该第二扫描线160分别与对应的一行子像素的第三晶体管T3的栅极T3g为一体的结构。
步骤S4：采用自对准工艺，利用该第二导电层502作为掩膜对该半导体层204进行导体化处理(例如等离子处理、掺杂处理等)，从而使得该半导体层204未被该第二导电层502覆盖的部分被导体化，从而得到该第一电容电极Ca，并使得各晶体管的有源层位于沟道区两侧的部分被导体化而形成分别第一极接触区及第二极接触区，该第一极接触区和第二极接触区分别用于与该晶体管的第一极和第二极电连接。图4B中示出了第一晶体管T1的有源层T1a的第一极接触区T1a1和第二极接触区T1a2、第二晶体管T2的有源层T2a的第一极接触区T2a1和第二极接触区T2a2、以及第三晶体管T3的有源层T3a的第一极接触区T3a1和第二极接触区T3a2。图4B中还示出了连接部720。在利用该第二导电层502作为掩膜对该半导体层204进行导体化处理时，同时形成图5所示的第一导体部A1、第二导体部A2和半导体部A3，即第一层与驱动晶体管的有源层通过半导体层的未被栅绝缘层遮挡的部分进行同一导体化处理工艺同时形成，以简化显示基板的制作工艺。
例如，在对该半导体层104进行导体化处理之前对栅绝缘层200进行刻蚀工艺，使得该栅绝缘层200未被该第二导电层502覆盖的区域全部被刻蚀，也即第二绝缘层103与第 二导电层502在垂直于衬底基板101的方向上重合。这样，在采用离子注入对半导体层204未被第二导电层202覆盖的区域进行导体化处理时，注入的离子可以不被栅绝缘层200阻挡。
步骤S5：在该第二导电层502上形成第一绝缘层201，并在该第一绝缘层201上形成第三导电材料层，对该第三导电材料层进行构图工艺形成如图4D所示的第三导电层503，也即形成第一晶体管T1的第一极T1s和第二极T1d、第二晶体管T2的第一极T2s和第二极T2d以及第三晶体管T3的第一极T3s和第二极T3d。在对第三导电材料层进行构图工艺时，利用同一构图工艺同时形成图5所示的第三层2403，即第三层与驱动晶体管的第一极通过对同一膜层执行同一构图工艺同时形成，以简化显示基板的制作工艺。
例如，该第三导电层503还包括彼此绝缘的数据线DL、检测线230和第一电源线240。
例如，数据线DL的线宽范围为5-15微米，检测线230的线宽范围为5-30微米，第一电源线240的线宽范围为5-30微米。
例如，如图4D所示，该第一电源线240和与之直接相邻的(最近的)子像素中的第一晶体管T1的第二极T1d为一体的结构。例如，每条数据线110和与之连接的子像素中的第二晶体管T2的第二极T2d为一体的结构。
例如，该半导体材料层的材料包括但不限于硅基材料(非晶硅a-Si，多晶硅p-Si等)、金属氧化物半导体(IGZO，ZnO，AZO，IZTO等)以及有机物材料(六噻吩，聚噻吩等)。
例如，上述第一导电材料层为遮光导电材料，例如包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)以及以上金属组合而成的合金材料。例如，该第一导电材料层可以是钼钛合金，例如厚度为50-100纳米。
例如，第二导电材料层和第三导电材料层的材料可以包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)以及以上金属组合而成的合金材料；或者导电金属氧化物材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化锌铝(AZO)等。
例如，第二导电材料层为钼钛合金与铜的叠层结构，例如钼钛合金的厚度为30-50纳米，铜的厚度为300-400纳米。
例如，第三导电材料层为钼钛合金与铜的叠层结构，例如钼钛合金的厚度为30-50纳米，铜的厚度为400-700纳米。
例如，该半导体材料层的材料包括但不限于硅基材料(非晶硅a-Si，多晶硅p-Si等)、金属氧化物半导体(IGZO，ZnO，AZO，IZTO等)以及有机物材料(六噻吩，聚噻吩等)。
例如，该半导体材料层的材料为氧化铟镓锌，厚度为30-50纳米。
例如，第二绝缘层202、栅绝缘层200、第一绝缘层201例如为无机绝缘层，例如氧化硅、氮化硅、氮氧化硅等硅的氧化物、硅的氮化物或硅的氮氧化物，或者氧化铝、氮化钛等包括金属氮氧化物绝缘材料。例如，这些绝缘层也可以是有机材料，例如聚酰亚胺(PI)、丙烯酸酯、环氧树脂、聚甲基丙烯酸甲酯(PMMA)等，本公开实施例对此不作限制。
例如，第二绝缘层202的材料为氧化硅，厚度为300-500纳米。例如，栅绝缘层200的材料为氧化硅，厚度为100-160纳米。例如，第三绝缘层的材料为氧化硅，厚度为400-600纳米。
例如，参考图3B，还可以在该第三导电层503上依次形成第三绝缘层203、彩膜层以及第四绝缘层204，并在该第四绝缘层204上形成发光元件的第一电极123，然后在该第一电极123上形成像素界定层206，并依次形成发光层124和第二电极122，这样就形成了如图3A所示的显示基板10。
例如，形成该彩膜层可以包括先形成红色彩膜层并对该红色彩膜层进行构图工艺形成对应红色子像素的彩膜部，再形成绿色彩膜层并对该绿色彩膜层进行构图工艺形成对应绿色子像素的彩膜部，然后形成蓝色彩膜层并对该蓝色彩膜层进行构图工艺形成对应蓝色子像素的彩膜部。
例如，该红色彩膜层、绿色彩膜层和蓝色彩膜层的厚度分别为2000-3000纳米，也即每个彩膜部的厚度为2000-3000纳米。
例如，相邻的子像素之间可以通过彩膜部的重叠形成遮光部避免串色。
例如，上述构图工艺可以采用常规的光刻工艺，例如包括光刻胶的涂布、曝光、显影、烘干、刻蚀等步骤。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。

Claims (25)

  1. 一种显示基板，包括：
    衬底基板，设置有呈阵列排布的多个像素，其中，所述多个像素中的至少部分像素包括多个子像素，所述多个子像素中的至少部分子像素包括发光元件和驱动所述发光元件发光的像素电路，所述像素电路包括存储电容、驱动晶体管和数据写入晶体管，所述驱动晶体管包括有源层、栅极、第一极和第二极，所述数据写入晶体管包括有源层、栅极、第一极和第二极；所述驱动晶体管的第一极配置为接收第一电源电压，所述驱动晶体管的第二极与发光器件连接以配置为控制所述发光器件发光，其中，
    所述多个子像素中的至少部分子像素包括第一过孔，所述数据写入晶体管的第一极通过所述第一过孔与所述驱动晶体管的栅极以及所述数据写入晶体管的有源层电连接。
  2. 根据权利要求1所述的显示基板，其中，所述驱动晶体管的栅极包括主体部和与所述主体部连接的延伸部，所述主体部在所述衬底基板上的正投影与所述驱动晶体管的有源层在所述衬底基板上的正投影重叠，所述延伸部自所述主体部延伸，所述延伸部通过所述第一过孔与所述数据写入晶体管的第一极和以及所述数据写入晶体管的有源层电连接。
  3. 根据权利要求2所述的显示基板，其中，所述数据写入晶体管的第一极包括在垂直于所述衬底基板的方向上彼此堆叠的第一导电部和第二导电部，所述第二导电部位于所述第一导电部的远离所述衬底基板的一侧；
    所述驱动晶体管的栅极位于所述第一导电部的靠近所述第二导电部的一侧且与所述第一导电部间隔开，所述第二导电部通过所述第一过孔与所述驱动晶体管的栅极以及所述第一导电部接触；
    所述显示基板还包括：
    连接部，与所述延伸部在垂直于所述衬底基板的方向重叠，且将所述第一导电部与所述数据写入晶体管的有源层连接为一体结构。
  4. 根据权利要求3所述的显示基板，其中，所述第二导电部的材料和所述连接部的材料包括相同的半导体材料，并且所述第一导电部所包括的半导体材料被导体化。
  5. 根据权利要求2-4任一所述的显示基板，其中，所述第一导电部包括：
    第一子部，位于所述延伸部的第一侧，其中，所述第二导电部在所述第一侧通过所述第一过孔与所述第一子部直接进接触；
    所述第二导电部从所述延伸部的第一侧在所述第一过孔中延伸至所述延伸部以与所述延伸部的远离所述衬底基板的上表面的至少部分接触。
  6. 根据权利要求5所述的显示基板，其中，所述第一导电部还包括：
    第二子部，位于所述延伸部的第二侧，其中，所述第二侧与第一侧相对，所述第二导电部从所述延伸部的第一侧在所述第一过孔中延伸跨过所述延伸部以延伸至所述延伸部的第二侧，所述第二导电部在所述第二侧通过所述第一过孔与所述第二子部直接接触。
  7. 根据权利要求2-6任一所述的显示基板，其中，还包括：
    栅绝缘层，位于所述驱动晶体管的栅极与所述驱动晶体管的有源层之间，所述驱动晶体管的栅极位于所述栅绝缘层的远离所述衬底基板的一侧；
    第一绝缘层，位于所述驱动晶体管的栅极的远离所述衬底基板的一侧，其中，所述第一过孔贯穿所述栅绝缘层和所述第一绝缘层；
    所述延伸部包括与所述上表面相交的侧表面，所述第二导电部还覆盖所述延伸部的侧表面且与所述延伸部的侧表面接触；
    栅绝缘层包括上表面和与所述栅绝缘层的上表面相交的侧表面，所述延伸部的侧表面与所述延伸部的上表面所在的平面的夹角中靠近所述延伸部的夹角为第一夹角，所述栅绝缘层的侧表面与所述延伸部的上表面所在的平面的夹角中靠近所述延伸部的夹角为第二夹角，所述第二导电部包括与所述延伸部直接接触的中间部分，所述中间部分的侧表面与所述延伸部的上表面所在的平面的夹角中靠近所述延伸部的夹角为第三夹角；
    所述第一夹角小于所述第二夹角，或者，所述第一夹角大于所述第三夹角且所述第三夹角大于所述第二夹角。
  8. 根据权利要求2-7任一所述的显示基板，其中，所述存储电容包括：
    第二电容电极，至少部分与所述驱动晶体管的第一极同层且为一体结构；以及
    第一电容电极，与所述第二电容电极绝缘且与所述驱动晶体管的有源层同层且为一体结构，其中，所述第二电容电极和所述第一电容电极构成所述存储电容的第一电容的两个极板。
  9. 根据权利要求8所述的显示基板，还包括：
    不透光的遮光层，其中，所述驱动晶体管的有源层位于所述遮光层在所述衬底基板上的正投影内，所述遮光层与所述第一电容的第二电容电极电连接，并且，所述遮光层与所述第一电容的第一电容电极绝缘且在垂直于所述衬底基板的方向上至少部分重叠以作为所述存储电容的第三电容电极，所述第三电容电极与所述第一电容电极构成所述存储电容的第二电容的两个极板，所述第二电容与所述第一电容并联。
  10. 根据权利要求9所述的显示基板，其中，所述驱动晶体管的第一极位于所述驱动晶体管的有源层的远离所述衬底基板的一侧，所述遮光层位于所述驱动晶体管的有源层的靠近所述衬底基板的一侧。
  11. 根据权利要求10所述的显示基板，其中，所述第二导电部与所述驱动晶体管的第一极同层且材料相同。
  12. 根据权利要求1-11任一所述的显示基板，还包括：
    信号线，包括在垂直于所述衬底基板且沿远离所述衬底基板的方向依次堆叠的第一层、第二层和第三层，其中，所述第一层与所述第二层间隔开，所述信号线还包括信号线过孔，所述第三层通过所述信号线过孔与所述第二层和所述第一层电连接。
  13. 根据权利要求12所述的显示基板，其中，所述第一层与所述驱动晶体管的有源 层同层，所述第二层与所述驱动晶体管的栅极同层且材料相同，所述第三层与所述驱动晶体管的第一极同层且材料相同。
  14. 根据权利要求12或13所述的显示基板，其中，所述第一层包括：
    第一导体部，位于所述第二层的第一侧，其中，所述第三层在所述第二层的第一侧通过所述信号线过孔与所述第一导体部直接接触；所述第三层从所述第一导体部的第一侧在所述信号线过孔中延伸至所述第一导体部的第二侧以与所述第二层的远离所述衬底基板的上表面的至少部分接触。
  15. 根据权利要求14所述的显示基板，其中，所述第三层与所述第二层的远离所述衬底基板的上表面和所述第二层的与其上表面相交的侧表面直接接触，且所述第三层与所述第一层直接接触。
  16. 根据权利要求14或15所述的显示基板，其中，所述第一层还包括：
    第二导体部，位于所述第二层在所述信号线的线宽方向上的第二侧，其中，所述第二层的第二侧与所述第二层的第一侧相对，所述第三层从所述第二层的第一侧在所述信号线过孔中沿所述信号线的线宽方向延伸跨过所述第二层以延伸至所述第二层的第二侧，所述第三层在所述第二层的第二侧通过所述信号线过孔与所述第二导体部直接接触。
  17. 根据权利要求16所述的显示基板，其中，所述第一层还包括：
    半导体部，在垂直于所述衬底基板的方向上与所述第二层重叠，与所述驱动晶体管的有源层同层，且与所述第一导体部构成一体结构。
  18. 根据权利要求12-17任一所述的显示基板，其中，还包括：
    数据线，与所述数据写入晶体管的第二极连接且配置为给所述数据写入晶体管提供数据信号，其中，所述信号线包括所述数据线。
  19. 根据权利要求12-18任一所述的显示基板，其中，还包括：
    第一电源线，配置为给所述驱动晶体管的第一极提供第一电源电压，其中，所述信号线包括所述第一电源线。
  20. 一种显示装置，包括根据权利要求1-19任一所述的显示基板。
  21. 一种显示基板的制作方法，包括：
    提供衬底基板；
    在衬底基板上形成多个像素，其中，所述多个像素中的至少部分像素包括多个子像素，所述多个子像素的每个包括发光元件和驱动所述发光元件发光的像素电路，所述像素电路包括发光器件、存储电容、驱动晶体管和数据写入晶体管，所述驱动晶体管和所述数据写入晶体管的每个包括有源层、栅极、第一极和第二极；所述驱动晶体管的第一极配置为接收第一电源电压，所述驱动晶体管的第二极与发光器件连接以配置为控制所述发光器件发光；以及
    在所述多个子像素中的至少部分子像素中形成第一过孔，其中，所述数据写入晶体管的第一极通过所述第一过孔与所述驱动晶体管的栅极以及所述数据写入晶体管的有源层 电连接。
  22. 根据权利要求21所述的显示基板的制作方法，包括：
    形成半导体层；
    在所述半导体层的远离所述衬底基板的一侧形成覆盖所述半导体层的栅绝缘层；
    在所述栅绝缘层的远离所述衬底基板的一侧形成栅导电层；
    通过构图工艺对所述栅导电层进行构图以形成所述驱动晶体管的栅极；
    以所述驱动晶体管的栅极作为刻蚀阻挡层对所述栅绝缘层执行构图工艺，以暴露部分所述半导体层，其中，所述半导体层包括被所述栅绝缘层遮挡的部分和未被所述栅绝缘层遮挡的部分；以及
    对所述半导体层的未被栅绝缘层遮挡的部分进行导体化处理以形成第一导电部，被所述栅绝缘层遮挡的部分未被导体化以构成所述驱动晶体管的有源层和连接部，其中，述驱动晶体管的栅极包括主体部和与所述主体部连接的延伸部，所述主体部的投影与所述驱动晶体管的有源层的投影重叠，所述延伸部自所述主体部延伸，所述延伸部通过所述第一过孔与所述驱动晶体管的栅极和以及所述数据写入晶体管的有源层电连接；所述连接部与所述延伸部在垂直于所述衬底基板的方向重叠，且将所述第一导电部与所述数据写入晶体管的有源层连接为一体结构。
  23. 根据权利要求22所述的显示基板的制作方法，其中，形成所述第一过孔包括：
    在形成所述驱动晶体管的有源层和所述数据写入晶体管的有源层之后，在所述驱动晶体管的栅极的远离所述衬底基板的一侧形成第一绝缘层，其中，所述第一绝缘层覆盖所述驱动晶体管的栅极、所述数据写入晶体管的栅极和所述栅绝缘层；以及
    对所述第一绝缘层执行构图工艺以形成所述第一过孔，其中，所述第一过孔暴露所述驱动晶体管的栅极至少部分以及所述第一导电部的至少部分；
    制作方法还包括：
    在所述驱动晶体管的栅极的远离所述衬底基板的一侧形成第二导电部，其中，所述第二导电部通过所述第一过孔与所述驱动晶体管的栅极以及所述第一导电部电连接，所述第一导电部与所述第二导电部构成所述数据写入晶体管的第一极。
  24. 根据权利要求22或23所述的显示基板的制作方法，还包括：
    形成信号线，包括形成在垂直于所述衬底基板且沿远离所述衬底基板的方向上依次堆叠的第一层、第二层和第三层，其中，所述第一层与所述第三层间隔开，所述信号线还包括信号线过孔，所述第三层通过所述信号线过孔与所述第二层和所述第一层电连接。
  25. 根据权利要求24所述的显示基板的制作方法，其中，所述第一层与所述驱动晶体管的有源层通过所述半导体层的未被所述栅绝缘层遮挡的部分进行同一所述导体化处理工艺同时形成；
    所述第二层与所述驱动晶体管的栅极通过对所述栅导电层进行同一构图工艺同时形成；
    所述第三层与所述驱动晶体管的第一极通过对同一膜层执行同一构图工艺同时形成。
PCT/CN2021/083857 2021-03-30 2021-03-30 显示基板及其制作方法以及显示装置 WO2022204922A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE112021001975.9T DE112021001975T5 (de) 2021-03-30 2021-03-30 Anzeigesubstrat und verfahren zu dessen herstellung, anzeigevorrichtung
PCT/CN2021/083857 WO2022204922A1 (zh) 2021-03-30 2021-03-30 显示基板及其制作方法以及显示装置
CN202180000658.0A CN115485852A (zh) 2021-03-30 2021-03-30 显示基板及其制作方法以及显示装置
US17/764,706 US20230337466A1 (en) 2021-03-30 2021-03-30 Display substrate and manufacture method thereof, display apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/083857 WO2022204922A1 (zh) 2021-03-30 2021-03-30 显示基板及其制作方法以及显示装置

Publications (1)

Publication Number Publication Date
WO2022204922A1 true WO2022204922A1 (zh) 2022-10-06

Family

ID=83457301

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/083857 WO2022204922A1 (zh) 2021-03-30 2021-03-30 显示基板及其制作方法以及显示装置

Country Status (4)

Country Link
US (1) US20230337466A1 (zh)
CN (1) CN115485852A (zh)
DE (1) DE112021001975T5 (zh)
WO (1) WO2022204922A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106920814A (zh) * 2015-12-28 2017-07-04 昆山工研院新型平板显示技术中心有限公司 Oled像素版图以及oled器件的制造方法
CN110265412A (zh) * 2019-06-27 2019-09-20 京东方科技集团股份有限公司 阵列基板、显示面板和阵列基板的制造方法
CN210984240U (zh) * 2019-12-12 2020-07-10 京东方科技集团股份有限公司 驱动背板及显示面板
US20200402466A1 (en) * 2019-06-24 2020-12-24 Samsung Display Co., Ltd. Display panel and display device including the same
CN212257399U (zh) * 2020-09-25 2020-12-29 京东方科技集团股份有限公司 背板

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109087922B (zh) * 2018-09-19 2020-09-29 合肥鑫晟光电科技有限公司 阵列基板及其制作方法、显示面板
US11437440B2 (en) * 2019-07-05 2022-09-06 Hefei Boe Joint Technology Co., Ltd. Array substrate having detection and compensation lead lines, display apparatus, method of fabricating array substrate, and pixel driving circuit having connection bridge
US11217656B2 (en) * 2019-11-29 2022-01-04 Hefei Xinsheng Optoelectronics Technology Co., Ltd. Display substrate and manufacturing method thereof, display device
CN115776830A (zh) * 2019-11-29 2023-03-10 京东方科技集团股份有限公司 显示基板及显示装置
WO2021102997A1 (zh) * 2019-11-29 2021-06-03 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
EP4068255A4 (en) * 2019-11-29 2022-11-23 BOE Technology Group Co., Ltd. DISPLAY SUBSTRATE AND DISPLAY APPARATUS
CN112331714B (zh) * 2021-01-04 2021-04-23 京东方科技集团股份有限公司 显示基板及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106920814A (zh) * 2015-12-28 2017-07-04 昆山工研院新型平板显示技术中心有限公司 Oled像素版图以及oled器件的制造方法
US20200402466A1 (en) * 2019-06-24 2020-12-24 Samsung Display Co., Ltd. Display panel and display device including the same
CN110265412A (zh) * 2019-06-27 2019-09-20 京东方科技集团股份有限公司 阵列基板、显示面板和阵列基板的制造方法
CN210984240U (zh) * 2019-12-12 2020-07-10 京东方科技集团股份有限公司 驱动背板及显示面板
CN212257399U (zh) * 2020-09-25 2020-12-29 京东方科技集团股份有限公司 背板

Also Published As

Publication number Publication date
US20230337466A1 (en) 2023-10-19
CN115485852A (zh) 2022-12-16
DE112021001975T5 (de) 2023-01-12

Similar Documents

Publication Publication Date Title
CN112331714B (zh) 显示基板及显示装置
CN113272964B (zh) 显示基板及显示装置
WO2021237725A9 (zh) 显示基板和显示装置
WO2021103015A1 (zh) 显示基板及其制作方法、显示装置
CN113366563B (zh) 显示基板及其制作方法、显示装置
CN111834292B (zh) 一种显示基板及其制作方法、显示面板及显示装置
CN113196370B (zh) 显示基板及显示装置
US20240057420A1 (en) Display substrate and display device
WO2022204922A1 (zh) 显示基板及其制作方法以及显示装置
WO2023122888A1 (zh) 显示基板及其制备方法、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21933607

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 21933607

Country of ref document: EP

Kind code of ref document: A1