WO2022056829A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

Info

Publication number
WO2022056829A1
WO2022056829A1 PCT/CN2020/116162 CN2020116162W WO2022056829A1 WO 2022056829 A1 WO2022056829 A1 WO 2022056829A1 CN 2020116162 W CN2020116162 W CN 2020116162W WO 2022056829 A1 WO2022056829 A1 WO 2022056829A1
Authority
WO
WIPO (PCT)
Prior art keywords
line
power supply
supply line
control
electrically connected
Prior art date
Application number
PCT/CN2020/116162
Other languages
English (en)
French (fr)
Inventor
杜丽丽
周宏军
魏博
马倩
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to GB2217902.2A priority Critical patent/GB2610958A/en
Priority to PCT/CN2020/116162 priority patent/WO2022056829A1/zh
Priority to CN202080002029.7A priority patent/CN114556205B/zh
Priority to US17/418,258 priority patent/US11721291B2/en
Publication of WO2022056829A1 publication Critical patent/WO2022056829A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0232—Special driving of display border areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the display field, and in particular, relate to a display substrate and a display device.
  • Organic Light Emitting Diode is one of the hotspots in the field of display research today. Compared with Liquid Crystal Display (LCD), organic light-emitting diode OLED has the advantages of low energy consumption, low production cost, self-illumination, wide viewing angle and fast response speed, and has been widely used in mobile phones, tablet computers and digital cameras. displayed in the field.
  • LCD Liquid Crystal Display
  • the present disclosure further provides a display substrate, comprising: a display area and a non-display area surrounding the display area, the display area including at least a segment of an arc-shaped display boundary;
  • the display area includes: a plurality of sub-pixels, a plurality of data lines extending along the first direction and a plurality of grid lines extending along the second direction; each sub-pixel includes: a pixel circuit and a light-emitting element connected to the pixel circuit, The pixel circuit in each sub-pixel is electrically connected to the gate line and the data line respectively; at least part of the sub-pixels close to the arc-shaped display boundary are arranged in a stepped shape;
  • the non-display area includes: a plurality of cascaded driving circuits that provide driving signals to a plurality of gate lines; at least part of the driving circuits close to the arc-shaped display boundary are arranged in a stepped shape;
  • the first direction intersects with the second direction.
  • the display area further includes: a plurality of first power lines extending along the first direction and a plurality of initial signal lines extending along the second direction, and the pixel circuits in each sub-pixel are respectively connected with the first power lines.
  • a power line is electrically connected to the initial signal line;
  • the non-display area further includes: a first power supply line and an initial signal power supply line; the first power supply line and the initial signal power supply line are annular;
  • the first power supply line is located on one side of the plurality of driving circuits close to the display area, and is electrically connected to the first power supply line connected to each pixel circuit; the first power supply line near the arc display boundary is stepped ;
  • the initial signal power supply line is located between the plurality of driving circuits and the first power supply line, and is electrically connected to the initial signal line connected to each pixel circuit; the initial signal power supply line close to the arc display boundary is stepped shape.
  • the line width of the first power supply line is larger than the line width of the initial signal power supply line.
  • the display area further includes: a second power supply line, and the light-emitting element in each sub-pixel is electrically connected to the second power supply line;
  • the non-display area further includes: a second power supply line; the second power supply line is annular;
  • the second power supply line is located on one side of the plurality of driving circuits away from the display area, and is electrically connected to the second power supply line connected to each light-emitting element; the second power supply line close to the arc-shaped display boundary is close to the display area
  • the surface of the display area is stepped, and the surface of the second power supply line that is close to the arc-shaped display boundary and away from the display area is arc-shaped.
  • the line width of the second power supply line is larger than the line width of the first power supply line.
  • the display area further includes: a plurality of light-emitting control lines and reset control lines extending along the second direction; the pixel circuit in each sub-pixel is associated with the light-emitting control lines and the reset control lines electrical connection;
  • the non-display area includes: a plurality of cascaded control circuits that provide control signals to a plurality of light-emitting control lines; at least part of the control circuits close to the arc-shaped display boundary are arranged in a stepped shape;
  • the plurality of driving circuits and the plurality of control circuits are located on oppositely disposed first and second sides of the display area, respectively.
  • the non-display area further includes: a plurality of multiplexing circuits, the multiplexing circuits are located between the plurality of driving circuits and the initial signal power supply lines, and are connected to a plurality of the data lines are electrically connected and configured to provide data signals to the connected data lines;
  • At least part of the multiplexing circuits adjacent to the arc-shaped display boundary are arranged in a stepped shape.
  • the non-display area further includes: multiple multiplexing control lines and multiple multiplexing data lines; each multiplexing circuit is respectively connected with multiple multiplexing control lines and a multiplexing control line. Electrically connected with a data line;
  • Multiple multiplexing control lines are located between multiple driving circuits and multiple multiplexing circuits; multiple multiplexing control lines close to the arc-shaped display boundary are stepped.
  • the non-display area further includes: a plurality of electrostatic discharge circuits, each of which is connected to a signal line and configured to discharge static electricity in the connected signal lines; the signal lines Including: multiplexed data lines;
  • a plurality of electrostatic discharge circuits are located between the plurality of driving circuits and the second power supply lines; at least part of the electrostatic discharge circuits near the arc-shaped display boundary are arranged in a stepped shape.
  • the non-display area further includes: a test control line and a plurality of test circuits; the test circuits are electrically connected to the test control line and the data line, respectively, and are configured to provide a test to the data line Signal;
  • the plurality of test circuits are located on a third side of the display area, the third side being different from the first side and the second side;
  • the test control line is located between the second power supply line and a plurality of electrostatic discharge circuits; the test control line close to the arc display boundary is stepped.
  • the non-display area further includes: a third power line and a fourth power line; each driving circuit is electrically connected to the third power line and the fourth power line, respectively; the third power line and the fourth power line is annular;
  • the third power line is located between the electrostatic discharge circuit and the plurality of driving circuits; the third power line near the arc display boundary is stepped;
  • the fourth power supply line is located between the third power supply line and the plurality of driving circuits, and the fourth power supply line near the arc display boundary is stepped.
  • the non-display area further includes: a first clock signal line, a second clock signal line, a signal input line and a signal output line, each driving circuit is connected to the first clock signal line, the second clock signal line The clock signal line, the signal input line and the signal output line are electrically connected;
  • the first clock signal line is located between the third power supply line and a plurality of driving circuits, and the first clock signal line near the arc display boundary is stepped;
  • the second clock signal line is located between the third power supply line and the first clock signal line; the second clock signal line near the arc display boundary is stepped;
  • the signal input line and the signal output line are located on one side of the driving circuit close to the display area.
  • the non-display area further includes: a plurality of multiplexed connection electrodes and a plurality of initial connection electrodes;
  • the multiplexing connection electrodes are respectively electrically connected with the multiplexing circuit and the data line,
  • the initial connection electrodes are respectively electrically connected to the initial signal line and the initial signal power supply line;
  • the multiplex connection electrodes and the multiple initial connection electrodes are arranged in the same layer, the initial connection electrodes are arranged in the same layer as the initial signal lines, and the multiplex connection electrodes and the data lines are in different layers. set up.
  • the non-display area further includes: a gate line connection electrode and a reset connection electrode;
  • the gate line connection electrodes are respectively electrically connected to the gate line and the signal output line;
  • the reset connection electrodes are respectively electrically connected to the reset signal line and the signal input line;
  • the gate line connection electrodes are provided in the same layer as the reset connection electrodes, and are provided in the same layer as the gate lines.
  • the non-display area further includes: an encapsulation electrode
  • the packaging electrode is located on the side of the second power supply line away from the display area; the packaging electrode and the second power supply line are arranged in different layers and are electrically connected to the second power supply line;
  • the package electrodes are provided with a plurality of via holes.
  • the display substrate further includes: a multiplexing circuit in the non-display area, an electrostatic discharge circuit, a testing circuit and a control circuit
  • the pixel circuit includes: a plurality of pixel transistors
  • the driving The circuit includes: a plurality of shift transistors
  • the multiplexing circuit includes: a plurality of multiplexing transistors
  • the electrostatic discharge circuit includes: a plurality of discharge transistors
  • the test circuit includes: a plurality of test transistors
  • the control The circuit includes: a plurality of control transistors;
  • the display substrate includes: a base and an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer and a third metal layer stacked on the base in sequence ;
  • the active layers include: active layers of a plurality of pixel transistors, active layers of a plurality of shift transistors, active layers of a plurality of multiplexing transistors, active layers of a plurality of release transistors, and active layers of a plurality of test transistors.
  • the first metal layer includes: control electrodes of multiple pixel transistors, control electrodes of multiple shift transistors, control electrodes of multiple multiplexing transistors, multiple test electrodes Control electrodes of transistors, control electrodes of multiple release transistors, control electrodes of multiple control transistors, multiplexed data lines, light-emitting control lines, gate lines, reset signal lines, gate line connection electrodes, reset connection electrodes, and package electrodes;
  • the second metal layer includes: an initial signal line, a multiplexing connection electrode and an initial connection electrode;
  • the third metal layer includes: first electrodes and second electrodes of a plurality of pixel transistors, and first electrodes of a plurality of shift transistors and second poles, first and second poles of multiple multiplexing transistors, first and second poles of multiple test transistors, first and second poles of multiple release transistors, multiple control transistors The first and second poles, the data line, the first power line, the first power supply line, the initial signal power supply line, the multiplexing control line,
  • the third insulating layer is provided with via holes exposing the multiplex connection electrodes and via holes exposing the initial connection electrodes; A via hole exposing the gate line connection electrode and a via hole exposing the reset connection electrode are provided;
  • the data line is electrically connected to the multiplexing connection electrode through the via hole exposing the multiplexing connection electrode, and the initial signal power supply line is electrically connected to the original signal line through the via hole exposing the original connection electrode;
  • the signal output line is electrically connected to the gate line connection electrode through the via hole exposing the gate line connection electrode, and the signal input line is electrically connected to the reset connection electrode through the via hole exposing the reset connection electrode.
  • the orthographic projection of the second power supply line on the substrate at least partially overlaps the orthographic projection of the package electrode on the substrate;
  • the second insulating layer and the third insulating layer are provided with via holes exposing the package electrodes; the second power supply line is electrically connected to the package electrodes through the via holes exposing the package electrodes;
  • a plurality of via hole arrays are also arranged on the second insulating layer and the third insulating layer; the orthographic projection of the via holes arranged on the package electrodes on the substrate covers the orthographic projection of the via hole array on the substrate .
  • the plurality of sub-pixels arranged along the second direction is called a row of sub-pixels, and the length of each row of sub-pixels along the first direction is 74 ⁇ m to 75 ⁇ m;
  • the length of each step in the stepped signal line along the first direction is an integer multiple of the length of each row of sub-pixels along the first direction;
  • the signal lines include: a first power supply line, an initial signal power supply line, a multiplexing control line, a third power supply line, a fourth power supply line, a first clock signal line, a second clock signal line, a test control line and a second power supply line. Power supply cord.
  • the present disclosure also provides a display device, comprising: the above-mentioned display substrate.
  • FIG. 1A is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • 1B is a schematic structural diagram of a sub-pixel
  • FIG. 2 is a layout of an area A1 in a display substrate provided by an exemplary embodiment
  • FIG. 3 is a schematic structural diagram of a package electrode provided by an exemplary embodiment
  • FIG. 4 is a partial schematic diagram of a region A2 of a display substrate provided by an exemplary embodiment
  • 5A is an equivalent circuit diagram of a pixel circuit provided by an exemplary embodiment
  • 5B is an equivalent circuit diagram of a driving circuit provided by an exemplary embodiment
  • 5C is a timing diagram of the driving circuit provided in FIG. 5B;
  • 5D is an equivalent circuit diagram of a control circuit provided by an exemplary embodiment
  • 5E is a timing diagram of the control circuit provided in FIG. 5D;
  • 5F is an equivalent circuit diagram of a multiplexing circuit provided by an exemplary embodiment
  • 5G is an equivalent circuit diagram of a test circuit provided by an exemplary embodiment
  • 5H is an equivalent circuit diagram of an electrostatic discharge circuit provided by an exemplary embodiment
  • FIG. 6 is a schematic diagram of a film layer of an active layer of a display substrate provided by an exemplary embodiment
  • FIG. 7 is a schematic diagram of a film layer of a first metal layer of a display substrate provided by an exemplary embodiment
  • FIG. 8 is a schematic diagram of a film layer of a second metal layer of a display substrate provided by an exemplary embodiment
  • FIG. 9 is a schematic diagram of a film layer of a third metal layer of a display substrate provided by an exemplary embodiment
  • 10A is a schematic diagram of a pixel circuit after forming an active layer
  • FIG. 10B is a schematic diagram of the drive circuit after the active layer is formed
  • 11A is a schematic diagram after forming a first metal layer
  • 11B is an enlarged schematic view of the pixel circuit after the first metal layer is formed
  • 11C is an enlarged schematic diagram of the driving circuit after forming the first metal layer
  • 12A is a schematic diagram after forming a second metal layer
  • FIG. 12B is an enlarged schematic view of the pixel circuit after forming the second metal layer
  • 12C is an enlarged schematic view of the driving circuit after forming the second metal layer
  • FIG. 13A is a schematic diagram after forming a third insulating layer
  • 13B is an enlarged schematic view of the pixel circuit after the third insulating layer is formed
  • 13C is an enlarged schematic view of the drive circuit after the third insulating layer is formed
  • 14A is a schematic diagram after forming a third metal layer
  • 14B is an enlarged schematic diagram of the pixel circuit after the third metal layer is formed
  • FIG. 14C is an enlarged schematic view of the driving circuit after the third metal layer is formed.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • transistors include: P-type transistors or N-type transistors, wherein the P-type transistor is turned on when the gate is low, and is turned off when the gate is high, and the N-type transistor is turned on when the gate is high. It is turned off when the gate is low.
  • electrically connected includes a case where constituent elements are connected together by an element having a certain electrical effect.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having a certain electrical effect” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • film and “layer” are interchangeable.
  • conductive layer may be replaced by “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • FIG. 1A is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG. 1B is a structural schematic diagram of a sub-pixel.
  • a display substrate provided by an embodiment of the present disclosure includes: a display area AA and a non-display area AA' surrounding the display area.
  • the display area includes at least one segment of an arc-shaped display boundary.
  • the display area AA includes: a plurality of sub-pixels 1, a plurality of data lines extending along the first direction, and a plurality of gate lines extending along the second direction (not shown in the figure).
  • Each sub-pixel includes: a pixel circuit 10 and a light-emitting element 100 connected to the pixel circuit 10.
  • the pixel circuit in each sub-pixel is electrically connected to the gate line and the data line, respectively; at least part of the sub-pixels close to the arc-shaped display boundary are arranged in a stepped row cloth.
  • the non-display area AA' includes a plurality of driving circuits 20 that are cascaded and supply driving signals to a plurality of gate lines. At least part of the driving circuits close to the arc-shaped display boundary are arranged in a stepped shape. Wherein, the first direction intersects with the second direction.
  • the shape of the display area may be a rounded polygon, or may be a circle.
  • the display area may further include: a straight line display boundary.
  • FIG. 1 is illustrated by taking an example that the display area is a quadrilateral with rounded corners.
  • a plurality of driving circuits close to the linear display boundary are arranged along the linear display boundary.
  • intersection of the first direction and the second direction means that the included angle between the first direction and the second direction is about 70 degrees to 90 degrees.
  • the light emitting element may be an organic light emitting diode OLED, and in this case, the display substrate is an organic light emitting diode OLED display substrate.
  • the representation forms of the sub-pixels 1 are various, and independent display can be implemented. Different sub-pixels 1 can have different colors, so that color display can be realized by light mixing of different sub-pixels 1 .
  • a plurality of sub-pixels 1 of different colors can be arranged together to form a "pixel (or pixel unit)", that is, the light emitted by these sub-pixels 1 is mixed together to form a visual "dot" ;
  • pixel or pixel unit
  • each intersection of the data line and the gate line can define a sub-pixel 1, and through the joint control of the gate line and the data line, the sub-pixel 1 at the intersection of the two can be show.
  • the sub-pixels in the display area may be arranged in an array, that is, the sub-pixels may be arranged in multiple rows and columns, each row of sub-pixels is connected to a gate line, and each column of sub-pixels is connected to a data line. It should be understood that the sub-pixels are not necessarily arranged in an array, and each data line and gate line are not necessarily connected to sub-pixels in the same column and row.
  • the number of driver circuits is the same as the number of rows of sub-pixels.
  • At least part of the driving circuits close to the arc-shaped display boundary are arranged in a stepped manner according to at least part of the sub-pixels close to the arc-shaped display boundary.
  • a distance along the second direction between at least part of the driving circuit of the arc-shaped display boundary and at least part of the sub-pixels arranged in a stepwise manner near the arc-shaped display boundary is smaller than a threshold distance.
  • the stepped distribution may be a 90-degree step, or may be a step of other angles, which is determined according to the layout of the display substrate.
  • At least a portion of the driving circuits near the boundary of the arc-shaped display may be arranged in a wavy shape.
  • a display substrate provided by an embodiment of the present disclosure includes: a display area and a non-display area surrounding the display area, the display area includes at least a segment of an arc-shaped display boundary; the display area includes: a plurality of sub-pixels, a plurality of strips extending along a first direction a data line and a plurality of grid lines extending along the second direction; each sub-pixel includes: a pixel circuit and a light-emitting element connected to the pixel circuit, and the pixel circuit in each sub-pixel is electrically connected to the grid line and the data line respectively; close to the arc At least part of the sub-pixels on the display boundary are arranged in a staircase shape; the non-display area includes: a plurality of cascaded driving circuits that provide driving signals to a plurality of gate lines; at least part of the driving circuits near the arc-shaped display boundary are in a staircase shape Arranged; wherein the first direction intersects the second direction.
  • the space occupied by the display device includes:
  • FIG. 2 is a layout of an area A1 in a display substrate provided by an exemplary embodiment.
  • the display area may further include: a plurality of first power lines VDD extending along a first direction and a plurality of initial signal lines Vinit extending along a second direction.
  • the pixel circuit in each sub-pixel is electrically connected to the first power supply line VDD and the initial signal line Vinit, respectively.
  • the non-display area may further include: a first power supply line S_VDD and an initial signal supply line S_Vinit.
  • the first power supply line S_VDD and the initial signal supply line S_Vinit are ring-shaped.
  • the first power supply line S_VDD is located on one side of the plurality of driving circuits close to the display area, and is electrically connected to the first power supply line VDD connected to each pixel circuit.
  • the initial signal power supply line S_Vinit is located between the plurality of driving circuits and the first power supply line, and is electrically connected to the initial signal line connected to each pixel circuit.
  • the first power supply line near the arc-shaped display boundary is stepped.
  • the arrangement of the first power supply line can realize a narrow frame of the display device.
  • the first power supply line close to the linear display boundary is linear.
  • the initial signal supply lines near the boundary of the arc-shaped display are stepped.
  • the arrangement of the initial signal power supply lines can realize a narrow frame of the display device.
  • the initial signal power supply line close to the straight line display boundary is in the shape of a straight line.
  • the line width of the first power supply line is larger than that of the initial signal supply line.
  • the display area further includes: a second power supply line (not shown in the figure), and the light-emitting element in each sub-pixel is electrically connected to the second power supply line.
  • the non-display area further includes: a second power supply line S_VSS; the second power supply line is annular.
  • the second power supply line is located on one side of the plurality of driving circuits away from the display area, and is electrically connected to the second power supply line connected to each light-emitting element.
  • the surface of the second power supply line close to the arc-shaped display boundary near the display area is stepped, and the surface of the second power supply line close to the arc-shaped display boundary away from the display area is arc-shaped.
  • the arrangement of the second power supply line can not only realize a narrow frame of the display device, but also reduce the resistance of the second power supply line.
  • the second power supply line close to the linear display boundary is linear.
  • the line width of the second power supply line S_VSS is larger than that of the first power supply line S_VDD.
  • the display area further includes: a plurality of light emission control lines EM and reset control lines Reset extending along the second direction; the pixel circuit in each sub-pixel and the light emission control lines and Reset the control line electrical connection.
  • the non-display area includes: a plurality of cascaded control circuits that provide control signals to a plurality of light-emitting control lines; at least part of the control circuits close to the arc-shaped display boundary are arranged in steps.
  • a plurality of control circuits close to the linear display boundary are arranged along the linear display boundary.
  • the plurality of driving circuits and the plurality of control circuits are located on oppositely disposed first sides C1 and second sides C2 of the display area, respectively.
  • the non-display area further includes: a plurality of multiplexing circuits 30, the multiplexing circuits 30 are located between the plurality of driving circuits and the initial signal power supply line S_Vinit, and are connected with the plurality of data lines an electrical connection configured to provide data signals to the connected data lines.
  • At least a portion of the multiplexing circuit 30 near the arc-shaped display boundary is arranged in a staircase pattern.
  • the arrangement of multiple multiplexing circuits can realize a narrow frame of the display device.
  • a plurality of multiplexing circuits close to the linear display boundary are arranged along the linear display boundary.
  • the non-display area further includes: multiple multiplexing control lines MUX and multiple multiplexing data lines 53; Use the control line MUX to electrically connect with a multiplexed data line 53;
  • the multiple multiplexing control lines MUX are located between the multiple driving circuits and the multiple multiplexing circuits; the multiple multiplexing control lines close to the boundary of the arc display are stepped.
  • the multiple multiplexing control lines close to the straight line display boundary are straight lines.
  • the non-display area further includes: a plurality of electrostatic discharge circuits 40 .
  • Each electrostatic discharge circuit 40 is connected to one signal line, and is configured to discharge static electricity in the connected signal line; the signal line includes: a multiplexed data line.
  • the plurality of electrostatic discharge circuits 40 are located between the plurality of driving circuits 20 and the second power supply line S_VSS. At least a portion of the electrostatic discharge circuit adjacent to the arc-shaped display boundary is arranged in a stepped arrangement.
  • a plurality of electrostatic discharge circuits close to the linear display boundary are arranged along the linear display boundary.
  • the non-display area further includes: a plurality of test circuits (not shown in the figure) and a test control line CT.
  • the test circuits are electrically connected to the test control lines and the data lines, respectively, and are configured to provide test signals to the data lines.
  • the plurality of test circuits are located on a third side C3 of the display area, and the third side C3 is different from the first side C1 and the second side C2 .
  • test control line CT is located between the second power supply line S_VSS and the plurality of electrostatic discharge circuits 40 .
  • the test control lines near the boundaries of the arc display are stepped.
  • the test control line close to the display boundary of the straight line is in the shape of a straight line.
  • the non-display area further includes: a third power supply line VGH and a fourth power supply line VGL.
  • Each driving circuit is electrically connected to the third power line and the fourth power line respectively; the third power line and the fourth power line are annular.
  • the third power supply line VGH is located between the electrostatic discharge circuit 40 and the plurality of driving circuits 20 .
  • the third power line VGH near the arc display boundary is stepped.
  • the third power line VGH close to the straight line display boundary is straight.
  • the fourth power supply line VGL is located between the first clock signal line CK and the plurality of driving circuits 20 .
  • the fourth power line VGL near the arc display boundary is stepped.
  • the fourth power supply line VGL close to the linear display boundary is linear.
  • the non-display area further includes: a first clock signal line CK, a second clock signal line CB, a signal input line and a signal output line (not shown in the figure), Each driving circuit is electrically connected to the first clock signal line CK, the second clock signal line CB, the signal input line and the signal output line, respectively.
  • the first clock signal line CK is located between the third power supply line VGH and the plurality of driving circuits 20, and the first clock signal line CK near the arc display boundary is stepped.
  • the first clock signal line close to the straight line display boundary is straight.
  • the second clock signal line CB is located between the third power supply line VGH and the first clock signal line CK; the second clock signal line CB near the arc display boundary is stepped.
  • the second clock signal line CB close to the straight line display boundary is in the shape of a straight line.
  • the signal input line and the signal output line are located on one side of the driving circuit close to the display area.
  • the non-display area further includes: a gate test line GT.
  • the gate test line GT is located between the third power supply line VGH and the second clock signal line CB, and is electrically connected to the last stage driving circuit.
  • FIG. 3 is a schematic structural diagram of a package electrode provided by an exemplary embodiment
  • FIG. 4 is a partial schematic diagram of an area A2 of a display substrate provided by an exemplary embodiment
  • the non-display area further includes: an encapsulation electrode 50 .
  • the package electrode 50 is located on the side of the second power supply line away from the display area; the package electrode 50 and the second power supply line S_VSS are disposed in different layers, and are electrically connected to the second power supply line S_VSS.
  • the package electrode is provided with a plurality of via holes V51.
  • FIG. 5A is an equivalent circuit diagram of a pixel circuit provided by an exemplary embodiment.
  • the pixel circuit is respectively connected with the first power supply line VDD, the data line Data, the gate line Gate, the reset signal line Reset, the initial signal line Vinit, the light-emitting control line EM and the light-emitting element. connected; the light-emitting element is connected to the second power supply line VSS.
  • the pixel circuit includes: a first pixel transistor PT1 to a sixth pixel transistor PT6 and a pixel storage capacitor PC.
  • the pixel storage capacitor PC includes: a first polar plate PC1 and a second polar plate PC2.
  • the control electrode of the first pixel transistor PT1 is electrically connected to the reset signal line Reset, the first electrode of the first pixel transistor PT1 is electrically connected to the first node N1, and the second electrode of the first pixel transistor PT1 is electrically connected to the initial signal line Vinit.
  • the control electrode of the second pixel transistor PT2 is electrically connected to the gate line Gate, the first electrode of the second pixel transistor PT2 is electrically connected to the first node N1, and the second electrode of the second pixel transistor PT2 is electrically connected to the second node N2.
  • the control electrode of the third pixel transistor PT3 is electrically connected to the first node N1, the first electrode of the third pixel transistor PT3 is electrically connected to the third node N3, and the second electrode of the third pixel transistor PT3 is electrically connected to the second node N2.
  • the control electrode of the fourth pixel transistor PT4 is electrically connected to the gate line Gate, the first electrode of the fourth pixel transistor PT4 is electrically connected to the data line Data, and the second electrode of the fourth pixel transistor PT4 is electrically connected to the third node N3.
  • the control electrode of the fifth pixel transistor PT5 is electrically connected to the light-emitting control line EM, the first electrode of the fifth pixel transistor PT5 is electrically connected to the first power supply line VDD, and the second electrode of the fifth pixel transistor PT5 is electrically connected to the third node N3 .
  • the control electrode of the sixth pixel transistor PT6 is electrically connected to the light emitting control line EM, the first electrode of the sixth pixel transistor PT6 is electrically connected to the second node N2, and the second electrode of the sixth pixel transistor PT6 is electrically connected to the light emitting element.
  • the first plate PC1 of the pixel storage capacitor PC is electrically connected to the first node N1
  • the second plate PC2 of the pixel storage capacitor PC is electrically connected to the first power line VDD.
  • the pixel circuit may be a 7T1C structure (ie, including 7 transistors and 1 capacitor).
  • the first power line VDD, the data line Data, the gate line Gate, the reset signal line Reset, the initial signal line Vinit and the light emission control line EM are located in the display area.
  • the first power line VDD and the data line Data extend along the second direction and are disposed at the same layer.
  • the gate line Gate, the reset signal line Reset, and the light-emitting control line EM extend along the first direction and are arranged in the same layer.
  • the initial signal line Vinit extends in the first direction.
  • the initial signal line Vinit is located on the side of the reset signal line Reset away from the gate line Gate; the light emission control line EM is located on the side of the gate line Gate away from the reset signal line Reset.
  • the first power supply line VDD is configured to continuously provide a high-level signal
  • the second power supply line VSS is configured to continuously provide a low-level signal
  • FIG. 5B is an equivalent circuit diagram of a driving circuit provided by an exemplary embodiment
  • FIG. 5C is a timing diagram of the driving circuit provided in FIG. 5B
  • the driving circuit is connected to the signal input line INPUT, the first clock signal line CK, the second clock signal line CB, the third power supply line VGH, the fourth power supply, respectively.
  • the line VGL and the signal input line OUT are electrically connected.
  • the driving circuit may be one gate shift register, and a plurality of gate shift registers are cascaded, so that the plurality of gate shift registers may respectively provide driving signals to a plurality of gate lines.
  • the driving circuit includes: first to eighth shift transistors GT1 to GT8 , a first shift storage capacitor GC1 and a second shift storage capacitor GC2 .
  • the control pole of the first shift transistor GT1 is electrically connected to the first clock signal line CK
  • the first pole of the first shift transistor GT1 is electrically connected to the signal input line INPUT
  • the second pole of the first shift transistor GT1 is electrically connected to the first clock signal line CK.
  • the node G1 is electrically connected; the control pole of the second shift transistor GT2 is electrically connected to the first node G1, the first pole of the second shift transistor GT2 is electrically connected to the first clock signal line CK, and the first pole of the second shift transistor GT2 is electrically connected to the first clock signal line CK.
  • the diode is electrically connected to the second node G2; the control electrode of the third shift transistor GT3 is electrically connected to the first clock signal line CK, the first electrode of the third shift transistor GT3 is electrically connected to the fourth power supply line VGL, and the third shift transistor GT3 is electrically connected to the fourth power supply line VGL.
  • the second pole of the shift transistor GT3 is electrically connected to the second node G2; the control pole of the fourth shift transistor GT4 is electrically connected to the second node G2, and the first pole of the fourth shift transistor GT4 is electrically connected to the third power supply line VGH.
  • the control pole of the fifth shift transistor GT5 is electrically connected to the third node G3, and the first pole of the fifth shift transistor GT5 is electrically connected to the second
  • the clock signal line CB is electrically connected, the second pole of the fifth shift transistor GT5 is electrically connected to the signal output line OUT; the control pole of the sixth shift transistor GT6 is electrically connected to the second node G2, and the second pole of the sixth shift transistor GT6 is electrically connected to the second node G2.
  • One pole is electrically connected to the third power supply line VGH
  • the second pole of the sixth shift transistor GT6 is electrically connected to the first pole of the seventh shift transistor GT7
  • the control pole of the seventh shift transistor GT7 is electrically connected to the second clock signal line CB is electrically connected, the second pole of the seventh shift transistor GT7 is electrically connected to the first node G1
  • the control pole of the eighth shift transistor GT8 is electrically connected to the fourth power supply terminal VGL
  • the first pole of the eighth shift transistor GT8 is electrically connected It is electrically connected to the first node G1, the second pole of the eighth shift transistor GT8 is electrically connected to the third node G3
  • the first plate GC11 of the first shift storage capacitor GC1 is electrically connected to the third power line VGH
  • the first The second plate GC12 of the displacement storage capacitor GC1 is electrically connected to the second node GC12
  • the first plate GC21 of the second displacement storage capacitor GC2 is electrically connected to the signal output line OUT
  • the third power line VGH continuously provides a high-level signal
  • the fourth power line VGL continuously provides a low-level signal
  • the first to eighth shift transistors GT1 to GT8 may be P-type transistors or may be N-type transistors.
  • a working process of the driving circuit includes the following stages:
  • the signal of the first clock signal line CK is at a low level
  • the signal of the second clock signal line CB is at a high level
  • the signal of the signal input terminal INPUT is at a low level. Since the signal of the first clock signal line CK is at a low level, the first shift transistor GT1 is turned on, and the signal of the signal input terminal INPUT is transmitted to the first node G1 through the first shift transistor GT1. Since the signal of the eighth shift transistor GT8 receives the low level signal of the fourth power supply terminal VGL, the eighth shift transistor GT8 is in an on state.
  • the level of the third node G3 can control the fifth shift transistor GT5 to be turned on, and the signal of the second clock signal line CB is transmitted to the signal output line OUT via the fifth shift transistor GT5, that is, in the input stage t1, the signal output line OUT The signal of the second clock signal line CB which is a high level.
  • the third shift transistor GT3 is turned on, and the low level signal of the fourth power supply line VGL is transmitted to the second node G2 via the third shift transistor GT3.
  • both the fourth shift transistor GT4 and the sixth shift transistor GT6 are turned on. Since the signal of the second clock signal line CB is at a high level, the seventh shift transistor GT7 is turned off.
  • the signal of the first clock signal line CK is high level
  • the signal of the second clock signal line CB is low level
  • the signal of the signal input terminal INPUT is high level.
  • the fifth shift transistor GT5 is turned on, and the signal of the second clock signal line CB is used as the signal of the signal output terminal OUT via the fifth shift transistor GT5.
  • the level of one end of the second shift storage capacitor GC2 connected to the output terminal OUT becomes the signal of the fourth power supply line VGL. Due to the bootstrap effect of the second shift storage capacitor GC2, the eighth shift transistor GT8 is turned off, the fifth shift transistor GT5 can be turned on better, and the signal of the signal output terminal OUT is at a low level.
  • the signal of the first clock signal line CK is at a high level, so that both the first shift transistor GT1 and the third shift transistor GT3 are turned off.
  • the second shift transistor GT2 is turned on, and the high level of the first clock signal line CK is transmitted to the second node G2 through the second shift transistor GT2, so that the fourth shift transistor GT4 and the sixth shift transistor GT6 are both deadline. Since the signal of the second clock signal line CB is at a low level, the seventh shift transistor GT7 is turned on.
  • the signals of the first clock signal line CK and the second gate clock signal CB are both high level, the signal of the signal input terminal INPUT is high level, the fifth shift transistor GT5 is turned on, and the second gate The pole clock signal CB is used as the gate output signal GOUT via the fifth shift transistor GT5.
  • the gate output signal GOUT is the second gate clock signal CB with a high level, namely VGH. Due to the bootstrap effect of the second gate capacitor C2, the level of the first gate node N1 becomes VGL-VthN1.
  • the signal of the first clock signal line CK is at a high level, so that both the first shift transistor GT1 and the third shift transistor GT3 are turned off, the eighth shift transistor GT8 is turned on, and the second shift transistor GT2 is turned on.
  • the high-level signal of the first clock signal line CK is transmitted to the second node G2 via the second shift transistor GT2, whereby both the fourth shift transistor GT4 and the sixth shift transistor GT6 are turned off. Since the signal of the second clock signal line CB is at a high level, the seventh shift transistor GT7 is turned off.
  • the signal of the first clock signal line CK is at a low level
  • the signal of the second clock signal CB is at a high level
  • the signal at the signal input terminal INPUT is at a high level. Since the signal of the first clock signal line CK is at a low level, the first shift transistor GT1 is turned on, the signal of the signal input terminal INPUT is transmitted to the first node G1 through the first shift transistor GT1, and the second shift transistor GT2 is turned off . Since the eighth shift transistor GT8 is in an on state, the fifth shift transistor GT5 is turned off.
  • the third shift transistor GT3 Since the signal of the first clock signal line CK is at a low level, the third shift transistor GT3 is turned on, the fourth shift transistor GT4 and the sixth shift transistor GT6 are both turned on, and the high level signal of the third power supply line VGH It is transmitted to the signal output line OUT through the fourth shift transistor GT4, that is, the gate output signal is a high level signal.
  • the signal of the first clock signal line CK is at a high level
  • the signal of the second clock signal CB is at a low level
  • the signal at the signal input terminal INPUT is at a high level.
  • Both the fifth shift transistor GT5 and the second shift transistor GT2 are turned off.
  • the signal of the first clock signal line CK is at a high level, so that both the first shift transistor GT1 and the third shift transistor GT3 are turned off. Due to the holding effect of the first shift storage capacitor C1, the fourth shift transistor GT4 and the third shift transistor GT3 are turned off.
  • the sixth shift transistors GT6 are all turned on, and the high-level signal is transmitted to the signal output line OUT through the fourth shift transistor GT4, that is, the gate output signal is a high-level signal.
  • the seventh shift transistor GT7 is turned on, so that the high level signal passes through the sixth shift transistor GT6 and the seventh shift transistor GT7 It is transmitted to the third node G3 and the first node G1 so that the signals of the third node G3 and the first node G1 are kept at a high level.
  • the signals of the first clock signal line CK and the second gate clock signal CB are both high level, and the signal of the signal input terminal INPUT is high level.
  • the fifth shift transistor GT5 and the second shift transistor GT2 are turned off.
  • the signal of the first clock signal line CK is at a high level, so that the first shift transistor GT1 and the third shift transistor GT3 are both turned off, and the fourth shift transistor GT4 and the sixth shift transistor GT6 are both turned on.
  • the high-level signal is sent to the signal output line OUT through the fourth shift transistor GT4, that is, the gate output signal is a high-level signal.
  • FIG. 5D is an equivalent circuit diagram of a control circuit provided by an exemplary embodiment
  • FIG. 5E is a timing diagram of the control circuit provided by FIG. 5D
  • the control circuit is respectively connected with the control input line EMINPUT, the third clock signal line CK', the fourth clock signal line CB', the third power supply line VGH, the third clock signal line
  • the four power lines VGL are electrically connected with the control input line EMOUT.
  • each control circuit may be a gate shift register, and a plurality of gate shift registers are cascaded, so that the plurality of gate shift registers may respectively provide a plurality of lighting control lines drive signal.
  • the driving circuit includes: a first control transistor ET1 to a tenth control transistor ET10 and a first control storage capacitor EC1 to a third control storage capacitor EC3.
  • the control electrode of the first control transistor ET1 is electrically connected to the third clock signal line CK', the first electrode of the first control transistor ET1 is electrically connected to the control input line EMINPUT, and the second electrode of the first control transistor ET1 is electrically connected to the first node E1 Electrically connected; the control pole of the second control transistor ET2 is electrically connected to the first node E1, the first pole of the second control transistor ET2 is electrically connected to the third clock signal line CK', and the second pole of the second control transistor ET2 is electrically connected to the first node E1.
  • the two nodes E2 are electrically connected; the control pole of the third control transistor ET3 is electrically connected to the third clock signal line CK', the first pole of the third control transistor ET3 is electrically connected to the fourth power supply line VGL, and the first pole of the third control transistor ET3 is electrically connected to the fourth power supply line VGL.
  • the diode is electrically connected to the second node E2; the control electrode of the fourth control transistor ET4 is electrically connected to the fourth clock signal line CB', the first electrode of the fourth control transistor ET4 is electrically connected to the first node E1, and the fourth control transistor ET4 is electrically connected to the first node E1.
  • the second pole of ET4 is electrically connected to the first pole of the fifth control transistor ET5; the control pole of the fifth control transistor ET5 is electrically connected to the second node E2, and the second pole of the fifth control transistor ET5 is electrically connected to the third power supply line VGH.
  • the control pole of the sixth control transistor ET6 is electrically connected to the second node E2, the first pole of the sixth control transistor ET6 is electrically connected to the fourth clock signal line CB', the second pole of the sixth control transistor ET6 is electrically connected to the third The node E3 is electrically connected; the control pole of the seventh control transistor ET7 is electrically connected to the fourth clock signal line CB', the second pole of the seventh control transistor ET7 is electrically connected to the control pole of the ninth control transistor ET9; the eighth control transistor ET8 The control electrode of the eighth control transistor ET8 is electrically connected to the first node E1, the first electrode of the eighth control transistor ET8 is electrically connected to the third power supply line VGH, and the second electrode of the eighth control transistor ET8 is electrically connected to one plate of the second control storage capacitor EC.
  • the first pole of the ninth control transistor ET9 is electrically connected to the third power supply line VGH, the second pole of the ninth control transistor ET9 is electrically connected to the control output line EMOUT;
  • the control pole of the tenth control transistor ET10 is electrically connected to the first node E1 Electrically connected, the first pole of the tenth control transistor ET10 is electrically connected to the fourth power supply line VGL, the second pole of the tenth control transistor ET10 is electrically connected to the control output line EMOUT;
  • the two nodes E2 are electrically connected, and the other plate of the first control storage capacitor EC1 is electrically connected to the third node E3; the other plate of the second control storage capacitor EC2 is electrically connected to the third power line VGH;
  • the third control storage capacitor One pole plate of EC3 is electrically connected to the first node E1, and the other pole plate of the third control storage capacitor EC3 is electrically connected to the fourth clock signal line CB'.
  • the first to tenth control transistors ET1 to ET10 may be P-type transistors or may be N-type transistors.
  • the low level of the following signal may be equal to the low level of the fourth power supply line VGL, and the high level of the signal may be equal to the third power supply
  • the high level of the line VGH as shown in FIG. 5E , the working process of the control circuit provided by an exemplary embodiment includes the following stages:
  • the signal of the third clock signal line CK' is at a low level, so the first control transistor ET1 and the third control transistor ET3 are turned on, and the turned-on first control transistor ET1 will control the high level of the output terminal EMINPUT
  • the level signal is transmitted to the first node E1, so that the level of the first node E1 becomes a high level, so the second control transistor ET2, the eighth control transistor ET8, and the tenth control transistor ET10 are turned off.
  • the turned-on third control transistor ET3 transmits the low level signal of the third power supply line VGL to the second node E2, so that the level of the second node E2 becomes a low level, so the fifth control transistor ET5 and The sixth control transistor ET6 is turned on.
  • the seventh control transistor ET7 Since the signal of the fourth clock signal line CB' is at a high level, the seventh control transistor ET7 is turned off. In addition, due to the storage function of the third control storage capacitor EC3, the ninth control transistor ET9 is turned off. In the first phase P1, since both the ninth control transistor ET9 and the tenth control transistor ET10 are turned off, the signal of the control output line EMOUT maintains the previous low level.
  • the signal of the fourth clock signal line CB' is at a low level, so the fourth control transistor ET4 and the seventh control transistor ET7 are turned on. Since the signal of the third clock signal line CK' is at a high level, the first control transistor ET1 and the third control transistor ET3 are turned off. Due to the storage function of the first control storage capacitor EC1, the second node E2 can continue to maintain the low level of the previous stage, so the fifth control transistor ET5 and the sixth control transistor ET6 are turned on.
  • the high-level signal of the third power supply line VGH is transmitted to the first node E1 through the turned-on fifth control transistor ET5 and the fourth control transistor ET4, so that the level of the first node E1 continues to maintain the high level of the previous stage , so the second control transistor ET2, the eighth control transistor ET8 and the tenth control transistor ET10 are turned off.
  • the low-level signal of the fourth clock signal line CB' is transmitted to the control electrode of the ninth control transistor ET9 through the turned-on sixth control transistor ET6 and the seventh control transistor ET7, and the ninth control transistor ET9 is turned on,
  • the turned-on ninth control transistor ET9 outputs the high level signal of the third power supply line VGH, so the signal of the control output line EMOUT is high level.
  • the signal of the third clock signal line CK' is at a low level, so the first control transistor ET1 and the third control transistor ET3 are turned on. Since the signal of the fourth clock signal line CB' is at a high level, the fourth control transistor ET4 and the seventh control transistor ET7 are turned off. Due to the storage function of the third control storage capacitor EC3, the ninth control transistor ET9 remains on, and the on-state ninth control transistor ET9 outputs the high-level signal of the third power supply line VGH, so the signal of the control output line EMOUT is still to high level.
  • the signal of the third clock signal line CK' is at a high level, so the first control transistor ET1 and the third control transistor ET3 are turned off. Since the signal of the fourth clock signal line CB' is at a low level, the fourth control transistor ET4 and the seventh control transistor ET7 are turned on. Due to the storage function of the second control storage capacitor EC2, the level of the first node E1 maintains the high level of the previous stage, so that the second control transistor ET2, the eighth control transistor ET8 and the tenth control transistor ET10 are turned off. Due to the storage function of the first control storage capacitor EC1, the second node E2 continues to maintain the low level of the previous stage, so that the fifth control transistor ET5 and the sixth control transistor ET6 are turned on.
  • the low-level signal of the fourth clock signal line CB' is transmitted to the gate of the ninth control transistor ET9 through the turned-on sixth control transistor ET6 and the seventh control transistor ET7, so the ninth control transistor ET9 is turned on , the turned-on ninth control transistor ET9 outputs the high level signal of the third power supply line VGH, so the signal of the control output line EMOUT is still at the high level.
  • the signal of the third clock signal line CK' is at a low level, so the first control transistor ET1 and the third control transistor ET3 are turned on. Since the signal of the fourth clock signal line CB' is at a high level, the fourth control transistor ET4 and the seventh control transistor ET7 are turned off.
  • the turned-on first control transistor ET1 transmits the high-level signal of the control input line EMINPUT to the first node E1, so that the level of the first node E1 becomes a low level, so the second control transistor ET2, the eighth control The transistor ET8 and the tenth control transistor ET10 are turned on.
  • the turned-on second control transistor ET2 transmits the signal of the low-level third clock signal line CK' to the second node E2, so that the level of the second node E2 can be further pulled down, so the second node E2 continues to keep on A stage of low level, so that the fifth control transistor ET5 and the sixth control transistor ET6 are turned on.
  • the turned-on eighth control transistor ET8 transmits the high-level signal of the third power supply line VGH to the gate of the ninth control transistor ET9, so the ninth control transistor ET9 is turned off.
  • the turned-on tenth control transistor ET10 outputs the low level signal of the fourth power supply line VGL, so the signal of the control output line EMOUT becomes the low level.
  • FIG. 5F is an equivalent circuit diagram of a multiplexing circuit provided by an exemplary embodiment.
  • at least one multiplexing circuit includes multiple multiplexing transistors; the gate of each multiplexing transistor is connected to a multiplexing control line, the first electrode is connected to a data line Data, and the second electrode is connected to a multiplexing transistor.
  • FIG. 5F illustrates an example in which the multiplexing circuit includes six multiplexing transistors MT1 to MT6.
  • the number of multiplexing transistors included in the multiplexing circuit depends on the number of multiplexed data lines.
  • the second electrodes of all the multiplexing transistors of the same multiplexing circuit are connected to the same multiplexing data line, and the second electrodes of the multiplexing transistors of different multiplexing circuits are connected differently of multiplexed data lines.
  • turn-on signals may be fed to multiple multiplexed control lines in turn, so that one multiplexed data line passes through one multiplexed data line.
  • Multiple multiplexing transistors in the circuit are turned on with multiple different data lines in turn, so as to provide the required data signals to multiple data lines through a multiplexed data line, that is, to realize the realization of a signal source (such as a connector) 6)
  • Control of multiple data lines 11 that is, to achieve "one drag and more", such as one drag 6), so that the number of signal sources that provide signals for the data lines is much smaller than the number of data lines, so as to simplify the product structure, for example, it can be Reduce the number of driver chips required.
  • the number of multiplexing control lines can be equal to the number of multiplexing transistors in each multiplexing circuit (for example, 6), that is, multiple multiplexing circuits in each multiplexing circuit
  • the transistors can be respectively connected to different multiplexing control lines, and each multiplexing control line is connected to one multiplexing transistor in each multiplexing circuit.
  • the multiplexing control line since the multiplexing control line connects a plurality of multiplexing circuits, the multiplexing control line may have a portion extending along the circumferential direction of the non-display area, and different positions of the portion are respectively connected to different multiplexing circuit.
  • Each multiplexing data line is only connected to one multiplexing circuit, so each multiplexing data line can be directly connected to the corresponding multiplexing circuit.
  • FIG. 5G is an equivalent circuit diagram of a test circuit provided by an exemplary embodiment.
  • the test circuit is electrically connected to the test signal line CT and the test data line, respectively.
  • At least one test circuit includes a plurality of test transistors; the gate of each test transistor is connected to a test control line CT, the first electrode is connected to a data line Data, and the second electrode is connected to a test data line.
  • 5G illustrates an example that the test circuit includes three test transistors: the first test transistor CT1 to the third test transistor CT3, and the test data line includes: the first test data line C_Data1 to the third test data line C_Data3.
  • each test data line is connected to a plurality of test circuits.
  • the signals in the test signal line can enter a plurality of corresponding data lines through the test transistors in different test circuits, In order to realize the detection of the display device.
  • each test data line is connected to a plurality of test circuits, the number of test data lines is much smaller than the number of multiplexed data lines. Therefore, although the test circuit is located above the display device, since the control of the test circuit can be realized only through a few test signal lines extending to the test circuit, these few test signal lines will not occupy a large amount of cloth. map area.
  • test data line the test control line and the test circuit
  • test control line the test circuit
  • the number of test data lines may be equal to the number of test transistors in each test circuit (for example, three), and there is only one test control line, that is, each test data line is connected to each test.
  • the second electrode of one test transistor in the circuit, the first electrode of different test transistors is connected to different data lines 11, and the gates of all test transistors of all test circuits are connected to the test control line.
  • the color of the sub-pixels connected to each data line may be the same (in the figure, R represents the red sub-pixel 1, G represents the green sub-pixel 1, and B represents the blue sub-pixel 1), and each The sub-pixels connected to the data lines corresponding to the test data lines are of the same color, so by continuously feeding the same test signal to the test data lines, the sub-pixels of the same color can display the same brightness (such as displaying a white image or other monochrome images as a whole). ), which is convenient for locating bad sub-pixels.
  • the multiplexed signal lines include multiplexed control lines and multiplexed data lines
  • the test signal lines include test control lines and test data lines.
  • the number of multiplexed signal lines is much more than the sum of the number of test signal lines. Therefore, a larger number of multiplexed signal lines can be connected to the multiplexing circuit "nearly"; It can be connected to the test circuit by extending a long distance, but because the number of test signal lines is small, the total length of the leads will not be too large; thus, the above design can reduce the total length of the leads and the layout area occupied , reducing the frame of the display device and increasing the screen ratio.
  • FIG. 5H is an equivalent circuit diagram of an electrostatic discharge circuit provided by an exemplary embodiment. As shown in FIG. 5H , in an exemplary embodiment, at least one electrostatic discharge circuit is connected to one signal line, and is configured to discharge static electricity in the connected signal line, wherein the signal line is the multiplexed data line 53 .
  • the electrostatic discharge circuit includes first to fourth discharge transistors ST1 to ST4.
  • the control electrode and the first electrode of the first release transistor ST1 are electrically connected to the fourth power supply line VGL
  • the second electrode of the first release transistor ST1 is electrically connected to the first electrode of the second release transistor ST2
  • the control of the second release transistor ST2 The electrode and the second electrode are electrically connected to the signal line corresponding to the electrostatic discharge circuit
  • the first electrode of the third discharge transistor ST3 is electrically connected to the signal line corresponding to the electrostatic discharge circuit
  • the control electrode and the second electrode of the third discharge transistor ST3 are electrically connected to the signal line corresponding to the electrostatic discharge circuit.
  • the first electrodes of the four release transistors ST4 are electrically connected
  • the control electrodes and the second electrodes of the fourth release transistor ST4 are electrically connected to the third power supply line VGH.
  • the electrostatic discharge circuit is provided to prevent the static electricity accumulated in the signal line from causing damage due to discharge breakdown, so as to release the static electricity accumulated in the signal line and realize the protection of the signal line.
  • the signal line connected to each electrostatic discharge circuit may be a test signal line.
  • an electrostatic discharge circuit may include two discharge transistors, where one pole of each discharge transistor is connected to its own gate, forming an equivalent diode connection; and two "diodes"
  • the signal lines to be protected are connected between them, and the other two ends of the two “diodes” are respectively connected to the third power line VGH and the fourth power line VGL. Therefore, when an instantaneous high voltage (such as 100V) occurs in the signal line due to the accumulation of positive charges, one of the "diodes” is turned on, releasing the positive charge in the signal line; -100V), the other "diode” conducts, releasing the negative charge in the signal line.
  • an instantaneous high voltage such as 100V
  • FIG. 6 is a schematic diagram of a film layer of an active layer of a display substrate provided by an exemplary embodiment
  • FIG. 7 is a schematic diagram of a film layer of a first metal layer of a display substrate provided by an exemplary embodiment
  • FIG. 8 is a schematic diagram of a film layer of a first metal layer of a display substrate provided by an exemplary embodiment.
  • FIG. 9 is a schematic diagram of the film layer of the third metal layer of the display substrate provided by an exemplary embodiment. As shown in FIGS.
  • the display substrate includes: a base, and an active layer, a first insulating layer, a first metal layer, a second insulating layer, a first insulating layer, a first insulating layer, a Two metal layers, a third insulating layer and a third metal layer.
  • the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but not limited to, one or more of glass and metal tabs; the flexible substrate may be, but not limited to, polyparaphenylene ethylene dicarboxylate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene , one or more of textile fibers.
  • the active layer includes: the active layer 11 of the pixel circuit, the active layer 21 of the driving circuit, the active layer 31 of the multiplexing circuit, and the electrostatic discharge circuit.
  • the active layer 11 of the pixel circuit includes: active layers of a plurality of pixel transistors.
  • the active layer of the driving circuit includes the active layers of a plurality of shift transistors.
  • the active layer of the multiplexing circuit includes: active layers of a plurality of multiplexing transistors.
  • the active layer of the electrostatic discharge circuit includes a plurality of active layers of discharge transistors.
  • the active layer of the test circuit includes: active layers of a plurality of test transistors.
  • the active layer of the driving circuit includes: active layers of a plurality of control transistors.
  • the first metal layer includes: the first metal layer 12 of the pixel circuit, the first metal layer 22 of the driving circuit, the first metal layer 32 of the multiplexing circuit, and the first metal layer 32 of the electrostatic discharge circuit.
  • the first metal layer of the pixel circuit includes: the control electrodes of a plurality of pixel transistors and the first electrode plate of the pixel storage capacitor.
  • the first metal layer of the driving circuit includes: control electrodes of a plurality of shift transistors, a second electrode plate of the first shift storage capacitor, and a second electrode plate of the second shift storage capacitor.
  • the first metal layer of the multiplexing circuit includes: gate electrodes of a plurality of multiplexing transistors.
  • the first metal layer of the electrostatic discharge circuit includes the gate electrodes of a plurality of discharge transistors.
  • the first metal layer located in the non-display area further includes: a gate line connection electrode 51 and a reset connection electrode 52 .
  • the gate line connection electrodes 51 are respectively electrically connected to the gate lines Gate and the signal output lines; the reset connection electrodes 52 are respectively electrically connected to the reset signal lines Reset and the signal input lines.
  • the second metal layer includes: the second metal layer 13 of the pixel circuit, the second metal layer 23 of the driving circuit, and the initial signal line Vinit.
  • the second metal layer of the pixel circuit includes: a second electrode plate of the pixel storage capacitor and a power supply connection line.
  • the second metal layer of the driving circuit includes: a first connection electrode, a second connection electrode, a first electrode plate of the first shift storage capacitor and a first electrode plate of the second shift storage capacitor.
  • the second metal layer located in the non-display area further includes: a multiplexing connection electrode 61 and an initial connection electrode 62 .
  • the multiplexing connection electrodes 61 are electrically connected to the multiplexing circuit and the data line, respectively, and the initial connection electrodes 62 are electrically connected to the initial signal line Vinit and the initial signal power supply line, respectively.
  • the third insulating layer is provided with via holes exposing the multiplex connection electrodes and via holes exposing the initial connection electrodes; the second insulating layer and the third insulating layer are provided with exposing gates The via hole of the wire connection electrode and the via hole exposing the reset connection electrode;
  • the data line is electrically connected to the multiplexing connection electrode through the via hole exposing the multiplexing connection electrode, and the initial signal power supply line is electrically connected to the original signal line through the via hole exposing the original connection electrode;
  • the signal output line is electrically connected to the gate line connection electrode through the via hole exposing the gate line connection electrode, and the signal input line is electrically connected to the reset connection electrode through the via hole exposing the reset connection electrode.
  • the third metal layer includes: the third metal layer 14 of the pixel circuit, the third metal layer 24 of the driving circuit, the third metal layer 34 of the multiplexing circuit, and the third metal layer of the electrostatic discharge circuit 44.
  • the third metal layer of the test circuit (not shown in the figure), the third metal layer of the control circuit (not shown in the figure), the connection electrode 71, the data line Data, the first power line VDD, and the first power supply line S_VDD, initial signal power supply line S_Vinit, multiplexing control line MUX, third power supply line VGH, fourth power supply line VGL, first clock signal line CK, second clock signal line CB, first clock signal line CK', th Two clock signal lines CB', test control lines CT and second power supply lines S_VSS.
  • the third metal layer of the pixel circuit includes: first electrodes and second electrodes of a plurality of pixel transistors.
  • the third metal layer of the driving circuit includes: first electrodes and second electrodes of a plurality of shift transistors.
  • the third metal layer of the multiplexing circuit includes: first electrodes and second electrodes of a plurality of shift transistors.
  • the third metal layer of the electrostatic discharge circuit includes: first electrodes and second electrodes of a plurality of discharge transistors.
  • the third metal layer of the test circuit includes: first electrodes and second electrodes of a plurality of test transistors.
  • the third metal layer of the control circuit includes: first electrodes and second electrodes of a plurality of control transistors.
  • the orthographic projection of the second power supply line S_VSS on the substrate at least partially overlaps the orthographic projection of the package electrode 50 on the substrate.
  • the second insulating layer and the third insulating layer are provided with via holes V11 exposing the package electrodes; the second power supply line is electrically connected to the package electrodes through the via holes exposing the package electrodes.
  • a plurality of via hole arrays V10 are disposed on the second insulating layer and the third insulating layer.
  • the orthographic projection of the vias disposed on the package electrodes on the substrate overlaps the orthographic projection of the via array on the substrate.
  • the plurality of sub-pixels arranged along the second direction is referred to as a row of sub-pixels, and the length of each row of sub-pixels along the first direction is 74 microns to 75 microns.
  • the length along the first direction of each step in the step-shaped signal line is close to the arc-shaped display boundary and is an integer multiple of the length along the first direction of each row of sub-pixels .
  • the signal lines include: a first power supply line, an initial signal power supply line, a multiplexing control line, a third power supply line, a fourth power supply line, a first clock signal line, a second clock signal line, a test control line and a second power supply line Power supply cord.
  • the first metal layer, the second metal layer, and the third metal layer may use metal materials, such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo).
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo).
  • Any one or more, or alloy materials of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo and the like.
  • the first insulating layer, the second insulating layer and the third insulating layer may adopt any one of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON). or more, it may be a single layer, multiple layers or composite layers.
  • the first insulating layer is called a first gate insulating layer
  • the second insulating layer is called a second gate insulating layer
  • the third insulating layer is called an interlayer insulating layer.
  • FIGS. 10 to 14 are schematic diagrams of a manufacturing process of a display substrate provided by an exemplary embodiment, and illustrate a layout structure in an area A1 of the display substrate. The following describes a display substrate provided by an exemplary embodiment with reference to FIG. 6 and FIG. 10 to FIG. 14 .
  • Forming an active layer on a substrate includes: depositing a semiconductor thin film on the substrate, and patterning the semiconductor thin film through a patterning process to form an active layer.
  • the active layer includes: the active layer 11 of the pixel circuit, the active layer 21 of the driving circuit, the active layer 31 of the multiplexing circuit, the active layer 41 of the electrostatic discharge circuit, and the active layer of the test circuit (Fig. not shown) and the active layer of the control circuit (not shown).
  • the active layer of the pixel circuit includes: the active layer PT11 of the first pixel transistor to the active layer PT61 of the active layer of the sixth pixel transistor.
  • the active layer 21 of the driving circuit includes: the active layer GT11 of the first shift transistor to the active layer GT81 of the eighth shift transistor, as shown in FIG. 6 , FIG. 10A and FIG. 10B , FIG. 10A is a pixel circuit formed with A schematic diagram after the source layer, FIG. 10B is a schematic diagram after the driver circuit forms the active layer.
  • Forming the first metal layer includes: depositing a first insulating film on the substrate on which the active layer is formed, and patterning the first insulating film through a patterning process to form the first insulating layer.
  • a first metal film is deposited on the first insulating layer, and the first metal film is patterned through a patterning process to form a first metal layer.
  • the first metal layer includes: the first metal layer 12 of the pixel circuit, the first metal layer 22 of the driving circuit, the first metal layer 32 of the multiplexing circuit, the first metal layer 42 of the electrostatic discharge circuit, and the first metal layer of the test circuit.
  • a metal layer (not shown in the figure), the first metal layer of the control circuit (not shown in the figure), the multiplexed data line 53, the light-emitting control line EM, the gate line Gate, the reset signal line Reset, the package electrode 50, The gate line connection electrode 51 and the reset connection electrode 52 are connected.
  • the first metal layer of the pixel circuit includes: the control electrode PT12 of the first pixel transistor to the control electrode PT62 of the sixth pixel transistor and the first electrode plate PC1 of the pixel storage capacitor.
  • the first metal layer of the driving circuit includes: the control electrode GT12 of the first shift transistor to the control electrode GT82 of the eighth shift transistor, the second plate GC12 of the first shift storage capacitor, and the second electrode of the second shift storage capacitor. Diode plate GC22.
  • the first metal layer of the multiplexing circuit includes: gate electrodes of a plurality of multiplexing transistors.
  • the first metal layer of the electrostatic discharge circuit includes the control electrodes of a plurality of discharge transistors, as shown in FIG. 11A , FIG. 11B and FIG. 11C ,
  • FIG. 11A is a schematic diagram after forming the first metal layer
  • FIG. 11B is the pixel circuit forming the first metal layer.
  • 11C is an enlarged schematic diagram of the driving circuit after the first metal layer is formed.
  • control electrode PT12 of the first pixel transistor and the reset signal line Reset are integrally formed, the control electrode PT22 of the second pixel transistor and the control electrode PT42 of the fourth pixel transistor, the gate line Gate and the gate line Gate
  • the control electrode PT32 of the third pixel transistor is integrally formed with the first plate PC1 of the pixel storage capacitor PC, and the control electrode PT52 of the fifth pixel transistor and the control electrode PT62 of the sixth pixel transistor are integrally formed with the light-emitting control line EM.
  • control electrode GT12 of the first shift transistor is integrally formed with the control electrode GT32 of the third shift transistor, the control electrode GT42 of the fourth shift transistor and the second shift storage capacitor
  • the electrode plate GC12 is integrally formed, and the control electrode GT52 of the fifth shift transistor and the second electrode plate GC22 of the second shift storage capacitor are integrally formed.
  • the gate line connection electrode 51 is electrically connected to the gate line Gate, and the reset connection electrode 52 is electrically connected to the reset signal line Reset.
  • Forming the second metal layer includes: depositing a second insulating film on the substrate on which the first metal layer is formed, and patterning the second insulating film through a patterning process to form a second insulating layer.
  • a second metal thin film is deposited on the substrate on which the second insulating layer is formed, and the second metal thin film is patterned through a patterning process to form a second metal layer.
  • the second metal layer includes: the second metal layer 13 of the pixel circuit, the second metal layer 23 of the driving circuit, the initial signal line Vinit, the multiplexing connection electrode 61 and the initial connection electrode 62 .
  • the second metal layer of the pixel circuit includes: the second plate PC2 of the pixel storage capacitor and the power connection line VL.
  • the second metal layer of the driving circuit includes: a first connection electrode 81, a second connection electrode 82, a first plate GC11 of the first shift storage capacitor, and a first plate GC21 of the second shift storage capacitor, as shown in FIG. 12A 12B and 12C,
  • FIG. 12A is a schematic diagram after forming the second metal layer
  • FIG. 12B is an enlarged schematic diagram after the pixel circuit forms the second metal layer
  • FIG. 12C is an enlarged schematic diagram after the driver circuit forms the second metal layer.
  • the initial connection electrode 62 is electrically connected to the initial signal line Vinit.
  • the multiplexing connection electrodes 61 are configured to connect data lines.
  • Forming the third insulating layer includes: depositing a third insulating film on the substrate on which the second metal layer is formed, and patterning the third insulating film through a patterning process to form the third insulating layer.
  • the third insulating layer is formed with a plurality of via holes.
  • the plurality of via holes include: a first via hole V1 in the pixel circuit, a second via hole V2 in the driving circuit, a third via hole V3 in the multiplexing circuit, and a fourth via hole V4 in the electrostatic discharge circuit.
  • FIGS. 13A, 13B and 13C The fifth via V5 exposing the gate line connection electrode, the sixth via V6 exposing the reset connection circuit, the via V7 exposing the multiplexing connection electrode, the via V8 exposing the initial connection electrode, and the multiplexing
  • the via hole V9 of the data line is shown in FIGS. 13A, 13B and 13C.
  • 13A is a schematic diagram after the third insulating layer is formed
  • FIG. 13B is an enlarged schematic diagram after the pixel circuit is formed with the third insulating layer
  • FIG. 13C is an enlarged schematic diagram after the driving circuit is formed with the third insulating layer.
  • the first via hole V1 in the pixel circuit includes: a first sub-via hole V1_1 opened on the first insulating layer, the second insulating layer and the third insulating layer To the fifth sub-via hole V1_5, the sixth sub-via hole V1_6 opened on the second insulating layer and the third insulating layer, and the seventh sub-via hole V1_7 to the ninth sub-via hole V1_9 opened on the third insulating layer.
  • the first sub-via V1_1 exposes the active layer PT11 of the first pixel transistor
  • the second sub-via V1_2 exposes the active layer PT21 of the second pixel transistor
  • the third sub-via V1_3 exposes the fourth pixel transistor
  • the active layer PT41 of the fourth sub-via V1_4 exposes the active layer PT61 of the sixth pixel transistor
  • the fifth sub-via V1_5 exposes the active layer PT51 of the fifth pixel transistor
  • the sixth sub-via V1_6 exposes the active layer PT51 of the fifth pixel transistor.
  • the first plate PC1 of the pixel storage capacitor PC the seventh sub-via V1_7 exposes the initial signal line Vinit, the eighth sub-via V1_8 exposes the power connection line VL, and the ninth sub-via V1_9 exposes the pixel storage capacitor PC.
  • the second via hole includes: the first sub-via hole V2_1 to the sixth sub-via hole opened on the first insulating layer, the second insulating layer and the third insulating layer
  • the first sub-via V2_1 exposes the active layers of the fourth shift transistor, the sixth shift transistor and the seventh shift transistor.
  • the second sub-via V2_2 exposes the active layer of the first shift transistor.
  • the third sub-via V2_3 exposes the active layer of the second shift transistor.
  • the fourth sub-via V2_4 exposes the active layer of the third shift transistor.
  • the fifth sub-via V2_5 exposes the active layer of the eighth shift transistor.
  • the sixth sub-via V2_6 exposes the active layer of the fifth shift transistor.
  • the seventh sub-via V2_7 exposes the gate electrode of the seventh shift transistor.
  • the eighth sub-via V2_8 exposes the gate electrodes of the first shift transistor and the third shift transistor.
  • the ninth sub-via V2_9 exposes the gate electrode of the second shift transistor.
  • the tenth sub-via V2_10 exposes the gate electrode of the eighth shift transistor.
  • the eleventh sub-via V2_11 exposes the second plate GC12 of the first shifted storage capacitor.
  • the twelfth sub-via V2_12 exposes the first connection electrode.
  • the thirteenth sub-via V2_13 exposes the first plate GC11 of the first shifted storage capacitor GC1.
  • the fourteenth sub-via V2_14 exposes the first plate of the second shift storage capacitor GC1.
  • the fifteenth sub-via V2_15 exposes the second connection electrode.
  • the third via hole includes: opening a plurality of sub-via holes on the first insulating layer, the second insulating layer and the third insulating layer exposing the active layers of the plurality of multiplexing transistors.
  • the fourth via hole includes opening a plurality of sub-via holes on the first insulating layer, the second insulating layer and the third insulating layer exposing the active layers of the plurality of release transistors.
  • Forming the third metal layer includes: depositing a third metal thin film on the substrate on which the third insulating layer is formed, and patterning the third metal thin film through a patterning process to form the third metal layer.
  • the third metal layer includes: the third metal layer 14 of the pixel circuit, the third metal layer 24 of the driving circuit, the third metal layer 34 of the multiplexing circuit, the third metal layer 44 of the electrostatic discharge circuit, and the third metal layer of the test circuit.
  • the third metal layer of the control circuit (not shown in the figure), the power supply connection line VL, the connection electrode 71, the data line Data, the first power supply line VDD, the first power supply line S_VDD, initial signal power supply line S_Vinit, multiplexing control line MUX, third power supply line VGH, fourth power supply line VGL, first clock signal line CK, second clock signal line CB, first clock signal line CK', second clock signal line CK The clock signal line CB', the test control line CT and the second power supply line S_VSS.
  • the third metal layer of the pixel circuit includes: the first electrode PT13 and the second electrode PT14 of the first pixel transistor to the first electrode PT63 and the second electrode PT64 of the sixth pixel transistor.
  • the third metal layer of the driving circuit includes: the first electrode GT13 and the second electrode GT14 of the first shift transistor to the first electrode GT83 and the second electrode GT84 of the eighth shift transistor.
  • the third metal layer of the multiplexing circuit includes: first electrodes and second electrodes of a plurality of shift transistors.
  • the third metal layer of the electrostatic discharge circuit includes: first electrodes and second electrodes of a plurality of discharge transistors.
  • the third metal layer of the test circuit includes: first electrodes and second electrodes of a plurality of test transistors.
  • the third metal layer of the control circuit includes: first and second electrodes of a plurality of control transistors, as shown in FIGS. 14A , 14B and 14C.
  • 14A is a schematic diagram after forming the third metal layer
  • FIG. 14B is an enlarged schematic diagram after the pixel circuit forms the third metal layer
  • FIG. 14C is an enlarged schematic diagram after the driving circuit forms the third metal layer.
  • the first electrode PT13 of the first pixel transistor is electrically connected to the active layer of the first pixel transistor PT1 through the first sub-via
  • the second The electrode PT14 is electrically connected to the initial signal line Vinit through the seventh sub-via hole
  • the first electrode PT23 of the second pixel transistor is electrically connected to the active layer of the second pixel transistor through the second sub-via hole
  • the first electrode of the second pixel transistor is electrically connected to the active layer of the second pixel transistor through the second sub-via hole.
  • the electrode PT23 is electrically connected to the first plate PC1 of the pixel storage capacitor PC through the sixth sub-via hole; the first electrode PT43 of the fourth pixel transistor is electrically connected to the active layer of the fourth pixel transistor through the third sub-via hole, and the first electrode PT43 of the fourth pixel transistor is electrically connected to the active layer of the fourth pixel transistor through the third sub-via hole.
  • the first electrode PT53 of the five-pixel transistor is electrically connected to the active layer of the fifth pixel transistor through the fifth sub-via hole, and the second electrode PT64 of the sixth pixel transistor is electrically connected to the active layer of the sixth pixel transistor through the sixth sub-via hole electrical connection.
  • the first power supply line VDD is integrally formed with the first electrode PT53 of the fifth pixel transistor
  • the connection electrode 71 is integrally formed with the second electrode PT64 of the sixth pixel transistor.
  • the first power line VDD is electrically connected to the power supply connection line VL through the eighth sub-via, and the first power line VDD is connected to the pixel storage capacitor PC through the ninth sub-via
  • the second plate PC2 is electrically connected.
  • part of the active layer is multiplexed into the second electrode PT24 of the second pixel transistor, the second electrode PT34 of the third pixel transistor, and the first electrode of the sixth pixel transistor PT63 is the same electrode, and part of the active layer is multiplexed into the second electrode PT24 of the second pixel transistor.
  • part of the active layer is multiplexed into the first electrode PT33 of the third pixel transistor, the second electrode PT44 of the fourth pixel transistor, and the second electrode of the fifth pixel transistor PT54 is the same electrode, and part of the active layer is multiplexed into the first electrode PT33 of the third pixel transistor.
  • the first electrode GT13 of the first shift transistor and the second electrode GT14 of the first shift transistor are connected to the first shift transistor through the second sub-via hole.
  • the source layer is electrically connected, and the first electrode GT13 of the first shift transistor is electrically connected to the second connection electrode through the fifteenth sub-via, and the second electrode GT14 of the first shift transistor is connected to the first through the seventh sub-via
  • the connection electrodes 81 are electrically connected.
  • the first electrode GT23 of the second shift transistor and the second electrode GT24 of the second shift transistor are electrically connected to the active layer of the second shift transistor through the third sub-via, and the first electrode of the second shift transistor is electrically connected to the active layer of the second shift transistor.
  • GT23 is electrically connected to the control electrode of the first shift transistor through the eighth sub-via hole
  • the second electrode GT24 of the second shift transistor is electrically connected to the control electrode of the first shift transistor through the eighth sub-via hole.
  • the first electrode GT33 of the third shift transistor and the second electrode GT34 of the third shift transistor are electrically connected to the active layer of the third shift transistor through the fourth sub-via
  • the first electrode GT33 of the third shift transistor is electrically connected to the active layer of the third shift transistor.
  • the control electrode of the eighth shift transistor is electrically connected through the tenth sub-via hole.
  • the first electrode GT43 of the fourth shift transistor and the second electrode GT44 of the fourth shift transistor are electrically connected to the active layer of the fourth shift transistor through the sixth via hole, and the first electrode GT43 of the fourth shift transistor is electrically connected to the active layer of the fourth shift transistor.
  • the first electrode plate GC11 of the first shift storage capacitor GC1 is electrically connected through the thirteenth via hole, and the second electrode GT44 of the fourth shift transistor is electrically connected to the first electrode plate GC11 of the second shift storage capacitor GC1 through the fourteenth through hole.
  • the plate GC21 is electrically connected.
  • the first electrode GT53 of the fifth shift transistor and the second electrode GT54 of the fifth shift transistor are electrically connected to the active layer of the fifth shift transistor through the sixth via hole, and the first electrode GT53 of the fifth shift transistor is electrically connected to the active layer of the fifth shift transistor.
  • the seventh sub-via is electrically connected to the control electrode of the seventh shift transistor.
  • the first electrode GT63 of the sixth shift transistor is electrically connected to the active layer of the sixth shift transistor through the first sub-via.
  • the second electrode GT74 of the seventh shift transistor is electrically connected to the active layer of the seventh shift transistor through the first sub-via.
  • the first electrode GT83 of the eighth shift transistor and the second electrode GT84 of the eighth shift transistor are electrically connected to the active layer of the eighth shift transistor through the fifth sub-via, and the first electrode of the eighth shift transistor is electrically connected to the active layer of the eighth shift transistor.
  • GT83 is electrically connected to the control electrode of the second shift transistor through the ninth sub-via; the second electrode GT84 of the eighth shift transistor is electrically connected to the second electrode of the second shift transistor through the fourteenth sub-via.
  • the first clock signal line CK is electrically connected to the control electrode of the first shift transistor through the eighth sub-via; the second clock signal line CB is electrically connected through the seventh sub-via The hole is electrically connected to the control electrode of the seventh shift transistor; the third power line VGH is electrically connected to the first connection electrode through the eleventh sub-via hole.
  • the second electrode GT14 of the first shift transistor and the seventh shift transistor GT74 are the same electrode, and the second electrode G24 of the second shift transistor and the third shift transistor GT74 are the same electrode.
  • the second pole G34 of the bit transistor is the same electrode
  • the first pole GT33 of the third shift transistor is integrally formed with the fourth power supply line VGL
  • the first pole GT43 of the fourth shift transistor and the first pole of the sixth shift transistor GT63 is the same electrode
  • part of the active layer is multiplexed into the first pole GT63 of the sixth shift transistor and the first pole GT73 of the seventh shift transistor
  • the first pole GT63 of the sixth shift transistor and the seventh shift transistor The first electrode GT73 of the transistor is the same electrode.
  • Forming the flat layer includes: depositing a fourth insulating film on the substrate on which the third metal layer is formed, and patterning the fourth insulating film through a patterning process to form a fourth insulating layer.
  • a flat film is coated on the substrate on which the fourth insulating layer is formed, and a first flat layer is formed by masking, exposing and developing the flat film.
  • Forming the transparent conductive layer includes: depositing a transparent conductive film on the substrate formed with the flat layer, and patterning the transparent conductive film through a patterning process to form the transparent conductive layer.
  • the transparent conductive layer includes a first electrode formed in each light emitting element, and the first electrode is connected to the connection electrode 71 .
  • a pixel definition layer comprising: coating a pixel definition film on a substrate forming a transparent conductive layer, and forming a pixel definition layer (Pixel Define Layer) through a mask, exposure and development process, and the pixel definition layer is formed on each light-emitting In the element, the pixel definition layer in each light-emitting element is formed with an opening region exposing the first electrode.
  • a pixel definition layer Panel Define Layer
  • Forming the organic light-emitting layer includes: forming an organic light-emitting layer in the opening area of the formed pixel definition layer and on the pixel definition layer, and the organic light-emitting layer is electrically connected to the first electrode.
  • Forming the second electrode includes: coating a conductive film on the substrate on which the organic light-emitting layer is formed, and patterning the conductive film through a patterning process to form the second electrode.
  • the second electrode covers the organic light-emitting layer in each light-emitting element.
  • the second electrode is electrically connected to the organic light-emitting layer.
  • the flat layer may be an organic material
  • the transparent conductive film may be indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the pixel definition layer may employ polyimide, acrylic, or polyethylene terephthalate.
  • the second electrode may employ any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or may Alloys made with any one or more of the above metals.
  • the active layer may be a metal oxide layer.
  • the metal oxide layer may employ oxides containing indium and tin, oxides containing tungsten and indium, oxides containing tungsten and indium and zinc, oxides containing titanium and indium, oxides containing titanium and indium and tin, Oxides containing indium and zinc, oxides containing silicon and indium and tin, or oxides containing indium or gallium and zinc.
  • the metal oxide layer may be a single layer, or it may be a double layer, or it may be multiple layers.
  • Embodiments of the present disclosure also provide a display device, including: a display substrate.
  • the display device may be a display, a TV, a mobile phone, a tablet computer, a navigator, a digital photo frame, a wearable display product, or a product or component with any display function.
  • the display substrate is the display substrate provided in any one of the foregoing embodiments, and the implementation principle and effect are similar, and details are not described herein again.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)

Abstract

一种显示基板和显示装置，显示基板包括：显示区和围绕显示区的非显示区；所述显示区包括至少一段弧形显示边界；显示区包括：多个子像素，多条沿第一方向延伸的数据线以及多条沿第二方向延伸的栅线；每个子像素包括：像素电路和与像素电路连接的发光元件，每个子像素中的像素电路分别与栅线和数据线电连接；靠近弧形显示边界的至少部分子像素呈阶梯状排布；非显示区包括：多个级联的，且向多条栅线提供驱动信号的驱动电路；靠近弧形显示边界的至少部分驱动电路呈阶梯状排布；其中，第一方向与第二方向相交。

Description

显示基板和显示装置 技术领域
本公开实施例涉及但不限于显示领域，特别涉及一种显示基板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)是当今显示器研究领域的热点之一。与液晶显示器(Liquid Crystal Display，简称LCD)相比，有机发光二极管OLED具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点，已广泛应用于手机、平板电脑和数码相机等显示领域中。
随着显示技术的不断发展，大“屏占比(即实际显示区的面积在显示侧总面积中的占比)”已成为显示装置追求的外观特性之一。尤其是对与佩戴式显示装置(如智能手表)，基于便携和视角效果的方面的考虑，极致窄边框甚至全屏显示成为发展的重要趋势。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开还提供了一种显示基板，包括：显示区和围绕所述显示区的非显示区，所述显示区包括至少一段弧形显示边界；
所述显示区包括：多个子像素，多条沿第一方向延伸的数据线以及多条沿第二方向延伸的栅线；每个子像素包括：像素电路和与所述像素电路连接的发光元件，每个子像素中的像素电路分别与栅线和数据线电连接；靠近所述弧形显示边界的至少部分子像素呈阶梯状排布；
所述非显示区包括：多个级联的，且向多条栅线提供驱动信号的驱动电路；靠近所述弧形显示边界的至少部分驱动电路呈阶梯状排布；
其中，所述第一方向与所述第二方向相交。
在一些可能的实现方式中，所述显示区还包括：多条沿第一方向延伸的第一电源线和多条沿第二方向延伸的初始信号线，每个子像素中的像素电路分别与第一电源线和初始信号线电连接；
所述非显示区还包括：第一电源供电线和初始信号供电线；所述第一电源供电线和所述初始信号供电线为环状；
所述第一电源供电线位于多个驱动电路靠近显示区的一侧，且与每个像素电路连接的第一电源线电连接；靠近所述弧形显示边界的第一电源供电线呈阶梯状；
所述初始信号供电线位于多个驱动电路和所述第一电源供电线之间，且与每个像素电路连接的初始信号线电连接；靠近所述弧形显示边界的初始信号供电线呈阶梯状。
在一些可能的实现方式中，所述第一电源供电线的线宽大于所述初始信号供电线的线宽。
在一些可能的实现方式中，所述显示区还包括：第二电源线，每个子像素中的发光元件与第二电源线电连接；
所述非显示区还包括：第二电源供电线；所述第二电源供电线为环状；
所述第二电源供电线位于多个驱动电路远离显示区的一侧，且与每个发光元件连接的第二电源线电连接；靠近所述弧形显示边界的第二电源供电线靠近显示区的表面呈阶梯状，靠近所述弧形显示边界的第二电源供电线远离显示区的表面呈圆弧状。
在一些可能的实现方式中，所述第二电源供电线的线宽大于所述第一电源供电线的线宽。
在一些可能的实现方式中，所述显示区还包括：多条沿第二方向延伸的发光控制线和复位控制线；每个子像素中的像素电路与所述发光控制线和所述复位控制线电连接；
所述非显示区包括：多个级联的，且向多条发光控制线提供控制信号的控制电路；靠近所述弧形显示边界的至少部分控制电路呈阶梯状排布；
所述多个驱动电路和多个控制电路分别位于所述显示区的相对设置的第 一侧和第二侧。
在一些可能的实现方式中，所述非显示区还包括：多个多路复用电路，所述多路复用电路位于所述多个驱动电路和初始信号供电线之间，且与多条数据线电连接，配置为向连接的数据线提供数据信号；
靠近所述弧形显示边界的至少部分多路复用电路呈阶梯状排布。
在一些可能的实现方式中，所述非显示区还包括：多条复用控制线和多条所述复用数据线；每个多路复用电路分别与多条复用控制线和一条复用数据线电连接；
多条复用控制线位于多个驱动电路和多个多路复用电路之间；靠近所述弧形显示边界的多条复用控制线呈阶梯状。
在一些可能的实现方式中，所述非显示区还包括：多个静电释放电路，每个静电释放电路与一条信号线连接，且配置为释放所连接的信号线中的静电；所述信号线包括：复用数据线；
多个静电释放电路位于所述多个驱动电路和第二电源供电线之间；靠近所述弧形显示边界的至少部分静电释放电路呈阶梯状排布。
在一些可能的实现方式中，所述非显示区还包括：测试控制线和多个测试电路；所述测试电路分别与所述测试控制线和数据线电连接，且配置为向数据线提供测试信号；
所述多个测试电路位于所述显示区的第三侧，所述第三侧不同于第一侧和第二侧；
所述测试控制线位于第二电源供电线和多个静电释放电路之间；靠近所述弧形显示边界的测试控制线呈阶梯状。
在一些可能的实现方式中，所述非显示区还包括：第三电源线和第四电源线；每个驱动电路分别与第三电源线和第四电源线电连接；所述第三电源线和所述第四电源线为环状；
所述第三电源线位于静电释放电路和多个驱动电路之间；靠近所述弧形显示边界的第三电源线呈阶梯状；
所述第四电源线位于所述第三电源线和多个驱动电路之间，靠近所述弧 形显示边界的第四电源线呈阶梯状。
在一些可能的实现方式中，所述非显示区还包括：第一时钟信号线、第二时钟信号线、信号输入线和信号输出线，每个驱动电路分别与第一时钟信号线、第二时钟信号线、信号输入线和信号输出线电连接；
所述第一时钟信号线位于所述第三电源线和多个驱动电路之间，靠近所述弧形显示边界的第一时钟信号线呈阶梯状；
所述第二时钟信号线位于所述第三电源线和所述第一时钟信号线之间；靠近所述弧形显示边界的第二时钟信号线呈阶梯状；
所述信号输入线和所述信号输出线位于所述驱动电路靠近显示区的一侧。
在一些可能的实现方式中，所述非显示区还包括：多个复用连接电极和多个初始连接电极；
所述复用连接电极分别与多路复用电路和数据线电连接，
所述初始连接电极分别与初始信号线和初始信号供电线电连接；
其中，所述多个复用连接电极和所述多个初始连接电极同层设置，所述初始连接电极与所述初始信号线同层设置，所述复用连接电极与所述数据线异层设置。
在一些可能的实现方式中，所述非显示区还包括：栅线连接电极和复位连接电极；
所述栅线连接电极分别与所述栅线和所述信号输出线电连接；
所述复位连接电极分别与所述复位信号线和所述信号输入线电连接；
其中，所述栅线连接电极与所述复位连接电极同层设置，且与所述栅线同层设置。
在一些可能的实现方式中，所述非显示区还包括：封装电极；
所述封装电极位于所述第二电源供电线远离所述显示区的一侧；所述封装电极与所述第二电源供电线异层设置，且与所述第二电源供电线电连接；
所述封装电极开设有多个过孔。
在一些可能的实现方式中，所述显示基板还包括：位于非显示区的多路 复用电路、静电释放电路、测试电路和控制电路，所述像素电路包括：多个像素晶体管、所述驱动电路包括：多个移位晶体管、所述多路复用电路包括：多个复用晶体管、所述静电释放电路包括：多个释放晶体管、所述测试电路包括：多个测试晶体管、所述控制电路包括：多个控制晶体管；
所述显示基板包括：基底以及依次叠设在所述基底上的有源层、第一绝缘层、第一金属层、第二绝缘层、第二金属层、第三绝缘层和第三金属层；
所述有源层包括：多个像素晶体管的有源层、多个移位晶体管的有源层、多个复用晶体管的有源层、多个释放晶体管的有源层、多个测试晶体管的有源层和多个控制晶体管的有源层；所述第一金属层包括：多个像素晶体管的控制极、多个移位晶体管的控制极、多个复用晶体管的控制极、多个测试晶体管的控制极、多个释放晶体管的控制极、多个控制晶体管的控制极、复用数据线、发光控制线、栅线、复位信号线、栅线连接电极、复位连接电极和封装电极；所述第二金属层包括：初始信号线、复用连接电极和初始连接电极；所述第三金属层包括：多个像素晶体管的第一极和第二极、多个移位晶体管的第一极和第二极、多个复用晶体管的第一极和第二极、多个测试晶体管的第一极和第二极、多个释放晶体管的第一极和第二极、多个控制晶体管的第一极和第二极、数据线、第一电源线、第一电源供电线、初始信号供电线、复用控制线、第三电源线、第四电源线、第一时钟信号线、第二时钟信号线、测试控制线和第二电源供电线。
在一些可能的实现方式中，所述第三绝缘层上设置有暴露出复用连接电极的过孔和暴露出初始连接电极的过孔；所述第二绝缘层和所述第三绝缘层上设置有暴露出栅线连接电极的过孔和暴露出复位连接电极的过孔；
所述数据线通过暴露出复用连接电极的过孔与复用连接电极电连接，所述初始信号供电线通过暴露出初始连接电极的过孔与所述初始信号线电连接；
所述信号输出线通过暴露出栅线连接电极的过孔与栅线连接电极电连接，所述信号输入线通过暴露出复位连接电极的过孔与复位连接电极电连接。
在一些可能的实现方式中，所述第二电源供电线在基底上的正投影与所述封装电极在基底上的正投影至少部分重叠；
所述第二绝缘层和所述第三绝缘层上设置有暴露出封装电极的过孔；所 述第二电源供电线通过暴露出封装电极的过孔与封装电极电连接；
所述第二绝缘层和所述第三绝缘层上还会设置有多个过孔阵列；设置在封装电极上的过孔在基底上的正投影覆盖所述过孔阵列在基底上的正投影。
在一些可能的实现方式中，沿第二方向排布的多个子像素称为一行子像素，每行子像素沿第一方向的长度为74微米至75微米；
靠近所述弧形显示边界，且呈阶梯状的信号线中的每一级阶梯沿第一方向的长度为每行子像素沿第一方向的长度的整数倍；
所述信号线包括：第一电源供电线、初始信号供电线、复用控制线、第三电源线、第四电源线、第一时钟信号线、第二时钟信号线、测试控制线和第二电源供电线。
第二方面，本公开还提供了一种显示装置，包括：上述显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1A为本公开实施例提供的显示基板的结构示意图；
图1B为子像素的结构示意图；
图2为一种示例性实施例提供的显示基板中区域A1的版图；
图3为一种示例性实施例提供的封装电极的结构示意图；
图4为一种示例性实施例提供的显示基板的区域A2的局部示意图；
图5A为一种示例性实施例提供的像素电路的等效电路图；
图5B为一种示例性实施例提供的驱动电路的等效电路图；
图5C为图5B提供的驱动电路的时序图；
图5D为一种示例性实施例提供的控制电路的等效电路图；
图5E为图5D提供的控制电路的时序图；
图5F为一种示例性实施例提供的多路复用电路的等效电路图；
图5G为一种示例性实施例提供的测试电路的等效电路图；
图5H为一种示例性实施例提供的静电释放电路的等效电路图；
图6为一种示例性实施例提供的显示基板的有源层的膜层示意图；
图7为一种示例性实施例提供的显示基板的第一金属层的膜层示意图；
图8为一种示例性实施例提供的显示基板的第二金属层的膜层示意图；
图9为一种示例性实施例提供的显示基板的第三金属层的膜层示意图；
图10A为像素电路形成有源层后的示意图；
图10B为驱动电路形成有源层后的示意图；
图11A为形成第一金属层后的示意图；
图11B为像素电路形成第一金属层后的放大示意图；
图11C为驱动电路形成第一金属层后的放大示意图；
图12A为形成第二金属层后的示意图；
图12B为像素电路形成第二金属层后的放大示意图；
图12C为驱动电路形成第二金属层后的放大示意图；
图13A为形成第三绝缘层后的示意图；
图13B为像素电路形成第三绝缘层后的放大示意图；
图13C为驱动电路形成第三绝缘层后的放大示意图；
图14A为形成第三金属层后的示意图；
图14B为像素电路形成第三金属层后的放大示意图；
图14C为驱动电路形成第三金属层后的放大示意图。
详述
本公开描述了多个实施例，但是该描述是示例性的，而不是限制性的，并且对于本领域的普通技术人员来说，在本公开所描述的实施例包含的范围 内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在详述中进行了讨论，但是所公开的特征的许多其它组合方式也是可能的。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
本公开包括并设想了与本领域普通技术人员已知的特征和元件的组合。本公开已经公开的实施例、特征和元件也可以与任何常规特征或元件组合，以形成由权利要求限定的技术方案。任何实施例的任何特征或元件也可以与来自其它技术方案的特征或元件组合，以形成另一个由权利要求限定的技术方案。因此，应当理解，在本公开中示出和/或讨论的任何特征可以单独地或以任何适当的组合来实现。因此，除了根据所附权利要求及其等同替换所做的限制以外，实施例不受其它限制。此外，可以在所附权利要求的保护范围内进行各种修改和改变。
除非另外定义，本公开中使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述的对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本说明书中，沟道区域是指电流主要流过的区域。第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本 说明书中，“源电极”和“漏电极”可以互相调换。此外，晶体管包括：P型晶体管或N型晶体管两种，其中，P型晶体管在栅极为低电平导通，在栅极为高电平时截止，N型晶体管在栅极为高电平时导通，在栅极为低电平时截止。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
在一种显示装置中，部分信号线和电路的布局方式使得显示装置无法实现窄边框。
图1A为本公开实施例提供的显示基板的结构示意图，图1B为子像素的结构示意图。如图1A和1B所示，本公开实施例提供的显示基板包括：显示区AA和围绕显示区的非显示区AA’。显示区包括至少一段弧形显示边界。
显示区AA包括：多个子像素1，多条沿第一方向延伸的数据线以及多条沿第二方向延伸的栅线(图中未示出)。每个子像素包括：像素电路10和与像素电路10连接的发光元件100，每个子像素中的像素电路分别与栅线和数据线电连接；靠近弧形显示边界的至少部分子像素呈阶梯状排布。
非显示区AA’包括：多个级联的，且向多条栅线提供驱动信号的驱动电路20。靠近弧形显示边界的至少部分驱动电路呈阶梯状排布。其中，第一方向与第二方向相交。
在一种示例性实施例中，显示区的形状可以为圆角多边形，或者可以为圆形。当显示区的形状为圆角多边形时，显示区还可以包括：直线显示边界。图1是以显示区为圆角四边形为例进行说明的。
在一种示例性实施例中，当显示区的形状为圆角多边形时，靠近直线显示边界的多个驱动电路沿直线显示边界排布。
在一种示例性实施例中，第一方向与第二方向相交指的是第一方向与第二方向之间的夹角约为70度至90度。
在一种示例性实施例中，发光元件可以为有机发光二极管OLED，此时，显示基板为有机发光二极管OLED显示基板。
在一种示例性实施例中，子像素1的表现形式是多样的，可以实现独立的显示即可。不同的子像素1可具有不同的颜色，从而通过不同子像素1的混光可实现彩色显示。当要实现彩色显示时，可以是多个排在一起的不同颜色的子像素1组成一个“像素(或像素单元)”，即这些子像素1发出的光混在一起成为视觉上的一个“点”；例如，可以是红色、绿色、蓝色三种颜色的三个子像素1组成一个像素。
在一种示例性实施例中，数据线与栅线的每个交叉处可限定出一个子像素1，而通过对栅线与数据线的共同控制，可使二者交叉处的子像素1进行显示。
在一种示例性实施例中，显示区中的子像素可排成阵列，即子像素可排成多行、多列，每行子像素连接一条栅极线，每列子像素连接一条数据线。应当理解，子像素不一定排成阵列，每条数据线、栅极线也不一定连接同列、同行的子像素。
在一种示例性实施例中，驱动电路的数量与子像素的行数相同。
在一种示例性实施例中，靠近弧形显示边界的至少部分驱动电路按照靠近弧形显示边界的至少部分子像素呈阶梯状排布方式进行阶梯状排布，即呈阶梯状排布的靠近弧形显示边界的至少部分驱动电路与呈阶梯状排布的靠近弧形显示边界的至少部分子像素沿第二方向之间的距离小于阈值距离。
在一种示例性实施例中，阶梯状分布可以为90度阶梯，或者可以为其他 角度的阶梯，根据显示基板的布局确定。
在一种示例性实施例中，靠近弧形显示边界的至少部分驱动电路可以呈波浪状排布。
本公开实施例提供的一种显示基板，包括：显示区和围绕显示区的非显示区，显示区包括至少一段弧形显示边界；显示区包括：多个子像素，多条沿第一方向延伸的数据线以及多条沿第二方向延伸的栅线；每个子像素包括：像素电路和与像素电路连接的发光元件，每个子像素中的像素电路分别与栅线和数据线电连接；靠近弧形显示边界的至少部分子像素呈阶梯状排布；非显示区包括：多个级联的，且向多条栅线提供驱动信号的驱动电路；靠近弧形显示边界的至少部分驱动电路呈阶梯状排布；其中，第一方向与第二方向相交。本公开通过靠近弧形显示边界的至少部分驱动电路呈阶梯状排布可以减少显示装置所占用的空间，可以实现显示装置的窄边框。
图2为一种示例性实施例提供的显示基板中区域A1的版图。如图1和2所示，在一种示例性实施例中，显示区还可以包括：多条沿第一方向延伸的第一电源线VDD和多条沿第二方向延伸的初始信号线Vinit。每个子像素中的像素电路分别与第一电源线VDD和初始信号线Vinit电连接。非显示区还可以包括：第一电源供电线S_VDD和初始信号供电线S_Vinit。
在一种示例性实施例中，第一电源供电线S_VDD和初始信号供电线S_Vinit为环状。
第一电源供电线S_VDD位于多个驱动电路靠近显示区的一侧，且与每个像素电路连接的第一电源线VDD电连接。初始信号供电线S_Vinit位于多个驱动电路和第一电源供电线之间，且与每个像素电路连接的初始信号线电连接。
在一种示例性实施例中，靠近弧形显示边界的第一电源供电线呈阶梯状。第一电源供电线的设置方式可以实现显示装置的窄边框。
在一种示例性实施例中，当显示区的形状为圆角多边形时，靠近直线显示边界的第一电源供电线呈直线状。
在一种示例性实施例中，靠近弧形显示边界的初始信号供电线呈阶梯状。 初始信号供电线的设置方式可以实现显示装置的窄边框。
在一种示例性实施例中，当显示区的形状为圆角多边形时，靠近直线显示边界的初始信号供电线呈直线状。
在一种示例性实施例中，第一电源供电线的线宽大于初始信号供电线的线宽。
在一种示例性实施例中，显示区还包括：第二电源线(图中未示出)，每个子像素中的发光元件与第二电源线电连接。非显示区还包括：第二电源供电线S_VSS；第二电源供电线为环状。第二电源供电线位于多个驱动电路远离显示区的一侧，且与每个发光元件连接的第二电源线电连接。
靠近弧形显示边界的第二电源供电线靠近显示区的表面呈阶梯状，靠近弧形显示边界的第二电源供电线远离显示区的表面呈圆弧状。第二电源供电线的设置方式不仅可以实现显示装置的窄边框，还可以减少第二电源供电线的电阻。
在一种示例性实施例中，当显示区的形状为圆角多边形时，靠近直线显示边界的第二电源供电线呈直线状。
在一种示例性实施例中，第二电源供电线S_VSS的线宽大于第一电源供电线S_VDD的线宽。
在一种示例性实施例中，如图2所示，显示区还包括：多条沿第二方向延伸的发光控制线EM和复位控制线Reset；每个子像素中的像素电路与发光控制线和复位控制线电连接。
非显示区包括：多个级联的，且向多条发光控制线提供控制信号的控制电路；靠近弧形显示边界的至少部分控制电路呈阶梯状排布。
在一种示例性实施例中，当显示区的形状为圆角多边形时，靠近直线显示边界的多个控制电路沿直线显示边界排布。
在一种示例性实施例中，多个驱动电路和多个控制电路分别位于显示区的相对设置的第一侧C1和第二侧C2。
在一种示例性实施例中，非显示区还包括：多个多路复用电路30，多路复用电路30位于多个驱动电路和初始信号供电线S_Vinit之间，且与多条数 据线电连接，配置为向连接的数据线提供数据信号。
靠近弧形显示边界的至少部分多路复用电路30呈阶梯状排布。多个多路复用电路的设置方式可以实现显示装置的窄边框。
在一种示例性实施例中，当显示区的形状为圆角多边形时，靠近直线显示边界的多个多路复用电路沿直线显示边界排布。
在一种示例性实施例中，如图2所示，非显示区还包括：多条复用控制线MUX和多条复用数据线53；每个多路复用电路30分别与多条复用控制线MUX和一条复用数据线53电连接；
多条复用控制线MUX位于多个驱动电路和多个多路复用电路之间；靠近弧形显示边界的多条复用控制线呈阶梯状。
在一种示例性实施例中，当显示区的形状为圆角多边形时，靠近直线显示边界的多条复用控制线呈直线状。
在一种示例性实施例中，如图2所示，非显示区还包括：多个静电释放电路40。每个静电释放电路40与一条信号线连接，且配置为释放其连接的信号线中的静电；信号线包括：复用数据线。
多个静电释放电路40位于多个驱动电路20和第二电源供电线S_VSS之间。靠近弧形显示边界的至少部分静电释放电路呈阶梯状排布。
在一种示例性实施例中，当显示区的形状为圆角多边形时，靠近直线显示边界的多个静电释放电路沿直线显示边界排布。
在一种示例性实施例中，如图2所示，非显示区还包括：多个测试电路(图中未示出)和测试控制线CT。测试电路分别与测试控制线和数据线电连接，且配置为向数据线提供测试信号。
在一种示例性实施例中，如图1所示，多个测试电路位于显示区的第三侧C3，第三侧C3不同于第一侧C1和第二侧C2。
如图2所示，测试控制线CT位于第二电源供电线S_VSS和多个静电释放电路40之间。靠近弧形显示边界的测试控制线呈阶梯状。
在一种示例性实施例中，当显示区的形状为圆角多边形时，靠近直线显示边界的测试控制线呈直线状。
在一种示例性实施例中，如图2所示，非显示区还包括：第三电源线VGH和第四电源线VGL。每个驱动电路分别与第三电源线和第四电源线电连接；第三电源线和第四电源线为环状。
在一种示例性实施例中，第三电源线VGH位于静电释放电路40和多个驱动电路20之间。靠近弧形显示边界的第三电源线VGH呈阶梯状。
在一种示例性实施例中，当显示区的形状为圆角多边形时，靠近直线显示边界的第三电源线VGH呈直线状。
在一种示例性实施例中，第四电源线VGL位于第一时钟信号线CK和多个驱动电路20之间。靠近弧形显示边界的第四电源线VGL呈阶梯状。
在一种示例性实施例中，当显示区的形状为圆角多边形时，靠近直线显示边界的第四电源线VGL呈直线状。
在一种示例性实施例中，如图2所示，非显示区还包括：第一时钟信号线CK、第二时钟信号线CB、信号输入线和信号输出线(图中未示出)，每个驱动电路分别与第一时钟信号线CK、第二时钟信号线CB、信号输入线和信号输出线电连接。
在一种示例性实施例中，第一时钟信号线CK位于第三电源线VGH和多个驱动电路20之间，靠近弧形显示边界的第一时钟信号线CK呈阶梯状。
在一种示例性实施例中，当显示区的形状为圆角多边形时，靠近直线显示边界的第一时钟信号线呈直线状。
在一种示例性实施例中，第二时钟信号线CB位于第三电源线VGH和第一时钟信号线CK之间；靠近弧形显示边界的第二时钟信号线CB呈阶梯状。
在一种示例性实施例中，当显示区的形状为圆角多边形时，靠近直线显示边界的第二时钟信号线CB呈直线状。
在一种示例性实施例中，信号输入线和信号输出线位于驱动电路靠近显示区的一侧。
在一种示例性实施例中，如图2所示，非显示区还包括：栅极测试线GT。
栅极测试线GT位于第三电源线VGH和第二时钟信号线CB之间，且与最后一级驱动电路电连接。
图3为一种示例性实施例提供的封装电极的结构示意图，图4为一种示例性实施例提供的显示基板的区域A2的局部示意图。如图3和图4所示，非显示区还包括：封装电极50。封装电极50位于第二电源供电线远离显示区的一侧；封装电极50与第二电源供电线S_VSS异层设置，且与第二电源供电线S_VSS电连接。
在一种示例性实施例中，封装电极开设有多个过孔V51。
图5A为一种示例性实施例提供的像素电路的等效电路图。如图5A所示，在一种示例性实施例中，像素电路分别与第一电源线VDD、数据线Data、栅线Gate、复位信号线Reset、初始信号线Vinit、发光控制线EM和发光元件连接；发光元件与第二电源线VSS连接。像素电路包括：第一像素晶体管PT1至第六像素晶体管PT6以及像素存储电容PC。其中，像素存储电容PC包括：第一极板PC1和第二极板PC2。
第一像素晶体管PT1的控制极与复位信号线Reset电连接，第一像素晶体管PT1的第一极与第一节点N1电连接，第一像素晶体管PT1的第二极与初始信号线Vinit电连接。第二像素晶体管PT2的控制极与栅线Gate电连接，第二像素晶体管PT2的第一极与第一节点N1电连接，第二像素晶体管PT2的第二极与第二节点N2电连接。第三像素晶体管PT3的控制极与第一节点N1电连接，第三像素晶体管PT3的第一极与第三节点N3电连接，第三像素晶体管PT3的第二极与第二节点N2电连接。第四像素晶体管PT4的控制极与栅线Gate电连接，第四像素晶体管PT4的第一极与数据线Data电连接，第四像素晶体管PT4的第二极与第三节点N3电连接。第五像素晶体管PT5的控制极与发光控制线EM电连接，第五像素晶体管PT5的第一极与第一电源线VDD电连接，第五像素晶体管PT5的第二极与第三节点N3电连接。第六像素晶体管PT6的控制极与发光控制线EM电连接，第六像素晶体管PT6的第一极与第二节点N2电连接，第六像素晶体管PT6的第二极与发光元件电连接。像素存储电容PC的第一极板PC1与第一节点N1电连接，像素存储电容容PC的第二极板PC2与第一电源线VDD电连接。
在一种示例性实施例中，像素电路可以为7T1C结构(即包括7个晶体管和1个电容)。
在一种示例性实施例中，第一电源线VDD、数据线Data、栅线Gate、复位信号线Reset、初始信号线Vinit和发光控制线EM位于显示区。
在一种示例性实施例中，第一电源线VDD、数据线Data沿第二方向延伸，且同层设置。栅线Gate、复位信号线Reset、发光控制线EM沿第一方向延伸，且同层设置。初始信号线Vinit沿第一方向延伸。
在一种示例性实施例中，初始信号线Vinit位于复位信号线Reset远离栅线Gate的一侧；发光控制线EM位于栅线Gate远离复位信号线Reset的一侧。
在一种示例性实施例中，第一电源线VDD配置为持续提供高电平信号，第二电源线VSS配置为持续提供低电平信号。
图5B为一种示例性实施例提供的驱动电路的等效电路图，图5C为图5B提供的驱动电路的时序图。如图5B和图5C所示，在一种示例性实施例中，驱动电路分别与信号输入线INPUT、第一时钟信号线CK、第二时钟信号线CB、第三电源线VGH、第四电源线VGL和信号输入线OUT电连接。
在一种示例性实施例中，驱动电路可以为一个栅极移位寄存器，而多个栅极移位寄存器级联，从而多个栅极移位寄存器可分别向多条栅线提供驱动信号。
如图5B所示，驱动电路包括：第一移位晶体管GT1至第八移位晶体管GT8、第一移位存储电容GC1和第二移位存储电容GC2。
第一移位晶体管GT1的控制极与第一时钟信号线CK电连接，第一移位晶体管GT1的第一极与信号输入线INPUT电连接，第一移位晶体管GT1的第二极与第一节点G1电连接；第二移位晶体管GT2的控制极与第一节点G1电连接，第二移位晶体管GT2的第一极与第一时钟信号线CK电连接，第二移位晶体管GT2的第二极与第二节点G2电连接；第三移位晶体管GT3的控制极与第一时钟信号线CK电连接，第三移位晶体管GT3的第一极与第四电源线VGL电连接，第三移位晶体管GT3的第二极与第二节点G2电连接；第四移位晶体管GT4的控制极与第二节点G2电连接，第四移位晶体管GT4的第一极与第三电源线VGH电连接，第四移位晶体管GT4的第二极与信号输出线OUT电连接；第五移位晶体管GT5的控制极与第三节点G3电连接，第五移位晶体管GT5的第一极与第二时钟信号线CB电连接，第五移 位晶体管GT5的第二极与信号输出线OUT电连接；第六移位晶体管GT6的控制极与第二节点G2电连接，第六移位晶体管GT6的第一极与第三电源线VGH电连接，第六移位晶体管GT6的第二极与第七移位晶体管GT7的第一极电连接；第七移位晶体管GT7的控制极与第二时钟信号线CB电连接，第七移位晶体管GT7的第二极与第一节点G1电连接；第八移位晶体管GT8的控制极与第四电源端VGL电连接，第八移位晶体管GT8的第一极与第一节点G1电连接，第八移位晶体管GT8的第二极与第三节点G3电连接；第一移位存储电容GC1的第一极板GC11与第三电源线VGH电连接，第一移位存储电容GC1的第二极板GC12与第二节点GC12电连接；第二移位存储电容GC2的第一极板GC21与信号输出线OUT电连接，第二移位存储电容GC2的第二极板GC22与第三节点G3电连接。
在一种示例性实施例中，第三电源线VGH持续提供高电平信号，第四电源线VGL持续提供低电平信号。
在一种示例性实施例中，第一移位晶体管GT1至第八移位晶体管GT8可以为P型晶体管或者可以为N型晶体管。
以第一移位晶体管GT1至第八移位晶体管GT8为P型晶体管为例，如图5C所示，一种示例性实施例提供的驱动电路的工作过程包括以下阶段：
在输入阶段t1，第一时钟信号线CK的信号为低电平，第二时钟信号线CB的信号为高电平，信号输入端INPUT的信号为低电平。由于第一时钟信号线CK的信号为低电平，第一移位晶体管GT1导通，信号输入端INPUT的信号经由第一移位晶体管GT1传输至第一节点G1。由于第八移位晶体管GT8的信号接收第四电源端VGL的低电平信号，从而第八移位晶体管GT8处于开启状态。第三节点G3的电平可以控制第五移位晶体管GT5导通，第二时钟信号线CB的信号经由第五移位晶体管GT5传输至信号输出线OUT，即在输入阶段t1，信号输出线OUT为高电平的第二时钟信号线CB的信号。另外，由于第一时钟信号线CK的信号为低电平，第三移位晶体管GT3导通，第四电源线VGL的低电平信号经由第三移位晶体管GT3传输至第二节点G2。此时，第四移位晶体管GT4和第六移位晶体管GT6均导通。由于第二时钟信号线CB的信号为高电平，第七移位晶体管GT7截止。
在输出阶段t2，第一时钟信号线CK的信号为高电平，第二时钟信号线CB的信号为低电平，信号输入端INPUT的信号为高电平。第五移位晶体管GT5导通，第二时钟信号线CB的信号经由第五移位晶体管GT5作为信号输出端OUT的信号。在输出阶段t2，第二移位存储电容GC2的连接输出端OUT的一端的电平变为第四电源线VGL的信号，由于第二移位存储电容GC2的自举作用，第八移位晶体管GT8截止，第五移位晶体管GT5可以更好地打开，信号输出端OUT的信号为低电平。另外，第一时钟信号线CK的信号为高电平，从而第一移位晶体管GT1和第三移位晶体管GT3均截止。第二移位晶体管GT2导通，第一时钟信号线CK的高电平经由第二移位晶体管GT2传输至第二节点G2，由此，第四移位晶体管GT4和第六移位晶体管GT6均截止。由于第二时钟信号线CB的信号为低电平，第七移位晶体管GT7导通。
在缓冲阶段t3，第一时钟信号线CK和第二栅极时钟信号CB的信号均为高电平，信号输入端INPUT的信号为高电平，第五移位晶体管GT5导通，第二栅极时钟信号CB经由第五移位晶体管GT5作为栅极输出信号GOUT，此时，栅极输出信号GOUT为高电平的第二栅极时钟信号CB，即VGH。由于第二栅极电容C2的自举作用，第一栅极节点N1的电平变为VGL-VthN1。另外，第一时钟信号线CK的信号为高电平，从而第一移位晶体管GT1和第三移位晶体管GT3均截止，第八移位晶体管GT8导通，第二移位晶体管GT2导通，第一时钟信号线CK的高电平信号经由第二移位晶体管GT2传输至第二节点G2，由此，第四移位晶体管GT4和第六移位晶体管GT6均截止。由于第二时钟信号线CB的信号为高电平，第七移位晶体管GT7截止。
在稳定阶段t4的第一子阶段t41中，第一时钟信号线CK的信号为低电平，第二时钟信号CB的信号为高电平，信号输入端INPUT的信号为高电平。由于第一时钟信号线CK的信号为低电平，第一移位晶体管GT1导通，信号输入端INPUT的信号经由第一移位晶体管GT1传输至第一节点G1，第二移位晶体管GT2截止。由于第八移位晶体管GT8处于开启状态，第五移位晶体管GT5截止。由于第一时钟信号线CK的信号为低电平，第三移位晶体管GT3导通，第四移位晶体管GT4和第六移位晶体管GT6均导通，第三电源线VGH的高电平信号经由第四移位晶体管GT4传输至信号输出线OUT，即 栅极输出信号为高电平信号。
在稳定阶段t4的第二子阶段t42中，第一时钟信号线CK的信号为高电平，第二时钟信号CB的信号为低电平，信号输入端INPUT的信号为高电平。第五移位晶体管GT5和第二移位晶体管GT2均截止。第一时钟信号线CK的信号为高电平，从而第一移位晶体管GT1和第三移位晶体管GT3均截止，由于第一移位存储电容C1的保持作用下，第四移位晶体管GT4和第六移位晶体管GT6均导通，高电平信号经由第四移位晶体管GT4传输至信号输出线OUT，即栅极输出信号为高电平信号。
在第二子阶段t42中，由于第二时钟信号线CB的信号为低电平，第七移位晶体管GT7导通，从而高电平信号经由第六移位晶体管GT6和第七移位晶体管GT7被传输至第三节点G3和第一节点G1，以使第三节点G3和第一节点G1的信号保持为高电平。
在第三子阶段t43中，第一时钟信号线CK和第二栅极时钟信号CB的信号均为高电平，信号输入端INPUT的信号为高电平。第五移位晶体管GT5和第二移位晶体管GT2截止。第一时钟信号线CK的信号为高电平，从而第一移位晶体管GT1和第三移位晶体管GT3均截止，第四移位晶体管GT4和第六移位晶体管GT6均导通。高电平信号经由第四移位晶体管GT4至信号输出线OUT，即栅极输出信号为高电平信号。
图5D为一种示例性实施例提供的控制电路的等效电路图，图5E为图5D提供的控制电路的时序图。如图5D和图5E所示，在一种示例性实施例中，控制电路分别与控制输入线EMINPUT、第三时钟信号线CK’、第四时钟信号线CB’、第三电源线VGH、第四电源线VGL和控制输入线EMOUT电连接。
在一种示例性实施例中，每个控制电路可为一个控制极移位寄存器，而多个控制极移位寄存器级联，从而多个控制极移位寄存器可分别向多条发光控制线提供驱动信号。
如图5D所示，驱动电路包括：第一控制晶体管ET1至第十控制晶体管ET10以及第一控制存储电容EC1至第三控制存储电容EC3。
第一控制晶体管ET1的控制极与第三时钟信号线CK’电连接，第一控 制晶体管ET1的第一极与控制输入线EMINPUT电连接，第一控制晶体管ET1的第二极与第一节点E1电连接；第二控制晶体管ET2的控制极与第一节点E1电连接，第二控制晶体管ET2的第一极与第三时钟信号线CK’电连接，第二控制晶体管ET2的第二极与第二节点E2电连接；第三控制晶体管ET3的控制极与第三时钟信号线CK’电连接，第三控制晶体管ET3的第一极与第四电源线VGL电连接，第三控制晶体管ET3的第二极与第二节点E2电连接；第四控制晶体管ET4的控制极与第四时钟信号线CB’电连接，第四控制晶体管ET4的第一极与第一节点E1电连接，第四控制晶体管ET4的第二极与第五控制晶体管ET5的第一极电连接；第五控制晶体管ET5的控制极与第二节点E2电连接，第五控制晶体管ET5的第二极与第三电源线VGH电连接；第六控制晶体管ET6的控制极与第二节点E2电连接，第六控制晶体管ET6的第一极与第四时钟信号线CB’电连接，第六控制晶体管ET6的第二极与第三节点E3电连接；第七控制晶体管ET7的控制极与第四时钟信号线CB’电连接，第七控制晶体管ET7的第二极与第九控制晶体管ET9的控制极电连接；第八控制晶体管ET8的控制极与第一节点E1电连接，第八控制晶体管ET8的第一极与第三电源线VGH电连接，第八控制晶体管ET8的第二极与第二控制存储电容EC的一个极板电连接；第九控制晶体管ET9的第一极与第三电源线VGH电连接，第九控制晶体管ET9的第二极与控制输出线EMOUT电连接；第十控制晶体管ET10的控制极与第一节点E1电连接，第十控制晶体管ET10的第一极与第四电源线VGL电连接，第十控制晶体管ET10的第二极与控制输出线EMOUT电连接；第一控制存储电容EC1的一个极板与第二节点E2电连接，第一控制存储电容EC1的另一个极板与第三节点E3电连接；第二控制存储电容EC2的另一个极板与第三电源线VGH电连接；第三控制存储电容EC3的一个极板与第一节点E1电连接，第三控制存储电容EC3的另一个极板与第四时钟信号线CB’电连接。
在一种示例性实施例中，第一控制晶体管ET1至第十控制晶体管ET10可以为P型晶体管或者可以为N型晶体管。
以第一控制晶体管ET1至第十控制晶体管ET10为N型晶体管为例，其中，以下信号的低电平可以等于第四电源线VGL的低电平，而信号的高电 平可以等于第三电源线VGH的高电平，如图5E所示，一种示例性实施例提供的控制电路的工作过程包括以下阶段：
在第一阶段P1，第三时钟信号线CK’的信号为低电平，所以第一控制晶体管ET1和第三控制晶体管ET3导通，导通的第一控制晶体管ET1将控制输出端EMINPUT的高电平信号传输至第一节点E1，从而使得第一节点E1的电平变为高电平，所以第二控制晶体管ET2、第八控制晶体管ET8以及第十控制晶体管ET10被截止。另外，导通的第三控制晶体管ET3将第三电源线VGL的低电平信号传输至第二节点E2，从而使得第二节点E2的电平变为低电平，所以第五控制晶体管ET5和第六控制晶体管ET6被导通。由于第四时钟信号线CB’的信号为高电平，所以第七控制晶体管ET7截止。另外，由于第三控制存储电容EC3的存储作用，第九控制晶体管ET9被截止。在第一阶段P1中，由于第九控制晶体管ET9以及第十控制晶体管ET10均被截止，控制输出线EMOUT的信号保持之前的低电平。
在第二阶段P2，第四时钟信号线CB’的信号为低电平，所以第四控制晶体管ET4、第七控制晶体管ET7导通。由于第三时钟信号线CK’的信号为高电平，所以第一控制晶体管ET1和第三控制晶体管ET3被截止。由于第一控制存储电容EC1的存储作用，所以第二节点E2可以继续保持上一阶段的低电平，所以第五控制晶体管ET5以及第六控制晶体管ET6被导通。第三电源线VGH的高电平信号通过导通的第五控制晶体管ET5以及第四控制晶体管ET4传输至第一节点E1，从而使得第一节点E1的电平继续保持上一阶段的高电平，所以第二控制晶体管ET2、第八控制晶体管ET8以及第十控制晶体管ET10被截止。另外，第四时钟信号线CB’的低电平信号通过导通的第六控制晶体管ET6以及第七控制晶体管ET7被传输至第九控制晶体管ET9的控制极，第九控制晶体管ET9被导通，导通的第九控制晶体管ET9将第三电源线VGH的高电平信号输出，所以控制输出线EMOUT的信号为高电平。
在第三阶段P3，第三时钟信号线CK’的信号为低电平，所以第一控制晶体管ET1以及第三控制晶体管ET3被导通。第四时钟信号线CB’的信号为高电平，所以第四控制晶体管ET4以及第七控制晶体管ET7被截止。由于第三控制存储电容EC3的存储作用，第九控制晶体管ET9保持导通状态，导 通的第九控制晶体管ET9将第三电源线VGH的高电平信号输出，所以控制输出线EMOUT的信号仍然为高电平。
在第四阶段P4，第三时钟信号线CK’的信号为高电平，所以第一控制晶体管ET1以及第三控制晶体管ET3被截止。第四时钟信号线CB’的信号为低电平，所以第四控制晶体管ET4以及第七控制晶体管ET7被导通。由于第二控制存储电容EC2的存储作用，所以第一节点E1的电平保持上一阶段的高电平，从而使得第二控制晶体管ET2、第八控制晶体管ET8以及第十控制晶体管ET10被截止。由于第一控制存储电容EC1的存储作用，第二节点E2继续保持上一阶段的低电平，从而使得第五控制晶体管ET5以及第六控制晶体管ET6被导通。另外，第四时钟信号线CB’的低电平信号通过导通的第六控制晶体管ET6以及第七控制晶体管ET7被传输至第九控制晶体管ET9的控制极，所以第九控制晶体管ET9被导通，导通的第九控制晶体管ET9将第三电源线VGH的高电平信号输出，所以控制输出线EMOUT的信号仍然为高电平。
在第五阶段P5，第三时钟信号线CK’的信号为低电平，所以第一控制晶体管ET1以及第三控制晶体管ET3被导通。第四时钟信号线CB’的信号为高电平，所以第四控制晶体管ET4以及第七控制晶体管ET7被截止。导通的第一控制晶体管ET1将控制输入线EMINPUT的高电平信号传输至第一节点E1，从而使得第一节点E1的电平变为低电平，所以第二控制晶体管ET2、第八控制晶体管ET8以及第十控制晶体管ET10被导通。导通的第二控制晶体管ET2将低电平的第三时钟信号线CK’的信号传输至第二节点E2，从而可以进一步拉低第二节点E2的电平，所以第二节点E2继续保持上一阶段的低电平，从而使得第五控制晶体管ET5以及第六控制晶体管ET6被导通。另外，导通的第八控制晶体管ET8将第三电源线VGH的高电平信号传输至第九控制晶体管ET9的控制极，所以第九控制晶体管ET9被截止。导通的第十控制晶体管ET10将第四电源线VGL的低电平信号输出，所以控制输出线EMOUT的信号变为低电平。
图5F为一种示例性实施例提供的多路复用电路的等效电路图。如图5F所示，至少一个多路复用电路包括多个复用晶体管；每个复用晶体管的栅极 连接一条复用控制线，第一极连接一条数据线Data，第二极连接一条复用数据线53。图5F是以多路复用电路包括六个复用晶体管MT1至MT6为例进行说明的。
在一种示例性实施例中，多路复用电路包括的复用晶体管的数量取决于复用数据线的数量。
在一种示例性实施例中，同一多路复用电路的所有复用晶体管的第二极连接同一条复用数据线，不同的多路复用电路的复用晶体管的第二极连接不同的复用数据线。
在一种示例性实施例中，在显示时，可向多条复用控制线轮流通入导通信号(能使晶体管导通的信号)，以使一条复用数据线经过一个多路复用电路中的多个复用晶体管轮流与多条不同的数据线导通，从而通过一条复用数据线向多条数据线分别提供所需的数据信号，也就是实现了通过一个信号源(如接头6)对多条数据线11的控制(即实现“一拖多”，如一拖6)，从而使为数据线提供信号的信号源的数量大大小于数据线的数量，以简化产品结构，例如可降低所需的驱动芯片的数量。
从简化结构的角度考虑，复用控制线的数量可等于每个多路复用电路中复用晶体管的数量(如均为6个)，即每个多路复用电路中的多个复用晶体管可分别连接不同的复用控制线，而每条复用控制线则与每个多路复用电路中的一个复用晶体管连接。
在一种示例性实施例中，由于复用控制线连接多个多路复用电路，故复用控制线可具有沿非显示区的周向延伸的部分，该部分的不同位置分别连接不同的多路复用电路。每条复用数据线仅连接一个多路复用电路，故每条复用数据线可直接连接到对应的多路复用电路。
图5G为一种示例性实施例提供的测试电路的等效电路图。如图5G所示，在一种示例性实施例中，测试电路分别与测试信号线CT和测试数据线电连接。至少一个测试电路包括多个测试晶体管；每个测试晶体管的栅极连接一条测试控制线CT，第一极连接一条数据线Data，第二极连接一条测试数据线。图5G是以测试电路包括三个测试晶体管：第一测试晶体管CT1至第三测试晶体管CT3、测试数据线包括：第一测试数据线C_Data1至第三测试数 据线C_Data3为例进行说明的。
在一种示例性实施例中，每条测试数据线与多个测试电路连接。
在一种示例性实施例中，在测试时，通过向测试控制线CT通入导通信号，即可使测试信号线中的信号经过不同测试电路中的测试晶体管进入多条相应的数据线，以实现对显示装置的检测。
在一种示例性实施例中，由于每条测试数据线与多个测试电路连接，故测试数据线的数量远远小于复用数据线的数量。因此，虽然测试电路位于显示装置的上方，但由于只要通过少数几条延伸到测试电路的测试信号线即可实现对测试电路的控制，故这些少数的测试信号线也不会占据很大的布图面积。
在一种示例性实施例中，测试数据线、测试控制线与测试电路的对应关系可以是多样的。
在一种示例性实施例中，测试数据线的数量可以等于每个测试电路中测试晶体管的数量(如均为3个)，而测试控制线只有一条，即每条测试数据线连接每个测试电路中的一个测试晶体管的第二极，而不同测试晶体管的第一极连接不同数据线11，所有测试电路的所有测试晶体管的栅极均连接该测试控制线。
在一种示例性实施例中，每条数据线连接的子像素颜色可以相同(图中用R表示红色子像素1，G表示绿色子像素1、B表示蓝色子像素1)，且每条测试数据线对应的数据线连接的子像素颜色相同，故通过向测试数据线持续通入相同的测试信号，可使同一颜色的子像素显示相同的亮度(如整体显示白色画面或其它单色画面)，便于定位有不良的子像素。
在一种示例性实施例中，复用信号线包括：复用控制线和复用数据线，测试信号线包括测试控制线和测试数据线。通常而言，复用信号线的数量远远多于测试信号线的数量总和，因此，可使数量较大的复用信号线“就近”与多路复用电路连接；而测试信号线虽然需要延伸较长的距离才能与测试电路连接，但因测试信号线的数量较少，故其引线的总长度也不会太大；由此，以上设计可降低引线的总长度和占用的布图面积，减小显示装置的边框，提高占屏比。
图5H为一种示例性实施例提供的静电释放电路的等效电路图。如图5H所示，在一种示例性实施例中，至少一个静电释放电路与一条信号线连接，且配置为释放其连接的信号线中的静电，其中，信号线为复用数据线53。静电释放电路包括：第一释放晶体管ST1至第四释放晶体管ST4。
第一释放晶体管ST1的控制极和第一极与第四电源线VGL电连接，第一释放晶体管ST1的第二极与第二释放晶体管ST2的第一极电连接，第二释放晶体管ST2的控制极和第二极与静电释放电路对应的信号线电连接，第三释放晶体管ST3的第一极与静电释放电路对应的信号线电连接，第三释放晶体管ST3的控制极和第二极与第四释放晶体管ST4的第一极电连接，第四释放晶体管ST4的控制极和第二极与第三电源线VGH电连接。
在一种示例性实施例中，设置静电释放电路可以防止信号线中的静电积累而引起放电击穿导致损坏，以释放信号线中积累的静电，实现对信号线的保护。
在一种示例性实施例中，每个静电释放电路连接的信号线可以为测试信号线。静电释放电路可有多个，分别与以上测试信号线和复用数据线以对它们进行保护。
在一种示例性实施例中，静电释放电路可以包括两个释放晶体管，其中，每个释放晶体管的一极都和自身的栅极连接，从而形成等效的二极管连接；而两个“二极管”之间连接要保护的信号线，两个“二极管”的另外两端分别连接第三电源线VGH和第四电源线VGL。由此，当信号线中因积累正电荷出现瞬时高压(如100V)时，其中一个“二极管”导通，释放信号线中的正电荷；而当信号线中因积累负电荷出现瞬时低压(如-100V)时，另一个“二极管”导通，释放信号线中的负电荷。
图6为一种示例性实施例提供的显示基板的有源层的膜层示意图，图7为一种示例性实施例提供的显示基板的第一金属层的膜层示意图，图8为一种示例性实施例提供的显示基板的第二金属层的膜层示意图，图9为一种示例性实施例提供的显示基板的第三金属层的膜层示意图。如图6至9所示，在一种示例性实施例中，显示基板包括：基底以及依次叠设在基底上的有源层、第一绝缘层、第一金属层、第二绝缘层、第二金属层、第三绝缘层和第 三金属层。
在一种示例性实施例中，基底可以为刚性基底或柔性基底，其中，刚性基底可以为但不限于玻璃、金属萡片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在一种示例性实施例中，如图6所示，有源层包括：像素电路的有源层11、驱动电路的有源层21、多路复用电路的有源层31、静电释放电路的有源层41、测试电路的有源层(图中未示出)以及控制电路的有源层(图中未示出)。其中，像素电路的有源层11包括：多个像素晶体管的有源层。驱动电路的有源层包括：多个移位晶体管的有源层。多路复用电路的有源层包括：多个复用晶体管的有源层。静电释放电路的有源层包括：多个释放晶体管的有源层。测试电路的有源层包括：多个测试晶体管的有源层。驱动电路的有源层包括：多个控制晶体管的有源层。
如图4和7所示，第一金属层包括：像素电路的第一金属层12、驱动电路的第一金属层22、多路复用电路的第一金属层32、静电释放电路的第一金属层42、测试电路的第一金属层(图中未示出)、控制电路的第一金属层(图中未示出)、复用数据线53、发光控制线EM、栅线Gate、复位信号线Reset和封装电极50。其中，像素电路的第一金属层包括：多个像素晶体管的控制极以及像素存储电容的第一极板。驱动电路的第一金属层包括：多个移位晶体管的控制极、第一移位存储电容的第二极板和第二移位存储电容的第二极板。多路复用电路的第一金属层包括：多个复用晶体管的控制极。静电释放电路的第一金属层包括多个释放晶体管的控制极。
如图7所示，在一种示例性实施例中，位于非显示区的第一金属层还包括：栅线连接电极51和复位连接电极52。
在一种示例性实施例中，栅线连接电极51分别与栅线Gate和信号输出线电连接；复位连接电极52分别与复位信号线Reset和信号输入线电连接。
如图8所示，在一种示例性实施例中，第二金属层包括：像素电路的第二金属层13、驱动电路的第二金属层23和初始信号线Vinit。其中，像素电 路的第二金属层包括：像素存储电容的第二极板以及电源连接线。驱动电路的第二金属层包括：第一连接电极、第二连接电极、第一移位存储电容的第一极板和第二移位存储电容的第一极板。
如图8所示，在一种示例性实施例中，位于非显示区的第二金属层还包括：复用连接电极61和初始连接电极62。
在一种示例性实施例中，复用连接电极61分别与多路复用电路和数据线电连接，初始连接电极62分别与初始信号线Vinit和初始信号供电线电连接。
在一种示例性实施例中，第三绝缘层上设置有暴露出复用连接电极的过孔和暴露出初始连接电极的过孔；第二绝缘层和第三绝缘层上设置有暴露出栅线连接电极的过孔和暴露出复位连接电极的过孔；
数据线通过暴露出复用连接电极的过孔与复用连接电极电连接，初始信号供电线通过暴露出初始连接电极的过孔与初始信号线电连接；
信号输出线通过暴露出栅线连接电极的过孔与栅线连接电极电连接，信号输入线通过暴露出复位连接电极的过孔与复位连接电极电连接。
如图9所示，第三金属层包括：像素电路的第三金属层14、驱动电路的第三金属层24、多路复用电路的第三金属层34、静电释放电路的第三金属层44、测试电路的第三金属层(图中未示出)、控制电路的第三金属层(图中未示出)、连接电极71、数据线Data、第一电源线VDD、第一电源供电线S_VDD、初始信号供电线S_Vinit、复用控制线MUX、第三电源线VGH、第四电源线VGL、第一时钟信号线CK、第二时钟信号线CB、第一时钟信号线CK’、第二时钟信号线CB’、测试控制线CT和第二电源供电线S_VSS。像素电路的第三金属层包括：多个像素晶体管的第一极和第二极。驱动电路的第三金属层包括：多个移位晶体管的第一极和第二极。多路复用电路的第三金属层包括：多个移位晶体管的第一极和第二极。静电释放电路的第三金属层包括：多个释放晶体管的第一极和第二极。测试电路的第三金属层包括：多个测试晶体管的第一极和第二极。控制电路的第三金属层包括：多个控制晶体管的第一极和第二极。
在一种示例性实施例中，如图4所示，第二电源供电线S_VSS在基底上的正投影与封装电极50在基底上的正投影至少部分重叠。
在一种示例性实施例中，第二绝缘层和第三绝缘层上设置有暴露出封装电极的过孔V11；第二电源供电线通过暴露出封装电极的过孔与封装电极电连接。
在一种示例性实施例中，第二绝缘层和第三绝缘层上设置有多个过孔阵列V10。设置在封装电极上的过孔在基底上的正投影覆盖过孔阵列在基底上的正投影。
在一种示例性实施例中，沿第二方向排布的多个子像素称为一行子像素，每行子像素的沿第一方向的长度为74微米至75微米。
在一种示例性实施例中，靠近弧形显示边界，且呈阶梯状的信号线中的每一级阶梯的沿第一方向的长度为每行子像素的沿第一方向的长度的整数倍。其中，信号线包括：第一电源供电线、初始信号供电线、复用控制线、第三电源线、第四电源线、第一时钟信号线、第二时钟信号线、测试控制线和第二电源供电线。
在一种示例性实施例中，第一金属层、第二金属层和第三金属层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
在一种示例性实施例中，第一绝缘层、第二绝缘层和第三绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层称为第一栅绝缘层、第二绝缘层成为第二栅绝缘层、第三绝缘层称为层间绝缘层。
图6、图10至图14为一种示例性实施例提供的显示基板的制备过程的示意图，示意了显示基板中区域A1内的版图结构。下面结合图6、图10至图14说明一种示例性实施例提供的显示基板。
(1)在基底形成有源层，包括：在基底上沉积半导体薄膜，通过构图工艺对半导体薄膜进行构图，形成有源层。有源层包括：像素电路的有源层11、驱动电路的有源层21、多路复用电路的有源层31、静电释放电路的有源层41、测试电路的有源层(图中未示出)以及控制电路的有源层(图中未示出)。 其中，像素电路的有源层包括：第一像素晶体管的有源层PT11至第六像素晶体管的有源层的有源层PT61。驱动电路的有源层21包括：第一移位晶体管的有源层GT11至第八移位晶体管的有源层GT81，如图6、图10A和图10B所示，图10A为像素电路形成有源层后的示意图，图10B为驱动电路形成有源层后的示意图。
(2)形成第一金属层，包括：在形成有有源层的基底上沉积第一绝缘薄膜，通过构图工艺对第一绝缘薄膜进行构图，形成位于第一绝缘层。在第一绝缘层上沉积第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，形成第一金属层。第一金属层包括：像素电路的第一金属层12、驱动电路的第一金属层22、多路复用电路的第一金属层32、静电释放电路的第一金属层42、测试电路的第一金属层(图中未示出)、控制电路的第一金属层(图中未示出)、复用数据线53、发光控制线EM、栅线Gate、复位信号线Reset、封装电极50、栅线连接电极51和复位连接电极52。其中，像素电路的第一金属层包括：第一像素晶体管的控制极PT12至第六像素晶体管的控制极PT62以及像素存储电容的第一极板PC1。驱动电路的第一金属层包括：第一移位晶体管的控制极GT12至第八移位晶体管的控制极GT82、第一移位存储电容的第二极板GC12和第二移位存储电容的第二极板GC22。多路复用电路的第一金属层包括：多个复用晶体管的控制极。静电释放电路的第一金属层包括多个释放晶体管的控制极，如图11A、图11B和图11C所示，图11A为形成第一金属层后的示意图，图11B为像素电路形成第一金属层后的放大示意图，图11C为驱动电路形成第一金属层后的放大示意图。
在一种示例性实施例中，第一像素晶体管的控制极PT12与复位信号线Reset一体成型，第二像素晶体管的控制极PT22和第四像素晶体管的控制极PT42与栅线Gate与栅线Gate一体成型，第三像素晶体管的控制极PT32与像素存储电容PC的第一极板PC1一体成型，第五像素晶体管的控制极PT52和第六像素晶体管的控制极PT62与发光控制线EM一体成型。
在一种示例性实施例中，第一移位晶体管的控制极GT12与第三移位晶体管的控制极GT32一体成型，第四移位晶体管的控制极GT42和第一移位存储电容的第二极板GC12一体成型，第五移位晶体管的控制极GT52和第 二移位存储电容的第二极板GC22一体成型。
在一种示例性实施例中，栅线连接电极51与栅线Gate电连接，复位连接电极52与复位信号线Reset电连接。
(3)形成第二金属层，包括：在形成有第一金属层的基底上，沉积第二绝缘薄膜，通过构图工艺对第二绝缘薄膜进行构图，形成第二绝缘层。在形成有第二绝缘层的基底上沉积第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，形成第二金属层。第二金属层包括：像素电路的第二金属层13、驱动电路的第二金属层23、初始信号线Vinit、复用连接电极61和初始连接电极62。其中，像素电路的第二金属层包括：像素存储电容的第二极板PC2以及电源连接线VL。驱动电路的第二金属层包括：第一连接电极81、第二连接电极82、第一移位存储电容的第一极板GC11和第二移位存储电容的第一极板GC21，如图12A、图12B和图12C所示，图12A为形成第二金属层后的示意图，图12B为像素电路形成第二金属层后的放大示意图，图12C为驱动电路形成第二金属层后的放大示意图。
在一种示例性实施例中，初始连接电极62与初始信号线Vinit电连接。复用连接电极61配置为连接数据线。
(4)形成第三绝缘层，包括：在形成有第二金属层的基底上，沉积第三绝缘薄膜，通过构图工艺对第三绝缘薄膜进行构图，形成第三绝缘层。形成第三绝缘层开设有多个过孔。多个过孔包括：像素电路中的第一过孔V1、驱动电路中的第二过孔V2、多路复用电路中的第三过孔V3、静电释放电路中的第四过孔V4、暴露出栅线连接电极的第五过孔V5、暴露出复位连接电路的第六过孔V6、暴露出复用连接电极的过孔V7、暴露出初始连接电极的过孔V8以及暴露出复用数据线的过孔V9，如图13A、13B和13C所示。图13A为形成第三绝缘层后的示意图，图13B为像素电路形成第三绝缘层后的放大示意图，图13C为驱动电路形成第三绝缘层后的放大示意图。
在一种示例性实施例中，如图13B所示，像素电路中的第一过孔V1包括：开设在第一绝缘层、第二绝缘层和第三绝缘层上的第一子过孔V1_1至第五子过孔V1_5，开设在第二绝缘和第三绝缘层上的第六子过孔V1_6以及开设在第三绝缘层上的第七子过孔V1_7至第九子过孔V1_9。其中，第一子 过孔V1_1暴露出第一像素晶体管的有源层PT11，第二子过孔V1_2暴露出第二像素晶体管的有源层PT21，第三子过孔V1_3暴露出第四像素晶体管的有源层PT41，第四子过孔V1_4暴露出第六像素晶体管的有源层PT61，第五子过孔V1_5暴露出第五像素晶体管的有源层PT51，第六子过孔V1_6暴露出像素存储电容PC的第一极板PC1，第七子过孔V1_7暴露出初始信号线Vinit，第八子过孔V1_8暴露出电源连接线VL，第九子过孔V1_9暴露出像素存储电容PC的第二极板PC2。
在一种示例性实施例中，如图13C所示，第二过孔包括：开设在第一绝缘层、第二绝缘层和第三绝缘层上的第一子过孔V2_1至第六子过孔V2_6，开设在第二绝缘和第三绝缘层上的第六子过孔V2_7至第十子过孔V2_10以及开设在第三绝缘层上的第十一子过孔V2_11至第十五子过孔V2_15。其中，第一子过孔V2_1暴露出第四移位晶体管、第六移位晶体管和第七移位晶体管的有源层。第二子过孔V2_2暴露出第一移位晶体管的有源层。第三子过孔V2_3暴露出第二移位晶体管的有源层。第四子过孔V2_4暴露出第三移位晶体管的有源层。第五子过孔V2_5暴露出第八移位晶体管的有源层。第六子过孔V2_6暴露出第五移位晶体管的有源层。第七子过孔V2_7暴露出第七移位晶体管的控制极。第八子过孔V2_8暴露出第一移位晶体管和第三移位晶体管的控制极。第九子过孔V2_9暴露出第二移位晶体管的控制极。第十子过孔V2_10暴露出第八移位晶体管的控制极。第十一子过孔V2_11暴露出第一移位存储电容的第二极板GC12。第十二子过孔V2_12暴露出第一连接电极。第十三子过孔V2_13暴露出第一移位存储电容GC1的第一极板GC11。第十四子过孔V2_14暴露出第二移位存储电容GC1的第一极板。第十五子过孔V2_15暴露出第二连接电极。
在一种示例性实施例中，第三过孔包括：开设第一绝缘层、第二绝缘层和第三绝缘层上的多个暴露出多个复用晶体管的有源层的子过孔。
在一种示例性实施例中，第四过孔包括：开设第一绝缘层、第二绝缘层和第三绝缘层上的多个暴露出多个释放晶体管的有源层的子过孔。
(5)形成第三金属层，包括：在形成有第三绝缘层的基底上，沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，形成第三金属层。第三 金属层包括：像素电路的第三金属层14、驱动电路的第三金属层24、多路复用电路的第三金属层34、静电释放电路的第三金属层44、测试电路的第三金属层(图中未示出)、控制电路的第三金属层(图中未示出)、电源连接线VL、连接电极71、数据线Data、第一电源线VDD、第一电源供电线S_VDD、初始信号供电线S_Vinit、复用控制线MUX、第三电源线VGH、第四电源线VGL、第一时钟信号线CK、第二时钟信号线CB、第一时钟信号线CK’、第二时钟信号线CB’、测试控制线CT和第二电源供电线S_VSS。其中，像素电路的第三金属层包括：第一像素晶体管的第一极PT13和第二极PT14至第六像素晶体管的第一极PT63和第二极PT64。驱动电路的第三金属层包括：第一移位晶体管的第一极GT13和第二极GT14至第八移位晶体管的第一极GT83和第二极GT84。多路复用电路的第三金属层包括：多个移位晶体管的第一极和第二极。静电释放电路的第三金属层包括：多个释放晶体管的第一极和第二极。测试电路的第三金属层包括：多个测试晶体管的第一极和第二极。控制电路的第三金属层包括：多个控制晶体管的第一极和第二极，如图14A、14B和14C所示。图14A为形成第三金属层后的示意图，图14B为像素电路形成第三金属层后的放大示意图，图14C为驱动电路形成第三金属层后的放大示意图。
在一种示例性实施例中，如图14B所示，第一像素晶体管的第一极PT13通过第一子过孔与第一像素晶体管PT1的有源层电连接，第一像素晶体管的第二极PT14通过第七子过孔与初始信号线Vinit电连接；第二像素晶体管的第一极PT23通过第二子过孔与第二像素晶体管的有源层电连接，第二像素晶体管的第一极PT23通过第六子过孔与像素存储电容PC的第一极板PC1电连接；第四像素晶体管的第一极PT43通过第三子过孔与第四像素晶体管的有源层电连接，第五像素晶体管的第一极PT53通过第五子过孔与第五像素晶体管的有源层电连接，第六像素晶体管的第二极PT64通过第六子过孔与第六像素晶体管的有源层电连接。
在一种示例性实施例中，如图14B所示，第一电源线VDD与第五像素晶体管的第一极PT53一体成型，连接电极71与第六像素晶体管的第二极PT64一体成型。
在一种示例性实施例中，如图14B所示，第一电源线VDD通过第八子过孔与电源连接线VL电连接，第一电源线VDD通过第九子过孔与像素存储电容PC的第二极板PC2电连接。
在一种示例性实施例中，如图14B所示，部分有源层复用为第二像素晶体管的第二极PT24、第三像素晶体管的第二极PT34和第六像素晶体管的第一极PT63为同一电极，部分有源层复用为第二像素晶体管的第二极PT24。
在一种示例性实施例中，如图14B所示，部分有源层复用为第三像素晶体管的第一极PT33、第四像素晶体管的第二极PT44和第五像素晶体管的第二极PT54为同一电极，部分有源层复用为第三像素晶体管的第一极PT33。
在一种示例性实施例中，如图14C所示，第一移位晶体管的第一极GT13和第一移位晶体管的第二极GT14通过第二子过孔与第一移位晶体管的有源层电连接，且第一移位晶体管的第一极GT13通过第十五子过孔与第二连接电极电连接，第一移位晶体管的第二极GT14通过第七子过孔与第一连接电极81电连接。第二移位晶体管的第一极GT23和第二移位晶体管的第二极GT24通过第三子过孔与第二移位晶体管的有源层电连接，且第二移位晶体管的第一极GT23通过第八子过孔与第一移位晶体管的控制极电连接，第二移位晶体管的第二极GT24通过第八子过孔与第一移位晶体管的控制极电连接。第三移位晶体管的第一极GT33和第三移位晶体管的第二极GT34通过第四子过孔与第三移位晶体管的有源层电连接，第三移位晶体管的第一极GT33通过第十子过孔与第八移位晶体管的控制极电连接。第四移位晶体管的第一极GT43和第四移位晶体管的第二极GT44通过第六过孔与第四移位晶体管的有源层电连接，且第四移位晶体管的第一极GT43通过第十三过孔与第一移位存储电容GC1的第一极板GC11电连接，第四移位晶体管的第二极GT44通过第十四过孔与第二移位存储电容GC1的第一极板GC21电连接。第五移位晶体管的第一极GT53和第五移位晶体管的第二极GT54通过第六过孔与第五移位晶体管的有源层电连接，且第五移位晶体管的第一极GT53通过第七子过孔与第七移位晶体管的控制极电连接。第六移位晶体管的第一极GT63通过第一子过孔与第六移位晶体管的有源层电连接。第七移位晶体管的第二极GT74通过第一子过孔与第七移位晶体管的有源层电连接。第八 移位晶体管的第一极GT83和第八移位晶体管的第二极GT84通过第五子过孔与第八移位晶体管的有源层电连接，且第八移位晶体管的第一极GT83通过第九子过孔与第二移位晶体管的控制极电连接；第八移位晶体管的第二极GT84通过第十四子过孔与第二移位晶体管的第二极电连接。
在一种示例性实施例中，如图14C所示，第一时钟信号线CK通过第八子过孔与第一移位晶体管的控制极电连接；第二时钟信号线CB通过第七子过孔与第七移位晶体管的控制极电连接；第三电源线VGH通过第十一子过孔与第一连接电极电连接。
在一种示例性实施例中，如图14C所示，第一移位晶体管的第二极GT14与第七移位晶体管GT74为同一电极，第二移位晶体管的第二极G24和第三移位晶体管的第二极G34为同一电极，第三移位晶体管的第一极GT33与第四电源线VGL一体成型，第四移位晶体管的第一极GT43和第六移位晶体管的第一极GT63为同一电极，部分有源层复用为第六移位晶体管的第一极GT63和第七移位晶体管的第一极GT73，且第六移位晶体管的第一极GT63和第七移位晶体管的第一极GT73为同一电极。
(6)形成平坦层，包括：在形成有第三金属层的基底上，沉积第四绝缘薄膜，通过构图工艺对第四绝缘薄膜进行构图，形成第四绝缘层。在形成有第四绝缘层的基底上涂覆平坦薄膜，通过平坦薄膜的掩膜、曝光和显影，形成第一平坦层。
(7)形成透明导电层，包括：在形成有平坦层的基底上，沉积透明导电薄膜，通过构图工艺对透明导电薄膜进行构图，形成透明导电层。透明导电层包括第一电极，第一电极形成在每个发光元件中，第一电极与连接电极71连接。
(8)形成像素定义层，包括：在形成透明导电层的基底上涂覆像素定义薄膜，通过掩膜、曝光和显影工艺形成像素定义层(Pixel Define Layer)，像素定义层形成在每个发光元件中，每个发光元件中的像素定义层形成有暴露出第一电极的开口区域。
(9)形成有机发光层，包括：在形成的像素定义层的开口区域内和像素 定义层上形成有机发光层，有机发光层与第一电极电连接。
(10)形成第二电极，包括：在形成有机发光层的基底上涂覆导电薄膜，通过构图工艺对导电薄膜进行构图，形成第二电极。第二电极覆盖每个发光元件中的有机发光层。第二电极与有机发光层电连接。
(11)形成封装层，在形成第二电极的基底上形成封装层，封装层包括无机材料的第一封装层、有机材料的第二封装层和无机材料的第三封装层，第一封装层设置在第二电极上，第二封装层设置在第一封装层上，第三封装层设置在第二封装层上，形成无机材料/有机材料/无机材料的叠层结构。
在一种示例性实施例中，平坦层可以采用有机材料，透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)。
在一种示例性实施例中，像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯。
在一种示例性实施例中，第二电极可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或更多种，或可以采用上述金属中任意一种或多种制成的合金。
在一种示例性实施例中，有源层可以为金属氧化物层。金属氧化物层可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物或者包含铟或镓和锌的氧化物。金属氧化物层可以单层，或者可以是双层，或者可以是多层。
本公开实施例还提供一种显示装置，包括：显示基板。
在一种示例性实施例中，显示装置可以为显示器、电视、手机、平板电脑、导航仪、数码相框、可穿戴显示产品具有任何显示功能的产品或者部件。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种显示基板，包括：显示区和围绕所述显示区的非显示区，所述显示区包括至少一段弧形显示边界；
    所述显示区包括：多个子像素，多条沿第一方向延伸的数据线以及多条沿第二方向延伸的栅线；每个子像素包括：像素电路和与所述像素电路连接的发光元件，每个子像素中的像素电路分别与栅线和数据线电连接；靠近所述弧形显示边界的至少部分子像素呈阶梯状排布；
    所述非显示区包括：多个级联的，且向多条栅线提供驱动信号的驱动电路；靠近所述弧形显示边界的至少部分驱动电路呈阶梯状排布；
    其中，所述第一方向与所述第二方向相交。
  2. 根据权利要求1所述的显示基板，其中，所述显示区还包括：多条沿第一方向延伸的第一电源线和多条沿第二方向延伸的初始信号线，每个子像素中的像素电路分别与第一电源线和初始信号线电连接；
    所述非显示区还包括：第一电源供电线和初始信号供电线；所述第一电源供电线和所述初始信号供电线为环状；
    所述第一电源供电线位于多个驱动电路靠近显示区的一侧，且与每个像素电路连接的第一电源线电连接；靠近所述弧形显示边界的第一电源供电线呈阶梯状；
    所述初始信号供电线位于多个驱动电路和所述第一电源供电线之间，且与每个像素电路连接的初始信号线电连接；靠近所述弧形显示边界的初始信号供电线呈阶梯状。
  3. 根据权利要求2所述的显示基板，其中，所述第一电源供电线的线宽大于所述初始信号供电线的线宽。
  4. 根据权利要求2或3所述的显示基板，其中，所述显示区还包括：第二电源线，每个子像素中的发光元件与第二电源线电连接；
    所述非显示区还包括：第二电源供电线；所述第二电源供电线为环状；
    所述第二电源供电线位于多个驱动电路远离显示区的一侧，且与每个发 光元件连接的第二电源线电连接；靠近所述弧形显示边界的第二电源供电线靠近显示区的表面呈阶梯状，靠近所述弧形显示边界的第二电源供电线远离显示区的表面呈圆弧状。
  5. 根据权利要求4所述的显示基板，其中，所述第二电源供电线的线宽大于所述第一电源供电线的线宽。
  6. 根据权利要求1至5任一所述的显示基板，其中，所述显示区还包括：多条沿第二方向延伸的发光控制线和复位控制线；每个子像素中的像素电路与所述发光控制线和所述复位控制线电连接；
    所述非显示区包括：多个级联的，且向多条发光控制线提供控制信号的控制电路；靠近所述弧形显示边界的至少部分控制电路呈阶梯状排布；
    多个驱动电路和多个控制电路分别位于所述显示区的相对设置的第一侧和第二侧。
  7. 根据权利要求1至6任一所述的显示基板，其中，所述非显示区还包括：多个多路复用电路，所述多路复用电路位于所述多个驱动电路和初始信号供电线之间，且与多条数据线电连接，配置为向连接的数据线提供数据信号；
    靠近所述弧形显示边界的至少部分多路复用电路呈阶梯状排布。
  8. 根据权利要求7所述的显示基板，其中，所述非显示区还包括：多条复用控制线和多条所述复用数据线；每个多路复用电路分别与多条复用控制线和一条复用数据线电连接；
    多条复用控制线位于多个驱动电路和多个多路复用电路之间；靠近所述弧形显示边界的多条复用控制线呈阶梯状。
  9. 根据权利要求1至8任一所述的显示基板，其中，所述非显示区还包括：多个静电释放电路，每个静电释放电路与一条信号线连接，且配置为释放所连接的信号线中的静电；所述信号线包括：复用数据线；
    多个静电释放电路位于所述多个驱动电路和第二电源供电线之间；靠近所述弧形显示边界的至少部分静电释放电路呈阶梯状排布。
  10. 根据权利要求1至9任一所述的显示基板，其中，所述非显示区还 包括：测试控制线和多个测试电路；所述测试电路分别与所述测试控制线和数据线电连接，且配置为向数据线提供测试信号；
    所述多个测试电路位于所述显示区的第三侧，所述第三侧不同于第一侧和第二侧；
    所述测试控制线位于第二电源供电线和多个静电释放电路之间；靠近所述弧形显示边界的测试控制线呈阶梯状。
  11. 根据权利要求1至10任一所述的显示基板，其中，所述非显示区还包括：第三电源线和第四电源线；每个驱动电路分别与第三电源线和第四电源线电连接；所述第三电源线和所述第四电源线为环状；
    所述第三电源线位于静电释放电路和多个驱动电路之间；靠近所述弧形显示边界的第三电源线呈阶梯状；
    所述第四电源线位于所述第三电源线和多个驱动电路之间，靠近所述弧形显示边界的第四电源线呈阶梯状。
  12. 根据权利要求11所述的显示基板，其中，所述非显示区还包括：第一时钟信号线、第二时钟信号线、信号输入线和信号输出线，每个驱动电路分别与第一时钟信号线、第二时钟信号线、信号输入线和信号输出线电连接；
    所述第一时钟信号线位于所述第三电源线和多个驱动电路之间，靠近所述弧形显示边界的第一时钟信号线呈阶梯状；
    所述第二时钟信号线位于所述第三电源线和所述第一时钟信号线之间；靠近所述弧形显示边界的第二时钟信号线呈阶梯状；
    所述信号输入线和所述信号输出线位于所述驱动电路靠近显示区的一侧。
  13. 根据权利要求12所述的显示基板，其中，所述非显示区还包括：多个复用连接电极和多个初始连接电极；
    所述复用连接电极分别与多路复用电路和数据线电连接，
    所述初始连接电极分别与初始信号线和初始信号供电线电连接；
    其中，所述多个复用连接电极和所述多个初始连接电极同层设置，所述初始连接电极与所述初始信号线同层设置，所述复用连接电极与所述数据线 异层设置。
  14. 根据权利要求13所述的显示基板，其中，所述非显示区还包括：栅线连接电极和复位连接电极；
    所述栅线连接电极分别与所述栅线和所述信号输出线电连接；
    所述复位连接电极分别与所述复位信号线和所述信号输入线电连接；
    其中，所述栅线连接电极与所述复位连接电极同层设置，且与所述栅线同层设置。
  15. 根据权利要求4所述的显示基板，其中，所述非显示区还包括：封装电极；
    所述封装电极位于所述第二电源供电线远离所述显示区的一侧；所述封装电极与所述第二电源供电线异层设置，且与所述第二电源供电线电连接；
    所述封装电极开设有多个过孔。
  16. 根据权利要求1所述的显示基板，其中，所述显示基板还包括：位于非显示区的多路复用电路、静电释放电路、测试电路和控制电路，所述像素电路包括：多个像素晶体管、所述驱动电路包括：多个移位晶体管、所述多路复用电路包括：多个复用晶体管、所述静电释放电路包括：多个释放晶体管、所述测试电路包括：多个测试晶体管、所述控制电路包括：多个控制晶体管；
    所述显示基板包括：基底以及依次叠设在所述基底上的有源层、第一绝缘层、第一金属层、第二绝缘层、第二金属层、第三绝缘层和第三金属层；
    所述有源层包括：多个像素晶体管的有源层、多个移位晶体管的有源层、多个复用晶体管的有源层、多个释放晶体管的有源层、多个测试晶体管的有源层和多个控制晶体管的有源层；所述第一金属层包括：多个像素晶体管的控制极、多个移位晶体管的控制极、多个复用晶体管的控制极、多个测试晶体管的控制极、多个释放晶体管的控制极、多个控制晶体管的控制极、复用数据线、发光控制线、栅线、复位信号线、栅线连接电极、复位连接电极和封装电极；所述第二金属层包括：初始信号线、复用连接电极和初始连接电极；所述第三金属层包括：多个像素晶体管的第一极和第二极、多个移位晶 体管的第一极和第二极、多个复用晶体管的第一极和第二极、多个测试晶体管的第一极和第二极、多个释放晶体管的第一极和第二极、多个控制晶体管的第一极和第二极、数据线、第一电源线、第一电源供电线、初始信号供电线、复用控制线、第三电源线、第四电源线、第一时钟信号线、第二时钟信号线、测试控制线和第二电源供电线。
  17. 根据权利要求16所述的显示基板，其中，所述第三绝缘层上设置有暴露出复用连接电极的过孔和暴露出初始连接电极的过孔；所述第二绝缘层和所述第三绝缘层上设置有暴露出栅线连接电极的过孔和暴露出复位连接电极的过孔；
    所述数据线通过暴露出复用连接电极的过孔与复用连接电极电连接，所述初始信号供电线通过暴露出初始连接电极的过孔与所述初始信号线电连接；
    所述信号输出线通过暴露出栅线连接电极的过孔与栅线连接电极电连接，所述信号输入线通过暴露出复位连接电极的过孔与复位连接电极电连接。
  18. 根据权利要求16或17所述的显示基板，其中，所述第二电源供电线在基底上的正投影与所述封装电极在基底上的正投影至少部分重叠；
    所述第二绝缘层和所述第三绝缘层上设置有暴露出封装电极的过孔；所述第二电源供电线通过暴露出封装电极的过孔与封装电极电连接；
    所述第二绝缘层和所述第三绝缘层上还设置有多个过孔阵列；设置在封装电极上的过孔在基底上的正投影覆盖所述过孔阵列在基底上的正投影。
  19. 根据权利要求1所述的显示基板，其中，沿第二方向排布的多个子像素称为一行子像素，每行子像素沿第一方向的长度为74微米至75微米；
    靠近所述弧形显示边界，且呈阶梯状的信号线中的每一级阶梯沿第一方向的长度为每行子像素沿第一方向的长度的整数倍；
    所述信号线包括：第一电源供电线、初始信号供电线、复用控制线、第三电源线、第四电源线、第一时钟信号线、第二时钟信号线、测试控制线和第二电源供电线。
  20. 一种显示装置，包括：如权利要求1至19任一项所述的显示基板。
PCT/CN2020/116162 2020-09-18 2020-09-18 显示基板和显示装置 WO2022056829A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB2217902.2A GB2610958A (en) 2020-09-18 2020-09-18 Display substrate and display device
PCT/CN2020/116162 WO2022056829A1 (zh) 2020-09-18 2020-09-18 显示基板和显示装置
CN202080002029.7A CN114556205B (zh) 2020-09-18 2020-09-18 显示基板和显示装置
US17/418,258 US11721291B2 (en) 2020-09-18 2020-09-18 Display substrate and display apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/116162 WO2022056829A1 (zh) 2020-09-18 2020-09-18 显示基板和显示装置

Publications (1)

Publication Number Publication Date
WO2022056829A1 true WO2022056829A1 (zh) 2022-03-24

Family

ID=80775819

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/116162 WO2022056829A1 (zh) 2020-09-18 2020-09-18 显示基板和显示装置

Country Status (4)

Country Link
US (1) US11721291B2 (zh)
CN (1) CN114556205B (zh)
GB (1) GB2610958A (zh)
WO (1) WO2022056829A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115241236A (zh) * 2022-06-20 2022-10-25 京东方科技集团股份有限公司 显示基板及显示装置
CN115691384B (zh) * 2022-10-21 2024-07-30 厦门天马微电子有限公司 一种显示面板及显示装置
CN115835723A (zh) * 2022-12-08 2023-03-21 京东方科技集团股份有限公司 显示基板、显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160139706A1 (en) * 2014-11-13 2016-05-19 Samsung Display Co., Ltd. Touch screen panel integrated display device
CN107833895A (zh) * 2017-11-27 2018-03-23 京东方科技集团股份有限公司 显示面板及其制造方法、显示装置
CN107991799A (zh) * 2018-01-02 2018-05-04 上海中航光电子有限公司 显示面板及显示装置
CN108445686A (zh) * 2018-03-28 2018-08-24 上海中航光电子有限公司 阵列基板、显示面板与显示装置
CN110297342A (zh) * 2019-06-28 2019-10-01 上海天马有机发光显示技术有限公司 一种显示面板和显示装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102295874B1 (ko) 2014-07-24 2021-08-31 엘지디스플레이 주식회사 디스플레이 장치
KR102466371B1 (ko) * 2014-12-30 2022-11-15 엘지디스플레이 주식회사 표시장치와 이의 구동방법
JP2016218216A (ja) * 2015-05-19 2016-12-22 パナソニック液晶ディスプレイ株式会社 表示パネル
KR102394409B1 (ko) 2015-09-30 2022-05-03 엘지디스플레이 주식회사 유기발광다이오드 표시장치
KR20170092726A (ko) 2016-02-03 2017-08-14 삼성디스플레이 주식회사 표시장치
CN105739154B (zh) * 2016-04-29 2019-09-27 上海天马有机发光显示技术有限公司 一种显示面板以及电子设备
KR102666848B1 (ko) 2016-05-17 2024-05-21 삼성디스플레이 주식회사 표시 장치
KR102559544B1 (ko) * 2016-07-01 2023-07-26 삼성디스플레이 주식회사 표시 장치
CN106873224A (zh) * 2017-04-25 2017-06-20 武汉华星光电技术有限公司 一种显示面板及显示装置
CN109308860A (zh) * 2017-07-26 2019-02-05 上海和辉光电有限公司 一种显示基板、显示面板及显示装置
CN107887421B (zh) 2017-10-30 2021-03-05 武汉天马微电子有限公司 一种显示面板及显示装置
KR102436563B1 (ko) 2017-12-27 2022-08-26 엘지디스플레이 주식회사 표시장치
CN110867472A (zh) 2019-11-26 2020-03-06 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
CN111128080B (zh) * 2020-03-30 2020-08-04 京东方科技集团股份有限公司 显示基板及显示装置
CN111445862B (zh) 2020-05-11 2022-05-24 京东方科技集团股份有限公司 显示面板和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160139706A1 (en) * 2014-11-13 2016-05-19 Samsung Display Co., Ltd. Touch screen panel integrated display device
CN107833895A (zh) * 2017-11-27 2018-03-23 京东方科技集团股份有限公司 显示面板及其制造方法、显示装置
CN107991799A (zh) * 2018-01-02 2018-05-04 上海中航光电子有限公司 显示面板及显示装置
CN108445686A (zh) * 2018-03-28 2018-08-24 上海中航光电子有限公司 阵列基板、显示面板与显示装置
CN110297342A (zh) * 2019-06-28 2019-10-01 上海天马有机发光显示技术有限公司 一种显示面板和显示装置

Also Published As

Publication number Publication date
GB202217902D0 (en) 2023-01-11
CN114556205B (zh) 2023-10-24
CN114556205A (zh) 2022-05-27
US11721291B2 (en) 2023-08-08
GB2610958A (en) 2023-03-22
US20220319437A1 (en) 2022-10-06

Similar Documents

Publication Publication Date Title
WO2022056829A1 (zh) 显示基板和显示装置
JP2023520267A (ja) 表示基板および表示装置
WO2023241490A1 (zh) 显示基板和显示装置
WO2021237725A1 (zh) 显示基板和显示装置
WO2022017044A1 (zh) 一种显示装置及其驱动方法
EP3993055A1 (en) Display substrate, preparation method therefor, and display apparatus
CN113745273A (zh) 显示基板和显示装置
WO2022160492A1 (zh) 显示基板及其制备方法、显示装置
WO2024109358A1 (zh) 显示面板及其制备方法、显示装置
CN114122025A (zh) 显示基板及其制备方法、显示装置
WO2022088980A1 (zh) 显示基板及其制备方法、显示装置
CN115020461A (zh) 显示基板及显示装置
WO2022017042A9 (zh) 显示装置及其驱动方法
WO2022082753A1 (zh) 显示基板及其制备方法、显示装置
WO2024046040A1 (zh) 显示面板和显示装置
WO2023066104A1 (zh) 显示基板及显示装置
WO2022198487A1 (zh) 显示基板及其制备方法、显示装置
WO2022227085A1 (zh) 显示基板及其制作方法、显示装置
WO2023035178A1 (zh) 显示基板及显示装置
WO2022227478A1 (zh) 一种显示基板及其制作方法、显示装置
WO2023184163A1 (zh) 显示基板及显示装置
WO2023226010A1 (zh) 移位寄存器及其驱动方法、显示基板和显示装置
WO2023231012A1 (zh) 显示基板和显示装置
US20240203343A1 (en) Display Substrate and Display Apparatus
WO2023060581A1 (zh) 显示基板及其制备方法、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20953687

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 202217902

Country of ref document: GB

Kind code of ref document: A

Free format text: PCT FILING DATE = 20200918

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 04.07.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 20953687

Country of ref document: EP

Kind code of ref document: A1