WO2022082753A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2022082753A1
WO2022082753A1 PCT/CN2020/123336 CN2020123336W WO2022082753A1 WO 2022082753 A1 WO2022082753 A1 WO 2022082753A1 CN 2020123336 W CN2020123336 W CN 2020123336W WO 2022082753 A1 WO2022082753 A1 WO 2022082753A1
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Prior art keywords
test
multiplexing
frame
signal line
display area
Prior art date
Application number
PCT/CN2020/123336
Other languages
English (en)
French (fr)
Inventor
杜丽丽
胡明
魏锋
周宏军
龙跃
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080002444.2A priority Critical patent/CN114667553B/zh
Priority to US17/419,305 priority patent/US20220320228A1/en
Priority to PCT/CN2020/123336 priority patent/WO2022082753A1/zh
Publication of WO2022082753A1 publication Critical patent/WO2022082753A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and more particularly, to a display substrate, a method for manufacturing the same, and a display device.
  • OLED Organic Light Emitting Diode
  • TFTs thin film transistors
  • an exemplary embodiment of the present disclosure provides a display substrate including a display area and a frame area located around the display area;
  • the frame area includes a first frame and a second frame oppositely disposed in a first direction , the third frame and the fourth frame oppositely arranged in the second direction, the first corner connecting the first frame and the third frame, the second corner connecting the second frame and the third frame, connecting the The third corner of the first frame and the fourth frame and the fourth corner connecting the second frame and the fourth frame, at least one of the first to fourth corners is an arc-shaped corner part, the first direction is the extension direction of the scan signal lines in the display area, the second direction is the extension direction of the data signal lines in the display area; At least one is provided with a first wiring and a second wiring, a plurality of first rectangles are enclosed between the first wiring and the second wiring, and a plurality of shift register units are respectively located in the plurality of first in the rectangle.
  • At least one of the first to fourth corners is further provided with a third wiring, and the third wiring is located between the display area and the second wiring , and a plurality of second rectangles are formed between the second wiring and the third wiring.
  • the second rectangle is a rectangle, and the extending direction of the long side of the second rectangle is parallel to the first direction.
  • a plurality of first test cells are disposed in at least one of the first and second corners, and the plurality of first test cells are respectively located in the plurality of second rectangles.
  • At least one first test unit is disposed in the same second rectangle in at least one of the first corner and the second corner.
  • At least two shift register units are provided in the same first rectangle in at least one of the first corner and the second corner.
  • the first traces include gate signal lines of stepped traces
  • the second traces include test signal lines of stepped traces
  • the third traces include stepped traces
  • the test signal line includes at least one test control signal line and a plurality of test data signal lines;
  • the first test unit includes a plurality of test transistors along the first The control electrodes of the multiple test transistors are connected to the same test control signal line, the first electrodes of the multiple test multiplexing transistors are respectively connected to different test data signal lines, and the The second poles are respectively connected to different data signal lines in the display area.
  • arranging the plurality of test transistors along the first direction includes: the test transistors are sequentially arranged along the first direction and are flush in the second direction.
  • At least one third rectangle is enclosed between the test control signal line and the test data signal line, and dummy cells are arranged in at least one third rectangle.
  • At least one compensation capacitor is provided between the power signal line and the display area, and the compensation capacitor includes a first electrode plate and a second electrode plate, the first electrode plate and the second power supply line One end of the second electrode plate is connected to the test data signal line of the first test unit, and the other end of the second electrode plate is connected to the data signal line of the display area.
  • the height of the first test unit is 0.9 times to 1.3 times the width of the first test unit; the height of the first test unit is the height of the first test unit in the first direction size, the width of the first test unit is the size of the first test unit in the second direction.
  • the height of the first test unit is 70 ⁇ m to 100 ⁇ m, and the width of the first test unit is 60 ⁇ m to 90 ⁇ m.
  • a plurality of multiplexing units are disposed in at least one of the third and fourth corners, and the multiplexing units are respectively located in the plurality of second rectangles.
  • At least one multiplexing unit is provided in the same second rectangle in at least one of the third corner and the fourth corner.
  • At least one shift register unit is provided in the same first rectangle in at least one of the third corner portion and the fourth corner portion.
  • the first traces include gate signal lines of stepped traces
  • the second traces include multiplexed signal lines of stepped traces
  • the third traces include stepped traces
  • the minimum distance between the power signal line and the edge of the display area is less than the minimum distance between the multiplexed signal line and the edge of the display area, and the minimum distance between the multiplexed signal line and the edge of the display area is smaller than the gate The minimum distance between the signal line and the edge of the display area.
  • the multiplexing signal line includes a plurality of multiplexing control signal lines and at least one multiplexing data signal line;
  • the multiplexing unit includes a plurality of multiplexing transistors, and the multiplexing transistors are The first direction arrangement; the control electrodes of the multiplexing transistors are respectively connected to different multiplexing control signal lines, the first electrodes of the multiplexing transistors are connected to the same multiplexing data signal line, and the multiplexing transistors are connected to the same multiplexing data signal line.
  • the second electrodes of the multiplexing transistors are respectively connected to different data signal lines in the display area.
  • arranging the multiplexing transistors along the first direction includes: the multiplexing transistors are arranged in sequence along the first direction and are flush in the second direction.
  • the height of the multiplexing unit is 0.5 times to 0.9 times the width of the multiplexing unit; the height of the multiplexing unit is the size of the multiplexing unit in the first direction, the The width of the multiplexing unit is the size of the multiplexing unit in the second direction.
  • the height of the multiplexing unit is 35 ⁇ m to 45 ⁇ m, and the width of the multiplexing unit is 48 ⁇ m to 70 ⁇ m.
  • an exemplary embodiment of the present disclosure also provides a display device including the display substrate described in any one of the foregoing.
  • an exemplary embodiment of the present disclosure also provides a method for manufacturing a display substrate, the display substrate includes a display area and a frame area around the display area; the frame area includes a frame area on the first side.
  • the first frame and the second frame oppositely arranged upward, the third frame and the fourth frame oppositely arranged in the second direction, the first corner connecting the first frame and the third frame, and the first frame connecting the first frame and the third frame.
  • the second corner portion of the second frame and the third frame, the third corner connecting the first frame and the fourth frame, and the fourth corner connecting the second frame and the fourth frame, the first corner to At least one of the fourth corners is an arc-shaped corner, the first direction is the extension direction of the scan signal lines in the display area, and the second direction is the extension direction of the data signal lines in the display area ;
  • Described preparation method comprises:
  • a display structure in the display area, and forming a first wiring, a second wiring and a plurality of shift register units in at least one of the first to fourth corners;
  • a plurality of first rectangles are enclosed between the first wiring and the second wiring, and a plurality of shift register units are respectively located in the plurality of first rectangles.
  • At least one of the first to fourth corners is further formed with a third wiring, and the third wiring is located between the display area and the second wiring , a plurality of second rectangles are formed between the third wiring and the second wiring.
  • Fig. 1 is the outline schematic diagram of a kind of display device
  • FIG. 2 is a schematic structural diagram of a display device
  • FIG. 3 is a schematic plan view of a display area of a display substrate
  • FIG. 4 is a schematic cross-sectional structure diagram of a display area of a display substrate
  • FIG. 8 is a layout structure diagram of a test circuit according to an exemplary embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a second test unit according to an exemplary embodiment of the present disclosure.
  • 10 to 14 are schematic diagrams of preparing a second test unit according to an exemplary embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of a first test unit according to an exemplary embodiment of the present disclosure.
  • 16 to 20 are schematic diagrams of preparing a first test unit according to an exemplary embodiment of the present disclosure.
  • FIG. 21 is a layout structure diagram of a first test unit according to an exemplary embodiment of the present disclosure.
  • FIG. 22 is a layout structure diagram of a multiplexing unit according to an exemplary embodiment of the present disclosure.
  • FIG. 23 is a schematic structural diagram of a multiplexing unit according to an exemplary embodiment of the present disclosure.
  • 24 to 28 are schematic diagrams of preparing a multiplexing unit according to an exemplary embodiment of the present disclosure.
  • 21 the first test active layer
  • 22 the first test gate electrode
  • 23 the first test data line
  • 31 the second test active layer
  • 32 the second test gate electrode
  • 33 the second test data line
  • 51 the first multiplexing active layer
  • 52 the first multiplexing gate electrode
  • 53 the first multiplexing data line
  • 54 the first multiplexing connecting line
  • 55 the first multiplexing source electrode
  • 56 the first multiplexing drain electrode
  • 61 the second multiplexing active layer
  • 62 the second multiplexing gate electrode
  • 63 the second multiplexing data line
  • 64 the second multiplexing connecting line
  • 65 the second multiplexing source electrode
  • 66 the second multiplexing drain electrode
  • 71 the third multiplexing active layer
  • 72 the third multiplexing gate electrode
  • 73 the third multiplexing data line
  • test data signal line 90—multiplexing unit; 91—multiplexing transistor;
  • 101 substrate
  • 102 drive circuit layer
  • 103 light emitting structure layer
  • 104 encapsulation layer
  • 110 shift register unit
  • 120 compressor capacitance
  • 121 gate signal line
  • 122 test signal line
  • 123 power signal line
  • 201 the first border
  • 202 the second border
  • 203 the third border
  • the terms “installed”, “connected” and “connected” should be construed in a broad sense.
  • it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed should be construed in a broad sense.
  • it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
  • connection includes a case where constituent elements are connected together by means of an element having a certain electrical effect.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having a certain electrical effect” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by the two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • FIG. 1 is a schematic diagram of the appearance of a display device, and the appearance is a rectangle with rounded corners.
  • the display device may include a display area 100 and a frame area 200 located around the display area 100 .
  • the display area 100 may include a first edge (left edge) and a second edge (right edge) disposed oppositely in the first direction X, and a third edge disposed oppositely in the second direction Y (upper edge) and the fourth edge (lower edge), the adjacent edges are connected by arc-shaped chamfers to form a rounded quadrilateral shape.
  • the frame area 200 may include a first frame (left frame) 201 and a second frame (right frame) 202 arranged oppositely in the first direction X, a third frame oppositely arranged in the second direction Y
  • first edge and the second edge may be parallel to the second direction Y
  • third edge and the fourth edge may be parallel to the first direction X
  • first direction X and the second direction Y intersect.
  • first direction X may be the extension direction (row direction) of the scan signal lines in the display area
  • second direction Y may be the extension direction (column direction) of the data signal lines in the display area
  • first direction The X and the second direction Y may be perpendicular to each other.
  • part of the display driving and performance detection circuits are usually arranged in the frame area.
  • the improvement of resolution, the increase of the number of pixels, and the increase of display driving circuits and performance detection circuits it not only increases the difficulty of circuit layout, but also results in a larger space occupied by the circuit, which is not conducive to the design of narrow borders.
  • FIG. 2 is a schematic structural diagram of a display device.
  • the OLED display device may include a scan signal driver, a data signal driver, a lighting signal driver, an OLED display substrate, a first power supply unit, a second power supply unit and an initial power supply unit.
  • the OLED display substrate includes at least a plurality of scan signal lines (S1 to SN), a plurality of data signal lines (D1 to DM), and a plurality of light emission signal lines (EM1 to EMN), and the scan signal driver is configured
  • the data signal driver is configured to supply the data signals to the plurality of data signal lines (D1 to DM)
  • the light emission signal driver is configured to sequentially supply the plurality of light emission signals Lines (EM1 to EMN) provide lighting control signals.
  • the plurality of scan signal lines and the plurality of light emitting signal lines extend in the horizontal direction
  • the plurality of data signal lines extend in the vertical direction
  • the OLED display substrate includes a plurality of scanning signal lines, light-emitting signal lines and data signal lines to define a plurality of sub-pixels, and at least one sub-pixel includes a pixel driving circuit and a light-emitting device.
  • the first power supply unit, the second power supply unit and the initial power supply unit are respectively configured to supply the first power supply voltage, the second power supply voltage and the initial power supply voltage to the pixel driving circuit through the first power supply line, the second power supply line and the initial signal line.
  • FIG. 3 is a schematic plan view of a display area of a display substrate.
  • the display area may include a plurality of pixel units P arranged in a matrix, and at least one of the plurality of pixel units P includes a first sub-pixel P1 that emits light of a first color, and a sub-pixel P1 that emits light of a second color.
  • the second sub-pixel P2 and the third sub-pixel P3 emitting light of the third color, the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 all include a pixel driving circuit and a light-emitting device.
  • the pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are respectively connected to the scanning signal line, the data signal line and the light-emitting signal line, and the pixel driving circuit is configured to connect the scanning signal line and the light-emitting signal line. Under the control of the line, the data voltage transmitted by the data signal line is received, and the corresponding current is output to the light-emitting device.
  • the light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to respond to the current output by the pixel driving circuit of the sub-pixel. Brightness of light.
  • the pixel unit P may include red sub-pixels, green sub-pixels, and blue sub-pixels, or may include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, the present disclosure is herein Not limited.
  • the shape of the sub-pixels in the pixel unit may be rectangular, diamond, pentagon or hexagonal.
  • the pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically, or in a zigzag manner.
  • the pixel unit includes four sub-pixels, the four sub-pixels can be arranged in a horizontal, vertical, or square manner. The arrangement is not limited in this disclosure.
  • FIG. 4 is a schematic cross-sectional structure diagram of a display area of a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate.
  • the display substrate may include a driving circuit layer 102 disposed on a substrate 101 , a light emitting device 103 disposed on the side of the driving circuit layer 102 away from the substrate 101 , and a light emitting device 103 disposed on the side of the substrate 101 .
  • the encapsulation layer 104 on the side of the device 103 away from the substrate 101 .
  • the display substrate may include other film layers, such as spacer columns, etc., which are not limited in the present disclosure.
  • the substrate may be a flexible substrate, or it may be a rigid substrate.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer and a second inorganic material layer, and the materials of the first flexible material layer and the second flexible material layer may be made of polymer.
  • the materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx ) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).
  • PI imide
  • PET polyethylene terephthalate
  • surface-treated soft polymer film the materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx ) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).
  • the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting the pixel driving circuit, and FIG. 4 takes the example of including one driving transistor and one storage capacitor in each sub-pixel for illustration.
  • the driving circuit layer 102 of each sub-pixel may include: a first insulating layer disposed on the substrate; an active layer disposed on the first insulating layer; and a second insulating layer covering the active layer The gate electrode and the first capacitor electrode arranged on the second insulating layer; the third insulating layer covering the gate electrode and the first capacitor electrode; the second capacitor electrode arranged on the third insulating layer; The fourth insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer are provided with via holes, and the via holes expose the active layer; the source electrode and the drain electrode arranged on the fourth insulating layer, the source electrode and the The drain electrodes are respectively connected with the active layer through via holes; the flat layer covering the aforementioned
  • the light emitting device 103 may include an anode, a pixel definition layer, an organic light emitting layer, and a cathode.
  • the anode is arranged on the flat layer, and is connected to the drain electrode of the driving transistor through the via hole opened on the flat layer;
  • the pixel definition layer is arranged on the anode and the flat layer, and a pixel opening is arranged on the pixel definition layer, and the pixel opening exposes the anode;
  • the organic The light-emitting layer is at least partially arranged in the pixel opening, and the organic light-emitting layer is connected to the anode;
  • the cathode is arranged on the organic light-emitting layer, and the cathode is connected to the organic light-emitting layer;
  • the encapsulation layer 104 may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of The organic material, the second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting device 103 .
  • the organic light emitting layer may include at least a hole injection layer, a hole transport layer, a light emitting layer and a hole blocking layer stacked on the anode.
  • the hole injection layers of all subpixels are a common layer connected together
  • the hole transport layers of all subpixels are a common layer connected together
  • the light emitting layers of adjacent subpixels may have a small amount of Overlapping, or possibly isolated, hole blocking layers are common layers that are joined together.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure.
  • FIG. 5 is an equivalent circuit diagram of a pixel driving circuit. As shown in FIG. 5, the pixel driving circuit may include 7 switching transistors (the first transistor T1 to the seventh transistor T7), 1 storage capacitor C and 8 signal lines (the data signal line DATA, the first scan signal line S1, The second scan signal line S2, the first initial signal line INIT1, the second initial signal line INIT2, the first power supply line VSS, the second power supply line VDD, and the light emitting signal line EM).
  • the control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the second scan signal line S2.
  • Node N2 is connected.
  • the control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the control electrode of the third transistor T3 is connected to the second node N2, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the control electrode of the fifth transistor T5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the second power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light emitting signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device.
  • the control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device.
  • the first end of the storage capacitor C is connected to the second power line VDD, and the second end of the storage capacitor C is connected to the second node N2.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.
  • the second pole of the light emitting device is connected to the first power supply line VSS, the signal of the first power supply line VSS is a low-level signal, and the signal of the second power supply line VDD is a continuous high-level signal.
  • the first scan signal line S1 is the scan signal line in the pixel driving circuit of the display row
  • the second scan signal line S2 is the scan signal line in the pixel driving circuit of the previous display row, that is, for the nth display row, the first scan signal
  • the line S1 is S(n)
  • the second scanning signal line S2 is S(n-1)
  • the second scanning signal line S2 of this display line is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display line
  • the signal lines can reduce the signal lines of the display panel and realize the narrow frame of the display panel.
  • the bezel area of the display substrate may be provided with a gate driving circuit (GOA), a test circuit (CT) and a multiplexing circuit (MUX).
  • the gate driving circuit may include a plurality of cascaded shift register units, each shift register unit is connected to at least one scan signal line of the display area, and is configured to connect to the at least one scan signal line of the display area Provides gate drive signals.
  • the test circuit may include a plurality of test units, each of which is connected to a plurality of data signal lines in the display area, and is configured to provide test data signals to the plurality of data signal lines in the display area.
  • the multiplexing circuit may include a plurality of multiplexing units, each of which is connected to a plurality of data signal lines in the display area, and is configured such that one signal source provides data signals for the plurality of data signal lines.
  • the specific form of the shift register unit is various, which is not limited in this disclosure.
  • the test circuit may include at least one test control signal line, a plurality of test data signal lines, and a plurality of test cells, each test cell being connected to the test control signal line and the test data signal line, and connected to the display area
  • the test unit is configured to provide (simultaneously or separately) the signals (data signals) of the test data signal lines to (simultaneously or separately) a plurality of data signal lines of the display area connected thereto according to the control of the test control signal lines , to detect and locate defective sub-pixels in the display area.
  • FIG. 6 is an equivalent circuit diagram of a test circuit.
  • the test circuit may include at least one test control signal line, n1 test data signal lines, and m1 test cells, at least one test cell in the m1 test cells includes n1 test transistors, and m1 and n1 are A positive integer greater than or equal to 2.
  • FIG. 6 illustrates by taking one test control signal line, three test data signal lines, and one test unit including three test transistors as an example. As shown in FIG. 6 , in the three test transistors 81 of the same test unit 80 , the control electrodes of the three test transistors 81 are all connected to the same test control signal line 82 .
  • the first poles of the three test transistors 81 are respectively connected to different test data signal lines, that is, the first pole of the first test transistor is connected to the first test data signal line 83-1, and the first pole of the second test transistor is connected to the first test data signal line 83-1.
  • Two test data signal lines 83-2, and the first electrode of the third test transistor is connected to the third test data signal line 83-3.
  • the second electrodes of the three test transistors 81 are respectively connected to different data signal lines DATA in the display area, that is, the second electrodes of the first test transistors are connected to one data signal line DATA, and the second electrodes of the second test transistors are connected to another data signal line DATA.
  • the data signal line DATA, and the second electrode of the third test transistor is connected to another data signal line DATA.
  • the conduction of the three test transistors 81 in the test unit 80 can be controlled by the test control signal line 82, and the signals of different test data signal lines can be controlled to be written into different data signal lines.
  • the control device provides a conduction signal to the test control signal line 82, and respectively provides the required test data signal to the plurality of test data signal lines, so that the plurality of data signal lines in the display area can obtain the test data signal, so as to realize detection.
  • the test control signal lines and the test data signal lines may be arranged in the frame area, and may be closed traces in a ring shape surrounding the display area.
  • the number of data signal lines may be equal to m1*n1
  • the sub-pixels connected to each data signal line have the same color
  • the same test data signal is provided to the data signal lines corresponding to sub-pixels of the same color during testing, so that the These sub-pixels are displayed in the same manner, and it is determined by the color of the display screen whether there are defective sub-pixels, and positioning the defective sub-pixels.
  • the multiplexing circuit may include multiple multiplexing control signal lines, multiple multiplexing data signal lines, and multiple multiplexing units, each multiplexing unit connecting multiple data signal lines of the display area , the multiplexing unit is configured to provide a signal (data signal) of one multiplexed data signal line to a plurality of data signal lines connected thereto in a time-division according to the control of the plurality of multiplexing control signal lines.
  • FIG. 7 is an equivalent circuit diagram of a multiplexing circuit.
  • the multiplexing circuit may include n2 multiplexing control signal lines, at least one multiplexing data signal line, and m2 multiplexing units 90, and at least one multiplexing unit in the m2 multiplexing units includes n2 multiplexing transistors, m2 and n2 are positive integers greater than or equal to 2.
  • FIG. 7 illustrates by taking six multiplexing control signal lines, two multiplexing data signal lines, and one multiplexing unit including six multiplexing transistors as an example. As shown in FIG.
  • the control electrodes of the six multiplexing transistors 91 are respectively connected to different multiplexing control signal lines, that is, the control of the first multiplexing transistor
  • the electrode is connected to the first multiplexing control signal line 92-1
  • the control electrode of the second multiplexing transistor is connected to the second multiplexing control signal line 92-2
  • the control electrode of the third multiplexing transistor is connected to the third multiplexing control signal.
  • Line 92-3 the control electrode of the fourth multiplexing transistor is connected to the fourth multiplexing control signal line 92-4
  • the control electrode of the fifth multiplexing transistor is connected to the fifth multiplexing control signal line 92-6
  • the sixth multiplexing control signal line 92-6 is connected to different multiplexing control signal lines
  • the control electrode of the multiplexing transistor is connected to the sixth multiplexing control signal line 92-6.
  • the first poles of the six multiplexing transistors 91 are all connected to the same multiplexed data signal line, that is, the first poles of the first transistor to the sixth multiplexing transistor in the first multiplexing unit 90 are all connected to the first multiplexing transistor.
  • the data signal line 93-1 With the data signal line 93-1, the first electrodes of the first transistor to the sixth multiplexing transistor in the second multiplexing unit 90 are all connected to the second multiplexed data signal line 93-2.
  • the second poles of the six multiplexing transistors 91 are respectively connected to different data signal lines DATA in the display area, that is, the second pole of the first multiplexing transistor is connected to a data signal line DATA in the display area, and the second multiplexing transistor is connected to a data signal line DATA in the display area.
  • the second pole of is connected to another data signal line DATA... in the display area.
  • the turn-on signal is provided to the six multiplexing control signal lines by the control device in a time-division, so that the six multiplexing transistors 91 in each multiplexing unit 90 are turned on in a time-division, and when any multiplexing transistor 91 is turned on
  • the multiplexed data signal line provides the data signal required by the data signal line connected to the turned-on multiplexing transistor 91, and the data signal line writes the data signal into the corresponding sub-pixel.
  • the number of data signal lines may be equal to m2*n2.
  • one signal source for example, one pin of the driver chip
  • the multiplexing unit 90 may include three multiplexing transistors 91 to control three data signal lines (one to three).
  • the display substrate may include a display area and a frame area around the display area;
  • the frame area includes a first frame and a second frame oppositely disposed in a first direction, and a frame area in the second direction
  • the third frame and the fourth frame are oppositely arranged on the upper side, the first corner connecting the first frame and the third frame, the second corner connecting the second frame and the third frame, and the first frame and the third corner of the fourth frame and the fourth corner connecting the second frame and the fourth frame, at least one of the first to fourth corners is an arc-shaped corner, the first One direction is the extension direction of the scan signal lines in the display area, the second direction is the extension direction of the data signal lines in the display area; at least one of the first to fourth corners is provided with a A first wiring and a second wiring, a plurality of first rectangles are enclosed between the first wiring and the second wiring, and a plurality of shift register units are respectively located in the plurality of first rectangles.
  • At least one of the first to fourth corners is further provided with a third wiring, and the third wiring is located between the display area and the second wiring , a plurality of second rectangles are formed between the third wiring and the second wiring.
  • the second rectangle is a rectangle, and the extending direction of the long side of the second rectangle is parallel to the first direction.
  • At least one of the first and second corners is provided with a plurality of first test units, the plurality of first test units are respectively located in the plurality of second rectangles
  • At least one first test unit is disposed in the same second rectangle in at least one of the first corner and the second corner.
  • At least two shift register units are provided in the same first rectangle in at least one of the first corner and the second corner.
  • a plurality of multiplexing units are disposed in at least one of the third and fourth corners, and the multiplexing units are respectively located in the plurality of second rectangles.
  • At least one multiplexing unit is provided in the same second rectangle in at least one of the third and fourth corners.
  • At least one shift register unit is provided in the same first rectangle in at least one of the third corner portion and the fourth corner portion.
  • the data processing circuit may include a first test circuit disposed in at least one of the first and second corners, the first test circuit including A plurality of first test units, the first test units are connected to at least one data signal line of the display area, and are configured to provide test data signals to the data signal line.
  • the third frame is provided with a second test circuit, the second test circuit includes a plurality of second test units, the second test units are connected to at least one data signal line of the display area, and are configured to be connected to all the The data signal lines provide test data signals.
  • the height of the first test unit is smaller than the height of the second test unit, and the height is the dimension in the second direction.
  • the exemplary embodiment of the present disclosure arranges the multiplexing unit of the multiplexing circuit in the third corner 213 and the fourth corner 213 and the fourth corner 203 by disposing the detection circuits in the first corner 211 , the second corner 212 and the third frame 203 respectively.
  • different circuit units are uniformly distributed, which is beneficial to reduce the width of the frame area and realize a narrow frame of the display device.
  • the test circuit may be disposed in the first corner portion 211 (or the second corner portion 212 ) and the third bezel 203 in the bezel area 200 and disposed in the first corner portion 211 (or the second corner portion 211 )
  • the structure of the test circuit in the part 212 ) is different from that of the test circuit provided in the third frame 203 .
  • FIG. 8 is a layout structure diagram of a test circuit according to an exemplary embodiment of the present disclosure.
  • the test circuit may include a first test circuit CT1 and a second test circuit CT2, and the first test circuit CT1 may be disposed in the first corner portion 211, or disposed in the second corner
  • the second test circuit CT2 can be disposed in the third frame 203, and the structure of the first test circuit CT1 is different from that of the second test circuit CT2. .
  • the first test circuit CT1 includes a plurality of first test units
  • the second test circuit CT2 includes a plurality of second test units
  • the structure of the first test unit is different from that of the second test unit including at least the first test unit
  • the height of the unit is smaller than the height of the second test unit, and the height is the dimension of the second direction Y.
  • FIG. 9 is a schematic structural diagram of a second test unit according to an exemplary embodiment of the present disclosure, illustrating that the second test unit includes three test transistors.
  • the second test unit in a plane parallel to the display substrate, the second test unit includes three test transistors, and the three test transistors are arranged in sequence along the second direction Y, and are arranged staggered in the first direction X.
  • the source electrode (first electrode) of the first test transistor TC1 is connected to the first test data signal line 27 through the first test connection line 24, and the drain electrode (second electrode) of the first test transistor is connected to the display through the first test data line 23. area of a data signal line.
  • the source electrode (first electrode) of the second test transistor TC2 is connected to the second test data signal line 37 through the second test connection line 34 , and the drain electrode (second electrode) of the second test transistor is connected to the display through the second test data line 33 Another data signal line in the area.
  • the source electrode (first electrode) of the third test transistor TC3 is connected to the third test data signal line 47 through the third test connection line 44 , and the drain electrode (second electrode) of the third test transistor TC3 is connected to the display through the third test data line 43 Another data signal line in the area.
  • the first test gate electrode of the first test transistor TC1, the second test gate electrode of the second test transistor TC2, and the third test gate electrode 42 of the third test transistor TC3 may be an integral structure connected to each other and connected to the test control signal line. 28.
  • the second test unit may be rectangular, the height of the second test unit (the second height H2 ) is greater than the width of the second test unit (the second width M2 ), and the second height H2 may be about the third 2 times to 3 times the width M2.
  • the width is the dimension in the first direction X
  • the height is the dimension in the second direction Y.
  • the width M2 of the second test unit may be about 44 ⁇ m to 66 ⁇ m, and the height H2 of the second test unit may be about 110 ⁇ m to 170 ⁇ m.
  • the width M2 of the second test unit may be about 54.92 ⁇ m, and the second height H2 may be about 141.6 ⁇ m.
  • the second test unit may include:
  • test active layers arranged on the first insulating layer, the plurality of test active layers are arranged at intervals along the second direction, and are arranged staggered in the first direction;
  • the active layer is adjacent to one side of the display area, and the second ends of the plurality of test data lines extend toward the direction of the display area;
  • a third insulating layer covering the plurality of test gate electrodes and a plurality of test data lines, and a plurality of test connection lines disposed on the third insulating layer, the plurality of test connection lines along the first The directions are arranged at intervals, the first ends of the plurality of test connection lines are respectively located on the side of the plurality of test active layers away from the display area, and the second ends of the plurality of test connection lines are located on the side away from the display area. extending in a direction, the distances between the second ends of the plurality of test connection lines and the edge of the display area are different;
  • a fourth insulating layer covering the plurality of test connection wires, and a plurality of via holes are arranged thereon;
  • test source electrodes are respectively connected to the corresponding test active layers and the first ends of the corresponding test connection lines through vias, The second end of the test connection line is connected with the corresponding test data signal line through the via hole; the test drain electrode is respectively connected with the corresponding test active layer and the first end of the corresponding test data line through the via hole, so The second end of the test data line is connected to the data signal line of the display area; the plurality of test gate electrodes are connected to the test control signal line through via holes.
  • the following is an exemplary illustration through the preparation process of the second test unit.
  • the "patterning process" mentioned in this disclosure includes photoresist coating, mask exposure, development, etching, stripping photoresist and other treatments, for organic materials, including Processes such as coating organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spraying, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings are not limited in the present disclosure.
  • “Film” refers to a thin film made of a material on a substrate by deposition, coating or other processes.
  • the "thin film” may also be referred to as a "layer”. If the "thin film” needs a patterning process in the whole manufacturing process, it is called a "thin film” before the patterning process, and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of A includes the orthographic projection of B
  • the orthographic projection of B is located within the range of the orthographic projection of A
  • the boundary of the orthographic projection of B falls within the orthographic projection of A or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.
  • the preparation process of the second test unit may include the following operations.
  • a semiconductor layer pattern is formed on a substrate.
  • forming the semiconductor layer pattern on the substrate may include: sequentially depositing a first insulating film and a semiconductor film on the substrate, and patterning the semiconductor film through a patterning process to form a first insulating layer covering the entire substrate , and a semiconductor layer pattern disposed on the first insulating layer, the semiconductor layer pattern including at least a first test active layer 21 , a second test active layer 31 and a third test active layer 41 , as shown in FIG. 10 .
  • the substrate may be a flexible substrate, or a rigid substrate.
  • the three test active layers are arranged at intervals along the second direction Y, and are dislocated in the first direction X, and the widths of the three test active layers in the first direction X may be about 20 ⁇ m to 25 ⁇ m, The height of the second direction Y may be about 13 ⁇ m to 19 ⁇ m. In an exemplary embodiment, each test active layer may have a width of about 22.9 ⁇ m and a height of about 16 ⁇ m.
  • forming the first metal layer pattern may include: sequentially depositing a second insulating film and a first metal film on the substrate on which the aforementioned pattern is formed, and patterning the first metal film through a patterning process to form a cover A second insulating layer of the semiconductor layer pattern, and a first metal layer pattern disposed on the second insulating layer, the first metal layer pattern at least includes a first test gate electrode 22, a second test gate electrode 32, and a third test gate electrode 42.
  • the first test data line 23, the second test data line 33 and the third test data line 43 as shown in FIG. 11 .
  • the three test gate electrodes are arranged at intervals along the second direction Y, and are staggered in the first direction X, and the width of the three test gate electrodes in the first direction X may be about 8 ⁇ m to 11 ⁇ m. In an exemplary embodiment, the width of each test gate electrode may be about 9.3 ⁇ m.
  • the three test data lines are arranged at intervals along the first direction X, the first ends of the three test data lines are respectively located on one side of the three test active layers adjacent to the display area, and the three test data lines The second end of the extends toward the direction of the display area (the second direction Y).
  • the first test gate electrode 22, the second test gate electrode 32, and the third test gate electrode 42 may be an interconnected integral structure.
  • the first test gate electrode 22 , the second test gate electrode 32 and the third test gate electrode 42 are configured to connect the test control signal lines, the first test data line 23 , the second test data line 33 and the third test data line formed subsequently.
  • 43 is configured to connect the data signal lines of the display area, respectively.
  • forming the second metal layer pattern may include: sequentially depositing a third insulating film and a second metal film on the substrate on which the foregoing pattern is formed, and patterning the second metal film through a patterning process to form a cover
  • the third insulating layer of the first metal layer pattern, and the second metal layer pattern disposed on the third insulating layer, the second metal layer pattern at least including the first test connection line 24, the second test connection line 34 and the third test Connection line 44, as shown in FIG. 12 .
  • the first ends of the three test connection lines are respectively located on one side of the three test active layers away from the display area, the second ends of the three test connection lines extend in a direction away from the display area, and the three test connection lines extend away from the display area. The distance between the second end of the test connection line and the edge of the display area is different.
  • the first test connection line 24 , the second test connection line 34 and the third test connection line 44 are configured to connect the test data signal lines formed subsequently, respectively.
  • a fourth insulating layer pattern is formed.
  • forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the foregoing pattern is formed, patterning the fourth insulating film through a patterning process, and forming a layer covering the second metal layer pattern.
  • the fourth insulating layer has a plurality of via holes opened on the fourth insulating layer, as shown in FIG. 13 .
  • the plurality of via holes on the fourth insulating layer may include: a first test on a side of the first test gate electrode 22 adjacent to the first test data line 23 and exposing the first test active layer 21
  • test via holes V4 a fifth test via hole V5 located on the side of the third test gate electrode 42 adjacent to the third test data line 43 and exposing the third test active layer 41, and located on the third test gate electrode 42 adjacent to the third test via hole V5
  • the sixth test via V6 on the side of the test connection line 44 and exposing the third test active layer 41 is located at the first end of the first test data line 23 adjacent to the first test active layer 21 and exposes the first test data
  • the data line 43 is adjacent to the first end of the third test active layer 41 and exposes the ninth test via V9 of the third test data line 43 and the first test connection line 24 adjacent to the first test active layer 21
  • the tenth test via V10 which is located at the end of the second test connection line 34 and exposes the first test connection line 24 , and the eleventh
  • the fourteenth test via hole V14 of the test connection line 34 the fifteenth test via hole V12 located at the second end of the third test connection line 44 away from the third test active layer 41 and exposing the third test connection line 44 ,
  • the sixteenth test via hole V16 is located at the second end of the first test gate electrode 22 away from the display area and exposes the first test gate electrode 22 .
  • a third metal layer pattern is formed.
  • forming the third metal layer pattern may include: depositing a third metal thin film on the substrate on which the aforementioned pattern is formed, patterning the third metal thin film through a patterning process, and forming a third metal thin film on the fourth insulating layer
  • the third metal layer pattern at least includes: a first test source electrode 25, a first test drain electrode 26, a second test source electrode 35, a second test drain electrode 36, a third test source electrode 45, a third test source electrode 45, and a third test source electrode 45.
  • the test drain electrode 46 , the first test data signal line 27 , the second test data signal line 37 , the first test data signal line 47 and the test control signal line 28 are shown in FIG. 14 .
  • one end of the first test drain electrode 26 is connected to the first test active layer 21 through the first test via V1, and the other end is connected to the first test data line 23 through the seventh test via V7.
  • One end is connected, and the second end of the first test data line 23 is connected with a data signal line in the display area.
  • One end of the first test source electrode 25 is connected to the first test active layer 21 through the second test via V2, and the other end is connected to the first end of the first test connection line 24 through the tenth test via V10.
  • the first test The second end of the connection line 24 is connected to the first test data signal line 27 through the thirteenth test via V13.
  • One end of the second test drain electrode 36 is connected to the second test active layer 31 through the third test via V3, and the other end is connected to the first end of the second test data line 33 through the eighth test via V8.
  • the second test The second end of the data line 33 is connected to a data signal line of the display area.
  • One end of the second test source electrode 35 is connected to the second test active layer 31 through the fourth test via V4, and the other end is connected to the first end of the second test connection line 34 through the eleventh test via V11.
  • the second end of the test connection line 34 is connected to the second test data signal line 37 through the fourteenth test via V14.
  • One end of the third test drain electrode 46 is connected to the third test active layer 41 through the fifth test via V5, and the other end is connected to the first end of the third test data line 43 through the ninth test via V9.
  • the third test The second end of the data line 43 is connected to a data signal line of the display area.
  • One end of the third test source electrode 45 is connected to the third test active layer 41 through the sixth test via V6, and the other end is connected to the first end of the third test connection line 44 through the twelfth test via V12.
  • the second end of the test connection line 44 is connected to the third test data signal line 47 through the fifteenth test via V15.
  • the first test gate electrode 22 is connected to the test control signal line 28 through the sixteenth test via hole V16.
  • a distance between a side edge of the first test source electrode 25 away from the first test active layer 21 and a side edge of the first test drain electrode 26 away from the first test active layer 21 may be about 20 ⁇ m To 25 ⁇ m
  • the distance between the side edge of the second test source electrode 35 away from the second test active layer 31 and the side edge of the second test drain electrode 36 away from the second test active layer 31 may be about 20 ⁇ m to 25 ⁇ m.
  • the distance between the side edge of the three test source electrodes 45 away from the third test active layer 41 and the side edge of the third test drain electrode 46 away from the third test active layer 41 may be about 20 ⁇ m to 25 ⁇ m.
  • the distance between the side edge of each test source electrode and the side edge of the test drain electrode may be about 22.9 ⁇ m.
  • the first test active layer 21, the first test gate electrode 22, the first test source electrode 25 and the first test drain electrode 26 constitute the first test transistor TC1; the second test active layer 31, The second test gate electrode 32, the second test source electrode 35 and the second test drain electrode 36 constitute the second test transistor TC2; the third test active layer 41, the third test gate electrode 42, the third test source electrode 45 and the The three test drain electrodes 46 form a third test transistor TC3; the first test transistor TC1, the second test transistor TC2 and the third test transistor TC3 form a test unit.
  • the first test gate electrode 22 , the second test gate electrode 32 and the third test gate electrode 42 are all connected to the same test control signal line 28 , the first test drain electrode 26 , the second test drain electrode 36 and the third test drain electrode 46
  • the first test data line 23, the second test data line 33 and the third test data line 43 are respectively connected to the data signal lines in different display areas, the first test source electrode 25, the second test source electrode 35 and the third test source electrode. 45 are respectively connected to the first test data signal line 27 , the second test data signal line 37 and the first test data signal line 47 through the first test connection line 24 , the second test connection line 34 and the third test connection line 44 .
  • the control device provides a conducting signal to the test control signal line 28 to control the first test transistor TC1, the second test transistor TC2 and the third test transistor TC3 to conduct, and the first test data signal line 27, the second test transistor TC2 and the third test transistor TC3 are turned on.
  • the test data signal provided by the test data signal line 37 and the first test data signal line 47 is transmitted to a plurality of data signal lines in the display area.
  • test connection lines may be provided in the first metal layer
  • test data lines may be provided in the second metal layer
  • test gate electrode, the test connection line and the test data line may be disposed in the same layer and formed through the same patterning process.
  • the second test unit may also be provided with other electrodes, leads or film layers, which are not limited in this disclosure.
  • FIG. 15 is a schematic structural diagram of a first test unit according to an exemplary embodiment of the present disclosure, illustrating that the first test unit includes three test transistors.
  • the first test unit in a plane parallel to the display substrate, the first test unit includes three test transistors, and the three test transistors are arranged in sequence along the first direction X and flush in the second direction Y.
  • the source electrode (first electrode) of the first test transistor TC1 is connected to the first test data signal line 27 through the first test connection line 24, and the drain electrode (second electrode) of the first test transistor is connected to the display through the first test data line 23. area of a data signal line.
  • the source electrode (first electrode) of the second test transistor TC2 is connected to the second test data signal line 37 through the second test connection line 34 , and the drain electrode (second electrode) of the second test transistor is connected to the display through the second test data line 33 Another data signal line in the area.
  • the source electrode (first electrode) of the third test transistor TC3 is connected to the third test data signal line 47 through the third test connection line 44 , and the drain electrode (second electrode) of the third test transistor TC3 is connected to the display through the third test data line 43 Another data signal line in the area.
  • the test gate electrode of the first test transistor TC1 , the test gate electrode of the second test transistor TC2 and the test gate electrode 42 of the third test transistor TC3 are all connected to the same test control signal line 28 .
  • the first test unit may be rectangular, the height of the first test unit (first height H1 ) may be greater than the width of the first test unit (first width M1 ), or the first height H1 may be smaller than or equal to the first width K1, the first height H1 may be about 0.9 times to 1.3 times the first width K1.
  • the height H2 of the second test unit may be about 1.5 times to 4 times the height H1 of the first test unit.
  • the width M1 of the first test unit may be about 60 ⁇ m to 90 ⁇ m, and the height H1 of the first test unit may be about 70 ⁇ m to 100 ⁇ m.
  • the first width M1 of the first test unit may be about 75.7 ⁇ m, and the height H1 of the first test unit may be about 84.78 ⁇ m.
  • the first test unit may include
  • test active layers disposed on the first insulating layer, the plurality of test active layers are spaced along the first direction and are flush in the second direction;
  • a second insulating layer covering the plurality of test active layers, and a plurality of test gate electrodes and a plurality of test data lines disposed on the second insulating layer; the plurality of test gate electrodes are arranged along the first The plurality of test data lines are arranged at intervals in one direction and are flush in the second direction; the plurality of test data lines are arranged at intervals along the first direction, and the first ends of the plurality of test data lines are respectively located in the plurality of test data lines.
  • the active layer is adjacent to one side of the display area, and the second ends of the plurality of test data lines extend toward the direction of the display area;
  • the plurality of test connection lines are along the first The directions are arranged at intervals, the first ends of the plurality of test connection lines are respectively located on the side of the plurality of test active layers away from the display area, and the second ends of the plurality of test connection lines are located on the side away from the display area. extending in a direction, the distances between the second ends of the plurality of test connection lines and the edge of the display area are different;
  • a fourth insulating layer covering the plurality of test connection wires, and a plurality of via holes are arranged thereon;
  • test source electrodes are respectively connected to the corresponding test active layers and the first ends of the corresponding test connection lines through vias, The second end of the test connection line is connected with the corresponding test data signal line through the via hole; the test drain electrode is respectively connected with the corresponding test active layer and the first end of the corresponding test data line through the via hole, so The second end of the test data line is connected to the data signal line of the display area; the plurality of test gate electrodes are connected to the test control signal line through via holes.
  • the manufacturing process of the first test unit may include the following operations.
  • a semiconductor layer pattern is formed on the substrate.
  • forming the semiconductor layer pattern on the substrate may include: sequentially depositing a first insulating film and a semiconductor film on the substrate, and patterning the semiconductor film through a patterning process to form a first insulating layer covering the entire substrate , and a semiconductor layer pattern disposed on the first insulating layer, the semiconductor layer pattern includes at least a first test active layer 21 , a second test active layer 31 and a third test active layer 41 , as shown in FIG. 16 .
  • the three test active layers in the second test unit are arranged at intervals along the second direction Y, and are staggered in the first direction X, while the three test active layers in the first test unit
  • the three test active layers are arranged at intervals along the first direction X, and the three test active layers are flush in the second direction Y, so that the size of the first test circuit in the second direction Y can be effectively reduced.
  • the width of the first direction X of the three test active layers may be about 20 ⁇ m to 25 ⁇ m, and the height of the second direction Y may be about 13 ⁇ m to 19 ⁇ m.
  • each test active layer may have a width of about 22.9 ⁇ m and a height of about 16 ⁇ m.
  • the width and height of the three test active layers in the first test unit and the second test unit and the spacing between adjacent test active layers may be the same, so as to ensure the consistency of the test effects.
  • a first metal layer pattern is formed.
  • forming the first metal layer pattern may include: sequentially depositing a second insulating film and a first metal film on the substrate on which the aforementioned pattern is formed, and patterning the first metal film through a patterning process to form a cover A second insulating layer of the semiconductor layer pattern, and a first metal layer pattern disposed on the second insulating layer, the first metal layer pattern at least includes a first test gate electrode 22, a second test gate electrode 32, and a third test gate electrode 42.
  • the first test data line 23, the second test data line 33 and the third test data line 43 as shown in FIG. 17 .
  • the three test gate electrodes in the second test unit are arranged at intervals along the second direction Y, and are staggered in the first direction X, while the three test gate electrodes in the first test unit are arranged along the The three test gate electrodes are arranged at intervals along the first direction X, and the three test gate electrodes are flush in the second direction Y, so the size of the first test circuit in the second direction Y can be effectively reduced.
  • the widths of the three test gate electrodes in the first direction X may be about 8 ⁇ m to 11 ⁇ m. In an exemplary embodiment, the width of each test gate electrode may be about 9.3 ⁇ m.
  • the widths of the three test gate electrodes in the first test unit and the second test unit and the spacing between adjacent test gate electrodes may be the same, so as to ensure the consistency of the test effects.
  • the three test data lines are arranged at intervals along the first direction X, the first ends of the three test data lines are respectively located on one side of the three test active layers adjacent to the display area, and the three test data lines The second ends of the three test data lines extend in the direction of the display area, and the second ends of the three test data lines are flush in the second direction Y.
  • a second metal layer pattern is formed.
  • forming the second metal layer pattern may include: sequentially depositing a third insulating film and a second metal film on the substrate on which the foregoing pattern is formed, and patterning the second metal film through a patterning process to form a cover The third insulating layer of the first metal layer pattern, and the second metal layer pattern disposed on the third insulating layer, the second metal layer pattern at least including the first test connection line 24, the second test connection line 34 and the third test Connection line 44, as shown in FIG. 18 .
  • the first ends of the three test connection lines are respectively located on one side of the three test active layers away from the display area, the second ends of the three test connection lines extend in a direction away from the display area, and the three test connection lines extend away from the display area.
  • the distance between the second end of the test connection line and the edge of the display area is different.
  • the first ends of the three test connection lines in the second test unit are spaced along the second direction Y, and the first ends of the three test connection lines in the first test unit are in the second test unit.
  • the two directions Y are flush, so the size of the first test circuit in the second direction Y can be effectively reduced.
  • a fourth insulating layer pattern is formed.
  • forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the foregoing pattern is formed, patterning the fourth insulating film through a patterning process, and forming a layer covering the second metal layer pattern.
  • the fourth insulating layer has a plurality of via holes opened on the fourth insulating layer, as shown in FIG. 19 .
  • the plurality of via holes on the fourth insulating layer may include: a first test on a side of the first test gate electrode 22 adjacent to the first test data line 23 and exposing the first test active layer 21
  • test via holes V4 a fifth test via hole V5 located on the side of the third test gate electrode 42 adjacent to the third test data line 43 and exposing the third test active layer 41, and located on the third test gate electrode 42 adjacent to the third test via hole V5
  • the sixth test via V6 on the side of the test connection line 44 and exposing the third test active layer 41 is located at the first end of the first test data line 23 adjacent to the first test active layer 21 and exposes the first test data
  • the seventh test via V7 of the line 23 is located in the second test data line 33 adjacent to the first end of the second test active layer 31 and the eighth test via V8 that exposes the second test data line 33 is located in the third test via V8
  • the data line 43 is adjacent to the first end of the third test active layer 41 and exposes the ninth test via V9 of the third test data line 43 and the first test connection line 24 adjacent to the first test active layer 21
  • the tenth test via V10 which is located at the end of the second test connection line 34 and exposes the first test connection line 24
  • the three test gate electrodes in the second test circuit are an integral structure connected to each other, only one test via hole is needed to realize the connection between the test control signal line and the three test gate electrodes. Since the three test gate electrodes in the first test circuit are isolated from each other, it is necessary to set the sixteenth test via V16, the seventeenth test via V17 and the eighteenth test via V18 to realize the test control signal line and the The three test gate electrodes are connected.
  • a third metal layer pattern is formed.
  • forming the third metal layer pattern may include: depositing a third metal thin film on the substrate on which the aforementioned pattern is formed, patterning the third metal thin film through a patterning process, and forming a third metal thin film on the fourth insulating layer
  • the third metal layer pattern at least includes: a first test source electrode 25, a first test drain electrode 26, a second test source electrode 35, a second test drain electrode 36, a third test source electrode 45, a third test source electrode 45, and a third test source electrode 45.
  • the test drain electrode 46 , the first test data signal line 27 , the second test data signal line 37 , the first test data signal line 47 and the test control signal line 28 are shown in FIG. 20 .
  • one end of the first test drain electrode 26 is connected to the first test active layer 21 through the first test via V1, and the other end is connected to the first test data line 23 through the seventh test via V7.
  • One end is connected, and the second end of the first test data line 23 is connected with a data signal line in the display area.
  • One end of the first test source electrode 25 is connected to the first test active layer 21 through the second test via V2, and the other end is connected to the first end of the first test connection line 24 through the tenth test via V10.
  • the first test The second end of the connection line 24 is connected to the first test data signal line 27 through the thirteenth test via V13.
  • One end of the second test drain electrode 36 is connected to the second test active layer 31 through the third test via V3, and the other end is connected to the first end of the second test data line 33 through the eighth test via V8.
  • the second test The second end of the data line 33 is connected to a data signal line of the display area.
  • One end of the second test source electrode 35 is connected to the second test active layer 31 through the fourth test via V4, and the other end is connected to the first end of the second test connection line 34 through the eleventh test via V11.
  • the second end of the test connection line 34 is connected to the second test data signal line 37 through the fourteenth test via V14.
  • One end of the third test drain electrode 46 is connected to the third test active layer 41 through the fifth test via V5, and the other end is connected to the first end of the third test data line 43 through the ninth test via V9.
  • the third test The second end of the data line 43 is connected to a data signal line of the display area.
  • One end of the third test source electrode 45 is connected to the third test active layer 41 through the sixth test via V6, and the other end is connected to the first end of the third test connection line 44 through the twelfth test via V12.
  • the second end of the test connection line 44 is connected to the third test data signal line 47 through the fifteenth test via V15.
  • the first test gate electrode 22 is connected to the test control signal line 28 through the sixteenth test via V16
  • the second test gate electrode 32 is connected to the test control signal line 28 through the seventeenth test via V17
  • the third test gate electrode 42 It is connected to the test control signal line 28 through the eighteenth test via V18.
  • a distance between a side edge of the first test source electrode 25 away from the first test active layer 21 and a side edge of the first test drain electrode 26 away from the first test active layer 21 may be about 20 ⁇ m To 25 ⁇ m
  • the distance between the side edge of the second test source electrode 35 away from the second test active layer 31 and the side edge of the second test drain electrode 36 away from the second test active layer 31 may be about 20 ⁇ m to 25 ⁇ m
  • the distance between the side edge of the three test source electrodes 45 away from the third test active layer 41 and the side edge of the third test drain electrode 46 away from the third test active layer 41 may be about 20 ⁇ m to 25 ⁇ m.
  • the distance between the side edge of the test source electrode and the side edge of the test drain electrode may be about 22.9 ⁇ m.
  • the sizes of the three test source electrodes and the three test drain electrodes in the first test unit and the second test unit may be the same, so as to ensure the consistency of the test effects.
  • the first test active layer 21, the first test gate electrode 22, the first test source electrode 25 and the first test drain electrode 26 constitute the first test transistor TC1; the second test active layer 31, The second test gate electrode 32, the second test source electrode 35 and the second test drain electrode 36 constitute the second test transistor TC2; the third test active layer 41, the third test gate electrode 42, the third test source electrode 45 and the The three test drain electrodes 46 form a third test transistor TC3; the first test transistor TC1, the second test transistor TC2 and the third test transistor TC3 form a test unit.
  • the first test gate electrode 22 , the second test gate electrode 32 and the third test gate electrode 42 are all connected to the same test control signal line 28 , the first test drain electrode 26 , the second test drain electrode 36 and the third test drain electrode 46
  • the first test data line 23, the second test data line 33 and the third test data line 43 are respectively connected to the data signal lines in different display areas, the first test source electrode 25, the second test source electrode 35 and the third test source electrode. 45 are respectively connected to the first test data signal line 27 , the second test data signal line 37 and the first test data signal line 47 through the first test connection line 24 , the second test connection line 34 and the third test connection line 44 .
  • the control device provides a conducting signal to the test control signal line 28 to control the first test transistor TC1, the second test transistor TC2 and the third test transistor TC3 to conduct, and the first test data signal line 27, the second test transistor TC2 and the third test transistor TC3 are turned on.
  • the test data signal provided by the test data signal line 37 and the first test data signal line 47 is transmitted to a plurality of data signal lines in the display area.
  • the structure of the first test circuit and the preparation process thereof shown in the present disclosure are merely exemplary descriptions.
  • the corresponding structure may be changed and patterning processes may be added or decreased according to actual needs.
  • the test connection lines may be provided in the first metal layer
  • the test data lines may be provided in the second metal layer.
  • the test gate electrode, the test connection line and the test data line may be disposed in the same layer and formed through the same patterning process.
  • the first test circuit may also be provided with other electrodes, leads or film layers, which are not limited in this disclosure.
  • the first test unit and the second test unit may be simultaneously formed through the same preparation process.
  • the semiconductor layer pattern of the first test unit and the semiconductor layer pattern of the second test unit are arranged in the same layer and formed by the same patterning process, and the first metal layer pattern of the first test unit and the first metal layer pattern of the second test unit are the same.
  • the second metal layer pattern of the first test unit and the second metal layer pattern of the second test unit are arranged in the same layer and formed by the same patterning process, and the fourth insulating layer of the first test unit is The layer via pattern and the fourth insulating layer via pattern of the second test unit are arranged in the same layer and formed by the same patterning process, and the third metal layer pattern of the first test unit and the third metal layer pattern of the second test unit are the same.
  • the layers are arranged and formed through the same patterning process, which is not limited in the present disclosure.
  • FIG. 21 is a layout structure diagram of a first test unit according to an exemplary embodiment of the present disclosure.
  • a rectangular display substrate with rounded corners includes a display area and a frame area, the display area includes a plurality of sub-pixels P arranged in a matrix, and the arc-shaped first corner in the frame area
  • a test circuit (CT), a gate drive circuit (GOA) and corresponding signal lines are provided.
  • the test circuit is a first test circuit
  • the plurality of test units 80 included in the test circuit are the first test units, and each test unit 80 is respectively connected to the test control signal line, the test data signal line and the signal line of the display area.
  • the data signal lines are connected, and the test unit 80 is configured to provide test data signals to a plurality of data signal lines in the display area.
  • the gate driving circuit may include a plurality of cascaded shift register units 110, each shift register unit 110 is respectively connected to the initial signal line, the clock signal line and the scan signal line of the display area, and the shift register unit 110 is configured to At least one scan signal line of the display area provides a gate driving signal.
  • the circuit structure of the second corner of the bezel region and the circuit structure of the first corner region may be the same.
  • the signal lines of the first corner portion 211 are routed in a stepped manner, and the test unit 80 and the shift register unit 110 are respectively disposed on different steps.
  • the signal line includes a first line, a second line and a third line.
  • the third line is located between the display area and the second line, and the second line is located between the first line and the third line.
  • a plurality of first rectangles are enclosed between the first wiring and the second wiring, a plurality of shift register units 110 are respectively located in the plurality of first rectangles, and a plurality of first rectangles are enclosed between the second wiring and the third wiring
  • the plurality of test units 80 are respectively located in the plurality of second rectangles.
  • the first traces may include gate signal lines 121 of stepped traces
  • the second traces may include test signal lines 122 of stepped traces
  • the third traces may include stepped traces of The power signal line 123, the minimum distance between the power signal line 123 and the edge of the display area is smaller than the minimum distance between the test signal line 122 and the edge of the display area, and the minimum distance between the test signal line 122 and the edge of the display area is smaller than the distance between the gate signal line 121 and the edge of the display area. shortest distance.
  • a plurality of first rectangles are enclosed between the gate signal lines 121 of the stepped wiring and the test signal lines 122 of the stepped wiring, and the plurality of shift register units 110 are arranged in the plurality of first rectangles in a stepped arrangement, respectively. , that is, a plurality of shift register units 110 are respectively disposed on a plurality of steps formed by the test signal lines 122 .
  • a plurality of second rectangles are formed between the test signal lines 122 of the stepped wiring and the power signal lines 123 of the stepped wiring, and the plurality of test units 80 are respectively arranged in the plurality of second rectangles in a stepped arrangement, that is, The plurality of shift register units 110 are respectively disposed on the plurality of steps formed by the power signal lines 123 .
  • the second rectangle is a rectangle in which the first direction X is the long side and the second direction Y is the short side, that is, the extending direction of the long side of the second rectangle is parallel to the first direction X.
  • the gate signal lines 121 , the test signal lines 122 and the power signal lines 123 may each include a plurality of first horizontal line groups and a plurality of first horizontal line groups and a plurality of first horizontal line groups arranged in sequence along the edge of the display area in the second direction Y
  • a vertical line group the first horizontal line group includes a plurality of first horizontal lines extending in the opposite direction of the first direction X
  • the first vertical line group includes a plurality of first vertical lines extending in the second direction Y
  • the first The horizontal line groups and the first vertical line groups are alternately arranged, and the plurality of first horizontal lines in the first horizontal line group and the plurality of first vertical lines in the first vertical line group are sequentially connected to form a stepped wiring.
  • a transition line group may be provided between the first horizontal line group and the first vertical line group.
  • At least two shift register units may be arranged in the same first rectangle of the first corner portion 211 .
  • one first test unit may be provided in the same second rectangle of the first corner portion 211 .
  • the gate signal line 121 may include one initial signal line and four clock signal lines
  • the test signal line 122 may include one test control signal line and three test data signal lines
  • the power signal line 123 may include Including a second power line VDD and an initial signal line INIT.
  • a side of the gate signal line 121 away from the display area may further be provided with a first power supply line VSS configured to provide a low-level signal to a pixel driving circuit in each sub-pixel of the display area.
  • At least one compensation capacitor 120 may further be disposed between the power signal line 123 and the display area, the compensation capacitor 120 may include a plurality of sub-capacitors, and the compensation capacitor 120 is configured to provide capacitance for the pixel driving circuit in the sub-pixel in the column. compensate.
  • the compensation capacitor 120 includes a first electrode plate and a second electrode plate, the first electrode plate is connected to the second power line VDD through a power connection line, and the second electrode plate of the compensation capacitor 120 is connected to a data signal line.
  • one end of the second plate of the compensation capacitor 120 adjacent to the test unit 80 is connected to the test data signal line, and the other end adjacent to the display area is connected to the data signal line of the display area, that is, the test data signal line of the test circuit passes through
  • the second electrode plate of the compensation capacitor is connected to the data signal line of the display area.
  • the test signal line 122 (the second trace) includes a test control signal line of a stepped trace and a test data signal line of a stepped trace, and the minimum distance between the test data signal line and the edge of the display area is less than Test the minimum distance between the control signal line and the edge of the display area.
  • at least one third rectangle may be enclosed between the test control signal lines of the stepped trace and the test data signal lines of the stepped trace, and a dummy cell 130 is disposed in the at least one third rectangle.
  • a dummy cell may include a plurality of transistors, which may have the same structure as the transistors in the shift register cell, but have no electrical connection with the transistors in the shift register cell, to improve etching Uniformity and improved preparation quality.
  • the third rectangle is a rectangle in which the first direction X is the long side and the second direction Y is the short side, that is, the extending direction of the long side of the third rectangle is parallel to the first direction X.
  • the upper frame (third frame) is relatively wide and the space is relatively sufficient, and the left frame (first frame) and the right frame (second frame) are relatively narrow, because the frame at the corner is made of The narrower left border and the wider upper border (or the narrower right border and the wider upper border) are gradually connected, so the corners adjacent to the left border (or the right border) reduce the border at the corner bottleneck.
  • the gate signal lines of the stepped routing and the test signal lines of the stepped routing are surrounded by many a plurality of second rectangles are formed between the test signal lines of the stepped trace and the power signal lines of the stepped trace, and a plurality of shift register units are arranged in a stepped shape in the plurality of first rectangles Among them, a plurality of test units are arranged in a plurality of second rectangles in a stair-like arrangement, and the test units and the shift register units are respectively arranged on different steps to maximize the effective use of the corner space, and only need a smaller
  • the chamfering radius can meet the space required by the circuit, effectively reducing the width of the rounded area, realizing a narrow frame, and increasing the screen ratio, which is conducive to the realization of a full-screen display.
  • the first test unit since the three test transistors in the first test unit are spaced along the first direction X, and the three test transistors are flush in the second direction Y, the first test unit has a smaller In the design of arranging multiple first test units in a stepped arrangement in the first corner 211, the smaller height of the first test units not only reduces the space occupied by the first test units in the second direction Y, Moreover, the space occupied by the stepped arrangement in the first direction X is reduced, the corner space is effectively utilized to the maximum extent, and only a small chamfering radius is required to meet the space required by the circuit, and the width of the corner area is effectively reduced.
  • the plurality of second test units are arranged in the third frame 203 in a side-by-side arrangement, that is, the plurality of second test units in the third frame 203 are arranged in sequence along the first direction X, and in the second is flush in direction Y. Since the three test transistors in the second test unit are arranged in sequence along the second direction Y and staggered in the first direction X, the shape of the second test unit is characterized by a small width and a large height.
  • the third frame 203 can accommodate the required number of second test units, it is possible to increase the number of second test units by increasing the The width of the second test unit is reduced as much as possible, the width of the upper frame is reduced to the maximum extent, the narrow frame is realized, and the screen ratio is increased, which is conducive to the realization of full-screen display.
  • the test signal line may include 4 signal lines, respectively 1 test control signal line and 3 test data signal lines, an upper frame (third frame), a left frame (first frame) and a right frame 4 signal lines are set in the (second frame), and the 4 signal wires in the left frame and right frame extend along the second direction Y and are introduced into the binding pins in the lower frame (fourth frame), thus displaying Four signal lines are arranged on the upper frame, the left frame and the right frame of the substrate.
  • the upper frame, the first corner and the second corner are all provided with 4 signal lines, while the left frame is provided with only 2 signal lines, and the 2 signal lines extend along the second direction Y
  • the binding pins are introduced into the lower frame, and only two signal lines are provided in the right frame, and the two signal wires extend along the second direction Y and are introduced into the binding pins in the lower frame.
  • 2 test data signal lines may be set in the left frame
  • 1 test control signal line and 1 test data signal line may be set in the right frame
  • 1 test data signal line may be set in the left frame
  • two test data signal lines are set in the right frame, which is not limited in this disclosure.
  • FIG. 22 is a layout structural diagram of a multiplexing unit according to an exemplary embodiment of the present disclosure.
  • a display substrate with rectangular rounded corners includes a display area and a frame area, the display area includes a plurality of sub-pixels P arranged in a matrix, and the third corner 213 of the frame area is provided with multiple Multiplexing circuit (MUX), gate driving circuit (GOA) and corresponding signal lines.
  • MUX Multiplexing circuit
  • GOA gate driving circuit
  • the multiplexing circuit may include a plurality of multiplexing units 90, each multiplexing unit 90 is connected to a plurality of data signal lines in the display area, and the multiplexing unit 90 is configured so that one signal source is a plurality of The data signal lines provide data signals.
  • the gate driving circuit may include a plurality of cascaded shift register units 110, each shift register unit 110 is connected to at least one scan signal line of the display area, and the shift register unit 110 is configured to transmit to at least one scan signal line of the display area. Provides gate drive signals.
  • the circuit structure of the fourth corner of the bezel region and the circuit structure of the third corner region may be the same.
  • the signal lines of the third corner portion 213 are routed in a stepped manner, and the multiplexing unit 90 and the shift register unit 110 are respectively disposed on different steps.
  • the signal line includes a first line, a second line and a third line.
  • the third line is located between the display area and the second line, and the second line is located between the first line and the third line.
  • a plurality of first rectangles are enclosed between the first wiring and the second wiring
  • a plurality of shift register units 110 are respectively located in the plurality of first rectangles
  • a plurality of first rectangles are enclosed between the second wiring and the third wiring
  • a plurality of multiplexing units 90 are respectively located in the plurality of second rectangles.
  • the second rectangle is a rectangle in which the first direction X is the long side and the second direction Y is the short side, that is, the extending direction of the long side of the second rectangle is parallel to the first direction X.
  • the first traces may include gate signal lines 121 of stepped traces
  • the second traces may include multiplexed signal lines 124 of stepped traces
  • the third traces may include stepped traces
  • a plurality of first rectangles are enclosed between the gate signal lines 121 of the stepped wiring and the multiplexed signal lines 124 of the stepped wiring, and the plurality of shift register units 110 are arranged in the plurality of first rectangles in a stepped arrangement. , that is, a plurality of shift register units 110 are respectively disposed on a plurality of steps formed by the gate signal lines 121 .
  • a plurality of second rectangles are enclosed between the multiplexed signal lines 124 of the stepped wiring and the power signal lines 123 of the stepped wiring, and the plurality of multiplexing units 90 are arranged in the plurality of second rectangles in a stepped arrangement. That is, the plurality of shift register units 110 are respectively disposed on the plurality of steps formed by the multiplexed signal lines 124 .
  • the gate signal line 121 , the multiplexed signal line 124 and the power supply signal line 123 may each include a plurality of second horizontal line groups and a plurality of second horizontal line groups arranged in sequence along the edge of the display area in the second direction Y
  • the second vertical line group, the second horizontal line group includes a plurality of second horizontal lines extending in the first direction X
  • the second vertical line group includes a plurality of second vertical lines extending in the second direction Y
  • the second horizontal lines The groups and the second vertical line groups are alternately arranged, and the plurality of second horizontal lines in the second horizontal line group are sequentially connected with the plurality of second vertical lines in the second vertical line group to form a stepped wiring.
  • a transition line group may be provided between the second horizontal line group and the second vertical line group.
  • At least one shift register unit may be disposed.
  • one multiplexing unit may be set in the same second rectangle of the third corner portion 213, one multiplexing unit may be set.
  • the gate signal line 121 may include 1 initial signal line and 4 clock signal lines
  • the multiplexed signal line 124 may include 3 multiplexed control signal lines and 1 multiplexed data signal line
  • the power supply signal The line 123 may include a second power supply line VDD and an initial signal line INIT
  • a first power supply line VSS may also be provided on the side of the gate signal line 121 away from the display area.
  • the signal lines in the third corner and the fourth corner adopt a circular arc-shaped routing mode
  • the multiplexing unit and the shift register unit are arranged in sequence along the arc-shaped routing
  • the multiplexing unit and the shift register are arranged in sequence.
  • the register units are alternately arranged between the arc-shaped traces. Studies have shown that this arrangement of multiplexing units and shift register units requires a large chamfering radius to meet the space required by the circuit, making the border narrowing of the lower rounded corner area a design bottleneck.
  • the gate signal lines of the stepped routing and the multiplexed signal lines of the stepped routing are surrounded by many
  • a plurality of second rectangles are formed between the multiplexed signal lines of the stepped wiring and the power signal lines of the stepped wiring, and a plurality of shift register units are arranged in a stepped arrangement on the plurality of first rectangles.
  • a plurality of multiplexing units are arranged in a plurality of second rectangles in a stepped arrangement, and the multiplexing unit and the shift register unit are respectively arranged on different steps to maximize the effective use of the corner space.
  • a small chamfering radius can meet the space required by the circuit, effectively reducing the width of the rounded corner area, realizing a narrow frame, increasing the screen ratio, and facilitating the realization of a full-screen display.
  • FIG. 23 is a schematic structural diagram of a multiplexing unit according to an exemplary embodiment of the present disclosure, illustrating that the multiplexing unit includes three multiplexing transistors. As shown in FIG. 23 , in a plane parallel to the display substrate, the multiplexing unit includes three multiplexing transistors, and the three test transistors are arranged in sequence along the first direction X and are flush in the second direction Y.
  • the multiplexing gate electrode (control electrode) of the first multiplexing transistor TF1 is connected to the first multiplexing control signal line 57
  • the multiplexing gate electrode (control electrode) of the second multiplexing transistor TF2 is connected to the second multiplexing control signal line 67
  • the multiplexing gate electrode (control electrode) of the third multiplexing transistor TF1 is connected to the third multiplexing control signal line 77 .
  • the multiplexing source electrode (first electrode) of the first multiplexing transistor TF1, the multiplexing source electrode (first electrode) of the second multiplexing transistor TF2, and the multiplexing source electrode (first electrode) of the third multiplexing transistor TF3 Both are connected to the multiplexed data signal line 58 .
  • the multiplexing drain electrode (second pole) of the first multiplexing transistor is connected to one data signal line in the display area, and the multiplexing drain electrode (second pole) of the second multiplexing transistor is connected to another data signal line in the display area.
  • the multiplexed drain electrode (second electrode) of the three multiplexed transistors is connected to another data signal line in the display area.
  • the height of the multiplexing unit may be smaller than the height of the shift register unit.
  • the height of the shift register unit may be approximately 1.5 to 2 times the height of the multiplexing unit.
  • the multiplexing unit may have a rectangular shape, and the height of the multiplexing unit (third height H3 ) is 0.5 times to 0.9 times the width (third width M3 ) of the multiplexing unit.
  • the height of the multiplexing unit (the third height H3 ) may be about 35 ⁇ m to 45 ⁇ m
  • the width of the multiplexing unit (the third width M3 ) may be about 48 ⁇ m to 70 ⁇ m
  • the height of the shift register unit may be About 68 ⁇ m to 70 ⁇ m.
  • the height of the multiplexing unit in the exemplary embodiment of the present disclosure may be reduced by 50% to 60% compared with the multiplexing unit that is alternately arranged in a circular arc shape.
  • the height of the multiplexing unit may be about 40 ⁇ m, and the width (the third width M3 ) of the multiplexing unit may be about 59 ⁇ m.
  • the multiplexing unit may include:
  • the multiplexed active layers are arranged at intervals along the first direction, and are flush in the second direction;
  • the distances between the second ends and the edge of the display area are different; the first ends of the multiplexed data lines are respectively located on one side of the multiplexed active layers adjacent to the display area, and the multiplexed data lines have different distances.
  • the second end extends in the direction of the display area;
  • a third insulating layer covering the plurality of multiplexed gate electrodes and a plurality of multiplexed data lines, and a plurality of multiplexed connection lines disposed on the third insulating layer, the multiplexed connection lines along the The first direction is spaced apart, the first ends of the multiplexed connecting lines are respectively located on the side of the multiple test active layers away from the display area, and the second ends of the multiple multiplexed connecting lines extending away from the display area;
  • a fourth insulating layer covering the plurality of multiplexed connection lines, and a plurality of via holes are arranged thereon;
  • the first end is connected, and the second end of the multiplexed connection line is connected to the multiplexed data signal line through the via hole;
  • the multiplexed drain electrode is respectively connected to the corresponding multiplexed active layer and the corresponding multiplexed data line through the via hole.
  • the first end is connected, the second end of the multiplexed data line is connected with the data signal line of the display area; the second end of the multiplexed gate electrode is connected with the corresponding multiplexed control signal line through the via hole.
  • the preparation process of the multiplexing unit may include the following operations.
  • a semiconductor layer pattern is formed on the substrate.
  • forming the semiconductor layer pattern on the substrate may include: sequentially depositing a first insulating film and a semiconductor film on the substrate, and patterning the semiconductor film through a patterning process to form a first insulating layer covering the entire substrate , and a semiconductor layer pattern disposed on the first insulating layer, the semiconductor layer pattern including at least a first multiplexed active layer 51, a second multiplexed active layer 61 and a third multiplexed active layer 71, as shown in FIG. 24 Show.
  • the three multiplexing active layers are arranged at intervals along the first direction X, and are flush in the second direction Y, so that the size of the multiplexing circuit in the second direction Y can be effectively reduced.
  • the width of the first direction X of the three multiplexed active layers may be about 14 ⁇ m to 21 ⁇ m, and the height of the second direction Y may be about 20 ⁇ m to 30 ⁇ m.
  • each test active layer may have a width of about 17.3 ⁇ m and a height of about 25 ⁇ m.
  • forming the first metal layer pattern may include: sequentially depositing a second insulating film and a first metal film on the substrate on which the aforementioned pattern is formed, and patterning the first metal film through a patterning process to form a cover
  • the second insulating layer of the semiconductor layer pattern, and the first metal layer pattern disposed on the second insulating layer, the first metal layer pattern at least includes a first multiplexed gate electrode 52, a second multiplexed gate electrode 62, a third multiplexed gate electrode
  • the gate electrode 72 , the first multiplexed data line 53 , the second multiplexed data line 63 and the third multiplexed data line 73 are used, as shown in FIG. 25 .
  • the three multiplexing gate electrodes are arranged at intervals along the first direction X, and the first ends of the three multiplexing gate electrodes adjacent to the display area are flush in the second direction Y, thus effectively reducing the complex
  • the distances between the second ends of the three multiplexed gate electrodes far from the display area and the edge of the display area are different, and are configured to be respectively connected to the multiplexed control signal lines formed subsequently.
  • the three multiplexed data lines are arranged at intervals along the first direction X, the first ends of the three multiplexed data lines are respectively located on one side of the three multiplexed active layers adjacent to the display area, the three The second ends of the multiplexed data lines extend in the direction of the display area, and are configured to be respectively connected to the data signal lines of the display area.
  • the widths of the three test gate electrodes in the first direction X may be about 5 ⁇ m to 7 ⁇ m. In an exemplary embodiment, the width of each test gate electrode may be about 6 ⁇ m.
  • forming the second metal layer pattern may include: sequentially depositing a third insulating film and a second metal film on the substrate on which the foregoing pattern is formed, and patterning the second metal film through a patterning process to form a cover
  • the third insulating layer of the first metal layer pattern, and the second metal layer pattern disposed on the third insulating layer, the second metal layer pattern at least includes the first multiplexing connecting line 54, the second multiplexing connecting line 64 and the first multiplexing connecting line 64.
  • the triplex connection line 74 is shown in FIG. 26 .
  • the three multiplexing connection lines are arranged at intervals along the first direction X, the first ends of the three multiplexing connection lines are respectively located on one side of the plurality of test active layers away from the display area, and the three multiplexed connection lines are The second end of the connecting line extends in a direction away from the display area, and is configured to simultaneously connect the multiplexed data signal lines formed later.
  • a fourth insulating layer pattern is formed.
  • forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the foregoing pattern is formed, patterning the fourth insulating film through a patterning process, and forming a layer covering the second metal layer pattern.
  • the fourth insulating layer, a plurality of via holes are opened on the fourth insulating layer, as shown in FIG. 27 .
  • the plurality of via holes on the fourth insulating layer may include: a side of the first multiplexed gate electrode 52 adjacent to the first multiplexed connection line 54 and exposing the first multiplexed active layer 51 A plurality of first multiplexing vias K1 , a plurality of second multiplexing vias K2 located on the side of the first multiplexing gate electrode 52 adjacent to the first multiplexing data line 53 and exposing the first multiplexing active layer 51 , A plurality of third multiplexing vias K3 located on the side of the second multiplexing gate electrode 62 adjacent to the second multiplexing connecting line 64 and exposing the second multiplexing active layer 61, and located adjacent to the second multiplexing gate electrode 62 A plurality of fourth multiplexing vias K4 on one side of the second multiplexing data line 63 and exposing the second multiplexing active layer 61 are located on the side of the third multiplexing gate electrode 72 adjacent to the third multiplexing connecting line 74 and exposed A plurality of fifth multiplexing
  • the first end of the three-multiplexed active layer 71 exposes the ninth multiplexed via K9 of the third multiplexed data line 73 , and the first multiplexed connection line 54 is located adjacent to the first multiplexed active layer 51 .
  • the tenth multiplexing via K10 which is located at the second multiplexing connection line 64 adjacent to the second multiplexing active layer 61 and exposes the second multiplexing connection line
  • the second end of 71 and the fifteenth multiplexing via K15 that exposes the third multiplexing connection line 74 is located at the second end of the first multiplexing gate electrode 52 away from the first multiplexing active layer 51 and exposes the first multiplexing via K15.
  • a third metal layer pattern is formed.
  • forming the third metal layer pattern may include: depositing a third metal thin film on the substrate on which the aforementioned pattern is formed, patterning the third metal thin film through a patterning process, and forming a third metal thin film on the fourth insulating layer
  • the third metal layer pattern at least includes: a first multiplexed source electrode 55, a first multiplexed drain electrode 56, a second multiplexed source electrode 65, a second multiplexed drain electrode 66, and a third multiplexed source Electrode 75, third multiplexed drain electrode 76, first multiplexed control signal line 57, second multiplexed control signal line 67, first multiplexed control signal line 77 and multiplexed data signal line 58, as shown in FIG.
  • one end of the first multiplexing source electrode 55 is connected to the first multiplexing active layer 51 through the first multiplexing via K1, and the other end is connected to the first multiplexing via the tenth multiplexing via K10
  • the first end of the connecting wire 54 is connected.
  • One end of the first multiplexed drain electrode 56 is connected to the first multiplexed active layer 51 through the second multiplexed via K2 , and the other end is connected to the first end of the first multiplexed data line 53 through the seventh multiplexed via K7
  • the second end of the first multiplexed data line 53 is connected to the data signal line of the display area.
  • One end of the second multiplexed source electrode 65 is connected to the second multiplexed active layer 61 through the third multiplexed via K3 , and the other end is connected to the first multiplexed connection line 64 through the eleventh multiplexed via K11 end connection.
  • One end of the second multiplexed drain electrode 66 is connected to the second multiplexed active layer 61 through the fourth multiplexed via K4 , and the other end is connected to the first end of the second multiplexed data line 63 through the eighth multiplexed via K8
  • the second end of the second multiplexed data line 63 is connected to the data signal line of the display area.
  • One end of the third multiplexing source electrode 75 is connected to the third multiplexing active layer 71 through the fifth multiplexing via K5 , and the other end is connected to the first multiplexing connection line 74 through the twelfth multiplexing via K12 end connection.
  • One end of the third multiplexed drain electrode 76 is connected to the third multiplexed active layer 71 through the sixth multiplexed via K6 , and the other end is connected to the first end of the third multiplexed data line 73 through the ninth multiplexed via K9 connected, the second end of the third multiplexed data line 73 is connected to the data signal line of the display area.
  • the first multiplexing control signal line 57 is connected to the second end of the first multiplexing gate electrode 52 through the sixteenth multiplexing via K16, and the second multiplexing control signal line 67 is connected to the second end of the first multiplexing gate electrode 52 through the seventeenth multiplexing via K17.
  • the second ends of the two multiplexed gate electrodes 62 are connected, and the third multiplexed control signal line 77 is connected to the second end of the third gate electrode 72 through the eighteenth multiplexed via K18.
  • the multiplexed data signal line 58 is respectively connected to the second end and the second multiplexed connection line 54 through the thirteenth multiplexed via K13, the fourteenth multiplexed via K14 and the fifteenth multiplexed via K15.
  • the second end of the connecting line 64 and the second end of the third multiplexing connecting line 74 are connected.
  • a distance between a side edge of the first multiplexed source electrode away from the first multiplexed active layer and a side edge of the first multiplexed drain electrode away from the first multiplexed active layer may be about 14 ⁇ m To 21 ⁇ m
  • the distance between the side edge of the second multiplexed source electrode away from the second multiplexed active layer and the side edge of the second multiplexed drain electrode away from the second multiplexed active layer may be about 14 ⁇ m to 21 ⁇ m.
  • a distance between a side edge of the triple multiplexed source electrode away from the third multiplexed active layer and a side edge of the third multiplexed drain electrode away from the third multiplexed active layer may be about 14 ⁇ m to 21 ⁇ m. In an exemplary embodiment, a distance between a side edge of each multiplexed source electrode and a side edge of the multiplexed drain electrode may be about 17.3 ⁇ m.
  • the first multiplexing active layer 51, the first multiplexing gate electrode 52, the first multiplexing source electrode 55 and the first multiplexing drain electrode 56 constitute the first multiplexing transistor TF1; the second multiplexing transistor TF1;
  • the second multiplexing transistor TF2 is composed of the active layer 61, the second multiplexing gate electrode 62, the second multiplexing source electrode 65 and the second multiplexing drain electrode 66; the third multiplexing active layer 71, the third multiplexing The gate electrode 72, the third multiplexing source electrode 75 and the third multiplexing drain electrode 76 form a third multiplexing transistor TF3; the first multiplexing transistor TF1, the second multiplexing transistor TF2 and the third multiplexing transistor TF3 form a complex.
  • the first multiplexing gate electrode 52 is connected to the first multiplexing control signal line 57
  • the second multiplexing gate electrode 62 is connected to the second multiplexing control signal line 67
  • the third multiplexing gate electrode 72 is connected to the third multiplexing control signal line 77
  • the first multiplexing source electrode 55 , the second multiplexing source electrode 65 and the third multiplexing source electrode 75 are connected through the first multiplexing connection line 54 , the second multiplexing connection line 64 and the third multiplexing connection line 74 respectively
  • the same multiplexed data signal line 58, the first multiplexed drain electrode 56, the second multiplexed drain electrode 66 and the third multiplexed drain electrode 76 pass through the first multiplexed data line 53, the second multiplexed data line 63 and the
  • the third multiplexed data line 73 is connected to data signal lines in different display areas.
  • a turn-on signal is provided to the first multiplexing control signal line 57 , the second multiplexing control signal line 67 and the third multiplexing control signal line 77 by the control device in time division, so that the first multiplexing transistor TF1 , The second multiplexing transistor TF2 and the third multiplexing transistor TF3 are time-divisionally turned on.
  • the multiplexed data signal line 58 provides the data required by the data signal line connected to the turned-on multiplexing transistor. signal, write the data signal into the corresponding sub-pixel.
  • Exemplary embodiments of the present disclosure propose a multiplexing circuit structure.
  • the height of the multiplexing unit is reduced, combined with the stepped routing mode of the signal lines in the third corner and the fourth corner, the multiplexing unit is arranged stepwise along the multiplexing signal line, and the shift register unit is arranged stepwise along the gate signal line.
  • the multiplexing unit and the shift register unit are respectively arranged on different steps to maximize the effective use of the corner space. Only a small chamfering radius is required to meet the space required by the circuit, effectively reducing the lower frame and lower frame.
  • the width of the rounded corner area realizes a narrow frame and improves the screen ratio, which is conducive to the realization of a full-screen display.
  • the structure of the multiplexing unit and the preparation process thereof shown in the present disclosure are merely exemplary descriptions.
  • the corresponding structure may be changed and the patterning process may be increased or decreased according to actual needs.
  • the multiplexed connection lines may be disposed in the first metal layer
  • the multiplexed data lines may be disposed in the second metal layer.
  • the multiplexed gate electrodes, the multiplexed connection lines, and the multiplexed data lines can be arranged in the same layer and formed through the same patterning process.
  • the multiplexing unit may also be provided with other electrodes, leads or film layers, which are not limited in this disclosure.
  • the aforementioned test unit and multiplexing unit may be formed simultaneously through the same preparation process.
  • the semiconductor layer pattern of the test unit and the semiconductor layer pattern of the multiplexing unit are placed on the same layer and formed by the same patterning process, and the first metal layer pattern of the test unit and the first metal layer pattern of the multiplexing unit are placed on the same layer and passed through the same time.
  • the patterning process is formed.
  • the second metal layer pattern of the test unit and the second metal layer pattern of the multiplexing unit are arranged in the same layer and formed by the same patterning process.
  • the insulating layer via pattern is arranged in the same layer and formed by the same patterning process, and the third metal layer pattern of the test unit and the third metal layer pattern of the multiplexing unit are arranged in the same layer and formed by the same patterning process. Do limit.
  • the test unit and the multiplexing unit of the frame area and the pixel driving circuit of the display area may be formed simultaneously in the same fabrication process.
  • the semiconductor layer patterns of the test unit and the multiplexing unit may be disposed in the same layer as the active layer of the thin film transistor in the pixel driving circuit and formed by the same patterning process, and the first metal layer patterns of the test unit and the multiplexing unit may be the same as that of the pixel.
  • the gate electrode of the thin film transistor in the driving circuit is arranged in the same layer and formed by the same patterning process, and the second metal layer pattern of the test unit and the multiplexing unit can be arranged in the same layer as the second capacitor plate of the thin film transistor in the pixel driving circuit and pass through.
  • the third metal layer pattern of the test unit and the multiplexing unit can be arranged in the same layer as the source electrode and drain electrode of the thin film transistor in the pixel driving circuit and formed by the same patterning process, which is not limited in this disclosure. .
  • the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may employ silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON) Any one or more of them can be a single layer, a multi-layer or a composite layer.
  • the first insulating layer can be called a buffer layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer and the third insulating layer can be called a gate insulating (GI) layer
  • the fourth insulating layer can be called It is an interlayer insulating (ILD) layer.
  • the first metal thin film, the second metal thin film and the third metal thin film can be made of metal materials, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo) or Various, or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti and the like.
  • metal materials such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo) or Various, or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the active layer film can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si) , hexathiophene or polythiophene, that is, the present disclosure is applicable to transistors fabricated based on oxide technology, silicon technology or organic technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • hexathiophene or polythiophene hexathiophene
  • the active layer based on oxide technology can employ oxides containing indium and tin, oxides containing tungsten and indium, oxides containing tungsten and indium and zinc, oxides containing titanium and indium, oxides containing titanium and indium and tin , oxides containing indium and zinc, oxides containing silicon and indium and tin, oxides containing indium and gallium and zinc, etc.
  • Exemplary embodiments of the present disclosure also provide a method for fabricating a display substrate, the display substrate includes a display area and a frame area located around the display area; the frame area includes a frame area disposed oppositely in the first direction The first frame and the second frame, the third frame and the fourth frame oppositely arranged in the second direction, the first corner connecting the first frame and the third frame, the connection between the second frame and the third frame.
  • the second corner of the three frame, the third corner connecting the first frame and the fourth frame, and the fourth corner connecting the second frame and the fourth frame, the first corner to the fourth corner At least one of them is an arc-shaped corner, the first direction is the extension direction of the scan signal lines in the display area, and the second direction is the extension direction of the data signal lines in the display area;
  • the preparation Methods include:
  • a display structure in the display area, and forming a first wiring, a second wiring and a plurality of shift register units in at least one of the first to fourth corners;
  • a plurality of first rectangles are enclosed between the first wiring and the second wiring, and a plurality of shift register units are respectively located in the plurality of first rectangles.
  • At least one of the first to fourth corners is further formed with a third wiring, and the third wiring is located between the display area and the second wiring , a plurality of second rectangles are formed between the third wiring and the second wiring.
  • Exemplary embodiments of the present disclosure also provide a display device including the display substrate of the foregoing embodiments.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, or a navigator.
  • the display device may be a wearable display device, which can be worn on the human body in some ways, such as a smart watch, a smart bracelet, and the like.

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Abstract

一种显示基板及其制备方法、显示装置，显示基板包括显示区域和边框区域；边框区域包括在第一方向上相对设置的第一边框和第二边框、在第二方向上相对设置的第三边框和第四边框、连接第一边框和第三边框的第一角部、连接第二边框和第三边框的第二角部、连接第一边框和第四边框的第三角部以及连接第二边框和第四边框的第四角部，第一角部至第四角部中的至少一个为弧形的角部，第一方向为所述显示区域中扫描信号线的延伸方向，第二方向为所述显示区域中数据信号线的延伸方向；第一角部至第四角部的至少一个中设置有第一走线和第二走线，第一走线和第二走线之间围成多个第一矩形，多个移位寄存器单元分别位于多个第一矩形中。

Description

显示基板及其制备方法、显示装置 技术领域
本公开涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度等优点。随着显示技术的不断发展，以OLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的显示装置已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开示例性实施例提供了一种显示基板，包括显示区域和位于所述显示区域周边的边框区域；所述边框区域包括在第一方向上相对设置的第一边框和第二边框、在第二方向上相对设置的第三边框和第四边框、连接所述第一边框和第三边框的第一角部、连接所述第二边框和第三边框的第二角部、连接所述第一边框和第四边框的第三角部以及连接所述第二边框和第四边框的第四角部，所述第一角部至第四角部中的至少一个为弧形的角部，所述第一方向为所述显示区域中扫描信号线的延伸方向，所述第二方向为所述显示区域中数据信号线的延伸方向；所述第一角部至第四角部的至少一个中设置有第一走线和第二走线，所述第一走线和第二走线之间围成多个第一矩形，多个移位寄存器单元分别位于所述多个第一矩形中。
在示例性实施方式中，所述第一角部至第四角部的至少一个中还设置有第三走线，所述第三走线位于所述显示区域与所述第二走线之间，第二走线 和第三走线之间围成多个第二矩形。
在示例性实施方式中，所述第二矩形为长方形，所述第二矩形长边的延伸方向与所述第一方向平行。
在示例性实施方式中，所述第一角部和第二角部的至少一个中设置有多个第一测试单元，所述多个第一测试单元分别位于所述多个第二矩形中。
在示例性实施方式中，所述第一角部和第二角部的至少一个中，同一个第二矩形中设置至少一个第一测试单元。
在示例性实施方式中，所述第一角部和第二角部的至少一个中，同一个第一矩形中设置至少两个移位寄存器单元。
在示例性实施方式中，所述第一走线包括阶梯状走线的栅信号线，所述第二走线包括阶梯状走线的测试信号线，所述第三走线包括阶梯状走线的电源信号线，所述电源信号线与显示区域边缘的最小距离小于所述测试信号线与显示区域边缘的最小距离，所述测试信号线与显示区域边缘的最小距离小于所述栅信号线与显示区域边缘的最小距离。
在示例性实施方式中，所述测试信号线包括至少一个测试控制信号线和多个测试数据信号线；所述第一测试单元包括多个测试晶体管，所述多个测试晶体管沿所述第一方向排布；所述多个测试晶体管的控制极连接相同的测试控制信号线，所述多个测试复用晶体管的第一极分别连接不同的测试数据信号线，所述多个复用晶体管的第二极分别连接显示区域中不同的数据信号线。
在示例性实施方式中，所述多个测试晶体管沿所述第一方向排布包括：所述测试晶体管沿所述第一方向依次设置，在所述第二方向上平齐。
在示例性实施方式中，所述测试控制信号线与测试数据信号线之间围成至少一个第三矩形，至少一个第三矩形中设置有虚拟单元。
在示例性实施方式中，所述电源信号线与显示区域之间设置有至少一个补偿电容，所述补偿电容包括第一极板和第二极板，所述第一极板与第二电源线连接，所述第二极板的一端与第一测试单元的测试数据信号线连接，所 述第二极板的另一端与显示区域的数据信号线连接。
在示例性实施方式中，所述第一测试单元的高度为所述第一测试单元的宽度的0.9倍至1.3倍；所述第一测试单元的高度为所述第一测试单元第一方向的尺寸，所述第一测试单元的宽度为所述第一测试单元第二方向的尺寸。
在示例性实施方式中，所述第一测试单元的高度为70μm至100μm，所述第一测试单元的宽度为60μm至90μm。
在示例性实施方式中，所述第三角部和第四角部的至少一个中设置有多个复用单元，所述多个复用单元分别位于所述多个第二矩形中。
在示例性实施方式中，所述第三角部和第四角部的至少一个中，同一个第二矩形中设置至少一个复用单元。
在示例性实施方式中，所述第三角部和第四角部的至少一个中，同一个第一矩形中设置至少一个移位寄存器单元。
在示例性实施方式中，所述第一走线包括阶梯状走线的栅信号线，所述第二走线包括阶梯状走线的复用信号线，所述第三走线包括阶梯状走线的电源信号线，所述电源信号线与显示区域边缘的最小距离小于所述复用信号线与显示区域边缘的最小距离，所述复用信号线与显示区域边缘的最小距离小于所述栅信号线与显示区域边缘的最小距离。
在示例性实施方式中，所述复用信号线包括多个复用控制信号线和至少一个复用数据信号线；所述复用单元包括多个复用晶体管，所述多个复用晶体管沿所述第一方向排布；所述多个复用晶体管的控制极分别连接不同的复用控制信号线，所述多个复用晶体管的第一极连接相同的复用数据信号线，所述多个复用晶体管的第二极分别连接显示区域中不同的数据信号线。
在示例性实施方式中，所述多个复用晶体管沿所述第一方向排布包括：所述复用晶体管沿所述第一方向依次设置，在所述第二方向上平齐。
在示例性实施方式中，所述复用单元的高度为所述复用单元的宽度的0.5倍至0.9倍；所述复用单元的高度为所述复用单元第一方向的尺寸，所述复用单元的宽度为所述复用单元第二方向的尺寸。
在示例性实施方式中，所述复用单元的高度为35μm至45μm，所述复用单元的宽度为48μm至70μm。
另一方面，本公开示例性实施例还提供了一种显示装置，包括前述任一项所述的显示基板。
又一方面，本公开示例性实施例还提供了一种显示基板的制备方法，所述显示基板包括显示区域和位于所述显示区域周边的边框区域；所述边框区域包括在所述第一方向上相对设置的第一边框和第二边框、在所述第二方向上相对设置的第三边框和第四边框、连接所述第一边框和第三边框的第一角部、连接所述第二边框和第三边框的第二角部、连接所述第一边框和第四边框的第三角部以及连接所述第二边框和第四边框的第四角部，所述第一角部至第四角部中的至少一个为弧形的角部，所述第一方向为所述显示区域中扫描信号线的延伸方向，所述第二方向为所述显示区域中数据信号线的延伸方向；所述制备方法包括：
在所述显示区域内形成显示结构，在所述第一角部至第四角部的至少一个中形成第一走线、第二走线和多个移位寄存器单元；
所述第一走线和第二走线之间围成多个第一矩形，多个移位寄存器单元分别位于所述多个第一矩形中。
在示例性实施方式中，所述第一角部至第四角部的至少一个中还形成有第三走线，所述第三走线位于所述显示区域与所述第二走线之间，第三走线和第二走线之间围成多个第二矩形。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示装置的外形示意图；
图2为一种显示装置的结构示意图；
图3为一种显示基板显示区域的平面结构示意图；
图4为一种显示基板显示区域的剖面结构示意图；
图5为一种像素驱动电路的等效电路图；
图6为一种测试电路的等效电路图；
图7为一种多路复用电路的等效电路图；
图8为本公开示例性实施例一种测试电路的布局结构图；
图9为本公开示例性实施例一种第二测试单元的结构示意图；
图10至图14为本公开示例性实施例制备第二测试单元的示意图；
图15为本公开示例性实施例一种第一测试单元的结构示意图；
图16至图20为本公开示例性实施例制备第一测试单元的示意图；
图21为本公开示例性实施例一种第一测试单元的布局结构图；
图22为本公开示例性实施例一种多路复用单元的布局结构图；
图23为本公开示例性实施例一种复用单元的结构示意图；
图24至图28为本公开示例性实施例制备复用单元的示意图。
附图标记说明:
21—第一测试有源层；   22—第一测试栅电极；   23—第一测试数据线；
24—第一测试连接线；   25—第一测试源电极；   26—第一测试漏电极；
31—第二测试有源层；   32—第二测试栅电极；   33—第二测试数据线；
34—第二测试连接线；   35—第二测试源电极；   36—第二测试漏电极；
41—第三测试有源层；   42—第三测试栅电极；   43—第三测试数据线；
44—第三测试连接线；   45—第三测试源电极；   46—第三测试漏电极；
51—第一复用有源层；   52—第一复用栅电极；   53—第一复用数据线；
54—第一复用连接线；   55—第一复用源电极；   56—第一复用漏电极；
61—第二复用有源层；    62—第二复用栅电极；    63—第二复用数据线；
64—第二复用连接线；    65—第二复用源电极；    66—第二复用漏电极；
71—第三复用有源层；    72—第三复用栅电极；    73—第三复用数据线；
74—第三复用连接线；    75—第三复用源电极；    76—第三复用漏电极；
80—测试单元；          81—测试晶体管；        82—测试控制信号线；
83—测试数据信号线；    90—复用单元；          91—复用晶体管；
92—复用控制信号线；    93—复用数据信号线；    100—显示区域；
101—基底；             102—驱动电路层；       103—发光结构层；
104—封装层；           110—移位寄存器单元；   120—补偿电容；
121—栅信号线；         122—测试信号线；       123—电源信号线；
124—复用信号线；       130—虚拟单元；         200—边框区域；
201—第一边框；         202—第二边框；         203—第三边框；
204—第四边框；         211—第一角部；         212—第二角部；
213—第三角部；         214—第四角部。
具体实施方式
下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以 上且95°以下的角度的状态。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
随着OLED显示技术的发展，“屏占比”已经成为显示装置比较重要的性能参数，根据消费者对显示产品便携、视角效果等方面的追求，极窄边框甚至全屏显示成为OLED显示产品发展的新趋势，因此边框的窄化在OLED显示产品设计中越来越受到重视。
图1为一种显示装置的外形示意图，外形为一种矩形倒圆角形状。如图1所示，显示装置可以包括显示区域100和位于显示区域100周边的边框区域200。在示例性实施方式中，显示区域100可以包括在第一方向X上相对设置的第一边缘(左边缘)和第二边缘(右边缘)，以及在第二方向Y上相对设置的第三边缘(上边缘)和第四边缘(下边缘)，相邻边缘之间通过弧形的倒角连接，形成倒圆角的四边形形状。在示例性实施方式中，边框区域200可以包括在第一方向X上相对设置的第一边框(左边框)201和第二边框(右边框)202，在第二方向Y上相对设置的第三边框(上边框)203和第四边框(下边框)204，以及连接第一边框201和第三边框203的第一角部211、连接第二边框202和第三边框203的第二角部212、连接第一边框201和第四边框204的第三角部213和连接第二边框202和第四边框204的第四角部214。
在示例性实施方式中，第一边缘和第二边缘可以平行于第二方向Y，第三边缘和第四边缘可以平行于第一方向X，第一方向X和第二方向Y交叉。在示例性实施方式中，第一方向X可以是显示区域中扫描信号线的延伸方向(行方向)，第二方向Y可以是显示区域中数据信号线的延伸方向(列方向)，第一方向X和第二方向Y可以相互垂直。
在示例性实施方式中，为了降低成本以及简化驱动和检测结构，通常将部分显示驱动和性能检测的电路设置在边框区域。随着分辨率的提高，像素数量的增加，显示驱动电路和性能检测电路增多，不但增加了电路的布局难度，而且导致电路占用的空间较大，不利于窄边框设计。研究表明，对于矩形倒圆角形状的显示基板，圆弧形角部区域中电路布设复杂，是减小边框的 瓶颈之一。
图2为一种显示装置的结构示意图。如图2所示，OLED显示装置可以包括扫描信号驱动器、数据信号驱动器、发光信号驱动器、OLED显示基板、第一电源单元、第二电源单元和初始电源单元。在示例性实施方式中，OLED显示基板至少包括多个扫描信号线(S1到SN)、多个数据信号线(D1到DM)和多个发光信号线(EM1到EMN)，扫描信号驱动器被配置为依次向多个扫描信号线(S1到SN)提供扫描信号，数据信号驱动器被配置为向多个数据信号线(D1到DM)提供数据信号，发光信号驱动器被配置为依次向多个发光信号线(EM1到EMN)提供发光控制信号。在示例性实施方式中，多个扫描信号线和多个发光信号线沿着水平方向延伸，多个数据信号线沿着竖直方向延伸。在示例性实施方式中，OLED显示基板包括多个，多个扫描信号线、发光信号线和数据信号线交叉限定出多个子像素，至少一个子像素包括像素驱动电路和发光器件。第一电源单元、第二电源单元和初始电源单元分别被配置为通过第一电源线、第二电源线和初始信号线向像素驱动电路提供第一电源电压、第二电源电压和初始电源电压。
图3为一种显示基板显示区域的平面结构示意图。如图3所示，显示区域可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个中包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3，第一子像素P1、第二子像素P2和第三子像素P3均包括像素驱动电路和发光器件。第一子像素P1、第二子像素P2和第三子像素P3中的像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向所述发光器件输出相应的电流。第一子像素P1、第二子像素P2和第三子像素P3中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，像素单元P中可以包括红色子像素、绿色子像素和蓝色子像素，或者可以包括红色子像素、绿色子像素、蓝色子像素和白色子像素，本公开在此不做限定。在示例性实施方式中，像素单元中子像素的 形状可以是矩形状、菱形、五边形或六边形。像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列，像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形(Square)方式排列，本公开在此不做限定。
图4为一种显示基板显示区域的剖面结构示意图，示意了OLED显示基板三个子像素的结构。如图4所示，在垂直于显示基板的平面上，显示基板了可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底101一侧的发光器件103以及设置在发光器件103远离基底101一侧的封装层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施方式中，每个子像素的驱动电路层102可以包括构成像素驱动电路的多个晶体管和存储电容，图4中以每个子像素中包括一个驱动晶体管和一个存储电容为例进行示意。在一些可能的实现方式中，每个子像素的驱动电路层102可以包括：设置在基底上的第一绝缘层；设置在第一绝缘层上的有源层；覆盖有源层的第二绝缘层；设置在第二绝缘层上的栅电极和第一电容电极；覆盖栅电极和第一电容电极的第三绝缘层；设置在第三绝缘层上的第二电容电极；覆盖第二电容电极的第四绝缘层，第二绝缘层、第三绝缘层和第四绝缘层上开设有过孔，过孔暴露出有源层；设置在第四绝缘层上的源电极和漏电极，源电极和漏电极分别通过过孔与有源层连接；覆盖前述结构的平坦层，平坦层上开设有过孔，过孔暴露出漏电极。有源层、栅电极、源电极和漏电极组成驱动晶体管105，第一电容电极和第二电容电极组成存储电容106。
在示例性实施方式中，发光器件103可以包括阳极、像素定义层、有机发光层和阴极。阳极设置在平坦层上，通过平坦层上开设的过孔与驱动晶体管的漏电极连接；像素定义层设置在阳极和平坦层上，像素定义层上设置有像素开口，像素开口暴露出阳极；有机发光层至少部分设置在像素开口内，有机发光层与阳极连接；阴极设置在有机发光层上，阴极与有机发光层连接；有机发光层在阳极和阴极驱动下出射相应颜色的光线。
在示例性实施方式中，封装层104可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可采用无机材料，第二封装层可采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光器件103。
在示例性实施方式中，有机发光层可以至少包括在阳极上叠设的空穴注入层、空穴传输层、发光层和空穴阻挡层。在示例性实施方式中，所有子像素的空穴注入层是连接在一起的共通层，所有子像素的空穴传输层是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，空穴阻挡层是连接在一起的共通层。
在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C结构。图5为一种像素驱动电路的等效电路图。如图5所示，像素驱动电路可以包括7个开关晶体管(第一晶体管T1到第七晶体管T7)、1个存储电容C和8个信号线(数据信号线DATA、第一扫描信号线S1、第二扫描信号线S2、第一初始信号线INIT1、第二初始信号线INIT2、第一电源线VSS、第二电源线VDD和发光信号线EM)。
在示例性实施方式中，第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与第一初始信号线INIT1连接，第一晶体管的第二极与第二节点N2连接。第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。第三晶体管T3的控制极与第二节点N2连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线DATA连接，第四晶体管T4的第二极与第一节 点N1连接。第五晶体管T5的控制极与发光信号线EM连接，第五晶体管T5的第一极与第二电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线EM连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第七晶体管T7的控制极与第一扫描信号线S1连接，第七晶体管T7的第一极与第二初始信号线INIT2连接，第七晶体管T7的第二极与发光器件的第一极连接。存储电容C的第一端与第二电源线VDD连接，存储电容C的第二端与第二节点N2连接。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，发光器件的第二极与第一电源线VSS连接，第一电源线VSS的信号为低电平信号，第二电源线VDD的信号为持续提供高电平信号。第一扫描信号线S1为本显示行像素驱动电路中的扫描信号线，第二扫描信号线S2为上一显示行像素驱动电路中的扫描信号线，即对于第n显示行，第一扫描信号线S1为S(n)，第二扫描信号线S2为S(n-1)，本显示行的第二扫描信号线S2与上一显示行像素驱动电路中的第一扫描信号线S1为同一信号线，可以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，显示基板的边框区域可以设置有栅极驱动电路(GOA)、测试电路(CT)和多路复用电路(MUX)。在示例性实施方式中，栅极驱动电路可以包括多个级联的移位寄存器单元，每个移位寄存器单元连接显示区域的至少一个扫描信号线，配置为向显示区域的至少一个扫描信号线提供栅极驱动信号。测试电路可以包括多个测试单元，每个测试单元连接显示区域的多个数据信号线，配置为向显示区域的多个数据信号线提供测试数据信号。多路复用电路可以包括多个复用单元，每个复用单元连接显示区域的的多个数据信号线连接，配置为使一个信号源为多个数据信号线提 供数据信号。在一些可能的实现方式中，移位寄存器单元的具体形式是多样的，本公开在此不做限定。
在示例性实施方式中，测试电路可以包括至少一个测试控制信号线、多个测试数据信号线和多个测试单元，每个测试单元与测试控制信号线和测试数据信号线连接，且连接显示区域的多个数据信号线，测试单元配置为根据测试控制信号线的控制，将测试数据信号线的信号(数据信号)提供给(同时提供或分别提供)与其连接的显示区域的多个数据信号线，以检测和定位显示区域发生不良的子像素。图6为一种测试电路的等效电路图。在示例性实施方式中，测试电路可以包括至少一个测试控制信号线、n1条测试数据信号线和m1个测试单元，m1个测试单元中的至少一个测试单元包括n1个测试晶体管，m1和n1为大于或等于2的正整数。图6以一个测试控制信号线、三条测试数据信号线以及一个测试单元包括三个测试晶体管为例进行了示意。如图6所示，在同一个测试单元80的三个测试晶体管81中，三个测试晶体管81的控制极均连接同一个测试控制信号线82。三个测试晶体管81的第一极分别连接不同的测试数据信号线，即第一个测试晶体管的第一极连接第一测试数据信号线83-1，第二个测试晶体管的第一极连接第二测试数据信号线83-2，第三个测试晶体管的第一极连接第三测试数据信号线83-3。三个测试晶体管81的第二极分别连接显示区域中不同的数据信号线DATA，即第一个测试晶体管的第二极连接一个数据信号线DATA，第二个测试晶体管的第二极连接另一个数据信号线DATA，第三个测试晶体管的第二极连接又一个数据信号线DATA。这样，通过测试控制信号线82可以控制测试单元80中的三个测试晶体管81的导通，可以控制不同的测试数据信号线的信号写入不同的数据信号线。在进行测试时，通过控制装置向测试控制信号线82提供导通信号，向多个测试数据信号线分别提供所需的测试数据信号，使显示区域中多个数据信号线获得测试数据信号，实现检测。在示例性实施方式中，测试控制信号线和测试数据信号线可以设置在边框区域，可以是围绕显示区域环形的闭合走线。
在示例性实施方式中，数据信号线数量可以等于m1*n1，每条数据信号线连接的子像素颜色相同，测试时向同一颜色的子像素对应的数据信号线提 供相同的测试数据信号，使这些子像素进行相同的显示，通过显示画面的颜色确定是否有发生不良的子像素，以及定位发生不良的子像素。
在示例性实施方式中，多路复用电路可以包括多个复用控制信号线、多个复用数据信号线和多个复用单元，每个复用单元连接显示区域的多个数据信号线，复用单元配置为根据多个复用控制信号线的控制，将一个复用数据信号线的信号(数据信号)分时提供给与其连接的多个数据信号线。图7为一种多路复用电路的等效电路图。在示例性实施方式中，多路复用电路可以包括n2条复用控制信号线、至少一个复用数据信号线和m2个复用单元90，m2个复用单元中的至少一个复用单元包括n2个复用晶体管，m2和n2为大于或等于2的正整数。图7以六条复用控制信号线、二条复用数据信号线以及一个复用单元包括六个复用晶体管为例进行了示意。如图7所示，在同一个复用单元90的六个复用晶体管91中，六个复用晶体管91的控制极分别连接不同的复用控制信号线，即第一个复用晶体管的控制极连接第一复用控制信号线92-1，第二个复用晶体管的控制极连接第二复用控制信号线92-2，第三个复用晶体管的控制极连接第三复用控制信号线92-3，第四个复用晶体管的控制极连接第四复用控制信号线92-4，第五个复用晶体管的控制极连接第五复用控制信号线92-6，第六个复用晶体管的控制极连接第六复用控制信号线92-6。六个复用晶体管91的第一极均连接同一个复用数据信号线，即第一个复用单元90中的第一个晶体管至第六个复用晶体管的第一极均连接第一复用数据信号线93-1，第二个复用单元90中的第一个晶体管至第六个复用晶体管的第一极均连接第二复用数据信号线93-2。六个复用晶体管91的第二极分别连接显示区域中不同的数据信号线DATA，即第一个复用晶体管的第二极连接显示区域中的一个数据信号线DATA，第二个复用晶体管的第二极连接显示区域中的另一个数据信号线DATA……。在显示过程中，通过控制装置分时向六条复用控制信号线提供导通信号，使每个复用单元90中的六个复用晶体管91分时导通，在任一复用晶体管91导通时，复用数据信号线提供与导通的复用晶体管91连接的数据信号线所需的数据信号，数据信号线将数据信号写入相应的子像素。
在示例性实施方式中，数据信号线数量可以等于m2*n2。通过设置多路 复用电路，可以使一个信号源(例如驱动芯片的一个引脚)为多个数据信号线提供数据信号，可以大大降低实际的信号源数量，简化产品结构。在示例性实施方式中，复用单元90可以包括三个复用晶体管91，控制三条数据信号线(一拖3)。
本公开示例性实施例中，显示基板可以包括显示区域和位于所述显示区域周边的边框区域；所述边框区域包括在第一方向上相对设置的第一边框和第二边框、在第二方向上相对设置的第三边框和第四边框、连接所述第一边框和第三边框的第一角部、连接所述第二边框和第三边框的第二角部、连接所述第一边框和第四边框的第三角部以及连接所述第二边框和第四边框的第四角部，所述第一角部至第四角部中的至少一个为弧形的角部，所述第一方向为所述显示区域中扫描信号线的延伸方向，所述第二方向为所述显示区域中数据信号线的延伸方向；所述第一角部至第四角部的至少一个中设置有第一走线和第二走线，所述第一走线和第二走线之间围成多个第一矩形，多个移位寄存器单元分别位于所述多个第一矩形中。
在示例性实施方式中，所述第一角部至第四角部的至少一个中还设置有第三走线，所述第三走线位于所述显示区域与所述第二走线之间，第三走线和第二走线之间围成多个第二矩形。
在示例性实施方式中，所述第二矩形为长方形，所述第二矩形长边的延伸方向与所述第一方向平行。
在示例性实施方式中，所述第一角部和第二角部的至少一个中设置有多个第一测试单元，所述多个第一测试单元分别位于所述多个第二矩形中
在示例性实施方式中，所述第一角部和第二角部的至少一个中，同一个第二矩形中设置至少一个第一测试单元。
在示例性实施方式中，所述第一角部和第二角部的至少一个中，同一个第一矩形中设置至少两个移位寄存器单元。
在示例性实施方式中，所述第三角部和第四角部的至少一个中设置有多个复用单元，所述多个复用单元分别位于所述多个第二矩形中。
在示例性实施方式中，所述第三角部和第四角部的至少一个中，同一个 第二矩形中设置至少一个复用单元。
在示例性实施方式中，所述第三角部和第四角部的至少一个中，同一个第一矩形中设置至少一个移位寄存器单元。
在示例性实施方式中，所述数据处理电路可以包括第一测试电路，所述第一测试电路设置在所述第一角部和第二角部的至少一个中，所述第一测试电路包括多个第一测试单元，所述第一测试单元与所述显示区域的至少一个数据信号线连接，配置为向所述数据信号线提供测试数据信号。所述第三边框中设置有第二测试电路，所述第二测试电路包括多个第二测试单元，所述第二测试单元与所述显示区域的至少一个数据信号线连接，配置为向所述数据信号线提供测试数据信号。
在示例性实施方式中，所述第一测试单元的高度小于所述第二测试单元的高度，所述高度为所述第二方向的尺寸。
本公开示例性实施例通过将检测电路分别设置在第一角部211、第二角部212和第三边框203内，将多路复用电路的复用单元设置在第三角部213和第四角部214的至少一个内，使不同的电路单元分布均匀，有利于减小边框区域的宽度，实现了显示装置的窄边框。
在示例性实施方式中，测试电路可以设置在边框区域200中的第一角部211(或第二角部212)和第三边框203内，且设置在第一角部211(或第二角部212)内的测试电路的结构与设置在第三边框203内的测试电路的结构不同。
图8为本公开示例性实施例一种测试电路的布局结构图。如图8所示，在示例性实施方式中，测试电路可以包括第一测试电路CT1和第二测试电路CT2，第一测试电路CT1可以设置在第一角部211内，或者设置在第二角部212内，或者设置在第一角部211和第二角部212内，第二测试电路CT2可以设置在第三边框203内，第一测试电路CT1的结构不同于第二测试电路CT2的结构。在示例性实施方式中，第一测试电路CT1包括多个第一测试单元，第二测试电路CT2包括多个第二测试单元，第一测试单元的结构不同于第二测试单元至少包括第一测试单元的高度小于第二测试单元的高度，高度为第二方向Y的尺寸。通过将位于上边框和位于角部的测试电路设置成两种 具有不同高度的结构，可以最大限度地有效利用上边框和角部的边框空间，缩减边框宽度，实现窄边框。
图9为本公开示例性实施例一种第二测试单元的结构示意图，示意了第二测试单元包括三个测试晶体管。如图9所示，在平行于显示基板的平面内，第二测试单元包括三个测试晶体管，三个测试晶体管沿第二方向Y依次设置，在第一方向X上错位设置。第一测试晶体管TC1的源电极(第一极)通过第一测试连接线24连接第一测试数据信号线27，第一测试晶体管的漏电极(第二极)通过第一测试数据线23连接显示区域的一个数据信号线。第二测试晶体管TC2的源电极(第一极)通过第二测试连接线34连接第二测试数据信号线37，第二测试晶体管的漏电极(第二极)通过第二测试数据线33连接显示区域的另一个数据信号线。第三测试晶体管TC3的源电极(第一极)通过第三测试连接线44连接第三测试数据信号线47，第三测试晶体管的漏电极(第二极)通过第三测试数据线43连接显示区域的又一个数据信号线。第一测试晶体管TC1的第一测试栅电极、第二测试晶体管TC2的第二测试栅电极和第三测试晶体管TC3的第三测试栅电极42可以为相互连接的一体结构，且连接测试控制信号线28。
在示例性实施方式中，第二测试单元可以为矩形状，第二测试单元的高度(第二高度H2)大于第二测试单元的宽度(第二宽度M2)，第二高度H2可以约为第二宽度M2的2倍至3倍。本公开示例性实施例中，宽度是第一方向X的尺寸，高度是第二方向Y的尺寸。
在示例性实施方式中，第二测试单元的宽度M2可以约为44μm至66μm，第二测试单元的高度H2可以约为110μm至170μm。
在示例性实施方式中，第二测试单元的宽度M2可以约为54.92μm，第二高度H2可以约为141.6μm。
在垂直于显示基板的平面内，第二测试单元可以包括：
设置在基底上的第一绝缘层；
设置在所述第一绝缘层上的多个测试有源层，所述多个测试有源层沿着所述第二方向间隔设置，在所述第一方向上错位设置；
覆盖所述多个测试有源层的第二绝缘层，以及设置在所述第二绝缘层上的多个测试栅电极和多个测试数据线；所述多个测试栅电极沿着所述第二方向间隔设置，在所述第一方向上错位设置；所述多个测试数据线沿着所述第一方向间隔设置，所述多个测试数据线的第一端分别位于所述多个测试有源层邻近显示区域的一侧，所述多个测试数据线的第二端向所述显示区域的方向延伸；
覆盖所述多个测试栅电极和多个测试数据线的第三绝缘层，以及设置在所述第三绝缘层上的多个测试连接线，所述多个测试连接线沿着所述第一方向间隔设置，所述多个测试连接线的第一端分别位于所述多个测试有源层远离显示区域的一侧，所述多个测试连接线的第二端向远离所述显示区域的方向延伸，所述多个测试连接线的第二端与显示区域边缘的距离不同；
覆盖所述多个测试连接线的第四绝缘层，其上设置有多个过孔；
设置在所述第四绝缘层上的多个测试源电极和多个测试漏电极；所述测试源电极通过过孔分别与对应的测试有源层和对应的测试连接线的第一端连接，所述测试连接线的第二端通过过孔与对应的测试数据信号线连接；所述测试漏电极通过过孔分别与对应的测试有源层和对应的测试数据线的第一端连接，所述测试数据线的第二端与所述显示区域的数据信号线连接；所述多个测试栅电极通过过孔与测试控制信号线连接。
下面通过第二测试单元的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案 化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“A的正投影包含B的正投影”或“B的正投影位于“A的正投影范围之内”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在一种示例性实施方式中，第二测试单元的制备过程可以包括如下操作。
(1)在基底上形成半导体层图案。在示例性实施方式中，在基底上形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖整个基底的第一绝缘层，以及设置在第一绝缘层上的半导体层图案，半导体层图案至少包括第一测试有源层21、第二测试有源层31和第三测试有源层41，如图10所示。在示例性实施方式中，基底可以是柔性基底，或者是刚性基底。在示例性实施方式中，三个测试有源层沿着第二方向Y间隔设置，在第一方向X上错位设置，三个测试有源层第一方向X的宽度可以约为20μm至25μm，第二方向Y的高度可以约为13μm至19μm。在示例性实施方式中，每个测试有源层的宽度可以约为22.9μm，高度可以约为16μm。
(2)形成第一金属层图案。在示例性实施方式中，形成第一金属层图案可以包括：在形成前述图案的基底上依次沉积第二绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一金属层图案，第一金属层图案至少包括第一测试栅电极22、第二测试栅电极32、第三测试栅电极42、第一测试数据线23、第二测试数据线33和第三测试数据线43，如图11所示。在示例性实施方式中，三个测试栅电极沿着第二方向Y间隔设置，在第一方向X上错位设置，三个测试栅电极第一方向X的宽度可以约为8μm至11μm。在示例性实施方式中，每个测试栅电极的宽度可以约为9.3μm。在示例性实施方式中，三个测试数据线沿着第一方向X间隔设置，三个测试数据线的第一端分别位于三个测试有源层邻近显示区域的一侧，三个测试数据线的第二端向显示区域的方向(第二方向Y)延伸。在示例性实施方式中，第一测试栅电极22、第二测试栅电极32和第三测试栅电极42可以是相互连接的一体结 构。第一测试栅电极22、第二测试栅电极32和第三测试栅电极42配置为连接后续形成的测试控制信号线，第一测试数据线23、第二测试数据线33和第三测试数据线43配置为分别连接显示区域的数据信号线。
(3)形成第二金属层图案。在示例性实施方式中，形成第二金属层图案可以包括：在形成前述图案的基底上依次沉积第三绝缘薄膜和第二金属薄膜，通过图案化工艺对第二金属薄膜进行图案化，形成覆盖第一金属层图案的第三绝缘层，以及设置在第三绝缘层上的第二金属层图案，第二金属层图案至少包括第一测试连接线24、第二测试连接线34和第三测试连接线44，如图12所示。在示例性实施方式中，三个测试连接线的第一端分别位于三个测试有源层远离显示区域的一侧，三个测试连接线的第二端向远离显示区域的方向延伸，三个测试连接线的第二端与显示区域边缘的距离不同。在示例性实施方式中，第一测试连接线24、第二测试连接线34和第三测试连接线44配置为分别连接后续形成的测试数据信号线。
(4)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的基底上沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二金属层图案的第四绝缘层，第四绝缘层上开设有多个过孔，如图13所示。在示例性实施方式中，第四绝缘层上的多个过孔可以包括：位于第一测试栅电极22邻近第一测试数据线23一侧且暴露出第一测试有源层21的第一测试过孔V1、位于第一测试栅电极22邻近第一测试连接线24一侧且暴露出第一测试有源层21的第二测试过孔V2、位于第二测试栅电极32邻近第二测试数据线33一侧且暴露出第二测试有源层31的第三测试过孔V3、位于第二测试栅电极32邻近第二测试连接线34一侧且暴露出第二测试有源层31的第四测试过孔V4、位于第三测试栅电极42邻近第三测试数据线43一侧且暴露出第三测试有源层41的第五测试过孔V5、位于第三测试栅电极42邻近第三测试连接线44一侧且暴露出第三测试有源层41的第六测试过孔V6、位于第一测试数据线23邻近第一测试有源层21的第一端且暴露出第一测试数据线23的第七测试过孔V7、位于第二测试数据线33邻近第二测试有源层31的第一端且暴露出第二测试数据线33的第八测试过孔V8、位于第三测试数据线43邻近第三测试有源层41的第一 端且暴露出第三测试数据线43的第九测试过孔V9、位于第一测试连接线24邻近第一测试有源层21的第一端且暴露出第一测试连接线24的第十测试过孔V10、位于第二测试连接线34邻近第二测试有源层31的第一端且暴露出第二测试连接线34的第十一测试过孔V11、位于第三测试连接线44邻近第三测试有源层41的第一端且暴露出第三测试连接线44的第十二测试过孔V12、位于第一测试连接线24远离第一测试有源层21一端且暴露出第一测试连接线24的第十三测试过孔V13、位于第二测试连接线34远离第二测试有源层31的第二端且暴露出第二测试连接线34的第十四测试过孔V14、位于第三测试连接线44远离第三测试有源层41的第二端且暴露出第三测试连接线44的第十五测试过孔V12、位于第一测试栅电极22远离显示区域的第二端且暴露出第一测试栅电极22的第十六测试过孔V16。
(5)形成第三金属层图案。在示例性实施方式中，形成第三金属层图案可以包括：在形成前述图案的基底上沉积第三金属薄膜，通过图案化工艺对第三金属薄膜进行图案化，在第四绝缘层上形成第三金属层图案，第三金属层图案至少包括：第一测试源电极25、第一测试漏电极26、第二测试源电极35、第二测试漏电极36、第三测试源电极45、第三测试漏电极46、第一测试数据信号线27、第二测试数据信号线37、第一测试数据信号线47和测试控制信号线28，如图14所示。
在示例性实施方式中，第一测试漏电极26的一端通过第一测试过孔V1与第一测试有源层21连接，另一端通过第七测试过孔V7与第一测试数据线23的第一端连接，第一测试数据线23的第二端与显示区域的一个数据信号线连接。第一测试源电极25的一端通过第二测试过孔V2与第一测试有源层21连接，另一端通过第十测试过孔V10与第一测试连接线24的第一端连接，第一测试连接线24的第二端通过第十三测试过孔V13与第一测试数据信号线27连接。第二测试漏电极36的一端通过第三测试过孔V3与第二测试有源层31连接，另一端通过第八测试过孔V8与第二测试数据线33的第一端连接，第二测试数据线33的第二端与显示区域的一个数据信号线连接。第二测试源电极35的一端通过第四测试过孔V4与第二测试有源层31连接，另一端通过第十一测试过孔V11与第二测试连接线34的第一端连接，第二测 试连接线34的第二端通过第十四测试过孔V14与第二测试数据信号线37连接。第三测试漏电极46的一端通过第五测试过孔V5与第三测试有源层41连接，另一端通过第九测试过孔V9与第三测试数据线43的第一端连接，第三测试数据线43的第二端与显示区域的一个数据信号线连接。第三测试源电极45的一端通过第六测试过孔V6与第三测试有源层41连接，另一端通过第十二测试过孔V12与第三测试连接线44的第一端连接，第三测试连接线44的第二端通过第十五测试过孔V15与第三测试数据信号线47连接。第一测试栅电极22通过第十六测试过孔V16与测试控制信号线28连接。
在示例性实施方式中，第一测试源电极25远离第一测试有源层21的侧边缘与第一测试漏电极26远离第一测试有源层21的侧边缘之间的距离可以约为20μm至25μm，第二测试源电极35远离第二测试有源层31的侧边缘与第二测试漏电极36远离第二测试有源层31的侧边缘之间的距离可以约为20μm至25μm，第三测试源电极45远离第三测试有源层41的侧边缘与第三测试漏电极46远离第三测试有源层41的侧边缘之间的距离可以约为20μm至25μm。在示例性实施方式中，每个测试源电极的侧边缘与测试漏电极的侧边缘之间的距离可以约为22.9μm。
在示例性实施方式中，第一测试有源层21、第一测试栅电极22、第一测试源电极25和第一测试漏电极26组成第一测试晶体管TC1；第二测试有源层31、第二测试栅电极32、第二测试源电极35和第二测试漏电极36组成第二测试晶体管TC2；第三测试有源层41、第三测试栅电极42、第三测试源电极45和第三测试漏电极46组成第三测试晶体管TC3；第一测试晶体管TC1、第二测试晶体管TC2和第三测试晶体管TC3组成一个测试单元。第一测试栅电极22、第二测试栅电极32和第三测试栅电极42均连接同一个测试控制信号线28，第一测试漏电极26、第二测试漏电极36和第三测试漏电极46分别通过第一测试数据线23、第二测试数据线33和第三测试数据线43连接显示区域不同的数据信号线，第一测试源电极25、第二测试源电极35和第三测试源电极45分别通过第一测试连接线24、第二测试连接线34和第三测试连接线44分别连接第一测试数据信号线27、第二测试数据信号线37和第一测试数据信号线47。在进行测试时，通过控制装置向测试控制信号线 28提供导通信号，控制第一测试晶体管TC1、第二测试晶体管TC2和第三测试晶体管TC3导通，第一测试数据信号线27、第二测试数据信号线37和第一测试数据信号线47提供的测试数据信号传输给显示区域中多个数据信号线。
本公开所示第二测试单元的结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，测试连接线可以设置在第一金属层中，测试数据线可以设置在第二金属层中。又如，测试栅电极、测试连接线和测试数据线可以设置同层设置，且通过同一次构图工艺形成。再如，第二测试单元还可以设置其它电极、引线或膜层，本公开在此不做限定。
图15为本公开示例性实施例一种第一测试单元的结构示意图，示意了第一测试单元包括三个测试晶体管。如图15所示，在平行于显示基板的平面内，第一测试单元包括三个测试晶体管，三个测试晶体管沿第一方向X依次设置，在第二方向Y上平齐。第一测试晶体管TC1的源电极(第一极)通过第一测试连接线24连接第一测试数据信号线27，第一测试晶体管的漏电极(第二极)通过第一测试数据线23连接显示区域的一个数据信号线。第二测试晶体管TC2的源电极(第一极)通过第二测试连接线34连接第二测试数据信号线37，第二测试晶体管的漏电极(第二极)通过第二测试数据线33连接显示区域的另一个数据信号线。第三测试晶体管TC3的源电极(第一极)通过第三测试连接线44连接第三测试数据信号线47，第三测试晶体管的漏电极(第二极)通过第三测试数据线43连接显示区域的又一个数据信号线。第一测试晶体管TC1的测试栅电极、第二测试晶体管TC2的测试栅电极和第三测试晶体管TC3的测试栅电极42均连接同一个测试控制信号线28。
在示例性实施方式中，第一测试单元可以为矩形状，第一测试单元的高度(第一高度H1)可以大于第一测试单元的宽度(第一宽度M1)，或者第一高度H1可以小于或等于第一宽度K1，第一高度H1可以约为第一宽度K1的0.9倍至1.3倍。
在示例性实施方式中，第二测试单元的高度H2可以约为第一测试单元的高度H1的1.5倍至4倍。
在示例性实施方式中，第一测试单元的宽度M1可以约为60μm至90μm，第一测试单元的高度H1可以约为70μm至100μm。
在示例性实施方式中，第一测试单元的第一宽度M1可以约为75.7μm，第一测试单元的高度H1可以约为84.78μm。
在垂直于显示基板的平面内，第一测试单元可以包括
设置在基底上的第一绝缘层；
设置在所述第一绝缘层上的多个测试有源层，所述多个测试有源层沿着所述第一方向间隔设置，在所述第二方向上平齐；
覆盖所述多个测试有源层的第二绝缘层，以及设置在所述第二绝缘层上的多个测试栅电极和多个测试数据线；所述多个测试栅电极沿着所述第一方向间隔设置，在所述第二方向上平齐；所述多个测试数据线沿着所述第一方向间隔设置，所述多个测试数据线的第一端分别位于所述多个测试有源层邻近显示区域的一侧，所述多个测试数据线的第二端向所述显示区域的方向延伸；
覆盖所述多个测试栅电极和多个测试数据线的第三绝缘层，以及设置在所述第三绝缘层上的多个测试连接线；所述多个测试连接线沿着所述第一方向间隔设置，所述多个测试连接线的第一端分别位于所述多个测试有源层远离显示区域的一侧，所述多个测试连接线的第二端向远离所述显示区域的方向延伸，所述多个测试连接线的第二端与显示区域边缘的距离不同；
覆盖所述多个测试连接线的第四绝缘层，其上设置有多个过孔；
设置在所述第四绝缘层上的多个测试源电极和多个测试漏电极；所述测试源电极通过过孔分别与对应的测试有源层和对应的测试连接线的第一端连接，所述测试连接线的第二端通过过孔与对应的测试数据信号线连接；所述测试漏电极通过过孔分别与对应的测试有源层和对应的测试数据线的第一端连接，所述测试数据线的第二端与所述显示区域的数据信号线连接；所述多个测试栅电极通过过孔与测试控制信号线连接。
在一种示例性实施方式中，第一测试单元的制备过程可以包括如下操 作。
(11)在基底上形成半导体层图案。在示例性实施方式中，在基底上形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖整个基底的第一绝缘层，以及设置在第一绝缘层上的半导体层图案，半导体层图案至少包括第一测试有源层21、第二测试有源层31和第三测试有源层41，如图16所示。
如图10和图16所示，第二测试单元中三个测试有源层沿着第二方向Y间隔设置，在第一方向X上错位设置，而第一测试单元中三个测试有源层沿着第一方向X间隔设置，三个测试有源层在第二方向Y上平齐，因而可以有效减少第一测试电路第二方向Y的尺寸。在示例性实施方式中，三个测试有源层第一方向X的宽度可以约为20μm至25μm，第二方向Y的高度可以约为13μm至19μm。在示例性实施方式中，每个测试有源层的宽度可以约为22.9μm，高度可以约为16μm。在示例性实施方式中，第一测试单元和第二测试单元中三个测试有源层的宽度、高度以及相邻测试有源层之间的间距可以相同，以保证测试效果的一致性。
(12)形成第一金属层图案。在示例性实施方式中，形成第一金属层图案可以包括：在形成前述图案的基底上依次沉积第二绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一金属层图案，第一金属层图案至少包括第一测试栅电极22、第二测试栅电极32、第三测试栅电极42、第一测试数据线23、第二测试数据线33和第三测试数据线43，如图17所示。
如图11和图17所示，第二测试单元中三个测试栅电极是沿着第二方向Y间隔设置，在第一方向X上错位设置，而第一测试单元中三个测试栅电极沿着第一方向X间隔设置，三个测试栅电极在第二方向Y上是平齐的，因而第一测试电路第二方向Y的尺寸可以有效减少。在示例性实施方式中，三个测试栅电极第一方向X的宽度可以约为8μm至11μm。在示例性实施方式中，每个测试栅电极的宽度可以约为9.3μm。在示例性实施方式中，第一测试单元和第二测试单元中三个测试栅电极的宽度以及相邻测试栅电极之间的间距可以相同，以保证测试效果的一致性。在示例性实施方式中，三个测试数据 线沿着第一方向X间隔设置，三个测试数据线的第一端分别位于三个测试有源层邻近显示区域的一侧，三个测试数据线的第二端向显示区域的方向延伸，三个测试数据线的第二端在第二方向Y上是平齐的。
(13)形成第二金属层图案。在示例性实施方式中，形成第二金属层图案可以包括：在形成前述图案的基底上依次沉积第三绝缘薄膜和第二金属薄膜，通过图案化工艺对第二金属薄膜进行图案化，形成覆盖第一金属层图案的第三绝缘层，以及设置在第三绝缘层上的第二金属层图案，第二金属层图案至少包括第一测试连接线24、第二测试连接线34和第三测试连接线44，如图18所示。在示例性实施方式中，三个测试连接线的第一端分别位于三个测试有源层远离显示区域的一侧，三个测试连接线的第二端向远离显示区域的方向延伸，三个测试连接线的第二端与显示区域边缘的距离不同。如图12和图18所示，第二测试单元中三个测试连接线的第一端是沿着第二方向Y间隔设置，而第一测试单元中三个测试连接线的第一端在第二方向Y上是平齐的，因而第一测试电路第二方向Y的尺寸可以有效减少。
(14)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的基底上沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二金属层图案的第四绝缘层，第四绝缘层上开设有多个过孔，如图19所示。在示例性实施方式中，第四绝缘层上的多个过孔可以包括：位于第一测试栅电极22邻近第一测试数据线23一侧且暴露出第一测试有源层21的第一测试过孔V1、位于第一测试栅电极22邻近第一测试连接线24一侧且暴露出第一测试有源层21的第二测试过孔V2、位于第二测试栅电极32邻近第二测试数据线33一侧且暴露出第二测试有源层31的第三测试过孔V3、位于第二测试栅电极32邻近第二测试连接线34一侧且暴露出第二测试有源层31的第四测试过孔V4、位于第三测试栅电极42邻近第三测试数据线43一侧且暴露出第三测试有源层41的第五测试过孔V5、位于第三测试栅电极42邻近第三测试连接线44一侧且暴露出第三测试有源层41的第六测试过孔V6、位于第一测试数据线23邻近第一测试有源层21的第一端且暴露出第一测试数据线23的第七测试过孔V7、位于第二测试数据线33邻近第二测试有源层31的第一端且暴露出第二测试数据线33 的第八测试过孔V8、位于第三测试数据线43邻近第三测试有源层41的第一端且暴露出第三测试数据线43的第九测试过孔V9、位于第一测试连接线24邻近第一测试有源层21的第一端且暴露出第一测试连接线24的第十测试过孔V10、位于第二测试连接线34邻近第二测试有源层31的第一端且暴露出第二测试连接线34的第十一测试过孔V11、位于第三测试连接线44邻近第三测试有源层41的第一端且暴露出第三测试连接线44的第十二测试过孔V12、位于第一测试连接线24远离第一测试有源层21的第二端且暴露出第一测试连接线24的第十三测试过孔V13、位于第二测试连接线34远离第二测试有源层31的第二端且暴露出第二测试连接线34的第十四测试过孔V14、位于第三测试连接线44远离第三测试有源层41的第二端且暴露出第三测试连接线44的第十五测试过孔V12、位于第一测试栅电极22远离第一测试有源层21一端且暴露出第一测试栅电极22的第十六测试过孔V16、位于第二测试栅电极32远离第二测试有源层31一端且暴露出第二测试栅电极32的第十七测试过孔V17、位于第三测试栅电极42远离第三测试有源层41一端且暴露出第三测试栅电极42的第十八测试过孔V18。
如图13和图19所示，由于第二测试电路中三个测试栅电极是相互连接的一体结构，因此只需要一个测试过孔可以实现测试控制信号线与三个测试栅电极连接。而由于第一测试电路中三个测试栅电极是相互隔离的，因此需要设置第十六测试过孔V16、第十七测试过孔V17和第十八测试过孔V18，实现测试控制信号线与三个测试栅电极连接。
(15)形成第三金属层图案。在示例性实施方式中，形成第三金属层图案可以包括：在形成前述图案的基底上沉积第三金属薄膜，通过图案化工艺对第三金属薄膜进行图案化，在第四绝缘层上形成第三金属层图案，第三金属层图案至少包括：第一测试源电极25、第一测试漏电极26、第二测试源电极35、第二测试漏电极36、第三测试源电极45、第三测试漏电极46、第一测试数据信号线27、第二测试数据信号线37、第一测试数据信号线47和测试控制信号线28，如图20所示。
在示例性实施方式中，第一测试漏电极26的一端通过第一测试过孔V1与第一测试有源层21连接，另一端通过第七测试过孔V7与第一测试数据线 23的第一端连接，第一测试数据线23的第二端与显示区域的一个数据信号线连接。第一测试源电极25的一端通过第二测试过孔V2与第一测试有源层21连接，另一端通过第十测试过孔V10与第一测试连接线24的第一端连接，第一测试连接线24的第二端通过第十三测试过孔V13与第一测试数据信号线27连接。第二测试漏电极36的一端通过第三测试过孔V3与第二测试有源层31连接，另一端通过第八测试过孔V8与第二测试数据线33的第一端连接，第二测试数据线33的第二端与显示区域的一个数据信号线连接。第二测试源电极35的一端通过第四测试过孔V4与第二测试有源层31连接，另一端通过第十一测试过孔V11与第二测试连接线34的第一端连接，第二测试连接线34的第二端通过第十四测试过孔V14与第二测试数据信号线37连接。第三测试漏电极46的一端通过第五测试过孔V5与第三测试有源层41连接，另一端通过第九测试过孔V9与第三测试数据线43的第一端连接，第三测试数据线43的第二端与显示区域的一个数据信号线连接。第三测试源电极45的一端通过第六测试过孔V6与第三测试有源层41连接，另一端通过第十二测试过孔V12与第三测试连接线44的第一端连接，第三测试连接线44的第二端通过第十五测试过孔V15与第三测试数据信号线47连接。第一测试栅电极22通过第十六测试过孔V16与测试控制信号线28连接，第二测试栅电极32通过第十七测试过孔V17与测试控制信号线28连接，第三测试栅电极42通过第十八测试过孔V18与测试控制信号线28连接。
在示例性实施方式中，第一测试源电极25远离第一测试有源层21的侧边缘与第一测试漏电极26远离第一测试有源层21的侧边缘之间的距离可以约为20μm至25μm，第二测试源电极35远离第二测试有源层31的侧边缘与第二测试漏电极36远离第二测试有源层31的侧边缘之间的距离可以约为20μm至25μm，第三测试源电极45远离第三测试有源层41的侧边缘与第三测试漏电极46远离第三测试有源层41的侧边缘之间的距离可以约为20μm至25μm。在示例性实施方式中，测试源电极的侧边缘与测试漏电极的侧边缘之间的距离可以约为22.9μm。在示例性实施方式中，第一测试单元和第二测试单元中三个测试源电极和三个测试漏电极的尺寸可以相同，以保证测试效果的一致性。
在示例性实施方式中，第一测试有源层21、第一测试栅电极22、第一测试源电极25和第一测试漏电极26组成第一测试晶体管TC1；第二测试有源层31、第二测试栅电极32、第二测试源电极35和第二测试漏电极36组成第二测试晶体管TC2；第三测试有源层41、第三测试栅电极42、第三测试源电极45和第三测试漏电极46组成第三测试晶体管TC3；第一测试晶体管TC1、第二测试晶体管TC2和第三测试晶体管TC3组成一个测试单元。第一测试栅电极22、第二测试栅电极32和第三测试栅电极42均连接同一个测试控制信号线28，第一测试漏电极26、第二测试漏电极36和第三测试漏电极46分别通过第一测试数据线23、第二测试数据线33和第三测试数据线43连接显示区域不同的数据信号线，第一测试源电极25、第二测试源电极35和第三测试源电极45分别通过第一测试连接线24、第二测试连接线34和第三测试连接线44分别连接第一测试数据信号线27、第二测试数据信号线37和第一测试数据信号线47。在进行测试时，通过控制装置向测试控制信号线28提供导通信号，控制第一测试晶体管TC1、第二测试晶体管TC2和第三测试晶体管TC3导通，第一测试数据信号线27、第二测试数据信号线37和第一测试数据信号线47提供的测试数据信号传输给显示区域中多个数据信号线。
本公开所示第一测试电路的结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，测试连接线可以设置在第一金属层中，测试数据线可以设置在第二金属层中。又如，测试栅电极、测试连接线和测试数据线可以设置同层设置，且通过同一次构图工艺形成。再如，第一测试电路还可以设置其它电极、引线或膜层，本公开在此不做限定。
在示例性实施方式中，第一测试单元和第二测试单元可以通过同一次制备过程同时形成。第一测试单元的半导体层图案和第二测试单元的半导体层图案同层设置且通过同一次构图工艺形成，第一测试单元的第一金属层图案和第二测试单元的第一金属层图案同层设置且通过同一次构图工艺形成，第一测试单元的第二金属层图案和第二测试单元的第二金属层图案同层设置且通过同一次构图工艺形成，第一测试单元的第四绝缘层过孔图案和第二测试 单元的第四绝缘层过孔图案同层设置且通过同一次构图工艺形成，第一测试单元的第三金属层图案和第二测试单元的第三金属层图案同层设置且通过同一次构图工艺形成，本公开在此不做限定。
图21为本公开示例性实施例一种第一测试单元的布局结构图。如图21所示，在示例性实施方式中，矩形倒圆角的显示基板包括显示区域和边框区域，显示区域包括矩阵方式排布的多个子像素P，边框区域中弧形的第一角部设置有测试电路(CT)、栅极驱动电路(GOA)以及相应的信号线。在示例性实施方式中，测试电路为第一测试电路，测试电路包括的多个测试单元80为第一测试单元，每个测试单元80分别与测试控制信号线、测试数据信号线以及显示区域的数据信号线连接，测试单元80配置为向显示区域的多个数据信号线提供测试数据信号。栅极驱动电路可以包括多个级联的移位寄存器单元110，每个移位寄存器单元110分别与初始信号线、时钟信号线以及显示区域的扫描信号线连接，移位寄存器单元110配置为向显示区域的至少一个扫描信号线提供栅极驱动信号。在示例性实施方式中，边框区域的第二角部的电路结构和第一角部区域的电路结构可以相同。
在示例性实施方式中，第一角部211的信号线采用阶梯形走线方式，测试单元80和移位寄存器单元110分别设置在不同的阶梯之上。信号线包括第一走线、第二走线和第三走线，第三走线位于显示区域与第二走线之间，第二走线位于第一走线和第三走线之间，第一走线和第二走线之间围成多个第一矩形，多个移位寄存器单元110分别位于多个第一矩形中，第二走线和第三走线之间围成多个第二矩形，多个测试单元80分别位于多个第二矩形中。
在示例性实施方式中，第一走线可以包括阶梯状走线的栅信号线121，第二走线可以包括阶梯状走线的测试信号线122，第三走线可以包括阶梯状走线的电源信号线123，电源信号线123与显示区域边缘的最小距离小于测试信号线122与显示区域边缘的最小距离，测试信号线122与显示区域边缘的最小距离小于栅信号线121与显示区域边缘的最小距离。阶梯状走线的栅信号线121与阶梯状走线的测试信号线122之间围成多个第一矩形，多个移位寄存器单元110以阶梯状排布分别设置在多个第一矩形中，即多个移位寄存器单元110分别设置在测试信号线122所形成的多个阶梯上。阶梯状走线 的测试信号线122与阶梯状走线的电源信号线123之间围成多个第二矩形，多个测试单元80以阶梯状排布分别设置在多个第二矩形中，即多个移位寄存器单元110分别设置在电源信号线123所形成的多个阶梯之上。
在示例性实施方式中，第二矩形为第一方向X为长边、第二方向Y为短边的矩形，即第二矩形长边的延伸方向与第一方向X平行。
在示例性实施方式中，栅信号线121、测试信号线122和电源信号线123均可以包括沿着显示区域边缘、在第二方向Y上依次设置的多个第一横线组和多个第一竖线组，第一横线组包括多个向第一方向X的反方向延伸的第一横线，第一竖线组包括多个向第二方向Y延伸的第一竖线，第一横线组和第一竖线组交替设置，且第一横线组中的多个第一横线与第一竖线组中的多个第一竖线依次连接，形成阶梯状走线。在示例性实施方式中，第一横线组和第一竖线组之间可以设置过渡线组。
在示例性实施方式中，第一角部211的同一个第一矩形中，可以设置至少两个移位寄存器单元。
在示例性实施方式中，第一角部211的同一个第二矩形中，可以设置一个第一测试单元。
在示例性实施方式中，栅信号线121可以包括1个初始信号线和4个时钟信号线，测试信号线122可以包括1个测试控制信号线和3个测试数据信号线，电源信号线123可以包括第二电源线VDD和初始信号线INIT。
在示例性实施方式中，栅信号线121远离显示区域的一侧还可以设置第一电源线VSS，第一电源线VSS配置为向显示区域每个子像素中的像素驱动电路提供低电平信号。
在示例性实施方式中，电源信号线123与显示区域之间还可以设置至少一个补偿电容120，补偿电容120可以包括多个子电容，补偿电容120配置为对所在列子像素中的像素驱动电路提供电容补偿。在示例性实施方式中，补偿电容120包括第一极板和第二极板，第一极板通过电源连接线连接第二电源线VDD，补偿电容120的第二极板连接数据信号线。在示例性实施方式中，补偿电容120的第二极板邻近测试单元80的一端连接测试数据信号线，邻近显示区域的另一端连接显示区域的数据信号线，即测试电路的测试数据 信号线通过补偿电容的第二极板与显示区域的数据信号线连接。
在示例性实施方式中，测试信号线122(第二走线)包括阶梯状走线的测试控制信号线和阶梯状走线的测试数据信号线，测试数据信号线与显示区域边缘的最小距离小于测试控制信号线与显示区域边缘的最小距离。在示例性实施方式中，阶梯状走线的测试控制信号线与阶梯状走线的测试数据信号线之间可以围成至少一个第三矩形，至少一个第三矩形中设置有虚拟单元130。在示例性实施方式中，虚拟(Dummy)单元可以包括多个晶体管，晶体管的结构可以与移位寄存器单元中晶体管的结构相同，但与移位寄存器单元中的晶体管没有电连接，以提高刻蚀均一性，提高制备质量。在示例性实施方式中，第三矩形为第一方向X为长边、第二方向Y为短边的矩形，即第三矩形长边的延伸方向与第一方向X平行。
一种矩形倒圆角的显示基板中，上边框(第三边框)比较宽，空间比较充足，左边框(第一边框)和右边框(第二边框)比较窄，由于角部处边框是由较窄的左边框和较宽的上边框(或者由较窄的右边框和较宽的上边框)渐变相接，因而邻近左边框(或者右边框)的角部是减小角部处边框的瓶颈。本公开示例性实施例通过将第一角部和第二角部内的信号线设置成阶梯形走线方式，阶梯状走线的栅信号线与阶梯状走线的测试信号线之间围成多个第一矩形，阶梯状走线的测试信号线与阶梯状走线的电源信号线之间围成多个第二矩形，多个移位寄存器单元以阶梯状排布设置在多个第一矩形中，多个测试单元以阶梯状排布设置在多个第二矩形中，测试单元和移位寄存器单元分别设置在不同的阶梯之上，最大限度地有效利用角部空间，只需要较小的倒角半径便能够满足电路所需的空间，有效缩减了圆角区域的宽度，实现了窄边框，提高了屏占比，有利于实现全面屏显示。
在示例性实施方式中，由于第一测试单元中三个测试晶体管是沿着第一方向X间隔设置，三个测试晶体管在第二方向Y上是平齐的，因而第一测试单元具有较小的高度，在第一角部211内以阶梯排布方式设置多个第一测试单元的设计中，第一测试单元较小的高度不仅减小了第一测试单元占用第二方向Y的空间，而且减小了阶梯排布占用第一方向X的空间，最大限度地有效利用角部空间，只需要较小的倒角半径便能够满足电路所需的空间，有效 缩减了角部区域的宽度。
在示例性实施方式中，多个第二测试单元以并列排布方式设置在第三边框203内，即第三边框203内的多个第二测试单元沿第一方向X依次设置，在第二方向Y上是平齐的。由于第二测试单元中三个测试晶体管是沿着第二方向Y依次设置，在第一方向X上错位设置，因而第二测试单元的形状具有宽度小、高度大的特点。在第三边框(上边框)203内设置多个第二测试单元的设计中，可以在保证第三边框203能够放置所需数量的第二测试单元的前提下，可以通过增加第二测试单元的宽度来尽可能减小第二测试单元的高度，最大限度地缩减上边框的宽度，实现了窄边框，提高了屏占比，有利于实现全面屏显示。
一种显示基板中，测试信号线可以包括4个信号线，分别为1个测试控制信号线和3个测试数据信号线，上边框(第三边框)、左边框(第一边框)和右边框(第二边框)内均设置4个信号线，左边框和右边框中的4个信号线沿着第二方向Y延伸并引入到下边框(第四边框)中的绑定引脚，因而显示基板的上边框、左边框和右边框中均设置有4个信号线。本公开示例性实施例中，上边框、第一角部和第二角部均设置4个信号线，而左边框中只设置有2个信号线，2个信号线沿着第二方向Y延伸并引入到下边框中的绑定引脚，右边框中只设置有2个信号线，2个信号线沿着第二方向Y延伸并引入到下边框中的绑定引脚。在示例性实施方式中，可以在左边框中设置2个测试数据信号线，在右边框中设置1个测试控制信号线和1个测试数据信号线，或者，可以在左边框中设置1个测试控制信号线和1个测试数据信号线，在右边框中设置2个测试数据信号线，本公开在此不做限定。通过在左边框和右边框中分别设置2个信号线，可以减小左边框和右边框的宽度，有利于实现窄边框。
图22为本公开示例性实施例一种多路复用单元的布局结构图。如图22所示，在示例性实施方式中，矩形倒圆角的显示基板包括显示区域和边框区域，显示区域包括矩阵方式排布的多个子像素P，边框区域的第三角部213设置有多路复用电路(MUX)、栅极驱动电路(GOA)以及相应的信号线。在示例性实施方式中，多路复用电路可以包括多个复用单元90，每个复用单 元90连接显示区域的多个数据信号线，复用单元90配置为使一个信号源为多个数据信号线提供数据信号。栅极驱动电路可以包括多个级联的移位寄存器单元110，每个移位寄存器单元110连接显示区域的至少一个扫描信号线，移位寄存器单元110配置为向显示区域的至少一个扫描信号线提供栅极驱动信号。在示例性实施方式中，边框区域的第四角部的电路结构和第三角部区域的电路结构可以相同。
在示例性实施方式中，第三角部213的信号线采用阶梯形走线方式，复用单元90和移位寄存器单元110分别设置在不同的阶梯之上。信号线包括第一走线、第二走线和第三走线，第三走线位于显示区域与第二走线之间，第二走线位于第一走线和第三走线之间，第一走线和第二走线之间围成多个第一矩形，多个移位寄存器单元110分别位于多个第一矩形中，第二走线和第三走线之间围成多个第二矩形，多个复用单元90分别位于多个第二矩形中。
在示例性实施方式中，第二矩形为第一方向X为长边、第二方向Y为短边的矩形，即第二矩形长边的延伸方向与第一方向X平行。
在示例性实施方式中，第一走线可以包括阶梯状走线的栅信号线121，第二走线可以包括阶梯状走线的复用信号线124，第三走线可以包括阶梯状走线的电源信号线123，电源信号线123与显示区域边缘的距离小于复用信号线124与显示区域边缘的距离，复用信号线124与显示区域边缘的距离小于栅信号线121与显示区域边缘的距离。阶梯状走线的栅信号线121与阶梯状走线的复用信号线124之间围成多个第一矩形，多个移位寄存器单元110以阶梯状排布设置在多个第一矩形中，即多个移位寄存器单元110分别设置在栅信号线121所形成的多个阶梯上。阶梯状走线的复用信号线124与阶梯状走线的电源信号线123之间围成多个第二矩形，多个复用单元90以阶梯状排布设置在多个第二矩形中，即多个移位寄存器单元110分别设置在复用信号线124所形成的多个阶梯之上。
在示例性实施方式中，栅信号线121、复用信号线124和电源信号线123均可以包括沿着显示区域边缘、在第二方向Y上依次设置的多个第二横线组和多个第二竖线组，第二横线组包括多个向第一方向X延伸的第二横线，第二竖线组包括多个向第二方向Y延伸的第二竖线，第二横线组和第二竖线组 交替设置，且第二横线组中的多个第二横线与第二竖线组中的多个第二竖线依次连接，形成阶梯状走线。在示例性实施方式中，第二横线组和第二竖线组之间可以设置过渡线组。
在示例性实施方式中，第三角部213的同一个第一矩形中，可以设置至少一个移位寄存器单元。
在示例性实施方式中，第三角部213的同一个第二矩形中，可以设置一个复用单元。
在示例性实施方式中，栅信号线121可以包括1个初始信号线和4个时钟信号线，复用信号线124可以包括3个复用控制信号线和1个复用数据信号线，电源信号线123可以包括第二电源线VDD和初始信号线INIT，栅信号线121远离显示区域的一侧还可以设置第一电源线VSS。
一种显示基板中，第三角部和第四角部中的信号线采用圆弧形走线方式，复用单元和移位寄存器单元沿着圆弧形走线依次排列，复用单元和移位寄存器单元交替设置在圆弧形走线之间。研究表明，复用单元和移位寄存器单元的这种排布需要较大的倒角半径才能满足电路所需的空间，使得下方圆角区域的边框窄化成为设计瓶颈。本公开示例性实施例通过将第三角部和第四角部内的信号线设置成阶梯形走线方式，阶梯状走线的栅信号线与阶梯状走线的复用信号线之间围成多个第一矩形，阶梯状走线的复用信号线与阶梯状走线的电源信号线之间围成多个第二矩形，多个移位寄存器单元以阶梯状排布设置在多个第一矩形中，多个复用单元以阶梯状排布设置在多个第二矩形中，复用单元和移位寄存器单元分别设置在不同的阶梯之上，最大限度地有效利用角部空间，只需要较小的倒角半径便能够满足电路所需的空间，有效缩减了圆角区域的宽度，实现了窄边框，提高了屏占比，有利于实现全面屏显示。
图23为本公开示例性实施例一种复用单元的结构示意图，示意了复用单元包括三个复用晶体管。如图23所示，在平行于显示基板的平面内，复用单元包括三个复用晶体管，三个测试晶体管沿第一方向X依次设置，在第二方向Y上平齐。第一复用晶体管TF1的复用栅电极(控制极)连接第一复用控制信号线57，第二复用晶体管TF2的复用栅电极(控制极)连接第二复用控制信号线67，第三复用晶体管TF1的复用栅电极(控制极)连接第三复用控 制信号线77。第一复用晶体管TF1的复用源电极(第一极)、第二复用晶体管TF2的复用源电极(第一极)和第三复用晶体管TF3的复用源电极(第一极)均连接复用数据信号线58。第一复用晶体管的复用漏电极(第二极)连接显示区域的一个数据信号线，第二复用晶体管的复用漏电极(第二极)连接显示区域的另一个数据信号线，第三复用晶体管的复用漏电极(第二极)连接显示区域的又一个数据信号线。
在示例性实施方式中，复用单元的高度可以小于移位寄存器单元的高度。
在示例性实施方式中，移位寄存器单元的高度可以约为复用单元的高度的1.5倍至2倍。
在示例性实施方式中，复用单元可以为矩形状，复用单元的高度(第三高度H3)为复用单元的宽度(第三宽度M3)的0.5倍至0.9倍。
在示例性实施方式中，复用单元的高度(第三高度H3)可以约为35μm至45μm，复用单元的宽度(第三宽度M3)可以约为48μm至70μm，移位寄存器单元的高度可以约为68μm至70μm。
在示例性实施方式中，与采用圆弧形交替排列的复用单元相比，本公开示例性实施例中复用单元的高度可以减少50％至60％。
在示例性实施方式中，复用单元的高度可以约为40μm，复用单元的宽度(第三宽度M3)可以约为59μm。
在垂直于显示基板的平面内，复用单元可以包括：
设置在基底上的第一绝缘层；
设置在所述第一绝缘层上的多个复用有源层，所述多个复用有源层沿着所述第一方向间隔设置，在所述第二方向上平齐；
覆盖所述多个复用有源层的第二绝缘层，以及设置在所述第二绝缘层上的多个复用栅电极和多个复用数据线；所述多个复用栅电极沿着所述第一方向间隔设置，所述多个复用栅电极邻近所述显示区域的第一端在所述第二方向上平齐，所述多个复用栅电极远离所述显示区域的第二端与显示区域边缘的距离不同；所述多个复用数据线的第一端分别位于所述多个复用有源层邻近显示区域的一侧，所述多个复用数据线的第二端向所述显示区域的方向延 伸；
覆盖所述多个复用栅电极和多个复用数据线的第三绝缘层，以及设置在所述第三绝缘层上的多个复用连接线，所述多个复用连接线沿着所述第一方向间隔设置，所述多个复用连接线的第一端分别位于所述多个测试有源层远离显示区域的一侧，所述多个复用连接线的的第二端向远离所述显示区域的方向延伸；
覆盖所述多个复用连接线的第四绝缘层，其上设置有多个过孔；
设置在所述第四绝缘层上的多个复用源电极和多个复用漏电极；所述复用源电极通过过孔分别与对应的复用有源层和对应的复用连接线的第一端连接，复用连接线的第二端通过过孔与复用数据信号线连接；所述复用漏电极通过过孔分别与对应的复用有源层和对应的复用数据线的第一端连接，所述复用数据线的第二端与所述显示区域的数据信号线连接；所述复用栅电极的第二端通过过孔与对应的复用控制信号线连接。
在一种示例性实施方式中，复用单元的制备过程可以包括如下操作。
(21)在基底上形成半导体层图案。在示例性实施方式中，在基底上形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖整个基底的第一绝缘层，以及设置在第一绝缘层上的半导体层图案，半导体层图案至少包括第一复用有源层51、第二复用有源层61和第三复用有源层71，如图24所示。在示例性实施方式中，三个复用有源层沿着第一方向X间隔设置，在第二方向Y上平齐，因而可以有效减少复用电路第二方向Y的尺寸。在示例性实施方式中，三个复用有源层第一方向X的宽度可以约为14μm至21μm，第二方向Y的高度可以约为20μm至30μm。在示例性实施方式中，每个测试有源层的宽度可以约为17.3μm，高度可以约为25μm。
(22)形成第一金属层图案。在示例性实施方式中，形成第一金属层图案可以包括：在形成前述图案的基底上依次沉积第二绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一金属层图案，第一金属层图案 至少包括第一复用栅电极52、第二复用栅电极62、第三复用栅电极72、第一复用数据线53、第二复用数据线63和第三复用数据线73，如图25所示。在示例性实施方式中，三个复用栅电极沿着第一方向X间隔设置，三个复用栅电极邻近显示区域的第一端在在第二方向Y上平齐，因而可以有效减少复用电路第二方向Y的尺寸，三个复用栅电极远离显示区域的第二端与显示区域边缘的距离不同，配置为分别连接后续形成的复用控制信号线。在示例性实施方式中，三个复用数据线沿着第一方向X间隔设置，三个复用数据线的第一端分别位于三个复用有源层邻近显示区域的一侧，三个复用数据线的第二端向显示区域的方向延伸，配置为分别连接显示区域的数据信号线。在示例性实施方式中，三个测试栅电极第一方向X的宽度可以约为5μm至7μm。在示例性实施方式中，每个测试栅电极的宽度可以约为6μm。
(23)形成第二金属层图案。在示例性实施方式中，形成第二金属层图案可以包括：在形成前述图案的基底上依次沉积第三绝缘薄膜和第二金属薄膜，通过图案化工艺对第二金属薄膜进行图案化，形成覆盖第一金属层图案的第三绝缘层，以及设置在第三绝缘层上的第二金属层图案，第二金属层图案至少包括第一复用连接线54、第二复用连接线64和第三复用连接线74，如图26所示。在示例性实施方式中，三个复用连接线沿着第一方向X间隔设置，三个复用连接线的第一端分别位于多个测试有源层远离显示区域的一侧，三个复用连接线的的第二端向远离显示区域的方向延伸，配置为同时连接后续形成的复用数据信号线。
(24)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的基底上沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二金属层图案的第四绝缘层，第四绝缘层上开设有多个过孔，如图27所示。在示例性实施方式中，第四绝缘层上的多个过孔可以包括：位于第一复用栅电极52邻近第一复用连接线54一侧且暴露出第一复用有源层51的多个第一复用过孔K1、位于第一复用栅电极52邻近第一复用数据线53一侧且暴露出第一复用有源层51的多个第二复用过孔K2、位于第二复用栅电极62邻近第二复用连接线64一侧且暴露出第二复用有源层61的多个第三复用过孔K3、位于第二复用栅电极62邻近第二 复用数据线63一侧且暴露出第二复用有源层61的多个第四复用过孔K4、位于第三复用栅电极72邻近第三复用连接线74一侧且暴露出第三复用有源层71的多个第五复用过孔K5、位于第三复用栅电极72邻近第三复用数据线73一侧且暴露出第三复用有源层71的多个第六复用过孔K6、位于第一复用数据线53邻近第一复用有源层51的第一端且暴露出第一复用数据线53的第七复用过孔K7、位于第二复用数据线63邻近第二复用有源层61的第一端且暴露出第二复用数据线63的第八复用过孔K8、位于第三复用数据线73邻近第三复用有源层71的第一端且暴露出第三复用数据线73的第九复用过孔K9、位于第一复用连接线54邻近第一复用有源层51的第一端且暴露出第一复用连接线54的第十复用过孔K10、位于第二复用连接线64邻近第二复用有源层61的第一端且暴露出第二复用连接线64的第十一复用过孔K11、位于第三复用连接线74邻近第三复用有源层71的第一端且暴露出第三复用连接线74的第十二复用过孔K12、位于第一复用连接线54远离第一复用有源层51的第二端且暴露出第一复用连接线54的第十三复用过孔K13、位于第二复用连接线64远离第二复用有源层61的第二端且暴露出第二复用连接线64的第十四复用过孔K14、位于第三复用连接线74远离第三复用有源层71的第二端且暴露出第三复用连接线74的第十五复用过孔K15、位于第一复用栅电极52远离第一复用有源层51的第二端且暴露出第一复用栅电极52的第十六复用过孔K16、位于第二复用栅电极62远离第二复用有源层61的第二端且暴露出第二复用栅电极62的第十七复用过孔K17、位于第三复用栅电极72远离第三复用有源层71的第二端且暴露出第三复用栅电极72的第十八复用过孔K18。
(25)形成第三金属层图案。在示例性实施方式中，形成第三金属层图案可以包括：在形成前述图案的基底上沉积第三金属薄膜，通过图案化工艺对第三金属薄膜进行图案化，在第四绝缘层上形成第三金属层图案，第三金属层图案至少包括：第一复用源电极55、第一复用漏电极56、第二复用源电极65、第二复用漏电极66、第三复用源电极75、第三复用漏电极76、第一复用控制信号线57、第二复用控制信号线67、第一复用控制信号线77和复用数据信号线58，如图28所示。在示例性实施方式中，第一复用源电极55的一端通过第一复用过孔K1与第一复用有源层51连接，另一端通过第十复 用过孔K10与第一复用连接线54的第一端连接。第一复用漏电极56的一端通过第二复用过孔K2与第一复用有源层51连接，另一端通过第七复用过孔K7与第一复用数据线53的第一端连接，第一复用数据线53的第二端与显示区域的数据信号线连接。第二复用源电极65的一端通过第三复用过孔K3与第二复用有源层61连接，另一端通过第十一复用过孔K11与第二复用连接线64的第一端连接。第二复用漏电极66的一端通过第四复用过孔K4与第二复用有源层61连接，另一端通过第八复用过孔K8与第二复用数据线63的第一端连接，第二复用数据线63的第二端与显示区域的数据信号线连接。第三复用源电极75的一端通过第五复用过孔K5与第三复用有源层71连接，另一端通过第十二复用过孔K12与第三复用连接线74的第一端连接。第三复用漏电极76的一端通过第六复用过孔K6与第三复用有源层71连接，另一端通过第九复用过孔K9与第三复用数据线73的第一端连接，第三复用数据线73的第二端与显示区域的数据信号线连接。第一复用控制信号线57通过第十六复用过孔K16与第一复用栅电极52的第二端连接，第二复用控制信号线67通过第十七复用过孔K17与第二复用栅电极62的第二端连接，第三复用控制信号线77通过第十八复用过孔K18与第三用栅电极72的第二端连接。复用数据信号线58分别通过第十三复用过孔K13、第十四复用过孔K14和第十五复用过孔K15与第一复用连接线54的第二端、第二复用连接线64的第二端和第三复用连接线74的第二端连接。
在示例性实施方式中，第一复用源电极远离第一复用有源层的侧边缘与第一复用漏电极远离第一复用有源层的侧边缘之间的距离可以约为14μm至21μm，第二复用源电极远离第二复用有源层的侧边缘与第二复用漏电极远离第二复用有源层的侧边缘之间的距离可以约为14μm至21μm，第三复用源电极远离第三复用有源层的侧边缘与第三复用漏电极远离第三复用有源层的侧边缘之间的距离可以约为14μm至21μm。在示例性实施方式中，每个复用源电极的侧边缘与复用漏电极的侧边缘之间的距离可以约为17.3μm。
在示例性实施方式中，第一复用有源层51、第一复用栅电极52、第一复用源电极55和第一复用漏电极56组成第一复用晶体管TF1；第二复用有源层61、第二复用栅电极62、第二复用源电极65和第二复用漏电极66组成第 二复用晶体管TF2；第三复用有源层71、第三复用栅电极72、第三复用源电极75和第三复用漏电极76组成第三复用晶体管TF3；第一复用晶体管TF1、第二复用晶体管TF2和第三复用晶体管TF3组成一个复用单元。第一复用栅电极52连接第一复用控制信号线57，第二复用栅电极62连接第二复用控制信号线67，第三复用栅电极72连接第三复用控制信号线77，第一复用源电极55、第二复用源电极65和第三复用源电极75分别通过第一复用连接线54、第二复用连接线64和第三复用连接线74连接同一个复用数据信号线58，第一复用漏电极56、第二复用漏电极66和第三复用漏电极76分别通过第一复用数据线53、第二复用数据线63和第三复用数据线73连接显示区域不同的的数据信号线。在显示过程中，通过控制装置分时向第一复用控制信号线57、第二复用控制信号线67和第三复用控制信号线77提供导通信号，使第一复用晶体管TF1、第二复用晶体管TF2和第三复用晶体管TF3分时导通，在任一复用晶体管导通时，复用数据信号线58提供与导通的复用晶体管连接的数据信号线所需的数据信号，将数据信号写入相应的子像素。
本公开示例性实施例提出了一种多路复用电路结构，通过多个复用晶体管沿第一方向依次设置，在第二方向上平齐，在不改变薄膜晶体管尺寸的前提下，有效减小了复用单元的高度，结合第三角部和第四角部内信号线的阶梯形走线方式，复用单元沿着复用信号线阶梯设置，移位寄存器单元沿着栅信号线阶梯设置，复用单元和移位寄存器单元分别设置在不同的阶梯之上，最大限度地有效利用角部空间，只需要较小的倒角半径便能够满足电路所需的空间，有效缩减了下边框和下方圆角区域的宽度，实现了窄边框，提高了屏占比，有利于实现全面屏显示。
本公开所示复用单元的结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，复用连接线可以设置在第一金属层中，复用数据线可以设置在第二金属层中。又如，复用栅电极、复用连接线和复用数据线可以设置同层设置，且通过同一次构图工艺形成。再如，复用单元还可以设置其它电极、引线或膜层，本公开在此不做限定。
在示例性实施方式中，前述的测试单元和复用单元可以通过同一次制备 过程同时形成。测试单元的半导体层图案和复用单元的半导体层图案同层设置且通过同一次构图工艺形成，测试单元的第一金属层图案和复用单元的第一金属层图案同层设置且通过同一次构图工艺形成，测试单元的第二金属层图案和复用单元的第二金属层图案同层设置且通过同一次构图工艺形成，测试单元的第四绝缘层过孔图案和复用单元的第四绝缘层过孔图案同层设置且通过同一次构图工艺形成，测试单元的第三金属层图案和复用单元的第三金属层图案同层设置且通过同一次构图工艺形成，本公开在此不做限定。
在示例性实施方式中，边框区域的测试单元和复用单元可以与显示区域的像素驱动电路可以在同一次制备过程中同时形成。例如，测试单元和复用单元的半导体层图案可以与像素驱动电路中薄膜晶体管的有源层同层设置且通过同一次构图工艺形成，测试单元和复用单元的第一金属层图案可以与像素驱动电路中薄膜晶体管的栅电极同层设置且通过同一次构图工艺形成，测试单元和复用单元的第二金属层图案可以与像素驱动电路中薄膜晶体管的第二电容极板同层设置且通过同一次构图工艺形成，测试单元和复用单元的第三金属层图案可以与像素驱动电路中薄膜晶体管的源电极和漏电极同层设置且通过同一次构图工艺形成，本公开在此不做限定。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层可称之为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层可称之为栅绝缘(GI)层，第四绝缘层可称之为层间绝缘(ILD)层。第一金属薄膜、第二金属薄膜和第三金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或多种，或者上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。有源层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。基于氧化物技术的有源层可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、 包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物、包含铟和镓和锌的氧化物等。
本公开示例性实施例还提供了一种显示基板的制备方法，所述显示基板包括显示区域和位于所述显示区域周边的边框区域；所述边框区域包括在所述第一方向上相对设置的第一边框和第二边框、在所述第二方向上相对设置的第三边框和第四边框、连接所述第一边框和第三边框的第一角部、连接所述第二边框和第三边框的第二角部、连接所述第一边框和第四边框的第三角部以及连接所述第二边框和第四边框的第四角部，所述第一角部至第四角部中的至少一个为弧形的角部，所述第一方向为所述显示区域中扫描信号线的延伸方向，所述第二方向为所述显示区域中数据信号线的延伸方向；所述制备方法包括：
在所述显示区域内形成显示结构，在所述第一角部至第四角部的至少一个中形成第一走线、第二走线和多个移位寄存器单元；
所述第一走线和第二走线之间围成多个第一矩形，多个移位寄存器单元分别位于所述多个第一矩形中。
在示例性实施方式中，所述第一角部至第四角部的至少一个中还形成有第三走线，所述第三走线位于所述显示区域与所述第二走线之间，第三走线和第二走线之间围成多个第二矩形。
本公开示例性实施例还提供了一种显示装置，包括前述实施例的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。在示例性实施方式中，显示装置可以为穿戴式显示装置，能通过某些方式佩戴在人体上，如智能手表、智能手环等。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的 权利要求的范围当中。

Claims (24)

  1. 一种显示基板，包括显示区域和位于所述显示区域周边的边框区域；所述边框区域包括在第一方向上相对设置的第一边框和第二边框、在第二方向上相对设置的第三边框和第四边框、连接所述第一边框和第三边框的第一角部、连接所述第二边框和第三边框的第二角部、连接所述第一边框和第四边框的第三角部以及连接所述第二边框和第四边框的第四角部，所述第一角部至第四角部中的至少一个为弧形的角部，所述第一方向为所述显示区域中扫描信号线的延伸方向，所述第二方向为所述显示区域中数据信号线的延伸方向；所述第一角部至第四角部的至少一个中设置有第一走线和第二走线，所述第一走线和第二走线之间围成多个第一矩形，多个移位寄存器单元分别位于所述多个第一矩形中。
  2. 根据权利要求1所述的显示基板，其中，所述第一角部至第四角部的至少一个中还设置有第三走线，所述第三走线位于所述显示区域与所述第二走线之间，第二走线和第三走线之间围成多个第二矩形。
  3. 根据权利要求2所述的显示基板，其中，所述第二矩形为长方形，所述第二矩形长边的延伸方向与所述第一方向平行。
  4. 根据权利要求2所述的显示基板，其中，所述第一角部和第二角部的至少一个中设置有多个第一测试单元，所述多个第一测试单元分别位于所述多个第二矩形中。
  5. 根据权利要求4所述的显示基板，其中，所述第一角部和第二角部的至少一个中，同一个第二矩形中设置至少一个第一测试单元。
  6. 根据权利要求4所述的显示基板，其中，所述第一角部和第二角部的至少一个中，同一个第一矩形中设置至少两个移位寄存器单元。
  7. 根据权利要求4所述的显示基板，其中，所述第一走线包括阶梯状走线的栅信号线，所述第二走线包括阶梯状走线的测试信号线，所述第三走线包括阶梯状走线的电源信号线，所述电源信号线与显示区域边缘的最小距离小于所述测试信号线与显示区域边缘的最小距离，所述测试信号线与显示 区域边缘的最小距离小于所述栅信号线与显示区域边缘的最小距离。
  8. 根据权利要求7所述的显示基板，其中，所述测试信号线包括至少一个测试控制信号线和多个测试数据信号线；所述第一测试单元包括多个测试晶体管，所述多个测试晶体管沿所述第一方向排布；所述多个测试晶体管的控制极连接相同的测试控制信号线，所述多个测试复用晶体管的第一极分别连接不同的测试数据信号线，所述多个复用晶体管的第二极分别连接显示区域中不同的数据信号线。
  9. 根据权利要求8所述的显示基板，其中，所述多个测试晶体管沿所述第一方向排布包括：所述测试晶体管沿所述第一方向依次设置，在所述第二方向上平齐。
  10. 根据权利要求8所述的显示基板，其中，所述测试控制信号线与测试数据信号线之间围成至少一个第三矩形，至少一个第三矩形中设置有虚拟单元。
  11. 根据权利要求8所述的显示基板，其中，所述电源信号线与显示区域之间设置有至少一个补偿电容，所述补偿电容包括第一极板和第二极板，所述第一极板与第二电源线连接，所述第二极板的一端与第一测试单元的测试数据信号线连接，所述第二极板的另一端与显示区域的数据信号线连接。
  12. 根据权利要求4所述的显示基板，其中，所述第一测试单元的高度为所述第一测试单元的宽度的0.9倍至1.3倍；所述第一测试单元的高度为所述第一测试单元第一方向的尺寸，所述第一测试单元的宽度为所述第一测试单元第二方向的尺寸。
  13. 根据权利要求4所述的显示基板，其中，所述第一测试单元的高度为70μm至100μm，所述第一测试单元的宽度为60μm至90μm。
  14. 根据权利要求2所述的显示基板，其中，所述第三角部和第四角部的至少一个中设置有多个复用单元，所述多个复用单元分别位于所述多个第二矩形中。
  15. 根据权利要求14所述的显示基板，其中，所述第三角部和第四角部的至少一个中，同一个第二矩形中设置至少一个复用单元。
  16. 根据权利要求14所述的显示基板，其中，所述第三角部和第四角部的至少一个中，同一个第一矩形中设置至少一个移位寄存器单元。
  17. 根据权利要求14所述的显示基板，其中，所述第一走线包括阶梯状走线的栅信号线，所述第二走线包括阶梯状走线的复用信号线，所述第三走线包括阶梯状走线的电源信号线，所述电源信号线与显示区域边缘的最小距离小于所述复用信号线与显示区域边缘的最小距离，所述复用信号线与显示区域边缘的最小距离小于所述栅信号线与显示区域边缘的最小距离。
  18. 根据权利要求17所述的显示基板，其中，所述复用信号线包括多个复用控制信号线和至少一个复用数据信号线；所述复用单元包括多个复用晶体管，所述多个复用晶体管沿所述第一方向排布；所述多个复用晶体管的控制极分别连接不同的复用控制信号线，所述多个复用晶体管的第一极连接相同的复用数据信号线，所述多个复用晶体管的第二极分别连接显示区域中不同的数据信号线。
  19. 根据权利要求18所述的显示基板，其中，所述多个复用晶体管沿所述第一方向排布包括：所述复用晶体管沿所述第一方向依次设置，在所述第二方向上平齐。
  20. 根据权利要求14所述的显示基板，其中，所述复用单元的高度为所述复用单元的宽度的0.5倍至0.9倍；所述复用单元的高度为所述复用单元第一方向的尺寸，所述复用单元的宽度为所述复用单元第二方向的尺寸。
  21. 根据权利要求14所述的显示基板，其中，所述复用单元的高度为35μm至45μm，所述复用单元的宽度为48μm至70μm。
  22. 一种显示装置，包括如权利要求1至21任一项所述的显示基板。
  23. 一种显示基板的制备方法，所述显示基板包括显示区域和位于所述显示区域周边的边框区域；所述边框区域包括在所述第一方向上相对设置的第一边框和第二边框、在所述第二方向上相对设置的第三边框和第四边 框、连接所述第一边框和第三边框的第一角部、连接所述第二边框和第三边框的第二角部、连接所述第一边框和第四边框的第三角部以及连接所述第二边框和第四边框的第四角部，所述第一角部至第四角部中的至少一个为弧形的角部，所述第一方向为所述显示区域中扫描信号线的延伸方向，所述第二方向为所述显示区域中数据信号线的延伸方向；所述制备方法包括：
    在所述显示区域内形成显示结构，在所述第一角部至第四角部的至少一个中形成第一走线、第二走线和多个移位寄存器单元；
    所述第一走线和第二走线之间围成多个第一矩形，多个移位寄存器单元分别位于所述多个第一矩形中。
  24. 根据权利要求23所述的制备方法，其中，所述第一角部至第四角部的至少一个中还形成有第三走线，所述第三走线位于所述显示区域与所述第二走线之间，第三走线和第二走线之间围成多个第二矩形。
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