WO2022021207A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2022021207A1
WO2022021207A1 PCT/CN2020/105788 CN2020105788W WO2022021207A1 WO 2022021207 A1 WO2022021207 A1 WO 2022021207A1 CN 2020105788 W CN2020105788 W CN 2020105788W WO 2022021207 A1 WO2022021207 A1 WO 2022021207A1
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WO
WIPO (PCT)
Prior art keywords
insulating layer
circuit board
connection line
layer
selection
Prior art date
Application number
PCT/CN2020/105788
Other languages
English (en)
French (fr)
Inventor
曾超
黄炜赟
高永益
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/292,011 priority Critical patent/US20220310769A1/en
Priority to PCT/CN2020/105788 priority patent/WO2022021207A1/zh
Priority to CN202080001404.6A priority patent/CN114341965B/zh
Publication of WO2022021207A1 publication Critical patent/WO2022021207A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and more particularly, to a display substrate, a method for manufacturing the same, and a display device.
  • OLED Organic Light Emitting Diode
  • TFT Thin Film Transistor
  • an exemplary embodiment of the present disclosure provides a display substrate including a display area and a binding area on one side of the display area, the binding area including a source driving circuit, a flexible circuit board, and a first selector a circuit, a second selector circuit and a plurality of selection connection lines, for at least one selection connection line of the plurality of selection connection lines, one end of the selection connection line is connected to the input port of the first selector circuit, and the other end of the selection connection line is connected to the input port of the first selector circuit.
  • One end is connected to the input port of the second selector circuit; the flexible circuit board is arranged on the side of the source driving circuit away from the display area, and the plurality of selection connecting lines are arranged between the source driving circuit and the between the flexible circuit boards.
  • the first selector circuit and the second selector circuit are respectively disposed on both sides of the source driving circuit; the edge of the display area is the edge of the display area.
  • the display area is adjacent to an edge on one side of the binding area.
  • a plurality of selector pins are arranged on the flexible circuit board, and along a direction parallel to the edge of the display area, the plurality of selector pins are arranged on both sides of the flexible circuit board ;
  • the selector pin is connected with the selection connection line through the selection lead, or is connected with the first selector circuit or the first selector circuit through the selection lead Two selector circuits are connected to the input ports.
  • the binding area in a plane perpendicular to the display substrate, includes: a binding structure layer disposed on a substrate; a composite insulating layer disposed on the binding structure layer; A plurality of selective connection lines on the composite insulating layer.
  • the binding fabric layer includes:
  • the third insulating layer and the fourth insulating layer covering the first signal connection line are provided with two first via holes exposing the first signal connection line;
  • the via hole is connected to the first end of the first signal connection line; one end of the circuit board signal line is connected to the flexible circuit board, and the other end of the circuit board signal line is connected to the flexible circuit board through the first via hole The second end of the first signal connection line is connected.
  • the binding fabric layer includes:
  • a first insulating layer, a second insulating layer and a third insulating layer disposed on the substrate;
  • a fourth insulating layer covering the second signal connection line, and two second via holes exposing the second signal connection line are opened thereon;
  • the via hole is connected to the first end of the second signal connection line; one end of the circuit board signal line is connected to the flexible circuit board, and the other end of the circuit board signal line is connected to the first end of the circuit board signal line through the second via hole.
  • the second ends of the two signal connecting lines are connected.
  • the binding fabric layer includes:
  • the fourth insulating layer covering the second signal connection line is provided with two first via holes exposing the first signal connection line, and two second via holes exposing the second signal connection line. via;
  • the via hole and the second via hole are respectively connected with the first ends of the first signal connection line and the second signal connection line; one end of the circuit board signal line is connected with the flexible circuit board, and the circuit board signal line The other end is connected to the second ends of the first signal connection line and the second signal connection line through the first via hole and the second via hole, respectively.
  • At least two shielding wires are further disposed on the composite insulating layer, and the at least two shielding wires are respectively disposed on one side of the plurality of selection connecting wires adjacent to the display area and away from the display area.
  • the orthographic projection width of the shielding line on the substrate is greater than the orthographic projection width of the selection connecting line on the substrate.
  • a shielding plate is further disposed on the fourth insulating layer, and the shielding plate is disposed between the driving chip signal line and the circuit board signal line, along a direction away from the display area, The boundary of the orthographic projection of the plurality of selection connecting lines on the substrate is located within the boundary of the orthographic projection of the shielding plate on the substrate.
  • the display region in a plane perpendicular to the display substrate, includes a first insulating layer, an active layer, a second insulating layer, a first gate metal layer, and a third insulating layer stacked on the substrate layer, a second gate metal layer, a fourth insulating layer, a first source-drain metal layer, a composite insulating layer and a second source-drain metal layer; the first signal connection line and the first gate metal layer are arranged in the same layer;
  • the second signal connection line is arranged in the same layer as the second gate metal layer;
  • the driver chip signal line and the circuit board signal line are arranged in the same layer as the first source-drain metal layer;
  • the multiple selection connection lines It It is arranged in the same layer as the second source-drain metal layer.
  • the driving chip signal line and the circuit board signal line are the first power supply line VDD, or the driving chip signal line and the circuit board signal line are the second power supply line VSS.
  • the binding area includes:
  • first selection connecting wire and at least two first shielding wires arranged on the second insulating layer, the at least two first shielding wires being respectively arranged on both sides of the plurality of first selection connecting wires;
  • a third insulating layer covering the first selection connecting wire and the at least two first shielding wires
  • a fourth insulating layer covering the second selection connecting wire and the at least two second shielding wires
  • the shielding plate disposed on the fourth insulating layer, the boundary of the orthographic projection of the plurality of first selection connection lines or the plurality of second selection connection lines on the substrate is located in the boundary range of the orthographic projection of the shielding plate on the substrate Inside;
  • a plurality of third signal connection lines arranged on the composite insulating layer.
  • the display region in a plane perpendicular to the display substrate, includes a first insulating layer, an active layer, a second insulating layer, a first gate metal layer, and a third insulating layer stacked on the substrate layer, a second gate metal layer, a fourth insulating layer, a first source-drain metal layer, a composite insulating layer and a second source-drain metal layer;
  • the first selection connection line is arranged in the same layer as the first gate metal layer;
  • the second selection connection line is arranged in the same layer as the second gate metal layer;
  • the shielding plate is arranged in the same layer as the first source-drain metal layer;
  • the third signal connection line is arranged in the same layer as the second source-drain metal layer
  • the metal layer is set on the same layer.
  • an exemplary embodiment of the present disclosure also provides a display device including the aforementioned display substrate.
  • an exemplary embodiment of the present disclosure also provides a method for manufacturing a display substrate, the display substrate includes a display area and a binding area on one side of the display area, and the manufacturing method includes:
  • a source driving circuit, a flexible circuit board, a first selector circuit, a second selector circuit and a plurality of selection connection lines are formed in the binding area; for at least one selection connection line in the plurality of selection connection lines, all One end of the selection connection line is connected to the input port of the first selector circuit, and the other end is connected to the input port of the second selector circuit; the flexible circuit board is arranged on the source drive circuit away from the display area. On one side, the plurality of selection connecting lines are arranged between the source driving circuit and the flexible circuit board.
  • FIG. 1 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a binding region in a display substrate according to an exemplary embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of selecting a connection line according to an exemplary embodiment of the present disclosure
  • FIG. 4 and FIG. 5 are schematic cross-sectional views of selected connection line regions according to an exemplary embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of an exemplary embodiment of the present disclosure after an active layer pattern is formed
  • FIG. 7 is a schematic diagram after forming a first gate metal layer pattern according to an exemplary embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram after forming a second gate metal layer pattern according to an exemplary embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of an exemplary embodiment of the present disclosure after forming a fourth insulating layer pattern
  • FIG. 10 is a schematic diagram of forming a first source-drain metal layer pattern according to an exemplary embodiment of the present disclosure
  • FIG. 11 is a schematic diagram of forming a composite insulating layer pattern according to an exemplary embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of forming a second source-drain metal layer pattern according to an exemplary embodiment of the present disclosure
  • FIG. 13 is a schematic diagram of an exemplary embodiment of the present disclosure after forming a second planarization layer pattern
  • FIG. 14 is a schematic plan view of selecting a connecting line area according to an exemplary embodiment of the present disclosure.
  • 15 and 16 are schematic diagrams of an exemplary embodiment selector circuit of the present disclosure.
  • FIG. 17 is another schematic cross-sectional view of a selected connecting line area according to an exemplary embodiment of the present disclosure.
  • 100 display area
  • 101 thin film transistor
  • 102 storage capacitor
  • connection electrode connection electrode
  • 110 display area edge
  • 200 binding area
  • 201 the first fan-out area
  • 202 the bending area
  • 203 the second fan-out area
  • 204 driver chip area
  • 205 circuit board area
  • 206 switch circuit area
  • 207 select connection line area
  • 210 first selector circuit
  • 220 second selector circuit
  • 230 touch lead
  • 300 flexible circuit board
  • 301 first signal connection line
  • 302 second signal connection line
  • 303 shield plate
  • 304 driver chip signal line
  • circuit board signal line 305—circuit board signal line
  • 306 select connection line
  • 306-1 first choice connection line
  • 306-2 second selection cable
  • 307 shielded cable
  • 308 third signal cable
  • the terms “installed”, “connected” and “connected” should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrically connected includes a case where constituent elements are connected together by an element having a certain electrical effect.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having a certain electrical effect” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • film and “layer” are interchangeable.
  • conductive layer may be replaced by “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • the touch substrate of the OLED adopts a flexible multi-layer overlay surface (Flexible Multi Layer On Cell, FMLOC for short) structure, and the flexible touch substrate is arranged on the encapsulation layer of the OLED display structure.
  • FMLOC Flexible Multi Layer On Cell
  • the OLED includes a display area, a binding area on one side of the display area, and an edge area on the other side of the display area, the display area includes a plurality of light emitting units arranged regularly, each light emitting unit connected to at least one One gate line and at least one data line, the binding area and the edge area are provided with driving circuits, and the driving circuits are configured to provide display signals and touch signals to the display area.
  • the driving circuit may include: Gate Driver On Array (GOA for short) circuits disposed on both sides of the display area, configured to provide scan signals to the display area; source drivers disposed in the binding area
  • the circuit (Driver IC) is configured to provide data signals to the display area; the touch leads arranged in the binding area and the edge area are configured to provide touch signals to the touch substrate; the selectors (Multiplexer, The MUX for short) circuit is configured to select the touch leads so as to reduce the number of touch leads that are led out to the touch substrate.
  • the signal lines of the array row drive circuit, the signal lines of the source drive circuit, and the signal lines of the selector circuit are connected to the external control device through a flexible printed circuit (Flexible Printed Circuit, FPC for short) arranged in the binding area.
  • FPC Flexible Printed Circuit
  • the driving circuit may include a touch and display driver integrated circuit (Touch and Display Driver Integration, TDDI for short).
  • Exemplary embodiments of the present disclosure provide a display substrate including a display area and a binding area on one side of the display area, the binding area including a source driving circuit, a flexible circuit board, a first selector circuit, a first selector circuit, a first Two selector circuits and a plurality of selection connection lines, for at least one selection connection line of the plurality of selection connection lines, one end of the selection connection line is connected to the input port of the first selector circuit, and the other end is connected to the input port of the first selector circuit.
  • the flexible circuit board is arranged on the side of the source driving circuit away from the display area, and the multiple selection connecting lines are arranged between the source driving circuit and the flexible circuit between the boards.
  • the first selector circuit and the second selector circuit are respectively disposed on both sides of the source driving circuit; the edge of the display area is the edge of the display area.
  • the display area is adjacent to an edge on one side of the binding area.
  • a plurality of selector pins are arranged on the flexible circuit board, and along a direction parallel to the edge of the display area, the plurality of selector pins are arranged on both sides of the flexible circuit board ; For at least one selector pin in the plurality of selector pins, the selector pin is connected to the selection connection line through a selection lead.
  • FIG. 1 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure.
  • the display substrate includes a display area 100 and a non-display area located around the display area 100 , and the non-display area includes a binding area 200 located on one side of the display area 100 and a non-display area located at the display area 100
  • the display area 100 at least includes a plurality of display units arranged regularly
  • the binding area 200 at least includes a selector circuit, a source driving circuit and a flexible circuit board for connecting the signal line to the external control device
  • the edge area at least includes Array row driver circuit.
  • FIG. 2 is a schematic diagram showing the structure of a binding region in a substrate according to an exemplary embodiment of the present disclosure.
  • the binding area 200 in an exemplary embodiment, in a plane parallel to the display substrate, the binding area 200 is located on one side of the display area 100 , and along the direction away from the display area 100 , the binding area 200 may include sequential
  • the provided first fan-out area 201 , bending area 202 , second fan-out area 203 , driver chip area 204 and circuit board area 205 may further include a selection connecting line area 206 and a selector circuit area 207 .
  • the first fan-out area 201 can be provided with a first power line, a second power line and a plurality of data transmission lines, and the plurality of data transmission lines are configured to connect the data lines of the display area 100 in a fan-out (Fanout) routing manner,
  • the first power supply line (VDD) is configured to be connected to a high-level power supply line of the display area 100
  • the second power supply line (VSS) is configured to be connected to a low-level power supply line of the edge area.
  • the bending area 202 may be provided with a groove, and the groove is configured to bend the binding area 200 to the back of the display area 100 .
  • the second fan-out area 203 may be provided with a plurality of data transmission lines drawn out in a fan-out routing manner.
  • the driver chip area 204 may be provided with a source driver circuit (Driver IC) configured to be connected to a plurality of data transmission lines of the second fan-out area 203 .
  • the circuit board area 205 can be provided with a flexible circuit board (FPC), and the flexible circuit board (FPC) includes a plurality of pins (PINs) connected to the bonding pads (Bonding Pads) of the source driving circuit, and the plurality of pins are configured to be connected with External control device connection.
  • FPC flexible circuit board
  • the selector circuit areas 207 may be disposed on both sides of the driving chip area 204, and the selector circuit areas 207 on one side of the driving chip area 204 may be disposed first
  • the selector circuit 210, the selector circuit area 207 on the other side of the driver chip area 204 can be provided with a second selector circuit 220.
  • the display area edge 110 is the edge of the side of the display area 100 adjacent to the binding area 200 .
  • the selection connection line area 206 may be disposed between the driving chip area 204 and the circuit board area 205 in a direction away from the display area 100 .
  • the selection connection line area 206 can be provided with a plurality of selection connection lines, and the plurality of selection connection lines are configured to realize the connection between the input port of the first selector circuit 210 and the input port of the second selector circuit 220.
  • the plurality of selection connection lines At least one selection connection line among the lines, one end of the selection connection line is connected to an input port of the first selector circuit 210, and the other end is connected to an input port of the second selector circuit 220, so as to realize the first selector circuit 210 and the first selector circuit 210.
  • the connection between the input ports of the two selector circuits 220 with the same input signal.
  • the binding area 200 may include an anti-static circuit configured to eliminate static electricity, an isolation dam configured to block water vapor from entering the display area, and other wiring areas, which are not limited herein.
  • FIG. 3 is a schematic diagram of selecting connecting lines according to an exemplary embodiment of the present disclosure.
  • the first selector circuit 210 and the second selector circuit 220 are respectively disposed on both sides of the driver chip area, each selector circuit includes M input ports, and N inputs of the first selector circuit 210
  • the ports and the N input ports of the second selector circuit 220 are correspondingly connected through N selection connection lines 306 , that is, the first input port of the first selector circuit 210 and the first input port of the second selector circuit 220 are connected.
  • N may be an even number greater than or equal to 2, then each group includes n/2 selector pins 310.
  • the first group of n/2 selector pins 310 are arranged on the left side of the flexible circuit board 300, adjacent to the first selector circuit 210, and the second group of n/2 selector pins 310 are arranged on the flexible circuit board 300 , adjacent to the second selector circuit 220 .
  • N may be an odd number greater than or equal to 2, then the first group may include (n-1)/2 selector pins 310, and the second group may include (n+1)/2 selector pins 310 Selector pins 310, or the first group may include (n+1)/2 selector pins 310 and the second group may include (n-1)/2 selector pins 310.
  • the first group is disposed on the left side of the flexible circuit board 300 , adjacent to the first selector circuit 210
  • the second group is disposed on the right side of the flexible circuit board 300 , adjacent to the second selector circuit 220 .
  • the flexible circuit board 300 may be provided with other pins, which are not limited in the present disclosure.
  • the N selector pins 310 are respectively connected to the N selection connection lines 306 through the N selection leads 320, respectively, and the nN selector pins 310 are respectively connected to the first selector through the nN selection leads 320.
  • the nN input ports of the selector circuit 210 and the second selector circuit 220 are connected correspondingly, that is, the first selector pin 310 is connected to the first selection connection line 306 through the first selection lead 320, ..., the Nth selection
  • the selector pin 310 is connected to the N-th selection connection line 306 through the N-th selection lead 320
  • the N+1-th selector pin 310 is connected to the N+th selection wire 306 of the first selector circuit 210 through the N+1-th selection lead 320 .
  • 1 input port is connected, or is connected to the N+1th input port of the second selector circuit 220, . . .
  • the nth selector pin 310 is connected to the Mth input of the first selector circuit 210 through the nth selection lead 320 port, or connected with the Mth input port of the second selector circuit 220 .
  • N/2 selector pins 310 are connected to N/2 select connection lines 306, and (MN) selector pins 310 Connected to the (MN) input ports of the first selector circuit 210 .
  • the N/2 selector pins 310 are connected to the other N/2 selection connection lines 306, and the (MN) selector pins 310 are connected to the second selector circuit 220 (MN) input port connections.
  • the first selector circuit 210 and the second selector circuit 220 have a total of 2M input ports. Since N selection connection lines 306 are provided, the N selection connection lines 306 are respectively connected to the first selector circuit. Connections are established between the N input ports of the circuit 210 and the N input ports of the second selector circuit 220. Therefore, only 2M-N selector pins 310 need to be set on the flexible circuit board 300 to realize 2M input ports. It is not necessary to set 2M selector pins 310 on the flexible circuit board 300, effectively reducing the number of selector pins, which is not only conducive to the pin arrangement of the flexible circuit board 300, but also conducive to improving the signal reliability of input.
  • the number of the selection connection lines 306 may be determined according to the input signals of the first selector circuit 210 and the second selector circuit 220 .
  • the first selector circuit and the second selector circuit by arranging the first selector circuit and the second selector circuit on both sides of the driver chip area, and two groups of selector pins are respectively arranged on both sides of the flexible circuit board, multiple selection
  • the connecting lines are set to establish connections between the multiple input ports of the first selector circuit and the multiple input ports of the second selector circuit, which not only effectively reduces the number of selector pins, but also does not increase the binding area.
  • the width improves the competitiveness of the product.
  • FIG. 4 and 5 are schematic cross-sectional views of selected connecting line regions according to an exemplary embodiment of the present disclosure
  • FIG. 4 is a cross-sectional view along A-A in FIG. 2
  • FIG. 5 is a cross-sectional view along B-B in FIG.
  • the N selection connection lines 306 are disposed in the selection connection line area 206 , that is, between the driving chip area 204 and the circuit board area 205 . As shown in FIG. 4 and FIG.
  • the selective connection line area 206 includes: a first insulating layer 11 and a second insulating layer 12 stacked on the substrate 10 and disposed on the second insulating layer
  • a selection connection line 306 is provided, and the second planarization layer 17 is disposed on the selection connection line 306 .
  • the selection connection line area 206 further includes shielded wires 307 arranged on the same layer as the selection connection wires 306 , and the shielded wires 307 are arranged on both sides of the plurality of selection connection wires 306 .
  • the side of the selection connecting line area 206 adjacent to the display area is the driving chip area 204
  • the driving chip area 204 is provided with the driving chip signal lines 304
  • the side of the selection connecting line area 206 away from the display area is the circuit board area 205
  • the circuit board area 205 is provided with a circuit board signal line 305 .
  • the driving chip signal lines 304 and the circuit board signal lines 305 are disposed on the same layer as the shielding plate 303 .
  • the first signal connection line 301 and the second signal connection line 302 are configured to establish a connection between the driver chip signal line 304 and the circuit board signal line 305, so that the signal of the source driving circuit passes through the selection connection line area 206 reaches the flexible circuit board.
  • one end of the driver chip signal line 304 is connected to the source driver circuit in the driver chip area 204, and the other end is connected to the first signal connection line 301 and the second signal line 301 through the first via hole and the second via hole, respectively.
  • the first end of the connection line 302 is connected.
  • One end of the circuit board signal line 305 is connected to the flexible circuit board in the circuit board area 205, and the other end is connected to the second end of the first signal connection line 301 and the second signal connection line 302 through the first via hole and the second via hole respectively .
  • the structures shown in FIG. 4 and FIG. 5 may include only the first signal connection line 301 or only the second signal connection line 302 , and can also be implemented in the driver chip signal line 304 and the circuit board signal line 305 establish a connection between them.
  • the display area 100 in a plane perpendicular to the display substrate, includes: a first insulating layer disposed on the substrate, an active layer disposed on the first insulating layer, a The second insulating layer, the first gate metal layer provided on the second insulating layer, the third insulating layer provided on the first gate metal layer, the second gate metal layer provided on the third insulating layer, the The fourth insulating layer on the second gate metal layer, the first source-drain metal layer on the fourth insulating layer, the fifth insulating layer and the first flat layer on the first source-drain metal layer, on the first a second source-drain metal layer on the flat layer.
  • the first signal connection line 301 of the selection connection line region 206 is disposed in the same layer as the first gate metal layer of the display region 100 and formed by the same patterning process at the same time.
  • the second signal connection lines 302 of the selection connection line region 206 are disposed in the same layer as the second gate metal layer of the display region 100 and formed through the same patterning process at the same time.
  • the shielding plate 303 of the selective connection line region 206 is disposed in the same layer as the first source-drain metal layer of the display region 100 , and is simultaneously formed by the same patterning process.
  • the selection connection lines 306 of the selection connection line region 206 are disposed in the same layer as the second source-drain metal layer of the display region 100 and are simultaneously formed by the same patterning process.
  • the following is an exemplary description through the preparation process of the display substrate.
  • the "patterning process” mentioned in this disclosure includes photoresist coating, mask exposure, development, etching, stripping photoresist and other treatments, for organic materials, including Processes such as coating organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spraying, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings are not limited in the present disclosure.
  • “Film” refers to a thin film made of a material on a substrate by deposition, coating or other processes.
  • the "thin film” may also be referred to as a "layer”. If the "thin film” needs a patterning process in the whole manufacturing process, it is called a "thin film” before the patterning process, and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A is the same as the boundary of the orthographic projection of B.
  • the projected boundaries overlap.
  • the substrate 10 is prepared on the glass carrier plate 1 .
  • the substrate 10 may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on the glass carrier 1 .
  • the materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated soft polymer films, and the first and second inorganic materials
  • the material of the layer can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate.
  • the first and second inorganic material layers are also called barrier layers.
  • the material can be amorphous silicon (a-si).
  • the preparation process may include: firstly coating a layer of polyimide on the glass carrier 1, and curing it into a After filming, a first flexible (PI1) layer is formed; then a barrier film is deposited on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then a non-contact layer is deposited on the first barrier layer A crystalline silicon film to form an amorphous silicon (a-si) layer covering the first barrier layer; then a layer of polyimide is coated on the amorphous silicon layer, and a second flexible (PI2) layer is formed after curing into a film ; Then deposit a layer of barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer to complete the preparation of the substrate 10 .
  • the substrate 10 may be a rigid substrate.
  • the active layer pattern on the insulating layer 11 includes at least the first active layer formed in the display area 100 , as shown in FIG. 6 .
  • the driver chip area 204 , the circuit board area 205 and the selection connection line area 206 in the bonding area include the first insulating layer 11 disposed on the substrate 10 .
  • the first gate metal layer pattern on the display area 100, the first gate metal layer pattern at least includes a first gate electrode, a first capacitor electrode and a first signal connection line 301, the first gate electrode and the first capacitor electrode are formed in the display area 100, the first gate electrode and the first capacitor electrode are formed in the display area 100.
  • a signal connection line 301 is formed in the selection connection wire area 206 of the bonding area, the driver chip area 204 adjacent to the selection connection wire area 206 and the circuit board area 205 adjacent to the selection connection wire area 206 , as shown in FIG. 7 .
  • the selective connection line area 206 of the bonding area includes the first insulating layer 11 , the second insulating layer 12 and the first signal connection line 301 stacked on the substrate 10 .
  • the selection connection line area 206 is provided with a plurality of selection connection lines, and the plurality of selection connection lines extend in a direction parallel to the edge of the display area, the signal lines of the source driving circuit in the driving chip area 204 are connected to the The signal lines of the flexible circuit board in the circuit board area 205 need to pass through the selection connection line area 206 .
  • the first signal connection line 301 is configured to connect the signal line of the source driving circuit and the signal line of the flexible circuit board to be formed later, so that the signal line of the source driving circuit and the signal line of the flexible circuit board pass through the first A signal connection line 301 realizes the connection and ensures the transmission of the signal.
  • the second gate metal layer pattern on 13, the second gate metal layer pattern at least includes a second capacitor electrode and a second signal connection line 302, the second capacitor electrode is formed in the display area 100, and the position of the second capacitor electrode is the same as that of the first capacitor electrode.
  • the second signal connection lines 302 are formed in the selection connection line area 206 of the bonding area, the area of the driver chip area 204 adjacent to the selection connection wire area 206 and the area of the circuit board area 205 adjacent to the selection connection wire area 206, As shown in Figure 8.
  • the selective connecting line area 206 of the bonding area includes the first insulating layer 11 , the second insulating layer 12 , the first signal connecting line 301 , the third insulating layer 13 and the Two signal connection lines 302 .
  • the second signal connection line 302 is configured to connect the signal line of the source driving circuit to be formed subsequently and the signal line of the flexible circuit board.
  • the plurality of vias at least include two active vias V1 , two first vias K1 and two second vias K2 , as shown in FIG. 9 .
  • two active vias V1 are formed in the display area 100, and the fourth insulating layer 14, the third insulating layer 13 and the second insulating layer 12 in the two active vias V1 are etched away , exposing the surface of the first active layer.
  • a second via hole K2 and a first via hole K1 are formed in the driver chip area 204 of the bonding area, and the distance between the second via hole K2 and the selection connection line area 206 is smaller than that of the first via hole K1
  • the distance from the selection connection line area 206, the fourth insulating layer 14 and the third insulating layer 13 in the first via hole K1 are etched away, exposing the surface of the first end of the first signal connection line 301, the second via hole
  • the fourth insulating layer 14 in K2 is etched away, exposing the surface of the first end of the second signal connection line 302 .
  • the first end is one end of the first signal connection line 301 and the second signal connection line 302 adjacent to the driving chip area 204 .
  • another second via K2 and another first via K1 are formed in the circuit board area 205 of the bonding area, and the distance between the second via K2 and the selection connection line area 206 is smaller than that of the first via
  • the distance between the hole K1 and the selection connection line area 206, the fourth insulating layer 14 and the third insulating layer 13 in the first via hole K1 are etched away, exposing the surface of the second end of the first signal connection line 301, and the second through hole K1 is etched away.
  • the fourth insulating layer 14 in the hole K2 is etched away, exposing the surface of the second end of the second signal connection line 302 .
  • the second end is one end of the first signal connection line 301 and the second signal connection line 302 adjacent to the circuit board area 205 .
  • the selective connection line area 206 of the bonding area includes the first insulating layer 11 , the second insulating layer 12 , the first signal connection line 301 , the third insulating layer 13 , the Two signal connection lines 302 and the fourth insulating layer 14 .
  • the two active vias V1 are configured to connect the subsequently formed first source electrode and the second drain electrode to the first active layer, respectively.
  • the two second via holes K2 are configured to connect the subsequently formed driver chip signal lines and the circuit board signal lines to the second signal connection lines 302 respectively, and the two first via holes K1 are configured to connect the subsequently formed driver chip signal lines and the circuit board signal lines to the second signal connection line 302 respectively.
  • the circuit board signal lines are respectively connected with the first signal connection lines 301 to realize the connection between the signal lines of the source driving circuit and the signal lines of the flexible circuit board.
  • the first source-drain metal layer at least includes the first source
  • the electrode, the first drain electrode, the shielding plate 303 , the driving chip signal line 304 and the circuit board signal line 305 are shown in FIG. 10 .
  • the first source electrode and the first drain electrode are formed in the display area 100, and are respectively connected to the first active layer through the first via hole.
  • the shielding plate 303 is formed in the selective connection line area 206 of the binding area, and is configured to provide a shielding function for the subsequently formed selective connection line.
  • the shielding plate 303 may be connected to the first power supply line VDD of the pixel driving circuit, or may be connected to the second power supply line VSS of the pixel driving circuit, or may be connected to the high voltage power supply line VGH of the array row driving circuit, or A low voltage power supply line VGL of the array row driver circuit can be connected.
  • the driver chip signal line 304 is formed in the driver chip region 204 of the bonding area, one end away from the selection connection line region 206 is connected to the source driving circuit, and one end adjacent to the selection connection line region 206 passes through the first via hole It is connected to the first end of the first signal connection line 301, and is connected to the first end of the second signal connection line 302 through the second via hole.
  • the circuit board signal line 305 is formed in the circuit board area 205 of the bonding area, one end away from the selection connection line area 206 is connected to the flexible circuit board, and one end adjacent to the selection connection line area 206 passes through the first via hole It is connected to the second end of the first signal connection line 301, and is connected to the second end of the second signal connection line 302 through the second via hole.
  • a dual-signal connection line structure connecting the driver chip signal line 304 and the circuit board signal line 305 is formed in the selection connection line area 206 .
  • the driver chip signal lines 304 and the circuit board signal lines 305 are arranged on the first source-drain metal layer (SD1), and in the select connection line area 206, the signal lines are respectively arranged on the first gate metal layer layer (Gate1) and a second gate metal layer (Gate2). That is to say, in the selection connection line area 206 , the signal lines are in the Gate1 layer and the Gate2 layer, and in the area outside the selection connection line area 206 , the signal lines are in the SD1 layer.
  • the dual-signal connection line structure of the exemplary embodiment of the present disclosure not only reduces the connection resistance, but also ensures the reliability of signal transmission.
  • only the first signal connection line 301 may be provided on the first gate metal layer, and only two first vias K1 may be opened on the fourth insulating layer 14 to form a single-signal connection line structure.
  • only the second signal connection line 302 may be provided on the second gate metal layer, and only two second vias K2 may be opened on the fourth insulating layer 14 to form a single-signal connection line structure.
  • a fifth insulating film is first deposited, and then a first flat film of organic material is coated to form a fifth insulating layer 15 covering the entire substrate 10 and disposed on the fifth insulating layer 15.
  • a connecting via V2 is formed on the first flat layer 16, and the connecting via V2 is formed in the display area 100, The first planar layer 16 and the fifth insulating layer 15 in the connection via hole V2 are removed to expose the surface of the first drain electrode of the first transistor 101, as shown in FIG. 11 .
  • the first planarization layer 16 may be formed only in the selective connection line region 206 of the bonding area, and the fifth insulating layer 15 and the first planarization layer 16 are referred to as composite insulating layers.
  • the composite insulating layer may include only the fifth insulating layer 15 , or only the first planar layer 16 .
  • the first flat layer 16 can be directly formed on the substrate on which the aforementioned patterns are formed, and the first flat layer 16 can be formed in the driver chip area 204 and the circuit board area 205 in the bonding area and select connector area 206.
  • the drain metal layer includes at least a connection electrode 103 , a plurality of selection connection lines 306 and at least two shield lines 307 .
  • the connection electrode 103 is formed in the display area 100 and is connected to the first drain electrode of the first transistor 101 through a connection via hole.
  • a plurality of selection connection wires 306 and at least two shield wires 307 are formed in the selection connection wire area 206 of the binding area, as shown in FIG. 12 .
  • the plurality of selection connection lines 306 are spaced apart, and the plurality of selection connection lines 306 are configured between the plurality of input ports of the first selector circuit 210 and the plurality of input ports of the second selector circuit 220 establish connection.
  • the plurality of selection connection lines 306 are configured between the plurality of input ports of the first selector circuit 210 and the plurality of input ports of the second selector circuit 220 establish connection.
  • one end of the selection connection line 306 is connected to the input port of the first selector circuit, and the other end is connected to the input port of the second selector circuit.
  • the two shielding lines 307 are respectively disposed on both sides of the plurality of selection connecting lines 306, that is, at least one shielding line 307 is disposed on one side of the selection connecting line area 206 adjacent to the driving chip area 204 (ie, the plurality of The side of the selection connection line adjacent to the display area), at least one shielding line 307 is arranged on the side of the selection connection line area 206 adjacent to the circuit board area 205 (that is, the side of the multiple selection connection lines away from the display area), at least two shielding lines 307 Lines 307 are configured to provide a lateral shielding function for the plurality of select connection lines 306 .
  • the width of the orthographic projection of the shielding line 307 on the substrate is greater than the width of the orthographic projection of the selection connecting line 306 on the substrate.
  • “width” refers to the dimension of a feature along a direction away from the display area.
  • the boundary of the orthographic projection of the plurality of selection connecting lines 306 on the substrate is located within the boundary of the orthographic projection of the shielding plate 303 on the substrate.
  • the boundary of the orthographic projection of the at least two shielding wires 307 on the substrate is located within the boundary of the orthographic projection of the shielding plate 303 on the substrate.
  • At least two shield lines 307 may be connected to the first power supply line VDD of the pixel driving circuit, or may be connected to the second power supply line VSS of the pixel driving circuit, or may be connected to the high voltage power supply line of the array row driving circuit VGH, or a low-voltage power supply line VGL that can be connected to the array row driver circuit.
  • each selection connection line 306 is about 1.5 ⁇ m to 6.0 ⁇ m, and the width of the spacing between adjacent selection connection lines 306 is about 2.0 ⁇ m to 6.0 ⁇ m.
  • the width of each shielding wire 307 is about 10 ⁇ m to 20 ⁇ m, and the width of the shielding plate 303 is about 500 ⁇ m to 700 ⁇ m.
  • the driving chip area 204 and the circuit board area 205 may form corresponding signal lines and pins, which are not limited in this disclosure.
  • a second flat film of organic material is coated, and a second flat layer 17 covering the entire substrate 10 is formed through a patterning process of masking, exposing, and developing.
  • An anode via V3 is formed on the flat layer 17 , and the anode via V3 is formed in the display area 100 .
  • the second flat layer 17 in the anode via V3 is removed to expose the surface of the connection electrode 103 , as shown in FIG. 13 .
  • the driving structure layer of the display area 100 and the binding structure layer pattern of the binding area 200 are prepared on the substrate 10 .
  • the first active layer, the first gate electrode, the first source electrode and the first drain electrode form the first transistor 101, the first capacitor electrode and the second capacitor electrode
  • the first storage capacitor 102 is formed.
  • the binding structure layers of the binding area 200 include:
  • the fourth insulating layer 14 covering the second signal connection line 302 is provided with a plurality of via holes, and the plurality of via holes include: two first through holes exposing the first end and the second end of the first signal connection line 301 .
  • the shielding plate 303, the driving chip signal line 304 and the circuit board signal line 305 are arranged on the fourth insulating layer 14; the shielding plate 303 is formed in the selection connecting line area 206 of the binding area; the driving chip signal line 304 is formed in the binding area
  • the driver chip area 204 is connected to the first ends of the first signal connection line 301 and the second signal connection line 302 respectively through a first via K1 and a second via K2 at the first end; the circuit board signal line 305
  • the circuit board area 205 formed in the binding area is connected to the second ends of the first signal connection line 301 and the second signal connection line 302 through a first via hole K1 and a second via hole K2 at the second end, respectively;
  • the fifth insulating layer 15 covering the shielding plate 303, the driving chip signal lines 304 and the circuit board signal lines 305, and the first flat layer 16 disposed on the fifth insulating layer 15;
  • the second flat layer 17 covers the plurality of selection connection wires 306 and the at least two shield wires 307 .
  • the display substrate further includes an anode, a pixel definition (PDL) layer, a spacer post (PS), an organic light emitting layer, a cathode, and an encapsulation layer formed in the display area 100
  • the encapsulation layer may include a stacked th An encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer are made of inorganic materials, and the second encapsulation layer is made of organic materials.
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may employ silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride Any one or more of (SiON), which may be a single layer, a multi-layer or a composite layer.
  • the first insulating layer is called a buffer layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer and the third insulating layer are called the gate insulating (GI) layer
  • the fourth insulating layer is called the layer
  • the fifth insulating layer is called the passivation (PVX) layer.
  • the first metal film, the second metal film, the third metal film and the fourth metal film can be made of metal materials such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo).
  • any one or more of the above metals, or alloy materials of the above metals can be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti, etc. .
  • the active layer film can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si) , hexathiophene, polythiophene and other materials, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • hexathiophene polythiophene and other materials
  • the exemplary embodiments of the present disclosure provide a plurality of selection connection lines in the selection connection line area, and the plurality of selection connection lines are in the first selector circuit 210 .
  • a connection is established between the multiple input ports of the second selector circuit 220 and the multiple input ports of the second selector circuit 220, so that the input ports with the same input signal in the first selector circuit 210 and the second selector circuit 220 are connected together, and only one
  • the selector pins can realize the signal input of two input ports, which effectively reduces the number of selector pins, which is not only beneficial to the pin arrangement of the flexible circuit board, but also helps to improve the reliability of the signal input.
  • the binding will not be increased.
  • the width of the area improves the competitiveness of the product.
  • the exemplary embodiment of the present disclosure utilizes the first gate metal layer and the second gate metal layer to form the first signal connection line and the second signal connection line, respectively, so as to realize the connection between the signal line of the driving chip and the signal line of the circuit board, and ensure the signal transmission.
  • the connection resistance is reduced, and the reliability of signal transmission is ensured.
  • Exemplary embodiments of the present disclosure use the first source-drain metal layer to form a shielding plate that provides a shielding function for the selection connection lines, which avoids the interference of the first signal connection line and the second signal connection line to multiple selection connection lines, and avoids multiple selection connection lines.
  • the interference of the selected connection lines to the first signal connection line and the second signal connection line improves the reliability of signal transmission.
  • shielding wires are formed on both sides of the plurality of selection connecting wires, and the shielding wires provide a lateral shielding function for the plurality of selection connecting wires, so as to avoid the signal wires in the driving chip area and the circuit board area from being connected to the multiple selection wires.
  • the interference of the line avoids the interference of a plurality of selection connecting lines to the signal lines in the driving chip area and the circuit board area, and improves the working reliability.
  • Exemplary embodiments of the present disclosure show the structure of the substrate and the fabrication process thereof are merely illustrative. In the exemplary embodiment, the corresponding structures may be changed and patterning processes may be increased or decreased according to actual needs, which is not limited in the present disclosure.
  • FIG. 14 is a schematic plan view of selecting a connecting line area according to an exemplary embodiment of the present disclosure.
  • the shielding plate 303 is disposed on the first source-drain metal layer, and provides a shielding function for the first signal connection line and the second signal connection line below it and the selection connection line 306 above it.
  • the two shielded lines 307 are arranged on both sides of the plurality of selection connecting wires 306 to provide a lateral shielding function for the plurality of selection connecting wires 306 .
  • One end of the driver chip signal line 304 adjacent to the selection connection line area 206 and one end of the circuit board signal line 305 adjacent to the selection connection line area 206 pass through the first signal connection line disposed on the first gate metal layer and the second gate metal layer.
  • the second signal connection line is connected, one end of the driver chip signal line 304 away from the selection connection line area 206 is connected to the source driving circuit of the driver chip area 204, and one end of the circuit board signal line 305 away from the selection connection line area 206 is connected with the circuit board area 205.
  • FIG. 15 and 16 are schematic plan views of exemplary embodiment selector circuits of the present disclosure. As shown in FIG. 15 , the output ports of the first selector circuit 210 are connected to the touch electrodes of the display area through a plurality of touch leads (TSP Trace) 230 , and a part of the input ports of the first selector circuit 210 are connected to the touch electrodes through the select leads 320 .
  • TSP Trace touch leads
  • the selector pin 310 on the left side of the flexible circuit board is connected, and another part of the input port of the first selector circuit 210 is connected to the input port of the second selector circuit through a plurality of selection connection lines 306, and the plurality of selection connection lines 306 Connect to another part of the selector pin 310 on the left side of the flexible circuit board through the selection lead 320 .
  • the first power supply line VDD and the second power supply line VSS are arranged on the first gate metal layer and the second gate metal layer, and in the region outside the plurality of selection connection lines 306, the first power supply line VDD and the second power supply line VSS is disposed on the first source-drain metal layer. As shown in FIG.
  • the output ports of the second selector circuit 220 are connected to the touch electrodes of the display area through a plurality of touch leads (TSP Trace) 230 , and a part of the input ports of the second selector circuit 220 are connected to the touch electrodes through the select leads 320 .
  • TSP Trace touch leads
  • Part of the selector pin 310 on the right side of the flexible circuit board is connected, and another part of the input port of the first selector circuit 210 is connected to the input port of the first selector circuit through a plurality of selection connection lines 306, and the plurality of selection connection lines 306 It is connected to another part of the selector pin 310 on the right side of the flexible circuit board through the selection lead 320 .
  • the first power supply line VDD and the second power supply line VSS are arranged on the first gate metal layer and the second gate metal layer, and in the region outside the plurality of selection connection lines 306, the first power supply line VDD and the second power supply line VSS is disposed on the first source-drain metal layer.
  • FIG. 17 is another schematic cross-sectional view of a selected connecting line area according to an exemplary embodiment of the present disclosure, and is a cross-sectional view taken along the direction B-B in FIG. 2 .
  • the selective connection line area 206 of the bonding area includes: a first insulating layer 11 and a second insulating layer 12 stacked on the substrate 10 and disposed on the second insulating layer A plurality of first selection connecting lines 306-1 on layer 12, a third insulating layer 13 disposed on the first selection connecting line 306-1, a plurality of second selection connecting lines 306 disposed on the third insulating layer 13 -2, the fourth insulating layer 14 disposed on the second selection connecting line 306-2, the shielding plate 303 disposed on the fourth insulating layer 14, the fifth insulating layer 15 disposed on the shielding plate 303 and the first flat Layer 16 , the third signal connection line 308 disposed on the first flat layer 16 , the second flat
  • the selection connection line area 206 further includes at least two first shielded wires arranged on the same layer as the first selection connection wire 306 - 1 , and the at least two first shielded wires are arranged on the plurality of first selection connection wires 306 -1 on both sides.
  • the selection connecting wire area 206 further includes at least two second shielding wires arranged on the same layer as the second selection connecting wires 306 - 2 , and the at least two second shielding wires are arranged on the plurality of second selection connecting wires 306 -2 sides.
  • the first selection connection line 306-1 is disposed in the same layer as the first gate metal layer of the display area 100, and is simultaneously formed by the same patterning process
  • the second selection connection line 306-2 is formed with the display area
  • the second gate metal layer of 100 is disposed in the same layer and formed at the same time by the same patterning process.
  • the shielding plate 303 is disposed in the same layer as the first source-drain metal layer of the display area 100 and formed at the same time by the same patterning process.
  • the three signal connection lines 308 are disposed in the same layer as the second source-drain metal layer of the display area 100, and are simultaneously formed by the same patterning process.
  • the driver chip area 204 of the bonding area is formed with driver chip signal lines
  • the circuit board area of the bonding area is formed with circuit board signal lines
  • the driver chip signal lines and the circuit board signal lines are the same as the shielding plate 303 .
  • the layers are arranged and formed simultaneously by the same patterning process.
  • One end of the driver chip signal line away from the selection connection line area 206 is connected to the source driving circuit, and an end adjacent to the selection connection line area 206 is connected to the first end of the third signal connection line 308 through a via hole.
  • the third signal connecting line 308 forms a single signal connecting line structure connecting the driving chip signal line and the circuit board signal line.
  • the plurality of first selection connection lines 306 - 1 and the plurality of second selection connection lines 306 - 2 are configured as multiple input ports of the first selector circuit 210 and the plurality of input ports of the second selector circuit 220 Establish connections between multiple input ports.
  • first selection connection lines 306-1 one end of the first selection connection line 306-1 is connected to the input port of the first selector circuit, and the other end is connected to the second selector input port of the circuit.
  • second selection connection line 306-2 in the second selection connection lines 306-2 one end of the second selection connection line 306-2 is connected to the input port of the first selector circuit, and the other end is connected to the second selector circuit input port of the circuit.
  • the first selection connection line 306-1 and the second selection connection line 306-2 can be connected to different input ports, and a plurality of selection connection lines are respectively arranged on two layers, which can reduce the selection connection line area 206 width.
  • the first selection connection line 306-1 and the second selection connection line 306-2 can be connected to the same input port, and multiple selection connection lines in two layers can form a double selection connection line structure, which reduces the The connection resistance ensures the reliability of signal transmission.
  • the present disclosure also provides a preparation method of a display substrate, the display substrate includes a display area and a binding area on one side of the display area.
  • the preparation method includes:
  • a source driving circuit, a flexible circuit board, a first selector circuit, a second selector circuit and a plurality of selection connection lines are formed in the binding area; for at least one selection connection line in the plurality of selection connection lines, all One end of the selection connection line is connected to the input port of the first selector circuit, and the other end is connected to the input port of the second selector circuit; the flexible circuit board is arranged on the source drive circuit away from the display area. On one side, the plurality of selection connecting lines are arranged between the source driving circuit and the flexible circuit board.
  • a source driving circuit, a flexible circuit board, a first selector circuit, a second selector circuit and a plurality of selection connecting lines are formed in the binding area, including:
  • a driver chip signal line and a circuit board signal line are formed on the fourth insulating layer, one end of the driver chip signal line is connected to the source driver circuit, and the other end of the driver chip signal line passes through a first via hole connected to one end of the first signal connection line; one end of the circuit board signal line is connected to the flexible circuit board, and the other end of the circuit board signal line is connected to the first signal through a first via hole Connect the other end of the line;
  • a plurality of selective connection lines are formed on the composite insulating layer.
  • a source driving circuit, a flexible circuit board, a first selector circuit, a second selector circuit and a plurality of selection connecting lines are formed in the binding area, including:
  • first insulating layer forming a first insulating layer, a second insulating layer and; a third insulating layer on the substrate;
  • a driver chip signal line and a circuit board signal line are formed on the fourth insulating layer, one end of the driver chip signal line is connected to the source driver circuit, and the other end of the driver chip signal line passes through a second via hole connected to one end of the second signal connection line; one end of the circuit board signal line is connected to the flexible circuit board, and the other end of the circuit board signal line is connected to the second signal through a second via hole Connect the other end of the line;
  • a plurality of selective connection lines are formed on the composite insulating layer.
  • a source driving circuit, a flexible circuit board, a first selector circuit, a second selector circuit and a plurality of selection connecting lines are formed in the binding area, including:
  • a fourth insulating layer covering the second signal connection line is formed, and two first via holes exposing the first signal connection line and two first vias exposing the second signal connection line are opened thereon. Two vias;
  • a driver chip signal line and a circuit board signal line are formed on the fourth insulating layer, one end of the driver chip signal line is connected to the source driver circuit, and the other end of the driver chip signal line passes through a first via hole and a second via are respectively connected to one end of the first signal connection line and one end of the second signal connection line; one end of the circuit board signal line is connected to the flexible circuit board, and the circuit board signal line is connected to the flexible circuit board. The other end is respectively connected to the other end of the first signal connection line and the other end of the second signal connection line through a first via hole and a second via hole;
  • a plurality of selective connection lines are formed on the composite insulating layer.
  • forming a plurality of selective connection wires on the composite insulating layer includes: forming a plurality of selective connection wires and at least two shielded wires on the composite insulating layer, the at least two shielded wires They are respectively arranged on both sides of the plurality of selection connection lines, and the width of the orthographic projection of the shielding lines on the substrate is greater than the width of the orthographic projection of the selection connection lines on the substrate.
  • forming the driving chip signal line and the circuit board signal line on the fourth insulating layer includes: forming a shielding plate, the driving chip signal line and the circuit board signal line on the fourth insulating layer, The shielding plate is arranged between the driving chip signal line and the circuit board signal line, and the boundary of the orthographic projection of the plurality of selection connection lines on the substrate is located within the boundary of the orthographic projection of the shielding plate on the substrate.
  • the preparation method further includes: forming a first insulating layer, an active layer, a second insulating layer, a first gate metal layer, a third insulating layer, and a second gate metal layer in the display region , a fourth insulating layer, a first source-drain metal layer, a composite insulating layer and a second source-drain metal layer.
  • the first signal connection line and the first gate metal layer are disposed in the same layer and formed through the same patterning process.
  • the second signal connection line and the second gate metal layer are disposed in the same layer and formed through the same patterning process.
  • the driving chip signal line and the circuit board signal line are disposed in the same layer as the first source-drain metal layer, and are formed through the same patterning process.
  • the plurality of selection connection lines and the second source-drain metal layer are disposed in the same layer and formed through the same patterning process.
  • the present disclosure also provides a display device including the display substrate of the foregoing embodiments.
  • the display device can be any product or component that has a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator.

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Abstract

一种显示基板及其制备方法、显示装置。显示基板包括包括显示区域和位于所述显示区域一侧的绑定区域，所述绑定区域包括源驱动电路、柔性电路板、第一选择器电路、第二选择器电路和多条选择连接线，对于所述多条选择连接线中的至少一条选择连接线，所述选择连接线的一端连接所述第一选择器电路的输入端口，另一端连接所述第二选择器电路的输入端口；所述柔性电路板设置在所述源驱动电路远离所述显示区域的一侧，所述多条选择连接线设置在所述源驱动电路与所述柔性电路板之间。

Description

显示基板及其制备方法、显示装置 技术领域
本公开涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度等优点。随着显示技术的不断发展，以OLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开示例性实施例提供了一种显示基板，包括显示区域和位于所述显示区域一侧的绑定区域，所述绑定区域包括源驱动电路、柔性电路板、第一选择器电路、第二选择器电路和多条选择连接线，对于所述多条选择连接线中的至少一条选择连接线，所述选择连接线的一端连接所述第一选择器电路的输入端口，另一端连接所述第二选择器电路的输入端口；所述柔性电路板设置在所述源驱动电路远离所述显示区域的一侧，所述多条选择连接线设置在所述源驱动电路与所述柔性电路板之间。
在示例性实施方式中，沿着平行于显示区域边缘的方向，所述第一选择器电路和第二选择器电路分别设置在所述源驱动电路的两侧；所述显示区域边缘是所述显示区域邻近所述绑定区域一侧的边缘。
在示例性实施方式中，所述柔性电路板上设置有多个选择器引脚，沿着平行于显示区域边缘的方向，所述多个选择器引脚设置在所述柔性电路板的 两侧；对于所述多个选择器引脚中的至少一个选择器引脚，所述选择器引脚通过选择引线与所述选择连接线连接，或者通过选择引线与所述第一选择器电路或第二选择器电路的输入端口连接。
在示例性实施方式中，在垂直于显示基板的平面内，所述绑定区域包括：设置在基底上的绑定结构层；设置在所述绑定结构层上的复合绝缘层；设置在所述复合绝缘层上的多条选择连接线。
在示例性实施方式中，所述绑定结构层包括：
设置在基底上的第一绝缘层和第二绝缘层；
设置在所述第二绝缘层上的第一信号连接线；
覆盖所述第一信号连接线的第三绝缘层和第四绝缘层，其上开设有暴露出所述第一信号连接线的两个第一过孔；
设置在所述第四绝缘层上的驱动芯片信号线和电路板信号线，所述驱动芯片信号线的一端与所述源驱动电路连接，所述驱动芯片信号线的另一端通过所述第一过孔与所述第一信号连接线的第一端连接；所述电路板信号线的一端与所述柔性电路板连接，所述电路板信号线的另一端通过所述第一过孔与所述第一信号连接线的第二端连接。
在示例性实施方式中，所述绑定结构层包括：
设置在基底上的第一绝缘层、第二绝缘层和第三绝缘层；
设置在所述第三绝缘层上的第二信号连接线；
覆盖所述第二信号连接线的第四绝缘层，其上开设有暴露出所述第二信号连接线的两个第二过孔；
设置在所述第四绝缘层上的驱动芯片信号线和电路板信号线，所述驱动芯片信号线的一端与所述源驱动电路连接，所述驱动芯片信号线的另一端通过所述第二过孔与所述第二信号连接线的第一端连接；所述电路板信号线的一端与所述柔性电路板连接，所述电路板信号线的另一端通过所述第二过孔与第二信号连接线的第二端连接。
在示例性实施方式中，所述绑定结构层包括：
设置在基底上的第一绝缘层和第二绝缘层；
设置在所述第二绝缘层上的第一信号连接线；
覆盖所述第一信号连接线的第三绝缘层；
设置在所述第三绝缘层上的第二信号连接线；
覆盖所述第二信号连接线的第四绝缘层，其上开设有暴露出所述第一信号连接线的两个第一过孔，以及暴露出所述第二信号连接线的两个第二过孔；
设置在所述第四绝缘层上的驱动芯片信号线和电路板信号线，所述驱动芯片信号线的一端与所述源驱动电路连接，所述驱动芯片信号线的另一端通过所述第一过孔和第二过孔分别与所述第一信号连接线和第二信号连接线的第一端连接；所述电路板信号线的一端与所述柔性电路板连接，所述电路板信号线的另一端通过所述第一过孔和第二过孔分别与所述第一信号连接线和第二信号连接线的第二端连接。
在示例性实施方式中，所述复合绝缘层上还设置有至少两条屏蔽线，所述至少两条屏蔽线分别设置在所述多条选择连接线邻近所述显示区域的一侧和远离所述显示区域的一侧，沿着远离所述显示区域的方向，所述屏蔽线在基底上正投影的宽度大于所述选择连接线在基底上正投影的宽度。
在示例性实施方式中，所述第四绝缘层上还设置有屏蔽板，所述屏蔽板设置在所述驱动芯片信号线和电路板信号线之间，沿着远离所述显示区域的方向，所述多条选择连接线在基底上正投影的边界位于所述屏蔽板在基底上正投影的边界范围内。
在示例性实施方式中，在垂直于显示基板的平面内，所述显示区域包括在基底上叠设的第一绝缘层、有源层、第二绝缘层、第一栅金属层、第三绝缘层、第二栅金属层、第四绝缘层、第一源漏金属层、复合绝缘层和第二源漏金属层；所述第一信号连接线与所述第一栅金属层同层设置；所述第二信号连接线与所述第二栅金属层同层设置；所述驱动芯片信号线和电路板信号线与所述第一源漏金属层同层设置；所述多条选择连接线与所述第二源漏金属层同层设置。
在示例性实施方式中，所述驱动芯片信号线和电路板信号线是第一电源 线VDD，或者，所述驱动芯片信号线和电路板信号线是第二电源线VSS。
在示例性实施方式中，所述绑定区域包括：
设置在基底上的第一绝缘层和第二绝缘层；
设置在所述第二绝缘层上的第一选择连接线和至少两条第一屏蔽线，所述至少两条第一屏蔽线分别设置在所述多条第一选择连接线的两侧；
覆盖所述第一选择连接线和至少两条第一屏蔽线的第三绝缘层；
设置在所述第三绝缘层上的第二选择连接线和至少两条第二屏蔽线，所述至少两条第二屏蔽线分别设置在所述多条第二选择连接线的两侧；
覆盖所述第二选择连接线和至少两条第二屏蔽线的第四绝缘层；
设置在所述第四绝缘层上的屏蔽板，所述多条第一选择连接线或多条第二选择连接线在基底上正投影的边界位于所述屏蔽板在基底上正投影的边界范围内；
设置在所述屏蔽板上的复合绝缘层；
设置在所述复合绝缘层上的多条第三信号连接线。
在示例性实施方式中，在垂直于显示基板的平面内，所述显示区域包括在基底上叠设的第一绝缘层、有源层、第二绝缘层、第一栅金属层、第三绝缘层、第二栅金属层、第四绝缘层、第一源漏金属层、复合绝缘层和第二源漏金属层；所述第一选择连接线与所述第一栅金属层同层设置；所述第二选择连接线与所述第二栅金属层同层设置；所述屏蔽板与所述第一源漏金属层同层设置；所述第三信号连接线与所述第二源漏金属层同层设置。
另一方面，本公开示例性实施例还提供了一种显示装置，包括前述的显示基板。
又一方面，本公开示例性实施例还提供了一种显示基板的制备方法，显示基板包括显示区域和位于显示区域一侧的绑定区域，所述制备方法包括：
在所述绑定区域形成源驱动电路、柔性电路板、第一选择器电路、第二选择器电路和多条选择连接线；对于所述多条选择连接线中的至少一条选择连接线，所述选择连接线的一端连接所述第一选择器电路的输入端口，另一 端连接所述第二选择器电路的输入端口；所述柔性电路板设置在所述源驱动电路远离所述显示区域的一侧，所述多条选择连接线设置在所述源驱动电路与所述柔性电路板之间。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开示例性实施例显示基板的结构示意图；
图2为本公开示例性实施例显示基板中绑定区域的结构示意图；
图3为本公开示例性实施例选择连接线的示意图；
图4和图5为本公开示例性实施例选择连接线区的一种剖面示意图；
图6为本公开示例性实施例形成有源层图案后的示意图；
图7为本公开示例性实施例形成第一栅金属层图案后的示意图；
图8为本公开示例性实施例形成第二栅金属层图案后的示意图；
图9为本公开示例性实施例形成第四绝缘层图案后的示意图；
图10为本公开示例性实施例形成第一源漏金属层图案后的示意图；
图11为本公开示例性实施例形成复合绝缘层图案后的示意图；
图12为本公开示例性实施例形成第二源漏金属层图案后的示意图；
图13为本公开示例性实施例形成第二平坦层图案后的示意图；
图14为本公开示例性实施例选择连接线区的平面示意图；
图15和图16为本公开示例性实施例选择器电路的示意图；
图17为本公开示例性实施例选择连接线区的另一种剖面示意图。
附图标记说明:
1—玻璃载板；            10—基底；            11—第一绝缘层；
12—第二绝缘层；         13—第三绝缘层；      14—第四绝缘层；
15—第五绝缘层；         16—第一平坦层；      17—第二平坦层；
100—显示区域；          101—薄膜晶体管；     102—存储电容；
103—连接电极；          110—显示区域边缘；   200—绑定区域；
201—第一扇出区；        202—弯折区；         203—第二扇出区；
204—驱动芯片区；        205—电路板区；       206—选择器电路区；
207—选择连接线区；      210—第一选择器电路； 220—第二选择器电路；
230—触控引线；          300—柔性电路板；     301—第一信号连接线；
302—第二信号连接线；    303—屏蔽板；         304—驱动芯片信号线；
305—电路板信号线；      306—选择连接线；     306-1—第一选择连接线；
306-2—第二选择连接线；  307—屏蔽线；         308—第三信号连接线；
310—选择器引脚；        320—选择引线。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的 混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下 的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
在示例性实施方式中，OLED的触控基板采用柔性多层覆盖表面式(Flexible Multi Layer On Cell，简称FMLOC)结构形式，柔性的触控基板设置在OLED显示结构的封装层上，将显示结构和触摸结构集成在一起，具有轻薄、可折叠等优点，可以满足柔性折叠、窄边框等产品需求。
在示例性实施方式中，OLED包括显示区域、位于显示区域一侧的绑定区域和位于显示区域其它侧的边缘区域，显示区包括规则排布的多个发光单元，每个发光单元连接到至少一条栅线和至少一条数据线，绑定区域和边缘区域设置有驱动电路，驱动电路配置为向显示区域提供显示信号和触控信号。在示例性实施方式中，驱动电路可以包括：设置在显示区域两侧的阵列行驱动(Gate Driver On Array，简称GOA)电路，配置为向显示区域提供扫描信号；设置在绑定区域的源驱动电路(Driver IC)，配置为向显示区域提供数据信号；设置在绑定区域和边缘区域的触控引线，配置为向触控基板提供触控信号；设置在绑定区域的选择器(Multiplexer，简称MUX)电路，配置为对触控引线进行选择，以减少引出至触控基板的触控引线数量。阵列行驱动电路的信号线、源驱动电路的信号线和选择器电路的信号线通过设置在绑定区域的柔性电路板(Flexible Printed Circuit，简称FPC)与外部控制装置连接。在一些可能的实现方式中，驱动电路可以包括触控与显示驱动器集成电路(Touch and Display Driver Integration，简称TDDI)。
本公开示例性实施例提供了一种显示基板，包括显示区域和位于所述显示区域一侧的绑定区域，所述绑定区域包括源驱动电路、柔性电路板、第一选择器电路、第二选择器电路和多条选择连接线，对于所述多条选择连接线中的至少一条选择连接线，所述选择连接线的一端连接所述第一选择器电路 的输入端口，另一端连接所述第二选择器电路的输入端口；所述柔性电路板设置在所述源驱动电路远离所述显示区域的一侧，所述多条选择连接线设置在所述源驱动电路与所述柔性电路板之间。
在示例性实施方式中，沿着平行于显示区域边缘的方向，所述第一选择器电路和第二选择器电路分别设置在所述源驱动电路的两侧；所述显示区域边缘是所述显示区域邻近所述绑定区域一侧的边缘。
在示例性实施方式中，所述柔性电路板上设置有多个选择器引脚，沿着平行于显示区域边缘的方向，所述多个选择器引脚设置在所述柔性电路板的两侧；对于所述多个选择器引脚中的至少一个选择器引脚，所述选择器引脚通过选择引线与所述选择连接线连接。
图1为本公开示例性实施例显示基板的结构示意图。如图1所示，在示例性实施方式中，显示基板包括显示区域100和位于显示区域100周边的非显示区域，非显示区域包括位于显示区域100一侧的绑定区域200和位于显示区域100其它侧的边缘区域，显示区域100至少包括规则排列的多个显示单元，绑定区域200至少包括选择器电路、源驱动电路和将信号线连接至外部控制装置的柔性电路板，边缘区域至少包括阵列行驱动电路。
图2为本公开示例性实施例显示基板中绑定区域的结构示意图。如图2所示，在示例性实施方式中，在平行于显示基板的平面内，绑定区域200位于显示区域100的一侧，沿着远离显示区域100的方向，绑定区域200可以包括依次设置的第一扇出区201、弯折区202、第二扇出区203、驱动芯片区204和电路板区205，还可以包括选择连接线区206和选择器电路区207。第一扇出区201可以设置第一电源线、第二电源线和多条数据传输线，多条数据传输线配置为以扇出(Fanout)走线方式连接显示区域100的数据线(Data Line)，第一电源线(VDD)配置为连接显示区域100的高电平电源线，第二电源线(VSS)配置为连接边缘区域的低电平电源线。弯折区202可以设置凹槽，凹槽配置为使绑定区域200弯折到显示区域100的背面。第二扇出区203可以设置以扇出走线方式引出的多条数据传输线。驱动芯片区204可以设置源驱动电路(Driver IC)，配置为与第二扇出区203的多条数据传输线连接。电路板区205可以设置柔性电路板(FPC)，柔性电路板(FPC) 包括与源驱动电路的绑定焊盘(Bonding Pad)连接的多个引脚(PIN)，多个引脚配置为与外部控制装置连接。
在示例性实施方式中，沿着平行于显示区域边缘110的方向，选择器电路区207可以设置在驱动芯片区204的两侧，驱动芯片区204一侧的选择器电路区207可以设置第一选择器电路210，驱动芯片区204另一侧的选择器电路区207可以设置第二选择器电路220。显示区域边缘110是显示区域100邻近绑定区域200一侧的边缘。
在示例性实施方式中，沿着远离显示区域100的方向，选择连接线区206可以设置在驱动芯片区204与电路板区205之间。选择连接线区206可以设置多条选择连接线，多条选择连接线配置为在第一选择器电路210的输入端口与第二选择器电路220的输入端口之间实现连接，对于多条选择连接线中的至少一条选择连接线，该选择连接线的一端连接第一选择器电路210的一个输入端口，另一端连接第二选择器电路220的一个输入端口，实现第一选择器电路210和第二选择器电路220中输入信号相同的输入端口之间的连接。
在示例性实施方式中，绑定区域200可以包括配置为消除静电的防静电电路、配置为阻隔水汽进入显示区域的隔离坝以及其它布线区，本公开在此不做限定。
图3为本公开示例性实施例选择连接线的示意图。如图3所示，第一选择器电路210和第二选择器电路220分别设置在驱动芯片区的两侧，每个选择器电路包括M个输入端口，第一选择器电路210的N个输入端口与第二选择器电路220的N个输入端口之间通过N条选择连接线306对应连接，即第一选择器电路210的第一输入端口与第二选择器电路220的第一输入端口之间通过第一条选择连接线306相互连接，……，第一选择器电路210的第N输入端口与第二选择器电路220的第N输入端口之间通过第N条选择连接线306相互连接。M为大于2的正整数，N为大于或等于2的正整数，N小于或等于M。在示例性实施方式中，第一选择器电路210的第i输入端口和第二选择器电路220的第i输入端口输入的信号相同，i＝1，……，N。
柔性电路板300上设置有n个选择器引脚310，n＝2M-N，n个选择器引脚310可以被划分为二组。在示例性实施方式中，N可以为大于或等于2的 偶数，则每组中包括n/2个选择器引脚310。第一组n/2个选择器引脚310设置在柔性电路板300的左侧，与第一选择器电路210邻近，第二组的n/2个选择器引脚310设置在柔性电路板300的右侧，与第二选择器电路220邻近。在示例性实施方式中，N可以为大于或等于2的奇数，则第一组可以包括(n-1)/2个选择器引脚310，第二组可以包括(n+1)/2个选择器引脚310，或者，第一组可以包括(n+1)/2个选择器引脚310，第二组可以包括(n-1)/2个选择器引脚310。第一组设置在柔性电路板300的左侧，与第一选择器电路210邻近，第二组设置在柔性电路板300的右侧，与第二选择器电路220邻近。在示例性实施方式中，柔性电路板300上可以设置有其它引脚，本公开在此不做限定。
n个选择器引脚310中，N个选择器引脚310分别通过N条选择引线320与N条选择连接线306对应连接，n-N个选择器引脚310分别通过n-N条选择引线320与第一选择器电路210和第二选择器电路220的n-N个输入端口对应连接，即第一选择器引脚310通过第一条选择引线320与第一条选择连接线306连接，……，第N选择器引脚310通过第N条选择引线320与第N条选择连接线306连接，第N+1选择器引脚310通过第N+1条选择引线320与第一选择器电路210的第N+1输入端口连接，或者与第二选择器电路220的第N+1输入端口连接，……，第n选择器引脚310通过第n条选择引线320与第一选择器电路210的第M输入端口连接，或者与第二选择器电路220的第M输入端口连接。
在示例性实施方式中，第一组n/2个选择器引脚310中，N/2个选择器引脚310与N/2条选择连接线306连接，(M-N)个选择器引脚310与第一选择器电路210的(M-N)个输入端口连接。第二组n/2个选择器引脚310中，N/2个选择器引脚310与另外N/2条选择连接线306连接，(M-N)个选择器引脚310与第二选择器电路220的(M-N)个输入端口连接。
本公开示例性实施例中，第一选择器电路210和第二选择器电路220总共有2M个输入端口，由于设置了N条选择连接线306，N条选择连接线306分别在第一选择器电路210的N个输入端口与第二选择器电路220的N个输入端口之间建立连接，因此柔性电路板300上只需要设置2M-N个选择器引 脚310，即可实现2M个输入端口的信号输入，而不需要在柔性电路板300上设置2M个选择器引脚310，有效减少了选择器引脚的数量，既有利于柔性电路板300的引脚排布，又有利于提高信号输入的可靠性。
在示例性实施方式中，可以根据第一选择器电路210和第二选择器电路220的输入信号来确定选择连接线306的数量。在一些可能的实现方式中，可以设置N＝M，柔性电路板300上只需要设置M个选择器引脚310，即可实现第一选择器电路210和第二选择器电路220的信号输入。
本公开示例性实施例中，通过将第一选择器电路和第二选择器电路分别设置在驱动芯片区的两侧，两组选择器引脚分别设置在柔性电路板的两侧，多条选择连接线设置为在第一选择器电路的多个输入端口与第二选择器电路的多个输入端口之间建立连接，不仅有效减少了选择器引脚的数量，而且不会增加绑定区域的宽度，提高了产品的竞争力。
图4和图5为本公开示例性实施例选择连接线区的一种剖面示意图，图4为图2中A-A向的剖视图，图5为图2中B-B向的剖视图。在示例性实施方式中，N条选择连接线306设置在选择连接线区206，即设置在驱动芯片区204与电路板区205之间。如图4和图5所示，在垂直于显示基板的平面内，选择连接线区206包括：在基底10上叠设的第一绝缘层11和第二绝缘层12，设置在第二绝缘层12上的第一信号连接线301，设置在第一信号连接线301上的第三绝缘层13，设置在第三绝缘层13上的第二信号连接线302，设置在第二信号连接线302上的第四绝缘层14，设置在第四绝缘层14上的屏蔽板303，设置在屏蔽板303上的第五绝缘层15和第一平坦层16，设置在第一平坦层16上的多条选择连接线306，设置在选择连接线306上的第二平坦层17。选择连接线区206还包括与选择连接线306同层设置的屏蔽线307，屏蔽线307设置在多条选择连接线306的两侧。
在示例性实施方式中，选择连接线区206邻近显示区域一侧为驱动芯片区204，驱动芯片区204设置有驱动芯片信号线304，选择连接线区206远离显示区域一侧为电路板区205，电路板区205设置有电路板信号线305。在示例性实施方式中，驱动芯片信号线304和电路板信号线305与屏蔽板303同层设置。
在示例性实施方式中，第一信号连接线301和第二信号连接线302配置为在驱动芯片信号线304与电路板信号线305之间建立连接，使源驱动电路的信号穿越选择连接线区206到达柔性电路板。
在示例性实施方式中，驱动芯片信号线304的一端与驱动芯片区204中的源驱动电路连接，另一端通过第一过孔和第二过孔分别与第一信号连接线301和第二信号连接线302的第一端连接。电路板信号线305的一端与电路板区205的柔性电路板连接，另一端通过第一过孔和第二过孔分别与第一信号连接线301和第二信号连接线302的第二端连接。
在示例性实施方式中，图4和图5所示结构可以只包括第一信号连接线301，或者只包括第二信号连接线302，同样可以实现在驱动芯片信号线304与电路板信号线305之间建立连接。
在示例性实施方式中，在垂直于显示基板的平面内，显示区域100包括：设置在基底上的第一绝缘层，设置在第一绝缘层上的有源层，设置在有源层上的第二绝缘层，设置在第二绝缘层上的第一栅金属层，设置在第一栅金属层上的第三绝缘层，设置在第三绝缘层上的第二栅金属层，设置在第二栅金属层上的第四绝缘层，设置在第四绝缘层上的第一源漏金属层，设置在第一源漏金属层上的第五绝缘层和第一平坦层，设置在第一平坦层上的第二源漏金属层。
在示例性实施方式中，选择连接线区206的第一信号连接线301与显示区域100的第一栅金属层同层设置，且通过同一次图案化工艺同时形成。
在示例性实施方式中，选择连接线区206的第二信号连接线302与显示区域100的第二栅金属层同层设置，且通过同一次图案化工艺同时形成。
在示例性实施方式中，选择连接线区206的屏蔽板303与显示区域100的第一源漏金属层同层设置，且通过同一次图案化工艺同时形成。
在示例性实施方式中，选择连接线区206的选择连接线306与显示区域100的第二源漏金属层同层设置，且通过同一次图案化工艺同时形成。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模 曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“A的正投影包含B的正投影”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
(1)在玻璃载板1上制备基底10。在示例性实施方式中，基底10可以包括在玻璃载板1上叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称之为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。在一示例性实施方式中，以叠层结构PI1/Barrier1/a-si/PI2/Barrier2为例，其制备过程可以包括：先在玻璃载板1上涂布一层聚酰亚胺，固化成膜后形成第一柔性(PI1)层；随后在第一柔性层上沉积一层阻挡薄膜，形成覆盖第一柔性层的第一阻挡(Barrier1)层；然后在第一阻挡层上沉积一层非晶硅薄膜，形成覆盖第一阻挡层的非晶硅(a-si)层；然后在非晶硅层上再涂布一层聚酰亚胺，固化成膜后形成第二柔性(PI2)层；然后在第二柔性层上沉积一层阻挡薄膜，形成覆盖第二柔性层的第二阻挡(Barrier2)层，完成基底10的制备。
在示例性实施方式中，基底10可以是硬质基底。
(2)在基底10上依次沉积第一绝缘薄膜和有源层薄膜，通过图案化工 艺对有源层薄膜进行图案化处理，形成覆盖整个基底10的第一绝缘层11，以及设置在第一绝缘层11上的有源层图案，有源层图案至少包括形成在显示区域100的第一有源层，如图6所示。本次图案化工艺后，绑定区域的驱动芯片区204、电路板区205和选择连接线区206包括设置在基底10上的第一绝缘层11。
(3)依次沉积第二绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化处理，形成覆盖有源层图案的第二绝缘层12，以及设置在第二绝缘层12上的第一栅金属层图案，第一栅金属层图案至少包括第一栅电极、第一电容电极和第一信号连接线301，第一栅电极和第一电容电极形成在显示区域100，第一信号连接线301形成在绑定区域的选择连接线区206、驱动芯片区204邻近选择连接线区206的区域以及电路板区205邻近选择连接线区206的区域，如图7所示。本次图案化工艺后，绑定区域的选择连接线区206包括在基底10叠设的第一绝缘层11、第二绝缘层12和第一信号连接线301。在示例性实施方式中，由于选择连接线区206设置有多条选择连接线，多条选择连接线沿着平行于显示区域边缘的方向延伸，因而驱动芯片区204中源驱动电路的信号线与电路板区205中柔性电路板的信号线需要穿越选择连接线区206。本公开示例性实施例中，第一信号连接线301配置为连接后续形成的源驱动电路的信号线与柔性电路板的信号线，使得源驱动电路的信号线与柔性电路板的信号线通过第一信号连接线301实现连接，保证信号的传输。
(4)依次沉积第三绝缘薄膜和第二金属薄膜，通过图案化工艺对第二金属薄膜进行图案化处理，形成覆盖第一栅金属层的第三绝缘层13，以及设置在第三绝缘层13上的第二栅金属层图案，第二栅金属层图案至少包括第二电容电极和第二信号连接线302，第二电容电极形成在显示区域100，第二电容电极的位置与第一电容电极的位置相对应，第二信号连接线302形成在绑定区域的选择连接线区206、驱动芯片区204邻近选择连接线区206的区域以及电路板区205邻近选择连接线区206的区域，如图8所示。本次图案化工艺后，绑定区域的选择连接线区206包括在基底10上叠设的第一绝缘层11、第二绝缘层12、第一信号连接线301、第三绝缘层13和第二信号连接线 302。在示例性实施方式中，第二信号连接线302配置为连接后续形成的源驱动电路的信号线与柔性电路板的信号线。
(5)沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行图案化处理，形成覆盖第二栅金属层的第四绝缘层14图案，第四绝缘层14上开设有多个过孔，多个过孔至少包括两个有源过孔V1、两个第一过孔K1和两个第二过孔K2，如图9所示。
在示例性实施方式中，两个有源过孔V1形成在显示区域100，两个有源过孔V1内的第四绝缘层14、第三绝缘层13和第二绝缘层12被刻蚀掉，暴露出第一有源层的表面。
在示例性实施方式中，一个第二过孔K2和一个第一过孔K1形成在绑定区域的驱动芯片区204，第二过孔K2与选择连接线区206的距离小于第一过孔K1与选择连接线区206的距离，第一过孔K1内的第四绝缘层14和第三绝缘层13被刻蚀掉，暴露出第一信号连接线301第一端的表面，第二过孔K2内的第四绝缘层14被刻蚀掉，暴露出第二信号连接线302第一端的表面。第一端是第一信号连接线301和第二信号连接线302邻近驱动芯片区204的一端。
在示例性实施方式中，另一个第二过孔K2和另一个第一过孔K1形成在绑定区域的电路板区205，第二过孔K2与选择连接线区206的距离小于第一过孔K1与选择连接线区206的距离，第一过孔K1内的第四绝缘层14和第三绝缘层13被刻蚀掉，暴露出第一信号连接线301第二端的表面，第二过孔K2内的第四绝缘层14被刻蚀掉，暴露出第二信号连接线302第二端的表面。第二端是第一信号连接线301和第二信号连接线302邻近电路板区205的一端。
本次图案化工艺后，绑定区域的选择连接线区206包括在基底10上叠设的第一绝缘层11、第二绝缘层12、第一信号连接线301、第三绝缘层13、第二信号连接线302和第四绝缘层14。
在示例性实施方式中，两个有源过孔V1配置为使后续形成的第一源电极和第二漏电极分别与第一有源层连接。两个第二过孔K2配置为使后续形 成的驱动芯片信号线和电路板信号线分别与第二信号连接线302连接，两个第一过孔K1配置为使后续形成的驱动芯片信号线和电路板信号线分别与第一信号连接线301连接，实现源驱动电路的信号线与柔性电路板的信号线之间的连接。
(6)沉积第三金属薄膜，通过图案化工艺对第三金属薄膜进行图案化处理，在第四绝缘层14上形成第一源漏金属层图案，第一源漏金属层至少包括第一源电极、第一漏电极、屏蔽板303、驱动芯片信号线304和电路板信号线305，如图10所示。
在示例性实施方式中，第一源电极和第一漏电极形成在显示区域100，分别通过第一过孔与第一有源层连接。
在示例性实施方式中，屏蔽板303形成在绑定区域的选择连接线区206，配置为对后续形成的选择连接线提供屏蔽功能。在示例性实施方式中，屏蔽板303可以连接像素驱动电路的第一电源线VDD，或者可以连接像素驱动电路的第二电源线VSS，或者可以连接阵列行驱动电路的高电压电源线VGH，或者可以连接阵列行驱动电路的低电压电源线VGL。
在示例性实施方式中，驱动芯片信号线304形成在绑定区域的驱动芯片区204，远离选择连接线区206的一端与源驱动电路连接，邻近选择连接线区206的一端通过第一过孔与第一信号连接线301的第一端连接，通过第二过孔与第二信号连接线302的第一端连接。
在示例性实施方式中，电路板信号线305形成在绑定区域的电路板区205，远离选择连接线区206的一端与柔性电路板连接，邻近选择连接线区206的一端通过第一过孔与第一信号连接线301的第二端连接，通过第二过孔与第二信号连接线302的第二端连接。
这样，在选择连接线区206形成了连接驱动芯片信号线304和电路板信号线305的双信号连接线结构。在驱动芯片区204和电路板区205，驱动芯片信号线304和电路板信号线305设置在第一源漏金属层(SD1)，在选择连接线区206，信号线分别设置在第一栅金属层(Gate1)和第二栅金属层(Gate2)。也就是说，在选择连接线区206，信号线在Gate1层和Gate2层， 在选择连接线区206以外区域，信号线在SD1层。本公开示例性实施例的双信号连接线结构，既降低了连接电阻，又保证了信号传输的可靠性。
在示例性实施方式中，可以只在第一栅金属层上设置第一信号连接线301，第四绝缘层14上只开设两个第一过孔K1，形成单信号连接线结构。或者，可以只在第二栅金属层上设置第二信号连接线302，第四绝缘层14上只开设两个第二过孔K2，形成单信号连接线结构。
(7)在形成前述图案的基底10上，先沉积一层第五绝缘薄膜，后涂覆一层有机材料的第一平坦薄膜，形成覆盖整个基底10的第五绝缘层15和设置在第五绝缘层15上的第一平坦(PLN)层16，通过掩膜、曝光、显影的图案化工艺，在第一平坦层16上形成有连接过孔V2，连接过孔V2形成在显示区域100，连接过孔V2内的第一平坦层16和第五绝缘层15被去掉，暴露出第一晶体管101的第一漏电极的表面，如图11所示。在示例性实施方式中，第一平坦层16可以只形成在绑定区域的选择连接线区206，第五绝缘层15和第一平坦层16称为复合绝缘层。
在示例性实施方式中，复合绝缘层可以只包括第五绝缘层15，或者只包括第一平坦层16。对于复合绝缘层只包括第一平坦层16情况，可以在形成前述图案的基底上直接形成第一平坦层16，第一平坦层16可以形成在绑定区域的驱动芯片区204、电路板区205和选择连接线区206。
(8)在形成前述图案的基底上，沉积第四金属薄膜，通过图案化工艺对第四金属薄膜进行图案化处理，在第一平坦层16上形成第二源漏金属层图案，第二源漏金属层至少包括连接电极103、多条选择连接线306和至少两条屏蔽线307，连接电极103形成在显示区域100，通过连接过孔与第一晶体管101的第一漏电极连接。多条选择连接线306和至少两条屏蔽线307形成在绑定区域的选择连接线区206，如图12所示。
在示例性实施方式中，多条选择连接线306间隔设置，多条选择连接线306配置为在第一选择器电路210的多个输入端口和第二选择器电路220的多个输入端口之间建立连接。对于多条选择连接线306中的至少一条选择连接线306，该选择连接线306的一端连接第一选择器电路的输入端口，另一端连接第二选择器电路的输入端口。
在示例性实施方式中，两条屏蔽线307分别设置在多条选择连接线306的两侧，即至少一条屏蔽线307设置在选择连接线区206邻近驱动芯片区204的一侧(即多条选择连接线邻近显示区域的一侧)，至少一条屏蔽线307设置在选择连接线区206邻近电路板区205的一侧(即多条选择连接线远离显示区域的一侧)，至少两条屏蔽线307配置为多条选择连接线306提供侧向屏蔽功能。
在示例性实施方式中，沿着远离显示区域的方向，屏蔽线307在基底上正投影的宽度大于选择连接线306在基底上正投影的宽度。本公开示例性实施例中，“宽度”是指沿着远离显示区域方向的特征尺寸。
在示例性实施方式中，多条选择连接线306在基底上正投影的边界位于屏蔽板303在基底上正投影的边界范围内。
在示例性实施方式中，至少两条屏蔽线307在基底上正投影的边界位于屏蔽板303在基底上正投影的边界范围内。
在示例性实施方式中，至少两条屏蔽线307可以连接像素驱动电路的第一电源线VDD，或者可以连接像素驱动电路的第二电源线VSS，或者可以连接阵列行驱动电路的高电压电源线VGH，或者可以连接阵列行驱动电路的低电压电源线VGL。
在示例性实施方式中，每条选择连接线306的宽度约为1.5μm至6.0μm，相邻选择连接线306之间间距的宽度约为2.0μm至6.0μm。每条屏蔽线307的宽度约为10μm至20μm，屏蔽板303的宽度约为500μm至700μm。
在示例性实施方式中，驱动芯片区204和电路板区205可以形成相应的信号线和引脚，本公开在此不做限定。
(9)在形成前述图案的基底10上，涂覆一层有机材料的第二平坦薄膜，通过掩膜、曝光、显影的图案化工艺，形成覆盖整个基底10的第二平坦层17，第二平坦层17上形成有阳极过孔V3，阳极过孔V3形成在显示区域100，阳极过孔V3内的第二平坦层17被去掉，暴露出连接电极103的表面，如图13所示。
至此，在基底10上制备完成显示区域100的驱动结构层和绑定区域200 的绑定结构层图案。如图13所示，显示区域100的驱动结构层中，第一有源层、第一栅电极、第一源电极和第一漏电极组成第一晶体管101，第一电容电极和第二电容电极组成第一存储电容102。
绑定区域200的绑定结构层包括：
设置在基底10上的第一绝缘层11和第二绝缘层12；
设置在第二绝缘层12上的第一信号连接线301；
覆盖第一信号连接线301的第三绝缘层13；
设置在第三绝缘层13上的第二信号连接线302；
覆盖第二信号连接线302的第四绝缘层14，其上开设有多个过孔，多个过孔包括：暴露出第一信号连接线301的第一端和第二端的两个第一过孔K1，暴露出第二信号连接线302的第一端和第二端的两个第二过孔K2；
设置在第四绝缘层14上的屏蔽板303、驱动芯片信号线304和电路板信号线305；屏蔽板303形成在绑定区域的选择连接线区206；驱动芯片信号线304形成在绑定区域的驱动芯片区204，通过第一端的一个第一过孔K1和一个第二过孔K2分别与第一信号连接线301和第二信号连接线302的第一端连接；电路板信号线305形成在绑定区域的电路板区205，通过第二端的一个第一过孔K1和一个第二过孔K2分别与第一信号连接线301和第二信号连接线302的第二端连接；
覆盖屏蔽板303、驱动芯片信号线304和电路板信号线305的第五绝缘层15和设置在第五绝缘层15上的第一平坦层16；
设置在第一平坦层16上的多条选择连接线306和至少两条屏蔽线307，至少两条屏蔽线307分别设置在多条选择连接线306的两侧；
覆盖多条选择连接线306和至少两条屏蔽线307的第二平坦层17。
在示例性实施方式中，显示基板还包括形成在显示区域100的阳极、像素定义(PDL)层、隔垫柱(PS)、有机发光层、阴极和封装层，封装层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层采用无机材料，第二封装层采用有机材料。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层称之为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层称之为栅绝缘(GI)层，第四绝缘层称之为层间绝缘(ILD)层，第五绝缘层称之为钝化(PVX)层。第一金属薄膜、第二金属薄膜、第三金属薄膜和第四金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。有源层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等各种材料，即本公开适用于基于氧化物Oxide技术、硅技术以及有机物技术制造的晶体管。
通过本公开示例性实施例显示基板的结构及其制备过程可以看出，本公开示例性实施例通过在选择连接线区设置多条选择连接线，多条选择连接线在第一选择器电路210的多个输入端口和第二选择器电路220的多个输入端口之间建立连接，使得第一选择器电路210和第二选择器电路220中输入信号相同的输入端口连接在一起，只需要一个选择器引脚即可实现两个输入端口的信号输入，有效减少了选择器引脚的数量，既有利于柔性电路板的引脚排布，又有利于提高信号输入的可靠性。本公开示例性实施例通过将第一选择器电路和第二选择器电路分别设置在驱动芯片区的两侧，选择器电路的引脚分别设置在柔性电路板的两侧，不会增加绑定区域的宽度，提高了产品的竞争力。
本公开示例性实施例利用第一栅金属层和第二栅金属层分别形成第一信号连接线和第二信号连接线，实现了驱动芯片信号线与电路板信号线之间的连接，保证信号的传输。通过双信号连接线结构，既降低了连接电阻，又保证了信号传输的可靠性。
本公开示例性实施例利用第一源漏金属层形成对选择连接线提供屏蔽功能的屏蔽板，避免了第一信号连接线和第二信号连接线对多条选择连接线的 干扰，避免了多条选择连接线对第一信号连接线和第二信号连接线的干扰，提高了信号传输的可靠性。
本公开示例性实施例通过在多条选择连接线两侧形成屏蔽线，屏蔽线为多条选择连接线提供侧向屏蔽功能，避免了驱动芯片区和电路板区的信号线对多条选择连接线的干扰，避免了多条选择连接线对驱动芯片区和电路板区的信号线的干扰，提高了工作可靠性。
本公开示例性实施例显示基板的结构及其制备过程仅仅是一种示例性说明。在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少图案化工艺，本公开在此不做限定。
图14为本公开示例性实施例选择连接线区的平面示意图。如图14所示，屏蔽板303设置在第一源漏金属层，对其下方的第一信号连接线和第二信号连接线以及对其上方的选择连接线306提供屏蔽功能，两条屏蔽线307设置在多条选择连接线306的两侧，为多条选择连接线306提供侧向屏蔽功能。驱动芯片信号线304邻近选择连接线区206的一端和电路板信号线305邻近选择连接线区206的一端通过设置在第一栅金属层的第一信号连接线和设置在第二栅金属层的第二信号连接线连接，驱动芯片信号线304远离选择连接线区206的一端与驱动芯片区204的源驱动电路连接，电路板信号线305远离选择连接线区206的一端与电路板区205的柔性电路板连接。
图15和图16为本公开示例性实施例选择器电路的平面示意图。如图15所示，第一选择器电路210的输出端口通过多条触控引线(TSP Trace)230与显示区域的触控电极连接，第一选择器电路210的一部分输入端口通过选择引线320与柔性电路板左侧的部分选择器引脚310连接，第一选择器电路210的另一部分输入端口通过多条选择连接线306与第二选择器电路的输入端口连接，且多条选择连接线306通过选择引线320与柔性电路板左侧的另一部分选择器引脚310连接。在多条选择连接线306所在区域，第一电源线VDD和第二电源线VSS设置在第一栅金属层和第二栅金属层，在多条选择连接线306以外区域，第一电源线VDD和第二电源线VSS设置在第一源漏金属层。如图16所示，第二选择器电路220的输出端口通过多条触控引线(TSP Trace)230与显示区域的触控电极连接，第二选择器电路220的一部 分输入端口通过选择引线320与柔性电路板右侧的部分选择器引脚310连接，第一选择器电路210的另一部分输入端口通过多条选择连接线306与第一选择器电路的输入端口连接，且多条选择连接线306通过选择引线320与柔性电路板右侧的另一部分选择器引脚310连接。在多条选择连接线306所在区域，第一电源线VDD和第二电源线VSS设置在第一栅金属层和第二栅金属层，在多条选择连接线306以外区域，第一电源线VDD和第二电源线VSS设置在第一源漏金属层。
图17为本公开示例性实施例选择连接线区的另一种剖面示意图，为图2中B-B向的剖视图。如图17所示，在垂直于显示基板的平面内，绑定区域的选择连接线区206包括：在基底10上叠设的第一绝缘层11和第二绝缘层12，设置在第二绝缘层12上的多条第一选择连接线306-1，设置在第一选择连接线306-1上的第三绝缘层13，设置在第三绝缘层13上的多条第二选择连接线306-2，设置在第二选择连接线306-2上的第四绝缘层14，设置在第四绝缘层14上的屏蔽板303，设置在屏蔽板303上的第五绝缘层15和第一平坦层16，设置在第一平坦层16上的第三信号连接线308，设置在第三信号连接线308选择连接线306上的第二平坦层17。
在示例性实施方式中，选择连接线区206还包括与第一选择连接线306-1同层设置的至少二条第一屏蔽线，至少二条第一屏蔽线设置在多条第一选择连接线306-1的两侧。
在示例性实施方式中，选择连接线区206还包括与第二选择连接线306-2同层设置的至少二条第二屏蔽线，至少二条第二屏蔽线设置在多条第二选择连接线306-2的两侧。
在示例性实施方式中，第一选择连接线306-1与显示区域100的第一栅金属层同层设置，且通过同一次图案化工艺同时形成，第二选择连接线306-2与显示区域100的第二栅金属层同层设置，且通过同一次图案化工艺同时形成，屏蔽板303与显示区域100的第一源漏金属层同层设置，且通过同一次图案化工艺同时形成，第三信号连接线308与显示区域100的第二源漏金属层同层设置，且通过同一次图案化工艺同时形成。
在示例性实施方式中，绑定区域的驱动芯片区204形成有驱动芯片信号 线，绑定区域的电路板区形成有电路板信号线，驱动芯片信号线和电路板信号线与屏蔽板303同层设置，且通过同一次图案化工艺同时形成。驱动芯片信号线远离选择连接线区206的一端与源驱动电路连接，邻近选择连接线区206的一端通过过孔与第三信号连接线308的第一端连接。电路板信号线远离选择连接线区206的一端与柔性电路板连接，邻近选择连接线区206的一端通过过孔与第三信号连接线308的第二端连接。第三信号连接线308形成了连接驱动芯片信号线和电路板信号线的单信号连接线结构。
在示例性实施方式中，多条第一选择连接线306-1和多条第二选择连接线306-2配置为在第一选择器电路210的多个输入端口和第二选择器电路220的多个输入端口之间建立连接。对于第一选择连接线306-1中的任意一条第一选择连接线306-1，该第一选择连接线306-1的一端连接第一选择器电路的输入端口，另一端连接第二选择器电路的输入端口。对于第二选择连接线306-2中的任意一条第二选择连接线306-2，该第二选择连接线306-2的一端连接第一选择器电路的输入端口，另一端连接第二选择器电路的输入端口。
在示例性实施方式中，第一选择连接线306-1和第二选择连接线306-2可以连接不同的输入端口，多条选择连接线分别设置在两层，可以减小选择连接线区206的宽度。
在示例性实施方式中，第一选择连接线306-1和第二选择连接线306-2可以连接相同的输入端口，两层的多条选择连接线可以形成双选择连接线结构，既降低了连接电阻，又保证了信号传输的可靠性。
本公开还提供了一种显示基板的制备方法，显示基板包括显示区域和位于显示区域一侧的绑定区域。在示例性实施方式中，所述制备方法包括：
在所述绑定区域形成源驱动电路、柔性电路板、第一选择器电路、第二选择器电路和多条选择连接线；对于所述多条选择连接线中的至少一条选择连接线，所述选择连接线的一端连接所述第一选择器电路的输入端口，另一端连接所述第二选择器电路的输入端口；所述柔性电路板设置在所述源驱动电路远离所述显示区域的一侧，所述多条选择连接线设置在所述源驱动电路与所述柔性电路板之间。
在示例性实施方式中，在所述绑定区域形成源驱动电路、柔性电路板、 第一选择器电路、第二选择器电路和多条选择连接线，包括：
在基底上形成第一绝缘层和第二绝缘层；
在所述第二绝缘层上形成第一信号连接线；
形成覆盖所述第一信号连接线的第三绝缘层和第四绝缘层，其上开设有暴露出所述第一信号连接线的两个第一过孔；
在所述第四绝缘层上形成驱动芯片信号线和电路板信号线，所述驱动芯片信号线的一端与所述源驱动电路连接，所述驱动芯片信号线的另一端通过一个第一过孔与所述第一信号连接线的一端连接；所述电路板信号线的一端与所述柔性电路板连接，所述电路板信号线的另一端通过一个第一过孔与所述第一信号连接线的另一端连接；
形成覆盖所述驱动芯片信号线和电路板信号线的复合绝缘层；
在所述复合绝缘层上形成多条选择连接线。
在示例性实施方式中，在所述绑定区域形成源驱动电路、柔性电路板、第一选择器电路、第二选择器电路和多条选择连接线，包括：
在基底上形成第一绝缘层、第二绝缘层和；第三绝缘层；
在所述第三绝缘层上形成第二信号连接线；
形成覆盖所述第二信号连接线的第四绝缘层，其上开设有暴露出所述第二信号连接线的两个第二过孔；
在所述第四绝缘层上形成驱动芯片信号线和电路板信号线，所述驱动芯片信号线的一端与所述源驱动电路连接，所述驱动芯片信号线的另一端通过一个第二过孔与所述第二信号连接线的一端连接；所述电路板信号线的一端与所述柔性电路板连接，所述电路板信号线的另一端通过一个第二过孔与所述第二信号连接线的另一端连接；
形成覆盖所述驱动芯片信号线和电路板信号线的复合绝缘层；
在所述复合绝缘层上形成多条选择连接线。
在示例性实施方式中，在所述绑定区域形成源驱动电路、柔性电路板、 第一选择器电路、第二选择器电路和多条选择连接线，包括：
在基底上形成第一绝缘层和第二绝缘层；
在所述第二绝缘层上形成第一信号连接线；
形成覆盖所述第一信号连接线的第三绝缘层；
在所述第三绝缘层上形成第二信号连接线；
形成覆盖所述第二信号连接线的第四绝缘层，其上开设有暴露出所述第一信号连接线的两个第一过孔，以及暴露出所述第二信号连接线的两个第二过孔；
在所述第四绝缘层上形成驱动芯片信号线和电路板信号线，所述驱动芯片信号线的一端与所述源驱动电路连接，所述驱动芯片信号线的另一端通过一个第一过孔和一个第二过孔分别与所述第一信号连接线的一端和第二信号连接线的一端连接；所述电路板信号线的一端与所述柔性电路板连接，所述电路板信号线的另一端通过一个第一过孔和一个第二过孔分别与所述第一信号连接线的另一端和第二信号连接线的另一端连接；
形成覆盖所述驱动芯片信号线和电路板信号线的复合绝缘层；
在所述复合绝缘层上形成多条选择连接线。
在示例性实施方式中，在所述复合绝缘层上形成多条选择连接线，包括：在所述复合绝缘层上形成多条选择连接线和至少两条屏蔽线，所述至少两条屏蔽线分别设置在所述多条选择连接线的两侧，所述屏蔽线在基底上正投影的宽度大于所述选择连接线在基底上正投影的宽度。
在示例性实施方式中，在所述第四绝缘层上形成驱动芯片信号线和电路板信号线，包括：在所述第四绝缘层上形成屏蔽板、驱动芯片信号线和电路板信号线，所述屏蔽板设置在所述驱动芯片信号线和电路板信号线之间，所述多条选择连接线在基底上正投影的边界位于所述屏蔽板在基底上正投影的边界范围内。
在示例性实施方式中，所述制备方法还包括：在所述显示区域形成第一绝缘层、有源层、第二绝缘层、第一栅金属层、第三绝缘层、第二栅金属层、 第四绝缘层、第一源漏金属层、复合绝缘层和第二源漏金属层。
在示例性实施方式中，所述第一信号连接线与所述第一栅金属层同层设置，且通过同一次图案化工艺形成。
在示例性实施方式中，所述第二信号连接线与所述第二栅金属层同层设置，且通过同一次图案化工艺形成。
在示例性实施方式中，所述驱动芯片信号线和电路板信号线与所述第一源漏金属层同层设置，且通过同一次图案化工艺形成。
在示例性实施方式中，所述多条选择连接线与所述第二源漏金属层同层设置，且通过同一次图案化工艺形成。
本公开还提供了一种显示装置，包括前述实施例的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本申请中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本申请的权利要求的范围当中。

Claims (15)

  1. 一种显示基板，包括显示区域和位于所述显示区域一侧的绑定区域，所述绑定区域包括源驱动电路、柔性电路板、第一选择器电路、第二选择器电路和多条选择连接线，对于所述多条选择连接线中的至少一条选择连接线，所述选择连接线的一端连接所述第一选择器电路的输入端口，另一端连接所述第二选择器电路的输入端口；所述柔性电路板设置在所述源驱动电路远离所述显示区域的一侧，所述多条选择连接线设置在所述源驱动电路与所述柔性电路板之间。
  2. 根据权利要求1所述的显示基板，其中，沿着平行于显示区域边缘的方向，所述第一选择器电路和第二选择器电路分别设置在所述源驱动电路的两侧；所述显示区域边缘是所述显示区域邻近所述绑定区域一侧的边缘。
  3. 根据权利要求2所述的显示基板，其中，所述柔性电路板上设置有多个选择器引脚，沿着平行于显示区域边缘的方向，所述多个选择器引脚设置在所述柔性电路板的两侧；对于所述多个选择器引脚中的至少一个选择器引脚，所述选择器引脚通过选择引线与所述选择连接线连接，或者通过选择引线与所述第一选择器电路或第二选择器电路的输入端口连接。
  4. 根据权利要求1所述的显示基板，其中，在垂直于显示基板的平面内，所述绑定区域包括：设置在基底上的绑定结构层；设置在所述绑定结构层上的复合绝缘层；设置在所述复合绝缘层上的多条选择连接线。
  5. 根据权利要求4所述的显示基板，其中，所述绑定结构层包括：
    设置在基底上的第一绝缘层和第二绝缘层；
    设置在所述第二绝缘层上的第一信号连接线；
    覆盖所述第一信号连接线的第三绝缘层和第四绝缘层，其上开设有暴露出所述第一信号连接线的两个第一过孔；
    设置在所述第四绝缘层上的驱动芯片信号线和电路板信号线，所述驱动芯片信号线的一端与所述源驱动电路连接，所述驱动芯片信号线的另一端通过所述第一过孔与所述第一信号连接线的第一端连接；所述电路板信号线的 一端与所述柔性电路板连接，所述电路板信号线的另一端通过所述第一过孔与所述第一信号连接线的第二端连接。
  6. 根据权利要求4所述的显示基板，其中，所述绑定结构层包括：
    设置在基底上的第一绝缘层、第二绝缘层和第三绝缘层；
    设置在所述第三绝缘层上的第二信号连接线；
    覆盖所述第二信号连接线的第四绝缘层，其上开设有暴露出所述第二信号连接线的两个第二过孔；
    设置在所述第四绝缘层上的驱动芯片信号线和电路板信号线，所述驱动芯片信号线的一端与所述源驱动电路连接，所述驱动芯片信号线的另一端通过所述第二过孔与所述第二信号连接线的第一端连接；所述电路板信号线的一端与所述柔性电路板连接，所述电路板信号线的另一端通过所述第二过孔与第二信号连接线的第二端连接。
  7. 根据权利要求4所述的显示基板，其中，所述绑定结构层包括：
    设置在基底上的第一绝缘层和第二绝缘层；
    设置在所述第二绝缘层上的第一信号连接线；
    覆盖所述第一信号连接线的第三绝缘层；
    设置在所述第三绝缘层上的第二信号连接线；
    覆盖所述第二信号连接线的第四绝缘层，其上开设有暴露出所述第一信号连接线的两个第一过孔，以及暴露出所述第二信号连接线的两个第二过孔；
    设置在所述第四绝缘层上的驱动芯片信号线和电路板信号线，所述驱动芯片信号线的一端与所述源驱动电路连接，所述驱动芯片信号线的另一端通过所述第一过孔和第二过孔分别与所述第一信号连接线和第二信号连接线的第一端连接；所述电路板信号线的一端与所述柔性电路板连接，所述电路板信号线的另一端通过所述第一过孔和第二过孔分别与所述第一信号连接线和第二信号连接线的第二端连接。
  8. 根据权利要求4至7任一项所述的显示基板，其中，所述复合绝缘层 上还设置有至少两条屏蔽线，所述至少两条屏蔽线分别设置在所述多条选择连接线邻近所述显示区域的一侧和远离所述显示区域的一侧，沿着远离所述显示区域的方向，所述屏蔽线在基底上正投影的宽度大于所述选择连接线在基底上正投影的宽度。
  9. 根据权利要求5至7任一项所述的显示基板，其中，所述第四绝缘层上还设置有屏蔽板，所述屏蔽板设置在所述驱动芯片信号线和电路板信号线之间，沿着远离所述显示区域的方向，所述多条选择连接线在基底上正投影的边界位于所述屏蔽板在基底上正投影的边界范围内。
  10. 根据权利要求5至7任一项所述的显示基板，其中，在垂直于显示基板的平面内，所述显示区域包括在基底上叠设的第一绝缘层、有源层、第二绝缘层、第一栅金属层、第三绝缘层、第二栅金属层、第四绝缘层、第一源漏金属层、复合绝缘层和第二源漏金属层；所述第一信号连接线与所述第一栅金属层同层设置；所述第二信号连接线与所述第二栅金属层同层设置；所述驱动芯片信号线和电路板信号线与所述第一源漏金属层同层设置；所述多条选择连接线与所述第二源漏金属层同层设置。
  11. 根据权利要求5至7任一项所述的显示基板，其中，所述驱动芯片信号线和电路板信号线是第一电源线VDD，或者，所述驱动芯片信号线和电路板信号线是第二电源线VSS。
  12. 根据权利要求1所述的显示基板，其中，在垂直于显示基板的平面内，所述绑定区域包括：
    设置在基底上的第一绝缘层和第二绝缘层；
    设置在所述第二绝缘层上的第一选择连接线和至少两条第一屏蔽线，所述至少两条第一屏蔽线分别设置在所述多条第一选择连接线的两侧；
    覆盖所述第一选择连接线和至少两条第一屏蔽线的第三绝缘层；
    设置在所述第三绝缘层上的第二选择连接线和至少两条第二屏蔽线，所述至少两条第二屏蔽线分别设置在所述多条第二选择连接线的两侧；
    覆盖所述第二选择连接线和至少两条第二屏蔽线的第四绝缘层；
    设置在所述第四绝缘层上的屏蔽板，所述多条第一选择连接线或多条第二选择连接线在基底上正投影的边界位于所述屏蔽板在基底上正投影的边界范围内；
    设置在所述屏蔽板上的复合绝缘层；
    设置在所述复合绝缘层上的多条第三信号连接线。
  13. 根据权利要求12所述的显示基板，其中，在垂直于显示基板的平面内，所述显示区域包括在基底上叠设的第一绝缘层、有源层、第二绝缘层、第一栅金属层、第三绝缘层、第二栅金属层、第四绝缘层、第一源漏金属层、复合绝缘层和第二源漏金属层；所述第一选择连接线与所述第一栅金属层同层设置；所述第二选择连接线与所述第二栅金属层同层设置；所述屏蔽板与所述第一源漏金属层同层设置；所述第三信号连接线与所述第二源漏金属层同层设置。
  14. 一种显示装置，包括如权利要求1至13任一项所述的显示基板。
  15. 一种显示基板的制备方法，显示基板包括显示区域和位于显示区域一侧的绑定区域；所述制备方法包括：
    在所述绑定区域形成源驱动电路、柔性电路板、第一选择器电路、第二选择器电路和多条选择连接线；对于所述多条选择连接线中的至少一条选择连接线，所述选择连接线的一端连接所述第一选择器电路的输入端口，另一端连接所述第二选择器电路的输入端口；所述柔性电路板设置在所述源驱动电路远离所述显示区域的一侧，所述多条选择连接线设置在所述源驱动电路与所述柔性电路板之间。
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