WO2021213050A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2021213050A1
WO2021213050A1 PCT/CN2021/080032 CN2021080032W WO2021213050A1 WO 2021213050 A1 WO2021213050 A1 WO 2021213050A1 CN 2021080032 W CN2021080032 W CN 2021080032W WO 2021213050 A1 WO2021213050 A1 WO 2021213050A1
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Prior art keywords
layer
metal layer
unit test
signal line
test electrode
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PCT/CN2021/080032
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English (en)
French (fr)
Inventor
王世龙
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/625,087 priority Critical patent/US11914811B2/en
Publication of WO2021213050A1 publication Critical patent/WO2021213050A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/80—Manufacture or treatment specially adapted for the organic devices covered by this subclass using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04102—Flexible digitiser, i.e. constructional details for allowing the whole digitising part of a device to be flexed or rolled like a sheet of paper
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2354/00—Aspects of interface with display user
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/851—Division of substrate

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate, a preparation method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • OLED can be divided into passive matrix driving organic light-emitting diodes (Passive Matrix Driving OLED, PMOLED) and active matrix driving organic light-emitting diodes (Active Matrix Driving OLED, AMOLED) according to the driving mode.
  • Passive Matrix Driving OLED PMOLED
  • Active Matrix Driving OLED AMOLED
  • LCD liquid crystal displays
  • the present disclosure provides a display substrate, which includes a flexible base and a display area on one side of the flexible base, a binding needle area, a first unit test electrode and a second unit test electrode, the binding needle area is located in the display area
  • the first unit test electrode is located on the side of the binding pin area away from the display area
  • the second unit test electrode is located on the side of the first unit test electrode away from the binding pin area
  • the display substrate includes a first metal layer, a second Two metal layers and an insulating layer located between the first metal layer and the second metal layer, the first unit test electrode is located on the first metal layer, and the second unit test electrode is located on the second metal layer.
  • the number of the first unit test electrode is one or more; the number of the second unit test electrode is one or more.
  • the first metal layer further includes a plurality of first signal lines, one end of the first signal line is connected to the first unit test electrode, and the other end is connected to the binding pin area. Connection; the second metal layer also includes a plurality of second signal lines, one end of the second signal line is connected to the second unit test electrode, the other end is connected to the binding pin area, the first The orthographic projection of the signal line on the flexible substrate and the orthographic projection of the second signal line on the flexible substrate do not overlap.
  • the first signal line and the second signal line are parallel to each other and arranged at intervals, the width of the first signal line and the second signal line is 45 to 75 microns, and the first signal line The interval between the signal line and the second signal line is 45 to 75 microns.
  • the display area includes a touch signal line and a data line; the first unit test electrode is connected to the touch signal line through the first signal line; the second unit test The electrode is connected to the data line through the second signal line; or, the first unit test electrode is connected to the data line through the first signal line; the second unit test electrode is connected to the data line through the second signal line; The signal line is connected to the touch signal line.
  • the width of the first unit test electrode is 2500 ⁇ m to 7500 ⁇ m and the height is 400 ⁇ m to 1200 ⁇ m
  • the width of the second unit test electrode is 2500 ⁇ m to 7500 ⁇ m
  • the height is 400 micrometers to 1200 micrometers
  • the distance between the first unit test electrode and the second unit test electrode is 400 micrometers to 1200 micrometers.
  • the display substrate further includes an array test electrode, the array test electrode is located on a side of the second unit test electrode away from the first unit test electrode; and the array test electrode is located on the side of the second unit test electrode. On the first metal layer or on the second metal layer.
  • the display substrate further includes a third signal line, one end of the third signal line is connected to the array test electrode, and the other end is connected to the binding pin area; the third signal line The signal line and the array test electrode are arranged on the same layer.
  • the number of the first unit test electrodes is two
  • the number of the second unit test electrodes is two
  • the third signal line is located on the two first unit test electrodes.
  • the third signal line is located between the two second unit test electrodes.
  • the display substrate further includes a fourth signal line, one end of the fourth signal line is connected to the array test electrode, and the other end is connected to the first unit test electrode and the second unit test electrode. At least one of the electrodes is connected.
  • the present disclosure also provides a display device including the display substrate as described above.
  • the present disclosure also provides a preparation method of a display substrate, the preparation method comprising: forming a flexible base on a rigid carrier; forming a driving structure layer on the flexible base, the driving structure layer including a first metal layer and a second metal layer And an insulating layer located between the first metal layer and the second metal layer, the first metal layer includes one or more first unit test electrodes; the second metal layer includes one or more second unit test electrodes; the flexible substrate Separate from rigid carrier.
  • the display substrate includes a display area
  • the drive structure layer of the display area includes a first insulating layer on the flexible substrate, an active layer on the first insulating layer, The second insulating layer covering the active layer, the first gate metal layer located on the second insulating layer, the third insulating layer covering the first gate metal layer, the insulating layer located on the third insulating layer A second gate metal layer, a fourth insulating layer covering the second gate metal layer, a first source-drain metal layer located on the fourth insulating layer, and a fifth insulating layer covering the first source-drain metal layer
  • the first metal layer and the first gate metal layer are provided in the same layer, and the second metal layer and the second gate metal layer are provided in the same layer; or, the first metal layer and the second The gate metal layer is arranged in the same layer, and the second metal layer is arranged in the same layer as the first source-drain metal layer.
  • FIG. 1 is a schematic diagram of a structure of a display substrate of the present disclosure
  • FIG. 2 is a schematic diagram of the cross-sectional structure of the display substrate shown in FIG. 1 in the AA, BB and CC directions;
  • FIG. 3 is a schematic diagram of a structure of the display motherboard of the present disclosure.
  • FIG. 4 is a schematic diagram of the structure after forming a flexible substrate in the present disclosure
  • FIG. 5 is a schematic diagram of the structure of the present disclosure after forming a pattern of a driving structure layer
  • FIG. 6 is a schematic diagram of the structure after forming the first opening and the second opening in the present disclosure
  • FIG. 7 is a schematic flow diagram of a method for preparing a display substrate of the present disclosure.
  • 100 display area
  • 110 first unit test area
  • 120 second unit test area
  • 10B the first barrier layer
  • 10C amorphous silicon layer
  • 10D the second flexible layer
  • 10E the second barrier layer
  • 11 the first insulating layer
  • 12A the first active layer
  • connection should be interpreted broadly. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between two components.
  • connection should be interpreted broadly. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • it may be the drain electrode of the first electrode and the source electrode of the second electrode, or it may be the source electrode of the first electrode and the drain electrode of the second electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged.
  • connection includes the case where constituent elements are connected together by elements having a certain electrical function.
  • An element having a certain electrical function is not particularly limited as long as it can transmit and receive electrical signals between connected constituent elements.
  • elements having a certain electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore, it also includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore, also includes a state where an angle of 85° or more and 95° or less is included.
  • film and “layer” can be interchanged.
  • the “conductive layer” can be replaced by the “conductive film.”
  • the “insulating film” can sometimes be replaced with an “insulating layer.”
  • the AMOLED display with touch function is produced based on the demand for enrichment of functions, including a touch structure layer and a display structure layer.
  • the touch structure layer includes a touch screen signal line
  • the touch screen signal line includes a plurality of driving signal lines Tx and a plurality of sensing signal lines Rx.
  • the touch screen signal line is usually formed in the flexible multi-layer surface touch screen (Flexible Mulit-layer On Cell Touch, FMLOC) process stage.
  • FMLOC Flexible Multi-layer surface touch screen
  • the AMOLED display with touch function adds pins for detecting touch screen signal lines in the unit test electrodes of the test area, the length of the unit test electrodes is more than doubled, which in turn leads to irregular cutting in the unit display panel stage. Cut the unit test electrode, therefore, the special-shaped cutting of the AMOLED display with touch function must be transferred to the module (Module, MDL) stage, which requires the modification of the module equipment, resulting in a reduction in the production capacity of the module stage.
  • At least one embodiment of the present disclosure provides a display substrate.
  • the display substrate includes a base and a display area on one side of the base, a binding pin area, a first unit test electrode and a second unit test electrode, and the binding pin area is located in the display area.
  • the first unit test electrode is located on the side of the binding pin area away from the display area
  • the second unit test electrode is located on the side of the first unit test electrode away from the binding pin area
  • the display substrate includes a first metal layer , The second metal layer and the insulating layer located between the first metal layer and the second metal layer, the first unit test electrode is located on the first metal layer, and the second unit test electrode is located on the second metal layer.
  • Some embodiments of the present disclosure also provide a display device corresponding to the above-mentioned display substrate and a preparation method of the display substrate.
  • the length of the unit test electrode is shortened, so that in the unit display panel stage, touch control
  • the special-shaped cutting of the functional AMOLED display will not cut the unit test electrodes, that is, the special-shaped cutting can still be performed in the unit display panel stage, thereby releasing the production capacity of the module stage and improving the overall production capacity.
  • an embodiment of the present disclosure provides a display substrate.
  • the display substrate includes a display area 100, a binding pin area 140, a first unit test area 110, and a second unit test area.
  • the unit test area 120, the binding pin area 140 is located on one side of the display area 100
  • the first unit test area 110 is located on the side of the binding pin area 140 away from the display area 100
  • the second unit test area 120 is located in the first unit test area 110 is away from the side of the binding needle area 140.
  • the first unit test area 110 includes one or more first unit test electrodes 111
  • the second unit test area 120 includes one or more second unit test electrodes 121.
  • the display substrate in a plane direction perpendicular to the display substrate, includes a first metal layer, Two metal layers and an insulating layer located between the first metal layer and the second metal layer, the first unit test electrode 111 is located on the first metal layer, and the second unit test electrode 121 is located on the second metal layer.
  • the first metal layer further includes a plurality of first signal lines 112 (not shown in FIG. 2). One end of the first signal line 112 is connected to the first unit test electrode 111, and the other end is connected to the first unit test electrode 111.
  • the binding pin area 140 is connected;
  • the second metal layer also includes a plurality of second signal lines 122 (not shown in FIG. 2), one end of the second signal line 122 is connected to the second unit test electrode 121, and the other end is connected to the binding
  • the needle area 140 is connected, and the orthographic projection of the first signal line 112 on the flexible substrate 10 and the orthographic projection of the second signal line 122 on the flexible substrate 10 do not overlap.
  • the first signal line 112 and the second signal line 122 are arranged parallel to each other and spaced apart, the width of the first signal line 112 and the second signal line 122 is 45 to 75 microns, and the first signal line 112 The distance between the second signal line 122 and the second signal line 122 is 45 to 75 microns.
  • the width of the first signal line 112 may be 60 ⁇ m
  • the width of the second signal line 122 may be 60 ⁇ m
  • the interval between the first signal line 112 and the second signal line 122 may be 60 ⁇ m.
  • the display area includes touch signal lines and data lines (not shown in the figure); the first unit test electrode 111 is connected to the touch signal line through the first signal line 112; the second unit test The electrode 121 is connected to the data line through the second signal line 122; or, the first unit test electrode 111 is connected to the data line through the first signal line 112; the second unit test electrode 121 is connected to the touch signal line through the second signal line 122 . That is, any one of the first unit test electrode 111 and the second unit test electrode 121 may be configured to detect the touch signal line, and the other may be configured to detect the pixel electrode.
  • the width of the first unit test electrode 111 is 2500 ⁇ m to 7500 ⁇ m and the height is 400 ⁇ m to 1200 ⁇ m
  • the width of the second unit test electrode 121 is 2500 ⁇ m to 7500 ⁇ m and the height is 400 ⁇ m.
  • the distance between the first unit test electrode 111 and the second unit test electrode 121 is 400 ⁇ m to 1200 ⁇ m.
  • the width of the first unit test electrode 111 or the second unit test electrode 121 refers to the length of the first unit test electrode 111 or the second unit test electrode 121 in the x direction.
  • the height of the unit test electrode 111 or the second unit test electrode 121 refers to the length of the first unit test electrode 111 or the second unit test electrode 121 in the y direction.
  • the width of the first unit test electrode 111 may be 5000 microns and the height may be 750 microns
  • the width of the second unit test electrode 121 may be 5000 microns
  • the height may be 750 microns
  • the first unit test electrode 111 and the first unit test electrode 111 The distance between the two unit test electrodes 121 may be 750 microns.
  • the display area 100 includes a first insulating layer 11 on the flexible substrate 10, an active layer on the first insulating layer 11, a second insulating layer 13 covering the active layer, and a second insulating layer 13 on the first insulating layer.
  • the first source-drain metal layer on the fourth insulating layer 17, and the fifth insulating layer 19 covering the first source-drain metal layer.
  • the first metal layer may be provided in the same layer as the first gate metal layer, and the second metal layer may be provided in the same layer as the second gate metal layer; alternatively, the first metal layer may be provided in the same layer as the second gate metal layer, and the second metal layer The layer can be provided in the same layer as the first source-drain metal layer.
  • the display substrate may further include an array test area 130, and the array test area 130 may be located on a side of the second unit test area 120 away from the display area 100.
  • the array test area 130 includes an array test electrode 131, and the array test electrode 131 may be located on the first metal layer or on the second metal layer.
  • the number of the first unit test electrodes 111 is two
  • the number of the second unit test electrodes 121 is two
  • the third signal line 132 is located between the two first unit test electrodes 111
  • the third signal line 132 is located between the two second unit test electrodes 121.
  • the array test area 130 may further include a fourth signal line 133.
  • One end of the fourth signal line 133 is connected to the array test electrode 131, and the other end is connected to the first unit test electrode 111 and the second unit test electrode 131. At least one of the electrodes 121 is connected.
  • the "patterning process” referred to in the present disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, developing, etching, and stripping the photoresist.
  • the deposition can be any one or more selected from sputtering, evaporation and chemical vapor deposition
  • the coating can be any one or more selected from spraying and spin coating
  • the etching can be selected from dry etching. Any one or more of wet engraving.
  • Thin film refers to a layer of film made by depositing or coating a certain material on a substrate.
  • the "film” can also be referred to as a "layer".
  • the patterning process is required for the "thin film” during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are formed at the same time through the same patterning process.
  • the orthographic projection of A includes the orthographic projection of B means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.
  • the display motherboard includes a substrate area and a cutting area 200 located at the periphery of the substrate area.
  • the substrate area includes a display area 100, a binding pin area 140, a first unit test area 110 and a second unit test area 120.
  • the flexible substrate 10 includes a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on the rigid carrier 1.
  • the materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film, etc.
  • the first and second inorganic materials The material of the layer can be silicon nitride (SiNx) or silicon oxide (SiOx) to improve the water and oxygen resistance of the substrate.
  • the first and second inorganic material layers are also called barrier layers.
  • the material can be amorphous silicon (a-si).
  • the preparation process may include: first coating a layer of polyimide on the rigid carrier 1 and curing it into After the film is formed, a first flexible (PI1) layer 10A is formed; then a barrier film is deposited on the first flexible layer 10A to form a first barrier (Barrier1) layer 10B covering the first flexible layer 10A; and then on the first barrier layer 10B A layer of amorphous silicon film is deposited on it to form an amorphous silicon (a-si) layer 10C covering the first barrier layer 10B; then a layer of polyimide is coated on the amorphous silicon layer 10C, and the film is cured A second flexible (PI2) layer 10D is formed; then a barrier film is deposited on the second flexible layer 10D to form a second barrier (Barrier2) layer 10E covering the second flexible layer 10D, and the preparation of the flexible substrate 10 is completed, as shown in the figure 4 shown. After this
  • a first insulating film and an active layer film are sequentially deposited on the flexible substrate 10, and the active layer film is patterned through a patterning process to form a first insulating layer 11 covering the entire flexible substrate 10, and a layer located on the first insulating layer 11
  • the active layer pattern is formed in the display area 100 and includes at least the first active layer 12A.
  • the first unit test area 110 and the second unit test area 120 include the first insulating layer 11 on the flexible substrate 10.
  • the first gate metal layer pattern is formed in the display area 100 and includes at least a first gate electrode 14A, a first capacitor electrode 14B and a plurality of gate lines (not shown).
  • the first unit test area 110 and the second unit test area 120 include a first insulating layer 11 and a second insulating layer 13 stacked on the flexible substrate 10.
  • a third insulating film and a second metal film are sequentially deposited, and the second metal film is patterned by a patterning process to form a third insulating layer 15 covering the first gate metal layer, and a second insulating layer 15 on the third insulating layer 15
  • the gate metal layer and the first metal layer pattern is formed in the display area 100 and includes at least the second capacitor electrode 16A.
  • the position of the second capacitor electrode 16A corresponds to the position of the first capacitor electrode 14B.
  • the first metal layer is formed in the first unit test area 110 and includes at least the first signal line 112 and the first unit test electrode 111 pattern.
  • the first signal line 112 is used to connect the first unit test electrode 111 and the binding pin area 140.
  • the second unit test area 120 includes a first insulating layer 11, a second insulating layer 13 and a third insulating layer 15 stacked on the flexible substrate 10.
  • a fourth insulating film is deposited, and the fourth insulating film is patterned through a patterning process to form a pattern of the fourth insulating layer 17 covering the second gate metal layer.
  • the fourth insulating layer 17 is provided with a plurality of first via holes.
  • the first via holes are formed in the display area 100, and their positions correspond to the positions of the two ends of the first active layer 12A.
  • the fourth insulating layer 17, the third insulating layer 15, and the second The insulating layer 13 is etched away, respectively exposing the surface of the first active layer 12A.
  • the first unit test area 110 includes a first insulating layer 11, a second insulating layer 13, a third insulating layer 15, a first metal layer, and a fourth insulating layer 17 stacked on the flexible substrate 10.
  • the second unit test area 120 includes a first insulating layer 11, a second insulating layer 13, a third insulating layer 15 and a fourth insulating layer 17 stacked on the flexible substrate 10.
  • the source-drain metal layer is formed in the display area 100, at least It includes a first source electrode 18A, a first drain electrode 18B, and a plurality of data line (not shown) patterns.
  • the first source electrode 18A and the first drain electrode 18B are respectively connected to the first active layer 12A through a first via hole.
  • the source/drain metal layer may further include any one or more of a power supply line (VDD), a compensation line, and an auxiliary cathode.
  • the width of the first unit test electrode 111 is 2500 ⁇ m to 7500 ⁇ m and the height is 400 ⁇ m to 1200 ⁇ m
  • the width of the second unit test electrode 121 is 2500 ⁇ m to 7500 ⁇ m and the height is 400 ⁇ m.
  • the distance between the first unit test electrode 111 and the second unit test electrode 121 is 400 ⁇ m to 1200 ⁇ m.
  • the width of the first unit test electrode 111 or the second unit test electrode 121 refers to the length of the first unit test electrode 111 or the second unit test electrode 121 in the x direction.
  • the height of the unit test electrode 111 or the second unit test electrode 121 refers to the length of the first unit test electrode 111 or the second unit test electrode 121 in the y direction.
  • a fifth insulating film is deposited to form a pattern of the fifth insulating layer 19 covering the source and drain metal layers.
  • the driving structure layer of the first unit test area 110 includes a first insulating layer 11, a second insulating layer 13, and a third insulating layer 15 sequentially stacked on the flexible substrate 10, and a first metal layer on the third insulating layer 15 ,
  • the fourth insulating layer 17 covering the first metal layer, the second metal layer located on the fourth insulating layer 17, and the fifth insulating layer 19 covering the second metal layer.
  • the driving structure layer of the second unit test area 120 includes a first insulating layer 11, a second insulating layer 13, a third insulating layer 15, and a fourth insulating layer 17 which are sequentially stacked on the flexible substrate 10, and are located on the fourth insulating layer 17.
  • the upper second metal layer covers the fifth insulating layer 19 of the second metal layer.
  • a plurality of first openings 20 and second openings 21 are opened on the fifth insulating layer 19, and the plurality of first openings 20 are formed in the first unit test area 110, and their positions are respectively the same as those of the first unit test electrode.
  • the position of 111 corresponds to the fourth insulating layer 16 in the plurality of first openings 20 is etched away, exposing the surface of the first unit test electrode 111 respectively.
  • a plurality of second openings 21 are formed in the second unit test area 120, and their positions respectively correspond to the positions of the second unit test electrodes 121, respectively exposing the surface of the second unit test electrodes 121, as shown in FIG. 6.
  • a first flat layer, a second source/drain metal layer, a second flat layer, a pixel definition layer, an organic light-emitting layer, a cathode, and an encapsulation layer are sequentially formed in the display area 100.
  • the display mother board is peeled off from the rigid carrier 1 by a peeling process, and then a layer of back film is attached to the back of the display mother board (the side surface of the flexible substrate 10 away from the film layer) using a roller bonding method to complete the display mother Preparation of the plate.
  • the cutting device cuts along the cutting lane 201 to separate the display mother board into the disclosed display substrate. After the cutting is completed, the cutting area 200 is cut away, as shown in FIG. 1.
  • the display substrate area may further include a protective film (Temporary Protective Film, TPF), the protective film is attached to the packaging layer, the protective film is used to protect the film structure of the display substrate, and the back film is attached The operation is performed after attaching the protective film. After the cutting is completed, the protective film is first removed, and then a touch layer and a cover plate are sequentially arranged on the packaging layer to form a touch display panel.
  • TPF Temporal Protective Film
  • the first insulating film, the second insulating film, the third insulating film, the fourth insulating film, and the fifth insulating film may be silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON) Any one or more of these may be a single layer, a multi-layer or a composite layer.
  • the first insulating layer is called a buffer layer, which is used to improve the water and oxygen resistance of the substrate
  • the second and third insulating layers are called gate insulating (GI) layers
  • the fourth insulating layer is called a layer
  • the fifth insulation layer is called the passivation (PVX) layer.
  • Organic materials may be used for the first flat layer and the second flat layer.
  • the first metal film, the second metal film, the third metal film, and the fourth metal film can be made of metal materials, such as any one of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo) or More kinds, or alloy materials of the above-mentioned metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can have a single-layer structure or a multilayer composite structure, such as Mo/Cu/Mo.
  • metal materials such as any one of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo) or More kinds, or alloy materials of the above-mentioned metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb
  • the cathode can be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or made of any one or more of the above metals Alloy.
  • the active layer film can use amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si) , Hexathiophene, polythiophene and other materials, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, and organic technology.
  • the transparent conductive film can be indium tin oxide ITO or indium zinc oxide IZO, and the pixel definition layer can be polyimide, acrylic or polyethylene terephthalate.
  • the embodiment of the present disclosure shortens the length of the unit test electrode by locating the first unit test electrode 111 and the second unit test electrode 121 on two metal layers, respectively.
  • the special-shaped cutting of the AMOLED display with touch function will not cut the unit test electrode, that is, the special-shaped cutting can still be performed in the unit display panel stage, thereby releasing the module stage production capacity and improving the overall production capacity.
  • the structure shown in the present disclosure and the preparation process thereof are only an exemplary description.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • the first metal layer and the second gate metal layer are provided in the same layer, and the second metal layer is provided in the same layer as the first source/drain metal layer.
  • the first metal layer may be provided in the same layer as the first gate metal layer, and the second metal layer may be provided in the same layer as the second gate metal layer; or, the first metal layer may be provided in the same layer as the first source and drain metal layer.
  • Layer arrangement, the second metal layer can be arranged in the same layer as the second source and drain metal layer.
  • the present disclosure does not make specific limitations here.
  • the present disclosure also provides a method for preparing a display substrate. As shown in FIG. 7, the method includes steps S1 to S3.
  • step S1 includes: forming a flexible substrate on a rigid carrier.
  • Step S2 includes: forming a driving structure layer on the flexible substrate, the driving structure layer including a first metal layer, a second metal layer, and an insulating layer located between the first metal layer and the second metal layer, the first metal layer including one or A plurality of first unit test electrodes; the second metal layer includes one or more second unit test electrodes.
  • the first metal layer further includes a plurality of first signal lines, one end of the first signal line is connected to the first unit test electrode, and the other end is connected to the binding pin area;
  • the second metal layer also It includes multiple second signal lines. One end of the second signal line is connected to the second unit test electrode, and the other end is connected to the binding needle area.
  • the first signal line 112 and the second signal line 122 are arranged parallel to each other and spaced apart, the width of the first signal line 112 and the second signal line 122 is 45 to 75 microns, and the first signal line 112 The distance between the second signal line 122 and the second signal line 122 is 45 to 75 microns.
  • the width of the first signal line 112 may be 60 ⁇ m
  • the width of the second signal line 122 may be 60 ⁇ m
  • the interval between the first signal line 112 and the second signal line 122 may be 60 ⁇ m.
  • the width of the first unit test electrode 111 is 2500 ⁇ m to 7500 ⁇ m and the height is 400 ⁇ m to 1200 ⁇ m
  • the width of the second unit test electrode 121 is 2500 ⁇ m to 7500 ⁇ m and the height is 400 ⁇ m.
  • the distance between the first unit test electrode 111 and the second unit test electrode 121 is 400 ⁇ m to 1200 ⁇ m.
  • the width of the first unit test electrode 111 or the second unit test electrode 121 refers to the length of the first unit test electrode 111 or the second unit test electrode 121 in the x direction.
  • the height of the two unit test electrodes 121 refers to the length of the first unit test electrode 111 or the second unit test electrode 121 in the y direction.
  • the width of the first unit test electrode 111 may be 5000 microns and the height may be 750 microns
  • the width of the second unit test electrode 121 may be 5000 microns
  • the height may be 750 microns
  • the first unit test electrode 111 and the first unit test electrode 111 The distance between the two unit test electrodes 121 may be 750 microns.
  • the display substrate includes a display area, the display area includes a first insulating layer on the flexible substrate, an active layer on the first insulating layer, a second insulating layer covering the active layer, The first gate metal layer on the second insulating layer, the third insulating layer covering the first gate metal layer, the second gate metal layer on the third insulating layer, the fourth insulating layer covering the second gate metal layer, The first source-drain metal layer on the fourth insulating layer and the fifth insulating layer covering the first source-drain metal layer.
  • the first metal layer may be provided in the same layer as the first gate metal layer, and the second metal layer may be provided in the same layer as the second gate metal layer; alternatively, the first metal layer may be provided in the same layer as the second gate metal layer, and the second metal layer The layer can be provided in the same layer as the first source-drain metal layer.
  • Step S3 includes: separating the flexible substrate from the rigid carrier board.
  • the present disclosure also provides a display device including the display substrate of the foregoing embodiment.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and so on.

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Abstract

一种显示基板及其制备方法、显示装置，其中，该显示基板包括基底以及位于基底一侧的显示区、绑定针区、第一单元测试电极和第二单元测试电极，绑定针区位于显示区的一侧，第一单元测试电极位于绑定针区远离显示区的一侧，第二单元测试电极位于第一单元测试电极远离绑定针区的一侧，显示基板包括第一金属层、第二金属层以及位于第一金属层和第二金属层之间的绝缘层，第一单元测试电极位于第一金属层上，第二单元测试电极位于第二金属层上。

Description

显示基板及其制备方法、显示装置 技术领域
本公开涉及但不限于显示技术领域，尤其涉及一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)为主动发光显示器件，具有自发光、广视角、高对比度、较低耗电、极高反应速度等优点。随着显示技术的不断发展，OLED技术越来越多的应用于柔性显示装置中。
OLED按驱动方式可分为无源矩阵驱动有机发光二极管(Passive Matrix Driving OLED，PMOLED)和有源矩阵驱动有机发光二极管(Active Matrix Driving OLED，AMOLED)两种，由于AMOLED显示装置具有低制造成本、高应答速度、省电、可用于便携式设备的直流驱动、工作温度范围大等等优点，而有望成为取代液晶显示器(Liquid Crystal Display，LCD)的下一代新型平面显示器。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种显示基板，所述显示基板包括柔性基底以及位于柔性基底一侧的显示区、绑定针区、第一单元测试电极和第二单元测试电极，绑定针区位于显示区的一侧，第一单元测试电极位于绑定针区远离显示区的一侧，第二单元测试电极位于第一单元测试电极远离绑定针区的一侧，显示基板包括第一金属层、第二金属层以及位于第一金属层和第二金属层之间的绝缘层，第一单元测试电极位于第一金属层上，第二单元测试电极位于第二金属层上。
在一些可能的实现方式中，第一单元测试电极的数量为一个或多个；第 二单元测试电极的数量为一个或多个。
在一些可能的实现方式中，所述第一金属层还包括多条第一信号线，所述第一信号线的一端与所述第一单元测试电极连接，另一端与所述绑定针区连接；所述第二金属层还包括多条第二信号线，所述第二信号线的一端与所述第二单元测试电极连接，另一端与所述绑定针区连接，所述第一信号线在所述柔性基底上的正投影和所述第二信号线在所述柔性基底上的正投影不重叠。
在一些可能的实现方式中，所述第一信号线和所述第二信号线相互平行且间隔设置，所述第一信号线和第二信号线的宽度为45至75微米，所述第一信号线和第二信号线之间的间隔为45至75微米。
在一些可能的实现方式中，所述显示区包括触控信号线和数据线；所述第一单元测试电极通过所述第一信号线连接至所述触控信号线；所述第二单元测试电极通过所述第二信号线连接至所述数据线；或者，所述第一单元测试电极通过所述第一信号线连接至所述数据线；所述第二单元测试电极通过所述第二信号线连接至所述触控信号线。
在一些可能的实现方式中，所述第一单元测试电极的宽度为2500微米至7500微米，高度为400微米至1200微米，所述第二单元测试电极的宽度为2500微米至7500微米，高度为400微米至1200微米，所述第一单元测试电极和所述第二单元测试电极之间的距离为400微米至1200微米。
在一些可能的实现方式中，所述显示区包括位于所述柔性基底上的第一绝缘层、位于所述第一绝缘层上的有源层、覆盖所述有源层的第二绝缘层、位于所述第二绝缘层上的第一栅金属层、覆盖所述第一栅金属层的第三绝缘层、位于所述第三绝缘层上的第二栅金属层、覆盖所述第二栅金属层的第四绝缘层、位于所述第四绝缘层上的第一源漏金属层、覆盖所述第一源漏金属层的第五绝缘层；所述第一金属层与所述第一栅金属层同层设置，所述第二金属层与所述第二栅金属层同层设置；或者，所述第一金属层与所述第二栅金属层同层设置，所述第二金属层与所述第一源漏金属层同层设置。
在一些可能的实现方式中，所述显示基板还包括阵列测试电极，所述阵列测试电极位于所述第二单元测试电极远离所述第一单元测试电极的一侧； 所述阵列测试电极位于所述第一金属层上或者所述第二金属层上。
在一些可能的实现方式中，所述显示基板还包括第三信号线，所述第三信号线的一端与所述阵列测试电极连接，另一端与所述绑定针区连接；所述第三信号线与所述阵列测试电极同层设置。
在一些可能的实现方式中，所述第一单元测试电极的数量为两个，所述第二单元测试电极的数量为两个，所述第三信号线位于两个所述第一单元测试电极之间，且所述第三信号线位于两个所述第二单元测试电极之间。
在一些可能的实现方式中，所述显示基板还包括第四信号线，所述第四信号线的一端与所述阵列测试电极连接，另一端与所述第一单元测试电极和第二单元测试电极中的至少一个连接。
本公开还提供了一种显示装置，包括如前所述的显示基板。
本公开还提供了一种显示基板的制备方法，所述制备方法包括：在刚性载板上形成柔性基底；在柔性基底上形成驱动结构层，驱动结构层包括第一金属层、第二金属层以及位于第一金属层和第二金属层之间的绝缘层，第一金属层包括一个或多个第一单元测试电极；第二金属层包括一个或多个第二单元测试电极；将柔性基底与刚性载板分离。
在一些可能的实现方式中，所述显示基板包括显示区，所述显示区的驱动结构层包括位于所述柔性基底上的第一绝缘层、位于所述第一绝缘层上的有源层、覆盖所述有源层的第二绝缘层、位于所述第二绝缘层上的第一栅金属层、覆盖所述第一栅金属层的第三绝缘层、位于所述第三绝缘层上的第二栅金属层、覆盖所述第二栅金属层的第四绝缘层、位于所述第四绝缘层上的第一源漏金属层、覆盖所述第一源漏金属层的第五绝缘层；所述第一金属层与所述第一栅金属层同层设置，所述第二金属层与所述第二栅金属层同层设置；或者，所述第一金属层与所述第二栅金属层同层设置，所述第二金属层与所述第一源漏金属层同层设置。
在阅读并理解了附图概述和本公开的实施方式后，可以明白其他方面。
附图说明
图1为本公开显示基板的一种结构示意图；
图2为图1所示显示基板的AA向、BB向和CC向剖面结构示意图；
图3为本公开显示母板的一种结构示意图；
图4为本公开形成柔性基底后的结构示意图；
图5为本公开形成驱动结构层图案后的结构示意图；
图6为本公开形成第一开孔和第二开孔后的结构示意图；
图7为本公开显示基板的制备方法的流程示意图。
附图标记说明：
100—显示区；         110—第一单元测试区； 120—第二单元测试区；
Figure PCTCN2021080032-appb-000001
112—第一信号线；     122—第二信号线；     132—第三信号线；
130—阵列测试区；     200—切割区域；       201—切割道；
133—第四信号线；     101—第一晶体管；     102—第一存储电容；
1—刚性载板；         10—柔性基底；        10A—第一柔性层；
10B—第一阻挡层；     10C—非晶硅层；       10D—第二柔性层；
10E—第二阻挡层；     11—第一绝缘层；      12A—第一有源层；
13—第二绝缘层；      14A—第一栅电极；     14B—第一电容电极；
15—第三绝缘层；      16A—第二电容电极；   17—第四绝缘层；
18A—第一源电极；     18B—第一漏电极；     19—第五绝缘层；
20—第一开孔；        21—第二开孔；        140—绑定针区。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此， 本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的实施方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的实施方式不局限于附图所示的形状或数值。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，可以是第一极为漏电极、第二极为源电极，或者可以是第一极为源电极、第二极为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
具有触控功能的AMOLED显示器是基于功能丰富化的需求产生的，包括触控结构层和显示结构层。触控结构层包括：触控屏信号线，触控屏信号线包括：多个驱动信号线Tx和多个感应信号线Rx。触控屏信号线通常在柔性多层表面式触控屏(Flexible Mulit-layer On Cell Touch，FMLOC)工艺阶段形成。由于具有触控功能的AMOLED显示器在测试区的单元测试电极中增加了检测触控屏信号线的引脚，导致单元测试电极的长度增大一倍以上，进而导致单元显示面板阶段的异形切割会切开单元测试电极，因此，具有触控功能的AMOLED显示器的异形切割必须转移至模组(Module，MDL)阶段进行，这就需要对模组设备进行改造，造成了模组阶段产能降低。
本公开至少一实施例提供一种显示基板，该显示基板包括基底以及位于基底一侧的显示区、绑定针区、第一单元测试电极和第二单元测试电极，绑定针区位于显示区的一侧，第一单元测试电极位于绑定针区远离显示区的一侧，第二单元测试电极位于第一单元测试电极远离绑定针区的一侧，其中：显示基板包括第一金属层、第二金属层以及位于第一金属层和第二金属层之间的绝缘层，第一单元测试电极位于第一金属层上，第二单元测试电极位于第二金属层上。
本公开一些实施例还提供对应于上述显示基板的显示装置及该显示基板的制备方法。
本公开上述实施例提供的显示基板中，通过将第一单元测试电极和第二单元测试电极分别位于两个金属层上，缩短了单元测试电极的长度，使得在单元显示面板阶段，具有触控功能的AMOLED显示器的异形切割不会切开单元测试电极，即异形切割仍可在单元显示面板阶段进行，从而释放了模组阶段产能，提升了整体产能。
如图1所示，本公开实施例提供了一种显示基板，在平行于显示基板的平面方向，所述显示基板包括显示区100、绑定针区140、第一单元测试区110和第二单元测试区120，绑定针区140位于显示区100的一侧，第一单元测试区110位于绑定针区140远离显示区100的一侧，第二单元测试区120位于第一单元测试区110远离绑定针区140的一侧。第一单元测试区110包括一个或多个第一单元测试电极111，第二单元测试区120包括一个或多个第二单元测试电极121。
图2为本公开显示基板的结构示意图，为图1中的AA向、BB向和CC向剖视图，如图2所示，在垂直于显示基板的平面方向，显示基板包括第一金属层、第二金属层以及位于第一金属层和第二金属层之间的绝缘层，第一单元测试电极111位于第一金属层上，第二单元测试电极121位于第二金属层上。
在一种示例性实施例中，第一金属层还包括多条第一信号线112(图2中未示出)，第一信号线112的一端与第一单元测试电极111连接，另一端与绑定针区140连接；第二金属层还包括多条第二信号线122(图2中未示出)，第二信号线122的一端与第二单元测试电极121连接，另一端与绑定针区140连接，第一信号线112在柔性基底10上的正投影和第二信号线122在柔性基底10上的正投影不重叠。
在一种示例性实施例中，第一信号线112和第二信号线122相互平行且间隔设置，第一信号线112和第二信号线122的宽度为45至75微米，第一信号线112和第二信号线122之间的间隔为45至75微米。
示例性的，第一信号线112的宽度可以为60微米，第二信号线122的宽度可以为60微米，第一信号线112和第二信号线122之间的间隔可以为60 微米。
在一种示例性实施例中，显示区包括触控信号线和数据线(图中未示出)；第一单元测试电极111通过第一信号线112连接至触控信号线；第二单元测试电极121通过第二信号线122连接至数据线；或者，第一单元测试电极111通过第一信号线112连接至数据线；第二单元测试电极121通过第二信号线122连接至触控信号线。即，第一单元测试电极111和第二单元测试电极121中的任一个可以被配置为对触控信号线进行检测，另一个可以被配置为对像素电极进行检测。
在一种示例性实施例中，第一单元测试电极111的宽度为2500微米至7500微米，高度为400微米至1200微米，第二单元测试电极121的宽度为2500微米至7500微米，高度为400微米至1200微米，第一单元测试电极111和第二单元测试电极121之间的距离为400微米至1200微米。本实施例中，如图1所示，第一单元测试电极111或第二单元测试电极121的宽度指的是第一单元测试电极111或第二单元测试电极121在x方向的长度，第一单元测试电极111或第二单元测试电极121的高度指的是第一单元测试电极111或第二单元测试电极121在y方向的长度。
示例性的，第一单元测试电极111的宽度可以为5000微米，高度可以为750微米，第二单元测试电极121的宽度可以为5000微米，高度可以为750微米，第一单元测试电极111和第二单元测试电极121之间的距离可以为750微米。
在一种示例性实施例中，显示区100包括位于柔性基底10上的第一绝缘层11、位于第一绝缘层11上的有源层、覆盖有源层的第二绝缘层13、位于第二绝缘层13上的第一栅金属层、覆盖第一栅金属层的第三绝缘层15、位于第三绝缘层15上的第二栅金属层、覆盖第二栅金属层的第四绝缘层17、位于第四绝缘层17上的第一源漏金属层、覆盖第一源漏金属层的第五绝缘层19。
第一金属层可以与第一栅金属层同层设置，第二金属层可以与第二栅金属层同层设置；或者，第一金属层可以与第二栅金属层同层设置，第二金属 层可以与第一源漏金属层同层设置。
在一种示例性实施例中，如图1所示，显示基板还可以包括阵列测试区130，阵列测试区130可以位于第二单元测试区120远离显示区100的一侧。
阵列测试区130包括阵列测试电极131，阵列测试电极131可以位于第一金属层上或者第二金属层上。
在一种示例性实施例中，阵列测试区130还可以包括第三信号线132，第三信号线132的一端与阵列测试电极131连接，另一端与绑定针区140连接。第三信号线132与阵列测试电极131同层设置。阵列测试电极131被配置为对显示基板进行测试，以检查是否有短路、断路等问题。
在一种示例性实施例中，第一单元测试电极111的数量为两个，第二单元测试电极121的数量为两个，第三信号线132位于两个第一单元测试电极111之间，且第三信号线132位于两个第二单元测试电极121之间。
在一种示例性实施例中，阵列测试区130还可以包括第四信号线133，第四信号线133的一端与阵列测试电极131连接，另一端与第一单元测试电极111和第二单元测试电极121中的至少一个连接。通过设置第四信号线133，可以在阵列测试时关闭单元测试相关单元，或在单元测试时，关闭阵列测试相关单元。
下面通过显示基板的制备过程的示例说明本公开显示基板的结构。本公开所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶等处理。沉积可以采用选自溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用选自喷涂和旋涂中的任意一种或多种，刻蚀可以采用选自干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。当在整个制作过程当中该“薄膜”还需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。本公开中所说的“A和B同层设置”是指，A和B通过同一次构图工艺同时形成。“A的正投影包含B的正投影”是指，B的正投影落入A的正投影范围内，或者A的正投影覆盖B的正投 影。
由于本公开显示基板的制备过程是先制备显示母板，然后将显示母板切割成个显示基板，因此下述描述中，切割前的基板称之为显示母板，切割后的基板称之为显示基板。如图3所示，显示母板包括基板区域和位于基板区域外围的切割区域200，基板区域包括显示区100、绑定针区140、第一单元测试区110和第二单元测试区120。
(1)在刚性载板1上制备柔性基底10。本公开中，柔性基底10包括在刚性载板1上叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称之为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。在一示例性实施方式中，以叠层结构PI1/Barrier1/a-si/PI2/Barrier2为例，其制备过程可以包括：先在刚性载板1上涂布一层聚酰亚胺，固化成膜后形成第一柔性(PI1)层10A；随后在第一柔性层10A上沉积一层阻挡薄膜，形成覆盖第一柔性层10A的第一阻挡(Barrier1)层10B；然后在第一阻挡层10B上沉积一层非晶硅薄膜，形成覆盖第一阻挡层10B的非晶硅(a-si)层10C；然后在非晶硅层10C上再涂布一层聚酰亚胺，固化成膜后形成第二柔性(PI2)层10D；然后在第二柔性层10D上沉积一层阻挡薄膜，形成覆盖第二柔性层10D的第二阻挡(Barrier2)层10E，完成柔性基底10的制备，如图4所示。本次工艺后，显示区100、第一单元测试区110和第二单元测试区120均包括柔性基底10。
(2)在柔性基底10上制备驱动结构层图案。显示区100的驱动结构层包括构成像素驱动电路的第一晶体管101和第一存储电容102，第一单元测试区110的驱动结构层包括第一单元测试电极111、第一信号线112和第二信号线122，第二单元测试区120的驱动结构层包括第二单元测试电极121和第二信号线122，本实施例中，第二信号线122穿过第一单元测试区110与绑定针区140连接。在一种示例性实施方式中，驱动结构层的制备过程可以包括：
在柔性基底10上依次沉积第一绝缘薄膜和有源层薄膜，通过构图工艺对有源层薄膜进行构图，形成覆盖整个柔性基底10的第一绝缘层11，以及位于第一绝缘层11上的有源层图案，有源层图案形成在显示区100，至少包括第一有源层12A。本次构图工艺后，第一单元测试区110和第二单元测试区120包括位于柔性基底10上的第一绝缘层11。
随后，依次沉积第二绝缘薄膜和第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，形成覆盖有源层图案的第二绝缘层13，以及位于第二绝缘层13上的第一栅金属层图案，第一栅金属层图案形成在显示区100，至少包括第一栅电极14A、第一电容电极14B和多条栅线(未示出)。本次构图工艺后，第一单元测试区110和第二单元测试区120包括在柔性基底10叠设的第一绝缘层11和第二绝缘层13。
随后，依次沉积第三绝缘薄膜和第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，形成覆盖第一栅金属层的第三绝缘层15，以及位于第三绝缘层15上的第二栅金属层和第一金属层图案，第二栅金属层图案形成在显示区100，至少包括第二电容电极16A，第二电容电极16A的位置与第一电容电极14B的位置相对应。第一金属层形成在第一单元测试区110，至少包括第一信号线112和第一单元测试电极111图案，第一信号线112用于连接第一单元测试电极111和绑定针区140。本次构图工艺后，第二单元测试区120包括在柔性基底10叠设的第一绝缘层11、第二绝缘层13和第三绝缘层15。
随后，沉积第四绝缘薄膜，通过构图工艺对第四绝缘薄膜进行构图，形成覆盖第二栅金属层的第四绝缘层17图案，第四绝缘层17上开设有多个第一过孔，多个第一过孔形成在显示区100，其位置分别与第一有源层12A的两端位置相对应，多个第一过孔内的第四绝缘层17、第三绝缘层15和第二绝缘层13被刻蚀掉，分别暴露出第一有源层12A的表面。本次构图工艺后，第一单元测试区110包括在柔性基底10上叠设的第一绝缘层11、第二绝缘层13、第三绝缘层15、第一金属层和第四绝缘层17。第二单元测试区120包括在柔性基底10上叠设的第一绝缘层11、第二绝缘层13、第三绝缘层15和第四绝缘层17。
随后，沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，在 第四绝缘层17上形成源漏金属层图案和第二金属层图案，源漏金属层形成在显示区100，至少包括第一源电极18A、第一漏电极18B和多条数据线(未示出)图案，第一源电极18A和第一漏电极18B分别通过第一过孔与第一有源层12A连接。在一示例性实施方式中，根据实际需要，源漏金属层还可以包括电源线(VDD)、补偿线和辅助阴极中的任意一种或多种，源漏金属层也称之为第一源漏金属层(SD1)。第二金属层至少包括第二单元测试电极121和第二信号线122图案，其中，第二信号线122同时形成在第一单元测试区110和第二单元测试区120，第二单元测试电极121形成在第二单元测试区120，第二信号线122用于连接第二单元测试电极121和绑定针区140，且第一信号线112在柔性基底10上的正投影和第二信号线122在柔性基底10上的正投影不重叠。在一种示例性实施例中，第一信号线112和第二信号线122相互平行且间隔设置，第一信号线112和第二信号线122的宽度为45至75微米，第一信号线112和第二信号线122之间的间隔为45至75微米。
在一种示例性实施方式中，第一单元测试电极111的宽度为2500微米至7500微米，高度为400微米至1200微米，第二单元测试电极121的宽度为2500微米至7500微米，高度为400微米至1200微米，第一单元测试电极111和第二单元测试电极121之间的距离为400微米至1200微米。本实施例中，如图1所示，第一单元测试电极111或第二单元测试电极121的宽度指的是第一单元测试电极111或第二单元测试电极121在x方向的长度，第一单元测试电极111或第二单元测试电极121的高度指的是第一单元测试电极111或第二单元测试电极121在y方向的长度。
随后，沉积第五绝缘薄膜，形成覆盖源漏金属层的第五绝缘层19图案。
至此，在柔性基底10上制备完成驱动结构层图案，如图5所示。显示区100的驱动结构层包括：位于柔性基底10上的第一绝缘层11，位于第一绝缘层11上的有源层，覆盖有源层的第二绝缘层13，位于第二绝缘层13上的第一栅金属层，覆盖第一栅金属层的第三绝缘层15，位于第三绝缘层15上的第二栅金属层，覆盖第二栅金属层的第四绝缘层17，位于第四绝缘层17上的源漏金属层，覆盖源漏金属层的第五绝缘层19。有源层至少包括第一有源层12A，第一栅金属层至少包括第一栅电极14A和第一电容电极14B，第二 栅金属层至少包括第二电容电极16A，源漏金属层至少包括第一源电极18A、第一漏电极18B，第一有源层12A、第一栅电极14A、第一源电极18A和第一漏电极18B组成第一晶体管101，第一电容电极14B和第二电容电极16A组成第一存储电容102。在一示例性实施方式中，第一晶体管101可以是像素驱动电路中的驱动晶体管，驱动晶体管可以是薄膜晶体管(Thin Film Transistor，TFT)。
第一单元测试区110的驱动结构层包括在柔性基底10上依次叠设的第一绝缘层11、第二绝缘层13、第三绝缘层15，位于第三绝缘层15上的第一金属层，覆盖第一金属层的第四绝缘层17，位于第四绝缘层17上的第二金属层，覆盖第二金属层的第五绝缘层19。
第二单元测试区120的驱动结构层包括在柔性基底10上依次叠设的第一绝缘层11、第二绝缘层13、第三绝缘层15、第四绝缘层17，位于第四绝缘层17上的第二金属层，覆盖第二金属层的第五绝缘层19。
(3)在第五绝缘层19上开设多个第一开孔20和第二开孔21，多个第一开孔20形成在第一单元测试区110，其位置分别与第一单元测试电极111的位置相对应，多个第一开孔20内的第四绝缘层16被刻蚀掉，分别暴露出第一单元测试电极111的表面。多个第二开孔21形成在第二单元测试区120，其位置分别与第二单元测试电极121的位置相对应，分别暴露出第二单元测试电极121的表面，如图6所示。
在制备完成上述膜层结构后，在显示区100依次形成第一平坦层、第二源漏金属层、第二平坦层、像素定义层、有机发光层、阴极和封装层。随后，通过剥离工艺将显示母板从刚性载板1上剥离，然后采用滚轮贴合方式在显示母板背面(柔性基底10远离膜层的一侧表面)贴附一层背膜，完成显示母板的制备。随后，切割设备沿着切割道201进行切割，将显示母板分隔成本公开的显示基板。切割完成后，切割区域200被切割掉，如图1所示。
在一种示例性实施方式中，显示基板区域还可以包括保护膜(Temporary Protect Film，TPF)，保护膜贴设在封装层上，保护膜用于保护显示基板的膜层结构，贴附背膜操作是在贴附保护膜后进行。完成切割后，先去除该保 护膜，然后在封装层上依次设置触控层和盖板，形成触控显示面板。
本公开中，第一绝缘薄膜、第二绝缘薄膜、第三绝缘薄膜、第四绝缘薄膜和第五绝缘薄膜可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层称之为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层称之为栅绝缘(GI)层，第四绝缘层称之为层间绝缘(ILD)层，第五绝缘层称之为钝化(PVX)层。第一平坦层和第二平坦层可以采用有机材料。第一金属薄膜、第二金属薄膜、第三金属薄膜和第四金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。阴极可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或更多种，或采用上述金属中任意一种或多种制成的合金。有源层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等各种材料，即本公开适用于基于氧化物Oxide技术、硅技术以及有机物技术制造的晶体管。透明导电薄膜可以采用氧化铟锡ITO或氧化铟锌IZO，像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等。
通过本公开显示基板的结构及其制备过程可以看出，本公开实施例通过将第一单元测试电极111和第二单元测试电极121分别位于两个金属层上，缩短了单元测试电极的长度，使得在单元显示面板阶段，具有触控功能的AMOLED显示器的异形切割不会切开单元测试电极，即异形切割仍可在单元显示面板阶段进行，从而释放了模组阶段产能，提升了整体产能。
本公开所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，本示例中，第一金属层与第二栅金属层同层设置，第二金属层与第一源漏金属层同层设置。在其他示例中，第一金属层可以与第一栅金属层同层设置，第二金属层可以与第二栅金属层同层设置；或者，第一金属层可以与第一源漏金属层同层设置，第二金属层可以与第二源漏金属层同层设置。本公开在此 不做具体的限定。
本公开还提供了一种显示基板的制备方法，如图7所示，该制备方法包括步骤S1至步骤S3。
其中，步骤S1包括：在刚性载板上形成柔性基底。
步骤S2包括：在柔性基底上形成驱动结构层，驱动结构层包括第一金属层、第二金属层以及位于第一金属层和第二金属层之间的绝缘层，第一金属层包括一个或多个第一单元测试电极；第二金属层包括一个或多个第二单元测试电极。
在一种示例性实施例中，第一金属层还包括多条第一信号线，第一信号线的一端与第一单元测试电极连接，另一端与绑定针区连接；第二金属层还包括多条第二信号线，第二信号线的一端与第二单元测试电极连接，另一端与绑定针区连接，第一信号线在柔性基底上的正投影和第二信号线在柔性基底上的正投影不重叠。
在一种示例性实施例中，第一信号线112和第二信号线122相互平行且间隔设置，第一信号线112和第二信号线122的宽度为45至75微米，第一信号线112和第二信号线122之间的间隔为45至75微米。
示例性的，第一信号线112的宽度可以为60微米，第二信号线122的宽度可以为60微米，第一信号线112和第二信号线122之间的间隔可以为60微米。
在一种示例性实施例中，第一单元测试电极111的宽度为2500微米至7500微米，高度为400微米至1200微米，第二单元测试电极121的宽度为2500微米至7500微米，高度为400微米至1200微米，第一单元测试电极111和第二单元测试电极121之间的距离为400微米至1200微米。本实施例中，第一单元测试电极111或第二单元测试电极121的宽度指的是第一单元测试电极111或第二单元测试电极121在x方向的长度，第一单元测试电极111或第二单元测试电极121的高度指的是第一单元测试电极111或第二单元测试电极121在y方向的长度。
示例性的，第一单元测试电极111的宽度可以为5000微米，高度可以为 750微米，第二单元测试电极121的宽度可以为5000微米，高度可以为750微米，第一单元测试电极111和第二单元测试电极121之间的距离可以为750微米。
在一种示例性实施例中，显示基板包括显示区，显示区包括位于柔性基底上的第一绝缘层、位于第一绝缘层上的有源层、覆盖有源层的第二绝缘层、位于第二绝缘层上的第一栅金属层、覆盖第一栅金属层的第三绝缘层、位于第三绝缘层上的第二栅金属层、覆盖第二栅金属层的第四绝缘层、位于第四绝缘层上的第一源漏金属层、覆盖第一源漏金属层的第五绝缘层。
第一金属层可以与第一栅金属层同层设置，第二金属层可以与第二栅金属层同层设置；或者，第一金属层可以与第二栅金属层同层设置，第二金属层可以与第一源漏金属层同层设置。
步骤S3包括：将柔性基底与刚性载板分离。
本公开还提供了一种显示装置，包括前述实施例的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本申请中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本申请的权利要求的范围当中。

Claims (14)

  1. 一种显示基板，包括基底以及位于所述基底一侧的显示区、绑定针区、第一单元测试电极和第二单元测试电极，所述绑定针区位于所述显示区的一侧，所述第一单元测试电极位于所述绑定针区远离所述显示区的一侧，所述第二单元测试电极位于所述第一单元测试电极远离所述绑定针区的一侧；
    所述显示基板包括第一金属层、第二金属层以及位于所述第一金属层和第二金属层之间的绝缘层，所述第一单元测试电极位于所述第一金属层上，所述第二单元测试电极位于所述第二金属层上。
  2. 根据权利要求1所述的显示基板，其中，所述第一单元测试电极的数量为一个或多个；所述第二单元测试电极的数量为一个或多个。
  3. 根据权利要求1所述的显示基板，其中，所述第一金属层还包括多条第一信号线，所述第一信号线的一端与所述第一单元测试电极连接，另一端与所述绑定针区连接；所述第二金属层还包括多条第二信号线，所述第二信号线的一端与所述第二单元测试电极连接，另一端与所述绑定针区连接，所述第一信号线在所述柔性基底上的正投影和所述第二信号线在所述柔性基底上的正投影不重叠。
  4. 根据权利要求3所述的显示基板，其中，所述第一信号线和所述第二信号线相互平行且间隔设置，所述第一信号线和第二信号线的宽度为45至75微米，所述第一信号线和第二信号线之间的间隔为45至75微米。
  5. 根据权利要求3所述的显示基板，其中，所述显示区包括触控信号线和数据线；
    所述第一单元测试电极通过所述第一信号线连接至所述触控信号线；所述第二单元测试电极通过所述第二信号线连接至所述数据线；或者，
    所述第一单元测试电极通过所述第一信号线连接至所述数据线；所述第二单元测试电极通过所述第二信号线连接至所述触控信号线。
  6. 根据权利要求1所述的显示基板，其中，所述第一单元测试电极的宽度为2500微米至7500微米，高度为400微米至1200微米，所述第二单元测试电极的宽度为2500微米至7500微米，高度为400微米至1200微米，所述第一单元测试电极和所述第二单元测试电极之间的距离为400微米至1200微米。
  7. 根据权利要求1所述的显示基板，其中，所述显示区包括位于所述柔性基底上的第一绝缘层、位于所述第一绝缘层上的有源层、覆盖所述有源层的第二绝缘层、位于所述第二绝缘层上的第一栅金属层、覆盖所述第一栅金属层的第三绝缘层、位于所述第三绝缘层上的第二栅金属层、覆盖所述第二栅金属层的第四绝缘层、位于所述第四绝缘层上的第一源漏金属层、覆盖所述第一源漏金属层的第五绝缘层；
    所述第一金属层与所述第一栅金属层同层设置，所述第二金属层与所述第二栅金属层同层设置；或者，所述第一金属层与所述第二栅金属层同层设置，所述第二金属层与所述第一源漏金属层同层设置。
  8. 根据权利要求1所述的显示基板，其中，所述显示基板还包括阵列测试电极，所述阵列测试电极位于所述第二单元测试电极远离所述第一单元测试电极的一侧；
    所述阵列测试电极位于所述第一金属层上或者所述第二金属层上。
  9. 根据权利要求8所述的显示基板，其中，所述显示基板还包括第三信号线，所述第三信号线的一端与所述阵列测试电极连接，另一端与所述绑定针区连接；所述第三信号线与所述阵列测试电极同层设置。
  10. 根据权利要求9所述的显示基板，其中，所述第一单元测试电极的数量为两个，所述第二单元测试电极的数量为两个，所述第三信号线位于两个所述第一单元测试电极之间，且所述第三信号线位于两个所述第二单元测试电极之间。
  11. 根据权利要求8所述的显示基板，其中，所述显示基板还包括第四信号线，所述第四信号线的一端与所述阵列测试电极连接，另一端与所述第 一单元测试电极和第二单元测试电极中的至少一个连接。
  12. 一种显示装置，包括：如权利要求1至11任一所述的显示基板。
  13. 一种显示基板的制备方法，所述制备方法包括：
    在刚性载板上形成柔性基底；
    在所述柔性基底上形成驱动结构层，所述驱动结构层包括第一金属层、第二金属层以及位于所述第一金属层和第二金属层之间的绝缘层，所述第一金属层包括一个或多个第一单元测试电极；所述第二金属层包括一个或多个第二单元测试电极；
    将所述柔性基底与所述刚性载板分离。
  14. 根据权利要求13所述的制备方法，其中，所述显示基板包括显示区，所述显示区的驱动结构层包括位于所述柔性基底上的第一绝缘层、位于所述第一绝缘层上的有源层、覆盖所述有源层的第二绝缘层、位于所述第二绝缘层上的第一栅金属层、覆盖所述第一栅金属层的第三绝缘层、位于所述第三绝缘层上的第二栅金属层、覆盖所述第二栅金属层的第四绝缘层、位于所述第四绝缘层上的第一源漏金属层、覆盖所述第一源漏金属层的第五绝缘层；
    所述第一金属层与所述第一栅金属层同层设置，所述第二金属层与所述第二栅金属层同层设置；或者，所述第一金属层与所述第二栅金属层同层设置，所述第二金属层与所述第一源漏金属层同层设置。
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