WO2022126469A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2022126469A1
WO2022126469A1 PCT/CN2020/137121 CN2020137121W WO2022126469A1 WO 2022126469 A1 WO2022126469 A1 WO 2022126469A1 CN 2020137121 W CN2020137121 W CN 2020137121W WO 2022126469 A1 WO2022126469 A1 WO 2022126469A1
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WIPO (PCT)
Prior art keywords
fan
area
data
sub
lines
Prior art date
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PCT/CN2020/137121
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English (en)
French (fr)
Inventor
金度岭
于鹏飞
张毅
肖云升
刘庭良
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/441,702 priority Critical patent/US20220399433A1/en
Priority to PCT/CN2020/137121 priority patent/WO2022126469A1/zh
Priority to CN202080003376.1A priority patent/CN115210878A/zh
Publication of WO2022126469A1 publication Critical patent/WO2022126469A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels

Definitions

  • This document relates to, but is not limited to, the field of display technology, especially a display substrate and a display device.
  • LCD liquid crystal display
  • OLED organic light emitting diode
  • PDP plasma display panel
  • FED Field Emission Display
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • an embodiment of the present disclosure provides a display substrate, including: a base substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of signal input pads, a data fan-out line layer, and a plurality of resistance compensation units.
  • the base substrate includes a display area and a frame area around the display area.
  • the frame area includes: a signal access area located on one side of the display area, and a fan-out area located between the display area and the signal access area.
  • a plurality of sub-pixels are located in the display area.
  • a plurality of data lines are located in the display area and are electrically connected to the plurality of sub-pixels, and the plurality of data lines are configured to provide data signals to the plurality of sub-pixels.
  • a plurality of signal input pads are located in the signal access area.
  • a data fan-out line layer and a plurality of resistance compensation units are arranged in the fan-out area.
  • the data fan-out line layer includes: a plurality of data fan-out lines, and the plurality of data fan-out lines are configured to connect the plurality of data lines and a plurality of signal input pads provided in the signal access area.
  • At least one of the plurality of resistance compensation units includes a semiconductor structure. At least one of the plurality of data fan-out lines is connected in series and electrically with the at least one resistance compensation unit.
  • the area of the semiconductor structure of the resistance compensation unit is proportional to the resistance value to be compensated for the data fan-out line connected in series with the resistance compensation unit.
  • the total area of the semiconductor structures of the resistance compensation units connected in series with the data fan-out lines with smaller resistance values is larger than the total area of the semiconductor structures of the resistance compensation units connected in series with the data fan-out lines with larger resistance values.
  • At least one of the plurality of resistance compensation units further includes a conductive connection structure, the semiconductor structure and the conductive connection structure are sequentially disposed on the base substrate, and the semiconductor structure and electrically connected to the conductive connection structure.
  • the conductive connection structure of the resistance compensation unit includes: a first connection electrode and a second connection electrode.
  • a data fanout line connected in series with the resistance compensation unit includes a disconnected first portion and a second portion. The first part of the data fan-out line is connected to the semiconductor structure of the resistance compensation unit through the first connection electrode, and the second part of the data fan-out line is connected to the semiconductor structure through the second connection electrode.
  • the first portion has an interconnected first end and a first extension
  • the second portion has an interconnected second end and a second extension.
  • the first end portion is connected to the semiconductor structure through the first connection electrode
  • the second end portion is connected to the semiconductor structure through the second connection electrode.
  • the length of the first end portion along the first direction is greater than the length of the first extension portion along the first direction, the length of the second end portion along the first direction, the length of the second extension portion along the first direction .
  • the first direction is perpendicular to the extending direction of the data lines of the display area.
  • a plurality of data fan-out lines in the fan-out region are connected in series and electrically connected to a plurality of resistance compensation units in a one-to-one correspondence.
  • the plurality of resistance compensation units are sequentially arranged along a direction perpendicular to the extending direction of the data lines of the display area, or, along the extension parallel to the data lines of the display area
  • the directions of the directions are staggered.
  • the total area of the semiconductor structure of the resistance compensation unit to which the plurality of data fan-out lines in the fan-out region are electrically connected increases in a direction from the edge to the middle of the fan-out region, Or, increment first and then decrement.
  • the fan-out area has a plurality of fan-out points in a direction perpendicular to an extending direction of the data lines of the display area.
  • the resistance compensation units electrically connected to the plurality of data fan-out lines in at least one fan-out partition are sequentially arranged along a direction perpendicular to the extending direction of the data lines in the display area, or along the data lines parallel to the display area The directions of the extending directions of the lines are staggered.
  • the total area of the semiconductor structure of the resistance compensation unit to which the plurality of data fan-out lines in the at least one fan-out region are electrically connected increases in a direction from the edge to the middle of the fan-out region, Or, increment first and then decrement.
  • the semiconductor structure is located on a side of the data fan-out layer close to the base substrate, and the conductive connection structure is located on a side of the data fan-out layer away from the base substrate .
  • the frame area further includes: a bending area located between the signal access area and the display area.
  • the fan-out area includes: a first fan-out area located between the display area and the bending area, and a second fan-out area located between the bending area and the signal access area.
  • the at least one data fan-out line includes: a first sub-data fan-out line located in the first fan-out area, and a second sub-data fan-out line located in the second fan-out area and connected to the first sub-data fan-out line.
  • the at least one resistance compensation unit is configured to satisfy one of the following: disposed in the first fan-out area and connected in series with and electrically connected to at least one first sub-data fan-out line; disposed in the second fan-out area and connected to the second fan-out area. At least one second sub-data fan-out line is connected in series and electrically.
  • the frame area further includes: a bending area located between the signal access area and the display area, and a test circuit located between the bending area and the signal access area area.
  • the fan-out area includes: a first fan-out area located between the display area and the bending area, a second fan-out area located between the bending area and the test circuit area, and a fan-out area located between the bending area and the test circuit area.
  • the at least one data fan-out line includes: a first sub-data fan-out line located in the first fan-out region, a second sub-data fan-out line located in the second fan-out region and electrically connected to the first sub-data fan-out line, and A third sub-data fan-out line located in the third fan-out region and electrically connected to the second sub-data fan-out line.
  • the at least one resistance compensation unit is configured to satisfy one of the following: disposed in the first fan-out area and connected in series with and electrically connected to at least one first sub-data fan-out line; disposed in the second fan-out area and connected to the second fan-out area.
  • At least one second sub-data fan-out line is connected in series and electrically; it is arranged in the third fan-out region and is connected in series and electrically with at least one third sub-data fan-out line.
  • the plurality of resistance compensation units are all disposed in the second fan-out area, and at least one second sub-data fan-out line and at least one resistance compensation unit in the second fan-out area in series and electrically connected.
  • the plurality of resistance compensation units disposed in the second fan-out area are close to a test circuit area or close to the signal access area.
  • the data fan-out line layer includes: a first data fan-out line layer and a second data fan-out line layer, which are sequentially arranged on the base substrate and are insulated from each other.
  • the first data fan-out line layer includes a plurality of first data fan-out lines
  • the second data fan-out line layer includes a plurality of second data fan-out lines. Orthographic projections of the first data fan-out line layer and the second data fan-out line layer on the base substrate do not overlap, and the plurality of first data fan-out lines and the plurality of second data fan-out lines are spaced apart Arrange.
  • the display area at least includes: a driving structure layer disposed on the base substrate, a light-emitting element disposed on the driving structure layer; the light-emitting element is electrically connected to the driving structure layer .
  • the driving structure layer includes: an active layer, a first gate metal layer, a second gate metal layer and a source-drain metal layer which are sequentially arranged on the base substrate.
  • the first data fan-out layer and the first gate metal layer are of the same layer structure, the second data fan-out layer and the second gate metal layer are of the same layer structure; the semiconductor structure and the The source layer is of the same layer structure; the conductive connection structure and the source and drain metal layers are of the same layer structure.
  • an embodiment of the present disclosure provides a display device including the above-mentioned display substrate.
  • FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the disclosure
  • FIG. 2 is a schematic diagram of a first frame area according to at least one embodiment of the disclosure
  • Fig. 3 is the partial enlarged schematic diagram of area S in Fig. 2;
  • FIG. 4 is a schematic cross-sectional view along the A-A direction in FIG. 3;
  • Figure 5 is a schematic cross-sectional view along the B-B direction in Figure 3;
  • FIG. 6 is a schematic diagram of a resistance distribution curve of a data fan-out line of a display substrate before and after resistance compensation is performed according to at least one embodiment of the present disclosure
  • Fig. 7 is a kind of sectional schematic diagram along P-P direction in Fig. 2;
  • FIG. 8 is another schematic cross-sectional view along the P-P direction in FIG. 2;
  • Fig. 9 is another partial enlarged schematic diagram of region S in Fig. 2;
  • Fig. 10 is another partial enlarged schematic diagram of region S in Fig. 2;
  • FIG. 11 is another schematic diagram of a first frame area of a display substrate according to at least one embodiment of the disclosure.
  • FIG. 12 is another schematic diagram of a first frame area of a display substrate according to at least one embodiment of the disclosure.
  • FIG. 13 is another schematic diagram of a first frame area of a display substrate according to at least one embodiment of the disclosure.
  • FIG. 14 is another schematic diagram of a first frame area of a display substrate according to at least one embodiment of the disclosure.
  • FIG. 15 is a schematic diagram of a display device according to at least one embodiment of the disclosure.
  • ordinal numbers such as “first”, “second”, and “third” are set to avoid confusion of constituent elements, rather than to limit the quantity.
  • "Plurality” in this disclosure means a quantity of two or more.
  • the terms “installed”, “connected” and “connected” should be construed broadly unless otherwise expressly specified and limited. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed should be construed broadly unless otherwise expressly specified and limited. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in the present disclosure, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrically connected includes the case where constituent elements are connected together by elements having some electrical function.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having some electrical function” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having one or more functions, and the like.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus can include a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to a state in which the angle formed by two straight lines is 80° or more and 100° or less, and therefore may include a state in which an angle of 85° or more and 95° or less is included.
  • film and “layer” are interchangeable.
  • conductive layer may be replaced by “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • Embodiments of the present disclosure provide a display substrate, including: a base substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of signal input pads, a data fan-out line layer, and a plurality of resistance compensation units.
  • the base substrate includes a display area and a frame area around the display area.
  • the frame area includes: a signal access area located on one side of the display area, and a fan-out area located between the display area and the signal access area.
  • a plurality of sub-pixels are located in the display area.
  • a plurality of data lines are located in the display area and are electrically connected to the plurality of sub-pixels, and the plurality of data lines are configured to provide data signals to the plurality of sub-pixels.
  • a number of signal input pads are located in the signal access area.
  • the data fan-out line layer and a plurality of resistance compensation units are arranged in the fan-out area.
  • the data fan-out line layer includes a plurality of data fan-out lines, and the plurality of data fan-out lines are configured to connect the plurality of data lines and a plurality of signal input pads provided in the signal access area.
  • At least one resistance compensation unit includes a semiconductor structure.
  • At least one data fanout line is connected in series and electrically with at least one resistance compensation unit. For example, one data fan-out line is connected in series with one resistance compensation unit and is electrically connected, or, one data fan-out line is connected in series and electrically with multiple resistance compensation units. However, this embodiment does not limit this.
  • the display substrate provided by the embodiment of the present disclosure, by arranging a plurality of resistance compensation units in the fan-out area, the resistance values of the plurality of data fan-out lines are compensated, the resistance value difference between the plurality of data fan-out lines after compensation is reduced, and the improvement of The display color shift or uneven brightness caused by the difference in the resistance value of the data fan-out lines, thereby improving the display effect.
  • the display substrate of this embodiment may be a liquid crystal display (LCD, Liquid Crystal Display), an organic light emitting diode (OLED, Organic Light-Emitting Diode) display, a plasma display panel (PDP, Plasma Display Panel) ), or a Field Emission Display (FED, Field Emission Display).
  • LCD Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • PDP Plasma Display Panel
  • FED Field Emission Display
  • the present embodiment does not limit the type of the display substrate.
  • the area of the semiconductor structure of the resistance compensation unit is proportional to the resistance value to be compensated for the data fan-out lines connected in series with the resistance compensation unit.
  • the larger the area of the semiconductor structure of the resistance compensation unit the larger the compensation resistance value provided by the resistance compensation unit; the smaller the area of the semiconductor structure of the resistance compensation unit, the smaller the compensation resistance value provided by the resistance compensation unit.
  • the total area of the semiconductor structures of the resistance compensation units connected in series with the data fan-out lines with smaller resistance values is larger than the total area of the semiconductor structures of the resistance compensation units connected in series with the data fan-out lines with larger resistance values.
  • by adjusting the area of the semiconductor structure of the resistance compensation unit connected in series with the data fan-out lines different compensation resistance values can be provided for different data fan-out lines, thereby compensating for the difference in resistance value between different data fan-out lines .
  • At least one of the plurality of resistance compensation units further includes a conductive connection structure.
  • the semiconductor structure and the conductive connection structure are sequentially arranged on the base substrate, and the semiconductor structure and the conductive connection structure are electrically connected.
  • the electrical connection between the data fan-out line and the semiconductor structure is achieved through the conductive connection structure.
  • the conductive connection structure of the resistance compensation unit includes: a first connection electrode and a second connection electrode.
  • the data fanout line connected in series with the resistance compensation unit includes a disconnected first portion and a second portion.
  • the first part of the data fan-out line is connected to the semiconductor structure through the first connection electrode of the resistance compensation unit, and the second part of the data fan-out line is connected to the semiconductor structure through the second connection electrode of the resistance compensation unit.
  • the series connection between the semiconductor structure and the data fan-out line can be achieved through the conductive connection structure.
  • a plurality of data fan-out lines in the fan-out region are connected in series with a plurality of resistance compensation units in a one-to-one correspondence.
  • one data fanout line is connected in series with one resistance compensation unit.
  • the areas of the semiconductor structures of the plurality of resistance compensation units may be different or partially the same. However, this embodiment does not limit this. In some examples, the areas of the semiconductor structures of the plurality of resistance compensation units may be the same, and the number of the resistance compensation units connected in series by at least one data fan-out line may be determined according to the resistance value to be compensated for the data fan-out line.
  • a plurality of data fan-out lines in the fan-out region are connected in series and electrically connected to a plurality of resistance compensation units in a one-to-one correspondence.
  • the plurality of resistance compensation units in the fan-out area are sequentially arranged along the first direction, or are arranged staggered along the second direction perpendicular to the first direction.
  • the first direction is perpendicular to the extending direction of the data lines of the display area.
  • the arrangement direction of the plurality of resistance compensation units in the fan-out region is parallel to the first direction, or there is a certain angle with the first direction.
  • this embodiment does not limit this.
  • the total area of the semiconductor structure of the resistance compensation unit electrically connected by the plurality of data fan-out lines in the fan-out region increases, or, increases first Decrease later.
  • the change of the total area of the semiconductor structure of the resistance compensation unit is related to the change of the resistance value of the data fan-out line connected to the resistance compensation unit.
  • the resistance value of the data fan-out line connected to the resistance compensation unit is along the As the direction decreases from the edge to the middle of the fan-out region, the total area of the semiconductor structure of the resistance compensation unit increases along the direction from the edge to the middle of the fan-out region.
  • the fan-out region has a plurality of fan-out partitions in the first direction.
  • the first direction is perpendicular to the extending direction of the data lines of the display area.
  • the resistance compensation units connected to the plurality of data fan-out lines in the at least one fan-out partition are sequentially arranged along the first direction, or staggered along the second direction perpendicular to the first direction.
  • the arrangement of the resistance compensation units in the multiple fan-out partitions is the same; for example, the arrangement direction of the multiple resistance compensation units in each fan-out partition is parallel to the first direction, or, The arrangement is staggered along the second direction.
  • the arrangement of the resistance compensation units in the multiple fan-out partitions is different; for example, the arrangement direction of the multiple resistance compensation units in at least one fan-out partition is parallel to the first direction, and the rest of the fan-out partitions are arranged in a direction parallel to the first direction.
  • the plurality of resistance compensation units in the partition are staggered along the second direction.
  • this embodiment does not limit this.
  • the total area of the semiconductor structure of the resistance compensation unit to which the plurality of data fan-out lines in the at least one fan-out region are electrically connected increases in a direction from the edge to the middle of the fan-out region, or, Increment first and then decrease.
  • this embodiment does not limit this.
  • the semiconductor structure is located on a side of the data fan-out layer close to the base substrate, and the conductive connection structure is located on a side of the data fan-out layer away from the base substrate.
  • the semiconductor structure and the data fan-out line of the data fan-out line layer are connected by the conductive connection structure.
  • the frame area further includes: a bending area located between the signal access area and the display area.
  • the fan-out area includes: a first fan-out area located between the display area and the bending area, and a second fan-out area located between the bending area and the signal access area.
  • the at least one data fan-out line includes: a first sub-data fan-out line located in the first fan-out area, and a second sub-data fan-out line located in the second fan-out area and connected to the first sub-data fan-out line.
  • the at least one resistance compensation unit is configured to satisfy one of the following: disposed in the first fan-out area and connected in series with and electrically connected to at least one first sub-data fan-out line; disposed in the second fan-out area and connected to at least one second sub-data fan-out line
  • the fanout lines are connected in series and electrically.
  • a plurality of resistance compensation units may all be arranged in the first fan-out area; alternatively, a plurality of resistance compensation units may be arranged in the second fan-out area; or, a part of the plurality of resistance compensation units may be arranged in the first fan-out area , and the other part is set in the second fan-out area.
  • this embodiment does not limit this.
  • the frame area further includes: a bending area between the signal access area and the display area, and a test circuit area between the bending area and the signal access area.
  • the fan-out area includes: a first fan-out area between the display area and the bending area, a second fan-out area between the bending area and the test circuit area, and between the test circuit area and the signal access area the third fan-out region.
  • the at least one data fan-out line includes: a first sub-data fan-out line located in the first fan-out area, a second sub-data fan-out line located in the second fan-out area and electrically connected to the first sub-data fan-out line, and a third fan-out line located in the third fan-out area.
  • the at least one resistance compensation unit is configured to satisfy one of the following: disposed in the first fan-out area and connected in series with and electrically connected to at least one first sub-data fan-out line; disposed in the second fan-out area and connected to at least one second sub-data fan-out line.
  • the fan-out lines are connected in series and electrically; they are arranged in the third fan-out region and are connected in series and electrically with at least one third sub-data fan-out line.
  • a plurality of resistance compensation units may all be arranged in the first fan-out area; or, a plurality of resistance compensation units may be arranged in a second fan-out area; or, a plurality of resistance compensation units may be arranged in the third fan-out area; or , a part of the plurality of resistance compensation units is arranged in the first fan-out area, and the other part is arranged in the second fan-out area; or, a part of the plurality of resistance compensation units is arranged in the second fan-out area, and the other part is arranged in the first fan-out area Three fan-out areas; or, a part of the plurality of resistance compensation units is disposed in the first fan-out area, and the other part is disposed in the third fan-out area; or, a first part of the plurality of resistance compensation units is disposed in the first fan-out area area, the second part is arranged in the second fan-out area, and the third part is arranged in the third fan-out area.
  • this embodiment does not limit this
  • the plurality of resistance compensation units are all disposed in the second fan-out area, and at least one second sub-data fan-out line in the second fan-out area is connected in series with at least one resistance compensation unit and is electrically connected.
  • the plurality of resistance compensation units are all disposed in the second fan-out region.
  • the plurality of resistance compensation units in the second fan-out area are close to the test circuit area or close to the signal access area.
  • the distance between the resistance compensation unit in the second fan-out area and the bending area is greater than the distance from the test circuit area .
  • the distance between the resistance compensation unit in the second fan-out area and the bending area is greater than the distance from the signal access area.
  • this embodiment does not limit this.
  • the data fan-out layer includes: a first data fan-out layer and a second data fan-out layer, which are sequentially arranged on the base substrate and are insulated from each other.
  • the first data fan-out line layer includes a plurality of first data fan-out lines
  • the second data fan-out line layer includes a plurality of second data fan-out lines.
  • the orthographic projections of the first data fan-out line layer and the second data fan-out line layer on the base substrate do not overlap, and the plurality of first data fan-out lines and the plurality of second data fan-out lines are arranged at intervals.
  • the distance between adjacent data fan-out lines can be reduced, and the transmission interference between adjacent data fan-out lines can be reduced, thereby improving signal transmission performance .
  • the display area includes at least: a driving structure layer disposed on the base substrate, and a light-emitting element disposed on the driving structure layer.
  • the light-emitting element is electrically connected to the driving structure layer.
  • the driving structure layer includes: an active layer, a first gate metal layer, a second gate metal layer and a source-drain metal layer which are sequentially arranged on the base substrate.
  • the first data fan-out layer and the first gate metal layer are in the same layer structure, the second data fan-out layer and the second gate metal layer are in the same layer structure; the semiconductor structure and the active layer are in the same layer structure; the conductive connection structure and the source
  • the drain metal layer is of the same layer structure.
  • this embodiment does not limit this.
  • the display substrate of the present embodiment will be illustrated below through some examples.
  • the display substrate is an OLED display substrate as an example for description.
  • the drawings since the number of data lines in the display area and the data fan-out lines in the fan-out area is usually large, the drawings only illustrate some data lines and data fan-out lines or only the positions of the fan-out areas, and do not limit the data lines. and the number of data fanout lines.
  • FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the disclosure.
  • the display substrate provided by this exemplary embodiment includes: a display area 100 and a frame area located around the display area 100 .
  • the frame area includes: a first frame area 200 on one side of the display area 100 , and a second frame area 300 at the periphery of the display area 100 and away from the first frame area 200 .
  • the first frame area 200 and the second frame area 300 surround the display area 100 after being connected.
  • the first frame area 200 is a lower frame of the display substrate
  • the second frame area 300 includes an upper frame, a left frame and a right frame of the display substrate.
  • this embodiment does not limit this.
  • the display area 100 at least includes a plurality of sub-pixels 1001 , a plurality of gate lines (not shown) and a plurality of data lines 1002 .
  • the orthographic projections of the plurality of gate lines and the plurality of data lines 1002 on the base substrate form a plurality of sub-pixel regions, and each sub-pixel region is provided with a sub-pixel 1001 .
  • the plurality of data lines 1002 are electrically connected to the plurality of sub-pixels 1001 , and the plurality of data lines 1002 are configured to provide data signals to the plurality of sub-pixels 1001 .
  • a plurality of gate lines are electrically connected to the plurality of sub-pixels 1001 , and the plurality of gate lines are configured to provide scan signals to the plurality of sub-pixels 1001 .
  • one pixel unit may include three sub-pixels, which are red sub-pixels, green sub-pixels, and blue sub-pixels, respectively. However, this embodiment does not limit this.
  • one pixel unit may include four sub-pixels, which are red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, respectively.
  • the shape of the sub-pixel 1001 may be a rectangle, a diamond, a pentagon or a hexagon.
  • the three sub-pixels can be arranged horizontally, vertically, or in a square pattern; when a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically, or square (Square ) arranged in the manner.
  • Square square
  • the second frame area 300 at least includes a gate driving circuit that provides scan signals to the plurality of sub-pixels 1001 of the display area 100 , and a power supply line (eg, a low voltage) that transmits voltage signals to the plurality of sub-pixels 1001 power cord (VSS)).
  • a gate driving circuit that provides scan signals to the plurality of sub-pixels 1001 of the display area 100
  • a power supply line eg, a low voltage
  • VSS power cord
  • FIG. 2 is a schematic diagram of a first frame area according to at least one embodiment of the disclosure.
  • the first frame area 200 includes: a first fan-out area 201 located on one side of the display area 100 , and a first fan-out area 201 located away from the display area.
  • the fan-out area in the first frame area 200 includes: a first fan-out area 201 , a second fan-out area 203 and a third fan-out area 205 .
  • the first fan-out area 201 is located between the display area 100 and the bending area 202
  • the second fan-out area 203 is located between the bending area 202 and the test circuit area 204
  • the third fan-out area 205 is located in the test circuit area 204 and the signal access area 206 .
  • the first frame area 200 may further include a binding electrode area (not shown) on the side of the signal access area 206 away from the display area 100 .
  • the bonding electrode area includes a plurality of bonding pads (Bonding Pad), which are configured to be bonded and connected to an external flexible circuit board (FPC, Flexible Printed Circuit).
  • the first fan-out area 201 is provided with a plurality of first sub-data fan-out lines, a first power line (not shown) and a second power line (not shown) .
  • the plurality of first sub-data fan-out lines are configured to be connected in a one-to-one correspondence with the plurality of data lines in the display area 100 in a fan-out routing manner.
  • the first power supply line is configured to connect a high voltage power supply line (VDD) of the display area 100 .
  • the second power line is configured to connect the low voltage power line (VSS) of the second bezel area.
  • the first power line and the second power line are arranged at the same layer, and the first power line and the second power line are arranged at different layers from the plurality of first sub-data fan-out lines; the plurality of first sub-data fan-out lines are in the lining
  • the orthographic projection on the base substrate partially overlaps the orthographic projection of the first power line on the base substrate, and the orthographic projection of the plurality of first sub-data fan-out lines on the base substrate overlaps the orthographic projection of the second power lines on the base substrate.
  • the orthographic projections partially overlap.
  • the plurality of first sub-data fanout lines may be divided into two groups.
  • the plurality of first sub-data fan-out lines of the first group and the plurality of first sub-data fan-out lines of the second group are arranged at different layers.
  • the orthographic projections of the plurality of first sub-data fan-out lines of the first group and the plurality of first sub-data fan-out lines of the second group on the substrate do not overlap, and the plurality of first sub-data fan-out lines of the first group and the plurality of first sub-data fan-out lines of the second group are arranged at intervals.
  • this embodiment does not limit this.
  • a plurality of first sub-data fan-out lines in the first fan-out area may be arranged at the same layer.
  • the first fan-out region 201 includes a plurality of first fan-out sub-regions, for example, four first fan-out sub-regions 211 and 212 arranged in sequence along the first direction D1 , 213 and 214.
  • a plurality of first sub-data fan-out lines are set in each first fan-out partition. The lengths of the plurality of first sub-data fan-out lines located in the first fan-out partition 211 at the left edge of the first fan-out region 201 decrease in a direction from the edge to the middle of the first fan-out region 201 .
  • the lengths of the plurality of first sub-data fan-out lines located in the first fan-out partition 214 at the right edge of the first fan-out area 201 decrease in a direction from the edge to the middle of the first fan-out area 201 .
  • the lengths of the plurality of first sub-data fan-out lines in the first fan-out partition 212 located on the right side of the first fan-out region 211 first decrease and then increase along the direction from the edge to the middle of the first fan-out region 201 .
  • the lengths of the plurality of first sub-data fan-out lines in the first fan-out partition 213 located on the left side of the first fan-out region 214 first decrease and then increase along the direction from the edge of the first fan-out region 201 to the middle.
  • this embodiment does not limit this.
  • the lengths of the plurality of first sub-data fan-out lines in each first fan-out partition may decrease in a direction from the edge to the middle of the first fan-out region.
  • the first direction D1 is perpendicular to the extending direction of the data lines in the display area 100
  • the second direction D2 is perpendicular to the first direction D1 , that is, the second direction D2 is parallel to the extending direction of the data lines in the display area 100 .
  • the bending area 202 is configured to bend a part of the first frame area to the back of the display area 100 .
  • the bending region 202 is provided with at least a plurality of data connection lines and a plurality of power connection lines.
  • the plurality of data connection lines are configured to be connected in a one-to-one correspondence with the plurality of first sub-data fan-out lines of the first fan-out region 201 .
  • the plurality of power supply connection lines may include a first power supply connection line (eg, a high voltage power supply connection line) and a second power supply connection line (eg, a low voltage power supply connection line); the first power supply connection line is configured to be connected to the first fan-out region
  • the first power supply line of 201 is connected, and the second power supply connection line is configured to be connected with the second power supply line of the first fan-out area 201 .
  • a plurality of data connection lines and a plurality of power connection lines are arranged on the same layer.
  • the power connection line can be arranged in the middle of a plurality of data connection lines.
  • the bending region 202 includes a plurality of first bending sub-regions (eg, four first bending sub-regions 220a, 220b, 220c arranged in sequence along the first direction D1 ) and 220d), a plurality of second bending sections (eg, five second bending sections 221a, 221b, 221c, 221d and 221e arranged in sequence along the first direction D1). At least one second bending subsection is disposed between two adjacent first bending subsections. A plurality of data connection lines are arranged in each first bending subsection, and power supply connection lines are arranged in each second bending subsection.
  • first bending sub-regions eg, four first bending sub-regions 220a, 220b, 220c arranged in sequence along the first direction D1
  • second bending sections eg, five second bending sections 221a, 221b, 221c, 221d and 221e arranged in sequence along the first direction D1
  • At least one second bending subsection is
  • the second power supply connection lines are provided in the second bending sections 221a and 221e, and the first power supply connection lines are provided in the second bending sections 221b, 221c and 221d.
  • the second bending section 221b is located between the first bending sections 220a and 220b
  • the second bending section 221c is located between the first bending sections 220b and 220c
  • the second bending section 221d is located in the first bending section 221d.
  • the multiple first fan-out regions of the first fan-out region 201 correspond to the multiple first bending regions of the bending region 202 one-to-one.
  • the multiple first sub-data fan-out lines in the first fan-out partition are connected in one-to-one correspondence with the multiple data connection lines in the corresponding first bending partition.
  • the second fan-out area 203 is provided with a plurality of second sub-data fan-out lines.
  • the plurality of second sub-data fan-out lines are configured to connect the plurality of data connection lines of the bending region 202 in a fan-out routing manner, and the plurality of second sub-data fan-out lines are connected to the plurality of data connection lines of the bending region 202 one by one. corresponding connection.
  • the plurality of second sub-data fanout lines may be divided into two groups. The plurality of second sub-data fan-out lines of the first group and the plurality of second sub-data fan-out lines of the second group are arranged at different layers.
  • the orthographic projections of the plurality of second sub-data fan-out lines of the first group and the plurality of second sub-data fan-out lines of the second group on the substrate do not overlap, and the plurality of second sub-data fan-out lines of the first group and the plurality of second sub-data fan-out lines of the second group are arranged at intervals.
  • the plurality of second sub-data fan-out lines in the first group of the second fan-out area 203 may be set at the same layer as the plurality of first sub-data fan-out lines in the first group in the first fan-out area 201 , and the second fan-out The plurality of second sub-data fan-out lines in the second group of the region 203 may be arranged at the same layer as the plurality of first sub-data fan-out lines in the second group of the first fan-out region 201 .
  • this embodiment does not limit this.
  • the second fan-out region 203 includes a plurality of second fan-out sub-regions, for example, four second fan-out sub-regions 231 and 232 arranged in sequence along the first direction D1 , 233 and 234.
  • a plurality of second sub-data fan-out lines are set in each second fan-out partition.
  • the lengths of the plurality of second sub-data fan-out lines in each second fan-out partition decrease along the direction from the edge to the middle of the second fan-out region 203 .
  • the plurality of second fan-out regions of the second fan-out region 203 are in one-to-one correspondence with the plurality of first bending regions of the bending region 202 .
  • the plurality of second sub-data fan-out lines in the second fan-out partition are connected in one-to-one correspondence with the plurality of data connection lines in the corresponding first bending partition.
  • the plurality of first sub-data fan-out lines in the first fan-out region 201 are connected to the plurality of second sub-data fan-out lines in the second fan-out region 203 in one-to-one correspondence through the plurality of data connection lines in the first bending zone.
  • the number of second fan-out partitions corresponds to the number of first fan-out partitions.
  • this embodiment does not limit this.
  • the test circuit area 204 includes a test circuit
  • the test circuit includes a plurality of test cells
  • each test cell is connected to a plurality of second sub-data fan-out lines of the second fan-out region 203 connect.
  • Each test unit may provide a test data signal to a plurality of data lines of the display area 100 through the second sub-data fan-out line, the data connection line and the first sub-data fan-out line connected in sequence.
  • the test circuit may include at least one test control signal line, a plurality of test data signal lines, and a plurality of test cells, each test cell is connected to the test control signal line and the test data signal line, and is connected to a plurality of test cells in the display area.
  • test unit is configured to provide (simultaneously or separately) a signal of the test data signal line (test data signal) to a plurality of data lines of the display area connected thereto according to the control of the test control signal line to detect and locate the display area Bad sub-pixels occur.
  • test data signal test data signal
  • this embodiment does not limit the structure of the test circuit.
  • the third fan-out region 205 includes a plurality of third fan-out partitions, for example, two third fan-out partitions 251 and 252 arranged in sequence along the first direction D1 .
  • a plurality of third sub-data fan-out lines are set in each third fan-out partition.
  • the plurality of third sub-data fan-out lines are configured to connect the signal input pads of the signal access area 206 in a fan-out routing manner.
  • the lengths of the plurality of third sub-data fan-out lines in each third fan-out partition may first decrease and then increase along the direction from the edge of the third fan-out region 203 to the middle.
  • one third fanout partition corresponds to two second fanout partitions.
  • the multiple third sub-data fan-out lines in one third fan-out partition may be connected to the multiple second sub-data fan-out lines in two adjacent second fan-out partitions of the second fan-out region in a one-to-one correspondence. That is, the numbers of the third sub-data fan-out lines in the third fan-out area and the second sub-data fan-out lines in the second fan-out area are the same, and may be connected in one-to-one correspondence. However, this embodiment does not limit this. In some examples, the number of third sub-data fan-out lines in the third fan-out region and the number of second sub-data fan-out lines in the second fan-out region may be in a 1:N relationship, where N is greater than 1 the integer.
  • the plurality of third sub-data fan-out lines within the third fan-out region 205 may be divided into two groups.
  • the multiple third sub-data fan-out lines of the first group and the multiple third sub-data fan-out lines of the second group are arranged at different layers.
  • the orthographic projections of the plurality of third sub-data fan-out lines of the first group and the plurality of third sub-data fan-out lines of the second group on the substrate do not overlap, and the plurality of third sub-data fan-out lines of the first group and the plurality of third sub-data fan-out lines of the second group are arranged at intervals.
  • the multiple third sub-data fan-out lines of the first group of the third fan-out area 205 may be arranged at the same layer as the multiple second sub-data fan-out lines of the first group of the second fan-out area 203 , and the third fan-out area 205
  • the plurality of third sub-data fan-out lines of the second group may be arranged at the same layer as the plurality of second sub-data fan-out lines of the second group of the second fan-out region 203 .
  • this embodiment does not limit this.
  • the signal access area 206 includes a plurality of signal input pads configured to connect to a driver integrated circuit (IC, Integrated Circuit).
  • the driving integrated circuit may be connected to a plurality of third sub-data fan-out lines of the third fan-out area 205 through a plurality of signal input pads, and is configured to provide data signals to the plurality of data lines of the display area 100 .
  • the fan-out area of the first frame area includes a first fan-out area 201, a second fan-out area 203 and a third fan-out area 205.
  • the data fan-out lines connecting the data lines of the display area 100 and the signal input pads of the signal access area 206 in the fan-out area include: a first sub-data fan-out line located in the first fan-out area 201 , a data fan-out line located in the second fan-out area 203 and A second sub-data fan-out line electrically connected to the first sub-data fan-out line, and a third sub-data fan-out line located in the third fan-out region 205 and electrically connected to the second sub-data fan-out line.
  • All data lines in the display area 100 can be connected in parallel to the driver integrated circuits connected to the signal access area 206 through the data fan-out lines and the data connection lines in the bending area 202, and the driver integrated circuits control these data lines to the display area 100.
  • the sub-pixels provide data signals for display.
  • multiple data fan-out lines are arranged in different layers, which can reduce the spacing between adjacent data fan-out lines, reduce transmission interference between adjacent data fan-out lines, and improve signal transmission performance.
  • FIG. 3 is a partially enlarged schematic view of the area S in FIG. 2 .
  • FIG. 4 is a schematic cross-sectional view along the A-A direction in FIG. 3 .
  • FIG. 5 is a schematic cross-sectional view along the B-B direction in FIG. 3 .
  • the structures of a plurality of second sub-data fan-out lines and resistance compensation units are enlarged and illustrated, so as to illustrate the difference of the resistance compensation units connected to different second sub-data fan-out lines.
  • the plurality of second sub-data fan-out lines of the second fan-out region 203 are divided into two groups. As shown in FIG. 3 , on a plane parallel to the display substrate, the plurality of second sub-data fan-out lines 52a of the first group and the plurality of second sub-data fan-out lines 52b of the second group are arranged at intervals. As shown in FIG. 3
  • the second sub-data fan-out lines 52b of the second group are located on the side away from the base substrate 10 of the second sub-data fan-out lines 52a of the first group, and the second sub-data fan-out lines 52b of the first group are
  • the third insulating layer 13 is disposed between the second sub-data fan-out line 52b of the group and the second sub-data fan-out line 52a of the first group.
  • this embodiment does not limit this.
  • multiple second sub-data fan-out lines in the second fan-out area may be arranged at the same layer.
  • the second fan-out region 203 is further provided with a plurality of resistance compensation units.
  • the plurality of second sub-data fan-out lines in the second fan-out region 203 are connected in series and electrically connected to the plurality of resistance compensation units in one-to-one correspondence. That is, one second sub-data fanout line is connected in series with one resistance compensation unit and is electrically connected.
  • a plurality of resistance compensation units may be sequentially arranged in the second fan-out region 203 along the first direction D1. In this exemplary embodiment, by connecting the second sub-data fan-out lines in the second fan-out region in series and electrically connecting the resistance compensation unit, resistance compensation can be performed on the entire data fan-out line in the entire fan-out region.
  • the resistance compensation unit may be disposed in the first fan-out area and be connected in series with the first sub-data fan-out line and electrically connected, or may be disposed in the third fan-out area and be connected in series and electrically connected with the third sub-data fan-out line.
  • the at least one resistance compensation unit includes: a semiconductor structure 61 and a conductive connection structure sequentially disposed on the base substrate 10 .
  • the conductive connection structure includes: a first connection electrode 62 and a second connection electrode 63 .
  • the first connection electrode 62 is electrically connected to one end of the semiconductor structure 61 through the two first vias K1
  • the second connection electrode 63 is electrically connected to the other end of the semiconductor structure 61 through the two first vias K1 .
  • the first via hole K1 may be circular, oval or rectangular. However, this embodiment does not limit the number and shape of the first via holes.
  • the second sub-data fanout line 52a includes a disconnected first portion 521a and a second portion 522a.
  • a resistance compensation unit is connected in series between the first portion 521a and the second portion 522a of the second sub-data fan-out line 52a.
  • the first portion 521a of the second sub-data fan-out line 52a is electrically connected to the first connection electrode 62 of the resistance compensation unit through two second vias K2, and the second portion 522a of the second sub-data fan-out line 52a is electrically connected through two third vias K2.
  • the hole K3 is electrically connected to the second connection electrode 63 of the resistance compensation unit.
  • the second sub-data fanout line 52b includes a disconnected first portion 521b and a second portion 522b.
  • a resistance compensation unit is connected in series between the first portion 521b and the second portion 522b of the second sub-data fan-out line 52b.
  • the first portion 521b of the second sub-data fan-out line 52b is electrically connected to the first connection electrode of one resistance compensation unit through two fourth vias K4, and the second portion 522b of the second sub-data fan-out line 52b is electrically connected through two fifth vias K4.
  • the hole K5 is electrically connected to the second connection electrode of the resistance compensation unit.
  • the second via hole K2, the third via hole K3, the fourth via hole K4 and the fifth via hole K5 may be circular, oval or rectangular. However, the present embodiment does not limit the number and shape of the second via hole K2 , the third via hole K3 , the fourth via hole K4 and the fifth via hole K5 .
  • the shapes and sizes of the plurality of first connection electrodes 62 and the plurality of second connection electrodes 63 may be the same, eg, both are rectangular (eg, rounded rectangles).
  • the shapes of the plurality of semiconductor structures 61 may be the same, eg, rectangular.
  • the areas of the plurality of semiconductor structures 61 may be different, for example, the lengths of the plurality of semiconductor structures 61 along the first direction D1 may be the same, and the lengths of the plurality of semiconductor structures 61 along the second direction D2 may be different.
  • this embodiment does not limit this.
  • the second fan-out area 203 includes: the semiconductor structure 61 , the first data A fan-out line layer, a second data fan-out line layer, and a conductive connection structure.
  • the first data fan-out line layer of the second fan-out area 203 includes a plurality of second sub-data fan-out lines 52a
  • the second data fan-out line layer includes a plurality of second sub-data fan-out lines 52b.
  • the conductive connection structure includes a first connection electrode 62 and a second connection electrode 63 .
  • the semiconductor structure 61 is located on the side of the second sub-data fan-out lines 52a and 52b close to the base substrate 10, and the first connection structure 62 and the second connection structure 63 are located on a side of the second sub-data fan-out lines 52a and 52b away from the base substrate 10. side.
  • a second insulating layer 12 is provided between the semiconductor structure 61 and the first data fan-out line layer, a third insulating layer 13 is provided between the first data fan-out line layer and the second data fan-out line layer, and the second data fan-out line layer and
  • a fourth insulating layer 14 is disposed between the conductive connection structures.
  • the first via hole K1 is disposed on the fourth insulating layer 14 and exposes the surface of the semiconductor structure 61
  • the second via hole K2 and the third via hole K3 are disposed on the fourth insulating layer 14 and expose the first data fan
  • the fourth via hole K4 and the fifth via hole K5 are disposed on the fourth insulating layer 14 and expose the surface of the second data fan-out wiring layer.
  • the semiconductor structure realizes the jumper connection with the first data fan-out line layer and the second data fan-out line layer through the first connection electrode and the second connection electrode.
  • FIG. 6 is a schematic diagram of a resistance distribution curve of a data fan-out line of a display substrate before and after resistance compensation is performed according to at least one embodiment of the present disclosure.
  • the abscissa represents the sequence of multiple data fanout lines along the first direction D1 in the first frame area in FIG. 2 from the left edge to the right edge; the ordinate represents the resistance value in ohms.
  • the dotted line in FIG. 6 represents the resistance values of the plurality of data fan-out lines from the left edge to the right edge along the first direction D1 before the resistance compensation unit is not provided, and the solid line represents the resistance value of the plurality of data fan-out lines after the resistance compensation unit is provided. resistance.
  • the difference between the resistance values of the solid line and the dotted line corresponding to the abscissa position in FIG. 6 is the compensation resistance value provided by the resistance compensation unit connected in series with the data fan-out line corresponding to the abscissa position.
  • the data fan-out lines are arranged in the fan-out area through the fan-out routing method, and the display substrates currently have rounded corners, and multiple data fan-out lines are present.
  • the relative positions between the outgoing lines and the signal access area are different, so that the lengths of each data fanout line are different.
  • the lengths of the data fan-out lines located at the edges on both sides along the first direction D1 are longer, and the lengths decrease and then increase in the direction from the edge to the middle area.
  • the multiple data fan-out lines are usually made of the same conductive material (that is, the resistivity is the same) and are formed under the same or similar patterning process, so that the line widths and thicknesses of the multiple data fan-out lines are correspondingly equal (or very different). approach), so that the resistance values of the plurality of data fan-out lines increase with the increase of their lengths. Due to the length difference between different data fan-out lines, there is a large resistance difference between multiple data fan-out lines, and the greater the length difference between different data fan-out lines, the greater the resistance difference, resulting in the display of the display area. The screen appears color cast, uneven brightness (ie Mura) and other defects, affecting the display effect.
  • uneven brightness ie Mura
  • the connected data fan-out line will have a jump in length, resulting in a jump in resistance value, resulting in block display failure (Mura).
  • a column of sub-pixels is a boundary, and there is a significant difference in brightness on both sides of the boundary.
  • the first resistance trip point a in FIG. 6 is generated by the data fanout lines on both sides of the second bending region 221b in FIG. 2
  • the second resistance trip point b is the second bending point in FIG. 2 . It is generated by the data fanout lines on both sides of the folding area 221d.
  • the resistance values of the plurality of data fan-out lines in the first frame area may be substantially the same, thereby improving the display area due to the resistance of the data fan-out lines.
  • the display color shift or uneven brightness caused by the difference in resistance value improves the display effect.
  • the area of the semiconductor structure of the resistance compensation unit is proportional to the resistance value provided by the resistance compensation unit, that is, the larger the area of the semiconductor structure, the larger the compensated resistance value, and the smaller the area of the semiconductor structure. , the smaller the compensation resistance value is.
  • the compensation resistance value can be adjusted by adjusting the area of the semiconductor structure.
  • the resistance value of the semiconductor structure is about 4000 ⁇ /um ⁇ 2, which can compensate a sufficient resistance difference in a limited space, and realize resistance compensation at the kiloohm level in a narrow space.
  • the total area of the semiconductor structures of the resistance compensation units connected in series with the data fan-out lines with smaller resistance values is larger than the total area of the semiconductor structures of the resistance compensation units connected in series with the data fan-out lines with larger resistance values.
  • the second bending partition 221b due to the existence of the second bending partition 221b, there will be a length jump between the second sub-data fan-out lines 52b and 52a at the boundary of the second fan-out partitions 231 and 232 .
  • the length of the second sub-data fan-out line in the second fan-out partition 231 decreases from the edge of the second fan-out region 203 to the middle direction, and the length of the second sub-data fan-out line in the second fan-out partition 232 It also decreases from the edge of the second fan-out region 203 to the middle direction, but at the junction of the second fan-out regions 231 and 232, the length of the second sub-data fan-out line 52a in the second fan-out region 232 will be greater than the length of the second fan-out region 232.
  • a resistance compensation unit is connected in series with the second sub-data fan-out lines 52a and 52b respectively.
  • the area of the semiconductor structure 61 of the resistance compensation unit connected in series with the second sub-data fan-out line 52a is smaller than the area of the semiconductor structure 61 of the resistance compensation unit connected in series with the second sub-data fan-out line 52b.
  • the lengths of the plurality of semiconductor structures along the first direction D1 may be the same, and the area of the semiconductor structures can be changed by adjusting the lengths of the semiconductor structures along the second direction D2.
  • the length of the semiconductor structure along the second direction D2 may vary in the order of microns.
  • the length of the semiconductor structures in the second fan-out partition 231 connected in series with the plurality of second sub-data fan-out lines along the second direction D2 may be along the direction from the The direction from the edge to the middle of the second fan-out region 203 increases, and the length of the semiconductor structures connected in series by the plurality of second sub-data fan-out lines in the second fan-out region 232 along the second direction D2 may be along the length from the second fan-out region 232 The edge of the region 203 increases first and then decreases in the middle direction.
  • FIG. 7 is a schematic partial cross-sectional view along the P-P direction in FIG. 2 .
  • the structure of the display substrate of the present disclosure will be described below with reference to FIG. 7 through an example of a manufacturing process of the display substrate.
  • the "patterning process" referred to in the present disclosure includes processes such as depositing film layers, coating photoresist, mask exposure, developing, etching and stripping photoresist.
  • Deposition can be selected from any one or more of sputtering, evaporation and chemical vapor deposition
  • coating can be selected from any one or more of spray coating and spin coating
  • etching can be selected from dry etching. and any one or more of wet engraving.
  • “Film” refers to a thin film made of a material on a substrate by a deposition or coating process. If the “film” does not require a patterning process during the entire manufacturing process, the “film” can also be referred to as a "layer”. When the “film” needs a patterning process during the entire production process, it is called a “film” before the patterning process, and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • a and B are arranged in the same layer means that A and B are simultaneously formed through the same patterning process.
  • the same layer does not always mean that the thickness of the layer or the height of the layer is the same in the cross-sectional view.
  • the orthographic projection of A includes the orthographic projection of B means that the orthographic projection of B falls within the range of the orthographic projection of A, or the orthographic projection of A covers the orthographic projection of B.
  • the preparation process of the display substrate of this embodiment may include the following steps (1) to (8).
  • the base substrate 10 includes a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier.
  • the material of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or surface-treated soft polymer film.
  • the material of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the base substrate.
  • the first inorganic material layer and the second inorganic material layer are also called barrier layers.
  • As the material of the semiconductor layer amorphous silicon (a-si) can be used.
  • the preparation process of the base substrate may include: firstly coating a layer of polyimide on a glass carrier, curing to form a film, and then forming a first flexible (PI1) material layer; A barrier film is deposited on the flexible layer to form a first barrier (Barrier1) layer covering the first flexible material layer; then an amorphous silicon film is deposited on the first barrier layer to form an amorphous silicon covering the first barrier layer (a-si) layer; then a layer of polyimide is coated on the amorphous silicon layer, and a second flexible (PI2) material layer is formed after curing into a film; then a barrier layer is deposited on the second flexible material layer film to form a second barrier (Barrier 2 ) layer covering the second flexible layer to complete the preparation of the base substrate 10 .
  • both the display area and the first frame area include the base substrate 10 .
  • a first insulating film and a semiconductor layer film are sequentially deposited on the base substrate 10 , the semiconductor layer film is patterned through a patterning process to form a first insulating layer 11 covering the entire base substrate 10 , and An active layer and a semiconductor structure pattern disposed on the first insulating layer 11 .
  • the active layer pattern is formed in the display area 100 and includes at least the first active layer 21 .
  • the semiconductor structure pattern is formed in the second fan-out region 203 and includes at least the semiconductor structure 61 .
  • a second insulating film and a first metal film are sequentially deposited on the base substrate 10 on which the above structure is formed, and the first metal film is patterned through a patterning process to form a covering active layer and a semiconductor structure
  • the patterned second insulating layer 12 , and the first gate metal layer pattern and the first data fan-out line layer pattern disposed on the second insulating layer 12 .
  • the first gate metal layer pattern is formed in the display area 100 and includes at least a first gate electrode 22 , a first capacitor electrode 25 and a plurality of gate lines (not shown).
  • the first data fan-out line layer pattern is formed in the fan-out area and includes at least a plurality of first data fan-out lines.
  • the first data fan-out line includes: a first sub-data fan-out line located in the first fan-out area, and a second sub-data fan-out line located in the second fan-out area and electrically connected to the first sub-data fan-out line at the same layer (for example, The second sub-data fan-out line 52a shown in FIG. 3, the second sub-data fan-out line 52a includes a disconnected first part 521a and a second part 522a), and is located in the third fan-out area and is in the same layer as the second sub-data fan The third sub-data fanout line that is electrically connected to the outgoing line.
  • the first sub-data fan-out line is configured to be electrically connected to a data line formed subsequently in the display area 100 .
  • the first sub-data fan-out line and the second sub-data fan-out line are configured to be electrically connected by data connection lines formed subsequently by the bending region.
  • a third insulating film and a second metal film are sequentially deposited on the base substrate 10 forming the above structure, and the second metal film is patterned through a patterning process to form a pattern covering the first gate metal layer , a first data fan-out line layer pattern and a third insulating layer 13 of the second insulating layer 12 , and a second gate metal layer pattern and a second data fan-out line layer pattern disposed on the third insulating layer 13 .
  • the second gate metal layer pattern is formed in the display area 100 and includes at least the second capacitor electrode 26 .
  • the second data fan-out line layer pattern is formed in the fan-out area and includes at least a plurality of second data fan-out lines.
  • the second data fan-out line includes: a first sub-data fan-out line located in the first fan-out area, a second sub-data fan-out line located in the second fan-out area and electrically connected to the first sub-data fan-out line at the same layer (for example, The second sub-data fan-out line 52b) shown in FIG. 3 is a third sub-data fan-out line located in the third fan-out region and electrically connected to the second sub-data fan-out line of the same layer.
  • the first sub-data fan-out lines of the second data fan-out line layer are configured to be electrically connected to data lines formed subsequently in the display area 100 .
  • the first sub-data fan-out line and the second sub-data fan-out line at the same layer are configured to be electrically connected through data connection lines formed subsequently in the bending region.
  • a fourth insulating film is deposited on the base substrate 10 on which the above structure is formed, and the fourth insulating film is patterned through a patterning process to form a layer covering the second gate metal layer and the second data fan-out line
  • the patterned fourth insulating layer 14 is patterned.
  • a plurality of first via holes K1 , a plurality of second via holes K2 , a plurality of third via holes K3 , a plurality of fourth via holes K4 and a plurality of fifth via holes K5 are located in the second fan-out region 203 .
  • the plurality of first vias K1 expose the surface of the semiconductor structure 61
  • the plurality of second vias K2 and the third vias K3 expose the surface of the second sub-data fan-out line located in the first data fan-out line layer
  • the plurality of The fourth via hole K4 and the plurality of fifth via holes K5 expose the surfaces of the second sub-data fan-out lines located in the second data fan-out line layer.
  • a plurality of sixth via holes are located in the display area 100 and expose the surface of the first active layer 21 .
  • a first mask etching (Etch Bending A MASK, EBA MASK for short) and a second mask etching (Etch Bending B MASK for short) are performed.
  • EBB MASK grooving the bending area to reduce the thickness of the bending area and improve the bending effect.
  • a third metal thin film is deposited on the base substrate 10 forming the above structure, the third metal thin film is patterned through a patterning process, and a source-drain metal layer pattern, Conductive connection structure, data connection line and power connection line pattern.
  • a source-drain metal layer pattern is formed in the display area 100, and includes at least a first source electrode 23, a first drain electrode 24, a plurality of data lines (not shown), and power lines (eg, VDD and VSS) pattern.
  • the first source electrode 23 and the first drain electrode 24 are respectively connected to the first active layer 21 through sixth via holes.
  • the conductive connection structure pattern is formed in the second fan-out region 203 and includes at least the first connection electrode 62 and the second connection electrode 63 .
  • One end of the first connection electrode 62 is connected to the first part 521a of the second sub-data fan-out line 52a through two second vias K2, and the other end of the first connection electrode 62 is connected to the semiconductor structure 61 through the two first vias K1 .
  • One end of the second connection electrode 63 is connected to the second portion 522a of the second sub-data fan-out line 52a through two third vias K3, and the other end of the second connection electrode 63 is connected to the semiconductor structure 61 through the two first vias K1 connect.
  • the data connecting line and the power connecting line are formed in the bending area, and the power connecting line is arranged in the middle of the data connecting line. Both ends of the at least one data connection line are respectively connected to the first sub-data fan-out line and the second sub-data fan-out line of the first data fan-out line layer, or are respectively connected to the first sub-data fan-out line and the second sub-data fan-out line of the second data fan-out line layer. Two sub-data fanout lines are connected.
  • the driving structure layer of the display area 100 is prepared on the base substrate 10 , as shown in FIG. 7 .
  • the first active layer 21 , the first gate electrode 22 , the first source electrode 23 and the first drain electrode 24 form a first transistor
  • the first capacitor electrode 25 and the second capacitor electrode 26 form a first transistor. the first storage capacitor.
  • the first insulating layer 11 may also be called a buffer layer
  • the second insulating layer 12 and the third insulating layer 13 may also be called a gate insulating layer
  • the fourth insulating layer 14 may also be called an interlayer Insulation.
  • the first insulating layer 11, the second insulating layer 12, the third insulating layer 13 and the fourth insulating layer 14 may be any one of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON) or more, it may be a single layer, multiple layers or composite layers.
  • the first insulating layer 11 can be used to improve the water and oxygen resistance of the base substrate 10 .
  • the first metal thin film, the second metal thin film and the third metal thin film can be made of metal materials, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo) or More, or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti and the like.
  • metal materials such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo) or More, or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the semiconductor layer film can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), One or more materials such as hexathiophene and polythiophene, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic matter technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • One or more materials such as hexathiophene and polythiophene, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic matter technology.
  • a fifth insulating film is deposited on the base substrate 10 on which the above structure is formed, and a fifth insulating layer 15 is formed through a patterning process. Then, a flat thin film is coated on the base substrate 10 having the above structure to form a flat layer 16 covering the entire base substrate 10 , and seventh via holes are formed in the flat layer 16 through a patterning process. A plurality of seventh via holes are formed in the display area 100 , and the flat layer 16 and the fifth insulating layer 15 in any seventh via hole are etched away to expose the surface of the first drain electrode 24 of the first transistor.
  • an anode, a pixel definition layer, a spacer column, an organic light-emitting layer, a cathode and an encapsulation layer are sequentially prepared on the base substrate.
  • a transparent conductive film is deposited on the base substrate 10 forming the aforementioned structure, and the transparent conductive film is patterned through a patterning process to form a pattern of the anode 31 .
  • the anode 31 is patterned on the flat layer 16 of the display area 100 and connected to the first drain electrode 24 through the seventh via hole.
  • a pixel definition film is coated on the base substrate 10 on which the aforementioned structure is formed, and a pixel definition layer (PDL, Pixel Definition Layer) 34 pattern is formed by masking, exposing, and developing processes.
  • PDL Pixel Definition Layer
  • the pixel definition layer 34 is formed in the display area 100 and the second fan-out area 203 .
  • a pixel opening is formed on the pixel defining layer 34 of the display area 100 , and the pixel defining film in the pixel opening is developed to expose the surface of the anode 31 .
  • a thin film of organic material is coated on the base substrate 10 on which the aforementioned patterns are formed, and a pattern of isolation pillar (PS) layers 41 is formed in the display area 100 through masking, exposing and developing processes.
  • the isolation pillar layer 41 of the display area 100 includes a plurality of isolation pillars.
  • the organic light-emitting layer 32 and the cathode 33 are sequentially formed on the base substrate 10 on which the aforementioned patterns are formed.
  • the organic light-emitting layer 32 includes a stacked hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer and an electron injection layer, and is formed in the pixel opening of the display area 100 to realize the organic light-emitting layer 32 Connected to anode 31 . Since the anode 31 is connected to the first drain electrode 24 of the first transistor, the light emission control of the organic light emitting layer 32 is realized. A part of the cathode 33 is formed on the organic light emitting layer 32 . After this patterning process, the film structure of the second fan-out region 203 does not change.
  • an encapsulation layer 42 is formed on the base substrate 10 on which the aforementioned patterns are formed. As shown in FIG. 7 , the encapsulation layer 42 is formed on the display area 100 , and a laminated structure of inorganic material/organic material/inorganic material may be adopted. The organic material layer is disposed between the two inorganic material layers. After this patterning process, the film structure of the second fan-out region 203 does not change.
  • the planarization layer 16 , the pixel definition layer 34 and the isolation pillar layer 41 may adopt organic materials such as polyimide, acrylic or polyethylene terephthalate.
  • the display substrate can be peeled off from the glass carrier through a peeling process.
  • the preparation process of the test circuit in the test circuit area is similar to the preparation process of the driving structure layer in the display area, so it will not be repeated here.
  • a plurality of resistance compensation units are arranged in the second fan-out area, and the resistance compensation units are connected in series with the second sub-data fan-out lines, so as to compensate the resistance of the data fan-out lines in the entire fan-out area value, reducing the resistance value difference between different data fan-out lines that provide data signals to different data lines in the display area, thereby improving the display effect.
  • the preparation process of the present exemplary embodiment can be realized by using the existing mature preparation equipment, and can be well compatible with the existing preparation process.
  • the process is simple to implement, easy to implement, high in production efficiency, low in production cost and high in yield.
  • the structure of the display substrate of the present exemplary embodiment and the manufacturing process thereof are merely an exemplary illustration. In some exemplary embodiments, corresponding structures may be changed and patterning processes may be increased or decreased according to actual needs.
  • a plurality of resistance compensation units may all be arranged in the first fan-out area, and the plurality of resistance compensation units may be electrically connected to a plurality of first sub-data fan-out lines in a one-to-one correspondence; or, a plurality of resistance compensation units may be arranged in the first fan-out area.
  • Three fan-out regions and can be electrically connected to a plurality of third sub-data fan-out lines in one-to-one correspondence; alternatively, a part of the resistance compensation unit is disposed in the first fan-out region, connected in series with the first sub-data fan-out lines and electrically connected, and the other part
  • the resistance compensation unit is arranged in the second fan-out area, and is connected in series with the second sub-data fan-out line and is electrically connected;
  • a part of the resistance compensation unit is disposed in the third fan-out region, and is connected in series with and electrically connected to the third sub-data fan-out line.
  • each resistance compensation unit is the same, and the number of the resistance compensation units connected in series can be determined according to the resistance value to be compensated for each data fan-out line.
  • a plurality of data fan-out lines may be arranged in the same layer.
  • the plurality of data fan-out lines may be in the same layer structure as the first gate metal layer of the display area, or in the same layer structure as the second gate metal layer.
  • this embodiment does not limit this.
  • FIG. 8 is another schematic cross-sectional view along the P-P direction in FIG. 2 .
  • the display area 100 in a plane perpendicular to the display substrate, the display area 100 includes: a driving structure layer disposed on the base substrate 10 , a light emitting structure layer disposed on the driving structure layer .
  • the driving structure layer includes: a first insulating layer 11 , an active layer (eg, including the first active layer 21 ), a second insulating layer 12 , and a first gate metal layer (eg, including The first gate electrode 22 and the first capacitor electrode 25), the third insulating layer 13, the second gate metal layer (for example, including the second capacitor electrode 26), the fourth insulating layer 14, the first source-drain metal layer (for example, including the first source-drain metal layer).
  • the semiconductor structure 61 of the resistance compensation unit disposed in the second fan-out area 203 is of the same layer structure as the active layer of the display area 100 , and the conductive connection structure of the resistance compensation unit (for example, including the first connection electrode 62 and the second connection electrode 63 ) It has the same layer structure as the second source-drain metal layer of the display area 100 .
  • the conductive connection structure of the resistance compensation unit may be the same layer structure as the first source-drain metal layer of the display area.
  • FIG. 9 is another partial enlarged schematic diagram of the area S in FIG. 2 .
  • the plurality of second sub-data fan-out lines 52a and the plurality of second sub-data fan-out lines 52b in the second fan-out region are disposed at different layers.
  • the second sub-data fan-out line 52a and the first gate metal layer in the display area are in the same layer structure
  • the second sub-data fan-out line 52b and the second gate metal layer in the display area are in the same layer structure.
  • the plurality of second sub-data fan-out lines in the second fan-out region are connected in series with the plurality of resistance compensation units in one-to-one correspondence, and the plurality of resistance compensation units are sequentially arranged along the first direction D1.
  • the second sub-data fanout line 52a includes a disconnected first portion 521a and a second portion 521b.
  • the first portion 521a of the second sub-data fan-out line 52a has a first end portion 5210 and a first extension portion 5211
  • the second portion 522a of the second sub-data fan-out line 52a has a second end portion 5220 and a second extension portion 5221.
  • One end of the first connection electrode 62 of the resistance compensation unit is connected to the first end 5210 through four via holes, and the other end of the first connection electrode 62 is connected to the semiconductor structure 61 through four via holes; one end of the second connection electrode 63 It is connected to the second end portion 5220 through four via holes, and the other end of the second connection electrode 63 is connected to the semiconductor structure 61 through four via holes.
  • the length of the first end portion 5210 along the first direction D1 is greater than the length of the first extension portion 5211 along the first direction D1
  • the length of the second end portion 5220 along the first direction D1 is greater than the length of the second extension portion 5221 along the first direction
  • the length of the first end portion 5210 along the first direction D1 may be approximately equal to the length of the second end portion 5220 along the first direction D1. However, this embodiment does not limit this.
  • the length of the first connection electrode 62 along the first direction D1 is approximately equal to the length of the first end portion 5210 along the first direction D1, and the second connection electrode 63 along the first direction
  • the length of D1 is approximately equal to the length of the second end portion 5220 along the first direction D1.
  • the length of the first connection electrode 62 along the first direction D1 is approximately equal to the length of the second electrode 63 along the first direction D1.
  • the semiconductor structure 61 is, for example, a rectangle, and the length of the semiconductor structure 61 along the first direction D1 may be approximately equal to the length of the first connection electrode 62 along the first direction D1. However, this embodiment does not limit this.
  • the lengths of the plurality of semiconductor structures 61 along the first direction D1 may be the same, and the lengths along the second direction D2 may vary, so that the areas of the plurality of semiconductor structures 61 are different, so as to Compensate for different resistance values for the corresponding data fanout lines.
  • the lengths of the plurality of semiconductor structures 61 in the second direction D2 vary in the order of micrometers. For example, in the second fan-out region 231 of the second fan-out region 203 shown in FIG.
  • the lengths of the plurality of semiconductor structures along the first direction are the same , the lengths along the second direction can be sequentially increased, for example, 3.04 microns, 3.11 microns, 3.18 microns, etc. in sequence.
  • the plurality of resistance compensation units in the second fan-out area are close to the test circuit area. That is, the distance between the plurality of resistance compensation units and the test circuit area is smaller than the distance from the bending area.
  • the second extension portions of the second portions of the plurality of second sub-data fan-out lines have the same extension length and are sequentially arranged along the first direction. The extension length of the first extension part of the first part of the plurality of second sub-data fan-out lines is greater than the extension length of the second extension part of the second part. In the present disclosure, the extension length refers to the characteristic dimension along the extension direction.
  • the first end portion and the second end portion at the first portion and the second portion of the second sub-data fan-out line, respectively, it is possible to avoid increasing the overall line width of the second sub-data fan-out line.
  • the contact area between the second sub-data fan-out line and the conductive connection structure of the resistance compensation unit is increased, thereby improving the effectiveness of the electrical connection between the second sub-data fan-out line and the resistance compensation unit.
  • FIG. 10 is another partial enlarged schematic diagram of the area S in FIG. 2 .
  • the plurality of second sub-data fan-out lines 52a and the plurality of second sub-data fan-out lines 52b in the second fan-out region are disposed in different layers.
  • the plurality of second sub-data fan-out lines in the second fan-out region are connected in series with the plurality of resistance compensation units in one-to-one correspondence.
  • the plurality of resistance compensation units 60 in each second fan-out partition are staggered along the second direction D2. For example, the distances between the plurality of resistance compensation units in the second fan-out subregion 231 of the second fan-out region 203 shown in FIG.
  • the test circuit region 2 and the test circuit region may be along the first direction D1 from the edge of the second fan-out region Descending to the middle direction; the distances between the plurality of resistance compensation units in the second fan-out region 232 and the test circuit region may increase along the first direction D1 from the edge of the second fan-out region to the middle direction.
  • this embodiment does not limit this.
  • FIG. 11 is another schematic diagram of the first frame region of at least one embodiment of the disclosure.
  • the first frame area 200 includes: a first fan-out area 201 located on one side of the display area 100 , a curved edge located on a side of the first fan-out area 201 away from the display area 100 .
  • the first fan-out region 201 includes two first fan-out partitions 211 and 212 .
  • a plurality of first sub-data fan-out lines are set in each first fan-out partition. The lengths of the plurality of first sub-data fan-out lines in each first fan-out partition first decrease and then increase along the direction from the edge to the middle of the first fan-out region 201 .
  • the bending region 202 includes a plurality of first bending sections (for example, two first bending sections 220a and 220b arranged in sequence along the first direction D1), a plurality of second bending sections (for example, along the first direction D1)
  • the three second bending zones 221a, 221b and 221c are arranged in sequence in the direction D1).
  • At least one second bending subsection is disposed between two adjacent first bending subsections.
  • a plurality of data connection lines are arranged in each first bending subsection, and power supply connection lines are arranged in each second bending subsection.
  • the second bending section 221b is located between the first bending sections 220a and 220b.
  • the second fan-out region 203 includes two second fan-out partitions 231 and 232 .
  • a plurality of second sub-data fan-out lines are set in each second fan-out partition.
  • the lengths of the plurality of second sub-data fan-out lines in each second fan-out partition decrease and then increase along the direction from the edge to the middle of the second fan-out region 203 .
  • the third fan-out region 205 includes two third fan-out partitions 251 and 252 .
  • a plurality of third sub-data fan-out lines are set in each third fan-out partition.
  • the lengths of the plurality of third sub-data fan-out lines in each third fan-out partition decrease and then increase along the direction from the edge to the middle of the third fan-out region 205 .
  • this embodiment does not limit this.
  • the lengths of the plurality of first sub-data fan-out lines in each first fan-out partition may decrease along the direction from the edge of the first fan-out region to the middle, and the lengths of the plurality of second sub-data fan-out lines in each second fan-out partition
  • the length of the sub-data fan-out lines may decrease along the direction from the edge of the second fan-out area to the middle. The edge to the middle direction can decrease.
  • the multiple resistance compensation units when multiple resistance compensation units are disposed in the second fan-out area 203 , and the multiple resistance compensation units are connected in series with the multiple second sub-data fan-out lines in the second fan-out area 203 in one-to-one correspondence
  • the area of the semiconductor structures of the plurality of resistance compensation units in each second fan-out region may first increase and then decrease along the direction from the edge of the second fan-out region 203 to the middle, so as to compensate for the size of the fan-out region.
  • the resistance value difference between multiple data fan-out lines can improve the display color shift or brightness unevenness caused by the resistance value difference of the data fan-out lines, thereby improving the display effect.
  • the area of may increase along the direction from the edge of the second fan-out region to the middle.
  • the structures of the display area and the first frame area and the structures of the resistance compensation unit in the present exemplary embodiment are similar to the corresponding structures described in the foregoing embodiments, and thus are not repeated here.
  • FIG. 12 is another schematic diagram of the first frame area of at least one embodiment of the disclosure.
  • the first frame area 200 includes: a first fan-out area 201 located on one side of the display area 100 , a curved edge located on a side of the first fan-out area 201 away from the display area 100 .
  • the power connection absorption in the bending area 202 is arranged on the same layer as the data connection lines, and the power connection lines in the bending area 202 are located on both sides of the plurality of data connection lines .
  • the plurality of data connection lines can be respectively connected to the first sub-data fan-out line and the first sub-data fan-out line of the first fan-out region 201 in sequence.
  • the length of the data fan-out line in the fan-out area does not jump.
  • the lengths of the data fan-out lines in the first fan-out area 201, the second fan-out area 203 and the third fan-out area 205 decrease in the direction from the edge to the middle.
  • the areas of the semiconductor structures of the plurality of resistance compensation units can be increased along the direction from the two side edges of the second fan-out region 203 to the middle, so as to compensate for the resistance value difference between the plurality of data fan-out lines in the fan-out region, and improve the performance of the data
  • the display color shift or brightness unevenness caused by the difference in the resistance value of the fan-out line improves the display effect.
  • a plurality of resistance compensation units are disposed in the second fan-out region 203, and the plurality of resistance compensation units are connected in series with a plurality of second sub-data fan-out lines in the second fan-out region in a one-to-one correspondence.
  • the second sub-data fan-out line within the second fan-out region may include the disconnected first portion and the second portion.
  • the resistance compensation unit may include a semiconductor structure and a conductive connection structure.
  • the conductive connection structure includes a first connection electrode and a second connection electrode.
  • the first connection electrode connects the first part of the second sub-data fan-out line and one end of the semiconductor structure
  • the second connection electrode connects the second part of the second sub-data fan-out line and the other end of the semiconductor structure, so as to realize the resistance compensation unit and the second Series electrical connection of sub-data fanout lines.
  • the plurality of resistance compensation units may be sequentially arranged along the first direction D1, the semiconductor structures of the plurality of resistance compensation units may have the same length along the first direction D1, and may have the same length along the second direction D2 It increases from the two side edges of the second fan-out region to the middle direction, so that the areas of the semiconductor structures of the plurality of resistance compensation units can increase along the direction from the two side edges to the middle direction of the second fan-out region.
  • this embodiment does not limit this.
  • the structures of the display area and the first frame area and the structures of the resistance compensation unit in the present exemplary embodiment are similar to the corresponding structures described in the foregoing embodiments, and thus are not repeated here.
  • FIG. 13 is another schematic diagram of the first frame area of at least one embodiment of the disclosure.
  • the first frame area 200 includes: a fan-out area 400 on one side of the display area 100 and a signal access area on the side of the fan-out area 400 away from the display area 100 206.
  • the fan-out area 400 is provided with a plurality of data fan-out lines, and the lengths of the plurality of data fan-out lines decrease in a direction from the two edges of the fan-out area 400 to the middle.
  • the semiconductors of the plurality of resistance compensation units can be increased along the direction from both sides of the fan-out region 400 to the middle in the first direction D1, so as to compensate for the resistance value difference between the multiple data fan-out lines in the fan-out region, and improve the resistance value of the data fan-out lines due to the The display color shift or brightness unevenness caused by the difference in resistance value improves the display effect.
  • the structures of the display area and the first frame area and the structures of the resistance compensation unit in the present exemplary embodiment are similar to the corresponding structures described in the foregoing embodiments, and thus are not repeated here.
  • FIG. 14 is another schematic diagram of the first frame region of at least one embodiment of the disclosure.
  • the first frame area 200 includes: a first fan-out area 201 located on one side of the display area 100 , and a curved edge located on a side of the first fan-out area 201 away from the display area 100 .
  • the fan-out area includes a first fan-out area 201 and a second fan-out area 203 .
  • the second fan-out area 203 is provided with a plurality of second sub-data fan-out lines, and the lengths of the plurality of second sub-data fan-out lines decrease along the direction from the two side edges of the second fan-out area 203 to the middle.
  • the area of the semiconductor structure of the plurality of resistance compensation units can be increased along the direction from the two side edges of the second fan-out region 203 to the middle, so as to compensate the resistance value difference between the plurality of data fan-out lines in the fan-out region and improve the Display color shift or uneven brightness caused by the resistance value difference of the data fan-out lines, thereby improving the display effect.
  • the structures of the display area and the first frame area and the structures of the resistance compensation unit in the present exemplary embodiment are similar to the corresponding structures described in the foregoing embodiments, and thus are not repeated here.
  • FIG. 15 is a schematic diagram of a display device according to at least one embodiment of the disclosure.
  • this embodiment provides a display device 91 including: a display substrate 910.
  • the display substrate 910 is the display substrate provided in the foregoing embodiments.
  • the display substrate 910 may be an OLED display substrate.
  • the display device 91 may be: an OLED display device, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • this embodiment does not limit this.

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Abstract

一种显示基板（910），包括：衬底基板（10）、多个子像素（1001）、多条数据线（1002）、多个信号输入垫、数据扇出线层、以及多个电阻补偿单元（60）。衬底基板（10）包括显示区域（100）和位于显示区域（100）周边的边框区域（200、 300），边框区域（200、 300）包括：位于显示区域（100）一侧的信号接入区域（206）、以及位于显示区域（100）和信号接入区域（206）之间的扇出区域（201、 203、 205、 400）。数据扇出线层和多个电阻补偿单元（60）设置在扇出区域（201、 203、 205、 400）。数据扇出线层包括多条数据扇出线。至少一个电阻补偿单元（60）包括：半导体结构（61）。至少一条数据扇出线与至少一个电阻补偿单元（60）串联且电连接。

Description

显示基板及显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及显示装置。
背景技术
随着显示技术的不断发展，显示产品的种类越来越多，例如，液晶显示器(LCD，Liquid Crystal Display)、有机发光二极管(OLED，Organic Light-Emitting Diode)显示器、等离子体显示面板(PDP，Plasma Display Panel)、场发射显示器(FED，Field Emission Display)等。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种显示基板及显示装置。
一方面，本公开实施例提供一种显示基板，包括：衬底基板、多个子像素、多条数据线、多个信号输入垫、数据扇出线层、以及多个电阻补偿单元。衬底基板包括显示区域和位于所述显示区域周边的边框区域。所述边框区域包括：位于所述显示区域一侧的信号接入区域、以及位于所述显示区域和所述信号接入区域之间的扇出区域。多个子像素，位于所述显示区域。多条数据线，位于所述显示区域且与所述多个子像素电连接，所述多条数据线被配置为向所述多个子像素提供数据信号。多个信号输入垫，位于所述信号接入区域。数据扇出线层和多个电阻补偿单元设置在所述扇出区域。所述数据扇出线层包括：多条数据扇出线，所述多条数据扇出线被配置为连接所述多条数据线和信号接入区域内设置的多个信号输入垫。多个电阻补偿单元中的至少一个包括半导体结构。多条数据扇出线中的至少一条与至少一个电阻补偿单元串联且电连接。
在一些示例性实施方式中，所述电阻补偿单元的半导体结构的面积与所 述电阻补偿单元串联的数据扇出线需补偿的电阻值呈正比关系。
在一些示例性实施方式中，电阻值较小的数据扇出线所串联的电阻补偿单元的半导体结构的总面积大于电阻值较大的数据扇出线所串联的电阻补偿单元的半导体结构的总面积。
在一些示例性实施方式中，所述多个电阻补偿单元中的至少一个还包括导电连接结构，所述半导体结构和所述导电连接结构依次设置在所述衬底基板上，且所述半导体结构和所述导电连接结构电连接。
在一些示例性实施方式中，所述电阻补偿单元的导电连接结构包括：第一连接电极和第二连接电极。与所述电阻补偿单元串联连接的数据扇出线包括断开的第一部分和第二部分。所述数据扇出线的第一部分通过所述第一连接电极与所述电阻补偿单元的半导体结构连接，所述数据扇出线的第二部分通过所述第二连接电极与所述半导体结构连接。
在一些示例性实施方式中，所述第一部分具有相互连接的第一端部和第一延伸部，所述第二部分具有相互连接的第二端部和第二延伸部。所述第一端部通过所述第一连接电极与所述半导体结构连接，所述第二端部通过所述第二连接电极与所述半导体结构连接。所述第一端部沿第一方向的长度大于所述第一延伸部沿第一方向的长度，所述第二端部沿第一方向的长度所述第二延伸部沿第一方向的长度。所述第一方向垂直于所述显示区域的数据线的延伸方向。
在一些示例性实施方式中，所述扇出区域内的多条数据扇出线与多个电阻补偿单元一一对应串联且电连接。
在一些示例性实施方式中，所述多个电阻补偿单元沿着垂直于所述显示区域的数据线的延伸方向的方向依次排布，或者，沿着平行于所述显示区域的数据线的延伸方向的方向错开排布。
在一些示例性实施方式中，沿着从所述扇出区域的边缘到中间的方向上，所述扇出区域内的多条数据扇出线电连接的电阻补偿单元的半导体结构的总面积递增，或者，先递增后递减。
在一些示例性实施方式中，所述扇出区域在垂直于所述显示区域的数据 线的延伸方向的方向上具有多个扇出分。至少一个扇出分区内的多条数据扇出线电连接的电阻补偿单元沿着垂直于所述显示区域的数据线的延伸方向的方向依次排布，或者，沿着平行于所述显示区域的数据线的延伸方向的方向错开排布。
在一些示例性实施方式中，沿着从所述扇出区域的边缘到中间的方向上，至少一个扇出分区内的多条数据扇出线电连接的电阻补偿单元的半导体结构的总面积递增，或者，先递增后递减。
在一些示例性实施方式中，所述半导体结构位于所述数据扇出线层靠近所述衬底基板的一侧，所述导电连接结构位于所述数据扇出线层远离所述衬底基板的一侧。
在一些示例性实施方式中，所述边框区域还包括：位于所述信号接入区域和所述显示区域之间的弯折区域。所述扇出区域包括：位于所述显示区域和弯折区域之间的第一扇出区域、位于所述弯折区域和所述信号接入区域之间的第二扇出区域。所述至少一条数据扇出线包括：位于第一扇出区域的第一子数据扇出线、以及位于第二扇出区域且与所述第一子数据扇出线连接的第二子数据扇出线。所述至少一个电阻补偿单元被配置为满足以下之一：设置在所述第一扇出区域且与至少一条第一子数据扇出线串联且电连接；设置在所述第二扇出区域且与至少一条第二子数据扇出线串联且电连接。
在一些示例性实施方式中，所述边框区域还包括：位于所述信号接入区域和所述显示区域之间的弯折区域、位于所述弯折区域和信号接入区域之间的测试电路区域。所述扇出区域包括：位于所述显示区域和弯折区域之间的第一扇出区域、位于所述弯折区域和所述测试电路区域之间的第二扇出区域、以及位于所述测试电路区域和所述信号接入区域之间的第三扇出区域。所述至少一条数据扇出线包括：位于第一扇出区域的第一子数据扇出线、位于第二扇出区域且与所述第一子数据扇出线电连接的第二子数据扇出线、以及位于第三扇出区域且与所述第二子数据扇出线电连接的第三子数据扇出线。所述至少一个电阻补偿单元被配置为满足以下之一：设置在所述第一扇出区域且与至少一条第一子数据扇出线串联且电连接；设置在所述第二扇出区域且与至少一条第二子数据扇出线串联且电连接；设置在所述第三扇出区域且与 至少一条第三子数据扇出线串联且电连接。
在一些示例性实施方式中，所述多个电阻补偿单元均设置在所述第二扇出区域，且所述第二扇出区域内的至少一条第二子数据扇出线与至少一个电阻补偿单元串联且电连接。
在一些示例性实施方式中，设置在所述第二扇出区域内的所述多个电阻补偿单元靠近测试电路区域或靠近所述信号接入区域。
在一些示例性实施方式中，所述数据扇出线层包括：依次设置在所述衬底基板上且相互绝缘的第一数据扇出线层和第二数据扇出线层。所述第一数据扇出线层包括多条第一数据扇出线，所述第二数据扇出线层包括多条第二数据扇出线。所述第一数据扇出线层和所述第二数据扇出线层在所述衬底基板上的正投影没有交叠，且所述多条第一数据扇出线和多条第二数据扇出线间隔排布。
在一些示例性实施方式中，所述显示区域至少包括：设置在所述衬底基板上的驱动结构层、设置在所述驱动结构层上的发光元件；所述发光元件与驱动结构层电连接。所述驱动结构层包括：依次设置在所述衬底基板上的有源层、第一栅金属层、第二栅金属层以及源漏金属层。所述第一数据扇出层与所述第一栅金属层为同层结构，所述第二数据扇出层与所述第二栅金属层为同层结构；所述半导体结构与所述有源层为同层结构；所述导电连接结构与所述源漏金属层为同层结构。
另一方面，本公开实施例提供一种显示装置，包括如上所述的显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开至少一实施例的显示基板的示意图；
图2为本公开至少一实施例的第一边框区域的一种示意图；
图3为图2中区域S的局部放大示意图；
图4为图3中沿A-A方向的剖面示意图；
图5为图3中沿B-B方向的剖面示意图；
图6为本公开至少一实施例的显示基板的数据扇出线进行电阻补偿前后的电阻分布曲线示意图；
图7为图2中沿P-P方向的一种剖面示意图；
图8为图2中沿P-P方向的另一剖面示意图；
图9为图2中区域S的另一局部放大示意图；
图10为图2中区域S的另一局部放大示意图；
图11为本公开至少一实施例的显示基板的第一边框区域的另一示意图；
图12为本公开至少一实施例的显示基板的第一边框区域的另一示意图；
图13为本公开至少一实施例的显示基板的第一边框区域的另一示意图；
图14为本公开至少一实施例的显示基板的第一边框区域的另一示意图；
图15为本公开至少一实施例的显示装置的示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为一种或多种形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本公开中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个或两个以上的数量。
在本公开中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本公开中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本公开中，沟道区域是指电流主要流过的区域。
在本公开中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本公开中，“源电极”和“漏电极”可以互相调换。
在本公开中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有一种或多种功能的元件等。
在本公开中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状 态，因此，可以包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，可以包括85°以上且95°以下的角度的状态。
在本公开中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
本公开实施例提供一种显示基板，包括：衬底基板、多个子像素、多条数据线、多个信号输入垫、数据扇出线层、以及多个电阻补偿单元。衬底基板包括显示区域和位于显示区域周边的边框区域。边框区域包括：位于显示区域一侧的信号接入区域、以及位于显示区域和信号接入区域之间的扇出区域。多个子像素位于显示区域。多条数据线位于显示区域且与多个子像素电连接，多条数据线被配置为向多个子像素提供数据信号。多个信号输入垫位于信号接入区域。数据扇出线层和多个电阻补偿单元设置在扇出区域。数据扇出线层包括多条数据扇出线，多条数据扇出线被配置为连接多条数据线和信号接入区域内设置的多个信号输入垫。至少一个电阻补偿单元包括半导体结构。至少一条数据扇出线与至少一个电阻补偿单元串联且电连接。例如，一条数据扇出线与一个电阻补偿单元串联且电连接，或者，一条数据扇出线与多个电阻补偿单元串联且电连接。然而，本实施例对此并不限定。
本公开实施例提供的显示基板，通过在扇出区域设置多个电阻补偿单元，对多条数据扇出线的电阻值进行补偿，减少补偿后的多条数据扇出线之间的电阻值差异，改善由于数据扇出线的电阻值差异引起的显示色偏或亮度不均的情况，从而提升显示效果。
在一些示例性实施方式中，本实施例的显示基板可以为液晶显示器(LCD，Liquid Crystal Display)、有机发光二极管(OLED，Organic Light-Emitting Diode)显示器、等离子体显示面板(PDP，Plasma Display Panel)、或者，场发射显示器(FED，Field Emission Display)。然而，本实施例对于显示基板的类型并不限定。
在一些示例性实施方式中，电阻补偿单元的半导体结构的面积与电阻补 偿单元串联的数据扇出线需补偿的电阻值呈正比关系。换言之，电阻补偿单元的半导体结构的面积越大，电阻补偿单元提供的补偿电阻值越大；电阻补偿单元的半导体结构的面积越小，电阻补偿单元提供的补偿电阻值越小。
在一些示例性实施方式中，电阻值较小的数据扇出线所串联的电阻补偿单元的半导体结构的总面积大于电阻值较大的数据扇出线所串联的电阻补偿单元的半导体结构的总面积。在本示例性实施方式中，通过调整数据扇出线所串联的电阻补偿单元的半导体结构的面积，可以给不同数据扇出线提供不同的补偿电阻值，从而补偿不同数据扇出线之间的电阻值差异。
在一些示例性实施方式中，多个电阻补偿单元中的至少一个还包括导电连接结构。半导体结构和导电连接结构依次设置在衬底基板上，且半导体结构和导电连接结构电连接。在本示例性实施方式中，通过导电连接结构实现数据扇出线与半导体结构之间的电连接。
在一些示例性实施方式中，电阻补偿单元的导电连接结构包括：第一连接电极和第二连接电极。与电阻补偿单元串联连接的数据扇出线包括断开的第一部分和第二部分。数据扇出线的第一部分通过电阻补偿单元的第一连接电极与半导体结构连接，数据扇出线的第二部分通过电阻补偿单元的第二连接电极与半导体结构连接。在本示例性实施方式中，通过导电连接结构可以实现半导体结构和数据扇出线之间的串联连接。
在一些示例性实施方式中，扇出区域内的多条数据扇出线与多个电阻补偿单元一一对应串联连接。换言之，一条数据扇出线与一个电阻补偿单元串联连接。其中，多个电阻补偿单元的半导体结构的面积可以不同或者部分相同。然而，本实施例对此并不限定。在一些示例中，多个电阻补偿单元的半导体结构的面积可以相同，至少一条数据扇出线所串联的电阻补偿单元的数目可以根据该条数据扇出线所需补偿的电阻值确定。
在一些示例性实施方式中，扇出区域内的多条数据扇出线与多个电阻补偿单元一一对应串联且电连接。扇出区域内的多个电阻补偿单元沿着第一方向依次排布，或者，沿着垂直于第一方向的第二方向错开排布。第一方向垂直于显示区域的数据线的延伸方向。例如，多个电阻补偿单元在扇出区域的排布方向平行于第一方向，或者，与第一方向存在一定夹角。然而，本实施 例对此并不限定。
在一些示例性实施方式中，沿着从扇出区域的边缘到中间的方向上，扇出区域内的多条数据扇出线电连接的电阻补偿单元的半导体结构的总面积递增，或者，先递增后递减。在本示例性实施方式中，电阻补偿单元的半导体结构的总面积的变化与电阻补偿单元所连接的数据扇出线的电阻值变化相关，例如，电阻补偿单元所连接的数据扇出线的电阻值沿着从扇出区域的边缘到中间的方向上递减，则电阻补偿单元的半导体结构的总面积沿着从扇出区域的边缘到中间的方向上递增。
在一些示例性实施方式中，扇出区域在第一方向上具有多个扇出分区。第一方向垂直于显示区域的数据线的延伸方向。至少一个扇出分区内的多条数据扇出线连接的电阻补偿单元沿着第一方向依次排布，或者，沿着垂直于第一方向的第二方向错开排布。在一些示例中，多个扇出分区内的电阻补偿单元的排布方式是相同的；例如，每个扇出分区内的多个电阻补偿单元的排布方向均平行于第一方向，或者，沿着第二方向错开排布。在一些示例中，多个扇出分区内的电阻补偿单元的排布方式是不同的；例如，至少一个扇出分区内的多个电阻补偿单元的排布方向平行于第一方向，其余扇出分区内的多个电阻补偿单元沿着第二方向错开排布。然而，本实施例对此并不限定。
在一些示例性实施方式中，沿着从扇出区域的边缘到中间的方向上，至少一个扇出分区内的多条数据扇出线电连接的电阻补偿单元的半导体结构的总面积递增，或者，先递增后递减。然而，本实施例对此并不限定。
在一些示例性实施方式中，半导体结构位于数据扇出线层靠近衬底基板的一侧，导电连接结构位于数据扇出线层远离衬底基板的一侧。通过导电连接结构连接半导体结构和数据扇出线层的数据扇出线。
在一些示例性实施方式中，边框区域还包括：位于信号接入区域和显示区域之间的弯折区域。扇出区域包括：位于显示区域和弯折区域之间的第一扇出区域、位于弯折区域和信号接入区域之间的第二扇出区域。至少一条数据扇出线包括：位于第一扇出区域的第一子数据扇出线、以及位于第二扇出区域且与第一子数据扇出线连接的第二子数据扇出线。至少一个电阻补偿单元被配置为满足以下之一：设置在第一扇出区域且与至少一条第一子数据扇 出线串联且电连接；设置在第二扇出区域且与至少一条第二子数据扇出线串联且电连接。例如，多个电阻补偿单元可以均设置在第一扇出区域；或者，多个电阻补偿单元均设置在第二扇出区域；或者，多个电阻补偿单元中的一部分设置在第一扇出区域，另一部分设置在第二扇出区域。然而，本实施例对此并不限定。
在一些示例性实施方式中，边框区域还包括：位于信号接入区域和显示区域之间的弯折区域、位于弯折区域和信号接入区域之间的测试电路区域。扇出区域包括：位于显示区域和弯折区域之间的第一扇出区域、位于弯折区域和测试电路区域之间的第二扇出区域、以及位于测试电路区域和信号接入区域之间的第三扇出区域。至少一条数据扇出线包括：位于第一扇出区域的第一子数据扇出线、位于第二扇出区域且与第一子数据扇出线电连接的第二子数据扇出线、以及位于第三扇出区域且与第二子数据扇出线电连接的第三子数据扇出线。至少一个电阻补偿单元被配置为满足以下之一：设置在第一扇出区域且与至少一条第一子数据扇出线串联且电连接；设置在第二扇出区域且与至少一条第二子数据扇出线串联且电连接；设置在第三扇出区域且与至少一条第三子数据扇出线串联且电连接。例如，多个电阻补偿单元可以均设置在第一扇出区域；或者，多个电阻补偿单元均设置在第二扇出区域；或者，多个电阻补偿单元均设置在第三扇出区域；或者，多个电阻补偿单元中的一部分设置在第一扇出区域，另一部分设置在第二扇出区域；或者，多个电阻补偿单元中的一部分设置在第二扇出区域，另一部分设置在第三扇出区域；或者，多个电阻补偿单元中的一部分设置在第一扇出区域，另一部分设置在第三扇出区域；或者，多个电阻补偿单元中的第一部分设置在第一扇出区域，第二部分设置在第二扇出区域，第三部分设置在第三扇出区域。然而，本实施例对此并不限定。
在一些示例性实施方式中，多个电阻补偿单元均设置在第二扇出区域，且第二扇出区域内的至少一条第二子数据扇出线与至少一个电阻补偿单元串联且电连接。通过将多个电阻补偿单元设置在第二扇出区域，可以实现电阻补偿单元的合理排布，并通过减小第一扇出区域的尺寸来实现窄边框。
在一些示例性实施方式中，多个电阻补偿单元均设置在第二扇出区域。 第二扇出区域内的多个电阻补偿单元靠近测试电路区域或靠近信号接入区域。在本示例中，当第二扇出区域位于弯折区域和测试电路区域之间时，第二扇出区域内的电阻补偿单元与弯折区域之间的距离大于与测试电路区域之间的距离。当第二扇出区域位于弯折区域和信号接入区域之间时，第二扇出区域内的电阻补偿单元与弯折区域之间的距离大于与信号接入区域之间的距离。然而，本实施例对此并不限定。
在一些示例性实施方式中，数据扇出线层包括：依次设置在衬底基板上且相互绝缘的第一数据扇出线层和第二数据扇出线层。第一数据扇出线层包括多条第一数据扇出线，第二数据扇出线层包括多条第二数据扇出线。第一数据扇出线层和第二数据扇出线层在衬底基板上的正投影没有交叠，且多条第一数据扇出线和多条第二数据扇出线间隔排布。本示例性实施方式中，通过将多条数据扇出线异层设置，可以减小相邻数据扇出线之间的间距，并减小相邻数据扇出线之间的传输干扰，从而提高信号传输性能。
在一些示例性实施方式中，显示区域至少包括：设置在衬底基板上的驱动结构层、设置在驱动结构层上的发光元件。发光元件与驱动结构层电连接。驱动结构层包括：依次设置在衬底基板上的有源层、第一栅金属层、第二栅金属层以及源漏金属层。第一数据扇出层与第一栅金属层为同层结构，第二数据扇出层与第二栅金属层为同层结构；半导体结构与有源层为同层结构；导电连接结构与源漏金属层为同层结构。然而，本实施例对此并不限定。
下面通过一些示例对本实施例的显示基板进行举例说明。下述示例性实施例中以显示基板为OLED显示基板为例进行说明。其中，由于显示区域的数据线和扇出区域的数据扇出线的数量通常较多，附图中仅示意了部分数据线和数据扇出线或仅示意了扇出区域的位置，并不限定数据线和数据扇出线的数量。
图1为本公开至少一实施例的显示基板的示意图。如图1所示，本示例性实施例提供的显示基板，包括：显示区域100以及位于显示区域100周边的边框区域。边框区域包括：位于显示区域100一侧的第一边框区域200、以及位于显示区域100外围且远离第一边框区域200的第二边框区域300。第一边框区域200和第二边框区域300连通后围绕显示区域100。在一些示 例中，第一边框区域200为显示基板的下边框，第二边框区域300包括显示基板的上边框、左边框和右边框。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图1所示，显示区域100至少包括多个子像素1001、多条栅线(图未示)以及多条数据线(Data Line)1002。多条栅线和多条数据线1002在衬底基板上的正投影交叉形成多个子像素区域，每个子像素区域内设置一个子像素1001。多条数据线1002与多个子像素1001电连接，多条数据线1002被配置为向多个子像素1001提供数据信号。多条栅线与多个子像素1001电连接，多条栅线被配置为向多个子像素1001提供扫描信号。在一些示例中，一个像素单元可以包括三个子像素，三个子像素分别为红色子像素、绿色子像素和蓝色子像素。然而，本实施例对此并不限定。在一些示例中，一个像素单元可以包括四个子像素，四个子像素分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。
在一些示例性实施方式中，子像素1001的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列；一个像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形(Square)方式排列。然而，本实施例对此并不限定。
在一些示例性实施方式中，第二边框区域300至少包括向显示区域100的多个子像素1001提供扫描信号的栅极驱动电路、以及向多个子像素1001传输电压信号的电源线(例如，低电压电源线(VSS))。
图2为本公开至少一实施例的第一边框区域的一种示意图。在一些示例性实施方式中，如图2所示，第一边框区域200包括：位于显示区域100一侧的第一扇出(Fan-out)区域201、位于第一扇出区域201远离显示区域100一侧的弯折区域202、位于弯折区域202远离显示区域100一侧的第二扇出区域203、位于第二扇出区域203远离显示区域100一侧的测试电路区域204、位于测试电路区域204远离显示区域100一侧的第三扇出区域205、位于第三扇出区域205远离显示区域100一侧的信号接入区域206。在本示例中，第一边框区域200内的扇出区域包括：第一扇出区域201、第二扇出区域203和第三扇出区域205。其中，第一扇出区域201位于显示区域100和弯折区 域202之间，第二扇出区域203位于弯折区域202和测试电路区域204之间，第三扇出区域205位于测试电路区域204和信号接入区域206之间。其中，第一边框区域200还可以包括位于信号接入区域206远离显示区域100一侧的绑定电极区域(图未示)。绑定电极区域包括多个绑定焊盘(Bonding Pad)，被配置为与外部的柔性线路板(FPC，Flexible Printed Circuit)绑定连接。
在一些示例性实施方式中，如图2所示，第一扇出区域201设置有多条第一子数据扇出线、第一电源线(图未示)和第二电源线(图未示)。多条第一子数据扇出线被配置为以扇出走线方式与显示区域100的多条数据线一一对应连接。第一电源线被配置为连接显示区域100的高电压电源线(VDD)。第二电源线被配置为连接第二边框区域的低电压电源线(VSS)。在一些示例中，第一电源线和第二电源线同层设置，第一电源线和第二电源线与多条第一子数据扇出线异层设置；多条第一子数据扇出线在衬底基板上的正投影与第一电源线在衬底基板上的正投影部分交叠，多条第一子数据扇出线在衬底基板上的正投影与第二电源线在衬底基板上的正投影部分交叠。在一些示例中，多条第一子数据扇出线可以被分成两组。第一组的多条第一子数据扇出线和第二组的多条第一子数据扇出线异层设置。第一组的多条第一子数据扇出线和第二组的多条第一子数据扇出线在衬底基板上的正投影没有交叠，且第一组的多条第一子数据扇出线和第二组的多条第一子数据扇出线间隔排布。然而，本实施例对此并不限定。例如，第一扇出区域的多条第一子数据扇出线可以同层设置。
在一些示例性实施方式中，如图2所示，第一扇出区域201包括多个第一扇出分区，例如，沿第一方向D1依次排布的四个第一扇出分区211、212、213和214。每个第一扇出分区内设置有多条第一子数据扇出线。位于第一扇出区域201的左侧边缘的第一扇出分区211内的多条第一子数据扇出线的长度沿着从第一扇出区域201的边缘到中间方向递减。位于第一扇出区域201的右侧边缘的第一扇出分区214内的多条第一子数据扇出线的长度沿着从第一扇出区域201的边缘到中间方向递减。位于第一扇出分区211右侧的第一扇出分区212内的多条第一子数据扇出线的长度沿着从第一扇出区域201的边缘到中间方向先递减后递增。位于第一扇出分区214左侧的第一扇出分区 213内的多条第一子数据扇出线的长度沿着从第一扇出区域201的边缘到中间方向先递减后递增。然而，本实施例对此并不限定。在一些示例中，每个第一扇出分区内的多条第一子数据扇出线的长度均可以沿着从第一扇出区域的边缘到中间方向递减。
在本公开中，第一方向D1垂直于显示区域100的数据线的延伸方向，第二方向D2垂直于第一方向D1，即第二方向D2平行于显示区域100的数据线的延伸方向。
在一些示例性实施方式中，如图2所示，弯折区域202被配置为使部分第一边框区域弯折到显示区域100的背面。弯折区域202至少设置有多条数据连接线、多条电源连接线。多条数据连接线配置为与第一扇出区域201的多条第一子数据扇出线一一对应连接。多条电源连接线可以包括第一电源连接线(例如，高电压电源连接线)和第二电源连接线(例如，低电压电源连接线)；第一电源连接线配置为与第一扇出区域201的第一电源线连接，第二电源连接线配置为与第一扇出区域201的第二电源线连接。其中，多条数据连接线和多条电源连接线同层设置。电源连接线可以排布在多条数据连接线的中间。
在一些示例性实施方式中，如图2所示，弯折区域202包括多个第一弯折分区(例如，沿第一方向D1依次排布的四个第一弯折分区220a、220b、220c和220d)、多个第二弯折分区(例如，沿着第一方向D1依次排布的五个第二弯折分区221a、221b、221c、221d和221e)。相邻两个第一弯折分区之间设置有至少一个第二弯折分区。每个第一弯折分区内设置有多条数据连接线，每个第二弯折分区内设置有电源连接线。例如，第二弯折分区221a和221e内设置有第二电源连接线，第二弯折分区221b、221c和221d内设置有第一电源连接线。在本示例中，第二弯折分区221b位于第一弯折分区220a和220b之间，第二弯折分区221c位于第一弯折分区220b和220c之间，第二弯折分区221d位于第一弯折分区220c和220d之间。第一扇出区域201的多个第一扇出分区和弯折区域202的多个第一弯折分区一一对应。第一扇出分区内的多条第一子数据扇出线与对应的第一弯折分区内的多条数据连接线一一对应连接。
在一些示例性实施方式中，如图2所示，第二扇出区域203设置有多条第二子数据扇出线。多条第二子数据扇出线被配置为以扇出走线方式连接弯折区域202的多条数据连接线，且多条第二子数据扇出线与弯折区域202的多条数据连接线一一对应连接。在一些示例中，多条第二子数据扇出线可以被分成两组。第一组的多条第二子数据扇出线和第二组的多条第二子数据扇出线异层设置。第一组的多条第二子数据扇出线和第二组的多条第二子数据扇出线在衬底基板上的正投影没有交叠，且第一组的多条第二子数据扇出线和第二组的多条第二子数据扇出线间隔排布。其中，第二扇出区域203的第一组的多条第二子数据扇出线可以与第一扇出区域201的第一组的多条第一子数据扇出线同层设置，第二扇出区域203的第二组的多条第二子数据扇出线可以与第一扇出区域201的第二组的多条第一子数据扇出线同层设置。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图2所示，第二扇出区域203包括多个第二扇出分区，例如，沿第一方向D1依次排布的四个第二扇出分区231、232、233和234。每个第二扇出分区内设置有多条第二子数据扇出线。每个第二扇出分区内的多条第二子数据扇出线的长度沿着从第二扇出区域203的边缘到中间方向递减。第二扇出区域203的多个第二扇出分区和弯折区域202的多个第一弯折分区一一对应。第二扇出分区内的多条第二子数据扇出线与对应的第一弯折分区内的多条数据连接线一一对应连接。换言之，第一扇出区域201的多条第一子数据扇出线通过第一弯折分区的多条数据连接线与第二扇出区域203的多条第二子数据扇出线一一对应连接。在本示例中，第二扇出分区的数目与第一扇出分区的数目对应。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图2所示，测试电路区域204包括测试电路，测试电路包括多个测试单元，每个测试单元与第二扇出区域203的多条第二子数据扇出线连接。每个测试单元可以通过依次连接的第二子数据扇出线、数据连接线和第一子数据扇出线向显示区域100的多个数据线提供测试数据信号。在一些示例中，测试电路可以包括至少一个测试控制信号线、多个测试数据信号线和多个测试单元，每个测试单元与测试控制信号线和测试数据信号线连接，且连接显示区域的多个数据线。测试单元配置为根据测试 控制信号线的控制，将测试数据信号线的信号(测试数据信号)提供给(同时提供或分别提供)与其连接的显示区域的多个数据线，以检测和定位显示区域发生不良的子像素。然而，本实施例对于测试电路的结构并不限定。
在一些示例性实施方式中，如图2所示，第三扇出区域205包括多个第三扇出分区，例如，沿第一方向D1依次排布的两个第三扇出分区251和252。每个第三扇出分区内设置有多条第三子数据扇出线。多条第三子数据扇出线被配置为以扇出走线方式连接信号接入区域206的信号输入垫。每个第三扇出分区内的多条第三子数据扇出线的长度可以沿着从第三扇出区域203的边缘到中间方向先递减后递增。在本示例中，一个第三扇出分区与两个第二扇出分区对应。一个第三扇出分区内的多条第三子数据扇出线可以与第二扇出区域的两个相邻第二扇出分区内的多条第二子数据扇出线一一对应连接。即，第三扇出区域内的第三子数据扇出线和第二扇出区域内的第二子数据扇出线的数目相同，可以一一对应连接。然而，本实施例对此并不限定。在一些示例中，第三扇出区域内的第三子数据扇出线的数目与第二扇出区域内的第二子数据扇出线的数目可以为1：N的关系，其中，N为大于1的整数。
在一些示例中，第三扇出区域205内的多条第三子数据扇出线可以被分成两组。第一组的多条第三子数据扇出线和第二组的多条第三子数据扇出线异层设置。第一组的多条第三子数据扇出线和第二组的多条第三子数据扇出线在衬底基板上的正投影没有交叠，且第一组的多条第三子数据扇出线和第二组的多条第三子数据扇出线间隔排布。第三扇出区域205的第一组的多条第三子数据扇出线可以与第二扇出区域203的第一组的多条第二子数据扇出线同层设置，第三扇出区域205的第二组的多条第三子数据扇出线可以与第二扇出区域203的第二组的多条第二子数据扇出线同层设置。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图2所示，信号接入区域206包括多个信号输入垫，配置为连接驱动集成电路(IC，Integrated Circuit)。驱动集成电路可以通过多个信号输入垫与第三扇出区域205的多条第三子数据扇出线连接，被配置为向显示区域100的多条数据线提供数据信号。
在一些示例性实施方式中，如图2所示，第一边框区域的扇出区域包括 第一扇出区域201、第二扇出区域203和第三扇出区域205。扇出区域内连接显示区域100的数据线和信号接入区域206的信号输入垫的数据扇出线包括：位于第一扇出区域201的第一子数据扇出线、位于第二扇出区域203且与第一子数据扇出线电连接的第二子数据扇出线、以及位于第三扇出区域205且与第二子数据扇出线电连接的第三子数据扇出线。显示区域100的所有数据线通过数据扇出线和弯折区域202内的数据连接线可以并行连接到信号接入区域206所连接的驱动集成电路，由驱动集成电路控制这些数据线给显示区域100中的子像素提供用于显示的数据信号。在本示例中，多条数据扇出线异层设置，可以减小相邻数据扇出线之间的间距，并减小相邻数据扇出线的传输干扰，提高信号传输性能。
图3为图2中区域S的一种局部放大示意图。图4为图3中沿A-A方向的剖面示意图。图5为图3中沿B-B方向的剖面示意图。图3中放大示意了多条第二子数据扇出线和电阻补偿单元的结构，以便示意出不同第二子数据扇出线所连接的电阻补偿单元的差异。
在一些示例性实施方式中，第二扇出区域203的多条第二子数据扇出线被分成两组。如图3所示，在平行于显示基板的平面上，第一组的多条第二子数据扇出线52a和第二组的多条第二子数据扇出线52b间隔排布。如图5所示，在垂直于显示基板的平面上，第二组的第二子数据扇出线52b位于第一组的第二子数据扇出线52a远离衬底基板10的一侧，且第二组的第二子数据扇出线52b和第一组的第二子数据扇出线52a之间设置有第三绝缘层13。在本示例中，通过将多条第二子数据扇出线异层设置，可以减小相邻第二子数据扇出线之间的间距，并减小相邻第二子数据扇出线的传输干扰，提高信号传输性能。然而，本实施例对此并不限定。例如，第二扇出区域内的多条第二子数据扇出线可以同层设置。
在一些示例性实施方式中，如图3所示，第二扇出区域203还设置有多个电阻补偿单元。第二扇出区域203的多条第二子数据扇出线与多个电阻补偿单元一一对应串联且电连接。即，一条第二子数据扇出线与一个电阻补偿单元串联且电连接。多个电阻补偿单元可以沿着第一方向D1依次排布在第二扇出区域203。在本示例性实施方式中，通过给第二扇出区域内的第二子 数据扇出线串联且电连接电阻补偿单元，可以对整个扇出区域的整条数据扇出线进行电阻补偿。然而，本实施例对此并不限定。例如，电阻补偿单元可以设置在第一扇出区域并与第一子数据扇出线串联且电连接，或者，可以设置在第三扇出区域并与第三子数据扇出线串联且电连接。
在一些示例性实施方式中，如图3和图4所示，至少一个电阻补偿单元包括：依次设置在衬底基板10上的半导体结构61和导电连接结构。导电连接结构包括：第一连接电极62和第二连接电极63。第一连接电极62通过两个第一过孔K1与半导体结构61的一端电连接，第二连接电极63通过两个第一过孔K1与半导体结构61的另一端电连接。其中，第一过孔K1可以为圆形或椭圆形或矩形。然而，本实施例对于第一过孔的数目和形状并不限定。
在一些示例性实施方式中，如图3所示，第二子数据扇出线52a包括断开的第一部分521a和第二部分522a。一个电阻补偿单元串联在第二子数据扇出线52a的第一部分521a和第二部分522a之间。第二子数据扇出线52a的第一部分521a通过两个第二过孔K2与电阻补偿单元的第一连接电极62电连接，第二子数据扇出线52a的第二部分522a通过两个第三过孔K3与电阻补偿单元的第二连接电极63电连接。第二子数据扇出线52b包括断开的第一部分521b和第二部分522b。一个电阻补偿单元串联在第二子数据扇出线52b的第一部分521b和第二部分522b之间。第二子数据扇出线52b的第一部分521b通过两个第四过孔K4与一个电阻补偿单元的第一连接电极电连接，第二子数据扇出线52b的第二部分522b通过两个第五过孔K5与该电阻补偿单元的第二连接电极电连接。其中，第二过孔K2、第三过孔K3、第四过孔K4和第五过孔K5可以为圆形或椭圆形或矩形。然而，本实施例对于第二过孔K2、第三过孔K3、第四过孔K4和第五过孔K5的数目和形状并不限定。
在一些示例中，如图3所示，多个第一连接电极62和多个第二连接电极63的形状和大小可以相同，例如，均为矩形(例如圆角矩形)。多个半导体结构61的形状可以相同，例如，均为矩形。多个半导体结构61的面积可以不同，例如，多个半导体结构61沿第一方向D1的长度可以相同，多个半导体结构61沿第二方向D2的长度可以不同。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图3至图5所示，在垂直于显示基板的平 面上，第二扇出区域203包括：依次设置在衬底基板10上的半导体结构61、第一数据扇出线层、第二数据扇出线层、以及导电连接结构。第二扇出区域203的第一数据扇出线层包括多条第二子数据扇出线52a，第二数据扇出线层包括多条第二子数据扇出线52b。导电连接结构包括第一连接电极62和第二连接电极63。半导体结构61位于第二子数据扇出线52a和52b靠近衬底基板10的一侧，第一连接结构62和第二连接结构63位于第二子数据扇出线52a和52b远离衬底基板10的一侧。半导体结构61和第一数据扇出线层之间设置有第二绝缘层12，第一数据扇出线层和第二数据扇出线层之间设置有第三绝缘层13，第二数据扇出线层和导电连接结构之间设置有第四绝缘层14。其中，第一过孔K1设置在第四绝缘层14上且暴露出半导体结构61的表面，第二过孔K2和第三过孔K3设置在第四绝缘层14上且暴露出第一数据扇出线层的表面，第四过孔K4和第五过孔K5设置在第四绝缘层14上且暴露出第二数据扇出线层的表面。在本示例中，半导体结构通过第一连接电极和第二连接电极实现与第一数据扇出线层和第二数据扇出线层的跳层连接。
图6为本公开至少一实施例的显示基板的数据扇出线进行电阻补偿前后的电阻分布曲线示意图。如图6所示，横坐标表示图2中第一边框区域内沿第一方向D1从左侧边缘至右侧边缘的多条数据扇出线的顺序；纵坐标表示电阻值，单位为欧姆。图6中的虚线表示沿第一方向D1从左侧边缘至右侧边缘的多条数据扇出线在未设置电阻补偿单元之前的电阻值，实线表示多条数据扇出线设置电阻补偿单元之后的电阻值。图6中横坐标位置所对应的实线与虚线电阻值的差值即为该横坐标位置对应的数据扇出线所串联的电阻补偿单元提供的补偿电阻值。
如图6所示，在第一边框区域的数据扇出线未进行电阻补偿之前，由于扇出区域通过扇出走线方式排布数据扇出线，而且显示基板目前均存在圆角设计，多条数据扇出线与信号接入区域之间的相对位置不同，使得每条数据扇出线的长度不同。例如，在图2中，沿第一方向D1上位于两侧边缘的数据扇出线的长度较长，且从边缘到中间区域的方向上长度递减后递增。由于多条数据扇出线通常采用同种导电材料制成(即电阻率相同)，并且是在相同或相似构图工艺下所形成，因此多条数据扇出线的线宽、厚度均对应相等 (或非常接近)，从而使得多条数据扇出线的电阻值随其长度的增加而增大。由于不同数据扇出线之间存在长度差异，进而导致多条数据扇出线之间存在较大的电阻差异，且不同数据扇出线之间的长度差异越大电阻差异也越大，导致显示区域的显示画面出现色偏、亮度不均匀(即Mura)等不良，影响显示效果。而且，由于弯折区域内的电源连接线与数据连接线同层设置，且电源连接线会排布在数据连接线的中间，导致电源连接线所在的第二弯折分区两侧的数据连接线所连接的数据扇出线会存在长度跳变，产生电阻值跳变，进而产生块状显示不良(Mura)，即显示区域以此第二弯折分区两侧的数据扇出线所连接的相邻两列子像素为分界，在该分界两侧出现明显的亮度差异。例如，图6中的第一电阻跳变点a是在图2中的第二弯折区221b两侧的数据扇出线所产生的，第二电阻跳变点b是图2中的第二弯折区221d两侧的数据扇出线所产生的。
在一些示例性实施方式中，如图6所示，在数据扇出线串联电阻补偿单元之后，第一边框区域的多条数据扇出线的电阻值可以基本相同，从而改善显示区域由于数据扇出线的电阻值差异导致的显示色偏或亮度不均情况，提升显示效果。在本示例性实施方式中，电阻补偿单元的半导体结构的面积与电阻补偿单元所提供的电阻值呈正比关系，即半导体结构的面积越大，补偿的电阻值越大，半导体结构的面积越小，补偿的电阻值越小。通过调整半导体结构的面积即可实现补偿电阻值的调整。而且，半导体结构的电阻值约为4000Ω/um^2，可以在有限空间内补偿足够的电阻差值，在狭小空间内实现千欧姆级别的电阻补偿。
在一些示例性实施方式中，电阻值较小的数据扇出线所串联的电阻补偿单元的半导体结构的总面积大于电阻值较大的数据扇出线所串联的电阻补偿单元的半导体结构的总面积。如图2和图3所示，由于第二弯折分区221b的存在，第二扇出分区231和232边界处的第二子数据扇出线52b和52a之间会存在长度跳变。例如，第二扇出分区231内的第二子数据扇出线的长度从第二扇出区域203的边缘到中间方向是递减的，第二扇出分区232内的第二子数据扇出线的长度从第二扇出区域203的边缘到中间方向也是递减的，但是在第二扇出分区231和232的交界处，第二扇出分区232内的第二子数 据扇出线52a的长度会大于相邻的第二扇出分区231内的第二子数据扇出线52b的长度。如图3所示，为了对第二扇出分区231和232交界处的第二子数据扇出线52a和52b的电阻值进行补偿，在第二子数据扇出线52a和52b分别串联一个电阻补偿单元，且第二子数据扇出线52a串联的电阻补偿单元的半导体结构61的面积小于第二子数据扇出线52b串联的电阻补偿单元的半导体结构61的面积。在本示例中，多个半导体结构沿第一方向D1的长度可以相同，通过调节半导体结构沿第二方向D2的长度来改变半导体结构的面积。例如，半导体结构沿第二方向D2的长度可以按照微米级别变化。在一些示例中，如图2、图3和图6所示，在第二扇出分区231内的多条第二子数据扇出线所串联的半导体结构沿第二方向D2的长度可以沿着从第二扇出区域203的边缘到中间方向递增，在第二扇出分区232内的多条第二子数据扇出线所串联的半导体结构沿第二方向D2的长度可以沿着从第二扇出区域203的边缘到中间方向先递增后递减。
图7为图2中沿P-P方向的局部剖面示意图。下面参照图7通过显示基板的制备过程的示例说明本公开显示基板的结构。本公开所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶等处理。沉积可以采用选自溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用选自喷涂和旋涂中的任意一种或多种，刻蚀可以采用选自干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。当在整个制作过程当中该“薄膜”还需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。
本公开中所说的“A和B同层设置”是指，A和B通过同一次构图工艺同时形成。“相同层”不总是意味着层的厚度或层的高度在截面图中是相同的。“A的正投影包含B的正投影”是指，B的正投影落入A的正投影范围内，或者A的正投影覆盖B的正投影。
在一些示例性实施方式中，本实施例的显示基板的制备过程可以包括以下步骤(1)至步骤(8)。
(1)、在玻璃载板上制备柔性的衬底基板。
在一些示例性实施方式中，衬底基板10包括在玻璃载板上叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料。第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高衬底基板的抗水氧能力。第一无机材料层和第二无机材料层也称之为阻挡(Barrier)层。半导体层的材料可以采用非晶硅(a-si)。
在一些示例性实施方式中，衬底基板的制备过程可以包括：先在玻璃载板上涂布一层聚酰亚胺，固化成膜后形成第一柔性(PI1)材料层；随后在第一柔性层上沉积一层阻挡薄膜，形成覆盖第一柔性材料层的第一阻挡(Barrier1)层；然后在第一阻挡层上沉积一层非晶硅薄膜，形成覆盖第一阻挡层的非晶硅(a-si)层；然后在非晶硅层上再涂布一层聚酰亚胺，固化成膜后形成第二柔性(PI2)材料层；然后在第二柔性材料层上沉积一层阻挡薄膜，形成覆盖第二柔性层的第二阻挡(Barrier2)层，完成衬底基板10的制备。本次工艺后，显示区域和第一边框区域均包括衬底基板10。
(2)、在衬底基板上制备有源层和半导体结构图案。
在一些示例性实施方式中，在衬底基板10上依次沉积第一绝缘薄膜和半导体层薄膜，通过构图工艺对半导体层薄膜进行构图，形成覆盖整个衬底基板10的第一绝缘层11，以及设置在第一绝缘层11上的有源层和半导体结构图案。如图7所示，有源层图案形成在显示区域100，至少包括第一有源层21。半导体结构图案形成在第二扇出区域203，至少包括半导体结构61。
(3)、在衬底基板上制备第一栅金属层和第一数据扇出线层图案。
在一些示例性实施方式中，在形成上述结构的衬底基板10上，依次沉积第二绝缘薄膜和第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，形成覆盖有源层和半导体结构图案的第二绝缘层12，以及设置在第二绝缘层12上的第一栅金属层图案和第一数据扇出线层图案。如图7所示，第一栅金属层图案形成在显示区域100，至少包括第一栅电极22、第一电容电极25、多条栅线(未示出)。第一数据扇出线层图案形成在扇出区域，至少包括多条 第一数据扇出线。第一数据扇出线包括：位于第一扇出区域的第一子数据扇出线、位于第二扇出区域且与同层的第一子数据扇出线电连接的第二子数据扇出线(例如，图3所示的第二子数据扇出线52a，第二子数据扇出线52a包括断开的第一部分521a和第二部分522a)、位于第三扇出区域且与同层的第二子数据扇出线电连接的第三子数据扇出线。第一子数据扇出线配置为与显示区域100后续形成的数据线电连接。第一子数据扇出线和第二子数据扇出线配置为通过弯折区域后续形成的数据连接线电连接。
(4)、在衬底基板上制备第二栅金属层和第二数据扇出线层图案。
在一些示例性实施方式中，在形成上述结构的衬底基板10上，依次沉积第三绝缘薄膜和第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，形成覆盖第一栅金属层图案、第一数据扇出线层图案和第二绝缘层12的第三绝缘层13，以及设置在第三绝缘层13上的第二栅金属层图案和第二数据扇出线层图案。如图7所示，第二栅金属层图案形成在显示区域100，至少包括第二电容电极26。第二数据扇出线层图案形成在扇出区域，至少包括多条第二数据扇出线。第二数据扇出线包括：位于第一扇出区域的第一子数据扇出线、位于第二扇出区域且与同层的第一子数据扇出线电连接的第二子数据扇出线(例如，图3所示的第二子数据扇出线52b)、位于第三扇出区域且与同层的第二子数据扇出线电连接的第三子数据扇出线。第二数据扇出线层的第一子数据扇出线配置为与显示区域100后续形成的数据线电连接。同层的第一子数据扇出线和第二子数据扇出线配置为通过弯折区域后续形成的数据连接线电连接。
(5)、在衬底基板上制备第四绝缘层图案。
在一些示例性实施方式中，在形成上述结构的衬底基板10上，沉积第四绝缘薄膜，通过构图工艺对第四绝缘薄膜进行构图，形成覆盖第二栅金属层和第二数据扇出线层图案的第四绝缘层14图案。如图3和图7所示，第四绝缘层上至少开设有多个第一过孔K1、多个第二过孔K2、多个第三过孔K3、多个第四过孔K4、多个第五过孔K5以及多个第六过孔。多个第一过孔K1、多个第二过孔K2、多个第三过孔K3、多个第四过孔K4和多个第五过孔K5位于第二扇出区域203。多个第一过孔K1暴露出半导体结构61的表面，多 个第二过孔K2和第三过孔K3暴露出与位于第一数据扇出线层的第二子数据扇出线的表面，多个第四过孔K4和多个第五过孔K5暴露出与位于第二数据扇出线层的第二子数据扇出线的表面。多个第六过孔位于显示区域100，暴露出第一有源层21的表面。
在一些示例性实施方式中，在形成第四绝缘层14之后，通过第一次掩模刻蚀(Etch Bending A MASK，简称EBA MASK)和第二次掩模刻蚀(Etch Bending B MASK，简称EBB MASK)对弯折区域进行挖槽，以减少弯折区域的厚度，提高弯折效果。
(6)、在衬底基板上制备源漏金属层、导电连接结构、数据连接线和电源连接线图案。
在一些示例性实施方式中，在形成上述结构的衬底基板10上，沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，在第四绝缘层14上形成源漏金属层图案、导电连接结构、数据连接线和电源连接线图案。如图7所示，源漏金属层图案形成在显示区域100，至少包括第一源电极23、第一漏电极24、多条数据线(未示出)、电源线(例如，VDD和VSS)图案。第一源电极23和第一漏电极24分别通过第六过孔与第一有源层21连接。如图3和图7所示，导电连接结构图案形成在第二扇出区域203，至少包括第一连接电极62和第二连接电极63。第一连接电极62的一端通过两个第二过孔K2和第二子数据扇出线52a的第一部分521a连接，第一连接电极62的另一端通过两个第一过孔K1与半导体结构61连接。第二连接电极63的一端通过两个第三过孔K3和第二子数据扇出线52a的第二部分522a连接，第二连接电极63的另一端通过两个第一过孔K1与半导体结构61连接。数据连接线和电源连接线形成在弯折区域，且电源连接线排布在数据连接线的中间。至少一条数据连接线的两端分别与第一数据扇出线层的第一子数据扇出线和第二子数据扇出线连接，或者分别与第二数据扇出线层的第一子数据扇出线和第二子数据扇出线连接。
至此，在衬底基板10上制备完成显示区域100的驱动结构层，如图7所示。显示区域100的驱动结构层中，第一有源层21、第一栅电极22、第一源电极23和第一漏电极24组成第一晶体管，第一电容电极25和第二电容电 极26组成第一存储电容。
在一些示例性实施方式中，第一绝缘层11又可以称为缓冲层，第二绝缘层12和第三绝缘层13还可以称为栅绝缘层，第四绝缘层14还可以称为层间绝缘层。第一绝缘层11、第二绝缘层12、第三绝缘层13和第四绝缘层14可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层11可以用于提高衬底基板10的抗水氧能力。第一金属薄膜、第二金属薄膜和第三金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。半导体层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等一种或多种材料，即本公开适用于基于氧化物(Oxide)技术、硅技术以及有机物技术制造的晶体管。
(7)、在衬底基板上制备第五绝缘层和平坦(PLN，Planarization)层。
在一些示例性实施方式中，在形成上述结构的衬底基板10上沉积第五绝缘薄膜，通过构图工艺形成第五绝缘层15。然后，在形成上述结构的衬底基板10上涂覆平坦薄膜，形成覆盖整个衬底基板10的平坦层16，通过构图工艺在平坦层16形成第七过孔。多个第七过孔形成在显示区域100，任一第七过孔内的平坦层16和第五绝缘层15被刻蚀掉，暴露出第一晶体管的第一漏电极24的表面。
(8)、在衬底基板上依次制备阳极、像素定义层、隔离柱、有机发光层、阴极和封装层。
在一些示例性实施方式中，在形成前述结构的衬底基板10上，沉积透明导电薄膜，通过构图工艺对透明导电薄膜进行构图，形成阳极31图案。如图7所示，阳极31图案形成在显示区域100的平坦层16上，通过第七过孔与第一漏电极24连接。
在一些示例性实施方式中，在形成前述结构的衬底基板10上，涂覆像素定义薄膜，通过掩膜、曝光、显影工艺，形成像素定义层(PDL，Pixel Definition  Layer)34图案。如图7所示，像素定义层34形成在显示区域100和第二扇出区域203。显示区域100的像素定义层34上开设有像素开口，像素开口内的像素定义薄膜被显影掉，暴露出阳极31的表面。
在一些示例性实施方式中，在形成前述图案的衬底基板10上，涂覆有机材料薄膜，通过掩膜、曝光、显影工艺，在显示区域100形成隔离柱(PS)层41图案。如图7所示，显示区域100的隔离柱层41包括多个隔离柱。
在一些示例性实施方式中，在形成前述图案的衬底基板10上依次形成有机发光层32和阴极33。如图7所示，有机发光层32包括叠设的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层，形成在显示区域100的像素开口内，实现有机发光层32与阳极31连接。由于阳极31与第一晶体管的第一漏电极24连接，实现有机发光层32的发光控制。阴极33的一部分形成在有机发光层32上。本次构图工艺之后，第二扇出区域203的膜层结构没有变化。
在一些示例性实施方式中，在形成前述图案的衬底基板10上，形成封装层42。如图7所示，封装层42形成在显示区域100，可以采用无机材料/有机材料/无机材料的叠层结构。有机材料层设置在两个无机材料层之间。本次构图工艺之后，第二扇出区域203的膜层结构没有变化。
在一些示例性实施方式中，平坦层16、像素定义层34和隔离柱层41可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。
在制备完成上述膜层结构后，可以通过剥离工艺将显示基板从玻璃载板上剥离。在上述制备过程中，测试电路区域的测试电路的制备过程类似于显示区域的驱动结构层的制备过程，故于此不再赘述。
本示例性实施例提供的显示基板，通过在第二扇出区域设置多个电阻补偿单元，且电阻补偿单元与第二子数据扇出线串联连接，以补偿整个扇出区域的数据扇出线的电阻值，减少给显示区域的不同数据线提供数据信号的不同数据扇出线之间的电阻值差异，从而提高显示效果。
本示例性实施例的制备工艺利用现有成熟的制备设备即可实现，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成 本低，良品率高。
本示例性实施例的显示基板的结构及其制备过程仅仅是一种示例性说明。在一些示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，多个电阻补偿单元可以均设置在第一扇出区域，且多个电阻补偿单元可以与多条第一子数据扇出线一一对应电连接；或者，多个电阻补偿单元可以设置在第三扇出区域，且可以与多条第三子数据扇出线一一对应电连接；或者，一部分电阻补偿单元设置在第一扇出区域，与第一子数据扇出线串联且电连接，另一部分电阻补偿单元设置在第二扇出区域，与第二子数据扇出线串联且电连接；或者，一部分电阻补偿单元设置在第二扇出区域，与第二子数据扇出线串联且电连接，另一部分电阻补偿单元设置在第三扇出区域，与第三子数据扇出线串联且电连接。又如，每个电阻补偿单元的半导体结构的面积相同，可以根据每个数据扇出线所需补偿的电阻值来确定串联的电阻补偿单元的数目。又如，多条数据扇出线可以同层设置，比如，多条数据扇出线与显示区域的第一栅金属层为同层结构，或者与第二栅金属层为同层结构。然而，本实施例对此并不限定。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图8为图2中沿P-P方向的另一剖面示意图。在一些示例性实施方式中，如图8所示，在垂直于显示基板的平面内，显示区域100包括：设置在衬底基板10上的驱动结构层、设置在驱动结构层上的发光结构层。其中，驱动结构层包括：依次设置在衬底基板10上的第一绝缘层11、有源层(例如包括第一有源层21)、第二绝缘层12、第一栅金属层(例如包括第一栅电极22和第一电容电极25)、第三绝缘层13、第二栅金属层(例如包括第二电容电极26)、第四绝缘层14、第一源漏金属层(例如包括第一源电极23和第一漏电极24)、第五绝缘层15、第二源漏金属层(例如包括阳极连接电极27)、以及平坦层16。第二扇出区域203设置的电阻补偿单元的半导体结构61与显示区域100的有源层为同层结构，电阻补偿单元的导电连接结构(例如包括第一连接电极62和第二连接电极63)与显示区域100的第二源漏金属层为同层结构。然而，本实施例对此并不限定。例如，电阻补偿单元的导电连 接结构可以与显示区域的第一源漏金属层为同层结构。
本示例性实施例中的显示区域和第一边框区域的其他结构与前述实施例中描述的相应结构类似，故于此不再赘述。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图9为图2中区域S的另一局部放大示意图。在一些示例性实施方式中，如图9所示，第二扇出区域的多条第二子数据扇出线52a和多条第二子数据扇出线52b异层设置。例如，第二子数据扇出线52a与显示区域的第一栅金属层为同层结构，第二子数据扇出线52b与显示区域的第二栅金属层为同层结构。在本示例中，第二扇出区域的多条第二子数据扇出线与多个电阻补偿单元一一对应串联，且多个电阻补偿单元沿第一方向D1依次排布。第二子数据扇出线52a包括断开的第一部分521a和第二部分521b。第二子数据扇出线52a的第一部分521a具有第一端部5210和第一延伸部5211，第二子数据扇出线52a的第二部分522a具有第二端部5220和第二延伸部5221。电阻补偿单元的第一连接电极62的一端通过四个过孔与第一端部5210连接，第一连接电极62的另一端通过四个过孔与半导体结构61连接；第二连接电极63的一端通过四个过孔与第二端部5220连接，第二连接电极63的另一端通过四个过孔与半导体结构61连接。其中，第一端部5210沿第一方向D1的长度大于第一延伸部5211沿第一方向D1的长度，第二端部5220沿第一方向D1的长度大于第二延伸部5221沿第一方向D2的长度。第一端部5210沿第一方向D1的长度可以约等于第二端部5220沿第一方向D1的长度。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图9所示，第一连接电极62沿第一方向D1的长度约等于第一端部5210沿第一方向D1的长度，第二连接电极63沿第一方向D1的长度约等于第二端部5220沿第一方向D1的长度。第一连接电极62沿第一方向D1的长度约等于第二电极63沿第一方向D1的长度。半导体结构61例如为矩形，且半导体结构61沿第一方向D1的长度可以约等于第一连接电极62沿第一方向D1的长度。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图9所示，多个半导体结构61沿第一方向 D1的长度可以相同，沿第二方向D2的长度存在变化，使得多个半导体结构61的面积不同，以给对应的数据扇出线补偿不同的电阻值。在本示例中，多个半导体结构61沿第二方向D2的长度按照微米级别变化。例如，在图2所示的第二扇出区域203的第二扇出分区231内，从第二扇出区域203的边缘到中间区域的方向上，多个半导体结构沿第一方向的长度相同，沿第二方向的长度可以依次递增，例如依次为3.04微米、3.11微米、3.18微米等。
在一些示例性实施方式中，第二扇出区域内的多个电阻补偿单元靠近测试电路区域。即，多个电阻补偿单元与测试电路区域之间的距离小于与弯折区域之间的距离。在一些示例中，多条第二子数据扇出线的第二部分的第二延伸部的延伸长度相同，且沿第一方向依次排布。多条第二子数据扇出线的第一部分的第一延伸部的延伸长度大于第二部分的第二延伸部的延伸长度。在本公开中，延伸长度表示沿延伸方向的特征尺寸。
在本示例性实施方式中，通过在第二子数据扇出线的第一部分和第二部分分别设置第一端部和第二端部，可以在避免增加第二子数据扇出线的整体线宽的基础上，增加第二子数据扇出线与电阻补偿单元的导电连接结构之间的接触面积，从而提高第二子数据扇出线与电阻补偿单元之间的电连接有效性。
本示例性实施例中的显示区域和第一边框区域的其他结构与前述实施例中描述的相应结构类似，故于此不再赘述。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图10为图2中区域S的另一局部放大示意图。在一些示例性实施方式中，第二扇出区域的多条第二子数据扇出线52a和多条第二子数据扇出线52b异层设置。第二扇出区域的多条第二子数据扇出线与多个电阻补偿单元一一对应串联。每个第二扇出分区内的多个电阻补偿单元60沿第二方向D2错开排布。例如，图2所示的第二扇出区域203的第二扇出分区231内的多个电阻补偿单元与测试电路区域之间的距离可以沿着第一方向D1从第二扇出区域的边缘到中间方向递减；第二扇出分区232内的多个电阻补偿单元与测试电路区域之间的距离可以沿着第一方向D1从第二扇出区域的边缘到中间方 向递增。然而，本实施例对此并不限定。
本示例性实施例中的显示区域和第一边框区域的其他结构与前述实施例中描述的相应结构类似，故于此不再赘述。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图11为本公开至少一实施例的第一边框区域的另一示意图。在一些示例性实施方式中，如图11所示，第一边框区域200包括：位于显示区域100一侧的第一扇出区域201、位于第一扇出区域201远离显示区域100一侧的弯折区域202、位于弯折区域202远离显示区域100一侧的第二扇出区域203、位于第二扇出区域203远离显示区域100一侧的测试电路区域204、位于测试电路区域204远离显示区域100一侧的第三扇出区域205、位于第三扇出区域205远离显示区域100一侧的信号接入区域206。
在一些示例性实施方式中，如图11所示，第一扇出区域201包括两个第一扇出分区211和212。每个第一扇出分区内设置有多条第一子数据扇出线。每个第一扇出分区内的多条第一子数据扇出线的长度沿着从第一扇出区域201的边缘到中间方向先递减后递增。弯折区域202包括多个第一弯折分区(例如，沿第一方向D1依次排布的两个第一弯折分区220a、220b)、多个第二弯折分区(例如，沿着第一方向D1依次排布的三个第二弯折分区221a、221b和221c)。相邻两个第一弯折分区之间设置有至少一个第二弯折分区。每个第一弯折分区内设置有多条数据连接线，每个第二弯折分区内设置有电源连接线。第二弯折分区221b位于第一弯折分区220a和220b之间。第二扇出区域203包括两个第二扇出分区231和232。每个第二扇出分区内设置有多条第二子数据扇出线。每个第二扇出分区内的多条第二子数据扇出线的长度沿着从第二扇出区域203的边缘到中间方向递减后递增。第三扇出区域205包括两个第三扇出分区251和252。每个第三扇出分区内设置有多条第三子数据扇出线。每个第三扇出分区内的多条第三子数据扇出线的长度沿着从第三扇出区域205的边缘到中间方向递减后递增。然而，本实施例对此并不限定。例如，每个第一扇出分区内的多条第一子数据扇出线的长度沿着从第一扇出区域的边缘到中间方向可以递减，每个第二扇出分区内的多条第二子数 据扇出线的长度沿着从第二扇出区域的边缘到中间方向可以递减，每个第三扇出分区内的多条第三子数据扇出线的长度沿着从第三扇出区域的边缘到中间方向可以递减。
在一些示例性实施方式中，当多个电阻补偿单元设置在第二扇出区域203，且多个电阻补偿单元与第二扇出区域203内的多条第二子数据扇出线一一对应串联且电连接时，每个第二扇出分区内的多个电阻补偿单元的半导体结构的面积可以沿着从第二扇出区域203的边缘到中间方向先递增后递减，以补偿扇出区域的多条数据扇出线之间的电阻值差异，改善由于数据扇出线的电阻值差异导致的显示色偏或亮度不均情况，从而提高显示效果。在一些示例中，在扇出区域的数据扇出线沿着扇出区域在第一方向上从边缘到中间方向递减的情况下，每个第二扇出分区内的多个电阻补偿单元的半导体结构的面积可以沿着从第二扇出区域的边缘到中间方向递增。
本示例性实施例中的显示区域和第一边框区域的结构以及电阻补偿单元的结构与前述实施例中描述的相应结构类似，故于此不再赘述。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图12为本公开至少一实施例的第一边框区域的另一示意图。在一些示例性实施方式中，如图12所示，第一边框区域200包括：位于显示区域100一侧的第一扇出区域201、位于第一扇出区域201远离显示区域100一侧的弯折区域202、位于弯折区域202远离显示区域100一侧的第二扇出区域203、位于第二扇出区域203远离显示区域100一侧的测试电路区域204、位于测试电路区域204远离显示区域100一侧的第三扇出区域205、位于第三扇出区域205远离显示区域100一侧的信号接入区域206。
在一些示例性实施方式中，如图12所示，弯折区域202内的电源连接吸纳与数据连接线同层设置，且弯折区域202内的电源连接线位于多条数据连接线的两侧。在本示例中，由于弯折区域202内的电源连接线没有设置在多条数据连接线的中间，多条数据连接线可以依次分别连接第一扇出区域201的第一子数据扇出线和第二扇出区域203的第二子数据扇出线，扇出区域的数据扇出线的长度没有跳变。第一扇出区域201、第二扇出区域203和第三 扇出区域205内数据扇出线的长度沿着从边缘到中间方向递减。在一些示例中，当多个电阻补偿单元均设置在第二扇出区域203，且多个电阻补偿单元与第二扇出区域203内的多条第二子数据扇出线一一对应串联时，多个电阻补偿单元的半导体结构的面积可以沿着从第二扇出区域203的两侧边缘到中间方向递增，以补偿扇出区域的多条数据扇出线之间的电阻值差异，改善由于数据扇出线的电阻值差异导致的显示色偏或亮度不均情况，从而提高显示效果。
在一些示例性实施方式中，多个电阻补偿单元均设置在第二扇出区域203，多个电阻补偿单元与第二扇出区域内的多条第二子数据扇出线一一对应串联连接。第二扇出区域内的第二子数据扇出线可以包括断开的第一部分和第二部分。电阻补偿单元可以包括半导体结构和导电连接结构。导电连接结构包括第一连接电极和第二连接电极。第一连接电极连接第二子数据扇出线的第一部分和半导体结构的一端，第二连接电极连接第二子数据扇出线的第二部分和半导体结构的另一端，从而实现电阻补偿单元和第二子数据扇出线的串联电连接。
在一些示例性实施方式中，多个电阻补偿单元可以沿着第一方向D1依次排布，多个电阻补偿单元的半导体结构沿第一方向D1的长度可以相同，沿第二方向D2的长度可以从第二扇出区域的两侧边缘到中间方向递增，以使得多个电阻补偿单元的半导体结构的面积可以沿着从第二扇出区域的两侧边缘到中间方向递增。然而，本实施例对此并不限定。
本示例性实施例中的显示区域和第一边框区域的结构以及电阻补偿单元的结构与前述实施例中描述的相应结构类似，故于此不再赘述。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图13为本公开至少一实施例的第一边框区域的另一示意图。在一些示例性实施方式中，如图13所示，第一边框区域200包括：位于显示区域100一侧的扇出区域400、以及位于扇出区域400远离显示区域100一侧的信号接入区域206。扇出区域400设置有多条数据扇出线，多条数据扇出线的长度沿着从扇出区域400的两侧边缘到中间方向递减。在一些示例中，当多个 电阻补偿单元均设置在扇出区域400，且多个电阻补偿单元与扇出区域内的多条数据扇出线一一对应串联连接时，多个电阻补偿单元的半导体结构的面积可以在第一方向D1上沿着从扇出区域400的两侧边缘到中间方向递增，以补偿扇出区域的多条数据扇出线之间的电阻值差异，改善由于数据扇出线的电阻值差异导致的显示色偏或亮度不均情况，从而提高显示效果。
本示例性实施例中的显示区域和第一边框区域的结构以及电阻补偿单元的结构与前述实施例中描述的相应结构类似，故于此不再赘述。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图14为本公开至少一实施例的第一边框区域的另一示意图。在一些示例性实施方式中，如图14所示，第一边框区域200包括：位于显示区域100一侧的第一扇出区域201、位于第一扇出区域201远离显示区域100一侧的弯折区域202、位于弯折区域202远离显示区域100一侧的第二扇出区域203、位于第二扇出区域203远离显示区域100一侧的信号接入区域206。扇出区域包括第一扇出区域201和第二扇出区域203。第二扇出区域203设置有多条第二子数据扇出线，多条第二子数据扇出线的长度沿着从第二扇出区域203的两侧边缘到中间方向递减。
在一些示例中，当多个电阻补偿单元均设置在第二扇出区域203，且多个电阻补偿单元与第二扇出区域203内的多条第二子数据扇出线一一对应串联连接时，多个电阻补偿单元的半导体结构的面积可以沿着从第二扇出区域203的两侧边缘到中间方向递增，以补偿扇出区域的多条数据扇出线之间的电阻值差异，改善由于数据扇出线的电阻值差异导致的显示色偏或亮度不均情况，从而提高显示效果。
本示例性实施例中的显示区域和第一边框区域的结构以及电阻补偿单元的结构与前述实施例中描述的相应结构类似，故于此不再赘述。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图15为本公开至少一实施例的显示装置的示意图。如图15所示，本实 施例提供一种显示装置91，包括：显示基板910。显示基板910为前述实施例提供的显示基板。其中，显示基板910可以为OLED显示基板。显示装置91可以为：OLED显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。然而，本实施例对此并不限定。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (19)

  1. 一种显示基板，包括：
    衬底基板，包括显示区域和位于所述显示区域周边的边框区域，所述边框区域包括：位于所述显示区域一侧的信号接入区域、以及位于所述显示区域和所述信号接入区域之间的扇出区域；
    多个子像素，位于所述显示区域；
    多条数据线，位于所述显示区域且与所述多个子像素电连接，所述多条数据线被配置为向所述多个子像素提供数据信号；
    多个信号输入垫，位于所述信号接入区域；
    数据扇出线层，设置在所述扇出区域，所述数据扇出线层包括：多条数据扇出线，所述多条数据扇出线被配置为连接所述多条数据线和所述多个信号输入垫；
    多个电阻补偿单元，设置在所述扇出区域；所述多个电阻补偿单元中的至少一个包括半导体结构；
    所述多条数据扇出线中的至少一条与所述至少一个电阻补偿单元串联且电连接。
  2. 根据权利要求1所述的显示基板，其中，所述电阻补偿单元的半导体结构的面积与所述电阻补偿单元串联的数据扇出线需补偿的电阻值呈正比关系。
  3. 根据权利要求2所述的显示基板，其中，电阻值较小的数据扇出线所串联的电阻补偿单元的半导体结构的总面积大于电阻值较大的数据扇出线所串联的电阻补偿单元的半导体结构的总面积。
  4. 根据权利要求1至3中任一项所述的显示基板，其中，所述多个电阻补偿单元中的至少一个还包括导电连接结构，所述半导体结构和所述导电连接结构依次设置在所述衬底基板上，且所述半导体结构和所述导电连接结构电连接。
  5. 根据权利要求4所述的显示基板，其中，所述电阻补偿单元的导电连 接结构包括：第一连接电极和第二连接电极；
    与所述电阻补偿单元串联连接的数据扇出线包括断开的第一部分和第二部分；所述数据扇出线的第一部分通过所述第一连接电极与所述电阻补偿单元的半导体结构连接，所述数据扇出线的第二部分通过所述第二连接电极与所述半导体结构连接。
  6. 根据权利要求5所述的显示基板，其中，所述第一部分具有相互连接的第一端部和第一延伸部，所述第二部分具有相互连接的第二端部和第二延伸部；所述第一端部通过所述第一连接电极与所述半导体结构连接，所述第二端部通过所述第二连接电极与所述半导体结构连接；
    所述第一端部沿第一方向的长度大于所述第一延伸部沿第一方向的长度，所述第二端部沿第一方向的长度所述第二延伸部沿第一方向的长度；
    所述第一方向垂直于所述显示区域的数据线的延伸方向。
  7. 根据权利要求1至6中任一项所述的显示基板，其中，所述扇出区域内的所述多条数据扇出线与所述多个电阻补偿单元一一对应串联且电连接。
  8. 根据权利要求7所述的显示基板，其中，所述多个电阻补偿单元沿着垂直于所述显示区域的数据线的延伸方向的方向依次排布，或者，沿着平行于所述显示区域的数据线的延伸方向的方向错开排布。
  9. 根据权利要求7所述的显示基板，其中，沿着从所述扇出区域的边缘到中间的方向上，所述扇出区域内的多条数据扇出线电连接的电阻补偿单元的半导体结构的总面积递增，或者，先递增后递减。
  10. 根据权利要求7所述的显示基板，其中，所述扇出区域在垂直于所述显示区域的数据线的延伸方向的方向上具有多个扇出分区；
    至少一个扇出分区内的多条数据扇出线电连接的电阻补偿单元沿着垂直于所述显示区域的数据线的延伸方向的方向依次排布，或者，沿着平行于所述显示区域的数据线的延伸方向的方向错开排布。
  11. 根据权利要求10所述的显示基板，其中，沿着从所述扇出区域的边缘到中间的方向上，至少一个扇出分区内的多条数据扇出线电连接的电阻补偿单元的半导体结构的总面积递增，或者，先递增后递减。
  12. 根据权利要求1至11中任一项所述的显示基板，其中，所述电阻补偿单元的半导体结构位于所述数据扇出线层靠近所述衬底基板的一侧，所述电阻补偿单元的导电连接结构位于所述数据扇出线层远离所述衬底基板的一侧。
  13. 根据权利要求1至12中任一项所述的显示基板，其中，所述边框区域还包括：位于所述信号接入区域和所述显示区域之间的弯折区域；
    所述扇出区域包括：位于所述显示区域和弯折区域之间的第一扇出区域、位于所述弯折区域和所述信号接入区域之间的第二扇出区域；
    所述至少一条数据扇出线包括：位于第一扇出区域的第一子数据扇出线、以及位于第二扇出区域且与所述第一子数据扇出线连接的第二子数据扇出线；
    所述至少一个电阻补偿单元被配置为满足以下之一：
    设置在所述第一扇出区域且与至少一条第一子数据扇出线串联且电连接；
    设置在所述第二扇出区域且与至少一条第二子数据扇出线串联且电连接。
  14. 根据权利要求1至12中任一项所述的显示基板，其中，所述边框区域还包括：位于所述信号接入区域和所述显示区域之间的弯折区域、位于所述弯折区域和信号接入区域之间的测试电路区域；
    所述扇出区域包括：位于所述显示区域和弯折区域之间的第一扇出区域、位于所述弯折区域和所述测试电路区域之间的第二扇出区域、以及位于所述测试电路区域和所述信号接入区域之间的第三扇出区域；
    所述至少一条数据扇出线包括：位于第一扇出区域的第一子数据扇出线、位于第二扇出区域且与所述第一子数据扇出线电连接的第二子数据扇出线、以及位于第三扇出区域且与所述第二子数据扇出线电连接的第三子数据扇出线；
    所述至少一个电阻补偿单元被配置为满足以下之一：
    设置在所述第一扇出区域且与至少一条第一子数据扇出线串联且电连接；
    设置在所述第二扇出区域且与至少一条第二子数据扇出线串联且电连接；
    设置在所述第三扇出区域且与至少一条第三子数据扇出线串联且电连接。
  15. 根据权利要求13或14所述的显示基板，其中，所述多个电阻补偿单元均设置在所述第二扇出区域，且所述第二扇出区域内的至少一条第二子数据扇出线与至少一个电阻补偿单元串联且电连接。
  16. 根据权利要求15所述的显示基板，其中，设置在所述第二扇出区域内的所述多个电阻补偿单元靠近测试电路区域或靠近所述信号接入区域。
  17. 根据权利要求1至16中任一项所述的显示基板，其中，所述数据扇出线层包括：依次设置在所述衬底基板上且相互绝缘的第一数据扇出线层和第二数据扇出线层；
    所述第一数据扇出线层包括多条第一数据扇出线，所述第二数据扇出线层包括多条第二数据扇出线；
    所述第一数据扇出线层和所述第二数据扇出线层在所述衬底基板上的正投影没有交叠，且所述多条第一数据扇出线和多条第二数据扇出线间隔排布。
  18. 根据权利要求17所述的显示基板，其中，所述显示区域至少包括：设置在所述衬底基板上的驱动结构层、设置在所述驱动结构层上的发光元件；所述发光元件与驱动结构层电连接；
    所述驱动结构层包括：依次设置在所述衬底基板上的有源层、第一栅金属层、第二栅金属层以及源漏金属层；
    所述第一数据扇出层与所述第一栅金属层为同层结构，所述第二数据扇出层与所述第二栅金属层为同层结构；所述电阻补偿单元的半导体结构与所述有源层为同层结构；所述电阻补偿单元的导电连接结构与所述源漏金属层为同层结构。
  19. 一种显示装置，包括如权利要求1至18中任一项所述的显示基板。
PCT/CN2020/137121 2020-12-17 2020-12-17 显示基板及显示装置 WO2022126469A1 (zh)

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