WO2022062740A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2022062740A1
WO2022062740A1 PCT/CN2021/111729 CN2021111729W WO2022062740A1 WO 2022062740 A1 WO2022062740 A1 WO 2022062740A1 CN 2021111729 W CN2021111729 W CN 2021111729W WO 2022062740 A1 WO2022062740 A1 WO 2022062740A1
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Prior art keywords
layer
insulating layer
substrate
display
lead
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PCT/CN2021/111729
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English (en)
French (fr)
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夏维
高涛
郭远征
任怀森
李�杰
韩永占
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/789,518 priority Critical patent/US20230040064A1/en
Publication of WO2022062740A1 publication Critical patent/WO2022062740A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H05K3/3426—Leaded components characterised by the leads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/03002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/80—Manufacture or treatment specially adapted for the organic devices covered by this subclass using temporary substrates

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular, relate to a display substrate, a method for manufacturing the same, and a display device.
  • the development trend of displays is to be thinner and thinner, with narrower bezels or no bezels.
  • Some methods of realizing a narrow frame for the lower frame of some display substrates are to adopt a Pad Bending structure. By designing a bending area, the binding area is bent to the back of the display substrate to achieve a narrow frame. This method is adopted.
  • the width of the lower frame of the display substrate can be reduced to about 3.0mm.
  • the display substrate using the Pad Bending structure is prone to film peeling, cracking and other problems in the bending area.
  • the yield of the display substrate is relatively low, and due to the limitation of the bending radius, the reduction of the width of the lower frame will increase the technical difficulty.
  • An embodiment of the present disclosure provides a display substrate, which includes a display area and a binding area on one side of the display area, the binding area includes a binding structure layer disposed on a substrate, and the binding structure layer includes a binding structure layer disposed on the substrate.
  • the composite insulating layer on the substrate, the binding area further includes a step structure formed by the substrate and the composite insulating layer, and the height of the steps in the step structure decreases sequentially in the direction away from the display area , in the step structure, the substrate forms a first step with the smallest height;
  • the binding structure layer further includes a signal connection line, and at least a part of the signal connection line is arranged on the step structure and located in the first step.
  • the substrate at the first step is provided with an opening for exposing the signal connection wire, and the portion of the signal connection wire exposed by the opening forms a binding pin.
  • Embodiments of the present disclosure also provide a display device, including the display substrate.
  • An embodiment of the present disclosure further provides a method for manufacturing a display substrate, the display substrate includes a display area and a binding area on one side of the display area, and the manufacturing method includes:
  • a composite insulating layer is formed on the substrate of the binding area, the substrate and the composite insulating layer form a stepped structure, and the heights of the steps in the stepped structure decrease sequentially in the direction away from the display area, and the In the step structure, the substrate forms a first step with the smallest height;
  • a signal connection line is formed in the binding area, and at least a part of the signal connection line is arranged on the step structure and located on the first step;
  • An opening is formed on the substrate at the first step, the opening exposes the signal connection line, and a portion of the signal connection line exposed by the opening forms a binding pin.
  • FIG. 1 is a schematic plan view of a bonding area of a display substrate in some technologies
  • Fig. 2 is the A-A sectional structure schematic diagram of Fig. 1;
  • FIG. 3 is a schematic plan view of a binding area of a display substrate according to some exemplary embodiments
  • FIG. 4 is a schematic diagram of the cross-sectional structure along the line B-B of FIG. 3 in some exemplary embodiments;
  • FIG. 5 is a schematic view of the structure after forming a substrate in some exemplary embodiments
  • FIG. 6 is a schematic structural diagram after forming a first composite insulating layer and a first stepped structure in some exemplary embodiments
  • FIG. 7 is a schematic structural diagram after forming a metal wiring layer and a fifth insulating layer in some exemplary embodiments.
  • FIG. 8 is a schematic diagram of the structure after forming the planarization layer, the anode, the pixel defining layer and the spacer pillar in some exemplary embodiments;
  • FIG. 9 is a schematic structural diagram after forming an organic light-emitting layer, a cathode and an encapsulation structure layer in some exemplary embodiments;
  • FIG. 10 is a schematic view of the structure after attaching an auxiliary film layer and forming an opening on a substrate in some exemplary embodiments;
  • FIG. 11 is a schematic diagram showing a partial cross-sectional structure of a substrate in other exemplary embodiments.
  • FIG. 12 is a schematic structural diagram after forming a substrate in other exemplary embodiments.
  • FIG. 13 is a schematic structural diagram after forming a second composite insulating layer and a second step structure in other exemplary embodiments
  • FIG. 14 is a schematic structural diagram after forming a first metal conductive layer in other exemplary embodiments.
  • FIG. 15 is a schematic structural diagram after forming a third insulating layer and a second metal conductive layer in other exemplary embodiments
  • FIG. 16 is a schematic structural diagram after forming a fourth insulating layer, a metal wiring layer and a fifth insulating layer in other exemplary embodiments;
  • FIG. 17 is a schematic diagram of the structure after forming the planarization layer, the anode, the pixel defining layer and the spacer column in other exemplary embodiments;
  • FIG. 18 is a schematic structural diagram after forming an organic light-emitting layer, a cathode and an encapsulation structure layer in other exemplary embodiments;
  • FIG. 19 is a schematic structural diagram after attaching an auxiliary film layer and forming an opening on a substrate in other exemplary embodiments.
  • FIG. 20 is a schematic plan view of the display substrate of FIG. 11 in other exemplary embodiments.
  • FIG. 21 is a schematic diagram showing a partial cross-sectional structure of a substrate in further exemplary embodiments.
  • a chip on film (COF for short) method or a chip on substrate (Chip On Pi, for short) method mounts the driver chip on the display substrate.
  • the lower border area ie the binding area
  • the binding pin area includes the wiring area and the binding pin area.
  • the driver chip (Integrated Circuit, IC for short) is fixed on the body of the thin film circuit board of the COF, and the COF is bound on the display substrate .
  • the driver IC is located on the back side of the display substrate, and the driver IC does not need to be bound on the display substrate, thereby reducing the width of the lower border of the display substrate, but the COF solution cannot satisfy the narrower border. need.
  • the COP scheme bends the binding area of the display substrate to the back of the display substrate, and the flexible printed circuit (FPC) and the driver chip are bound to the binding area bent to the back of the display substrate, so it can greatly reduce the downtime.
  • the width of the frame, the COP scheme can reduce the width of the lower frame to about 2.5mm.
  • a schematic diagram of the plane structure of the display substrate in the COP scheme is shown in FIG. 1 .
  • the display substrate includes a display area 100 and a binding area 200 located on one side of the display area 100 .
  • the first fan-out area 201 , the bending area 202 , the anti-static area 203 , the second fan-out area 204 and the bonding pin area 205 wherein, in the binding area bending process of the COP scheme, the binding area 200 is bent to the back side of the display area 100 along the bending area 202 .
  • the first fan-out area 201 includes a plurality of data connection lines, and the plurality of data connection lines are configured to connect the data lines (Data Lines) of the display area 100 in a fan-out (Fanout) routing manner, and the second fan-out area 204 includes A plurality of data connection lines drawn out by way of wiring.
  • the anti-static area 203 includes an anti-static circuit configured to prevent electrostatic damage to the display substrate by eliminating static electricity.
  • the bonding pin area 205 includes a plurality of bonding pads, and the bonding pads can be configured to be bonded and connected to the flexible circuit board and the driver chip.
  • the driver IC receives the signal transmitted by the FPC, and drives the display substrate (Panel) to display.
  • FIG. 2 is a cross-sectional view along AA of the display substrate of FIG. 1 .
  • the bending area 202 includes signal wire leads (such as data connection wires) 210
  • the binding pin area 205 includes binding pins connected to the signal wire leads 210 .
  • Fixed pad 220 Fixed pad 220 .
  • the bending area 202 In the COP scheme, in the bending process of the bonding area, the bending area 202 often has defects such as peeling, cracking, metal line corrosion, etc. Therefore, the display substrate using the COP scheme has a low yield and is subject to Limited by the bending radius, it is difficult to reduce the width of the lower frame of the display substrate.
  • FIG. 3 shows a schematic plan view of the display substrate of the present disclosure.
  • the display substrate includes a display area 100 and a binding area 200 on one side of the display area 100 .
  • the binding area 200 may include a first fan-out area 201, an anti-static area 203, a second fan-out area 204 and a binding pin area 205 that are sequentially arranged along a direction away from the display area 100.
  • the first fan-out area 201 may include a plurality of signal leads, such as a plurality of data connection lines, and the plurality of data connection lines are configured to connect the data lines of the display area 100 in a fan-out wiring manner.
  • the second fan-out area 204 includes a plurality of signal leads (eg, a plurality of data connection lines) drawn out in a fan-out routing manner.
  • the anti-static area 203 includes an anti-static circuit configured to prevent electrostatic damage to the display substrate by eliminating static electricity.
  • the bonding pin area 205 includes a plurality of bonding pins (or bonding pads, Bonding Pads). The bonding pins can be configured to be bound and connected to one end of the chip-on-chip film, and the other end of the chip-on-chip film is configured as Binding connection with flexible circuit board.
  • the chip on film receives the signal transmitted from the flexible circuit board, and transmits the output signal to the display substrate to drive the display substrate to display.
  • FIG. 4 shows a BB cross-sectional view of the display substrate of FIG. 3 .
  • the display substrate of an embodiment of the present disclosure includes a display area 100 and a binding area 200 located on one side of the display area 100 .
  • the fixed area 200 includes a binding structure layer disposed on the substrate 10, the binding structure layer includes a first composite insulating layer disposed on the substrate 10, and the binding area 200 further includes the substrate 10 and the The first step structure formed by the first composite insulating layer, the height of the steps in the first step structure decreases in turn in the direction away from the display area 100, and the substrate 10 is formed in the first step structure
  • the first step 51 with the smallest height; the binding structure layer further includes a signal connection line, at least a part of the signal connection line is arranged on the first step structure and located on the first step 51, the first step 51
  • the substrate 10 at a step 51 is provided with an opening 40 for exposing the signal connection line, and the portion of the signal connection line exposed by the opening 40 forms a binding pin 41 .
  • the display substrate of the embodiment of the present disclosure at least a part of the signal connection lines of the binding area 200 is disposed on the first step structure and located on the substrate 10 , and the opening 40 is disposed on the substrate 10 to expose the signal connection lines, and The part of the signal connection line exposed by the opening 40 is used as the binding pin 41, so that when the display substrate is bound and connected with the external circuit board, the external circuit board can be bound on the back side of the display substrate (ie, the one facing away from the display side).
  • the binding area 200 of the display substrate does not need to be bent to the back side of the display substrate, and thus the binding area 200 of the display substrate may not be provided with a bend for bending the binding area 200
  • the folding area can reduce defects such as film peeling and cracking caused by the bending of the binding area 200, improve product yield, and The frame width of the side where the binding area 200 of the display substrate is located can be reduced.
  • the bonding structure layer further includes a metal wiring layer disposed on the first composite insulating layer, and the metal wiring layer includes a connection with the display area.
  • the signal lead 18C connected to the signal line of 100; the signal connection line includes the signal lead 18C, the signal lead 18C is arranged on the first step structure and located on the first step 51, the signal lead The portion of 18C exposed by the opening 40 forms the binding pin 41 .
  • the display region 100 includes a driving structure layer and a light emitting structure layer disposed on the driving structure layer, the driving structure layer is provided with a pixel driving circuit, and the The driving structure layer includes a source-drain metal layer, the source-drain metal layer includes a source electrode 18A and a drain electrode 18B, and the metal wiring layer is provided in the same layer as the source-drain metal layer.
  • the driving structure layer of the display area 100 includes a pixel driving circuit, and the pixel driving circuit includes a plurality of transistors and a storage capacitor.
  • FIG. 4 takes one driving transistor and one storage capacitor as an example for illustration.
  • the driving structure layer of the display area 100 includes a first insulating layer 11 disposed on the flexible substrate 10, an active layer 12 disposed on the first insulating layer 11, and a second insulating layer 13 covering the active layer 12, disposed on the first insulating layer 11.
  • the first gate metal layer includes at least a gate electrode 14A and a first capacitor electrode 14B
  • the second gate metal layer includes at least a second capacitor electrode 16A
  • the source-drain metal layer includes at least a source electrode 18A and a drain electrode 18B.
  • the active layer 12, the gate electrode 14A, the source electrode 18A, and the drain electrode 18B constitute a driving transistor.
  • the first capacitor electrode 14B and the second capacitor electrode 16A constitute a storage capacitor.
  • a flat layer 20 may be provided on the driving structure layer of the display area 100 , the flat layer 20 may be provided on the fifth insulating layer 19 , and the light emitting structure layer may be provided on the flat layer 20 .
  • the light emitting structure layer includes: an anode 21 , a pixel defining layer 22 , an organic light emitting layer 24 and a cathode 25 disposed on the flat layer 20 .
  • the organic light emitting layer 24 may be disposed within the opening of the pixel defining layer 22 and between the anode 21 and the cathode 25 , and the organic light emitting layer 24 emits light at a voltage between the anode 21 and the cathode 25 .
  • the display area 100 further includes an encapsulation structure layer disposed on the light emitting structure layer, and the encapsulation structure layer may include a first inorganic encapsulation layer 26 , an organic encapsulation layer 27 and a second inorganic encapsulation layer 28 .
  • the substrate 10 includes a first flexible layer 10A, a first barrier layer 10B, an amorphous silicon layer 10C, a second flexible layer 10D and a second barrier layer 10E stacked in sequence.
  • the first composite insulating layer of the bonding region 200 includes a first insulating layer 11, a second insulating layer 13, a third insulating layer 15 and a fourth insulating layer 17 stacked on the second barrier layer 10E;
  • a stepped structure includes a first step 51 formed by the first flexible layer 10A, the first barrier layer 10B, the amorphous silicon layer 10C and the second flexible layer 10D, the second barrier layer 10E and the first insulating layer 11, and the third step 53 formed by the second insulating layer 13, the third insulating layer 15 and the fourth insulating layer 17, the first step 51, the second step 52 and the third step 53
  • the heights of the steps 53 increase sequentially; the signal leads 18C are arranged on the third step 53 , the second step 52 and the first step 51 .
  • the substrate 10 includes the stacked second flexible layer 10D and the second barrier layer 10E, and does not include the first flexible layer 10A, the first barrier layer 10B and the amorphous silicon layer 10C, then, the first A step 51 includes the second flexible layer 10D and does not include the first flexible layer 10A, the first barrier layer 10B and the amorphous silicon layer 10C.
  • the height of the step refers to the distance from the surface of the step to the surface of the flexible substrate 10 facing away from the display side.
  • the height h1 of the first step 51 , the height h2 of the second step 52 , and the height h3 of the third step 53 increase sequentially.
  • the width s1 of the first step 51 may be the distance from the edge of the second flexible layer 10D to the edge of the second step 52
  • the width s2 of the second step 52 may be the edge of the second step 52
  • the distance to the edge of the third step 53 , the width s3 of the third step 53 may be the distance from the edge of the third step 53 to the edge of the display area 100 .
  • the structure of the display substrate of the present disclosure will be described below through an example of a preparation process of the display substrate.
  • the "patterning process” referred to in the present disclosure includes processes such as depositing film layers, coating photoresist, mask exposure, developing, etching and stripping photoresist.
  • Deposition can be selected from any one or more of sputtering, evaporation and chemical vapor deposition, coating can be selected from any one or more of spray coating and spin coating, and etching can be selected from dry etching. and any one or more of wet engraving.
  • “Film” refers to a thin film made of a material on a substrate by a deposition or coating process.
  • the "film” may be referred to as a "layer”.
  • the "film” needs a patterning process in the entire manufacturing process, it is called a “film” before the patterning process, and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process.
  • the orthographic projection of A includes the orthographic projection of B means that the orthographic projection of B falls within the range of the orthographic projection of A, or the orthographic projection of A covers the orthographic projection of B.
  • the manufacturing process of the display substrate of FIG. 4 may include the following steps:
  • the flexible substrate 10 is prepared on the glass carrier plate 1 .
  • the flexible substrate 10 may adopt a two-layer flexible layer structure, and the flexible substrate 10 includes a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, a second A flexible material layer and a second inorganic material layer.
  • the material of the first flexible material layer and the second flexible material layer can be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated soft polymer film.
  • the first inorganic material is The material of the layer and the second inorganic material layer can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate.
  • the first inorganic material layer and the second inorganic material layer are called barrier ( Barrier) layer
  • the material of the semiconductor layer can be amorphous silicon (a-si).
  • the preparation process of the flexible substrate 10 may include: firstly coating a layer of polyimide on the glass carrier 1 , forming a first flexible (PI1) layer 10A after curing into a film; then depositing a barrier film on the first flexible layer 10A to form a first barrier (Barrier1) layer 10B covering the first flexible layer 10A; A layer of amorphous silicon film is deposited on the barrier layer 10B to form an amorphous silicon (a-si) layer 10C covering the first barrier layer 10B; then a layer of polyimide is coated on the amorphous silicon layer 10C and cured After film formation, a second flexible (PI2) layer 10D is formed; then a barrier film is deposited on the second flexible layer 10D to
  • the flexible substrate 10 may adopt a one-layer flexible layer structure.
  • the flexible substrate 10 includes a stacked flexible (PI) layer and a barrier (Barrier) layer. After the first flexible (PI1) layer 10A, the first barrier (Barrier1) layer 10B and the amorphous silicon (a-si) layer 10C are removed, the stacked second flexible (PI2) layer 10D and the second barrier (Barrier2) layer remain. ) layer 10E.
  • the flexible substrate 10 adopts a one-layer flexible layer structure rather than a two-layer flexible layer structure, which facilitates the subsequent opening 40 on the flexible substrate 10 .
  • the preparation process of this step may include:
  • a first insulating film and an active layer film are sequentially deposited on the flexible substrate 10 , and the active layer film is patterned through a patterning process to form a first insulating layer 11 covering the entire flexible substrate 10 and disposed on the first insulating layer 11
  • the active layer pattern is formed in the display area 100 and includes at least the active layer 12 .
  • the binding region 200 includes the first insulating layer 11 disposed on the flexible substrate 10 .
  • a second insulating film and a first metal film are sequentially deposited, and the first metal film is patterned through a patterning process to form a second insulating layer 13 covering the pattern of the active layer, and a first insulating layer 13 disposed on the second insulating layer 13
  • the gate metal layer pattern is formed in the display area 100 and includes at least a gate electrode 14A and a first capacitor electrode 14B.
  • the bonding region 200 includes the first insulating layer 11 and the second insulating layer 13 stacked on the flexible substrate 10 .
  • a third insulating film and a second metal film are sequentially deposited, and the second metal film is patterned through a patterning process to form a third insulating layer 15 covering the first gate metal layer, and a third insulating layer 15 disposed on the third insulating layer 15.
  • Two gate metal layer patterns are formed in the display area 100 and includes at least a second capacitor electrode 16A, and the position of the second capacitor electrode 16A corresponds to the position of the first capacitor electrode 14B.
  • the bonding area 200 includes the first insulating layer 11 , the second insulating layer 13 and the third insulating layer 15 stacked on the flexible substrate 10 .
  • a fourth insulating film is deposited, the fourth insulating film in the display area 100 is patterned by a patterning process, and the composite insulating film in the binding area 200 (the composite insulating film includes the first insulating layer 11 stacked on the flexible substrate 10 ) is patterned.
  • the second insulating layer 13, the third insulating layer 15 and the fourth insulating film) are patterned, the fourth insulating layer 17 pattern covering the second gate metal layer is formed in the display area 100, and the first step structure is formed in the binding area 200.
  • the patterning process in this step can be performed by the following two patterning processes:
  • the fourth insulating film, the third insulating layer 15 and the second insulating layer 13 in the display area 100 and the bonding area 200 are etched using the first mask, and the fourth insulating film and the third insulating layer 15 in the display area 100 are etched.
  • a via hole 17A and a via hole 17B are formed on the second insulating layer 13 and the fourth insulating film, the third insulating layer 15 and the second insulating layer 13 in the via hole 17A and the via hole 17B are etched away, exposing the active surface of layer 12 .
  • a first groove is formed on the fourth insulating film, the third insulating layer 15 and the second insulating layer 13 in the bonding region 200, and the fourth insulating film, the third insulating layer 15 and the second insulating layer in the first groove 13 is etched away, exposing the surface of the first insulating layer 11 .
  • the first insulating layer 11 in the first groove in the bonding area 200 and the second barrier layer 10E of the flexible substrate 10 are etched by using a second mask, and the first insulating layer 11 and the second barrier layer 10E are formed on the first insulating layer 11 and the second barrier layer 10E In the second groove, the first insulating layer 11 and the second barrier layer 10E in the second groove are etched away, exposing the surface of the second flexible layer 10D of the flexible substrate 10 .
  • the first groove exposes the second groove
  • the second groove exposes the second flexible layer 10D of the flexible substrate 10, thereby forming a first stepped structure
  • the first stepped structure includes The first step 51 formed by the first flexible layer 10A, the first barrier layer 10B, the amorphous silicon layer 10C and the second flexible layer 10D, and the second step formed by the second barrier layer 10E and the first insulating layer 11 52, and a third step 53 formed by the second insulating layer 13, the third insulating layer 15 and the fourth insulating layer 17, the heights of the first step 51, the second step 52 and the third step 53 increase sequentially Big.
  • the first step 51 includes the second flexible layer 10D, but does not include the first flexible layer 10A, the first barrier layer 10B and the amorphous silicon layer 10C.
  • a first composite insulating layer is formed in the binding area 200 .
  • the first composite insulating layer includes the first insulating layer 11 , the second insulating layer 13 , the The third insulating layer 15 and the fourth insulating layer 17 .
  • the first composite insulating layer and the flexible substrate 10 form a first stepped structure, and the first stepped structure includes a first step 51 , a second step 52 , and a third step 53 , the first step 51 , the second step 52 and the third step 53 The heights of the steps 53 are sequentially increased.
  • a third metal film is deposited on the flexible substrate 10 formed with the aforementioned pattern, the third metal film is patterned through a patterning process, and a source-drain metal is formed on the fourth insulating layer 17 of the display area 100 layer pattern, a metal wiring layer pattern is formed on the first step structure of the bonding area 200 .
  • the source-drain metal layer includes a source electrode 18A and a drain electrode 18B.
  • the source electrode 18A is connected to the surface of the active layer 12 away from the flexible substrate 10 through the via hole 17A, and the drain electrode 18B is connected to the active layer 12 through the via hole 17B.
  • the surface of the layer 12 remote from the flexible substrate 10 is attached.
  • the metal wiring layer includes the signal leads 18C disposed on the first step 51 , the second step 52 and the third step 53 of the first step structure.
  • a fifth insulating film is deposited on the display area 100 and the bonding area 200 to form a pattern of the fifth insulating layer 19 covering the source-drain metal layer and the metal wiring layer.
  • the driving structure layer pattern is prepared in the display area 100 of the flexible substrate 10, and the film layer of the binding structure layer is prepared in the binding area 200.
  • the active layer 12, the gate electrode 14A, the source electrode 18A and the drain electrode 18B form a transistor, which can be a driving transistor in a pixel driving circuit.
  • the first capacitor electrode 14B and the second capacitor electrode 16A constitute a storage capacitor.
  • the first insulating film, the second insulating film, the third insulating film, the fourth insulating film, and the fifth insulating film may employ silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride Any one or more of (SiON), which may be a single layer, a multi-layer or a composite layer.
  • the first insulating layer 11 is called a buffer layer, which is used to improve the water and oxygen resistance of the flexible substrate 10
  • the second insulating layer 13 and the third insulating layer 15 are called a gate insulating (GI) layer
  • the fourth insulating layer 17 Called the interlayer insulating (ILD) layer
  • the fifth insulating layer is called the passivation (PVX) layer.
  • the first metal thin film, the second metal thin film, and the third metal thin film can be made of metal materials, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo).
  • Various, or alloy materials of the above metals can be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti and the like.
  • the active layer film can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si) , hexathiophene or polythiophene, that is, the present disclosure is applicable to transistors fabricated based on oxide technology, silicon technology or organic technology.
  • the flat layer 20 is formed on the flexible substrate 10 formed with the aforementioned pattern, the anode 21 and the pixel defining layer 22 of the light emitting structure layer are formed in the display area 100, and the spacer column 23 is formed in the binding area 200, as shown in FIG. 8 Show.
  • a flat thin film of organic material is coated on the flexible substrate 10 formed with the aforementioned pattern to form a planarization (PLN) layer 20 covering the entire flexible substrate 10, and through masking, exposing, and developing processes, A via hole is formed on the flat layer 20 and the fifth insulating layer 19 of the display area 100 , and the flat layer 20 and the fifth insulating layer 19 in the via hole are developed away to expose the surface of the drain electrode 18B of the driving transistor.
  • PPN planarization
  • a transparent conductive film is deposited on the flexible substrate 10 formed with the aforementioned pattern, and the transparent conductive film is patterned through a patterning process to form an anode 21 pattern.
  • the anode 21 is formed on the flat layer 20 of the display area 100.
  • the via on layer 19 is connected to the drain electrode 18B of the drive transistor. After this patterning process, the film layer structure of the binding region 200 does not change.
  • the material of the transparent conductive film may be indium tin oxide (ITO) or indium zinc oxide (IZO).
  • a pixel-defining film is coated on the flexible substrate 10 formed with the aforementioned pattern, and a pixel-defining (PDL) layer 22 pattern is formed by masking, exposing, and developing processes.
  • the pixel defining layer 22 is formed on the display area 100 and a partial area of the binding area 200 adjacent to the display area 100.
  • a pixel opening is formed on the pixel defining layer 22 of the display area 100, and the pixel defining layer 22 in the pixel opening is developed and exposed. out of the surface of the anode 21 .
  • a thin film of organic material is coated on the flexible substrate 10 formed with the aforementioned pattern, and a plurality of spacer pillars (PS) 23 patterns are formed by masking, exposing and developing processes, and the plurality of spacer pillars 23 are formed in the pixels of the binding area 200 on the defining layer 22 .
  • PS spacer pillars
  • An organic light-emitting layer 24 , a cathode 25 , and an encapsulation structure layer are formed on the flexible substrate 10 formed with the aforementioned pattern, as shown in FIG. 9 .
  • the organic light emitting layer 24 may be formed in the pixel opening of the pixel defining layer 22 in the display area 100 by an evaporation process, so as to realize the connection between the organic light emitting layer 24 and the anode 21 .
  • the cathode 25 is formed on the pixel defining layer 22 , is connected to the organic light emitting layer 24 , and wraps the plurality of spacer pillars 23 on the pixel defining layer 22 of the binding region 200 .
  • the material of the cathode 25 may use any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or use the aforementioned metals Alloys made of any one or more of them.
  • An encapsulation structure layer is formed on the flexible substrate 10 formed with the aforementioned pattern, and the encapsulation structure layer may include a stacked first inorganic encapsulation layer 26 , an organic encapsulation layer 27 and a second inorganic encapsulation layer 28 .
  • the first inorganic encapsulation layer 26 covers the cathode 25 in the display area 100 and wraps the plurality of spacer pillars 23 in the binding area 200 .
  • the organic encapsulation layer 27 is disposed on the display area 100 and the area where the spacer pillars 23 of the binding area 200 are located.
  • the second inorganic encapsulation layer 28 covers the first inorganic encapsulation layer 26 and the organic encapsulation layer 27 .
  • the auxiliary film layer may include a stacked protective layer film 31 and heat dissipation film 32 and the like.
  • An opening 40 is formed on the flexible substrate 10 and the auxiliary film layer at a position corresponding to the first step 51 , the opening 40 exposes the signal lead 18C on the first step 51 , and the portion of the signal lead 18C exposed by the opening 40 forms a binding pin 41.
  • the area where the binding pins 41 are formed in the binding area 200 is the binding pin area 205, and the binding pins 41 of the binding pin area 205 can be bound and connected with an external circuit board, as shown in FIG. 10 .
  • the COF can be used to bind the driving IC on the display substrate.
  • the COF 60 includes a thin film circuit board body and a driving IC 61 fixed on the thin film circuit board body. One end of the film circuit board body is bound and connected to the binding pin 41 of the display substrate, and the other end is bound and connected to the FPC 70 . Both the COF 60 and the FPC 70 can be fixed to the surface of the display substrate facing away from the display side by an adhesive.
  • the COF 60 receives the signal transmitted from the FPC 70, and transmits the output signal to the display substrate to drive the display substrate to display.
  • the bonding pins 41 can be directly bonded and connected to the driver IC or FPC, and the driver IC or FPC is directly bonded to the back side of the display substrate.
  • FIG. 11 shows another BB cross-sectional view of the display substrate of FIG. 3 .
  • the display substrate of an embodiment of the present disclosure includes a display area 100 and a binding area 200 located on one side of the display area 100 .
  • the binding area 200 includes a binding structure layer disposed on the substrate 10
  • the binding structural layer includes a second composite insulating layer disposed on the substrate 10
  • the binding area 200 further includes a structure formed by the substrate 10 .
  • the binding structure layer further includes a signal connection line, at least a part of the signal connection line is arranged on the second step structure and located on the first step 91, the The substrate 10 at the first step 91 is provided with an opening 40 for exposing the signal connection line, and the portion of the signal connection line exposed by the opening 40 forms a binding pin 41 .
  • the display substrate of the embodiment of the present disclosure at least a part of the signal connection lines of the binding area 200 is disposed on the second step structure and located on the substrate 10, and the opening 40 is disposed on the substrate 10 to expose the signal connection lines, and The part of the signal connection line exposed by the opening 40 is used as the binding pin 41, so that when the display substrate is bound and connected with the external circuit board, the external circuit board can be bound on the back side of the display substrate (ie, the one facing away from the display side).
  • the binding area 200 of the display substrate does not need to be bent to the back side of the display substrate, and thus the binding area 200 of the display substrate may not be provided with a bend for bending the binding area 200
  • the folding area can reduce defects such as film peeling and cracking caused by the bending of the binding area 200, improve product yield, and The frame width of the side where the binding area 200 of the display substrate is located can be reduced.
  • the bonding structure layer further includes a first metal conductive layer provided on the second composite insulating layer, and a metal conductive layer provided on the first metal conductive layer.
  • the bonding structure layer further includes a second metal conductive layer disposed between the first metal conductive layer and the metal wiring layer.
  • the two metal conductive layers include a second connecting lead 16B, the second connecting lead 16B is connected to the first connecting lead 14C through a first via V1, and the signal lead 18C is connected to the second connecting lead 18C through a second via V2
  • the connection lead 16B is connected.
  • the first via hole V1 is disposed closer to the display area 100 than the second via hole V2 , and the opening 40 is closer to the display area 100 than the first via hole V2
  • the via hole V1 is disposed away from the display area 100 .
  • FIG. 20 shows a schematic plan view of the display substrate shown in FIG. 11 .
  • the area where the signal lead 18C is located is the first fan-out area 230
  • the area where the second connecting lead 16B is located is the first fan-out area 230
  • the area where the first connection lead 14C is located is the third fan-out area 250 .
  • the signal lead 18C is connected to the second connection lead 16B through the second via hole V2
  • the second connection lead 16B is connected to the first connection lead 14C through the first via hole V1
  • the end of the first connection lead 14C away from the display area 100 is opened 40 is exposed to form bonding pins 41 .
  • the first fan-out area 230 is located in the metal wiring layer
  • the second fan-out area 240 is located in the second metal conductive layer
  • the third fan-out area 250 is located in the first metal conductive layer
  • the first metal conductive layer is close to the Substrate 10 .
  • the wirings of the signal connecting lines (including the signal lead 18C, the second connecting lead 16B and the first connecting lead 14C) in the first fan-out area 230, the second fan-out area 240 and the third fan-out area 250 are gradually closed, One end of the first connection lead 14C close to the third fan-out area 250 of the substrate 10 and away from the display area 100 is exposed by the opening 40 to form the bonding pin 41 .
  • the signal lines of the display area 100 of the display substrate need to be folded when they are drawn out, and the corresponding area is a fanout area.
  • the existing exposure and etching processes determine that the wiring spacing in the Fanout area cannot be too small, which makes some solutions for wiring in a single layer require the Fanout area to have enough length to achieve the wiring convergence effect.
  • the lower frame of the display substrate is not significantly shortened.
  • the signal connection wires (including the signal wire 18C, the second connection wire 16B and the first connection wire 14C) are wired in three layers: the metal wire layer, the second metal conductive layer and the first metal conductive layer , the wiring of the three film layers of the signal connection line is in an "S-shaped" round-trip wiring mode, and the wiring is gradually gathered in the three film layers, and the first connection lead 14C of the first metal conductive layer close to the substrate 10 is made.
  • One end far from the display area 100 is exposed by the opening 40 to form the binding pin 41.
  • the wiring scheme of this embodiment can greatly reduce the length of the Fanout area while achieving the corresponding folding effect of the signal connection line, thereby reducing the length of the fanout area.
  • the lower frame of the display substrate becomes narrower.
  • the wiring scheme of the signal connection lines in three film layers is shown, and in other examples, the signal connection lines may be wired in two or more film layers.
  • the substrate 10 includes a first flexible layer, a first barrier layer, an amorphous silicon layer, a second flexible layer 10D and a second barrier layer 10E stacked in sequence
  • the second composite insulating layer includes a first insulating layer 11 and a second insulating layer 13 sequentially stacked on the second barrier layer 10E;
  • the second stepped structure includes the first flexible layer, the first The first step 91 formed by the barrier layer, the amorphous silicon layer and the second flexible layer 10D, and the second step 92 formed by the second barrier layer 10E, the first insulating layer 11 and the second insulating layer 13 .
  • the width s1 of the first step 91 may be the distance from the edge of the second flexible layer 10D away from the display area 100 to the edge of the second step 92, and the width s2 of the second step 92 may be the The distance from the edge of the second step 92 to the edge of the display area 100 .
  • the height h2 of the second step 92 is greater than the height h1 of the first step 91 , and the second step 92 is disposed closer to the display area 100 than the first step 91 ; the first connecting lead 14C is disposed on the second step 92 and the first step 91 , the first step 91 is provided with the opening 40 .
  • the substrate 10 includes the stacked second flexible layer 10D and the second barrier layer 10E, and does not include the first flexible layer, the first barrier layer and the amorphous silicon layer, then the first step 91
  • the second flexible layer 10D is included, and the first flexible layer, the first barrier layer and the amorphous silicon layer are not included.
  • the bonding structure layer further includes a third insulating layer 15 covering the first metal conductive layer, and the second metal conductive layer is provided on the third conductive layer.
  • the bonding structure layer further includes a fourth insulating layer 17 covering the second metal conductive layer, the metal wiring layer is provided on the fourth insulating layer 17, and the third insulating layer
  • the layer 15 is provided with the first via hole V1, and the fourth insulating layer is provided with the second via hole V2.
  • the display area 100 includes a driving structure layer and a light emitting structure layer disposed on the driving structure layer, the driving structure layer is provided with a pixel driving circuit, and the pixel driving The circuit includes a plurality of transistors and storage capacitors, and a driving transistor and a storage capacitor are used as an example for illustration in FIG. 11 .
  • the driving structure layer of the display area 100 includes: a first insulating layer 11 arranged on the flexible substrate 10, an active layer 12 arranged on the first insulating layer 11, a second insulating layer 13 covering the active layer 12, arranged on the The first gate metal layer on the second insulating layer 13, the third insulating layer 15 covering the first gate metal layer, the second gate metal layer disposed on the third insulating layer 15, the fourth gate metal layer covering the second gate metal layer
  • the insulating layer 17 is a source-drain metal layer disposed on the fourth insulating layer 17 .
  • the first gate metal layer includes at least a gate electrode 14A and a first capacitor electrode 14B
  • the second gate metal layer includes at least a second capacitor electrode 16A
  • the source-drain metal layer includes at least a source electrode 18A and a drain electrode 18B.
  • the active layer 12, the gate electrode 14A, the source electrode 18A, and the drain electrode 18B constitute a driving transistor.
  • the first capacitor electrode 14B and the second capacitor electrode 16A constitute a storage capacitor.
  • the first metal conductive layer of the bonding region 200 can be provided in the same layer as the first gate metal layer, and the first connection lead 14C, the gate electrode 14A and the first capacitor electrode 14B can be subjected to the same patterning process Formed at the same time; the second metal conductive layer and the second gate metal layer can be provided in the same layer, and the second connection lead 16B and the second capacitor electrode 16A can be formed simultaneously through the same patterning process; the metal wiring The layer and the source-drain metal layer can be disposed in the same layer, and the signal lead 18C, the source electrode 18A, and the drain electrode 18B can be formed simultaneously through the same patterning process.
  • the second connection lead 16B is connected to the first connection lead 14C on the second step 92 through the first via V1 .
  • one end of the signal lead 18C away from the display area 100 may be connected to one end of the first connection lead 14C away from the display area 100 through the via V3 .
  • a first metal conductive layer is disposed between the metal trace layer and the substrate 10 , the first metal conductive layer includes a first connection lead 14C connected to the signal lead 18C, and the first connection lead 14C is disposed in the second step structure Above, the portion of the first connecting lead 14C exposed by the opening 40 forms the binding pin 41 . Since the first connection lead 14C may extend from the position connected to the signal lead 18C (at the via hole V3 ) to a direction close to the display area 100 , the signal connection lead (including the signal lead 18C and the first connection lead 14C) is Compared with the solution of wiring only on the metal wiring layer (such as the solution shown in FIG.
  • the wiring scheme of the metal wiring layer and the first metal conductive layer can further reduce the bonding area 200 . Therefore, the width of the frame on the side where the binding area 200 of the display substrate is located can be reduced.
  • the display substrate of this example does not have the second connection lead 16B of the display substrate of FIG. 11 , that is, the signal lead 18C is directly connected to the first connection lead 14C through the via V3 .
  • the manufacturing process of the display substrate of FIG. 11 may include the following steps:
  • the flexible substrate 10 is prepared on the glass carrier plate 1, as shown in FIG. 12 .
  • the flexible substrate 10 may include a first flexible layer 10A, a first barrier layer 10B, an amorphous silicon layer 10C, a second flexible layer 10D and a second barrier layer 10E which are stacked in sequence.
  • the flexible substrate 10 includes the stacked second flexible layer 10D and the second barrier layer 10E, and does not include the first flexible layer 10A, the first barrier layer 10B, and the amorphous silicon layer 10C.
  • both the display area 100 and the binding area 200 include the flexible substrate 10 .
  • the preparation process of this step may include:
  • a first insulating film and an active layer film are sequentially deposited on the flexible substrate 10 , and the active layer film is patterned through a patterning process to form a first insulating layer 11 covering the entire flexible substrate 10 and disposed on the first insulating layer 11
  • the active layer pattern is formed in the display area 100 and includes at least the active layer 12 .
  • a second insulating film is deposited on the flexible substrate 10 formed with the aforementioned pattern, and the second insulating layer 13 is formed.
  • the second insulating layer 13 covers the pattern of the active layer 12 in the display area 100 , and is stacked on the first insulating layer 11 in the bonding area 200 .
  • the bonding area 200 includes the first insulating layer 11 and the second insulating layer 13 stacked on the flexible substrate 10 .
  • a groove is formed on the second barrier layer 10E, the first insulating layer 11 and the second insulating layer 13 of the bonding region 200, and the second barrier layer 10E, the first insulating layer 11 and the second insulating layer 13 in the groove are formed is etched away to expose the surface of the second flexible layer 10D, thereby forming a second stepped structure.
  • the second step structure includes a first step 91 formed by the first flexible layer 10A, the first barrier layer 10B, the amorphous silicon layer 10C and the second flexible layer 10D, and the second barrier layer 10E, the first step 91
  • the second step 92 formed by the insulating layer 11 and the second insulating layer 13 has a height greater than that of the first step 91 , and is disposed closer to the display area 100 than the first step 91 .
  • the flexible substrate 10 adopts a one-layer flexible layer structure
  • the flexible substrate 10 includes the stacked second flexible layer 10D and the second barrier layer 10E, and does not include the first flexible layer 10A, the first barrier layer 10B and the amorphous layer
  • the first step 91 includes the second flexible layer 10D and does not include the first flexible layer 10A, the first barrier layer 10B and the amorphous silicon layer 10C.
  • the first gate metal layer includes at least a gate electrode 14A and a first capacitor electrode 14B.
  • the first metal conductive layer includes a first connection lead 14C, and the first connection lead 14C is disposed on the second step 92 and the first step 91 of the second step structure, as shown in FIG. 14 .
  • a third insulating film is deposited on the flexible substrate 10 formed with the aforementioned pattern, and the third insulating film is patterned through a patterning process to form a third insulating layer 15 covering the first gate metal layer and the first metal conductive layer.
  • a first via hole V1 is formed on the third insulating layer 15 of the bonding region 200 , and the third insulating film in the first via hole V1 is etched away, exposing the surface of the first connection lead 14C on the second step 92 , as shown in Figure 15.
  • a second metal film is deposited on the flexible substrate 10 formed with the aforementioned pattern, the second metal film is patterned through a patterning process, and a second gate metal layer pattern disposed on the third insulating layer 15 is formed in the display area 100, A second metal conductive layer pattern disposed on the third insulating layer 15 is formed in the bonding region 200 .
  • the second gate metal layer pattern includes at least a second capacitor electrode 16A, and the position of the second capacitor electrode 16A corresponds to the position of the first capacitor electrode 14B.
  • the second metal conductive layer pattern includes at least a second connecting lead 16B, and the second connecting lead 16B is connected to the first connecting lead 14C through the first via V1, as shown in FIG. 15 .
  • a fourth insulating film is deposited on the flexible substrate 10 formed with the aforementioned pattern, and the fourth insulating film is patterned through a patterning process to form a fourth insulating layer 17 covering the second gate metal layer and the second metal conductive layer.
  • Two via holes are formed on the fourth insulating layer 17 of the display area 100, and the fourth insulating film, the third insulating layer 15 and the second insulating layer 13 in the two via holes are all etched away, exposing the active surface of layer 12 .
  • a second via hole V2 is formed on the fourth insulating layer 17 of the bonding region 200, and the fourth insulating film in the second via hole V2 is etched away to expose the surface of the second connection lead 16B, as shown in FIG. 16 . .
  • a third metal film is deposited on the flexible substrate 10 formed with the aforementioned pattern, the third metal film is patterned through a patterning process, and a source-drain metal layer pattern disposed on the fourth insulating layer 17 is formed in the display area 100 .
  • the bonding region 200 forms a metal wiring layer pattern disposed on the fourth insulating layer 17 .
  • the source-drain metal layer pattern includes at least a source electrode 18A and a drain electrode 18B.
  • the metal wiring layer pattern includes a signal lead 18C, and the signal lead 18C is connected to the second connection lead 16B through the second via hole V2, as shown in FIG. 16 .
  • a fifth insulating film is deposited on the flexible substrate 10 formed with the aforementioned pattern to form a fifth insulating layer 19 pattern covering the source-drain metal layer and the metal wiring layer, as shown in FIG. 16 .
  • the driving structure layer pattern is prepared in the display area 100 of the flexible substrate 10
  • the film layer of the binding structure layer is prepared in the binding area 200 , as shown in FIG. 16 .
  • the active layer 12, the gate electrode 14A, the source electrode 18A and the drain electrode 18B constitute a transistor, and the transistor may be a driving transistor in a pixel driving circuit.
  • the first capacitor electrode 14B and the second capacitor electrode 16A constitute a storage capacitor.
  • the materials of all the film layers of the driving structure layer and the binding structure layer may be the same as those of the film layers in the process of preparing the display substrate of FIG. 4 above.
  • a flat layer 20 is formed on the flexible substrate 10 formed with the aforementioned pattern, an anode 21 and a pixel defining layer 22 of a light-emitting structure layer are formed in the display area 100, and a spacer column 23 is formed in the binding area 200, as shown in FIG. 17 .
  • the preparation process of this step may be the same as the corresponding steps in the preparation process of the display substrate of FIG. 4 above.
  • An organic light-emitting layer 24, a cathode 25, and an encapsulation structure layer are formed on the flexible substrate 10 formed with the aforementioned pattern.
  • the encapsulation structure layer includes a stacked first inorganic encapsulation layer 26, an organic encapsulation layer 27, and a second inorganic encapsulation layer. 28, as shown in Figure 18.
  • the preparation process of this step may be the same as the corresponding steps in the preparation process of the display substrate of FIG. 4 above.
  • the auxiliary film layer may include a stacked protective layer film 31 and heat dissipation film 32 and the like.
  • An opening 40 is formed on the flexible substrate 10 and the auxiliary film layer at a position corresponding to the first step 91 , the opening 40 exposes the first connection lead 14C on the first step 91 , and the portion of the first connection lead 14C exposed by the opening 40 is formed Bind pin 41.
  • the area where the binding pins 41 are formed in the binding area 200 is the binding pin area 205 , and the binding pins 41 of the binding pin area 205 can be bound and connected to an external circuit board, as shown in FIG. 19 .
  • the COF can be used to bind the driving IC on the display substrate.
  • the COF 60 includes a thin film circuit board body and a driving IC 61 fixed on the thin film circuit board body. One end of the film circuit board body is bound and connected to the binding pin 41 of the display substrate, and the other end is bound and connected to the FPC 70 . Both the COF 60 and the FPC 70 can be fixed to the surface of the display substrate facing away from the display side by an adhesive.
  • the COF 60 receives the signal transmitted from the FPC 70, and transmits the output signal to the display substrate to drive the display substrate to display.
  • the bonding pins 41 can be directly bonded and connected to the driver IC or FPC, and the driver IC or FPC is directly bonded to the back side of the display substrate.
  • an embodiment of the present disclosure provides a method for manufacturing a display substrate.
  • the display substrate includes a display area and a binding area on one side of the display area.
  • the manufacturing method includes:
  • a composite insulating layer is formed on the substrate of the binding area, the substrate and the composite insulating layer form a stepped structure, and the heights of the steps in the stepped structure decrease sequentially in the direction away from the display area, and the In the step structure, the substrate forms a first step with the smallest height;
  • a signal connection line is formed in the binding area, and at least a part of the signal connection line is arranged on the step structure and located on the first step;
  • An opening is formed on the substrate at the first step, the opening exposes the signal connection line, and a portion of the signal connection line exposed by the opening forms a binding pin.
  • the forming a signal connection line in the binding area includes:
  • a first metal conductive layer is formed on the composite insulating layer, the first metal conductive layer includes a first connection lead, and the first connection lead is arranged on the step structure and located on the first step;
  • a second metal conductive layer is formed on the side of the first metal conductive layer away from the substrate, the second metal conductive layer includes a second connection lead, and the second connection lead is connected to the first metal conductive layer through a first via hole. a connecting lead connection;
  • a metal wiring layer is formed on the side of the second metal conductive layer away from the substrate, and the metal wiring layer includes a signal lead connected to a signal line of the display area, and the signal lead passes through a second via hole connected with the second connection lead, the signal connection line includes the signal lead, the second connection lead and the first connection lead;
  • an embodiment of the present disclosure further provides a display device including the display substrate described in any of the foregoing embodiments.
  • the display device further includes a chip-on-film 60 bonded to the binding pins 41 , and bonded to the chip-on film 60 .
  • the connected flexible circuit board 70, the chip-on-film 60 is bound and connected with the driving IC 61.
  • the display device further includes a flexible circuit board (FPC) and a driver IC that are bound and connected in the binding area 200 , and the flexible circuit board or the driver IC is bound and connected to the binding pin 41 . .
  • FPC flexible circuit board
  • the driving IC receives the signal transmitted by the flexible circuit board 70 and transmits the output signal to the display substrate, so as to drive the display substrate to display.
  • the display device in the embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator.
  • connection means a fixed connection or a detachable connection, or integrally connected;
  • installed may be direct connection, or indirect connection through an intermediary, or internal communication between two elements.

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Abstract

一种显示基板及其制备方法、显示装置，所述显示基板包括显示区域和位于显示区域一侧的绑定区域，绑定区域包括设置在基底上的绑定结构层，绑定结构层包括设置在基底上的复合绝缘层，绑定区域还包括由基底和复合绝缘层形成的台阶结构，台阶结构中台阶的高度在远离显示区域的方向上依次减小，台阶结构中基底形成高度最小的第一台阶；绑定结构层还包括信号连接线，信号连接线的至少一部分设置在台阶结构上并位于所述第一台阶上，第一台阶处的基底上设有暴露出所述信号连接线的开口，信号连接线的被所述开口暴露的部分形成绑定引脚。

Description

显示基板及其制备方法、显示装置
本申请要求于2020年9月25日提交中国专利局、申请号为202011020687.7、发明名称为“一种显示基板及其制备方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于显示技术领域，尤其涉及一种显示基板及其制备方法、显示装置。
背景技术
显示屏的发展趋势是更加轻薄，边框更窄或者无边框。一些显示基板的下边框实现窄边框的方法为采用绑定区域弯折(Pad Bending)结构，通过设计弯折区将绑定区域弯折到显示基板的背面，从而实现窄边框，采用此种方法显示基板的下边框宽度可以缩小到3.0mm左右。但是，采用Pad Bending结构的显示基板在弯折区易发生膜层剥离、开裂等问题，显示基板的良率比较低，且受弯折半径限制，下边框宽度的降低会增加技术难度。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板，包括显示区域和位于显示区域一侧的绑定区域，所述绑定区域包括设置在基底上的绑定结构层，所述绑定结构层包括设置在所述基底上的复合绝缘层，所述绑定区域还包括由所述基底和所述复合绝缘层形成的台阶结构，所述台阶结构中台阶的高度在远离所述显示区域的方向上依次减小，所述台阶结构中所述基底形成高度最小的第一台阶；所述绑定结构层还包括信号连接线，所述信号连接线的至少一部分设置在所述台阶结构上并位于所述第一台阶上，所述第一台阶处的所述基底上设有暴露出所述信号连接线的开口，所述信号连接线的被所述开口暴露的部分形成绑定引脚。
本公开实施例还提供一种显示装置，包括所述的显示基板。
本公开实施例还提供一种显示基板的制备方法，所述显示基板包括显示区域和位于显示区域一侧的绑定区域，所述制备方法包括：
在所述绑定区域的基底上形成复合绝缘层，所述基底和所述复合绝缘层形成台阶结构，所述台阶结构中台阶的高度在远离所述显示区域的方向上依次减小，所述台阶结构中所述基底形成高度最小的第一台阶；
在所述绑定区域形成信号连接线，所述信号连接线的至少一部分设置在所述台阶结构上并位于所述第一台阶上；
在所述第一台阶处的所述基底上形成开口，所述开口暴露出所述信号连接线，所述信号连接线的被所述开口暴露的部分形成绑定引脚。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一些技术中显示基板的绑定区域的平面结构示意图；
图2为图1的A-A剖面结构示意图；
图3为一些示例性实施例的显示基板的绑定区域的平面结构示意图；
图4为在一些示例性实施例中图3的B-B剖面结构示意图；
图5为在一些示例性实施例中形成基底后的结构示意图；
图6为在一些示例性实施例中形成第一复合绝缘层和第一台阶结构后的结构示意图；
图7为在一些示例性实施例中形成金属走线层和第五绝缘层后的结构示意图；
图8为在一些示例性实施例中形成平坦层、阳极、像素界定层和隔垫柱后的结构示意图；
图9为在一些示例性实施例中形成有机发光层、阴极和封装结构层后的结构示意图；
图10为在一些示例性实施例中在基底上贴合辅助膜层和形成开口后的结构示意图；
图11为在另一些示例性实施例中显示基板的部分剖面结构示意图；
图12为在另一些示例性实施例中形成基底后的结构示意图；
图13为在另一些示例性实施例中形成第二复合绝缘层和第二台阶结构后的结构示意图；
图14为在另一些示例性实施例中形成第一金属导电层后的结构示意图；
图15为在另一些示例性实施例中形成第三绝缘层和第二金属导电层后的结构示意图；
图16为在另一些示例性实施例中形成第四绝缘层、金属走线层和第五绝缘层后的结构示意图；
图17为在另一些示例性实施例中形成平坦层、阳极、像素界定层和隔垫柱后的结构示意图；
图18为在另一些示例性实施例中形成有机发光层、阴极和封装结构层后的结构示意图；
图19为在另一些示例性实施例中在基底上贴合辅助膜层和形成开口后的结构示意图；
图20为在另一些示例性实施例中图11的显示基板的平面结构示意图；
图21为在又一些示例性实施例中显示基板的部分剖面结构示意图。
具体实施方式
本领域的普通技术人员应当理解，可以对本公开实施例的技术方案进行修改或者等同替换，而不脱离本公开实施例技术方案的精神和范围，均应涵盖在本公开的权利要求范围当中。
一些技术中，为了降低显示基板的下边框(显示基板的绑定区域所在侧 边的边框)的宽度，采用覆晶薄膜(chip on film，简称COF)方式或基板上芯片(Chip On Pi，简称COP)方式将驱动芯片搭载在显示基板上。下边框区域(即绑定区域)包括布线区域和绑定引脚区域，COF方案中，将驱动芯片(Integrated Circuit，简称IC)固定在COF的薄膜电路板本体上，COF绑定在显示基板上，通过弯折COF的薄膜电路板本体使驱动IC位于显示基板背侧，驱动IC不需要绑定在显示基板上，由此可以降低显示基板的下边框宽度，但是COF方案满足不了更窄边框的需求。COP方案将显示基板的绑定区域弯折到显示基板背面，柔性电路板(Flexible Printed Circuit，简称FPC)和驱动芯片绑定在弯折到显示基板背面的绑定区域上，因此能够大大降低下边框的宽度，采用COP方案能将下边框宽度缩减到2.5mm左右。COP方案中显示基板的平面结构示意图如图1所示，显示基板包括显示区域100和位于显示区域100一侧的绑定区域200，绑定区域200包括沿着远离显示区域100的方向依次设置的第一扇出区201、弯折区202、防静电区203、第二扇出区204和绑定引脚区205。其中，COP方案的绑定区域弯折工艺中，沿着弯折区202将绑定区域200弯折到显示区域100的背侧。第一扇出区201包括多条数据连接线，多条数据连接线配置为以扇出(Fanout)走线方式连接显示区域100的数据线(Data Line)，第二扇出区204包括以扇出走线方式引出的多条数据连接线。防静电区203包括防静电电路，配置为通过消除静电防止显示基板的静电损伤。绑定引脚区205包括多个绑定焊盘(Bonding Pad)，绑定焊盘可以配置为与柔性电路板、驱动芯片绑定连接。驱动IC接收FPC传输过来的信号，并驱动显示基板(Panel)进行显示。
图2为图1的显示基板中的A-A剖视图，如图2所示，弯折区202包括信号线引线(比如数据连接线)210，绑定引脚区205包括与信号线引线210连接的绑定焊盘220。COP方案在绑定区域弯折工艺中，弯折区202常发生膜层剥离(Peeling)、开裂(Crack)、金属线腐蚀等不良，因此，采用COP方案的显示基板良率较低，并且受限于弯折半径，降低显示基板的下边框宽度存在困难。
图3示出了本公开显示基板的一种平面结构示意图。如图3所示，显示基板包括显示区域100和位于显示区域100一侧的绑定区域200。绑定区域 200可以包括沿着远离显示区域100的方向依次设置的第一扇出区201、防静电区203、第二扇出区204和绑定引脚区205。第一扇出区201可以包括多条信号引线，多条信号引线比如为多条数据连接线，多条数据连接线配置为以扇出走线方式连接显示区域100的数据线。第二扇出区204包括以扇出走线方式引出的多条信号引线(比如为多条数据连接线)。防静电区203包括防静电电路，配置为通过消除静电防止显示基板的静电损伤。绑定引脚区205包括多个绑定引脚(或称绑定焊盘，Bonding Pad)，绑定引脚可以配置为与覆晶薄膜的一端绑定连接，覆晶薄膜的另一端配置为与柔性电路板绑定连接。覆晶薄膜接收柔性电路板传输过来的信号，并将输出信号传输至显示基板上，以驱动显示基板进行显示。
图4示出了图3的显示基板的一种B-B剖视图，如图4所示，本公开实施例的显示基板，包括显示区域100和位于显示区域100一侧的绑定区域200，所述绑定区域200包括设置在基底10上的绑定结构层，所述绑定结构层包括设置在所述基底10上的第一复合绝缘层，所述绑定区域200还包括由所述基底10和所述第一复合绝缘层形成的第一台阶结构，所述第一台阶结构中台阶的高度在远离所述显示区域100的方向上依次减小，所述第一台阶结构中所述基底10形成高度最小的第一台阶51；所述绑定结构层还包括信号连接线，所述信号连接线的至少一部分设置在所述第一台阶结构上并位于所述第一台阶51上，所述第一台阶51处的所述基底10上设有暴露出所述信号连接线的开口40，所述信号连接线的被所述开口40暴露的部分形成绑定引脚41。
本公开实施例的显示基板，将绑定区域200的信号连接线的至少一部分设置在第一台阶结构上并位于基底10上，并通过在基底10上设置开口40以暴露出信号连接线，并将信号连接线的被所述开口40暴露的部分作为绑定引脚41，如此，显示基板与外接电路板绑定连接时，外接电路板可以绑定在显示基板背侧(即背离显示侧的一侧)的绑定引脚41上，显示基板的绑定区域200不需要弯折到显示基板背侧，进而显示基板的绑定区域200可以不设置用于将绑定区域200弯折的弯折区，相较于一些技术中将绑定区域200弯折到显示基板背侧的方案，可以减少因绑定区域200弯折而产生的膜层剥离、开裂等不良，提升产品良率，并且可以降低显示基板的绑定区域200所在侧 边的边框宽度。
在一些示例性实施例中，如图4所示，所述绑定结构层还包括设于所述第一复合绝缘层上的金属走线层，所述金属走线层包括与所述显示区域100的信号线连接的信号引线18C；所述信号连接线包括所述信号引线18C，所述信号引线18C设置在所述第一台阶结构上并位于所述第一台阶51上，所述信号引线18C的被所述开口40暴露的部分形成所述绑定引脚41。
在一些示例性实施例中，如图4所示，所述显示区域100包括驱动结构层和设于所述驱动结构层上的发光结构层，所述驱动结构层设有像素驱动电路，所述驱动结构层包括源漏金属层，所述源漏金属层包括源电极18A和漏电极18B，所述金属走线层与所述源漏金属层同层设置。
本实施例的一个示例中，显示区域100的驱动结构层包括像素驱动电路，像素驱动电路包括多个晶体管和存储电容，图4中以一个驱动晶体管和一个存储电容为例进行示意。显示区域100的驱动结构层包括设置在柔性基底10上的第一绝缘层11，设置在第一绝缘层11上的有源层12，覆盖有源层12的第二绝缘层13，设置在第二绝缘层13上的第一栅金属层，覆盖第一栅金属层的第三绝缘层15，设置在第三绝缘层15上的第二栅金属层，覆盖第二栅金属层的第四绝缘层17，设置在第四绝缘层17上的源漏金属层，覆盖源漏金属层的第五绝缘层19。其中，第一栅金属层至少包括栅电极14A和第一电容电极14B，第二栅金属层至少包括第二电容电极16A，源漏金属层至少包括源电极18A和漏电极18B。有源层12、栅电极14A、源电极18A和漏电极18B组成驱动晶体管。第一电容电极14B和第二电容电极16A组成存储电容。
显示区域100的驱动结构层上可以设置有平坦层20，平坦层20设置在第五绝缘层19上，发光结构层设置在平坦层20上。发光结构层包括：设置在平坦层20上的阳极21、像素界定层22、有机发光层24和阴极25。有机发光层24可以设置在像素界定层22的开口内并位于阳极21和阴极25之间，有机发光层24在阳极21和阴极25之间的电压下进行发光。显示区域100还包括设置在发光结构层上的封装结构层，封装结构层可以包括第一无机封装层26、有机封装层27和第二无机封装层28。
在一些示例性实施例中，所述基底10包括依次叠设的第一柔性层10A、第一阻挡层10B、非晶硅层10C、第二柔性层10D和第二阻挡层10E。绑定区域200的第一复合绝缘层包括在所述第二阻挡层10E上叠设的第一绝缘层11、第二绝缘层13、第三绝缘层15和第四绝缘层17；所述第一台阶结构包括由所述第一柔性层10A、第一阻挡层10B、非晶硅层10C和第二柔性层10D形成的第一台阶51、由所述第二阻挡层10E和第一绝缘层11形成的第二台阶52，以及由所述第二绝缘层13、第三绝缘层15和第四绝缘层17形成的第三台阶53，所述第一台阶51、第二台阶52和第三台阶53的高度依次增大；所述信号引线18C设置在所述第三台阶53、所述第二台阶52和所述第一台阶51上。或者，在其他示例中，所述基底10包括叠设的第二柔性层10D和第二阻挡层10E，不包括第一柔性层10A、第一阻挡层10B和非晶硅层10C，则，第一台阶51包括第二柔性层10D，不包括第一柔性层10A、第一阻挡层10B和非晶硅层10C。
本文中，台阶的高度是指台阶表面到柔性基底10的背离显示侧的表面的距离。如图4所示，第一台阶51的高度h1、第二台阶52的高度h2、第三台阶53的高度h3依次增大。在平行于基底10的方向上，第一台阶51的宽度s1可以为第二柔性层10D的边缘到第二台阶52的边缘的距离，第二台阶52的宽度s2可以为第二台阶52的边缘到第三台阶53的边缘的距离，第三台阶53的宽度s3可以为第三台阶53的边缘到显示区域100的边缘的距离。
下面通过显示基板的制备过程的示例说明本公开显示基板的结构。本公开所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶等处理。沉积可以采用选自溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用选自喷涂和旋涂中的任意一种或多种，刻蚀可以采用选自干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺，则该“薄膜”可以称为“层”。当在整个制作过程当中该“薄膜”需要构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。本公开中所说的“A和B同层设置”是指，A和B通过同一次构图工艺同时形成。“A的正投影包含B的正投影” 是指，B的正投影落入A的正投影范围内，或者A的正投影覆盖B的正投影。
在一些示例性实施例中，图4的显示基板的制备过程可以包括如下步骤：
(1)在玻璃载板1上制备柔性基底10。
本公开实施例的一个示例中，柔性基底10可以采用两层柔性层结构，柔性基底10包括在玻璃载板1上叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一柔性材料层、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一无机材料层、第二无机材料层称为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。在一示例性实施方式中，以叠层结构PI1/Barrier1/a-si/PI2/Barrier2为例，柔性基底10的制备过程可以包括：先在玻璃载板1上涂布一层聚酰亚胺，固化成膜后形成第一柔性(PI1)层10A；随后在第一柔性层10A上沉积一层阻挡薄膜，形成覆盖第一柔性层10A的第一阻挡(Barrier1)层10B；然后在第一阻挡层10B上沉积一层非晶硅薄膜，形成覆盖第一阻挡层10B的非晶硅(a-si)层10C；然后在非晶硅层10C上再涂布一层聚酰亚胺，固化成膜后形成第二柔性(PI2)层10D；然后在第二柔性层10D上沉积一层阻挡薄膜，形成覆盖第二柔性层10D的第二阻挡(Barrier2)层10E，完成柔性基底10的制备，如图5所示。本次工艺后，显示区域100和绑定区域200均包括柔性基底10。
在其他示例中，柔性基底10可以采用一层柔性层结构，比如，柔性基底10包括叠设的柔性(PI)层和阻挡(Barrier)层，本示例的柔性基底10可以是将图5中的第一柔性(PI1)层10A、第一阻挡(Barrier1)层10B和非晶硅(a-si)层10C去除后，剩下叠设的第二柔性(PI2)层10D和第二阻挡(Barrier2)层10E。柔性基底10采用一层柔性层结构比采用两层柔性层结构，有利于后续在柔性基底10上开设开口40。
(2)在柔性基底10上制备显示区域100的驱动结构层的部分膜层，以及绑定区域200的第一复合绝缘层，并在绑定区域200形成第一台阶结构。 在一示例性实施方式中，如图6所示，本步骤的制备过程可以包括：
在柔性基底10上依次沉积第一绝缘薄膜和有源层薄膜，通过构图工艺对有源层薄膜进行构图，形成覆盖整个柔性基底10的第一绝缘层11，以及设置在第一绝缘层11上的有源层图案，有源层图案形成在显示区域100，至少包括有源层12。本次构图工艺后，绑定区域200包括设置在柔性基底10上的第一绝缘层11。
随后，依次沉积第二绝缘薄膜和第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，形成覆盖有源层图案的第二绝缘层13，以及设置在第二绝缘层13上的第一栅金属层图案，第一栅金属层图案形成在显示区域100，至少包括栅电极14A、第一电容电极14B。本次构图工艺后，绑定区域200包括在柔性基底10叠设的第一绝缘层11和第二绝缘层13。
随后，依次沉积第三绝缘薄膜和第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，形成覆盖第一栅金属层的第三绝缘层15，以及设置在第三绝缘层15上的第二栅金属层图案，第二栅金属层图案形成在显示区域100，至少包括第二电容电极16A，第二电容电极16A的位置与第一电容电极14B的位置相对应。本次构图工艺后，绑定区域200包括在柔性基底10叠设的第一绝缘层11、第二绝缘层13和第三绝缘层15。
随后，沉积第四绝缘薄膜，通过构图工艺对显示区域100的第四绝缘薄膜进行构图，以及对绑定区域200的复合绝缘薄膜(复合绝缘薄膜包括在柔性基底10叠设的第一绝缘层11、第二绝缘层13、第三绝缘层15和第四绝缘薄膜)进行构图，在显示区域100形成覆盖第二栅金属层的第四绝缘层17图案，在绑定区域200形成第一台阶结构。本步骤的构图工艺可以采用下面两次构图工艺进行：
先利用第一次掩膜刻蚀显示区域100和绑定区域200的第四绝缘薄膜、第三绝缘层15和第二绝缘层13，在显示区域100的第四绝缘薄膜、第三绝缘层15和第二绝缘层13上形成过孔17A和过孔17B，过孔17A和过孔17B内的第四绝缘薄膜、第三绝缘层15和第二绝缘层13被刻蚀掉，暴露出有源层12的表面。在绑定区域200的第四绝缘薄膜、第三绝缘层15和第二绝缘层13上形成第一凹槽，第一凹槽内的第四绝缘薄膜、第三绝缘层15和第二 绝缘层13被刻蚀掉，暴露出第一绝缘层11的表面。然后利用第二次掩膜刻蚀绑定区域200中第一凹槽内的第一绝缘层11和柔性基底10的第二阻挡层10E，在第一绝缘层11和第二阻挡层10E上形成第二凹槽，第二凹槽内的第一绝缘层11和第二阻挡层10E被刻蚀掉，暴露出柔性基底10的第二柔性层10D的表面。这样，绑定区域200内，第一凹槽暴露出第二凹槽，第二凹槽暴露出柔性基底10的第二柔性层10D，由此形成第一台阶结构，第一台阶结构包括由所述第一柔性层10A、第一阻挡层10B、非晶硅层10C和第二柔性层10D形成的第一台阶51、由所述第二阻挡层10E和第一绝缘层11形成的第二台阶52，以及由所述第二绝缘层13、第三绝缘层15和第四绝缘层17形成的第三台阶53，所述第一台阶51、第二台阶52和第三台阶53的高度依次增大。在柔性基底10采用一层柔性层结构的示例中，第一台阶51包括第二柔性层10D，不包括第一柔性层10A、第一阻挡层10B和非晶硅层10C。
本次构图工艺后，如图6所示，在绑定区域200形成第一复合绝缘层，第一复合绝缘层包括在柔性基底10上叠设的第一绝缘层11、第二绝缘层13、第三绝缘层15和第四绝缘层17。第一复合绝缘层和柔性基底10形成第一台阶结构，第一台阶结构包括第一台阶51、第二台阶52，以及第三台阶53，所述第一台阶51、第二台阶52和第三台阶53的高度依次增大。
(3)在显示区域100和绑定区域200分别形成源漏金属层和金属走线层，以及形成覆盖源漏金属层和金属走线层的第五绝缘层。
在一些示例性实施例中，在形成有前述图案的柔性基底10上沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，在显示区域100的第四绝缘层17上形成源漏金属层图案，在绑定区域200的第一台阶结构上形成金属走线层图案。如图7所示，源漏金属层包括源电极18A和漏电极18B，源电极18A通过过孔17A与有源层12的远离柔性基底10的表面连接，漏电极18B通过过孔17B与有源层12的远离柔性基底10的表面连接。金属走线层包括设置在第一台阶结构的第一台阶51、第二台阶52和第三台阶53上的信号引线18C。
随后，在显示区域100和绑定区域200沉积第五绝缘薄膜，形成覆盖源漏金属层和金属走线层的第五绝缘层19图案。
至此，在柔性基底10的显示区域100制备完成驱动结构层图案，在绑定区域200制备完成绑定结构层的膜层，如图7所示，有源层12、栅电极14A、源电极18A和漏电极18B组成晶体管，该晶体管可以是像素驱动电路中的驱动晶体管。第一电容电极14B和第二电容电极16A组成存储电容。
在示例性实施方式中，第一绝缘薄膜、第二绝缘薄膜、第三绝缘薄膜、第四绝缘薄膜和第五绝缘薄膜可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层11称为缓冲(Buffer)层，用于提高柔性基底10的抗水氧能力，第二绝缘层13和第三绝缘层15称为栅绝缘(GI)层，第四绝缘层17称为层间绝缘(ILD)层，第五绝缘层称为钝化(PVX)层。第一金属薄膜、第二金属薄膜、第三金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。有源层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物Oxide技术、硅技术或者有机物技术制造的晶体管。
(3)在形成前述图案的柔性基底10上形成平坦层20，以及在显示区域100形成发光结构层的阳极21、像素界定层22，在绑定区域200形成隔垫柱23，如图8所示。
在一些示例性实施例中，在形成前述图案的柔性基底10上涂覆有机材料的平坦薄膜，形成覆盖整个柔性基底10的平坦化(PLN)层20，通过掩膜、曝光、显影工艺，在显示区域100的平坦层20和第五绝缘层19上形成过孔，该过孔内的平坦层20和第五绝缘层19被显影掉，暴露出驱动晶体管的漏电极18B的表面。
在形成前述图案的柔性基底10上沉积透明导电薄膜，通过构图工艺对透明导电薄膜进行构图，形成阳极21图案，阳极21形成在显示区域100的平坦层20上，通过平坦层20和第五绝缘层19上的过孔与驱动晶体管的漏电极18B连接。本次构图工艺后，绑定区域200的膜层结构没有变化。在示例性 实施方式中，透明导电薄膜的材料可以采用氧化铟锡(ITO)或氧化铟锌(IZO)。
在形成前述图案的柔性基底10上涂覆像素界定薄膜，通过掩膜、曝光、显影工艺，形成像素界定(PDL)层22图案。像素界定层22形成在显示区域100以及绑定区域200的邻近显示区域100的部分区域，显示区域100的像素界定层22上开设有像素开口，像素开口内的像素界定层22被显影掉，暴露出阳极21的表面。
在形成前述图案的柔性基底10上涂覆有机材料薄膜，通过掩膜、曝光、显影工艺，形成多个隔垫柱(PS)23图案，多个隔垫柱23形成在绑定区域200的像素界定层22上。
(4)在形成前述图案的柔性基底10上形成有机发光层24、阴极25，以及封装结构层，如图9所示。
在一些示例性实施例中，有机发光层24可以采用蒸镀工艺形成在显示区域100内像素界定层22的像素开口内，实现有机发光层24与阳极21连接。阴极25形成在像素界定层22上，并与有机发光层24连接，且包裹绑定区域200的像素界定层22上的多个隔垫柱23。在示例性实施方式中，阴极25的材料可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或多种，或采用上述金属中任意一种或多种制成的合金。
在形成前述图案的柔性基底10上形成封装结构层，封装结构层可以包括叠设的第一无机封装层26、有机封装层27和第二无机封装层28。第一无机封装层26在显示区域100覆盖阴极25，在绑定区域200包裹多个隔垫柱23。有机封装层27设置在显示区域100和绑定区域200的隔垫柱23所在区域。第二无机封装层28覆盖第一无机封装层26和有机封装层27。
(5)将形成前述膜层的柔性基底10从玻璃载板1上剥离下来，在柔性基底10的背离显示侧的表面贴合辅助膜层，示例性地，辅助膜层可以包括叠设的保护膜31和散热膜32等。在柔性基底10和辅助膜层的与第一台阶51对应的位置形成开口40，开口40暴露出第一台阶51上的信号引线18C，信号引线18C的被开口40暴露的部分形成绑定引脚41。绑定区域200内形成绑定引脚41的区域为绑定引脚区205，绑定引脚区205的绑定引脚41可以 与外接电路板绑定连接，如图10所示。
(6)将显示基板与驱动IC、FPC绑定连接。
在一些示例性实施例中，如图4所示，可利用COF将驱动IC绑定在显示基板上，COF 60包括薄膜电路板本体和固定在薄膜电路板本体上的驱动IC 61，COF 60的薄膜电路板本体的一端与显示基板的绑定引脚41绑定连接，另一端与FPC 70绑定连接。COF 60和FPC 70均可通过胶粘剂固定在显示基板的背离显示侧的表面。COF 60接收FPC 70传输过来的信号，并将输出信号传输至显示基板上，以驱动显示基板进行显示。在其他示例中，可以将绑定引脚41直接与驱动IC或FPC绑定连接，驱动IC或FPC直接绑定在显示基板的背侧。
图11示出了图3的显示基板的另一种B-B剖视图，如图11所示，本公开实施例的显示基板，包括显示区域100和位于显示区域100一侧的绑定区域200，所述绑定区域200包括设置在基底10上的绑定结构层，所述绑定结构层包括设置在所述基底10上的第二复合绝缘层，所述绑定区域200还包括由所述基底10和所述第二复合绝缘层形成的第二台阶结构，所述第二台阶结构中台阶的高度在远离所述显示区域100的方向上依次减小，所述第二台阶结构中所述基底10形成高度最小的第一台阶91；所述绑定结构层还包括信号连接线，所述信号连接线的至少一部分设置在所述第二台阶结构上并位于所述第一台阶91上，所述第一台阶91处的所述基底10上设有暴露出所述信号连接线的开口40，所述信号连接线的被所述开口40暴露的部分形成绑定引脚41。
本公开实施例的显示基板，将绑定区域200的信号连接线的至少一部分设置在第二台阶结构上并位于基底10上，并通过在基底10上设置开口40以暴露出信号连接线，并将信号连接线的被所述开口40暴露的部分作为绑定引脚41，如此，显示基板与外接电路板绑定连接时，外接电路板可以绑定在显示基板背侧(即背离显示侧的一侧)的绑定引脚41上，显示基板的绑定区域200不需要弯折到显示基板背侧，进而显示基板的绑定区域200可以不设置用于将绑定区域200弯折的弯折区，相较于一些技术中将绑定区域200弯折到显示基板背侧的方案，可以减少因绑定区域200弯折而产生的膜层剥离、 开裂等不良，提升产品良率，并且可以降低显示基板的绑定区域200所在侧边的边框宽度。
在一些示例性实施例中，如图11所示，所述绑定结构层还包括设于所述第二复合绝缘层上的第一金属导电层，以及设于所述第一金属导电层的远离基底10一侧的金属走线层，所述金属走线层包括与所述显示区域100的信号线连接的信号引线18C，所述第一金属导电层包括与所述信号引线18C连接的第一连接引线14C；所述信号连接线包括所述信号引线18C和所述第一连接引线14C，所述第一连接引线14C设置在所述第二台阶结构上并位于所述第一台阶91上，所述第一连接引线14C的被所述开口40暴露的部分形成所述绑定引脚41。
在一些示例性实施例中，如图11所示，所述绑定结构层还包括设于所述第一金属导电层和所述金属走线层之间的第二金属导电层，所述第二金属导电层包括第二连接引线16B，所述第二连接引线16B通过第一过孔V1与所述第一连接引线14C连接，所述信号引线18C通过第二过孔V2与所述第二连接引线16B连接。
在一些示例性实施例中，如图11所示，所述第一过孔V1相较于所述第二过孔V2靠近所述显示区域100设置，所述开口40相较于所述第一过孔V1远离所述显示区域100设置。
示例性地，图20示出了图11所示显示基板的平面结构示意图，如图20所示，信号引线18C所在的区域为第一扇出区230，第二连接引线16B所在的区域为第二扇出区240，第一连接引线14C所在的区域为第三扇出区250。信号引线18C通过第二过孔V2与第二连接引线16B连接，第二连接引线16B通过第一过孔V1与第一连接引线14C连接，第一连接引线14C的远离显示区域100的一端被开口40暴露而形成绑定引脚41。第一扇出区230位于所述金属走线层，第二扇出区240位于所述第二金属导电层，第三扇出区250位于所述第一金属导电层，第一金属导电层靠近基底10。所述信号连接线(包括信号引线18C、第二连接引线16B和第一连接引线14C)在第一扇出区230、第二扇出区240和第三扇出区250内的布线逐渐收拢，并使靠近基底10的第三扇出区250的第一连接引线14C的远离显示区域100的一端被开口40暴 露，从而形成绑定引脚41。
基于窄边框的设计以及绑定工艺的要求，显示基板显示区域100的信号线引出时需要进行收拢，相应的区域为扇出(Fanout)区。在保证线宽的条件下，现有的曝光和刻蚀工艺决定了Fanout区的布线间距不能太小，这使得一些在单层进行布线的方案需要Fanout区有足够的长度，才能实现布线收拢效果，相较于COP方案，显示基板的下边框缩短就不明显。本示例中，所述信号连接线(包括信号引线18C、第二连接引线16B和第一连接引线14C)在金属走线层、第二金属导电层和第一金属导电层三个膜层进行布线，所述信号连接线在此三个膜层的布线呈“S型”往返布线方式，且布线在三个膜层逐渐收拢，并使靠近基底10的第一金属导电层的第一连接引线14C的远离显示区域100的一端被开口40暴露而形成绑定引脚41，本实施例的布线方案能够使所述信号连接线在达到相应的收拢效果的同时，大大降低了Fanout区的长度，从而使得显示基板的下边框变得更窄。此外，本示例中，示出了所述信号连接线在三个膜层的布线方案，在其他示例中，所述信号连接线可以在两个或三个以上膜层进行布线。
在一些示例性实施例中，如图11所示，所述基底10包括依次叠设的第一柔性层、第一阻挡层、非晶硅层、第二柔性层10D和第二阻挡层10E，所述第二复合绝缘层包括在所述第二阻挡层10E上依次叠设的第一绝缘层11和第二绝缘层13；所述第二台阶结构包括由所述第一柔性层、第一阻挡层、非晶硅层和第二柔性层10D形成的第一台阶91，以及由所述第二阻挡层10E、第一绝缘层11和第二绝缘层13形成的第二台阶92。在平行于基底10的方向上，第一台阶91的宽度s1可以为第二柔性层10D的远离显示区域100的边缘到第二台阶92的边缘的距离，第二台阶92的宽度s2可以为第二台阶92的边缘到显示区域100的边缘的距离。所述第二台阶92的高度h2大于第一台阶91的高度h1，第二台阶92相较于第一台阶91靠近所述显示区域100设置；所述第一连接引线14C设于第二台阶92和第一台阶91上，所述第一台阶91上设有所述开口40。或者，在其他示例中，所述基底10包括叠设的第二柔性层10D和第二阻挡层10E，不包括第一柔性层、第一阻挡层和非晶硅层，则，第一台阶91包括第二柔性层10D，不包括第一柔性层、第一阻挡 层和非晶硅层。
在一些示例性实施例中，如图11所示，所述绑定结构层还包括覆盖所述第一金属导电层的第三绝缘层15，所述第二金属导电层设于所述第三绝缘层15上，所述绑定结构层还包括覆盖所述第二金属导电层的第四绝缘层17，所述金属走线层设于所述第四绝缘层17上，所述第三绝缘层15上设有所述第一过孔V1，所述第四绝缘层上设有所述第二过孔V2。
在一些示例性实施例中，如图11所示，所述显示区域100包括驱动结构层和设于所述驱动结构层上的发光结构层，所述驱动结构层设有像素驱动电路，像素驱动电路包括多个晶体管和存储电容，图11中以一个驱动晶体管和一个存储电容为例进行示意。显示区域100的驱动结构层包括：设置在柔性基底10上的第一绝缘层11，设置在第一绝缘层11上的有源层12，覆盖有源层12的第二绝缘层13，设置在第二绝缘层13上的第一栅金属层，覆盖第一栅金属层的第三绝缘层15，设置在第三绝缘层15上的第二栅金属层，覆盖第二栅金属层的第四绝缘层17，设置在第四绝缘层17上的源漏金属层。第一栅金属层至少包括栅电极14A和第一电容电极14B，第二栅金属层至少包括第二电容电极16A，源漏金属层至少包括源电极18A和漏电极18B。有源层12、栅电极14A、源电极18A和漏电极18B组成驱动晶体管。第一电容电极14B和第二电容电极16A组成存储电容。绑定区域200的所述第一金属导电层可以与所述第一栅金属层同层设置，所述第一连接引线14C、所述栅电极14A和第一电容电极14B可通过同一次构图工艺同时形成；所述第二金属导电层与所述第二栅金属层可以同层设置，所述第二连接引线16B与第二电容电极16A可通过同一次构图工艺同时形成；所述金属走线层与所述源漏金属层可以同层设置，所述信号引线18C与所述源电极18A、漏电极18B可通过同一次构图工艺同时形成。
在一些示例性实施例中，如图11所示，所述第二连接引线16B通过所述第一过孔V1与所述第二台阶92上的所述第一连接引线14C连接。
在一些示例性实施例中，如图21所示，信号引线18C的远离显示区域100的一端可通过过孔V3与第一连接引线14C的远离显示区域100的一端连接。
本示例中，在金属走线层和基底10之间设置第一金属导电层，第一金属导电层包括与信号引线18C连接的第一连接引线14C，第一连接引线14C设置在第二台阶结构上，第一连接引线14C的被所述开口40暴露的部分形成所述绑定引脚41。由于第一连接引线14C可以自与信号引线18C连接的位置(过孔V3处)向靠近显示区域100的方向延伸，如此，所述信号连接线(包括信号引线18C和第一连接引线14C)在金属走线层和第一金属导电层两个膜层进行布线的方案，相较于只在金属走线层进行布线的方案(比如图4所示的方案)，可进一步降低绑定区域200的宽度，从而可降低显示基板的绑定区域200所在侧边的边框宽度。本示例的显示基板相较于图11的显示基板，没有设置图11的显示基板的第二连接引线16B，即信号引线18C通过过孔V3直接与第一连接引线14C连接。
下面通过显示基板的制备过程的示例说明本公开图11的显示基板的结构。在一些示例性实施例中，图11的显示基板的制备过程可以包括如下步骤：
(1)在玻璃载板1上制备柔性基底10，如图12所示。
本步骤可以与前文图4的显示基板的制备过程中形成柔性基底10的步骤相同。柔性基底10可以包括依次叠设的第一柔性层10A、第一阻挡层10B、非晶硅层10C、第二柔性层10D和第二阻挡层10E。或者，柔性基底10包括叠设的第二柔性层10D和第二阻挡层10E，不包括第一柔性层10A、第一阻挡层10B、非晶硅层10C。本次工艺后，显示区域100和绑定区域200均包括柔性基底10。
(2)在柔性基底10上制备显示区域100的驱动结构层的部分膜层，以及绑定区域200的第二复合绝缘层，并形成第二台阶结构。在一示例性实施方式中，如图13所示，本步骤的制备过程可以包括：
在柔性基底10上依次沉积第一绝缘薄膜和有源层薄膜，通过构图工艺对有源层薄膜进行构图，形成覆盖整个柔性基底10的第一绝缘层11，以及设置在第一绝缘层11上的有源层图案，有源层图案形成在显示区域100，至少包括有源层12。
随后，在形成有前述图案的柔性基底10上沉积第二绝缘薄膜，形成第二 绝缘层13。第二绝缘层13在显示区域100覆盖有源层12图案，在绑定区域200叠设在第一绝缘层11上。本次工艺后，绑定区域200包括叠设在柔性基底10上的第一绝缘层11和第二绝缘层13。
在绑定区域200的第二阻挡层10E、第一绝缘层11和第二绝缘层13上形成凹槽，该凹槽内的第二阻挡层10E、第一绝缘层11和第二绝缘层13被刻蚀掉，暴露出第二柔性层10D的表面，由此形成第二台阶结构。第二台阶结构包括由所述第一柔性层10A、第一阻挡层10B、非晶硅层10C和第二柔性层10D形成的第一台阶91，以及由所述第二阻挡层10E、第一绝缘层11和第二绝缘层13形成的第二台阶92，第二台阶92的高度大于第一台阶91的高度，第二台阶92相较于第一台阶91靠近显示区域100设置。在柔性基底10采用一层柔性层结构的示例中，即柔性基底10包括叠设的第二柔性层10D和第二阻挡层10E，不包括第一柔性层10A、第一阻挡层10B和非晶硅层10C，则，第一台阶91包括第二柔性层10D，不包括第一柔性层10A、第一阻挡层10B和非晶硅层10C。
(3)在形成前述图案的柔性基底10上沉积第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，则同时在显示区域100和绑定区域200分别形成第一栅金属层图案和第一金属导电层图案。
第一栅金属层至少包括栅电极14A和第一电容电极14B。第一金属导电层包括第一连接引线14C，第一连接引线14C设置在第二台阶结构的第二台阶92和第一台阶91上，如图14所示。
(4)在形成前述图案的柔性基底10上沉积第三绝缘薄膜，通过构图工艺对第三绝缘薄膜进行构图，形成覆盖第一栅金属层和第一金属导电层的第三绝缘层15。绑定区域200的第三绝缘层15上形成有第一过孔V1，第一过孔V1内的第三绝缘薄膜被刻蚀掉，暴露出第二台阶92上的第一连接引线14C的表面，如图15所示。
随后，在形成有前述图案的柔性基底10上沉积第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，在显示区域100形成设置在第三绝缘层15上的第二栅金属层图案，在绑定区域200形成设置在第三绝缘层15上的第二金属导电层图案。第二栅金属层图案至少包括第二电容电极16A，第二电容 电极16A的位置与第一电容电极14B的位置相对应。第二金属导电层图案至少包括第二连接引线16B，第二连接引线16B通过第一过孔V1与第一连接引线14C连接，如图15所示。
(5)在形成前述图案的柔性基底10上沉积第四绝缘薄膜，通过构图工艺对第四绝缘薄膜进行构图，形成覆盖第二栅金属层和第二金属导电层的第四绝缘层17。显示区域100的第四绝缘层17上形成有两个过孔，两个过孔内的第四绝缘薄膜、第三绝缘层15和第二绝缘层13均被刻蚀掉，均暴露出有源层12的表面。绑定区域200的第四绝缘层17上形成有第二过孔V2，第二过孔V2内的第四绝缘薄膜被刻蚀掉，暴露出第二连接引线16B的表面，如图16所示。
随后，在形成有前述图案的柔性基底10上沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，在显示区域100形成设置在第四绝缘层17上的源漏金属层图案，在绑定区域200形成设置在第四绝缘层17上的金属走线层图案。源漏金属层图案至少包括源电极18A和漏电极18B。金属走线层图案包括信号引线18C，信号引线18C通过第二过孔V2与第二连接引线16B连接，如图16所示。
随后，在形成有前述图案的柔性基底10上沉积第五绝缘薄膜，形成覆盖源漏金属层和金属走线层的第五绝缘层19图案，如图16所示。
至此，在柔性基底10的显示区域100制备完成驱动结构层图案，在绑定区域200制备完成绑定结构层的膜层，如图16所示。有源层12、栅电极14A、源电极18A和漏电极18B组成晶体管，该晶体管可以是像素驱动电路中的驱动晶体管。第一电容电极14B和第二电容电极16A组成存储电容。驱动结构层和绑定结构层的所有膜层的材料可以与前文图4的显示基板制备过程中的膜层材料相同。
(6)在形成前述图案的柔性基底10上形成平坦层20，以及在显示区域100形成发光结构层的阳极21、像素界定层22，在绑定区域200形成隔垫柱23，如图17所示。本步骤的制备过程可以与前文图4的显示基板制备过程中的相应步骤相同。
(7)在形成前述图案的柔性基底10上形成有机发光层24、阴极25，以及封装结构层，封装结构层包括叠设的第一无机封装层26、有机封装层27和第二无机封装层28，如图18所示。本步骤的制备过程可以与前文图4的显示基板制备过程中的相应步骤相同。
(8)将形成前述膜层的柔性基底10从玻璃载板1上剥离下来，在柔性基底10的背离显示侧的表面贴合辅助膜层，示例性地，辅助膜层可以包括叠设的保护膜31和散热膜32等。在柔性基底10和辅助膜层的与第一台阶91对应的位置形成开口40，开口40暴露出第一台阶91上的第一连接引线14C，第一连接引线14C的被开口40暴露的部分形成绑定引脚41。绑定区域200内形成绑定引脚41的区域为绑定引脚区205，绑定引脚区205的绑定引脚41可以与外接电路板绑定连接，如图19所示。
(9)将显示基板与驱动IC、FPC绑定连接。
在一些示例性实施例中，如图11所示，可利用COF将驱动IC绑定在显示基板上，COF 60包括薄膜电路板本体和固定在薄膜电路板本体上的驱动IC 61，COF 60的薄膜电路板本体的一端与显示基板的绑定引脚41绑定连接，另一端与FPC 70绑定连接。COF 60和FPC 70均可通过胶粘剂固定在显示基板的背离显示侧的表面。COF 60接收FPC 70传输过来的信号，并将输出信号传输至显示基板上，以驱动显示基板进行显示。在其他示例中，可以将绑定引脚41直接与驱动IC或FPC绑定连接，驱动IC或FPC直接绑定在显示基板的背侧。
基于前文内容，本公开实施例提供一种显示基板的制备方法，所述显示基板包括显示区域和位于显示区域一侧的绑定区域，所述制备方法包括：
在所述绑定区域的基底上形成复合绝缘层，所述基底和所述复合绝缘层形成台阶结构，所述台阶结构中台阶的高度在远离所述显示区域的方向上依次减小，所述台阶结构中所述基底形成高度最小的第一台阶；
在所述绑定区域形成信号连接线，所述信号连接线的至少一部分设置在所述台阶结构上并位于所述第一台阶上；
在所述第一台阶处的所述基底上形成开口，所述开口暴露出所述信号连 接线，所述信号连接线的被所述开口暴露的部分形成绑定引脚。
在一些示例性实施例中，所述在所述绑定区域形成信号连接线，包括：
在所述复合绝缘层上形成第一金属导电层，所述第一金属导电层包括第一连接引线，所述第一连接引线设置在所述台阶结构上并位于所述第一台阶上；
在所述第一金属导电层的远离所述基底一侧形成第二金属导电层，所述第二金属导电层包括第二连接引线，所述第二连接引线通过第一过孔与所述第一连接引线连接；
在所述第二金属导电层的远离所述基底一侧形成金属走线层，所述金属走线层包括与所述显示区域的信号线连接的信号引线，所述信号引线通过第二过孔与所述第二连接引线连接，所述信号连接线包括所述信号引线、所述第二连接引线和所述第一连接引线；
所述在所述第一台阶处的所述基底上形成开口，所述开口暴露出所述信号连接线，所述信号连接线的被所述开口暴露的部分形成绑定引脚，包括：在所述第一台阶处的所述基底上形成开口，所述开口暴露出所述第一连接引线，所述第一连接引线的被所述开口暴露的部分形成绑定引脚。
本公开实施例还提供一种显示装置，包括前文任一实施例所述的显示基板。在一些示例性实施例中，如图4和图11所示，所述显示装置还包括与所述绑定引脚41绑定连接的覆晶薄膜60，以及与所述覆晶薄膜60绑定连接的柔性电路板70，所述覆晶薄膜60上绑定连接有驱动IC 61。在其他实施例中，所述显示装置还包括绑定连接在绑定区域200的柔性电路板(FPC)和驱动IC，所述柔性电路板或驱动IC与所述绑定引脚41绑定连接。驱动IC接收柔性电路板70传输的信号，并将输出信号传输至显示基板上，以驱动显示基板进行显示。本公开实施例的显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
在本文的描述中，术语“上”、“下”、“左”、“右”、“顶”、“内”、“外”、“轴向”、“四角”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开实施例的简化描述，而不是指示或暗示所指的结构具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
在本文的描述中，除非另有明确的规定和限定，术语“连接”、“固定连接”、“安装”、“装配”应做广义理解，例如，可以是固定连接，或者是可拆卸连接，或一体地连接；术语“安装”、“连接”、“固定连接”可以是直接相连，或是通过中间媒介间接相连，或是两个元件内部的连通。对于本领域的普通技术人员而言，可以理解上述术语在本文中的含义。

Claims (16)

  1. 一种显示基板，包括显示区域和位于显示区域一侧的绑定区域，所述绑定区域包括设置在基底上的绑定结构层，所述绑定结构层包括设置在所述基底上的复合绝缘层，所述绑定区域还包括由所述基底和所述复合绝缘层形成的台阶结构，所述台阶结构中台阶的高度在远离所述显示区域的方向上依次减小，所述台阶结构中所述基底形成高度最小的第一台阶；
    所述绑定结构层还包括信号连接线，所述信号连接线的至少一部分设置在所述台阶结构上并位于所述第一台阶上，所述第一台阶处的所述基底上设有暴露出所述信号连接线的开口，所述信号连接线的被所述开口暴露的部分形成绑定引脚。
  2. 如权利要求1所述的显示基板，其中：所述绑定结构层还包括设于所述复合绝缘层上的金属走线层，所述金属走线层包括与所述显示区域的信号线连接的信号引线；
    所述信号连接线包括所述信号引线，所述信号引线设置在所述台阶结构上并位于所述第一台阶上，所述信号引线的被所述开口暴露的部分形成所述绑定引脚。
  3. 如权利要求2所述的显示基板，其中：所述基底包括叠设的柔性层和阻挡层，所述复合绝缘层包括在所述阻挡层上叠设的第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层；
    所述台阶结构包括由所述柔性层形成的所述第一台阶，由所述阻挡层和所述第一绝缘层形成的第二台阶，以及由所述第二绝缘层、所述第三绝缘层和所述第四绝缘层形成的第三台阶，所述第一台阶、所述第二台阶和所述第三台阶的高度依次增大；
    所述信号引线设置在所述第三台阶、所述第二台阶和所述第一台阶上。
  4. 如权利要求2所述的显示基板，其中：所述显示区域包括驱动结构层和设于所述驱动结构层上的发光结构层，所述驱动结构层设有像素驱动电路，所述驱动结构层包括源漏金属层，所述源漏金属层包括源电极和漏电极，所述金属走线层与所述源漏金属层同层设置。
  5. 如权利要求1所述的显示基板，其中：所述绑定结构层还包括设于所述复合绝缘层上的第一金属导电层，以及设于所述第一金属导电层的远离所述基底一侧的金属走线层，所述金属走线层包括与所述显示区域的信号线连接的信号引线，所述第一金属导电层包括与所述信号引线连接的第一连接引线；
    所述信号连接线包括所述信号引线和所述第一连接引线，所述第一连接引线设置在所述台阶结构上并位于所述第一台阶上，所述第一连接引线的被所述开口暴露的部分形成所述绑定引脚。
  6. 如权利要求5所述的显示基板，其中：所述信号引线的远离所述显示区域的一端通过过孔与所述第一连接引线的远离所述显示区域的一端连接。
  7. 如权利要求5所述的显示基板，其中：所述绑定结构层还包括设于所述第一金属导电层和所述金属走线层之间的第二金属导电层，所述第二金属导电层包括第二连接引线，所述第二连接引线通过第一过孔与所述第一连接引线连接，所述信号引线通过第二过孔与所述第二连接引线连接。
  8. 如权利要求7所述的显示基板，其中：所述第一过孔相较于所述第二过孔靠近所述显示区域设置，所述开口相较于所述第一过孔远离所述显示区域设置。
  9. 如权利要求7所述的显示基板，其中：所述基底包括叠设的柔性层和阻挡层，所述复合绝缘层包括在所述阻挡层上依次叠设的第一绝缘层和第二绝缘层；
    所述台阶结构包括由所述柔性层形成的所述第一台阶，以及由所述阻挡层、所述第一绝缘层和所述第二绝缘层形成的第二台阶，所述第二台阶相较于所述第一台阶靠近所述显示区域设置；
    所述第一连接引线设于所述第二台阶和所述第一台阶上。
  10. 如权利要求9所述的显示基板，其中：所述绑定结构层还包括覆盖所述第一金属导电层的第三绝缘层，所述第二金属导电层设于所述第三绝缘层上，所述绑定结构层还包括覆盖所述第二金属导电层的第四绝缘层，所述金属走线层设于所述第四绝缘层上，所述第三绝缘层上设有所述第一过孔， 所述第四绝缘层上设有所述第二过孔。
  11. 如权利要求10所述的显示基板，其中：所述显示区域包括驱动结构层和设于所述驱动结构层上的发光结构层，所述驱动结构层设有像素驱动电路，所述驱动结构层包括：设置在基底上的第一绝缘层，设置在所述第一绝缘层上的有源层，覆盖所述有源层的第二绝缘层，设置在所述第二绝缘层上的第一栅金属层，覆盖所述第一栅金属层的第三绝缘层，设置在所述第三绝缘层上的第二栅金属层，覆盖所述第二栅金属层的第四绝缘层，设置在所述第四绝缘层上的源漏金属层；
    所述第一金属导电层与所述第一栅金属层同层设置，所述第二金属导电层与所述第二栅金属层同层设置，所述金属走线层与所述源漏金属层同层设置。
  12. 如权利要求9所述的显示基板，其中：所述第二连接引线通过所述第一过孔与所述第二台阶上的所述第一连接引线连接。
  13. 一种显示装置，包括权利要求1至12任一项所述的显示基板。
  14. 如权利要求13所述的显示装置，还包括与所述绑定引脚绑定连接的覆晶薄膜，以及与所述覆晶薄膜绑定连接的柔性电路板。
  15. 一种显示基板的制备方法，所述显示基板包括显示区域和位于显示区域一侧的绑定区域，所述制备方法包括：
    在所述绑定区域的基底上形成复合绝缘层，所述基底和所述复合绝缘层形成台阶结构，所述台阶结构中台阶的高度在远离所述显示区域的方向上依次减小，所述台阶结构中所述基底形成高度最小的第一台阶；
    在所述绑定区域形成信号连接线，所述信号连接线的至少一部分设置在所述台阶结构上并位于所述第一台阶上；
    在所述第一台阶处的所述基底上形成开口，所述开口暴露出所述信号连接线，所述信号连接线的被所述开口暴露的部分形成绑定引脚。
  16. 如权利要求15所述的显示基板的制备方法，其中，所述在所述绑定区域形成信号连接线，包括：
    在所述复合绝缘层上形成第一金属导电层，所述第一金属导电层包括第 一连接引线，所述第一连接引线设置在所述台阶结构上并位于所述第一台阶上；
    在所述第一金属导电层的远离所述基底一侧形成第二金属导电层，所述第二金属导电层包括第二连接引线，所述第二连接引线通过第一过孔与所述第一连接引线连接；
    在所述第二金属导电层的远离所述基底一侧形成金属走线层，所述金属走线层包括与所述显示区域的信号线连接的信号引线，所述信号引线通过第二过孔与所述第二连接引线连接，所述信号连接线包括所述信号引线、所述第二连接引线和所述第一连接引线；
    所述在所述第一台阶处的所述基底上形成开口，所述开口暴露出所述信号连接线，所述信号连接线的被所述开口暴露的部分形成绑定引脚，包括：在所述第一台阶处的所述基底上形成开口，所述开口暴露出所述第一连接引线，所述第一连接引线的被所述开口暴露的部分形成绑定引脚。
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CN109638049A (zh) * 2018-12-13 2019-04-16 武汉华星光电半导体显示技术有限公司 显示面板
CN109616480A (zh) * 2018-12-27 2019-04-12 厦门天马微电子有限公司 一种显示面板及显示装置
CN111128080A (zh) * 2020-03-30 2020-05-08 京东方科技集团股份有限公司 显示基板及显示装置
CN112133729A (zh) * 2020-09-25 2020-12-25 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置

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