WO2023165357A1 - 显示装置及其制备方法 - Google Patents

显示装置及其制备方法 Download PDF

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Publication number
WO2023165357A1
WO2023165357A1 PCT/CN2023/077147 CN2023077147W WO2023165357A1 WO 2023165357 A1 WO2023165357 A1 WO 2023165357A1 CN 2023077147 W CN2023077147 W CN 2023077147W WO 2023165357 A1 WO2023165357 A1 WO 2023165357A1
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WO
WIPO (PCT)
Prior art keywords
layer
pin
flexible substrate
wiring
lead
Prior art date
Application number
PCT/CN2023/077147
Other languages
English (en)
French (fr)
Inventor
王美丽
王磊
孙伟
吴仲远
董学
韩文超
董水浪
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Filing date
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Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2023165357A1 publication Critical patent/WO2023165357A1/zh

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/306—Lead-in-hole components, e.g. affixing or retention before soldering, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • the present application relates to the field of display technology, in particular to a display device and a manufacturing method thereof.
  • COF Chip On Film, chip-on-film
  • COF is a chip packaging technology, which is to fix the driver chip (IC) on the flexible circuit board.
  • IC driver chip
  • COF is connected to the display panel; however, due to the manufacturing process, the binding accuracy of COF and display panel is limited, and the number of drive channels that can be output is limited, which makes it difficult to meet the requirements of high-resolution 3D display products.
  • a method for manufacturing a display device comprising:
  • the chip packaging structure includes at least one chip packaging unit;
  • the chip packaging unit at least includes: a flexible substrate, a rigid substrate arranged on one side of the flexible substrate, and a rigid substrate arranged on the flexible substrate away from The pin layer on one side of the rigid substrate, the pin layer at least includes a plurality of first pins, and the orthographic projections of the plurality of first pins on the flexible substrate are located on the rigid substrate on the flexible substrate. within the orthographic projection of the base;
  • the display panel includes a non-display area, and the non-display area includes a rigid substrate and a binding portion disposed on the rigid substrate;
  • the method further includes:
  • the thermal expansion coefficients of the rigid base and the rigid substrate are the same.
  • a display device which is formed by the above-mentioned one of the manufacturing methods, including: a chip packaging structure and a display panel; the chip packaging structure includes at least A chip packaging unit; the chip packaging unit at least includes: a flexible substrate, a rigid substrate arranged on one side of the flexible substrate, and a pin layer arranged on the side of the flexible substrate away from the rigid substrate, the lead The foot layer includes at least a plurality of first pins, and the orthographic projections of the first pins on the flexible base are located within the orthographic projection of the rigid base on the flexible base; the display panel includes a non-display area , the non-display area includes a rigid substrate and a binding portion disposed on the rigid substrate; the first pin of the chip packaging structure is bound and connected to the binding portion of the display panel ;
  • the display device is formed by the above-mentioned preparation method, including: a chip packaging structure and a display panel; the chip packaging structure includes at least one chip packaging unit; the chip packaging unit includes: a flexible substrate, and a The pin layer on one side of the flexible substrate, the pin layer at least includes a plurality of first pins; the display panel includes a non-display area, the non-display area includes a rigid substrate and is arranged on the rigid substrate The binding portion on the chip packaging structure; the first pin of the chip package structure is bound and connected to the binding portion of the display panel.
  • the distance between the first pin and the flexible base along the direction perpendicular to the flexible base is greater than the distance between the adjacent part of the first pin and the flexible base along the direction perpendicular to the flexible base. The distance from the flexible base.
  • the distance between the first pin and the flexible base along the direction perpendicular to the flexible base, and the adjacent part of the first pin along the direction perpendicular to the flexible base and the distance between The difference in the distance of the flexible substrate is in the range of 2-8 microns.
  • the chip package unit further includes at least one lead unit, and the lead unit is arranged between the lead layer and the flexible substrate;
  • a distance between a portion covered by a pin and the flexible base along a direction perpendicular to the flexible base is smaller than a distance between a portion covered by the first pin and the flexible base along a direction perpendicular to the flexible base ;
  • the thickness of the flexible base is uniform along the direction perpendicular to the flexible base;
  • the wiring unit includes: a first wiring layer and a first organic layer, and the first organic layer covers the first wiring layer; the first wiring layer includes at least a plurality of first wiring lines and/or a plurality of second wiring layers. A wiring pin; the first wiring and/or the first wiring pin are electrically connected to the corresponding first pin.
  • the portion not covered by the first pin is along a direction perpendicular to the The distance between the direction of the flexible base and the flexible base is smaller than the distance between the part covered by the first pin and the flexible base in a direction perpendicular to the flexible base;
  • the thickness of the other lead units along the direction perpendicular to the flexible base is uniform.
  • the chip packaging unit further includes a water-oxygen insulating layer, wherein the water-oxygen insulating layer covers the flexible base, and the pin layer is arranged on a side of the water-oxygen insulating layer away from the flexible base. side;
  • the thickness of the part not covered by the first lead is smaller than the thickness of the part covered by the first lead.
  • the first pin includes at least one conductive layer, and the material of the conductive layer includes metal or metal alloy.
  • the first pin includes a layer of the conductive layer
  • the first pin further includes an anti-oxidation layer, and the anti-oxidation layer covers the conductive layer.
  • the first lead includes multiple layers of the conductive layer
  • the first lead includes a first conductive layer, a second conductive layer and a second conductive layer stacked on the flexible substrate.
  • the thickness of the first conductive layer along the direction perpendicular to the flexible substrate and the thickness of the third conductive layer along the direction perpendicular to the flexible substrate are respectively smaller than the thickness of the second conductive layer along the direction perpendicular to the flexible substrate.
  • materials of the first conductive layer and the third conductive layer are the same, and materials of the first conductive layer and the second conductive layer are different.
  • the chip packaging unit further includes at least one lead unit, the lead unit is disposed between the lead layer and the flexible substrate; the lead unit includes: a first lead layer and a first organic layer , the first organic layer covers the first wiring layer;
  • the first wiring layer includes a plurality of first wirings, and the layer structure included in the first wiring is the same as the layer structure included in the first pin;
  • the first wiring layer includes a plurality of first wiring pins, and the layer structure included in the first wiring pins is the same as the layer structure included in the first pins.
  • the chip packaging unit further includes at least one lead unit, the lead unit is disposed between the lead layer and the flexible substrate; the lead unit includes: a first lead layer and a first organic layer , the first organic layer covers the first wiring layer;
  • the first wiring layer includes a plurality of first wirings, the first wirings include a multi-layer conductive layer, and the first pin includes a conductive layer;
  • the first wiring layer includes a plurality of first wiring pins, the first wiring pins include multiple conductive layers stacked, and the first pins include one conductive layer.
  • multiple first pins are arranged in an array.
  • the pin layer also includes: a plurality of second pins, and a plurality of the second pins are arranged on On one side of the flexible substrate, the display device further includes a driving board, and a plurality of the second pins are bound and connected to the driving board.
  • the second pin and the first pin are arranged on the same layer.
  • the chip packaging unit further includes a chip, and the first pin and the second pin are respectively electrically connected to the chip.
  • the display panel further includes a display area connected to the non-display area;
  • the length of the side bound to the display panel in the chip packaging structure along the preset direction, the length of the binding part of the display panel along the preset direction, and the length of the display panel The three display areas have the same length along the preset direction.
  • FIG. 1 is a schematic structural diagram of a chip packaging unit provided in an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • Fig. 3 is a structural schematic diagram after binding of Fig. 1 and Fig. 2;
  • Fig. 4 is a structural schematic diagram after peeling off the rigid substrate in Fig. 3;
  • Fig. 5, Fig. 6a, Fig. 6b and Fig. 7 are schematic structural diagrams of four kinds of chip packaging units provided by the embodiment of the present application after bending;
  • FIG. 8 is a schematic structural diagram of another chip packaging unit provided by the embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a single-layer wiring chip packaging unit provided by an embodiment of the present application.
  • Fig. 10 is a sectional view along CC1 direction of Fig. 9;
  • Fig. 11 is a sectional view along the C2C3 direction of Fig. 9;
  • FIG. 12 is a schematic structural diagram of a first wiring layer provided by an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a pin layer provided by an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a chip packaging unit including two layers of wiring
  • Fig. 15 is a sectional view along the EE1 direction of Fig. 14;
  • Figure 16 is a cross-sectional view along the E2E3 direction of Figure 14;
  • 17 is a schematic structural view of a chip packaging unit including two lead units
  • Fig. 18 is a schematic structural diagram of another chip packaging unit provided by the embodiment of the present application.
  • FIG. 19 and FIG. 20 are structural schematic diagrams of two chip packaging structures including two chips provided by the embodiment of the present application.
  • 21-24 are schematic diagrams of the arrangement structure of four kinds of multiple first pins provided by the embodiment of the present application.
  • FIG. 25 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • 26-27 are structural schematic diagrams of two kinds of display panels and chip packaging structures provided by the embodiments of the present application.
  • words such as “first”, “second”, and “third” are used to distinguish the same or similar items with basically the same functions and functions, only for clearly describing the technology of the embodiments of the present application scheme, and should not be understood as indicating or implying the relative importance or implying the number of indicated technical features.
  • orientations or positional relationships indicated by the terms “upper”, “lower”, etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the application and simplifying the description, rather than indicating or None to imply that a referenced device or element must have a particular orientation, be constructed, and operate in a particular orientation should therefore not be construed as limiting the application.
  • An embodiment of the present application provides a method for manufacturing a display device, the method comprising:
  • the chip packaging structure includes at least one chip packaging unit 1 as shown in FIG.
  • the base is within the orthographic projection of the flexible base.
  • the material of the above flexible base is not limited, for example, the material of the flexible base may include flexible materials such as polyimide (PI).
  • the material of the above-mentioned rigid base is not limited, for example, the material of the rigid base may include rigid materials such as glass.
  • the specific method for forming the above-mentioned chip package structure can be determined according to the specific structure.
  • a rigid base, a flexible base and a pin layer may be formed in sequence.
  • the rigid base of the chip packaging unit can be set opposite to the entire surface of the flexible base as shown in Figure 1; or, it can also be set only in the area corresponding to the first pin; Corresponding area, and other binding areas (for example: chip binding area and/or driver board binding area) settings.
  • TN Transmission Nematic, twisted nematic
  • VA Vertical Alignment, vertical orientation
  • IPS In-Plane Switching, plane conversion
  • ADS Advanced Super Dimension Switch, advanced ultra-dimensional field switching
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • the material of the above rigid substrate is not limited, for example, the material of the rigid substrate may include rigid materials such as glass.
  • the material of the rigid substrate may be the same as that of the rigid base of the chip package unit, and in this case, the coefficients of thermal expansion of the two materials are the same.
  • the above-mentioned display panel may also include a display area (Active Area, AA), and the display area is connected to a non-display area, wherein the display area refers to an area for realizing display, and the non-display area is generally used for setting a driving circuit and the like.
  • AA Active Area
  • the chip package structure includes a PI flexible substrate, and the display panel includes a glass substrate, and the thermal expansion coefficients of PI and glass are different.
  • temperature compensation is required, that is, the upper and lower substrates are heated at different temperatures to achieve upper and lower bonding.
  • the plurality of first pins and the orthographic projection on the flexible substrate are located within the orthographic projection of the rigid substrate on the flexible substrate; at the same time, the binding of the display panel
  • the part is arranged on the rigid substrate, and the thermal expansion coefficients of the rigid substrate and the rigid substrate are the same or similar.
  • the compensation amount introduced by thermal expansion can be minimized, thereby achieving high-precision bonding.
  • the above method further include:
  • LLO laser lift off technique
  • thermal dissociation thermal dissociation
  • mechanical dissociation mechanical dissociation
  • the rigid base can also be kept; or it can be thinned by grinding and other methods and brought into the terminal; the specific choice can be made according to actual requirements.
  • the chip packaging structure is bent to form three structures as shown in FIGS. 5-7.
  • the rigid base of the chip package unit included in the end product is not reserved;
  • the rigid base of the chip package unit included in the end product is reserved in the area corresponding to the first pin and the chip binding area;
  • the rigid base of the chip packaging unit included in the terminal product is reserved in the area corresponding to the first pin;
  • the rigid base of the chip packaging unit included in the terminal product is reserved in the area corresponding to the first pin, Both the fixed area and the driver board binding area are reserved.
  • the thermal expansion coefficients of the rigid base and the rigid substrate are the same.
  • the rigid base and the material of the rigid substrate may both include glass.
  • the thermal expansion coefficients of the rigid substrate and the rigid substrate may also be similar.
  • the material of the rigid substrate may include glass
  • the material of the rigid substrate may include PET (Polyethylene Terephthalate, polyethylene terephthalate).
  • the embodiment of the present application also provides a display device, the display device is formed by the above-mentioned preparation method of steps S01-S03, the display device includes: a chip packaging structure and a display panel; the chip packaging structure includes at least one chip packaging unit; refer to the figure 6 and FIG.
  • the chip packaging unit at least includes: a flexible substrate 11, a rigid substrate 10 disposed on one side of the flexible substrate 11, and a pin layer 12 disposed on the side of the flexible substrate 11 away from the rigid substrate, and the pin layer is at least Including a plurality of first pins, the orthographic projection of the plurality of first pins on the flexible base is located within the orthographic projection of the rigid base on the flexible base; the display panel includes a non-display area, the non-display area includes a rigid substrate 20 and is arranged on a rigid The bonding part 21 on the substrate 20; the first pin of the chip package structure and the display panel The binding unit binds the connection.
  • the chip packaging unit may include panel binding area B1, chip binding area B2, driver board binding area B3 and other non-binding areas (not framed by dotted lines in Figure 8) as shown in Figure 8 other areas), the panel binding area is used for binding with the display panel, the chip binding area is used for binding with the chip, and the driving board binding area is used for binding with the driving board.
  • the first pins 13 may be disposed in the panel binding area B1.
  • the rigid substrate can only be arranged in the panel binding area; or, in order to ensure the degree of warpage, the rigid substrate can be arranged in the panel binding area and the driving plate binding area; or, the rigid substrate can be arranged In the panel binding area, the chip binding area and the driving board binding area; or, the rigid substrate may be disposed in all areas of the chip packaging unit, which is not limited here.
  • the display device provided in the embodiment of the present application can also be formed by the above-mentioned preparation method of steps S01-S04, the display device includes: a chip packaging structure and a display panel; the chip packaging structure includes at least one chip packaging unit; refer to FIG. 4 and FIG. 5, the chip packaging unit includes: a flexible substrate 11, and a pin layer 12 arranged on one side of the flexible substrate 11, the pin layer includes at least a plurality of first pins; the display panel includes a non-display area, and the non-display area includes The rigid substrate 20 and the binding part 21 arranged on the rigid substrate 20; the first pin of the chip packaging structure is bound and connected to the binding part of the display panel.
  • the thickness of the above-mentioned flexible substrate is not limited, for example, the thickness range may be 10-40 microns, which may include a single-layer or multi-layer structure, which is not limited here.
  • the orthographic projections of the plurality of first pins and the flexible substrate are located at the position of the orthographic projection of the rigid substrate on the flexible substrate.
  • the binding portion of the display panel is set on the rigid substrate, and the thermal expansion coefficients of the rigid substrate and the rigid substrate are the same or similar, so the compensation amount introduced by thermal expansion can be minimized during the bonding process, reducing Binding bias and binding spacing for high precision binding.
  • the display device can greatly improve the binding accuracy of the chip packaging unit and the display panel, thereby greatly increasing the number of output channels of the chip packaging unit, thereby meeting the requirements of high-resolution display products (eg, 3D display products).
  • the first pin and the binding part can be bound with anisotropic conductive film (ACF, Anisotropic Conductive Films).
  • ACF anisotropic Conductive Films
  • FIG. 10 As shown in FIG. 11 , the distance H1 between the first pin 13 and the flexible base 11 along the direction perpendicular to the flexible base 11 is greater than the distance between the adjacent part of the first pin and the flexible base 11 along the direction perpendicular to the flexible base 11 H2.
  • the distance between the first pin and the flexible base along the direction perpendicular to the flexible base, and the adjacent part of the first pin along the distance perpendicular to the flexible base is 2-8 microns, for example, the difference may be 2 microns, 4 microns, 6 microns or 8 microns and so on.
  • the above-mentioned chip package unit may adopt the single-layer wiring structure shown in FIG. 10 and FIG. 11 , or adopt the multi-layer wiring structure shown in FIG. 15 and FIG. 16 , which is not limited here.
  • a chip packaging unit including multilayer wires is provided below.
  • the chip package unit further includes at least one lead unit.
  • the lead unit 3 is arranged between the lead layer and the flexible substrate 11;
  • the distance H4 between the part covered by the pin and the flexible base along the direction perpendicular to the flexible base is less than the distance H3 between the part covered by the first pin and the flexible base along the direction perpendicular to the flexible base;
  • the flexible base is along the direction perpendicular to the flexible base
  • the thickness H in the direction is uniform.
  • the lead unit 3 includes: a first lead layer 18 and a first organic layer 19, the first organic layer 19 covers the first lead layer 18; the first lead layer 18 includes at least a plurality of first lead layers A wiring 182 and/or a plurality of first wiring pins 181; the first wiring 182 and/or the first wiring pins 181 are electrically connected to the corresponding first pins 13, for example, the first wiring The wire pins 181 can be electrically connected to the corresponding first pins 13 through the transition holes 180 shown in FIG. 14 .
  • the above-mentioned first wiring layer includes at least a plurality of first wirings and/or a plurality of first wiring pins including three situations: first, the first wiring layer includes at least a plurality of first wirings, at this time, the first A trace is electrically connected to the corresponding first pin, and the first trace and the first pin may or may not overlap along a direction perpendicular to the flexible substrate.
  • the first wiring layer includes at least a plurality of first wiring pins. At this time, the first wiring pins are electrically connected to the corresponding first pins. At this time, the first wiring pins are connected to the first wiring pins The leads may or may not overlap in a direction perpendicular to the flexible substrate.
  • the first wiring layer at least includes a plurality of first wirings 182 and a plurality of first wiring pins 181 as shown in FIG.
  • the three first pins are electrically connected, the first trace and the first trace pin can be arranged on the same layer, and the first trace pin and the first trace are respectively connected with the first pin in a direction perpendicular to the flexible substrate It can be overlapped or not; in order to reduce the generation of parasitic capacitance, as shown in FIG. 14, the first trace pin 181 overlaps with the first lead 13 along the direction perpendicular to the flexible substrate, further, the orthographic projection of the first trace pin on the flexible substrate is located at the first lead The feet are within the orthographic projection on the flexible substrate.
  • One patterning process refers to the process of forming the required layer structure after one exposure.
  • a patterning process includes processes such as masking, exposure, development, etching and stripping.
  • the first wiring and the first wiring pin may include a conductive layer, for example: a copper conductive layer; or It may include multiple conductive layers, for example: a three-layer laminated structure of titanium conductive layer, aluminum conductive layer and titanium conductive layer, or a three-layer laminated structure of molybdenum conductive layer, aluminum conductive layer and molybdenum conductive layer, etc.
  • the specific layer structure of the first trace, the first trace pin and the specific layer structure of the first pin may be the same, or may also be different, which is not limited here.
  • the above-mentioned first organic layer may include a single-layer structure or a multi-layer structure, which is not limited here. Its thickness may be 5-10 microns. In the case where the first organic layer includes a multilayer structure, the materials of the organic layers may be the same or different.
  • the functions of the first pin and the first wiring can be realized respectively, so as to further set more pins and further increase the number of output channels of the chip package structure.
  • the part not covered by the first lead is along the direction perpendicular to the flexible substrate.
  • the distance H6 between the direction and the flexible base is smaller than the distance H5 between the part covered by the first lead along the direction perpendicular to the flexible base and the flexible base; the thickness H7 of the other lead units along the direction perpendicular to the flexible base is uniform.
  • the structure is simple and easy to implement, and only needs to pattern the first organic layer of the lead unit which is in contact with the first pin, so as to ensure sufficient glue overflow space.
  • FIG. 17 shows an example including two lead units.
  • the chip packaging unit further includes a water and oxygen isolation layer 16 shown in FIG. 10, wherein the water and oxygen isolation layer 16 Layer 16 covers the flexible base 11, and the pin layer is arranged on the side of the water-oxygen barrier layer away from the flexible base; as shown in FIG.
  • the thickness h1 of the portion covered by the first lead is not limited, for example, the thickness range is 100-500 nanometers, and its material may include silicon dioxide or silicon nitride.
  • the first pin includes at least one conductive layer, and the material of the conductive layer includes metal or metal alloy.
  • the material of the conductive layer may include Mo, Al, Ti, Cu and other metals or alloys.
  • the first pin can be formed by etching a thick copper plate or electroplating thick copper, and the thickness of the copper is about 8 microns. Due to the isotropy of wet etching, it is difficult to make the size deviation (CD Bias) smaller, so the pitch of the formed pins is greater than 16 microns.
  • the first pin in the case where the first pin includes a conductive layer, if the first pin is made of a material that is easily oxidized, such as copper, in order to avoid copper oxidation, the first pin also includes an anti-oxidation layer 13, An anti-oxidation layer covers the conductive layer.
  • the anti-oxidation layer can use chemical plating of Sn, Au, etc., with a thickness ranging from 0.5um to 2um; or, it can also be covered with ITO (Indium Tin Oxide, indium tin oxide) on the surface of the first pin to prevent oxidation.
  • the anti-oxidation layer is also conducive to increasing the height of the area where the first pin is located, ensuring sufficient glue overflow space when it is subsequently bound to the panel.
  • a solder resist layer (for example: green oil) may be provided on the non-bonding area of the chip packaging unit, with a thickness ranging from 5-20 microns.
  • the first pin includes a multi-layer conductive layer
  • the first pin includes a first conductive layer, a second conductive layer and a third conductive layer stacked on a flexible substrate; wherein, the first The thickness of the conductive layer along the direction perpendicular to the flexible substrate and the thickness of the third conductive layer along the direction perpendicular to the flexible substrate are respectively smaller than the thickness of the second conductive layer along the direction perpendicular to the flexible substrate.
  • the materials of the above-mentioned first conductive layer and the third conductive layer may be the same or different.
  • the above-mentioned second conductive layer can be made of metal materials such as aluminum, and the first conductive layer and the third conductive layer can be made of metal materials such as molybdenum or titanium, so that finer wiring can be formed by photolithography or electroplating, and the wiring distance ( pitch) can be reduced to less than 16 microns, or even to a few microns (for example: 3.6 microns or 5 microns, etc.); and if copper is used, the minimum pitch of the wiring is 16-18 microns.
  • the multi-layer stack structure can greatly reduce the wiring space, so that the chip package unit can provide more output pins to meet the needs of high-resolution display products and 3D display products.
  • the trace spacing refers to the sum of the line width W1 of the trace (the trace 17 shown in FIG. 9 ) and the distance D1 between adjacent traces
  • the pin pitch is the guideline The sum of the width W of the pin (the first pin 13 shown in FIG. 9 ) and the distance D between adjacent pins.
  • the materials of the first conductive layer and the third conductive layer are the same, and the materials of the first conductive layer and the second conductive layer are different.
  • the material of the second conductive layer may include aluminum, etc.
  • the materials of the first conductive layer and the third conductive layer may include molybdenum or titanium.
  • the chip packaging unit further includes at least one lead unit, and the lead unit is arranged between the lead layer and the flexible substrate; the lead unit includes: a first lead layer and a first organic layer, the first organic layer covers the first wiring layer.
  • the first wiring layer includes a plurality of first wirings, and the layer structure included in the first wiring is the same as that included in the first pin; and/or, the first wiring layer includes a plurality of first wiring pins, and the first wiring layer includes a plurality of first wiring pins.
  • the layer structure included in the first trace pin is the same as the layer structure included in the first pin.
  • the chip packaging unit includes three cases: first, the first wiring layer includes a plurality of first wirings, at this time, the layer structure included in the first wiring is the same as the layer structure included in the first pin, for example,
  • the first routing may also include a single-layer or multi-layer structure.
  • the first wiring layer includes a plurality of first wiring pins, and the layer structure included in the first wiring pins is the same as the layer structure included in the first pins.
  • the first wiring layer may also include a single
  • For the layer or multi-layer structure please refer to the description of the layer structure of the first pin above for details, and details will not be repeated here.
  • the first wiring layer includes multiple first wirings and multiple first wiring pins, and the first wiring and the first wiring pins may include a single-layer or multi-layer structure.
  • the first wiring and the first wiring pins may include a single-layer or multi-layer structure.
  • the chip packaging unit further includes at least one lead unit, and the lead unit is arranged between the lead layer and the flexible substrate; the lead unit includes: a first lead layer and a first organic layer, and the first organic layer covers the first lead layer.
  • the first wiring layer includes a plurality of first wirings, the first wiring includes a multi-layer conductive layer arranged in layers, and the first pin includes a layer of conductive layer; and/or, the first wiring layer includes a plurality of first wirings
  • the wire pins, the first wire pins include multiple layers of conductive layers stacked, and the first pins include one layer of conductive layers.
  • the chip packaging unit includes three situations: first, the first wiring layer includes a plurality of first wirings, the first wirings include a multi-layer conductive layer arranged in layers, and the first pin includes a layer of conductive layer, for example Yes, the first trace includes a titanium conductive layer, an aluminum conductive layer, and a titanium conductive layer that are laminated, and the first pin includes a copper conductive layer.
  • the first wiring layer includes a plurality of first wiring pins, the first wiring pins include multi-layer conductive layers arranged in layers, and the first pins include a layer of conductive layers.
  • the first wiring The wire pin includes a titanium conductive layer, an aluminum conductive layer and a titanium conductive layer that are laminated, and the first pin includes a copper conductive layer.
  • the first wiring layer includes a plurality of first wirings and a plurality of first wiring pins, the first wiring and the first wiring pins include multilayer conductive layers arranged in stacks, and the first pins A conductive layer is included; for example, the first trace and the first trace pin include a titanium conductive layer, an aluminum conductive layer, and a titanium conductive layer that are laminated, and the first pin includes a copper conductive layer.
  • the display device includes at least one chip packaging unit, and the number of chip packaging units can be selected according to the size of the product.
  • the arrangement of the chips included in each chip packaging unit is not limited.
  • each chip 14 can be arranged laterally along the OA direction as shown in FIG. 19; or, each chip 14 It can be arranged vertically along the OB direction as shown in FIG. 20 ; or, partly arranged horizontally and partly arranged vertically; it is not limited here.
  • multiple first pins are arranged in an array.
  • the multiple first pins may be arranged in multiple rows, for example: 2 rows, 3 rows, 4 rows (as shown in FIGS. 21-24 ), or 5 rows, and so on.
  • the setting directions of multiple first pins in each row and the setting directions of multiple rows are not limited.
  • multiple rows can be arranged vertically as shown in Figure 21, or as shown in Figure 22;
  • the first pins can be arranged vertically as shown in FIG. 21 and FIG. 22 , or arranged obliquely as shown in FIG. 23 and FIG. 24 , thereby forming a figure-eight arrangement.
  • the total length of the plurality of first pins may be 60 mm, 68 mm, 70 mm or 127 mm or more, which may be adjusted according to the length of the panel.
  • the pin layer further includes: a plurality of second pins 15 shown in FIG. 8 and FIG.
  • the display device further includes a driving board 4, and a plurality of second pins 15 are bound and connected to the driving board 4.
  • the driver board here can be a PCB (Printed Circuit Board, printed circuit board) circuit board, or it can also be an FPC (Flexible Printed Circuit, flexible circuit board) circuit board, considering further reducing the frame, you can choose the latter.
  • PCB Print Circuit Board, printed circuit board
  • FPC Flexible Printed Circuit, flexible circuit board
  • the second pin and the first pin are arranged on the same layer.
  • the second pin and the first pin include the same layer structure.
  • the second pin may include a single-layer or multi-layer structure.
  • the chip packaging unit further includes a chip (IC) as shown in FIG. 8 , and the first pin 13 and the second pin 15 are respectively electrically connected to the chip 14 . Since the number of the second pins bound and connected to the driver board is less than the number of the first pins bound and connected to the display panel, the extra second pins can also be used for binding with the display panel, thereby further Increase output channels while saving space.
  • an encapsulation layer such as a resin layer (resin), may also be provided.
  • the display panel further includes a display area connected to the non-display area; the length of the side of the chip package structure bound to the display panel along a preset direction, the binding of the display panel The length of the fixed portion along the preset direction and the length of the display area of the display panel along the preset direction are the same.
  • the size of the PI-based COF is limited.
  • the display panel In order to match the size of the COF, the display panel needs to set a fan-shaped lead area (Fanout area) A2 as shown in Figure 26 in the non-display area. , gather the leads in a certain area, and then connect with the binding part.
  • the leads in the lead area In order to ensure equal-resistance wiring, the leads in the lead area are set in a few shapes, which takes up a lot of space and results in a large frame.
  • the present application uses a glass substrate to form a chip package structure, and the size is not limited. Referring to FIG.
  • the length L2 of the side of the chip package structure bound to the display panel along the preset direction (the OA direction shown in FIG. 27 ) is shown in FIG.
  • the length L1 of the binding portion of the display panel along the preset direction (the OA direction shown in FIG. 27 )
  • the length L of the display area A0 of the display panel along the preset direction (the OA direction shown in FIG. 27 ) are the same
  • the lead wires 100 of the display panel can be directly drawn out along the direction perpendicular to the preset direction (the OB direction shown in FIG.
  • the bezel is convenient to form a display product with an ultra-narrow bezel.

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Abstract

本申请提供了一种显示装置及其制备方法，涉及显示技术领域，该显示装置可以大幅提升芯片封装单元和显示面板的绑定精度，从而大幅提升芯片封装单元的输出通道数量，进而满足高分辨率显示产品的要求。形成芯片封装结构，芯片封装结构包括至少一个芯片封装单元；芯片封装单元至少包括：柔性基底、设置在柔性基底一侧的刚性基底、以及设置在柔性基底远离刚性基底一侧的引脚层，引脚层至少包括多个第一引脚，多个第一引脚在柔性基底的正投影位于刚性基底在柔性基底的正投影以内；形成显示面板，显示面板包括非显示区，非显示区包括刚性衬底和设置在刚性衬底上的绑定部；将芯片封装结构的第一引脚与显示面板的绑定部进行绑定连接。

Description

显示装置及其制备方法
相关申请的交叉引用
本申请要求在2022年03月02日提交中国专利局、申请号为202210204960.4、名称为“一种显示装置及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示装置及其制备方法。
背景技术
随着高分辨率3D显示产品的发展，多通道(channel)数的COF(Chip On Film，覆晶薄膜)驱动是未来趋势。COF是一种芯片封装技术，即将驱动芯片(IC)固定在柔性线路板上的晶粒软膜构装技术。3D显示产品中，COF与显示面板连接；但是囿于制作工艺，COF与显示面板的绑定精度受限，其可输出的驱动通道数有限，难以满足高分辨率3D显示产品的要求。
发明内容
本申请的实施例采用如下技术方案：
一方面，提供了一种显示装置的制备方法，该方法包括：
形成芯片封装结构，其中，所述芯片封装结构包括至少一个芯片封装单元；所述芯片封装单元至少包括：柔性基底、设置在所述柔性基底一侧的刚性基底、以及设置在所述柔性基底远离所述刚性基底一侧的引脚层，所述引脚层至少包括多个第一引脚，多个所述第一引脚在所述柔性基底的正投影位于所述刚性基底在所述柔性基底的正投影以内；
形成显示面板，其中，所述显示面板包括非显示区，所述非显示区包括刚性衬底和设置在所述刚性衬底上的绑定部；
将所述芯片封装结构的所述第一引脚与所述显示面板的所述绑定部进行绑定连接。
可选的，在将所述芯片封装结构的所述第一引脚与所述显示面板的所述绑定部进行绑定连接之后，所述方法还包括：
去除所述芯片封装单元的全部所述刚性基底。
可选的，所述刚性基底和所述刚性衬底的热膨胀系数相同。
另一方面，提供了一种显示装置，所述显示装置采用上述所述的一种制备方法形成，包括：芯片封装结构和显示面板；所述芯片封装结构包括至少 一个芯片封装单元；所述芯片封装单元至少包括：柔性基底、设置在所述柔性基底一侧的刚性基底、以及设置在所述柔性基底远离所述刚性基底一侧的引脚层，所述引脚层至少包括多个第一引脚，多个所述第一引脚在所述柔性基底的正投影位于所述刚性基底在所述柔性基底的正投影以内；所述显示面板包括非显示区，所述非显示区包括刚性衬底和设置在所述刚性衬底上的绑定部；所述芯片封装结构的所述第一引脚与所述显示面板的所述绑定部绑定连接；
或者，所述显示装置采用上述所述的制备方法形成，包括：芯片封装结构和显示面板；所述芯片封装结构包括至少一个芯片封装单元；所述芯片封装单元包括：柔性基底、以及设置在所述柔性基底一侧的引脚层，所述引脚层至少包括多个第一引脚；所述显示面板包括非显示区，所述非显示区包括刚性衬底和设置在所述刚性衬底上的绑定部；所述芯片封装结构的所述第一引脚与所述显示面板的所述绑定部绑定连接。
可选的，所述第一引脚沿垂直于所述柔性基底的方向与所述柔性基底的距离，大于所述第一引脚的相邻部分沿垂直于所述柔性基底的方向与所述柔性基底的距离。
可选的，所述第一引脚沿垂直于所述柔性基底的方向与所述柔性基底的距离，与所述第一引脚的相邻部分沿垂直于所述柔性基底的方向与所述柔性基底的距离的差值的范围为2-8微米。
可选的，所述芯片封装单元还包括至少一个引线单元，所述引线单元设置在所述引脚层和所述柔性基底之间；所有所述引线单元形成的整体中，未被所述第一引脚覆盖的部分沿垂直于所述柔性基底的方向与所述柔性基底的距离，小于被所述第一引脚覆盖的部分沿垂直于所述柔性基底的方向与所述柔性基底的距离；所述柔性基底沿垂直于所述柔性基底的方向的厚度均一；
所述引线单元包括：第一引线层和第一有机层，所述第一有机层覆盖所述第一引线层；所述第一引线层至少包括多条第一走线和/或多个第一走线引脚；所述第一走线和/或所述第一走线引脚，与对应的所述第一引脚电连接。
可选的，所有所述引线单元中，与所述第一引脚相接触的所述引线单元的所述第一有机层中，未被所述第一引脚覆盖的部分沿垂直于所述柔性基底的方向与所述柔性基底的距离，小于被所述第一引脚覆盖的部分沿垂直于所述柔性基底的方向与所述柔性基底的距离；
其余所述引线单元沿垂直于所述柔性基底的方向的厚度均一。
可选的，所述芯片封装单元还包括水氧隔绝层，其中，所述水氧隔绝层覆盖所述柔性基底，所述引脚层设置在所述水氧隔绝层远离所述柔性基底的一侧；
所述柔性基底中，未被所述第一引脚覆盖的部分的厚度，小于被所述第一引脚覆盖的部分的厚度。
可选的，所述第一引脚包括至少一层导电层，所述导电层的材料包括金属或者金属合金。
可选的，在所述第一引脚包括一层所述导电层的情况下，所述第一引脚还包括防氧化层，所述防氧化层覆盖所述导电层。
可选的，在所述第一引脚包括多层所述导电层的情况下，所述第一引脚包括叠层设置在所述柔性基底上的第一导电层、第二导电层和第三导电层；
其中，所述第一导电层沿垂直于所述柔性基底的方向的厚度、以及所述第三导电层沿垂直于所述柔性基底的方向的厚度分别小于所述第二导电层沿垂直于所述柔性基底的方向的厚度。
可选的，所述第一导电层和所述第三导电层的材料相同，所述第一导电层和所述第二导电层的材料不同。
可选的，所述芯片封装单元还包括至少一个引线单元，所述引线单元设置在所述引脚层和所述柔性基底之间；所述引线单元包括：第一引线层和第一有机层，所述第一有机层覆盖所述第一引线层；
所述第一引线层包括多条第一走线，所述第一走线包括的层结构和所述第一引脚包括的层结构相同；
和/或，所述第一引线层包括多个第一走线引脚，所述第一走线引脚包括的层结构和所述第一引脚包括的层结构相同。
可选的，所述芯片封装单元还包括至少一个引线单元，所述引线单元设置在所述引脚层和所述柔性基底之间；所述引线单元包括：第一引线层和第一有机层，所述第一有机层覆盖所述第一引线层；
所述第一引线层包括多条第一走线，所述第一走线包括叠层设置的多层导电层，所述第一引脚包括一层导电层；
和/或，所述第一引线层包括多个第一走线引脚，所述第一走线引脚包括叠层设置的多层导电层，所述第一引脚包括一层导电层。
可选的，多个所述第一引脚呈阵列排布。
可选的，所述引脚层还包括：多个第二引脚，多个所述第二引脚设置在 所述柔性基底的一侧，所述显示装置还包括驱动板，多个所述第二引脚与所述驱动板绑定连接。
可选的，所述第二引脚和所述第一引脚同层设置。
可选的，，所述芯片封装单元还包括芯片，所述第一引脚和所述第二引脚分别与所述芯片电连接。
可选的，所述显示面板还包括与所述非显示区相连的显示区；
所述芯片封装结构中与所述显示面板绑定的一侧沿预设方向的长度、所述显示面板的所述绑定部沿所述预设方向的长度、以及所述显示面板的所述显示区沿所述预设方向的长度三者相同。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其它目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种芯片封装单元的结构示意图；
图2为本申请实施例提供的一种显示面板的结构示意图；
图3为图1和图2绑定后的结构示意图；
图4为将图3中刚性基底剥离后的结构示意图；
图5、图6a、图6b和图7为本申请实施例提供的四种芯片封装单元弯折后的结构示意图；
图8为本申请实施例提供的另一种芯片封装单元的结构示意图；
图9为本申请实施例提供的一种单层走线的芯片封装单元的结构示意图；
图10为图9沿CC1方向的截面图；
图11为图9沿C2C3方向的截面图；
图12本申请实施例提供的一种第一引线层的结构示意图；
图13为本申请实施例提供的一种引脚层的结构示意图；
图14为包括两层走线的芯片封装单元的结构示意图；
图15为图14沿EE1方向的截面图；
图16为图14沿E2E3方向的截面图；
图17为包括两个引线单元的芯片封装单元的结构示意图；
图18为本申请实施例提供的又一种芯片封装单元的结构示意图；
图19和图20为本申请实施例提供的两种包括两个芯片的芯片封装结构的结构示意图；
图21-24为本申请实施例提供的四种多个第一引脚的排布结构示意图；
图25为本申请实施例提供的一种显示装置的结构示意图；
图26-27为本申请实施例提供的两种显示面板和芯片封装结构的结构示意图。
具体实施例
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的实施例中，采用“第一”、“第二”、“第三”等字样对功能和作用基本相同的相同项或相似项进行区分，仅为了清楚描述本申请实施例的技术方案，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
在本申请的实施例中，“多个”的含义是两个或两个以上，“多条”的含义是两条或两条以上，“至少一个”的含义是一个或一个以上，除非另有明确具体的限定。
在本申请的实施例中，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
本申请实施例提供了一种显示装置的制备方法，该方法包括：
S01、形成芯片封装结构，其中，芯片封装结构包括至少一个如图1所示的芯片封装单元1；芯片封装单元1至少包括：柔性基底11、设置在柔性基底11一侧的刚性基底10、以及设置在柔性基底11远离刚性基底10一侧的引脚层12，引脚层至少包括多个第一引脚(图1未示出)，多个第一引脚在柔性基底的正投影位于刚性基底在柔性基底的正投影以内。
上述柔性基底的材料不做限定，示例的，该柔性基底的材料可以包括聚酰亚胺(PI)等柔性材料。上述刚性基底的材料不做限定，示例的，该刚性基底的材料可以包括玻璃等刚性材料。
上述形成芯片封装结构的具体方法可以根据具体结构确定。示例的，可以依次形成刚性基底、柔性基底和引脚层。
需要说明的是，芯片封装单元的刚性基底可以图1所示与柔性基底整面相对设置；或者，还可以仅在与第一引脚对应的区域设置；或者，还可以在与第一引脚对应的区域、以及其他绑定区域内(例如：芯片绑定区和/或驱动板绑定区)设置。
S02、形成如图2所示的显示面板，其中，显示面板2包括非显示区A1，非显示区A1包括刚性衬底和设置在刚性衬底上的绑定部21。
这里对于显示面板的类型不做限定，其类型可以是TN(Twisted Nematic，扭曲向列)型、VA(Vertical Alignment，垂直取向)型、IPS(In-Plane Switching，平面转换)型或ADS(Advanced Super Dimension Switch，高级超维场转换)型等液晶显示面板，还可以是OLED(Organic Light-Emitting Diode，有机发光二极管)显示面板。
上述刚性衬底的材料不做限定，示例的，该刚性衬底的材料可以包括玻璃等刚性材料。该刚性衬底的材料与芯片封装单元的刚性基底的材料可以相同，此时，两者材料的热膨胀系数相同。
上述显示面板还可以包括显示区(Active Area，AA)，显示区和非显示区相连，其中，显示区是指用于实现显示的区域，非显示区一般用于设置驱动电路等。
S03、将芯片封装结构的第一引脚与显示面板的绑定部进行绑定连接，得到如图3所示的结构。
相关技术中，芯片封装结构包括PI柔性基材，显示面板包括玻璃基材，PI和玻璃的热膨胀系数不同。在绑定过程中，需要采用温度补偿的方式，即上下基板采用不同温度加热，从而实现上下对合。虽然可以实现一部分补偿，但在实际操作过程中，存在对位精度低及较大良率损失，绑定精度低。基于此，本申请提供的芯片封装结构中，多个第一引脚与在柔性基底的正投影位于刚性基底在柔性基底的正投影以内；同时，显示面板的绑定 部设置在刚性衬底上，而刚性基底和刚性衬底的热膨胀系数相同或者相近，在步骤S03绑定过程中，可以最大限度地降低热膨胀引入的补偿量，从而实现高精度绑定。
可选的，为了尽可能地节省空间，减小产品尺寸，同时有利于弯折，在S03、将芯片封装结构的第一引脚与显示面板的绑定部进行绑定连接之后，上述方法还包括：
S04、去除芯片封装单元的全部刚性基底，得到图4所示的结构。
示例的，可以通过激光剥离技术(LLO)、热解离、或者机械解离等方式剥离。
需要说明的是，在步骤S03之后，也可以将刚性基底保留；或者，通过研磨等方式减薄后带入终端；具体可以根据实际要求选择。为了更进一步减小边框，在步骤S04之后，对芯片封装结构进行弯折，形成如图5-7所示的三种结构。图5中，终端产品包括的芯片封装单元的刚性基底均不保留；图6a中，终端产品包括的芯片封装单元的刚性基底在与第一引脚对应的区域、以及芯片绑定区保留；图6b中，终端产品包括的芯片封装单元的刚性基底在与第一引脚对应的区域保留；图7中，终端产品包括的芯片封装单元的刚性基底在与第一引脚对应的区域、芯片绑定区以及驱动板绑定区均保留。
可选的，刚性基底和刚性衬底的热膨胀系数相同。示例的，刚性基底和刚性衬底的材料可以均包括玻璃。当然，刚性基底和刚性衬底的热膨胀系数也可以相近，示例的，刚性衬底的材料可以包括玻璃，刚性基底的材料可以包括PET(Polyethylene Terephthalate，聚对苯二甲酸乙二醇酯)。
本申请实施例还提供了一种显示装置，该显示装置采用上述步骤S01-S03的制备方法形成，该显示装置包括：芯片封装结构和显示面板；芯片封装结构包括至少一个芯片封装单元；参考图6和图7所示，芯片封装单元至少包括：柔性基底11、设置在柔性基底11一侧的刚性基底10、以及设置在柔性基底11远离刚性基底一侧的引脚层12，引脚层至少包括多个第一引脚，多个第一引脚在柔性基底的正投影位于刚性基底在柔性基底的正投影以内；显示面板包括非显示区，非显示区包括刚性衬底20和设置在刚性衬底20上的绑定部21；芯片封装结构的第一引脚与显示面板的 绑定部绑定连接。
需要说明的是，该芯片封装单元可以包括如图8所示的面板绑定区B1、芯片绑定区B2、驱动板绑定区B3以及其他非绑定区(图8中未被虚线框定的其他区域)，面板绑定区用于与显示面板绑定，芯片绑定区用于与芯片绑定，驱动板绑定区用于与驱动板绑定。第一引脚13可以设置在面板绑定区B1。上述显示装置的芯片封装单元中，刚性基底可以仅设置在面板绑定区；或者，为了保证翘曲度，刚性基底可以设置在面板绑定区和驱动板绑定区；或者，刚性基底可以设置在面板绑定区、芯片绑定区和驱动板绑定区；或者，刚性基底可以设置在芯片封装单元的所有区域，这里不做限定。
或者，本申请实施例提供的显示装置还可以采用上述步骤S01-S04的制备方法形成，该显示装置包括：芯片封装结构和显示面板；芯片封装结构包括至少一个芯片封装单元；参考图4和图5所示，芯片封装单元包括：柔性基底11、以及设置在柔性基底11一侧的引脚层12，引脚层至少包括多个第一引脚；显示面板包括非显示区，非显示区包括刚性衬底20和设置在刚性衬底20上的绑定部21；芯片封装结构的第一引脚与显示面板的绑定部绑定连接。
上述柔性基底的厚度不做限定，示例的，该厚度范围可以是10-40微米，其可以包括单层或者多层结构，这里不做限定。
上述两种显示装置在芯片封装结构的第一引脚与显示面板的绑定部进行绑定的过程中，多个第一引脚与在柔性基底的正投影位于刚性基底在柔性基底的正投影以内，同时，显示面板的绑定部设置在刚性衬底上，而刚性基底和刚性衬底的热膨胀系数相同或者相近，则绑定过程中，可以最大限度地降低热膨胀引入的补偿量，减小绑定偏差和绑定间距，从而实现高精度绑定。该显示装置可以大幅提升芯片封装单元和显示面板的绑定精度，从而大幅提升芯片封装单元的输出通道数量，进而满足高分辨率显示产品(例如：3D显示产品)的要求。
第一引脚与绑定部可以采用各向异性导电胶(ACF，Anisotropic Conductive Films)绑定，为了提供足够的溢胶空间，保证绑定质量，在一个或者多个实施例中，参考图10和图11所示，第一引脚13沿垂直于柔性基底11的方向与柔性基底11的距离H1，大于第一引脚的相邻部分沿垂直于柔性基底11的方向与柔性基底11的距离H2。
可选的，为了保证足够的溢胶空间，同时减小产品尺寸，第一引脚沿垂直于柔性基底的方向与柔性基底的距离，与第一引脚的相邻部分沿垂直于柔性基底的方向与柔性基底的距离的差值的范围为2-8微米，示例的，该差值可以是2微米、4微米、6微米或者8微米等等。
上述芯片封装单元可以采用图10和图11所示的单层走线结构，或者，采用图15和图16所示的多层走线结构，这里不做限定。
下面提供一种包括多层走线的芯片封装单元。
可选的，芯片封装单元还包括至少一个引线单元，参考图15和图16所示，引线单元3设置在引脚层和柔性基底11之间；所有引线单元形成的整体中，未被第一引脚覆盖的部分沿垂直于柔性基底的方向与柔性基底的距离H4，小于被第一引脚覆盖的部分沿垂直于柔性基底的方向与柔性基底的距离H3；柔性基底沿垂直于柔性基底的方向的厚度H均一。
参考图12、图14-16所示，引线单元3包括：第一引线层18和第一有机层19，第一有机层19覆盖第一引线层18；第一引线层18至少包括多条第一走线182和/或多个第一走线引脚181；第一走线182和/或第一走线引脚181，与对应的第一引脚13电连接，示例的，第一走线引脚181可通过图14所示的转接孔180与对应的第一引脚13电连接。
上述第一引线层至少包括多条第一走线和/或多个第一走线引脚包括三种情况：第一种，第一引线层至少包括多条第一走线，此时，第一走线与对应的第一引脚电连接，第一走线与第一引脚沿垂直于柔性基底的方向可以交叠，或者不交叠。第二种，第一引线层至少包括多个第一走线引脚，此时，第一走线引脚与对应的第一引脚电连接，此时，第一走线引脚与第一引脚沿垂直于柔性基底的方向可以交叠，或者不交叠。第三种，第一引线层至少包括如图12所示的多条第一走线182和多个第一走线引脚181，此时，第一走线、第一走线引脚与对应的第一引脚三者电连接，第一走线和第一走线引脚可以同层设置，第一走线引脚和第一走线分别与第一引脚沿垂直于柔性基底的方向可以交叠，或者不交叠；为了减少产生寄生电容，参考图14所示，第一走线182与第一引脚13沿垂直于柔性基底的方向不交叠；为了节约空间，减小间距，参考图14所示，第一走线引脚181与第一引脚13沿垂直于柔性基底的方向交叠，进一步的，第一走线引脚在柔性基底上的正投影位于第一引脚在柔性基底上的正投影以内。这里同层设置 是指采用一次构图工艺制作。一次构图工艺是指经过一次曝光形成所需要的层结构工艺。一次构图工艺包括掩膜、曝光、显影、刻蚀和剥离等工艺。
这里对于第一走线、第一走线引脚的具体层结构不做限定，示例的，第一走线、第一走线引脚可以包括一层导电层，例如：铜导电层；或者还可以包括多层导电层，例如：钛导电层、铝导电层和钛导电层三层叠层结构，或者钼导电层、铝导电层和钼导电层三层叠层结构等等。
这里第一走线、第一走线引脚的具体层结构与第一引脚的具体层结构可以相同，或者，也可以不同，这里不做限定。
上述第一有机层可以包括单层结构或者多层结构，这里不做限定。其厚度可以是5-10微米。在第一有机层包括多层结构的情况下，各层有机层的材料可以相同或者不同。
该结构中，通过设置引脚层和第一引线层，可以分别实现第一引脚和第一走线功能，从而实现进一步设置更多的引脚数量，进一步提高芯片封装结构的输出通道数量。
可选的，所有引线单元中，参考图17所示，与第一引脚13相接触的引线单元3的第一有机层19中，未被第一引脚覆盖的部分沿垂直于柔性基底的方向与柔性基底的距离H6，小于被第一引脚覆盖的部分沿垂直于柔性基底的方向与柔性基底的距离H5；其余引线单元沿垂直于柔性基底的方向的厚度H7均一。该结构简单易实现，仅需对与第一引脚相接触的引线单元的第一有机层图案化，即可保证足够的溢胶空间。图17以包括两个引线单元为例进行绘示。
在一个或者多个实施例中，由于柔性基底采用有机材料制作，容易受到水氧侵蚀，为了防止水氧侵蚀，芯片封装单元还包括图10所示的水氧隔绝层16，其中，水氧隔绝层16覆盖柔性基底11，引脚层设置在水氧隔绝层远离柔性基底的一侧；参考图10所示，柔性基底11中，未被第一引脚13覆盖的部分的厚度h2，小于被第一引脚覆盖的部分的厚度h1。水氧隔绝层的厚度不做限定，示例的，该厚度范围为100-500纳米，其材料可以包括二氧化硅或者氮化硅。
在一个或者多个实施例中，第一引脚包括至少一层导电层，导电层的材料包括金属或者金属合金。示例的，导电层的材料可以包括Mo、Al、 Ti、Cu等金属或合金。以铜为例，第一引脚可以采用厚铜板刻蚀或者电镀厚铜工艺形成，铜的厚度在8微米左右。由于湿刻的各项同性，尺寸偏差(CD Bias)很难做的较小，因此形成的引脚间距大于16微米。
可选的，在第一引脚包括一层导电层的情况下，若第一引脚采用易氧化的材料制作，例如：铜，为了避免铜氧化，第一引脚还包括防氧化层13，防氧化层覆盖导电层。该防氧化层可以采用化学镀Sn、Au等工艺，厚度范围为0.5um～2um；或者，还可以采用在第一引脚的表面覆盖ITO(Indium Tin Oxide，氧化铟锡)，来防止氧化。另外，防氧化层还有利于提高第一引脚所在区域的高度，在后续与面板绑定时保证足够的溢胶空间。
为了保护非绑定区，可选的，在芯片封装单元的非绑定区可以设置阻焊层(例如：绿油)，厚度范围为5-20微米。
可选的，在第一引脚包括多层导电层的情况下，第一引脚包括叠层设置在柔性基底上的第一导电层、第二导电层和第三导电层；其中，第一导电层沿垂直于柔性基底的方向的厚度、以及第三导电层沿垂直于柔性基底的方向的厚度分别小于第二导电层沿垂直于柔性基底的方向的厚度。
上述第一导电层和第三导电层的材料可以相同，或者不同。上述第二导电层可以采用铝等金属材料，第一导电层和第三导电层可以采用钼或者钛等金属材料，这样可以采用光刻工艺或者电镀等工艺形成更精细的布线，走线间距(pitch)能减小至16微米以下，甚至减小至几微米(例如：3.6微米或者5微米等)左右；而若采用铜制作，其走线间距(pitch)最小在16-18微米。多层叠层结构比铜单层结构，可以大幅减小布线空间，使得芯片封装单元能够提供更多的输出引脚，满足高分辨率显示产品和3D显示产品的需求。需要说明的是，如图9所示，走线间距是指走线(图9所示的走线17)的线宽W1与相邻走线之间的间距D1之和，引脚间距是指引脚(图9所示的第一引脚13)的宽度W与相邻引脚之间的间距D之和。
为了简化工艺，第一导电层和第三导电层的材料相同，第一导电层和第二导电层的材料不同。示例的，第二导电层的材料可以包括铝等，第一导电层和第三导电层的材料可以包括钼或者钛等。
在一些实施方式中，芯片封装单元还包括至少一个引线单元，引线单元设置在引脚层和柔性基底之间；引线单元包括：第一引线层和第一有机 层，第一有机层覆盖第一引线层。
第一引线层包括多条第一走线，第一走线包括的层结构和第一引脚包括的层结构相同；和/或，第一引线层包括多个第一走线引脚，第一走线引脚包括的层结构和第一引脚包括的层结构相同。
该芯片封装单元包括三种情况：第一种，第一引线层包括多条第一走线，此时，第一走线包括的层结构和第一引脚包括的层结构相同，示例的，第一走线也可以包括单层或者多层结构，具体可以参考前述第一引脚的层结构说明，这里不再赘述。第二种，第一引线层包括多个第一走线引脚，第一走线引脚包括的层结构和第一引脚包括的层结构相同，示例的，第一走线也可以包括单层或者多层结构，具体可以参考前述第一引脚的层结构说明，这里不再赘述。第三种，第一引线层包括多条第一走线和多个第一走线引脚，第一走线和第一走线引脚可以包括单层或者多层结构，具体可以参考前述第一引脚的层结构说明，这里不再赘述。
在一些实施方式中，芯片封装单元还包括至少一个引线单元，引线单元设置在引脚层和柔性基底之间；引线单元包括：第一引线层和第一有机层，第一有机层覆盖第一引线层。
第一引线层包括多条第一走线，第一走线包括叠层设置的多层导电层，第一引脚包括一层导电层；和/或，第一引线层包括多个第一走线引脚，第一走线引脚包括叠层设置的多层导电层，第一引脚包括一层导电层。
该芯片封装单元包括三种情况：第一种，第一引线层包括多条第一走线，第一走线包括叠层设置的多层导电层，第一引脚包括一层导电层，示例的，第一走线包括叠层设置的钛导电层、铝导电层和钛导电层，第一引脚包括铜导电层。第二种，第一引线层包括多个第一走线引脚，第一走线引脚包括叠层设置的多层导电层，第一引脚包括一层导电层，示例的，第一走线引脚包括叠层设置的钛导电层、铝导电层和钛导电层，第一引脚包括铜导电层。第三种，第一引线层包括多条第一走线和多个第一走线引脚，第一走线和第一走线引脚包括叠层设置的多层导电层，第一引脚包括一层导电层；示例的，第一走线和第一走线引脚包括叠层设置的钛导电层、铝导电层和钛导电层，第一引脚包括铜导电层。
由于受到目前的硅片制作、切割等因素限制，单颗IC(芯片)的横向 尺寸一般最大只能对应到32mm左右，难于引出更多的信号线。本申请中，显示装置包括至少一个芯片封装单元，可以根据产品的尺寸选择芯片封装单元的数量。在显示装置包括多个芯片封装单元的情况下，各芯片封装单元包括的芯片的设置方式不做限定，示例的，各芯片14可以如图19所示沿OA方向横向设置；或者，各芯片14可以如图20所示沿OB方向纵向设置；或者，部分横向设置，部分纵向设置；这里不做限定。
另外，芯片尺寸受限，芯片封装单元中多个引脚的设置方式同样会影响输出通道的数量。可选的，多个第一引脚呈阵列排布。示例的，多个第一引脚可以采用多排设置方式，例如：2排、3排、4排(图21-24所示)、或者5排等等。每一排中多个第一引脚的设置方向以及多排的设置方向均不做限定，示例的，多排可以如图21所示竖排，或者如图22所示斜排；各排中，各第一引脚可以如图21和图22所示的竖排，或者如图23和图24所示的斜排，进而形成八字排布。多个第一引脚的总长度可以为60mm、68mm、70mm或者127mm及以上，具体可以根据面板长度进行调整。
在一个或者多个实施例中，引脚层还包括：多个图8和图25所示的第二引脚15，多个第二引脚15设置在柔性基底的一侧，参考图25所示，显示装置还包括驱动板4，多个第二引脚15与驱动板4绑定连接。
这里驱动板可以是PCB(Printed Circuit Board，印制电路板)电路板，或者，还可以是FPC(Flexible Printed Circuit，柔性电路板)电路板，考虑到进一步减小边框，可以选择后者。
可选的，为了简化工艺，降低成本，第二引脚和第一引脚同层设置。第二引脚和第一引脚包括的层结构相同，示例的，第二引脚可以包括单层或者多层结构，具体可以参考前述第一引脚的层结构说明，这里不再赘述。
可选的，芯片封装单元还包括图8所示的芯片(IC)，第一引脚13和第二引脚15分别与芯片14电连接。由于与驱动板绑定连接的第二引脚的数量小于与显示面板绑定连接的第一引脚的数量，因此，多出的第二引脚还可以用作与显示面板绑定，从而进一步增大输出通道，同时节省空间。为了保护芯片，还可设置封装层，例如：树脂层(resin)。
在一个或者多个实施例中，显示面板还包括与非显示区相连的显示区；芯片封装结构中与显示面板绑定的一侧沿预设方向的长度、显示面板的绑 定部沿预设方向的长度、以及显示面板的显示区沿预设方向的长度三者相同。
相关技术中，采用PI基的COF的尺寸受限，显示面板与COF绑定时，显示面板为了匹配COF的尺寸，在非显示区需要设置如图26所示的扇形引线区(Fanout区)A2，将引线收拢在一定区域内，然后与绑定部相连。为了保证等电阻布线，引线区的引线采用几字形等方式设置，占用空间大，导致边框大。而本申请采用玻璃基形成芯片封装结构，尺寸不受限，参考图27所示，芯片封装结构中与显示面板绑定的一侧沿预设方向(图27所示的OA方向)的长度L2、显示面板的绑定部沿预设方向(图27所示的OA方向)的长度L1、以及显示面板的显示区A0沿预设方向(图27所示的OA方向)的长度L三者相同，这样，显示面板的引线100可以沿与预设方向垂直的方向(图27所示的OB方向)直接引出，与绑定部电连接，不再需要等电阻布线设置，从而最大程度地减小边框，便于形成超窄边框的显示产品。
本文中所称的“一个实施例”、“实施例”或者“一个或者多个实施例”意味着，结合实施例描述的特定特征、结构或者特性包括在本申请的至少一个实施例中。此外，请注意，这里“在一个实施例中”的词语例子不一定全指同一个实施例。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本申请的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (20)

  1. 一种显示装置的制备方法，其中，包括：
    形成芯片封装结构，其中，所述芯片封装结构包括至少一个芯片封装单元；所述芯片封装单元至少包括：柔性基底、设置在所述柔性基底一侧的刚性基底、以及设置在所述柔性基底远离所述刚性基底一侧的引脚层，所述引脚层至少包括多个第一引脚，多个所述第一引脚在所述柔性基底的正投影位于所述刚性基底在所述柔性基底的正投影以内；
    形成显示面板，其中，所述显示面板包括非显示区，所述非显示区包括刚性衬底和设置在所述刚性衬底上的绑定部；
    将所述芯片封装结构的所述第一引脚与所述显示面板的所述绑定部进行绑定连接。
  2. 根据权利要求1所述的制备方法，其中，在将所述芯片封装结构的所述第一引脚与所述显示面板的所述绑定部进行绑定连接之后，所述方法还包括：
    去除所述芯片封装单元的全部所述刚性基底。
  3. 根据权利要求1或2所述的显示装置，其中，所述刚性基底和所述刚性衬底的热膨胀系数相同。
  4. 一种显示装置，其中，所述显示装置采用权利要求1所述的制备方法形成，包括：芯片封装结构和显示面板；所述芯片封装结构包括至少一个芯片封装单元；所述芯片封装单元至少包括：柔性基底、设置在所述柔性基底一侧的刚性基底、以及设置在所述柔性基底远离所述刚性基底一侧的引脚层，所述引脚层至少包括多个第一引脚，多个所述第一引脚在所述柔性基底的正投影位于所述刚性基底在所述柔性基底的正投影以内；所述显示面板包括非显示区，所述非显示区包括刚性衬底和设置在所述刚性衬底上的绑定部；所述芯片封装结构的所述第一引脚与所述显示面板的所述绑定部绑定连接；
    或者，所述显示装置采用权利要求2所述的制备方法形成，包括：芯片封装结构和显示面板；所述芯片封装结构包括至少一个芯片封装单元；所述芯片封装单元包括：柔性基底、以及设置在所述柔性基底一侧的引脚层，所述引脚层至少包括多个第一引脚；所述显示面板包括非显示区，所述非显示区包括刚性衬底和设置在所述刚性衬底上的绑定部；所述芯片封装结构的所述第一引脚与所述显示面板的所述绑定部绑定连接。
  5. 根据权利要求4所述的显示装置，其中，所述第一引脚沿垂直于所述柔性基底的方向与所述柔性基底的距离，大于所述第一引脚的相邻部分沿垂直于所述柔性基底的方向与所述柔性基底的距离。
  6. 根据权利要求5所述的显示装置，其中，所述第一引脚沿垂直于所述柔性基底的方向与所述柔性基底的距离，与所述第一引脚的相邻部分沿垂直于所述柔性基底的方向与所述柔性基底的距离的差值的范围为2-8微米。
  7. 根据权利要求5所述的显示装置，其中，所述芯片封装单元还包括至少一个引线单元，所述引线单元设置在所述引脚层和所述柔性基底之间；所有所述引线单元形成的整体中，未被所述第一引脚覆盖的部分沿垂直于所述柔性基底的方向与所述柔性基底的距离，小于被所述第一引脚覆盖的部分沿垂直于所述柔性基底的方向与所述柔性基底的距离；所述柔性基底沿垂直于所述柔性基底的方向的厚度均一；
    所述引线单元包括：第一引线层和第一有机层，所述第一有机层覆盖所述第一引线层；所述第一引线层至少包括多条第一走线和/或多个第一走线引脚；所述第一走线和/或所述第一走线引脚，与对应的所述第一引脚电连接。
  8. 根据权利要求7所述的显示装置，其中，所有所述引线单元中，与所述第一引脚相接触的所述引线单元的所述第一有机层中，未被所述第一引脚覆盖的部分沿垂直于所述柔性基底的方向与所述柔性基底的距离，小于被所述第一引脚覆盖的部分沿垂直于所述柔性基底的方向与所述柔性基底的距离；
    其余所述引线单元沿垂直于所述柔性基底的方向的厚度均一。
  9. 根据权利要求5所述的显示装置，其中，所述芯片封装单元还包括水氧隔绝层，其中，所述水氧隔绝层覆盖所述柔性基底，所述引脚层设置在所述水氧隔绝层远离所述柔性基底的一侧；
    所述柔性基底中，未被所述第一引脚覆盖的部分的厚度，小于被所述第一引脚覆盖的部分的厚度。
  10. 根据权利要求4-9任一项所述的显示装置，其中，所述第一引脚包括至少一层导电层，所述导电层的材料包括金属或者金属合金。
  11. 根据权利要求10所述的显示装置，其中，在所述第一引脚包括一层所述导电层的情况下，所述第一引脚还包括防氧化层，所述防氧化层 覆盖所述导电层。
  12. 根据权利要求10所述的显示装置，其中，在所述第一引脚包括多层所述导电层的情况下，所述第一引脚包括叠层设置在所述柔性基底上的第一导电层、第二导电层和第三导电层；
    其中，所述第一导电层沿垂直于所述柔性基底的方向的厚度、以及所述第三导电层沿垂直于所述柔性基底的方向的厚度分别小于所述第二导电层沿垂直于所述柔性基底的方向的厚度。
  13. 根据权利要求12所述的显示装置，其中，所述第一导电层和所述第三导电层的材料相同，所述第一导电层和所述第二导电层的材料不同。
  14. 根据权利要求10所述的显示装置，其中，所述芯片封装单元还包括至少一个引线单元，所述引线单元设置在所述引脚层和所述柔性基底之间；所述引线单元包括：第一引线层和第一有机层，所述第一有机层覆盖所述第一引线层；
    所述第一引线层包括多条第一走线，所述第一走线包括的层结构和所述第一引脚包括的层结构相同；
    和/或，所述第一引线层包括多个第一走线引脚，所述第一走线引脚包括的层结构和所述第一引脚包括的层结构相同。
  15. 根据权利要求10所述的显示装置，其中，所述芯片封装单元还包括至少一个引线单元，所述引线单元设置在所述引脚层和所述柔性基底之间；所述引线单元包括：第一引线层和第一有机层，所述第一有机层覆盖所述第一引线层；
    所述第一引线层包括多条第一走线，所述第一走线包括叠层设置的多层导电层，所述第一引脚包括一层导电层；
    和/或，所述第一引线层包括多个第一走线引脚，所述第一走线引脚包括叠层设置的多层导电层，所述第一引脚包括一层导电层。
  16. 根据权利要求4所述的显示装置，其中，多个所述第一引脚呈阵列排布。
  17. 根据权利要求4所述的显示装置，其中，所述引脚层还包括：多个第二引脚，多个所述第二引脚设置在所述柔性基底的一侧，所述显示装置还包括驱动板，多个所述第二引脚与所述驱动板绑定连接。
  18. 根据权利要求17所述的显示装置，其中，所述第二引脚和所述第一引脚同层设置。
  19. 根据权利要求18所述的显示装置，其中，所述芯片封装单元还包括芯片，所述第一引脚和所述第二引脚分别与所述芯片电连接。
  20. 根据权利要求4所述的显示装置，其中，所述显示面板还包括与所述非显示区相连的显示区；
    所述芯片封装结构中与所述显示面板绑定的一侧沿预设方向的长度、所述显示面板的所述绑定部沿所述预设方向的长度、以及所述显示面板的所述显示区沿所述预设方向的长度三者相同。
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