1^23378 九、發明說明： 【發明所屬之技術領域】 本發明有關一種顯示基板’其中接合墊部分具有相對 較寬之接合_距，特別是有關一 種液晶顯示袭置。 【先前技術】 、.°、'"、衣置為目如日趨流行的一種顯示裝置，其中 液aa 員示m更因為具有外型輕薄、耗電量少以及無輻射污 木等特性，已被廣泛應用在個人桌上型電腦螢幕以及筆記 型電腦、個人數位助理(P D A)等攜帶式資訊產品上，甚至已 有逐漸取代陰極射線管(CathGde Ray 丁·，crt)監視器及 傳統電視的趨勢。 一般而言’液晶顯示器之驅動電路係利用一連接物做 為媒”笔ί生連接至一印刷電路板(printed circuit board)以及 液晶顯不為之下玻璃基板，以將控制訊號從印刷電路板傳 送至各驅動積體電路晶片，再將經過處理之訊號輸入下玻 璃基板上的各個像素。在業界之發展之下，連接物及其電 性接合等相關技術有例如複數個封裝有驅動積體電路晶片 之帶狀载座封裝體技術(tape carrier package，TCP)、具有晶 粒玻璃接合技術(chip on glass, COG)、晶粒薄膜接合技術 (chip on film, COF)、可撓式印刷電路薄板(flexible printed circuit film, FPC)技術、線覆陣列基板（wiring on array, WOA) 1323378 技術等等。 例如，第1圖所示為習知之WOA型液晶顯示器10的 示意圖。習知之WOA液晶顯示器10包含有一液晶顯示面 板12、複數個源極TCP 14分別電連接於液晶顯示面板12 的一側邊與一源極 PCB(printing circuit board, PCB) 16、複數 個閘極TCP 18分別電連接於液晶顯示面板12的另一側 邊、複數個源極驅動積體電路晶片（driver 1C) 20分別設於 一源極TCP 14上，以及複數個閘極驅動積體電路晶片22 分別設於一閘極TCP 18。此外，液晶顯示面板12包含有 一用來設置各訊號線與薄膜電晶體之下基板24、一用來設 置彩色濾光片之上基板26以及一設於下基板24與上基板 26間之液晶材料層（未顯示）。此外，液晶顯示面板12另包 含有一影像顯示區（picture display area) 28，而在影像顯示 區28中，則設有複數條交錯排列的掃瞄線30以及資料線 32分別電連接於各閘極驅動積體電路晶片22以及各源極 驅動積體電路晶片20。 又如第1圖所示，源極TCP 14包含有複數個源極輸入 接合墊（input pad) 34以及複數個源極輸出接合墊（output pad) 36，用來將源極PCB 16電連接於資料線32。而且， 在最靠近閘極TCP 18之源極PCB 16中另包含有一組閘極 驅動訊號傳輸線37，用來電連接以W0A方式設於下基板 6 1323378 24表面之WOA閘極驅動訊號匯流排38。而每一閘極TCP 18中均設有一組閘極驅動訊號傳輸線40以及複數個閘極 輸出接合墊42，均電連接於各閘極驅動積體電路晶片22。 可知一般利用接合墊以將不同導線之間電連接。 然而，對於接合墊結構而言，習知之接合墊之排列一 般如第2圖所示。由上基板26與下基板24之間延伸出來 之導線15,在下基板24之周邊區域表面上之接合墊部分， 具有接合墊17，各接合墊為長條狀，並呈平行排列，以供 TCP 14電連接。各接合墊17之間之排列關係又可如第3 圖所示，各接合墊17為長條狀，且包括導電層44，彼此 呈平行排列，接合墊17.包括有複數個通孔46以連接導體 層，因此，複數個接合墊具有一節距T，接合塾與接合墊 之間距為a，通孔46之寬度為d，通孔46之一邊緣與覆蓋 於其上之接合墊之一邊緣距離為b。一般而言，此種結構， 基於現行製程寬裕度(process window)及製程解析度，在T 為55//m，w為8至14#m之情況下，接合墊之間之距離 a至多為47 μ m，因此，往往因環境或製程中之顆粒或阻劑 的殘餘物掉落接合墊之間，引起短路，影響良率。 因此，對於接合墊*部分之構形（configuration)，仍有改 善之必要，以獲得更佳之製程良率。 7 1323378 【發明内容】 因此，本發明之目的係提供一種接合墊結構及一種包 括此種接合墊結構之顯示基板及液晶顯示裝置，此種接合 墊結構具有特殊之接合墊構形，在不變更接合墊與接合墊 之節距，且不變更製程解析度之條件下，能夠增加接合墊 彼此之間之間距，因此增加了製程寬裕度，亦能夠避免大 部分顆粒或阻劑殘餘物在接合墊上.造成短路之情形。 為達成上述目的，本發明之接合墊結構包括至少二條 導線平行位於顯示基板上，並各具有一接合墊區。導線上 覆蓋保護層，保護層具有複數個通孔區，各通孔區具有至 少一個通孔以部分曝露出導線之接合墊區。保護層上有複 數個導電層，係位於相對於導線之接合墊區之處，並且可 經由保護層具有之通孔與導線電相連。因此，導電層具有 與通孔區位置對應之第一部分及與非通孔區位置對應之第 二部分，任兩相鄰近之導電層之第一部分相對應第二部 分，而交替排列，並且各導電層之寬度在第二部分之處小 於在第一部分之處。 依據本發明提供一顯示基板包括至少一如上述之接合 垫結構做為接合墊部分，以接受來自電路基板之電子訊號。 依據本發明提供一液晶顯示裝置包括一液晶顯示面板 8 1323378 及一電路基板。液晶顯示面板包括形成於基板上之複數個 畫素部分及如上述之接合墊部分。電路基板則具有一輸出 埠與接合墊部分或液晶顯示面板電相連以將電訊號施加於 液晶顯不面板。 於本發明之接合整結構、顯示基板及液晶顯示裝置 中，由於使接合墊區之通孔區交錯排列，因此做為接合墊 的導電層能被區分為第一部分與第二部分，互相對應而交 替排列，將導電層之第二部分之處之寬度縮減，二鄰近之 導電層相隔之距離即可增加。亦即，在不變更節距之情形 及增加製程解析度之情形下，可增加二相鄰近之接合墊之 間距’達到增加液晶顯不裝置（LCD)或液晶顯不模組（LCM) 之製程寬裕度及降低顆粒或阻劑殘餘物之影響之效果，且 可適用於業已被廣泛使用之各種技術例如COG、COF、 TCP、FPC、WOA等技術及其商品化產品。 【實施方式】 參閱第4至7圖所示說明本發明。本發明之接合墊結 構50，包括如第4圖所示之至少二條導線54平行位於一 基板52上，導線54可包括一金屬層，例如用來製備掃描 線的第一金屬層（Metal 1)或用來製備訊號線的第二金屬層 (Metal 2)，其具有一接合墊區55,做為與其他元件例如TCP 之導線接合之接合墊位置。一般在導線54上會覆蓋一層保 1323378 護層56。保護層可經由例如電漿化學氣相沉積（plasma CVD) 方法所形成。保護層可以整片覆蓋全部導線之方式，或是 以分開的複數層分別覆蓋住導線。保護層56具有複數個通 . 孔區57，通孔區57係對應於接合墊之位置，是形成通孔 . 58之區域，或可形成複數個通孔。使通孔58貫穿保護層 56，以曝露出接合墊區55.之導線54。一通孔區具有複數 個通孔時，可使各通孔在通孔區内做適當之排列。通孔之 φ 目的是為了使下層之導線能夠增加與後來沉積於保護層上 的導電層增加接觸面積。而各通孔區57係以預定位置錯開 排列，如第4圖所示，以達本發明之特徵與功效。各通孔 可經由例如微影及蝕刻之製程而形成。. 請參閱第5圖，保護層上有複數個導電層59，例如氧 化銦錫（indium tin oxide, ITO)層，係位於相對應於導線54 之接合墊區55之處，並且可經由保護層56具有之通孔58 * 與導線54電相連，即通孔58中可填充與導電層相同之導 電材料，而使導電層59與導線54經由通孔58而電相連。 因此，導電層59具有與通孔區57位置對應之第一部分61 及與非通孔區位置對應之第二部分62，任兩相鄰近之導電 層之第一部分相對應第二部分，二者交替排列，例如第一 部分61與第二部分62以交替排列之方式配置。並且各導 電層59之寬度在第二部分62之處小於在第一部分61之 處，因此同一導電層會具有凹凸之形狀。其中，導電層之 1323378 較佳實施例係使第一部分61之整個面積蓋過通孔區57之 面積，亦即，使通孔區57之周邊在第一部分61之周邊範 圍内。 又參閱第6圖，清楚顯示本發明之接合墊結構之一具 體實施例中，各接合墊彼此間之幾何形狀與位置之示意 圖。接合墊具有節距T，通孔區寬度d，各導電層59之寬 度在第一部分61之處為w+2b，在第二部分62之處之寬度 為w，因此，在導電層形狀為具有凹凸之情形下，可使相 鄰近的二導電層距離保持為a+b，較習知技術之距離a多 出b之距離。例如，以習知之技術之製程解析度可製得T 為50/zm (例如對於COG技術之習知產品）或55/zm (例如 對於COF技術之習知產品），w為8至14//m，b為2至5 // m。因此例如在w為8 // m，b為2時，可得a+b為44 或49 // m。較習知技術之接合整距離多2 // m。 又參閱第7圖，係顯示在第6圖中A-A’截面之另一實 施例示意圖。此係通常為液晶顯示裝置資料端之接合墊， 在金屬導線54與玻璃基板52之間進一步具有閘極絕緣層 53。閘極絕緣層可包括例如SiNx。保護層56包括SiNx2 材質。ITO導電層59覆蓋在保護層56上並填充通孔58。 請參閱第8圖，顯示在通孔區具有複數個通孔之情形。通 孔個數及排列依所需而定。 1323378 請參閱第9圖，係顯示在第6圖中A-A’截面之又一實 施例示意圖。此係通常為液晶顯示裝置掃瞄端之接合墊， . 在金屬導線54與SiNx保護層56之間進一步具有閘極絕緣 層51。閘極絕緣層可包括例如SiNx。閘極絕緣層51與保 護層56在穿孔區一起形成貫穿的通孔58。ITO導電層59 覆蓋在保護層56上並填充通孔58。 第10圖顯示依據本發明之接合墊結構之另一具體實 施例，在具有面積較大與較小之通孔區之情形，接合墊部 分之幾何形狀與徘列之示意圖。導電層59具有第一部分 61與第二部分62，第一部分與通孔區57中面積較大的通 孔區57位置對應，第二部务與通孔區中面積較小的通孔區 57’位置對應，其中，任兩相鄰近之導電層59之第一部分 61相對應第二部分62配置，及各導電層59之寬度在第二 ® 部分62之處小於在第一部分61之處。各通孔區具有之通 孔58個數與排列可依所需而定。例如，第10圖中，第一 部分所對應之通孔區具有二並列之通孔，第二部分所對應 之通孔區具有一個通孔。因此，可知在第一部分與第二部 分對應之結構可具有種種變異，但均.不悖於本發明之精 神，而應在本發明之範疇中。 因此，本發明之顯示基板即使用上述本發明之接合墊 1323378 結構，做為至少一接合墊部分，以接受來自電路基板之電 訊號。可藉由例如COG、COF、TCP、FPC、WOA等技， 使電路基板與接合墊接合。 本發明之液晶顯示裝置包括一液晶顯示面板及一電路 基板。液晶顯示面板即包括形成於基板上之複數個畫素部 分及如上述之接合墊部分。電路基板則具有一輸出埠與接 φ合墊部分或液晶顯示面板電相連以將電訊號施加於液晶顯 示面板。使用上述本發明之接合墊結構，使位於液晶顯示 面板之下基板之周緣位置，可藉由例如晶粒玻璃接合技 術、晶粒軟膜接合技術、可撓性基板接合技術、或捲帶式 封裝體技術使電路基板與接合墊接合，以接受來自電路基 板之電訊號。或是在外引腳接合結構（〇uter lead b〇nding region，〇LB regi〇n)之處做為電接合之用。由於在本發明 鲁中，導電層所形成之接合墊間距增大，因此可在不改變製 耘解析度，而能在寬裕之製程寬裕度下，就可達降低顆粒 或光阻殘餘物造成短路之功效。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 Will圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 WOA型液晶顯示器的示意圖。 第1圖為習知— 1323378 第2圖為習知之接合墊部分之示意圖。 第3圖為習知之接合墊部分之幾何排列之示意圖。 第4圖為依據本發明之一具體實施例之接合墊結構之 一部分之配置之示意圖。 第5圖為依據本發明之一具體實施例之接合墊結構之 配置之示意圖。 第6圖為依據本發明之一具體實施例之接合墊部分之 幾何排列之示意圖。 第7圖為依據本發明之依據本發明之一具體實施例之 資料端接合墊部分之結構之截面示意圖。 第8圖為依據本發明之依據本發明之另一具體實施例 之資料端接合墊部分之結構之截面示意圖。 第9圖為依據本發明之依據本發明之一具體實施例之 掃瞄端接合墊部分之結構之截面示意圖。 •第10圖為依據本發明之另一具體實施例之接合墊部 分之幾何排列之示意圖。 【主要元件符號說明】 10:WOA型液晶顯示器 12 ·液晶顯不面板1^23378 IX. Description of the Invention: [Technical Field] The present invention relates to a display substrate in which a bonding pad portion has a relatively wide bonding distance, particularly relating to a liquid crystal display. [Prior Art], .°, '", clothing is a display device that is becoming more and more popular. Among them, the liquid aa member shows that m is characterized by its slimness, low power consumption and no radiation. It is widely used in personal desktop computer screens and portable information products such as notebook computers and personal digital assistants (PDAs), and has even gradually replaced cathode ray tubes (CathGde Ray D., crt) monitors and traditional TVs. trend. Generally speaking, the driving circuit of the liquid crystal display uses a connector as a medium, and the printer is connected to a printed circuit board and a liquid crystal display substrate to control signals from the printed circuit board. It is sent to each driver integrated circuit chip, and then the processed signal is input to each pixel on the lower glass substrate. Under the development of the industry, the related technologies such as the connector and its electrical bonding have, for example, a plurality of packages with driving integrated bodies. Tape carrier package (TCP) for circuit chips, chip on glass (COG), chip on film (COF), flexible printed circuit A flexible printed circuit film (FPC) technology, a wiring on array (WOA) 1323378 technology, etc. For example, Fig. 1 is a schematic view of a conventional WOA type liquid crystal display 10. A conventional WOA liquid crystal display 10 includes a liquid crystal display panel 12, and a plurality of source TCPs 14 are electrically connected to one side of the liquid crystal display panel 12 and a source PCB (printing circuit board, respectively). PCB) 16. A plurality of gates TCP 18 are electrically connected to the other side of the liquid crystal display panel 12, and a plurality of source driver integrated circuit chips (driver 1C) 20 are respectively disposed on a source TCP 14 and a plurality of The gate driving integrated circuit wafers 22 are respectively disposed on a gate TCP 18. In addition, the liquid crystal display panel 12 includes a substrate 24 for setting the signal lines and the thin film transistor, and a color filter for setting the color filter. The upper substrate 26 and a liquid crystal material layer (not shown) disposed between the lower substrate 24 and the upper substrate 26. Further, the liquid crystal display panel 12 further includes a picture display area 28, and in the image display area 28. Then, a plurality of scanning lines 30 and data lines 32 which are alternately arranged are electrically connected to the gate driving integrated circuit wafers 22 and the respective source driving integrated circuit wafers 20. Further, as shown in FIG. The pole TCP 14 includes a plurality of source input pads 34 and a plurality of source output pads 36 for electrically connecting the source PCB 16 to the data line 32. Moreover, in the closest Source of the gate TCP 18 The CB 16 further includes a set of gate drive signal transmission lines 37 for electrically connecting the WOA gate drive signal bus bars 38 disposed on the surface of the lower substrate 6 1323378 24 in the W0A manner, and each gate has a set of TCP 18 The gate driving signal transmission line 40 and the plurality of gate output bonding pads 42 are electrically connected to the gate driving integrated circuit wafers 22. It is known that bond pads are typically utilized to electrically connect different wires. However, for the bond pad structure, the arrangement of the conventional bond pads is generally as shown in Fig. 2. The wire 15 extending from between the upper substrate 26 and the lower substrate 24 has a bonding pad 17 on the surface of the peripheral portion of the lower substrate 24, and the bonding pads are elongated and arranged in parallel for TCP. 14 electrical connections. The arrangement relationship between the bonding pads 17 can be as shown in FIG. 3, each bonding pad 17 is elongated, and includes a conductive layer 44 arranged in parallel with each other. The bonding pad 17 includes a plurality of through holes 46. Connecting the conductor layers, therefore, the plurality of bonding pads have a pitch T, the spacing between the bonding pads and the bonding pads is a, the width of the through holes 46 is d, and the edge of one of the through holes 46 and the edge of one of the bonding pads covered thereon The distance is b. In general, this structure is based on the current process window and process resolution. When T is 55//m and w is 8 to 14#m, the distance a between the pads is at most 47 μm, therefore, often due to environmental or process residues or resist residues falling between the bond pads, causing a short circuit, affecting yield. Therefore, for the configuration of the bond pad portion, there is still a need for improvement to achieve better process yield. 7 1323378 SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a bonding pad structure and a display substrate and a liquid crystal display device including the same, which have a special bonding pad configuration and are not changed. The pitch of the bonding pad and the bonding pad can increase the distance between the bonding pads without changing the process resolution, thereby increasing the process margin and avoiding most of the particles or resist residues on the bonding pads. The situation that caused a short circuit. To achieve the above object, the bond pad structure of the present invention comprises at least two wires in parallel on the display substrate and each having a bond pad region. The wire is covered with a protective layer having a plurality of via regions, each via region having at least one via hole to partially expose the bonding pad region of the wire. The protective layer has a plurality of conductive layers located at the bond pad regions of the wires and electrically connected to the wires via the vias of the protective layer. Therefore, the conductive layer has a first portion corresponding to the position of the via region and a second portion corresponding to the position of the non-via region, and the first portion of the conductive layer adjacent to the two phases corresponds to the second portion, alternately arranged, and each conductive The width of the layer is smaller in the second part than in the first part. According to the present invention, a display substrate includes at least one bond pad structure as described above as a bond pad portion for receiving electronic signals from a circuit substrate. According to the present invention, a liquid crystal display device includes a liquid crystal display panel 8 1323378 and a circuit substrate. The liquid crystal display panel includes a plurality of pixel portions formed on the substrate and a bonding pad portion as described above. The circuit substrate has an output 电 electrically connected to the pad portion or the liquid crystal display panel to apply an electrical signal to the liquid crystal display panel. In the bonded structure, the display substrate, and the liquid crystal display device of the present invention, since the via regions of the bonding pad region are staggered, the conductive layer as the bonding pad can be divided into the first portion and the second portion, corresponding to each other. Alternatingly, the width of the second portion of the conductive layer is reduced, and the distance between two adjacent conductive layers is increased. That is, in the case of not changing the pitch and increasing the resolution of the process, the distance between the adjacent pads of the two phases can be increased to achieve the process of increasing the liquid crystal display device (LCD) or the liquid crystal display module (LCM). The effect of wide margin and the effect of reducing the influence of particles or resist residues, and is applicable to various technologies that have been widely used, such as COG, COF, TCP, FPC, WOA, and the like, and commercial products thereof. [Embodiment] The present invention will be described with reference to Figs. 4 to 7. The bonding pad structure 50 of the present invention comprises at least two wires 54 as shown in FIG. 4 in parallel on a substrate 52. The wires 54 may comprise a metal layer, such as a first metal layer (Metal 1) for preparing a scanning line. Or a second metal layer (Metal 2) for preparing a signal line having a bond pad region 55 as a bond pad location for bonding with other components such as TCP wires. Typically, the conductor 54 is covered with a layer 1323378. The protective layer can be formed by, for example, a plasma chemical vapor deposition (plasma CVD) method. The protective layer may cover all of the wires in a single piece, or cover the wires separately in separate layers. The protective layer 56 has a plurality of via regions 57, the via regions 57 corresponding to the locations of the bond pads, the regions forming the vias 58 or a plurality of vias. The through hole 58 is passed through the protective layer 56 to expose the wire 54 of the bonding pad region 55. When a through hole region has a plurality of through holes, the through holes can be appropriately arranged in the through hole region. The purpose of the via φ is to enable the underlying conductor to increase the contact area with the conductive layer deposited later on the protective layer. The through-hole areas 57 are arranged in a staggered manner at predetermined positions, as shown in Fig. 4, to achieve the features and effects of the present invention. Each of the via holes can be formed by a process such as lithography and etching. Referring to FIG. 5, the protective layer has a plurality of conductive layers 59, such as an indium tin oxide (ITO) layer, located at a bonding pad region 55 corresponding to the wires 54, and may be via a protective layer. The through hole 58* having a through hole 58 is electrically connected to the wire 54, that is, the through hole 58 can be filled with the same conductive material as the conductive layer, and the conductive layer 59 and the wire 54 are electrically connected via the through hole 58. Therefore, the conductive layer 59 has a first portion 61 corresponding to the position of the via region 57 and a second portion 62 corresponding to the position of the non-via region, and the first portion of the conductive layer adjacent to the two phases corresponds to the second portion, and the two are alternated The arrangement, for example, the first portion 61 and the second portion 62 are arranged in an alternating arrangement. Also, the width of each of the conductive layers 59 is smaller at the second portion 62 than at the first portion 61, so that the same conductive layer may have a concavo-convex shape. Wherein the preferred embodiment of the conductive layer 1323378 is such that the entire area of the first portion 61 covers the area of the via portion 57, i.e., the periphery of the via portion 57 is within the perimeter of the first portion 61. Referring also to Fig. 6, there is clearly shown a schematic view of the geometry and position of the bond pads in a particular embodiment of the bond pad structure of the present invention. The bonding pad has a pitch T, a width d of the via region, and the width of each conductive layer 59 is w+2b at the first portion 61 and w at the second portion 62. Therefore, the shape of the conductive layer is In the case of the unevenness, the distance between the adjacent two conductive layers can be kept a+b, which is more than the distance b from the prior art. For example, a process resolution of the prior art can produce a T of 50/zm (e.g., a conventional product for COG technology) or 55/zm (e.g., a conventional product for COF technology), w is 8 to 14// m, b is 2 to 5 // m. So for example, when w is 8 // m and b is 2, a+b is obtained as 44 or 49 // m. More than 2 // m of the joint distance of the prior art. Referring also to Fig. 7, there is shown a schematic view of another embodiment of the A-A' section in Fig. 6. This is usually a bonding pad of the data terminal of the liquid crystal display device, and further has a gate insulating layer 53 between the metal wire 54 and the glass substrate 52. The gate insulating layer may include, for example, SiNx. The protective layer 56 is made of a SiNx2 material. An ITO conductive layer 59 is overlaid on the protective layer 56 and fills the vias 58. Please refer to Fig. 8 for the case where there are a plurality of through holes in the through hole area. The number of holes and the arrangement are as needed. 1323378 Referring to Fig. 9, there is shown a schematic view of still another embodiment of the A-A' section in Fig. 6. This is usually the bonding pad of the scanning end of the liquid crystal display device, and further has a gate insulating layer 51 between the metal wire 54 and the SiNx protective layer 56. The gate insulating layer may include, for example, SiNx. The gate insulating layer 51 and the protective layer 56 form a through via 58 therethrough in the perforated area. An ITO conductive layer 59 is overlaid on the protective layer 56 and fills the vias 58. Figure 10 is a schematic illustration of the geometry and alignment of the mat portion in the case of a larger and smaller through-hole region in accordance with another embodiment of the bond pad structure of the present invention. The conductive layer 59 has a first portion 61 and a second portion 62. The first portion corresponds to the area of the through hole portion 57 having a larger area in the through hole portion 57, and the second portion and the through hole portion 57' having a smaller area in the through hole portion. Corresponding to the position, wherein the first portion 61 of the conductive layer 59 adjacent to the two phases is disposed corresponding to the second portion 62, and the width of each conductive layer 59 is smaller at the second portion 62 than at the first portion 61. The number and arrangement of the vias 58 in each via region can be as desired. For example, in Fig. 10, the through-hole region corresponding to the first portion has two parallel via holes, and the via portion corresponding to the second portion has a through hole. Therefore, it is understood that the structures corresponding to the first portion and the second portion may have various variations, but they are not inconsistent with the spirit of the present invention and should be within the scope of the present invention. Therefore, the display substrate of the present invention uses the above-described bonding pad 1323378 structure of the present invention as at least one bonding pad portion to receive the electrical signal from the circuit substrate. The circuit substrate and the bonding pad can be bonded by techniques such as COG, COF, TCP, FPC, WOA, and the like. The liquid crystal display device of the present invention comprises a liquid crystal display panel and a circuit substrate. The liquid crystal display panel includes a plurality of pixel portions formed on the substrate and a bonding pad portion as described above. The circuit substrate has an output port and a pad portion or a liquid crystal display panel electrically connected to apply a signal to the liquid crystal display panel. By using the bonding pad structure of the present invention described above, the peripheral position of the substrate under the liquid crystal display panel can be obtained by, for example, a die glass bonding technique, a die bonding technique, a flexible substrate bonding technique, or a tape and tape package. Techniques engage the circuit substrate with the bond pads to accept electrical signals from the circuit substrate. Or in the external pin joint structure (〇 uter lead b〇nding region, 〇 LB regi〇n) for electrical bonding. In the invention, the spacing of the bonding pads formed by the conductive layer is increased, so that the shortness of the process can be achieved without changing the resolution of the system, and the defect of the particles or the photoresist residue can be shortened under a wide process margin. The effect. The above is only the preferred embodiment of the present invention, and all changes and modifications made by the application of the present invention should be within the scope of the present invention. [Simple diagram of the diagram] A schematic diagram of a WOA type liquid crystal display. Figure 1 is a conventional view - 1323378. Figure 2 is a schematic view of a conventional joint pad portion. Figure 3 is a schematic illustration of the geometric arrangement of the known bond pad portions. Figure 4 is a schematic illustration of the configuration of a portion of a bond pad structure in accordance with an embodiment of the present invention. Figure 5 is a schematic illustration of the configuration of a bond pad structure in accordance with an embodiment of the present invention. Figure 6 is a schematic illustration of the geometric arrangement of the bond pad portions in accordance with an embodiment of the present invention. Figure 7 is a schematic cross-sectional view showing the structure of a portion of a mat for a data terminal according to an embodiment of the present invention. Figure 8 is a cross-sectional view showing the structure of a portion of a material end pad according to another embodiment of the present invention. Figure 9 is a cross-sectional view showing the structure of a portion of a scanning end joint pad according to an embodiment of the present invention. Figure 10 is a schematic illustration of the geometric arrangement of the mat portions in accordance with another embodiment of the present invention. [Main component symbol description] 10: WOA type liquid crystal display 12 · LCD display panel
14 :源極TCP 15 :導線14: Source TCP 15: Wire
16 :源極PCB 1323378 17 :接合墊16: Source PCB 1323378 17 : Bond pad
18 .問極T C P 20:源極驅動積體電路晶片 . 2 2 :閘極驅動積體電路晶片 24 :下基板 26 :上基板 28 :影像顯示區 鲁 3〇 :掃瞄線 32 :資料線 34 :輸入接合墊 36 :輸出接合墊 37:閘極驅動訊號傳輸線 38:閘極驅動訊號匯流排 40:閘極驅動訊號傳輸線 42 :閘極輸出接合墊 鲁44 :導電層 46 :通孔 51 :閘極絕緣層 52 :基板 53 :閘極絕緣層 54 :導線 55 :接合墊區 56 :保護層 1323378 57 :通孔區 5 7 ’ ·通孔區 58 :通孔 58’ ：通孔 . 59 :導電層 61 :第一部分 62 :第二部分 φ T :節距 w:第一部分之寬度 a :距離 b :距離 d:通孔之寬度18. Ask the pole TCP 20: source drive integrated circuit chip. 2 2: gate drive integrated circuit wafer 24: lower substrate 26: upper substrate 28: image display area Lu 3: scan line 32: data line 34 : Input bond pad 36: Output bond pad 37: Gate drive signal transmission line 38: Gate drive signal bus 40: Gate drive signal transmission line 42: Gate output bond pad Lu 44: Conductive layer 46: Through hole 51: Gate Pole insulating layer 52: Substrate 53: Gate insulating layer 54: Conductor 55: Bond pad region 56: Protective layer 1323378 57: Through hole region 5 7 '. Through hole region 58: Through hole 58': Through hole. 59: Conductive Layer 61: first portion 62: second portion φ T : pitch w: width of the first portion a: distance b: distance d: width of the through hole