WO2022227085A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2022227085A1
WO2022227085A1 PCT/CN2021/091747 CN2021091747W WO2022227085A1 WO 2022227085 A1 WO2022227085 A1 WO 2022227085A1 CN 2021091747 W CN2021091747 W CN 2021091747W WO 2022227085 A1 WO2022227085 A1 WO 2022227085A1
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Prior art keywords
light
emitting
electrically connected
transistor
scan
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PCT/CN2021/091747
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English (en)
French (fr)
Inventor
陈文波
张跳梅
易宏
燕青青
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/091747 priority Critical patent/WO2022227085A1/zh
Priority to US17/637,447 priority patent/US11900875B2/en
Priority to CN202180001058.6A priority patent/CN114730541B/zh
Publication of WO2022227085A1 publication Critical patent/WO2022227085A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
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    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
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    • G09G2300/0408—Integration of the drivers onto the display substrate
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    • G09G2300/0421—Structural details of the set of electrodes
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    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the display field, and in particular, relate to a display substrate and a display device.
  • Organic Light Emitting Diode is one of the hotspots in the field of display research today. Compared with Liquid Crystal Display (LCD), organic light-emitting diode OLED has the advantages of low energy consumption, low production cost, self-illumination, wide viewing angle and fast response speed, and has been widely used in mobile phones, tablet computers and digital cameras. displayed in the field.
  • LCD Liquid Crystal Display
  • the present disclosure provides a display substrate, comprising: a display area and a non-display area, the display substrate includes: a base substrate and a substrate sequentially stacked on the base substrate and located in the display area A driving structure layer and a light emitting structure layer, the display substrate further comprises: M rows of scanning signal lines and M rows of light emitting signal lines; the light emitting structure layer comprises: M rows and N columns of light emitting structures, the driving structure layer comprises: along the columns A pixel circuit array and a driving circuit array extending in a direction; the pixel circuit array and the driving circuit array are sequentially arranged along the row direction;
  • the pixel circuit array includes: M rows and N columns of pixel circuits, the pixel circuits are in one-to-one correspondence with the light-emitting structures, and are electrically connected to the corresponding light-emitting structures, and the pixel circuits in the i-th row are connected with the scan signal lines in the i-th row and the light-emitting signals in the i-th row. Wire connection, 1 ⁇ i ⁇ M;
  • the drive circuit array includes: at least one scan drive circuit and at least one light emitting drive circuit, the scan drive circuit is configured to provide drive signals to the scan signal lines, and the light emitting drive circuit is configured to provide the light emitting signal lines drive signal.
  • the driving structure layer further includes: a blank circuit array; the blank circuit array is provided between the pixel circuit array and the driving circuit array;
  • the blank circuit array includes: a plurality of blank circuits, and the blank circuits are electrically connected with the scanning signal lines and the light-emitting signal lines.
  • the display area includes: at least one end of an arc-shaped display boundary, the display area includes: a first boundary and a second boundary arranged oppositely and a third boundary and a fourth boundary arranged oppositely; the length of the first boundary is greater than the length of the third boundary;
  • the first border and the second border extend along the column direction and are non-linear structures, the arc display border is located in the first border and the second border, the third border and all The fourth boundary extends along the row direction and is a linear structure;
  • At least part of the pixel circuits close to the arc-shaped display boundary are arranged in an arc shape.
  • the pixel circuit array includes: a second pixel circuit array, a first pixel circuit array, and a third pixel circuit array arranged in sequence along the row direction;
  • the driving circuit array includes: along the row direction Arranged first drive circuit arrays and second drive circuit arrays;
  • the first driving circuit array is located between the first pixel circuit array and the second pixel circuit array, and the second driving circuit array is located between the first pixel circuit array and the third pixel circuit array. between;
  • the plurality of driving circuits in the first driving circuit array and the second driving circuit array are arranged in a straight line.
  • the blank circuit array when the driving structure layer further includes a blank circuit array, includes: a first blank circuit array, a second blank circuit array, a third blank circuit array, and a fourth blank circuit array ;
  • the first blank circuit array is located between the second pixel circuit array and the first driving circuit array, and the second blank circuit array is located between the first driving circuit array and the first pixel circuit array.
  • the third blank circuit array is located between the first pixel circuit array and the second driving circuit array, and the fourth blank circuit array is located between the second driving circuit array and the third pixel circuit array between;
  • the plurality of blank circuits of the first blank circuit array, the second blank circuit array, the third blank circuit array and the fourth blank circuit array are arranged in a straight line.
  • the drive circuit array includes: a first drive circuit array and a second drive circuit array sequentially arranged in a row direction;
  • the first driving circuit array is arranged on the side of the pixel circuit array close to the first boundary of the display area, and the second driving circuit array is arranged at the second boundary of the pixel circuit array adjacent to the display area side;
  • At least part of the driving circuits in the first driving circuit array close to the arc-shaped display boundary are arranged in an arc shape; at least part of the driving circuits in the second driving circuit array close to the arc-shaped display boundary are arranged in an arc shape.
  • the blank circuit array when the driving structure layer further includes a blank circuit array, includes: a first blank circuit array and a second blank circuit array;
  • the first blank circuit array is located between the first driving circuit array and the pixel circuit array, and the second blank circuit array is located between the pixel circuit array and the second driving circuit array;
  • At least part of the blank circuits in the first blank circuit array close to the arc-shaped display boundary are arranged in an arc shape; at least part of the blank circuits in the second blank circuit array close to the arc-shaped display boundary are arranged in an arc shape.
  • both the first driving circuit array and the second driving circuit array include: scanning driving circuits and light-emitting driving circuits; the scanning driving circuits and light-emitting driving circuits located in the same driving circuit array are arranged in a row direction cloth;
  • the first drive circuit array includes: a scan drive circuit
  • the second drive circuit array includes: a light-emitting drive circuit
  • the pixel circuit array includes: a first pixel circuit array and a second pixel circuit array arranged in sequence along a row direction;
  • the driving circuit array includes: a first pixel circuit array arranged in sequence along the row direction a drive circuit array, a second drive circuit array, and a third drive circuit array;
  • the first pixel circuit array is located between the first driving circuit array and the second driving circuit array, and the second pixel circuit array is located between the second driving circuit array and the third driving circuit array;
  • At least part of the drive circuits in the first drive circuit array close to the arc-shaped display boundary are arranged in an arc shape; at least part of the drive circuits in the third drive circuit array close to the arc-shaped display boundary are arranged in an arc shape; the The plurality of driving circuits in the second driving circuit array are arranged in a straight line.
  • the first drive circuit array and the third drive circuit array include: scan drive circuits, and the second drive circuit array includes: light-emitting drive circuits.
  • the blank circuit array when the driving structure layer further includes a blank circuit array, includes: a first blank circuit array, a second blank circuit array, a third blank circuit array, and a fourth blank circuit array ;
  • the first blank circuit array is located between the first driving circuit array and the first pixel circuit array
  • the second blank circuit array is located between the first pixel circuit array and the second driving circuit array
  • the third blank circuit array is located between the second driving circuit array and the second pixel circuit array
  • the fourth blank circuit array is located between the second pixel circuit array and the third driving circuit between arrays
  • At least part of the blank circuits in the first blank circuit array close to the arc-shaped display boundary are arranged in an arc shape; the plurality of blank circuits in the second blank circuit array and the third blank circuit array are arranged in a straight line, and the first blank circuit array is arranged in a straight line. At least part of the blank circuits in the array of four blank circuits near the arc-shaped display boundary are arranged in an arc shape.
  • the method further includes: a first power supply line, a second power supply line and a data signal line extending along the column direction, and a reset signal line and an initial signal line extending along the row direction, the light emitting structure is connected to the second Power cord electrical connection;
  • each pixel circuit includes: a first pixel transistor to a seventh pixel transistor and a first pixel capacitor; wherein, the control electrode of the first pixel transistor is electrically connected to the reset signal line, and the control electrode of the first pixel transistor is electrically connected to the reset signal line.
  • the first pole is electrically connected to the first pixel node, the second pole of the first pixel transistor is electrically connected to the initial signal line; the control pole of the second pixel transistor is electrically connected to the scan signal line, and the first pole of the second pixel transistor is electrically connected to the first A pixel node is electrically connected, the second pole of the second pixel transistor is electrically connected to the second pixel node; the control pole of the third pixel transistor is electrically connected to the first pixel node, and the first pole of the third pixel transistor is electrically connected to the third pixel node Electrically connected, the second pole of the third pixel transistor is electrically connected to the second pixel node; the control pole of the fourth pixel transistor is electrically connected to the scan signal line, the first pole of the fourth pixel transistor is electrically connected to the data signal line, and the fourth pixel transistor is electrically connected to the data signal line.
  • the second pole of the pixel transistor is electrically connected to the third pixel node; the control pole of the fifth pixel transistor is electrically connected to the light-emitting signal line, the first pole of the fifth pixel transistor is electrically connected to the first power supply line, and the first pole of the fifth pixel transistor is electrically connected to the first power supply line.
  • the second electrode is electrically connected to the third pixel node; the control electrode of the sixth pixel transistor is electrically connected to the light-emitting signal line, the first electrode of the sixth pixel transistor is electrically connected to the second pixel node, and the second electrode of the sixth pixel transistor is electrically connected to the light-emitting signal line
  • the structure is electrically connected; the control electrode of the seventh pixel transistor is electrically connected to the scanning signal line, the first electrode of the seventh pixel transistor is electrically connected to the initial signal line, and the second electrode of the seventh pixel transistor is electrically connected to the light emitting structure; the first pixel The first plate of the capacitor is electrically connected to the first pixel node, and the second plate of the first pixel capacitor is electrically connected to the first power line.
  • the method further includes: a first power supply line extending in the column direction, and a reset signal line and an initial signal line extending in the row direction;
  • the blank circuit includes: a first blank transistor to a seventh blank transistor and a first blank capacitor; wherein the control electrode of the first blank transistor is electrically connected to the reset signal line, and the first electrode of the first blank transistor is connected to the first blank node Electrically connected, the second pole of the first blank transistor is electrically connected to the initial signal line; the control pole of the second blank transistor is electrically connected to the scan signal line, the first pole of the second blank transistor is electrically connected to the first blank node, and the second blank transistor is electrically connected to the first blank node.
  • the second electrode of the blank transistor is electrically connected to the second blank node; the control electrode of the third blank transistor is electrically connected to the first blank node, the first electrode of the third blank transistor is electrically connected to the third blank node, and the third blank transistor is electrically connected to the third blank node.
  • the second electrode is electrically connected to the second blank node;
  • the control electrode of the fourth blank transistor is electrically connected to the scan signal line, the first electrode of the fourth blank transistor is floating, and the second electrode of the fourth blank transistor is electrically connected to the third blank node connected;
  • the control electrode of the fifth blank transistor is electrically connected to the light-emitting signal line, the first electrode of the fifth blank transistor is electrically connected to the first power supply line, and the second electrode of the fifth blank transistor is electrically connected to the third blank node;
  • the sixth The control electrode of the blank transistor is electrically connected to the light-emitting signal line, the first electrode of the sixth blank transistor is electrically connected to the second blank node, the second electrode of the sixth blank transistor is floating or electrically connected to the first power line;
  • the seventh blank transistor The control electrode of the transistor is electrically connected to the scanning signal line, the first electrode of the seventh blank transistor is electrically connected to the initial signal line, and the second electrode of the seventh blank transistor is floating or electrically connected to the first power supply line
  • the method further includes: a third power supply line, a fourth power supply line, a first scan clock signal line, a second scan clock signal line, and a scan initial signal line extending along the column direction;
  • the scan driving circuit includes: a plurality of cascaded first shift registers arranged in sequence along the column direction, each first shift register includes: a first scan transistor to an eighth scan transistor, a first scan capacitor, a two scan capacitors, a scan signal input terminal, a scan signal output terminal, a first scan clock signal terminal, a second scan clock signal terminal, a first scan power supply terminal and a second scan power supply terminal;
  • the control electrode of the first scan transistor is electrically connected to the first scan clock signal terminal, the first electrode of the first scan transistor is electrically connected to the scan signal input terminal, and the second electrode of the first scan transistor is electrically connected to the first scan node;
  • the control electrodes of the two scan transistors are electrically connected to the first scan node, the first electrodes of the second scan transistors are electrically connected to the first scan clock signal terminal, the second electrodes of the second scan transistors are electrically connected to the second scan node;
  • the third scan transistor is electrically connected to the second scan node.
  • the control electrode of the scan transistor is electrically connected to the first scan clock signal terminal, the first electrode of the third scan transistor is electrically connected to the second scan power supply terminal, and the second electrode of the third scan transistor is electrically connected to the second scan node; the fourth scan transistor is electrically connected to the second scan node.
  • the control electrode of the scan transistor is electrically connected to the second scan node, the first electrode of the fourth scan transistor is electrically connected to the first scan power supply terminal, the second electrode of the fourth scan transistor is electrically connected to the scan signal output terminal, and the fifth scan transistor is electrically connected to the scan signal output terminal.
  • the control electrode of the fifth scan transistor is electrically connected to the third scan node, the first electrode of the fifth scan transistor is electrically connected to the scan signal output end, the second electrode of the fifth scan transistor is electrically connected to the second scan clock signal end;
  • the control electrode is electrically connected to the second scan node, the first electrode of the sixth scan transistor is electrically connected to the first scan power supply terminal, the second electrode of the sixth scan transistor is electrically connected to the first electrode of the seventh scan transistor;
  • the seventh scan transistor is electrically connected to the first electrode of the seventh scan transistor;
  • the control electrode of the transistor is electrically connected to the second scan clock signal terminal, the second electrode of the seventh scan transistor is electrically connected to the first scan node;
  • the control electrode of the eighth scan transistor is electrically connected to the second scan power terminal, and the eighth scan transistor is electrically connected to the second scan power terminal.
  • the first pole of the eighth scan transistor is electrically connected to the first scan node, the second pole of the eighth scan transistor is electrically connected to the third scan node; the first plate of the first scan capacitor is electrically connected to the first scan power supply terminal, and the first scan capacitor
  • the second electrode plate of the second scanning capacitor is electrically connected with the second scanning node; the first electrode plate of the second scanning capacitor is electrically connected with the scanning signal output terminal, and the second electrode plate of the second scanning capacitor is electrically connected with the third scanning node;
  • the scan signal input end of the first shift register of the first stage is electrically connected to the scanning initial signal line, and the scan signal output end of the i-1th first shift register is connected to the scan signal input end of the i-th first shift register. Electrically connected, the first scanning power supply terminals of all the first shift registers are electrically connected to the third power supply line, the second scanning power supply terminals of the first shift registers are electrically connected to the fourth power supply line, and the odd-numbered stage first shifts
  • the first scan clock signal terminal of the register is electrically connected to the first scan clock signal line, the second scan clock signal terminal of the odd-numbered stage first shift register is electrically connected to the second scan clock signal line, and the even-numbered stage first shift register is electrically connected to the second scan clock signal line.
  • the first scan clock signal terminal is electrically connected to the second scan clock signal line
  • the second scan clock signal terminal of the even-numbered first shift register is electrically connected to the first scan clock signal line
  • the scan signal output terminal of the first shift register It is electrically connected to the scanning signal line, wherein i is a positive integer greater than or equal to 2.
  • it further includes: a third power supply line, a fourth power supply line, a first light-emitting clock signal line, a second light-emitting clock signal line, and a light-emitting initial signal line extending along the column direction;
  • the light-emitting driving circuit includes: a plurality of cascaded second shift registers arranged in sequence along the column direction, and each second shift register includes: a first light-emitting transistor to a tenth light-emitting transistor, a first light-emitting capacitor to a first light-emitting capacitor three light-emitting capacitors, a light-emitting signal input end, a light-emitting signal output end, a first light-emitting clock signal end, a second light-emitting clock signal end, a first light-emitting power supply end and a second light-emitting power supply end;
  • the control electrode of the first light-emitting transistor is electrically connected to the first light-emitting clock signal terminal, the first electrode of the first light-emitting transistor is electrically connected to the light-emitting signal input end, and the second electrode of the first light-emitting transistor is electrically connected to the first light-emitting node;
  • the control electrode of the second light-emitting transistor is electrically connected to the first light-emitting node, the first electrode of the second light-emitting transistor is electrically connected to the first light-emitting clock signal terminal, and the second electrode of the second light-emitting transistor is electrically connected to the second light-emitting node
  • the node is electrically connected;
  • the control electrode of the third light-emitting transistor is electrically connected to the first light-emitting clock signal terminal, the first electrode of the third light-emitting transistor is electrically connected to the second light-emitting power supply terminal, and the second electrode of the third light-emitting transistor is electrically connected to the
  • the two light-emitting nodes are electrically connected; the control electrode of the fourth light-emitting transistor is electrically connected to the second light-emitting clock signal terminal, the first electrode of the fourth light-emitting transistor is electrically connected to the first light-emitting node, and the second electrode of the fourth light-emitting transistor is electrically connected to the fifth light-emitting node.
  • the first electrode of the light-emitting transistor is electrically connected; the control electrode of the fifth light-emitting transistor is electrically connected to the second light-emitting node, the second electrode of the fifth light-emitting transistor is electrically connected to the first light-emitting power supply terminal; the control electrode of the sixth light-emitting transistor is electrically connected to the first light-emitting power supply terminal;
  • the two light-emitting nodes are electrically connected, the first electrode of the sixth light-emitting transistor is electrically connected to the second light-emitting clock signal terminal, the second electrode of the sixth light-emitting transistor is electrically connected to the third light-emitting node, and the control electrode of the seventh light-emitting transistor is electrically connected to the second light-emitting node.
  • the light-emitting clock signal terminal is electrically connected, the first pole of the seventh light-emitting transistor is electrically connected to the third light-emitting node, the second pole of the seventh light-emitting transistor is electrically connected to the fourth light-emitting node; the control electrode of the eighth light-emitting transistor is electrically connected to the first light-emitting node
  • the nodes are electrically connected, the first pole of the eighth light-emitting transistor is electrically connected to the first light-emitting power supply terminal, the second pole of the eighth light-emitting transistor is electrically connected to the fourth light-emitting node;
  • the control electrode of the ninth light-emitting transistor is electrically connected to the fourth light-emitting node connection, the first pole of the ninth light-emitting transistor is electrically connected to the light-emitting signal output terminal, the second pole of the ninth light-emitting transistor is electrically connected to the first light-emitting power supply terminal;
  • the light-emitting signal input end of the second shift register of the first stage is electrically connected to the light-emitting initial signal line, and the light-emitting signal output end of the second shift register of the i-1st stage is connected to the light-emitting signal input end of the second shift register of the i-th stage.
  • the first light-emitting power supply terminals of all second shift registers are electrically connected to the third power supply line
  • the second light-emitting power supply terminals of the second shift registers are electrically connected to the fourth power supply line
  • the odd-numbered stage second shift The first light-emitting clock signal end of the register is electrically connected to the first light-emitting clock signal line
  • the second light-emitting clock signal end of the odd-numbered second shift register is electrically connected to the second light-emitting clock signal line
  • the even-numbered second shift register is electrically connected to the second light-emitting clock signal line.
  • the first light-emitting clock signal terminal is electrically connected to the second light-emitting clock signal line
  • the second light-emitting clock signal terminal of the even-numbered second shift register is electrically connected to the first light-emitting clock signal line
  • the light-emitting signal output terminal of the second shift register is It is electrically connected to the light-emitting signal line, wherein i is a positive integer greater than or equal to 2.
  • the light-emitting structure layer includes: a first electrode layer, a pixel defining layer, a light-emitting layer and a second electrode layer sequentially stacked on the driving structure layer;
  • the first electrode layer includes: a plurality of a first electrode
  • the light-emitting layer includes: a plurality of organic light-emitting layers
  • the second electrode layer includes: a plurality of second electrodes, each light-emitting structure includes: a first electrode, an organic light-emitting layer and a second electrode;
  • each pixel circuit there is no overlapping area between the orthographic projection of the second electrode of the sixth pixel transistor on the base substrate and the orthographic projection of the first electrode in the light-emitting structure connected to the pixel circuit on the base substrate;
  • the driving structure layer further includes: a connection electrode, the connection electrode is located between the pixel circuit and the light-emitting structure, and is respectively electrically connected to the second electrode of the sixth pixel transistor in the pixel circuit and the first electrode of the light-emitting structure. connect.
  • connection electrode includes: a first connection part and a second connection part
  • the first connection part is arranged on a side of the second connection part close to the base substrate, and the first connection part is respectively connected to the second electrode of the sixth pixel transistor in the pixel circuit and the second electrode
  • the second connecting part is electrically connected with the first electrode in the light emitting structure
  • the first connecting portion and the second connecting portion are integrally formed, or the first connecting portion is a metal electrode, and the second connecting portion is a transparent electrode.
  • the display substrate further includes: an encapsulation layer and a spacer
  • the encapsulation layer is arranged on a side of the light emitting structure layer away from the base substrate, and the spacer is arranged at a side of the encapsulation layer away from the base substrate.
  • the driving structure layer includes: a first insulating layer sequentially stacked on the base substrate , semiconductor layer, second insulating layer, first metal layer, third insulating layer, second metal layer, fourth insulating layer, third metal layer, fifth insulating layer, first flat layer, fourth metal layer, first two flat layers, a fifth metal layer and a third flat layer;
  • the semiconductor layer includes: active layers of a plurality of pixel transistors, active layers of a plurality of blank transistors, active layers of a plurality of scan transistors, and active layers of a plurality of light-emitting transistors;
  • the first metal layer includes: Lighting signal line, scanning signal line, reset signal line, the first electrode plate of the first pixel capacitor, the second electrode plate of the first scanning capacitor, the second electrode plate of the second scanning capacitor, and the first electrode of the first light-emitting capacitor plate, the second plate of the second light-emitting capacitor, the third plate of the third light-emitting capacitor, the control electrodes of multiple pixel transistors, the control electrodes of multiple blank transistors, the control electrodes of multiple scanning transistors, and the multiple light-emitting transistors
  • the second metal layer includes: the initial signal line, the second plate of the first pixel capacitor, the first plate of the first scan capacitor, the second plate of the second scan capacitor, the first light-emitting capacitor The second plate of the second light-emitting capacitor,
  • the orthographic projection of the first power line on the base substrate at least partially overlaps the orthographic projection of the sixth pixel capacitor on the base substrate.
  • the driving structure layer includes: a first connecting part stacked on the base substrate in sequence Insulating layer, semiconductor layer, second insulating layer, first metal layer, third insulating layer, second metal layer, fourth insulating layer, third metal layer, fifth insulating layer, first flat layer, fourth metal layer , a second flat layer, a fifth metal layer, a transparent conductive layer and a third flat layer;
  • the semiconductor layer includes: active layers of a plurality of pixel transistors, active layers of a plurality of blank transistors, active layers of a plurality of scan transistors, and active layers of a plurality of light-emitting transistors;
  • the first metal layer includes: Lighting signal line, scanning signal line, reset signal line, the first electrode plate of the first pixel capacitor, the second electrode plate of the first scanning capacitor, the second electrode plate of the second scanning capacitor, and the first electrode of the first light-emitting capacitor plate, the second plate of the second light-emitting capacitor, the third plate of the third light-emitting capacitor, the control electrodes of multiple pixel transistors, the control electrodes of multiple blank transistors, the control electrodes of multiple scanning transistors, and the multiple light-emitting transistors
  • the second metal layer includes: the initial signal line, the second plate of the first pixel capacitor, the first plate of the first scan capacitor, the second plate of the second scan capacitor, the first light-emitting capacitor The second plate of the second light-emitting capacitor,
  • the orthographic projection of the first power line on the base substrate at least partially overlaps the orthographic projection of the sixth pixel capacitor on the base substrate.
  • the present disclosure also provides a display device including the above-mentioned display substrate.
  • the present disclosure also provides a method for fabricating a display substrate, which is configured to fabricate the above-mentioned display substrate, and the method includes:
  • the driving structure layer includes: a pixel circuit array and a driving circuit array extending along the column direction; the pixel circuit The array and the driving circuit array are arranged in sequence along the row direction; the pixel circuit array comprises: M rows and N columns of pixel circuits, the pixel circuits in the i-th row are electrically connected with the scanning signal lines in the i-th row and the light-emitting signal lines in the i-th row, 1 ⁇ i ⁇ M; the drive circuit array includes: at least one scan drive circuit and at least one light-emitting drive circuit, the scan drive circuit is configured to provide a drive signal to the scan signal line, and the light-emitting drive circuit is configured to provide a drive signal to the scan signal line. the light-emitting signal line provides a driving signal;
  • a light-emitting structure layer is formed on the driving structure layer; the light-emitting structure layer includes: M rows and N columns of light-emitting structures, pixel circuits and light-emitting structures are in one-to-one correspondence, and are electrically connected to the corresponding light-emitting structures.
  • forming the driving structure layer in the display area on the base substrate includes:
  • the forming the light-emitting structure layer on the driving structure layer includes:
  • first electrode layer forming a first electrode layer, a pixel defining layer, a light-emitting layer and a second electrode layer in sequence on the driving structure layer;
  • the method further includes:
  • An encapsulation layer and spacers are formed on the light emitting structure layer.
  • 1 is a schematic structural diagram of a display substrate
  • FIG. 2 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG. 3 is a size comparison diagram 1 of the pixel circuit in the display substrate provided in FIG. 1 and the pixel circuit in the display substrate provided in FIG. 2;
  • FIG. 4 is a size comparison of the pixel circuit in the display substrate provided in FIG. 1 and the pixel circuit in the display substrate provided in FIG. 2 FIG. 2
  • FIG. 5 is a schematic structural diagram of a display area provided by an exemplary embodiment
  • FIG. 6 is a cross-sectional view of a display substrate provided by an exemplary embodiment
  • FIG. 7 is a schematic structural diagram 1 of a display substrate provided by an exemplary embodiment
  • Figure 8 is a cross-sectional view along the A-A' direction of Figure 7;
  • FIG. 9 is a second structural schematic diagram of a display substrate provided by an exemplary embodiment.
  • Figure 10 is a cross-sectional view along the A-A' direction of Figure 9;
  • FIG. 11 is a third structural schematic diagram of a display substrate provided by an exemplary embodiment.
  • Figure 12 is a cross-sectional view along the A-A' direction of Figure 11;
  • FIG. 13 is a fourth schematic structural diagram of a display substrate provided by an exemplary embodiment
  • Figure 14 is a cross-sectional view along the A-A' direction of Figure 13;
  • FIG. 15 is a fifth structural schematic diagram of a display substrate provided by an exemplary embodiment
  • Figure 16 is a cross-sectional view along the A-A' direction of Figure 15;
  • FIG. 17 is a sixth structural schematic diagram of a display substrate provided by an exemplary embodiment.
  • Figure 18 is a cross-sectional view along the A-A' direction of Figure 17;
  • FIG. 19 is an equivalent circuit diagram of a pixel circuit provided by an exemplary embodiment
  • Fig. 20 is a working timing diagram of a pixel circuit provided in Fig. 19;
  • 21 is a schematic structural diagram of a blank circuit provided by an exemplary embodiment
  • FIG. 22 is a schematic structural diagram of a scan driving circuit provided by an exemplary embodiment
  • FIG. 24 is a working timing diagram of the first shift register provided by an exemplary embodiment
  • FIG. 25 is a schematic structural diagram of a light-emitting driving circuit provided by an exemplary embodiment
  • FIG. 26 is an equivalent circuit diagram of a second shift register provided by an exemplary embodiment
  • FIG. 27 is a working timing diagram of a second shift register provided by an exemplary embodiment
  • FIG. 28 is a cross-sectional view 1 of a display substrate provided by an exemplary embodiment
  • FIG. 29 is a second cross-sectional view of a display substrate provided by an exemplary embodiment.
  • the terms “installed”, “connected” and “connected” should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrically connected includes a case where constituent elements are connected together by an element having a certain electrical effect.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having a certain electrical effect” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • film and “layer” are interchangeable.
  • conductive layer may be replaced by “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • FIG. 1 is a schematic structural diagram of a display substrate.
  • the display substrate includes a display area and a non-display area.
  • the display substrate may include a timing controller, a data driving circuit, a scanning driving circuit, a light-emitting driving circuit and a pixel array disposed on the substrate and located in the non-display area, and the display substrate may also include a plurality of scanning signal lines (G1 to Gm), A plurality of data signal lines (D1 to Dn), a plurality of light emission signal lines (E1 to Em), and a plurality of sub-pixels PA.
  • the timing controller may provide grayscale values and control signals suitable for the specification of the data driving circuit to the data driving circuit, and may provide the clock signal, scan start and scanning start suitable for the specification of the scan driving circuit to the data driving circuit Signals and the like are supplied to the scan drive circuit, and a clock signal, an emission stop signal, and the like suitable for the specifications of the light emission drive circuit can be supplied to the light emission drive circuit.
  • the data driving circuit may generate data voltages to be supplied to the data signal lines D1 , D2 , D3 , . . . and Dn using the grayscale values and control signals received from the timing controller.
  • the data driving circuit may sample grayscale values with a clock signal, and apply data voltages corresponding to the grayscale values to the data signal lines D1 to Dn in pixel row units, where n may be a natural number.
  • the scan driving circuit may generate scan signals to be supplied to the scan signal lines G1 , G2 , G3 , . . . and Gm by receiving a clock signal, a scan start signal, and the like from the timing controller.
  • the scan driving circuit may sequentially supply scan signals having on-level pulses to the scan signal lines G1 to Gm.
  • the scan drive circuit may be constructed in the form of a shift register, and may generate scanning in such a manner that a scan start signal supplied in the form of an on-level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal signal, m can be a natural number.
  • the light emission driving circuit may generate emission signals to be supplied to the light emission signal lines E1 , E2 , E3 , . . . and Em by receiving a clock signal, an emission stop signal, and the like from the timing controller.
  • the light emission driving circuit may sequentially supply emission signals having off-level pulses to the light emission signal lines E1 to Em.
  • the light emission drive circuit may be constructed in the form of a shift register, and may generate light emission signals in such a manner that a light emission stop signal supplied in the form of off-level pulses is sequentially transmitted to the next stage circuit under the control of a clock signal.
  • Each sub-pixel may be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light-emitting signal line.
  • each sub-pixel includes a pixel circuit and a light emitting structure.
  • the pixel circuit is electrically connected with the light-emitting structure, and is configured to drive the light-emitting structure to emit light.
  • the light-emitting driving circuit and the scanning driving circuit are arranged in the non-display area, so that the display substrate cannot realize a narrow frame.
  • FIG. 2 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • a display substrate provided by an embodiment of the present disclosure may include: a display area AA and a non-display area.
  • the display substrate includes a base substrate 10 , a driving structure layer 20 and a light emitting structure layer 30 that are sequentially stacked on the base substrate 10 and located in the display area AA.
  • the display substrate further includes: M rows of scanning signal lines and M rows of light-emitting signal lines.
  • the driving structure layer 20 includes: an array 100 of pixel circuits 200 and an array of driving circuits 200 extending along the column direction, and the pixel circuit array 100 and the array of driving circuits 200 are sequentially arranged along the row direction.
  • the light emitting structure layer 30 includes: M rows and N columns of light emitting structures.
  • the pixel circuit array may include: M rows and N columns of pixel circuits.
  • the pixel circuits correspond to the light-emitting structures one-to-one, and are electrically connected to the corresponding light-emitting structures.
  • the pixel circuits of the i-th row are electrically connected to the scan signal lines of the i-th row and the light-emitting signal lines of the i-th row, 1 ⁇ i ⁇ M.
  • the driving circuit array includes: at least one scanning driving circuit and at least one light-emitting driving circuit, the scanning driving circuit is configured to provide driving signals to the scanning signal lines, and the light-emitting driving circuit is configured to provide driving signals to the light-emitting signal lines.
  • the base substrate 10 may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but not limited to, one or more of glass and metal tabs; the flexible substrate may be, but not limited to Polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride , one or more of polyethylene and textile fibers.
  • the scan signal lines and the light emitting signal lines may be disposed in the display area.
  • the intersection of the row direction and the column direction means that the included angle between the row direction and the column direction is about 70 degrees to 90 degrees.
  • the row and column directions can lie in the same plane.
  • the row direction may be the row direction, which is parallel to the extension direction of the scan lines;
  • the column direction may be the column direction, which is parallel to the extension direction of the data lines.
  • the pixel circuit and the light emitting structure may constitute a sub-pixel.
  • the sub-pixels may be any of red (R) sub-pixels, green (G) sub-pixels, blue (B) sub-pixels, and white sub-pixels, which are not limited in the present disclosure.
  • the display panel includes red (R) sub-pixels, green (G) sub-pixels and blue (B) sub-pixels, the three sub-pixels can be arranged in a horizontal parallel, vertical parallel or fringe manner.
  • the display panel includes red (R) sub-pixels, green (G) sub-pixels, blue (B) sub-pixels and white sub-pixels
  • the four sub-pixels can be arranged in a horizontal parallel, vertical parallel or array manner. This is not limited.
  • the light emitting structure may be an organic electroluminescent diode (OLED).
  • OLED organic electroluminescent diode
  • FIG. 3 is a size comparison of the pixel circuit in the display substrate provided in FIG. 1 and the pixel circuit in the display substrate provided in FIG. 2
  • FIG. 4 is the pixel circuit in the display substrate provided in FIG. 1 and the display substrate provided in FIG. 2 .
  • the size of the pixel circuit is compared in Figure 2.
  • the light-emitting structure of the display substrate provided in FIG. 2 remains unchanged compared with the display substrate provided in FIG. 1 .
  • the pixel circuit in FIG. 2 is the same as that in FIG. 1 .
  • the pixel circuits in are proportionally compressed.
  • the equal-proportional compression may include equal-proportional compression along the row direction or equal-proportional compression along the row and column directions.
  • FIG. 3 shows that the pixel circuit PE2 provided in FIG. 2 is formed by compressing the pixel circuit PE1 in the display substrate provided in FIG. 1 with equal proportions in the row direction and the column direction.
  • FIG. 4 shows that the pixel circuit PE2 provided in FIG. 2 is formed by compressing the pixel circuit PE1 in the display substrate provided in FIG. 1 with equal proportions in the row direction.
  • L1 is the length of PE1 along the row direction
  • L2 is the length of PE1 along the column direction
  • L3 is the length of PE2 along the row direction
  • L4 is the length of PE2 along the column direction
  • k is the compression ratio, 0 ⁇ k ⁇ 1.
  • the display substrate provided by the embodiment of the present disclosure includes: a display area and a non-display area, the display substrate includes a base substrate, a driving structure layer and a light-emitting structure layer sequentially stacked on the base substrate and located in the display area, and the display substrate further It includes: M rows of scanning signal lines and M rows of light-emitting signal lines; the light-emitting structure layer includes: M-row and N-column light-emitting structures, and the driving structure layer includes: pixel circuit arrays and driving circuit arrays extending along the column direction; pixel circuit arrays and driving circuits The array is arranged in sequence along the row direction; the pixel circuit array includes: M rows and N columns of pixel circuits, the pixel circuits correspond to the light-emitting structures one-to-one, and are electrically connected with the corresponding light-emitting structures, and the pixel circuits in the ith row are connected with the scanning signal lines in the ith row.
  • the driving circuit array includes: at least one scanning driving circuit and at least one light-emitting driving circuit, the scanning driving circuit is set to provide driving signals to the scanning signal line, and the light-emitting driving circuit is set For providing driving signals to the light-emitting signal lines.
  • the driving circuit array is arranged in the display area, the width of the non-display area is reduced, and a narrow frame can be realized.
  • the area of each pixel circuit may be the same, which ensures that the load of each pixel circuit is the same, and the risk of abnormal display can be avoided to a large extent.
  • FIG. 5 is a schematic structural diagram of a display area provided by an exemplary embodiment.
  • the display area includes an arc-shaped display boundary, and the display area may include: a first boundary AL1 and a second boundary AL2 arranged oppositely, and a third boundary AL3 and a fourth boundary AL4 arranged oppositely.
  • the length of the first boundary AL1 is greater than the length of the third boundary AL3.
  • the first border AL1 and the second border AL2 extend along the column direction and are non-linear structures
  • the arc display border is located in the first border AL1 and the second border AL2
  • the third border AL3 and the fourth border AL4 are along the row. It extends in the direction and has a linear structure.
  • At least a portion of the pixel circuits near the boundary of the arc-shaped display are arranged in an arc shape.
  • the shape of the display area AA may be a rectangle with rounded corners, which is not limited in the present disclosure.
  • FIG. 6 is a cross-sectional view of a display substrate provided by an exemplary embodiment.
  • the driving structure layer further includes: a blank circuit array 300 .
  • the blank circuit array is disposed between the pixel circuit array 100 and the driving circuit array 200 .
  • the blank circuit array includes: a plurality of blank circuits, and the blank circuits are electrically connected with the scanning signal lines and the light-emitting signal lines. Disposing the blank circuit array in the present disclosure can fully ensure the uniformity of the pixel circuit driving display.
  • the display substrate may include: M rows and K columns of blank circuits, and the i-th row of blank circuits is electrically connected to the i-th row of scan signal lines and the i-th row of light-emitting signal lines.
  • the value of K may be determined according to the size of the display substrate and the signals of each signal line.
  • FIG. 7 is a first structural schematic diagram of a display substrate provided by an exemplary embodiment
  • FIG. 8 is a cross-sectional view along the direction A-A' of FIG. 7
  • the pixel circuit array includes: a second pixel circuit array PR2 , a first pixel circuit array PR1 and a third pixel circuit array PR3 which are sequentially arranged along the row direction.
  • the driving circuit array includes: a first driving circuit array GR1 and a second driving circuit array GR2 arranged in the row direction.
  • the first driving circuit array GR1 is located between the first pixel circuit array PR1 and the second pixel circuit array PR2, and the second driving circuit array GR2 is located between the first pixel circuit array PR1 and the third pixel circuit array PR3.
  • the first pixel circuit array may include: M rows and N1 columns of pixel circuits
  • the second pixel circuit array may include: M rows and N2 columns of pixel circuits
  • the plurality of driving circuits in the first driving circuit array and the second driving circuit array may be arranged in a straight line.
  • the first driving circuit array and the second driving circuit array may include: scanning driving circuits and light-emitting driving circuits; the scanning driving circuits and light-emitting driving circuits located in the same driving circuit array are arranged in a row direction
  • the first drive circuit array includes: a scan drive circuit
  • the second drive circuit array includes: a light-emitting drive circuit
  • the first drive circuit array includes: a light-emitting drive circuit
  • the second drive circuit array includes: a scan drive circuit.
  • FIG. 9 is a second structural schematic diagram of a display substrate provided by an exemplary embodiment
  • FIG. 10 is a cross-sectional view along the direction A-A' of FIG. 9
  • the blank circuit array includes: a first blank circuit array BR1, a second blank circuit array BR2, a third blank circuit array BR2, and a third blank circuit array Blank circuit array BR3 and fourth blank circuit array BR4.
  • the first blank circuit array BR1 is located between the second pixel circuit array PR2 and the first drive circuit array GR1
  • the second blank circuit array BR2 is located between the first drive circuit array GR1 and the first pixel circuit array PR1
  • the third blank circuit array BR2 is located between the first drive circuit array GR1 and the first pixel circuit array PR1.
  • the blank circuit array BR4 is located between the first pixel circuit array PR1 and the second driving circuit array GR2, and the fourth blank circuit array BR4 is located between the second driving circuit array GR2 and the third pixel circuit array PR3.
  • the plurality of blank circuits of the first blank circuit array, the second blank circuit array, the third blank circuit array and the fourth blank circuit array may be arranged in a straight line
  • FIG. 11 is a third structural schematic diagram of a display substrate provided by an exemplary embodiment
  • FIG. 12 is a cross-sectional view along the direction A-A' of FIG. 11
  • the driving circuit array includes: a first driving circuit array GR1 and a second driving circuit array GR2 sequentially arranged in a row direction.
  • the first driving circuit array GR1 is disposed on the side of the pixel circuit array PR close to the first boundary of the display area
  • the second driving circuit array GR2 is disposed on the side of the pixel circuit array PR close to the second boundary of the display area.
  • At least part of the driving circuits in the first driving circuit array close to the arc-shaped display boundary are arranged in an arc shape.
  • At least part of the driving circuits in the second driving circuit array close to the arc-shaped display boundary are arranged in an arc shape.
  • the first driving circuit array and the second driving circuit array may include: scanning driving circuits and light-emitting driving circuits; the scanning driving circuits and light-emitting driving circuits located in the same driving circuit array are arranged in a row direction
  • the first drive circuit array includes: a scan drive circuit
  • the second drive circuit array includes: a light-emitting drive circuit
  • the first drive circuit array includes: a light-emitting drive circuit
  • the second drive circuit array includes: a scan drive circuit.
  • Fig. 13 is a schematic diagram 4 of a structure of a display substrate provided by an exemplary embodiment
  • Fig. 14 is a cross-sectional view taken along the direction A-A' of Fig. 13
  • the driving structure layer further includes: a blank circuit array
  • the blank circuit array includes: a first blank circuit array BR1 and a second blank circuit array BR2.
  • the first blank circuit array BR1 is located between the first driving circuit array GR1 and the pixel circuit array PR
  • the second blank circuit array BR2 is located between the pixel circuit array PR and the second driving circuit array GR2.
  • At least part of the blank circuits in the first blank circuit array close to the arc-shaped display boundary are arranged in an arc shape.
  • At least part of the blank circuits in the second blank circuit array close to the arc-shaped display boundary are arranged in an arc shape.
  • Fig. 15 is a fifth structural schematic diagram of a display substrate provided by an exemplary embodiment
  • Fig. 16 is a cross-sectional view taken along the direction A-A' of Fig. 15
  • the pixel circuit array includes: a first pixel circuit array PR1 and a second pixel circuit array PR2 which are sequentially arranged along the row direction.
  • the drive circuit array includes: a first drive circuit array GR1, a second drive circuit array GR2 and a third drive circuit array GR3 arranged in sequence along the row direction.
  • the first pixel circuit array PR1 is located between the first driving circuit array GR1 and the second driving circuit array GR2, and the second pixel circuit array PR2 is located between the second driving circuit array GR2 and the third driving circuit array GR3.
  • the first pixel circuit array includes: M rows and N4 columns of pixel circuits
  • At least part of the driving circuits in the first driving circuit array close to the arc-shaped display boundary are arranged in an arc shape.
  • At least part of the driving circuits in the third driving circuit array close to the arc-shaped display boundary are arranged in an arc shape.
  • the plurality of driving circuits in the second driving circuit array are arranged in a straight line.
  • the first driving circuit array and the third driving circuit array may include: a scanning driving circuit
  • the second driving circuit array may include: a light-emitting driving circuit.
  • the present disclosure places the light-emitting driving circuit in the middle of the display, using The unilateral drive method is conducive to narrowing the left and right borders of the display product;
  • Fig. 17 is a sixth schematic structural diagram of a display substrate provided by an exemplary embodiment
  • Fig. 18 is a cross-sectional view taken along the direction A-A' of Fig. 17
  • the blank circuit array includes: a first blank circuit array BR1 , a second blank circuit array BR2 , a third blank circuit array BR3 and a fourth blank circuit array BR1 Circuit array BR4.
  • the first blank circuit array BR1 is located between the first drive circuit array GR1 and the first pixel circuit array PR1
  • the second blank circuit array BR2 is located between the first pixel circuit array PR1 and the second drive circuit array GR2
  • the third blank circuit array BR2 is located between the first pixel circuit array PR1 and the second drive circuit array GR2.
  • the blank circuit array BR3 is located between the second driving circuit array GR2 and the second pixel circuit array PR2
  • the fourth blank circuit array BR4 is located between the second pixel circuit array PR2 and the third driving circuit array GR3.
  • At least part of the blank circuits in the first blank circuit array close to the arc-shaped display boundary are arranged in an arc shape.
  • the plurality of blank circuits in the second blank circuit array are arranged in a straight line.
  • the plurality of blank circuits in the third blank circuit array are arranged in a straight line.
  • At least part of the blank circuits in the fourth blank circuit array close to the arc-shaped display boundary are arranged in an arc shape.
  • the display substrate may further include: first power lines, second power lines, third power lines, fourth power lines, data signal lines, first scan clock signal lines, The second scan clock signal line, the first light emission clock signal line, the second light emission clock signal line, the scan initial signal line and the light emission initial signal line, and the reset signal line and the initial signal line extending in the row direction.
  • the light emitting structure is electrically connected to the second power line.
  • the first power line and the third power line continuously provide a high-level signal
  • the second power line and the third power line continuously provide a low-level signal
  • the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure.
  • FIG. 19 is an equivalent circuit diagram of a pixel circuit provided by an exemplary embodiment.
  • a pixel circuit provided by an exemplary embodiment may include: first pixel transistors PT1 to seventh pixel transistors PT7 and a first pixel capacitor PC.
  • the control electrode of the first pixel transistor PT1 is electrically connected to the reset signal line RESET, the first electrode of the first pixel transistor PT1 is electrically connected to the first pixel node PN1, and the second electrode of the first pixel transistor PT1 is electrically connected to the initial signal line INIT electrical connection.
  • the control electrode of the second pixel transistor PT2 is electrically connected to the scanning signal line GATE, the first electrode of the second pixel transistor PT2 is electrically connected to the first pixel node PN1, and the second electrode of the second pixel transistor PT2 is electrically connected to the second pixel node PN2 connect.
  • the control electrode of the third pixel transistor PT3 is electrically connected to the first pixel node PN1, the first electrode of the third pixel transistor PT3 is electrically connected to the third pixel node PN3, and the second electrode of the third pixel transistor PT3 is electrically connected to the second pixel node PN2 electrical connection.
  • the control electrode of the fourth pixel transistor PT4 is electrically connected to the scan signal line G, the first electrode of the fourth pixel transistor PT4 is electrically connected to the data signal line D, and the second electrode of the fourth pixel transistor PT4 is electrically connected to the third pixel node PN3 .
  • the control electrode of the fifth pixel transistor PT5 is electrically connected to the light-emitting signal line E, the first electrode of the fifth pixel transistor PT5 is electrically connected to the first power supply line VDD, and the second electrode of the fifth pixel transistor PT5 is electrically connected to the third pixel node PN3. connect.
  • the control electrode of the sixth pixel transistor PT6 is electrically connected to the light-emitting signal line E, the first electrode of the sixth pixel transistor PT6 is electrically connected to the second pixel node PN2, and the second electrode of the sixth pixel transistor PT6 is electrically connected to the light-emitting structure L.
  • the control electrode of the seventh pixel transistor PT7 is electrically connected to the scanning signal line G, the first electrode of the seventh pixel transistor PT7 is electrically connected to the initial signal line INIT, and the second electrode of the seventh pixel transistor PT7 is electrically connected to the light emitting structure L.
  • the first plate PC11 of the first pixel capacitor PC1 is electrically connected to the first pixel node PN1, and the second plate PC12 of the first pixel capacitor PC1 is electrically connected to the first power line VDD.
  • the first pixel transistor PT1, the second pixel transistor PT2, the fourth pixel transistor PT4 to the seventh pixel transistor PT7 may be switching transistors.
  • the third pixel transistor PT3 may be a driving transistor.
  • the first to seventh pixel transistors PT1 to PT7 may employ low temperature polysilicon thin film transistors, or may employ oxide thin film transistors, or may employ both low temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor adopts low temperature polysilicon (Low Temperature Poly-Silicon, LTPS for short), and the active layer of the oxide thin film transistor adopts oxide (Oxide).
  • Low temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • a low temperature polycrystalline silicon thin film transistor and an oxide thin film transistor can be integrated on a display substrate to form a low temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide, LTPO for short) display substrate, and the advantages of both can be utilized, It can achieve high resolution (Pixel Per Inch, PPI for short), low frequency drive, reduce power consumption, and improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • the first to seventh pixel transistors PT1 to PT7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.
  • the first to seventh pixel transistors PT1 to PT7 may include P-type transistors and N-type transistors.
  • FIG. 20 is an operation timing diagram of a pixel circuit provided in FIG. 19 .
  • the first pixel transistor PT1 to the seventh pixel transistor PT7 are P-type transistors through the operation process of the pixel circuit exemplified in FIG. 19 .
  • the pixel circuit in FIG. One pixel transistor T1 to seventh pixel transistor T7), one capacitor (PC1), seven signal lines (data signal line D, scan signal line G, light-emitting signal line E, initial signal line INIT and reset signal line RESET) and Two power lines (first power line VDD and second power line VSS).
  • the working process of the pixel circuit can include:
  • the first stage A1 is called the reset stage, the signal of the reset signal line RESET is a low-level signal, and the signals of the scanning signal line G and the light-emitting signal line E are high-level signals.
  • the signal of the reset signal line RESET is a low-level signal, which turns on the first pixel transistor T1, and the signal of the initial signal line INIT is supplied to the first pixel node PN1 to initialize the first pixel capacitor PC1 and clear the first pixel capacitor PC1. Central data voltage.
  • the signals of the scanning signal line G and the light-emitting signal line E are high-level signals, so that the second pixel transistor T2, the fourth pixel transistor T4, the fifth pixel transistor T5, the sixth pixel transistor T6 and the seventh pixel transistor T7 are turned off, At this stage, the light emitting structure L does not emit light.
  • the second stage A2 called the data writing stage or the threshold compensation stage, the signal of the scanning signal line G is a low-level signal, the signals of the reset signal line RESET and the light-emitting signal line E are a high-level signal, and the data signal line D outputs data voltage.
  • the third pixel transistor T3 is turned on.
  • the signal of the scan signal line G is a low level signal, so that the second pixel transistor T2, the fourth pixel transistor T4 and the seventh pixel transistor T7 are turned on.
  • the second pixel transistor T2 and the fourth pixel transistor T4 are turned on so that the data voltage output from the data signal line D passes through the third pixel node N3, the turned-on third pixel transistor T3, the second pixel node PN2, and the turned-on second pixel
  • the transistor T2 is provided to the first pixel node PN1, and charges the difference between the data voltage output by the data signal line D and the threshold voltage of the third pixel transistor T3 into the first pixel capacitor PC1, and the voltage of the first pixel node PN1 is Vd-
  • the seventh pixel transistor T7 is turned on so that the initial voltage of the initial signal line INIT is supplied to the first pole of the light emitting structure L, the first pole of the light emitting structure L is initialized (reset), the internal pre-stored voltage is cleared, the initialization is completed, and the OLEDs do not emit light.
  • the signal of the reset signal line RESET is a high level signal, so that the first pixel transistor T1 is turned off.
  • the signal of the light-emitting signal line E is a high-level signal, so that the fifth pixel transistor T5 and the sixth pixel transistor T6 are turned off.
  • the third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the scanning signal line G and the reset signal line RESET are high-level signals.
  • the signal of the light-emitting signal line E is a low-level signal, so that the fifth pixel transistor T5 and the sixth pixel transistor T6 are turned on, and the power supply voltage output from the first power supply line VDD passes through the fifth pixel transistor T5 and the third pixel transistor that are turned on.
  • T3 and the sixth pixel transistor T6 provide a driving voltage to the first electrode of the light emitting structure L to drive the light emitting structure L to emit light.
  • the driving current flowing through the third pixel transistor T3 (the driving pixel transistor) is determined by the voltage difference between the control electrode and the first electrode thereof. Since the voltage of the first pixel node PN1 is Vdata-
  • I is the driving current flowing through the third pixel transistor T3, that is, the driving current driving the light-emitting structure L
  • K is a constant
  • Vgs is the voltage difference between the control electrode and the first electrode of the third pixel transistor T3
  • Vth is the threshold voltage of the third pixel transistor T3
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power line VDD.
  • FIG. 21 is a schematic structural diagram of a blank circuit provided by an exemplary embodiment.
  • a blank circuit provided by an exemplary embodiment includes: a first blank transistor BT1 to a seventh blank transistor BT7 and a first blank capacitor BC1.
  • the control electrode of the first blank transistor BT1 is electrically connected to the reset signal line RESET, the first electrode of the first blank transistor BT1 is electrically connected to the first blank node BN1, and the second electrode of the first blank transistor BT1 is electrically connected to the initial signal line INIT electrical connection.
  • the control electrode of the second blank transistor BT2 is electrically connected to the scan signal line G, the first electrode of the second blank transistor BT2 is electrically connected to the first blank node BN1, and the second electrode of the second blank transistor BT2 is electrically connected to the second blank node BN2 connect.
  • the control electrode of the third blank transistor BT3 is electrically connected to the first blank node BN1, the first electrode of the third blank transistor BT3 is electrically connected to the third blank node BN3, and the second electrode of the third blank transistor BT3 is electrically connected to the second blank node BN2 electrical connection.
  • the control electrode of the fourth blank transistor BT4 is electrically connected to the scan signal line G, the first electrode of the fourth blank transistor BT4 is floating, and the second electrode of the fourth blank transistor BT4 is electrically connected to the third blank node BN3.
  • the control electrode of the fifth blank transistor BT5 is electrically connected to the light-emitting signal line E, the first electrode of the fifth blank transistor BT5 is electrically connected to the first power supply line VDD, and the second electrode of the fifth blank transistor BT5 is electrically connected to the third blank node BN3. connect.
  • the control electrode of the sixth blank transistor BT6 is electrically connected to the light-emitting signal line E, the first electrode of the sixth blank transistor BT6 is electrically connected to the second blank node BN2, and the second electrode of the sixth blank transistor BT6 is floating or connected to the first power supply. electrical connection.
  • the control electrode of the seventh blank transistor BT7 is electrically connected to the scanning signal line G, the first electrode of the seventh blank transistor BT7 is electrically connected to the initial signal line INIT, and the second electrode of the seventh blank transistor BT7 is electrically connected to the first electrode of the sixth blank transistor BT6. Diode electrical connection.
  • the first plate BC11 of the first blank capacitor BC1 is electrically connected to the first blank node BN1, and the second plate BC12 of the first blank capacitor BC1 is electrically connected to the first power line VDD.
  • FIG. 21 illustrates by taking an example that the second electrode of the sixth blank transistor BT6 is floating.
  • the first to seventh blank transistors BT1 to BT7 may be switching transistors.
  • the first blank transistor BT1 to the seventh blank transistor BT7 may use low temperature polysilicon thin film transistors, or may use oxide thin film transistors, or may use low temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor adopts low temperature polysilicon (Low Temperature Poly-Silicon, LTPS for short), and the active layer of the oxide thin film transistor adopts oxide (Oxide).
  • Low temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • a low temperature polycrystalline silicon thin film transistor and an oxide thin film transistor can be integrated on a display substrate to form a low temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide, LTPO for short) display substrate, and the advantages of both can be utilized, It can achieve high resolution (Pixel Per Inch, PPI for short), low frequency drive, reduce power consumption, and improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • FIG. 22 is a schematic structural diagram of a scan driving circuit provided by an exemplary embodiment
  • FIG. 23 is an equivalent circuit diagram of a first shift register provided by an exemplary embodiment
  • FIG. 24 is provided by an exemplary embodiment.
  • a scan driving circuit provided by an exemplary embodiment may include: a plurality of cascaded first shift registers GOA sequentially arranged in a column direction.
  • Each first shift register GOA includes: a first scan transistor GT1 to an eighth scan transistor GT8, a first scan capacitor GC1, a second scan capacitor GC2, a scan signal input terminal GIN, a scan signal output terminal GOUT, a first scan clock The signal terminal GCK1, the second scan clock signal terminal GCK2, the first scan power terminal GV1 and the second scan power terminal GV2.
  • the control electrode of the first scan transistor GT1 is electrically connected to the first scan clock signal terminal GCK1, the first electrode of the first scan transistor GT1 is electrically connected to the scan signal input terminal GIN, and the second electrode of the first scan transistor GT1 is electrically connected to the first scan signal input terminal GIN.
  • Node GN1 is electrically connected.
  • the control electrode of the second scan transistor GT2 is electrically connected to the first scan node GN1, the first electrode of the second scan transistor GT2 is electrically connected to the first scan clock signal terminal GCK1, and the second electrode of the second scan transistor GT2 is electrically connected to the second scan node GCK1.
  • Node GN2 is electrically connected.
  • the control electrode of the third scan transistor GT3 is electrically connected to the first scan clock signal terminal GCK1, the first electrode of the third scan transistor GT3 is electrically connected to the second scan power supply terminal GV2, and the second electrode of the third scan transistor GT3 is electrically connected to the second scan power supply terminal GV2.
  • the scanning node GN2 is electrically connected.
  • the control pole of the fourth scan transistor GT4 is electrically connected to the second scan node GN2, the first pole of the fourth scan transistor GT4 is electrically connected to the first scan power supply terminal, and the second pole of the fourth scan transistor GT4 is electrically connected to the scan signal output terminal GOUT Electrically connected, the control pole of the fifth scan transistor GT5 is electrically connected to the third scan node, the first pole of the fifth scan transistor GT5 is electrically connected to the scan signal output terminal GOUT, and the second pole of the fifth scan transistor GT5 is electrically connected to the second scan node
  • the clock signal terminal GCK2 is electrically connected.
  • the control electrode of the sixth scan transistor GT6 is electrically connected to the second scan node GN2, the first electrode of the sixth scan transistor GT6 is electrically connected to the first scan power supply terminal GV1, and the second electrode of the sixth scan transistor GT6 is electrically connected to the seventh scan transistor The first pole of GT7 is electrically connected.
  • the control electrode of the seventh scan transistor GT7 is electrically connected to the second scan clock signal terminal GCK2, and the second electrode of the seventh scan transistor GT7 is electrically connected to the first scan node GN1.
  • the control electrode of the eighth scan transistor GT8 is electrically connected to the second scan power supply terminal GV2, the first electrode of the eighth scan transistor GT8 is electrically connected to the first scan node GN1, and the second electrode of the eighth scan transistor GT8 is electrically connected to the third scan node GN3 electrical connection.
  • the first plate GC11 of the first scan capacitor GC1 is electrically connected to the first scan power terminal GV1, and the second plate GC12 of the first scan capacitor GC1 is electrically connected to the second scan node GN2.
  • the first plate GC21 of the second scan capacitor GC2 is electrically connected to the scan signal output terminal GOUT, and the second plate GC22 of the second scan capacitor GC2 is electrically connected to the third scan node GN3.
  • the scanning signal input terminal GIN of the first shift register GOA(1) of the first stage is electrically connected to the scanning initial signal line GSTV, and the scanning signal output terminal GOUT of the i-1st stage first shift register GOA(i-1) is electrically connected to the scanning signal line GSTV.
  • the scan signal input terminal GIN of the first shift register GOA(i) of the i-th stage is electrically connected, and the first scan power supply terminals GV1 of all the first shift registers are electrically connected to the third power supply line VGH.
  • the second scan power supply terminal GV2 is electrically connected to the fourth power supply line VGL
  • the first scan clock signal terminal GCK1 of the odd-numbered first shift registers is electrically connected to the first scan clock signal line GCK
  • the odd-numbered first shift registers are electrically connected to the first scan clock signal line GCK.
  • the second scan clock signal terminal GCK2 is electrically connected to the second scan clock signal line GCB
  • the first scan clock signal terminal GCK1 of the even-numbered first shift register is electrically connected to the second scan clock signal line GCB
  • the even-numbered first shift register is electrically connected to the second scan clock signal line GCB.
  • the second scan clock signal end GCK2 of the register is electrically connected to the first scan clock signal line GCK
  • the scan signal output end of the first shift register is electrically connected to the scan signal line, wherein i is a positive integer greater than or equal to 2.
  • the first to eighth scan transistors GT1 to GT8 may be switching transistors.
  • the first to eighth scan transistors GT1 to GT8 may employ low temperature polysilicon thin film transistors, or may employ oxide thin film transistors, or may employ both low temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor adopts low temperature polysilicon (Low Temperature Poly-Silicon, LTPS for short), and the active layer of the oxide thin film transistor adopts oxide (Oxide).
  • Low temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • a low temperature polycrystalline silicon thin film transistor and an oxide thin film transistor can be integrated on a display substrate to form a low temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide, LTPO for short) display substrate, and the advantages of both can be utilized, It can achieve high resolution (Pixel Per Inch, PPI for short), low frequency drive, reduce power consumption, and improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • the number of the first shift registers may be M.
  • the working process of the first shift register may include the following stages:
  • the signal of the first scan clock signal line GCK1 is a low level signal
  • the signal of the second scan clock signal line GCK2 is a high level signal
  • the signal of the scan signal input terminal GIN is a low level signal. Since the signal of the first scan clock signal terminal GCK1 is a low level signal, the first scan transistor GT1 is turned on, and the signal of the scan signal input terminal GIN is transmitted to the first scan node GN1 through the first scan transistor GT1. Since the signal of the eighth scan transistor GT8 receives the low level signal of the second scan power supply terminal GV2, the eighth scan transistor GT8 is in an on state.
  • the level signal of the third scan node GN3 can control the fifth scan transistor GT5 to be turned on, and the signal of the second scan clock signal terminal GCK2 is transmitted to the scan signal output terminal GOUT through the fifth scan transistor GT5, that is, in the input stage t1, the scan signal
  • the output terminal GOUT is the signal of the second scan clock signal terminal GCK2 of the high level signal.
  • the third scan transistor GT3 is turned on, and the low level signal of the second scan power supply terminal GV2 is transmitted to the second scan node GN2 via the third scan transistor GT3 .
  • both the fourth scan transistor GT4 and the sixth scan transistor GT6 are turned on. Since the signal of the second scan clock signal terminal GCK2 is a high level signal, the seventh scan transistor GT7 is turned off.
  • the signal of the first scan clock signal terminal GCK1 is a high level signal
  • the signal of the second scan clock signal terminal GCK2 is a low level signal
  • the signal of the scan signal input terminal GIN is a high level signal.
  • the fifth scan transistor GT5 is turned on, and the signal of the second scan clock signal terminal GCK2 is used as the signal of the scan signal output terminal GOUT via the fifth scan transistor GT5.
  • the level signal of the end of the second scan capacitor GC2 connected to the scan signal output terminal GOUT becomes the signal of the second scan power supply terminal GV2.
  • the eighth scan transistor GT8 When it is turned off, the fifth scan transistor GT5 can be turned on better, and the signal of the signal output terminal OUT is a low-level signal.
  • the signal of the first scan clock signal terminal GCK1 is a high level signal, so that both the first scan transistor GT1 and the third scan transistor GT3 are turned off.
  • the second scan transistor GT2 is turned on, and the high-level signal of the first scan clock signal terminal GCK1 is transmitted to the second scan node GN2 via the second scan transistor GT2, so that both the fourth scan transistor GT4 and the sixth scan transistor GT6 are turned off . Since the signal of the second scan clock signal terminal GCK2 is a low level signal, the seventh scan transistor GT7 is turned on.
  • the signals of the first scan clock signal terminal GCK1 and the second scan clock signal terminal GCK2 are both high-level signals
  • the signal of the scan signal input terminal GIN is a high-level signal
  • the fifth scan transistor GT5 is turned on
  • the signal of the second scan clock signal terminal GCK2 is used as the signal of the scan signal output terminal GOUT through the fifth scan transistor GT5.
  • the scan signal output terminal GOUT is a high level signal. Due to the bootstrap action of the second scan capacitor GC2, the level signal of the first scan node GN1 becomes VGL-VthN1.
  • the signal of the first scan clock signal terminal GCK1 is a high level signal, so that both the first scan transistor GT1 and the third scan transistor GT3 are turned off, the eighth scan transistor GT8 is turned on, the second scan transistor GT2 is turned on, and the first scan transistor GT1 is turned on.
  • the high-level signal of the scan clock signal terminal GCK1 is transmitted to the second scan node GN2 via the second scan transistor GT2, so that both the fourth scan transistor GT4 and the sixth scan transistor GT6 are turned off. Since the signal of the second scan clock signal terminal GCK2 is a high level signal, the seventh scan transistor GT7 is turned off.
  • the signal of the first scan clock signal terminal GCK1 is a low level signal
  • the signal of the second clock signal CB is a high level signal
  • the signal of the scan signal input terminal GIN is a high level signal flat signal. Since the signal of the first scan clock signal terminal GCK1 is a low level signal, the first scan transistor GT1 is turned on, the signal of the scan signal input terminal GIN is transmitted to the first scan node GN1 through the first scan transistor GT1, and the second scan transistor GT2 deadline. Since the eighth scan transistor GT8 is in an on state, the fifth scan transistor GT5 is turned off.
  • the third scan transistor GT3 is turned on, the fourth scan transistor GT4 and the sixth scan transistor GT6 are both turned on, and the high level signal of the first scan power supply terminal GV1 It is transmitted to the scan signal output terminal GOUT through the fourth scan transistor GT4, that is, the gate output signal is a high level signal.
  • the signal of the first scan clock signal terminal GCK1 is a high level signal
  • the signal of the second clock signal CB is a low level signal
  • the signal of the scan signal input terminal GIN is a high level signal flat signal.
  • Both the fifth scan transistor GT5 and the second scan transistor GT2 are turned off.
  • the signal of the first scan clock signal terminal GCK1 is a high-level signal, so that the first scan transistor GT1 and the third scan transistor GT3 are both turned off. Due to the holding effect of the first scan capacitor C1, the fourth scan transistor GT4 and the sixth scan transistor GT4 and the sixth scan transistor are both turned off.
  • the transistors GT6 are all turned on, and the high-level signal is transmitted to the scan signal output terminal GOUT through the fourth scan transistor GT4, that is, the gate output signal is a high-level signal.
  • the seventh scan transistor GT7 is turned on, so that the high-level signal is transmitted through the sixth scan transistor GT6 and the seventh scan transistor GT7.
  • the signals are transmitted to the third scan node GN3 and the first scan node GN1, so that the signals of the third scan node GN3 and the first scan node GN1 are kept as high-level signals.
  • the signals of the first scan clock signal terminal GCK1 and the second scan clock signal terminal GCK2 are both high-level signals, and the signals of the scan signal input terminal GIN are high-level signals.
  • the fifth scan transistor GT5 and the second scan transistor GT2 are turned off.
  • the signal of the first scan clock signal terminal GCK1 is a high level signal, so that the first scan transistor GT1 and the third scan transistor GT3 are both turned off, and the fourth scan transistor GT4 and the sixth scan transistor GT6 are both turned on.
  • the high-level signal passes through the fourth scan transistor GT4 to the scan signal output terminal GOUT, that is, the gate output signal is a high-level signal.
  • FIG. 25 is a schematic structural diagram of a light-emitting driving circuit provided by an exemplary embodiment
  • FIG. 26 is an equivalent circuit diagram of a second shift register provided by an exemplary embodiment
  • FIG. 27 is provided by an exemplary embodiment.
  • a light-emitting driving circuit provided by an exemplary embodiment includes: a plurality of cascaded second shift registers EOA arranged in sequence along a column direction, and each second shift register includes: a first shift register EOA.
  • the control electrode of the first light-emitting transistor ET1 is electrically connected to the first light-emitting clock signal terminal ECK1
  • the first electrode of the first light-emitting transistor ET1 is electrically connected to the light-emitting signal input terminal EIN
  • the second electrode of the first light-emitting transistor ET1 is electrically connected to the first light-emitting transistor ET1.
  • Node EN1 is electrically connected.
  • the control electrode of the second light-emitting transistor ET2 is electrically connected to the first light-emitting node EN1
  • the first electrode of the second light-emitting transistor ET2 is electrically connected to the first light-emitting clock signal terminal ECK1
  • the second electrode of the second light-emitting transistor ET2 is electrically connected to the second light-emitting node EN1.
  • Node EN2 is electrically connected.
  • the control electrode of the third light-emitting transistor ET3 is electrically connected to the first light-emitting clock signal terminal ECK1, the first electrode of the third light-emitting transistor ET3 is electrically connected to the second light-emitting power supply terminal EV2, and the second electrode of the third light-emitting transistor ET3 is electrically connected to the second light-emitting power supply terminal EV2.
  • the light emitting node EN2 is electrically connected.
  • the control electrode of the fourth light-emitting transistor ET4 is electrically connected to the second light-emitting clock signal terminal ECK2, the first electrode of the fourth light-emitting transistor ET4 is electrically connected to the first light-emitting node EN1, and the second electrode of the fourth light-emitting transistor ET4 is electrically connected to the fifth light-emitting node EN1.
  • the first pole of the transistor ET5 is electrically connected.
  • the control electrode of the fifth light-emitting transistor ET5 is electrically connected to the second light-emitting node EN2, and the second electrode of the fifth light-emitting transistor ET5 is electrically connected to the first light-emitting power supply terminal EV1.
  • the control electrode of the sixth light-emitting transistor ET6 is electrically connected to the second light-emitting node EN2
  • the first electrode of the sixth light-emitting transistor ET6 is electrically connected to the second light-emitting clock signal terminal ECK2
  • the second electrode of the sixth light-emitting transistor ET6 is electrically connected to the third light-emitting node Node EN3 is electrically connected.
  • the control electrode of the seventh light-emitting transistor ET7 is electrically connected to the second light-emitting clock signal terminal ECK2, the first electrode of the seventh light-emitting transistor ET7 is electrically connected to the third light-emitting node EN3, and the second electrode of the seventh light-emitting transistor ET7 is electrically connected to the fourth light-emitting node Node EN4 is electrically connected.
  • the control electrode of the eighth light-emitting transistor ET8 is electrically connected to the first light-emitting node EN1
  • the first electrode of the eighth light-emitting transistor ET8 is electrically connected to the first light-emitting power supply terminal EV1
  • the second electrode of the eighth light-emitting transistor ET8 is electrically connected to the fourth light-emitting node EN4 electrical connection.
  • the control pole of the ninth light-emitting transistor ET9 is electrically connected to the fourth light-emitting node EN4, the first pole of the ninth light-emitting transistor ET9 is electrically connected to the light-emitting signal output terminal EOUT, and the second pole of the ninth light-emitting transistor ET9 is electrically connected to the first light-emitting power supply terminal EV1 is electrically connected.
  • the control electrode of the tenth light-emitting transistor ET10 is electrically connected to the first light-emitting node EN1, the first electrode of the tenth light-emitting transistor ET10 is electrically connected to the second light-emitting power supply terminal EV2, and the second electrode of the tenth light-emitting transistor ET10 is electrically connected to the light-emitting signal output terminal. EOUT is electrically connected.
  • the first plate EC11 of the first light-emitting capacitor EC1 is electrically connected to the second light-emitting node EN2, the second plate EC12 of the first light-emitting capacitor EC1 is electrically connected to the third light-emitting node EN3; the first plate of the second light-emitting capacitor EC2 EC21 is electrically connected to the first light-emitting node EN1, the second plate EC22 of the second light-emitting capacitor EC2 is electrically connected to the second light-emitting clock signal terminal ECK2; the first plate EC31 of the third light-emitting capacitor EC3 is electrically connected to the fourth light-emitting node EN4 connected, the second plate EC32 of the third light-emitting capacitor EC3 is electrically connected to the first light-emitting power supply terminal EV1.
  • the light-emitting signal input end EIN of the first-stage second shift register EOA(1) is electrically connected to the light-emitting initial signal line ESTV
  • the light-emitting signal output end EOUT of the i-1st-stage second shift register EOA(i-1) is electrically connected to the light-emitting signal line ESTV.
  • the light-emitting signal input terminals EIN of the i-th second shift registers EOA(i) are electrically connected
  • the first light-emitting power supply terminals EV1 of all second shift registers are electrically connected to the third power supply line VGH.
  • the second shift registers are electrically connected to the third power supply line VGH.
  • the second light-emitting power supply terminal EV2 is electrically connected to the fourth power supply line VGL
  • the first light-emitting clock signal terminal ECK1 of the odd-numbered second shift registers is electrically connected to the first light-emitting clock signal line GCK
  • the odd-numbered second shift registers are electrically connected to the first light-emitting clock signal line GCK.
  • the second light-emitting clock signal terminal ECK2 is electrically connected to the second light-emitting clock signal line GCB
  • the first light-emitting clock signal terminal ECK1 of the even-numbered second shift register is electrically connected to the second light-emitting clock signal line GCB
  • the even-numbered second shift register is electrically connected to the second light-emitting clock signal line GCB.
  • the second light-emitting clock signal terminal ECK2 of the register is electrically connected to the first light-emitting clock signal line GCK.
  • the light-emitting signal output terminal EOUT of the second shift register is electrically connected to the light-emitting signal line E, wherein i is a positive integer greater than or equal to 2.
  • the number of the second shift registers may be M, or may be M/2.
  • the first to tenth light emitting transistors ET1 to ET10 may be switching transistors.
  • the first to tenth light emitting transistors ET1 to ET10 may employ low temperature polysilicon thin film transistors, or may employ oxide thin film transistors, or may employ both low temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor adopts low temperature polysilicon (Low Temperature Poly-Silicon, LTPS for short), and the active layer of the oxide thin film transistor adopts oxide (Oxide).
  • Low temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • a low temperature polycrystalline silicon thin film transistor and an oxide thin film transistor can be integrated on a display substrate to form a low temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide, LTPO for short) display substrate, and the advantages of both can be utilized, It can achieve high resolution (Pixel Per Inch, PPI for short), low frequency drive, reduce power consumption, and improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • the working process of the second shift register may include the following stages:
  • the signal of the light-emitting signal input terminal EIN is a high-level signal
  • the signal of the first light-emitting clock signal terminal ECK1 is a low-level signal
  • the first light-emitting transistor ET1 and the third light-emitting transistor ET3 are turned on, and the light-emitting signal input
  • the signal of the terminal EIN is written to the first light-emitting node EN1, at this time, the first light-emitting node EN1 is at a high level
  • the signal of the second power supply terminal VL2 is written to the second light-emitting node EN2, at this time, the second light-emitting node EN2 Node EN2 is low.
  • the second light emitting transistor ET2 , the eighth light emitting transistor ET8 and the tenth light emitting transistor ET10 are turned off.
  • the signal of the second light-emitting clock signal terminal ECK2 is a high-level signal, and the fourth light-emitting transistor ET4 and the seventh light-emitting transistor ET7 are turned off.
  • the second light emitting node EN2 is at a low level, the fifth light emitting transistor ET5 and the sixth light emitting transistor ET6 are turned on, and the signal of the second light emitting clock signal terminal ECK2 is written to the third light emitting node EN3.
  • the fourth light emitting node EN4 maintains the high level of the previous frame
  • the ninth light emitting transistor ET9 is turned off, and the output signal of the light emitting signal output terminal EOUT maintains the low level of the previous frame.
  • the signal of the light-emitting signal input terminal EIN and the signal of the first light-emitting clock signal terminal ECK1 are high-level signals
  • the first light-emitting transistor ET1 and the third light-emitting transistor ET3 are turned off
  • the first light-emitting node EN1 maintains a high level.
  • the second light-emitting transistor ET2, the eighth light-emitting transistor ET10 and the tenth light-emitting transistor ET10 are turned off, the second light-emitting node EN2 is kept at a low level, the fifth light-emitting transistor ET5 and the sixth light-emitting transistor ET6 are turned on, due to the second light-emitting clock signal
  • the signal of the terminal ECK2 is a low level signal
  • the fourth light-emitting transistor ET4 and the seventh light-emitting transistor ET7 are turned on
  • the signal of the second light-emitting clock signal terminal ECK2 is written into the third light-emitting node EN3, and the third light-emitting node EN3 is powered by a high level.
  • the signal of the third light-emitting node EN3 is written into the fourth light-emitting node EN4, the fourth light-emitting node EN4 is low level, the ninth light-emitting transistor ET9 is turned on, and the light-emitting signal output terminal EOUT outputs the first power supply terminal. High level signal of VL1.
  • the signal of the light-emitting signal input terminal EIN is a high-level signal
  • the signal of the first light-emitting clock signal terminal ECK1 is a low-level signal
  • the first light-emitting transistor ET1 and the third light-emitting transistor ET3 are turned on
  • the first light-emitting transistor ET1 and the third light-emitting transistor ET3 are turned on.
  • the node EN1 is at a high level, the second light-emitting transistor ET2, the eighth light-emitting transistor ET10 and the tenth light-emitting transistor ET10 are turned off, the second light-emitting node EN2 is kept at a low level, the fifth light-emitting transistor ET5 and the sixth light-emitting transistor ET6 are turned on,
  • the signal of the second light-emitting clock signal terminal ECK2 is written into the third light-emitting node EN3. Since the signal of the second light-emitting clock signal terminal ECK2 is a high-level signal, the third light-emitting node EN3 changes from the low level of the previous stage to the high level.
  • the fourth light-emitting transistor ET4 and the seventh light-emitting transistor ET7 are turned off, the fourth light-emitting node EN4 remains low, the ninth light-emitting transistor ET9 is turned on, and the light-emitting signal output terminal EOUT outputs a high-level signal of the first power supply terminal VL1.
  • the signal of the light-emitting signal input terminal EIN is a low-level signal
  • the signal of the first light-emitting clock signal terminal ECK1 is a high-level signal
  • the first light-emitting transistor ET1 and the third light-emitting transistor ET3 are turned off
  • the first light-emitting node is turned off.
  • EN1 maintains a high level
  • the second light emitting transistor ET2 the eighth light emitting transistor ET10 and the tenth light emitting transistor ET10 are turned off
  • the second light emitting node EN2 maintains a low level
  • the fifth light emitting transistor ET5 and the sixth light emitting transistor ET6 are turned on
  • the first light emitting transistor ET5 and the sixth light emitting transistor ET6 are turned on.
  • the signal of the second light-emitting clock signal terminal ECK2 is written into the third light-emitting node EN3. Since the signal of the second light-emitting clock signal terminal ECK2 is a low-level signal, the third light-emitting node EN3 changes from the high level of the previous stage to the low level.
  • the fourth light-emitting transistor ET4 and the seventh light-emitting transistor ET7 are turned on, the signal of the third light-emitting node EN3 is written into the fourth light-emitting node EN4, the fourth light-emitting node EN4 is kept at a low level, the ninth light-emitting transistor ET9 is turned on, and the light-emitting signal
  • the output terminal EOUT outputs a high level signal of the first power supply terminal VL1.
  • the signal of the light-emitting signal input terminal EIN and the signal of the first light-emitting clock signal terminal ECK1 are low-level signals
  • the first light-emitting transistor ET1 and the third light-emitting transistor ET3 are turned on
  • the first light-emitting node EN1 is powered by a high level.
  • the third light-emitting node EN3 changes from the low level of the previous stage to a high level level
  • the fourth light-emitting transistor ET4 and the seventh light-emitting transistor ET7 are turned off. Since the eighth light-emitting transistor ET8 is turned on, the high-level signal of the first power supply terminal VL1 is written into the fourth light-emitting node EN4, and the fourth light-emitting node EN4 becomes When the level is high, the ninth light-emitting transistor ET9 is turned off.
  • the tenth light-emitting transistor ET10 Since the tenth light-emitting transistor ET10 is turned on, the low-level signal of the second power supply terminal VL2 is written to the light-emitting signal output terminal EOUT, and the light-emitting signal output terminal EOUT outputs a low-level signal.
  • the signal of the light-emitting signal input terminal EIN is a low-level signal
  • the signal of the first light-emitting clock signal terminal ECK1 is a high-level signal
  • the first light-emitting transistor ET1 and the third light-emitting transistor ET3 are turned off, and the first light-emitting node is turned off.
  • EN1 remains at a low level
  • the second light-emitting transistor ET2, the eighth light-emitting transistor ET10 and the tenth light-emitting transistor ET10 are turned on
  • the signal of the first light-emitting node EN1 is written into the second light-emitting node EN2
  • the second light-emitting node EN2 is at a low level Transition to a high level
  • the fifth light-emitting transistor ET5 and the sixth light-emitting transistor ET6 are turned off
  • the third light-emitting node EN3 maintains a high level.
  • the fourth light-emitting transistor ET4 and the seventh light-emitting transistor ET7 is turned on, the signal of the third light-emitting node EN3 is written into the fourth light-emitting node EN4, the fourth light-emitting node EN4 maintains a high level, and the ninth light-emitting transistor ET9 is turned off. Since the tenth light-emitting transistor ET10 is turned on, The low-level signal of the second power supply terminal VL2 is written into the light-emitting signal output terminal EOUT, and the light-emitting signal output terminal EOUT outputs a low-level signal.
  • the signal of the light-emitting signal input terminal EIN is a low-level signal
  • the signal of the first light-emitting clock signal terminal ECK1 is a low-level signal
  • the first light-emitting transistor ET1 and the third light-emitting transistor ET3 are turned on
  • the first light-emitting transistor ET1 and the third light-emitting transistor ET3 are turned on.
  • the node EN1 is kept at a low level, the second light-emitting transistor ET2, the eighth light-emitting transistor ET10 and the tenth light-emitting transistor ET10 are turned on, the signal of the first light-emitting node EN1 is written into the second light-emitting node EN2, and the second light-emitting node EN2 is low. level, the fifth light-emitting transistor ET5 and the sixth light-emitting transistor ET6 are turned on, and the signal of the second light-emitting clock signal terminal ECK2 is written into the third light-emitting node EN3.
  • the signal of the second light-emitting clock signal terminal ECK2 is a high-level signal
  • the The fourth light-emitting transistor ET4 and the seventh light-emitting transistor ET7 are turned off, the fourth light-emitting node EN4 is kept at a high level, and the ninth light-emitting transistor ET9 is turned off. Since the tenth light-emitting transistor ET10 is turned on, the low-level signal of the second power supply terminal VL2 is written The light-emitting signal output end EOUT, and the light-emitting signal output end EOUT outputs a low-level signal.
  • the signal of the light-emitting signal input terminal EIN is a low-level signal
  • the signal of the first light-emitting clock signal terminal ECK1 is a high-level signal
  • the first light-emitting transistor ET1 and the third light-emitting transistor ET3 are turned off
  • the first light-emitting node is turned off.
  • EN1 remains at a low level
  • the second light-emitting transistor ET2, the eighth light-emitting transistor ET10 and the tenth light-emitting transistor ET10 are turned on
  • the signal of the first light-emitting node EN1 is written into the second light-emitting node EN2
  • the second light-emitting node EN2 is at a low level Transition to a high level
  • the fifth light-emitting transistor ET5 and the sixth light-emitting transistor ET6 are turned off
  • the third light-emitting node EN3 maintains a high level.
  • the fourth light-emitting transistor ET4 and the seventh light-emitting transistor ET7 is turned on, the signal of the third light-emitting node EN3 is written into the fourth light-emitting node EN4, the fourth light-emitting node EN4 maintains a high level, and the ninth light-emitting transistor ET9 is turned off. Since the tenth light-emitting transistor ET10 is turned on, The low-level signal of the second power supply terminal VL2 is written into the light-emitting signal output terminal EOUT, and the light-emitting signal output terminal EOUT outputs a low-level signal.
  • the eighth light-emitting transistor ET8 is continuously turned on
  • the ninth light-emitting transistor ET9 is turned off
  • the first light-emitting transistor ET1 periodically charges the second capacitor C2
  • the first light-emitting node EN1 maintains a low level
  • the tenth light-emitting transistor ET10 is continuously turned on
  • the light-emitting signal output terminal EOUT outputs a low-level signal until a pulse of the light-emitting signal input terminal EIN of the next frame enters.
  • FIG. 28 is a first cross-sectional view of a display substrate provided by an exemplary embodiment
  • FIG. 29 is a second cross-sectional view of a display substrate provided by an exemplary embodiment
  • the light emitting structure layer 30 includes: a first electrode layer, a pixel defining layer 34 , a light emitting layer and a second electrode layer that are sequentially stacked on the driving structure layer 20 .
  • the first electrode layer includes a plurality of first electrodes 31, the light-emitting layer includes a plurality of organic light-emitting layers 32, the second electrode layer includes a plurality of second electrodes 33, and each light-emitting structure includes: an electrode, an organic light-emitting layer and a second electrode.
  • the organic light-emitting layer may include a stacked hole injection layer (Hole Injection Layer, referred to as HIL), a hole transport layer (Hole Transport Layer, referred to as HTL), an electron blocking layer (Electron Block Layer). , referred to as EBL), light-emitting layer (Emitting Layer, referred to as EML), hole blocking layer (Hole Block Layer, referred to as HBL), electron transport layer (Electron Transport Layer, referred to as ETL) and electron injection layer (Electron Injection Layer, referred to as EIL) ).
  • HIL stacked hole injection layer
  • HTL hole transport layer
  • EML electron blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • the hole injection layers of all subpixels may be a common layer connected together
  • the electron injection layers of all subpixels may be a common layer connected together
  • the hole transport layers of all subpixels may be A common layer connected together
  • the electron transport layer of all subpixels can be a common layer connected together
  • the hole blocking layer of all subpixels can be a common layer connected together
  • the light emitting layers of adjacent subpixels can have a small amount of The electron blocking layers of adjacent sub-pixels may overlap slightly, or may be isolated.
  • the sixth pixel transistor PT6 may include an active layer 61 , a control electrode 62 , a first electrode 63 and a second electrode 64 .
  • the orthographic projection of the second electrode 64 of the sixth pixel transistor PT6 on the base substrate 10 and the orthographic projection of the first electrode 31 in the light-emitting structure connected to the pixel circuit on the base substrate 10 do not exist
  • the overlapping area, that is, the pixel circuit and the light emitting structure are arranged staggered.
  • the pixel defining layer may be an organic material such as polyimide, acrylic, or polyethylene terephthalate.
  • the first electrode layer may be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the second electrode layer may employ any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or Alloys made with any one or more of the above metals.
  • the driving structure layer 20 includes: a connection electrode 21 , the connection electrode 21 is located between the pixel circuit and the light-emitting structure, and is connected to the sixth pixel transistor in the pixel circuit
  • the second electrode 64 is electrically connected to the first electrode 31 in the light emitting structure.
  • the connection electrode 21 includes: a first connection part 210 and a second connection part 220 .
  • the first connection part is arranged on the side of the second connection part 220 close to the base substrate 10 , the first connection part 210 is electrically connected to the second electrode 64 and the second connection part 220 of the sixth pixel transistor in the pixel circuit, respectively, and the first connection part 210
  • the two connection parts 220 are electrically connected to the first electrode 31 in the light emitting structure.
  • the first connection part may be a metal electrode
  • the second connection part may be a transparent electrode
  • the first connecting portion is a metal electrode
  • the second connecting portion is a transparent electrode, so that the connecting electrode is not easy to see, and the display effect of the display substrate can be ensured.
  • first connecting portion and the second connecting portion may be integrally formed.
  • first connecting portion and the second connecting portion are integrally formed, which can simplify the manufacturing process of the display substrate and save the manufacturing cost of the display substrate.
  • the display substrate may further include: an encapsulation layer 40 and a spacer 50 .
  • the encapsulation layer 40 is disposed on the side of the light emitting structure layer 30 away from the base substrate 10
  • the spacer 50 is disposed on the side of the encapsulation layer 40 away from the base substrate 10 .
  • the encapsulation layer may adopt a stacked structure of inorganic material/organic material/inorganic material, and the organic material layer is disposed between two inorganic material layers.
  • the driving structure layer may further include: An insulating layer 22, a semiconductor layer, a second insulating layer 23, a first metal layer, a third insulating layer 24, a second metal layer, a fourth insulating layer 25, a third metal layer, a fifth insulating layer 26, a first flat layer 27 , a fourth metal layer, a second planarization layer 28 , a fifth metal layer, a transparent conductive layer, and a third planarization layer 29 .
  • the semiconductor layer includes: active layers of a plurality of pixel transistors, active layers of a plurality of blank transistors, active layers of a plurality of scan transistors, and active layers of a plurality of light-emitting transistors;
  • a metal layer includes: a light-emitting signal line, a scanning signal line, a reset signal line, a first electrode plate PC11 of the first pixel capacitor, a second electrode plate of the first scanning capacitor, a second electrode plate of the second scanning capacitor, a first electrode plate PC11 of the first pixel capacitor.
  • the second metal layer includes: the initial signal line, the second electrode plate PC22 of the first pixel capacitor, the first electrode plate of the first scanning capacitor, and the second electrode plate of the second scanning capacitor ,
  • the driving structure layer 20 when the first connecting portion and the second connecting portion are integrally formed, the driving structure layer 20 further includes: a first connecting portion sequentially stacked on the base substrate 10 Insulating layer 22, semiconductor layer, second insulating layer 23, first metal layer, third insulating layer 24, second metal layer, fourth insulating layer 25, third metal layer, fifth insulating layer 26, first planarization layer 27 .
  • a fourth metal layer, a second flat layer 28 , a fifth metal layer and a third flat layer 29 a fourth metal layer, a second flat layer 28 , a fifth metal layer and a third flat layer 29 .
  • the semiconductor layer includes: active layers of a plurality of pixel transistors, active layers of a plurality of blank transistors, active layers of a plurality of scan transistors, and active layers of a plurality of light-emitting transistors;
  • the first metal layer includes: a light-emitting signal Line, scan signal line, reset signal line, first plate PC11 of the first pixel capacitor, second plate of the first scan capacitor, second plate of the second scan capacitor, first plate of the first light-emitting capacitor , the second plate of the second light-emitting capacitor, the third plate of the third light-emitting capacitor, the control electrodes of multiple pixel transistors, the control electrodes of multiple blank transistors, the control electrodes of multiple scanning transistors, and the control electrodes of multiple light-emitting transistors control electrode;
  • the second metal layer includes: the initial signal line, the second electrode plate PC12 of the first pixel capacitor, the first electrode plate of the first scanning capacitor, the second electrode plate of the second scanning capacitor, the first electrode plate of the first light-
  • the orthographic projection of the first power line on the base substrate in the display substrate covers the orthographic projection of the first pixel capacitor on the base substrate.
  • the orthographic projection of the first power line in the display substrate on the base substrate covers the orthographic projection of the first pixel capacitor on the base substrate, which can reduce the area occupied by the pixel circuit.
  • the first power line and the data signal line may also be disposed on the third metal layer.
  • the first metal layer, the second metal layer, the third metal layer, the fourth metal layer and the fifth metal layer may use metal materials, such as silver (Ag), copper (Cu), aluminum Any one or more of (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), may be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • metal materials such as silver (Ag), copper (Cu), aluminum
  • AlNd aluminum-neodymium alloy
  • MoNb molybdenum-niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may adopt silicon oxide (SiOx), silicon nitride (SiNx) and nitrogen Any one or more of silicon oxide (SiON), which may be a single layer, multiple layers or composite layers.
  • the first insulating layer is called a buffer layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer and the third insulating layer are called the gate insulating (GI) layer
  • the fourth insulating layer is called the layer
  • the fifth insulating layer is called the passivation (PVX) layer.
  • organic materials such as polyimide, acrylic or polyethylene terephthalate may be used for the first to third planarizing layers.
  • Embodiments of the present disclosure also provide a display device including a display substrate.
  • the display device may be a liquid crystal display device (Liquid Crystal Display, LCD for short) or an organic light emitting diode (Organic Light Emitting Diode, OLED for short) display device.
  • the display device can be: liquid crystal panel, electronic paper, OLED panel, active-matrix organic light emitting diode (active-matrix organic light emitting diode, AMOLED for short) panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame , navigator and any other product or component with display function.
  • the display substrate is the display substrate provided in the above-mentioned embodiment, and the realization principle and effect are similar, and details are not repeated here.
  • An embodiment of the present disclosure further provides a method for manufacturing a display substrate, which is configured to manufacture a display substrate.
  • the method for manufacturing a display substrate provided by an embodiment of the present disclosure includes:
  • Step S1 providing a base substrate.
  • Step S2 forming M rows of scanning signal lines, M rows of light-emitting signal lines and a driving structure layer in the display area on the base substrate.
  • the driving structure layer includes: a pixel circuit array and a driving circuit array extending in a column direction. Wherein, the pixel circuit array and the driving circuit array are sequentially arranged along the row direction.
  • the pixel circuit array includes: M rows and N columns of pixel circuits, the pixel circuits of the i-th row are electrically connected to the scan signal lines of the i-th row and the light-emitting signal lines of the i-th row.
  • the driving circuit array includes: a plurality of driving circuits configured to provide driving signals to the scanning signal lines and the light emitting signal lines.
  • Step S3 forming a light emitting structure layer on the driving structure layer.
  • the light emitting structure layer includes: M rows and N columns of light emitting structures, the pixel circuits and the light emitting structures are in one-to-one correspondence, and are electrically connected to the corresponding light emitting structures.
  • the "patterning process” mentioned in this embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, developing, etching and stripping photoresist.
  • the "photolithography process” mentioned in this embodiment includes processes such as film coating, mask exposure, and development.
  • the deposition may be any one or more selected from sputtering, evaporation and chemical vapor deposition.
  • the coating may be any one or more selected from spray coating and spin coating.
  • the etching may be any one or more selected from dry etching and wet etching.
  • “Film” refers to a thin film made of a material on a substrate by a deposition or coating process.
  • the "film” can also be referred to as a "layer”.
  • the "film” needs a patterning process during the entire production process, it is called a “film” before the patterning process, and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • a first insulating layer, a semiconductor layer, a second insulating layer, a first metal layer, a third insulating layer, a second metal layer, and a fourth insulating layer are sequentially formed on the base substrate , a third metal layer, a fifth insulating layer, a first flat layer, a fourth metal layer, a second flat layer, a fifth metal layer, a transparent conductive layer and a third flat layer.
  • the three metal layers, the fifth insulating layer, the first planarization layer, the fourth metal layer, the second planarization layer, the fifth metal layer, the transparent conductive layer and the third planarization layer may include: sequentially depositing the first insulating layer on the base substrate Thin film and semiconductor thin film, patterning the first insulating thin film and semiconductor thin film through a patterning process to form a first insulating layer pattern and a semiconductor layer pattern; on the substrate forming the aforementioned pattern, sequentially depositing a second insulating thin film and a first metal thin film, The second insulating film and the first metal film are patterned through a patterning process to form a second insulating layer pattern and a first metal layer pattern on the second insulating layer; on the substrate on which
  • forming the driving structure layer in the display area on the base substrate may include: sequentially forming a first insulating layer, a semiconductor layer, a second insulating layer, a first metal layer, The third insulating layer, the second metal layer, the fourth insulating layer, the third metal layer, the fifth insulating layer, the first planarization layer, the fourth metal layer, the second planarization layer, the fifth metal layer, and the third planarization layer.
  • the three metal layers, the fifth insulating layer, the first flat layer, the fourth metal layer, the second flat layer, the fifth metal layer and the third flat layer may include: sequentially depositing the first insulating film and the semiconductor film on the base substrate , patterning the first insulating film and the semiconductor film through a patterning process to form a first insulating layer pattern and a semiconductor layer pattern; on the substrate forming the aforementioned pattern, sequentially depositing the second insulating film and the first metal film, through the patterning process The second insulating film and the first metal film are patterned to form a second insulating layer pattern and a first metal layer pattern on the second insulating layer; on the substrate on which the foregoing pattern is formed, a third insulating film and a second metal
  • forming the light emitting structure layer on the driving structure layer includes: sequentially forming a first electrode layer, a pixel defining layer, a light emitting layer and a second electrode layer on the driving structure layer.
  • Forming the first electrode layer, the pixel defining layer, the light emitting layer and the second electrode layer in sequence on the driving structure layer may include: coating the first electrode thin film on the substrate on which the third flat layer pattern is formed, and forming the first electrode through a patterning process Layer pattern, coating a pixel-defining film on the substrate forming the aforementioned pattern, and forming a pixel-defining (PDL) layer pattern through masking, exposing, and developing processes, a pixel opening is provided on the pixel-defining layer, and the pixel-defining film in the pixel opening is developed away, exposing the surface of the first electrode.
  • PDL pixel-defining
  • the pixel defining layer is provided with first openings, and the pixel defining film in the first openings is developed to expose the surface of the connection electrodes; a light-emitting layer and a second electrode layer are formed in sequence on the substrate on which the pattern is formed.
  • the method for fabricating the display substrate may further include: forming an encapsulation layer and a spacer on the light emitting structure layer.

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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种显示基板及其制作方法、显示装置，其中，显示基板包括：衬底基板以及依次叠设在衬底基板上，且位于显示区的驱动结构层和发光结构层，显示基板还包括：M行扫描信号线和M行发光信号线；发光结构层包括：M行N列发光结构，驱动结构层包括：沿列方向延伸的像素电路阵列和驱动电路阵列；像素电路阵列和驱动电路阵列沿行方向依次排布；像素电路阵列包括：M行N列像素电路，像素电路和发光结构一一对应，且与对应的发光结构电连接，驱动电路阵列包括：至少一个扫描驱动电路和至少一个发光驱动电路，扫描驱动电路设置为向扫描信号线提供驱动信号，发光驱动电路设置为向发光信号线提供驱动信号。

Description

显示基板及其制作方法、显示装置 技术领域
本公开实施例涉及但不限于显示领域，特别涉及一种显示基板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)是当今显示器研究领域的热点之一。与液晶显示器(Liquid Crystal Display，简称LCD)相比，有机发光二极管OLED具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点，已广泛应用于手机、平板电脑和数码相机等显示领域中。
随着显示技术的不断发展，大“屏占比(即实际显示区的面积在显示侧总面积中的占比)”已成为显示装置追求的外观特性之一。尤其是对与佩戴式显示装置(如智能手表)，基于便携和视角效果的方面的考虑，极致窄边框甚至全屏显示成为发展的重要趋势。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种显示基板，包括：显示区和非显示区，所述显示基板包括：衬底基板以及依次叠设在所述衬底基板上，且位于所述显示区的驱动结构层和发光结构层，所述显示基板还包括：M行扫描信号线和M行发光信号线；所述发光结构层包括：M行N列发光结构，所述驱动结构层包括：沿列方向延伸的像素电路阵列和驱动电路阵列；所述像素电路阵列和所述驱动电路阵列沿行方向依次排布；
所述像素电路阵列包括：M行N列像素电路，像素电路和发光结构一一对应，且与对应的发光结构电连接，第i行像素电路与第i行扫描信号线和第i行发光信号线电连接，1≤i≤M；
所述驱动电路阵列包括：至少一个扫描驱动电路和至少一个发光驱动电路，所述扫描驱动电路设置为向所述扫描信号线提供驱动信号，所述发光驱动电路设置为向所述发光信号线提供驱动信号。
在一些可能的实现方式中，所述驱动结构层还包括：空白电路阵列；所述空白电路阵列设置在所述像素电路阵列和所述驱动电路阵列之间；
所述空白电路阵列包括：多个空白电路，空白电路与扫描信号线和发光信号线电连接。
在一些可能的实现方式中，所述显示区包括：至少一端弧形显示边界，所述显示区包括：相对设置的第一边界和第二边界及相对设置的第三边界和第四边界；所述第一边界的长度大于所述第三边界的长度；
所述第一边界和所述第二边界沿列方向延伸，且为非直线型结构，所述弧形显示边界位于所述第一边界和所述第二边界中，所述第三边界和所述第四边界沿行方向延伸，且为直线型结构；
靠近弧形显示边界的至少部分像素电路呈弧形状排布。
在一些可能的实现方式中，所述像素电路阵列包括：沿行方向依次排布的第二像素电路阵列、第一像素电路阵列和第三像素电路阵列；所述驱动电路阵列包括：沿行方向排布的第一驱动电路阵列和第二驱动电路阵列；
所述第一驱动电路阵列位于所述第一像素电路阵列和所述第二像素电路阵列之间，所述第二驱动电路阵列位于所述第一像素电路阵列和所述第三像素电路阵列之间；
所述第一驱动电路阵列和所述第二驱动电路阵列中的多个驱动电路呈直线型排布。
在一些可能的实现方式中，所述驱动结构层还包括空白电路阵列时，所述空白电路阵列包括：第一空白电路阵列、第二空白电路阵列、第三空白电路阵列和第四空白电路阵列；
所述第一空白电路阵列位于所述第二像素电路阵列和所述第一驱动电路阵列之间，所述第二空白电路阵列位于所述第一驱动电路阵列和所述第一像素电路阵列之间，所述第三空白电路阵列位于所述第一像素电路阵列和所述 第二驱动电路阵列，所述第四空白电路阵列位于所述第二驱动电路阵列和所述第三像素电路阵列之间；
第一空白电路阵列、第二空白电路阵列、第三空白电路阵列和第四空白电路阵列的多个空白电路呈直线型排布。
在一些可能的实现方式中，所述驱动电路阵列包括：沿行方向依次排布的第一驱动电路阵列和第二驱动电路阵列；
所述第一驱动电路阵列设置在所述像素电路阵列靠近所述显示区的第一边界的一侧，所述第二驱动电路阵列设置在所述像素电路阵列靠近所述显示区的第二边界的一侧；
所述第一驱动电路阵列中靠近弧形显示边界的至少部分驱动电路呈弧形状排布；所述第二驱动电路阵列中靠近弧形显示边界的至少部分驱动电路呈弧形状排布。
在一些可能的实现方式中，所述驱动结构层还包括空白电路阵列时，所述空白电路阵列包括：第一空白电路阵列和第二空白电路阵列；
所述第一空白电路阵列位于所述第一驱动电路阵列和所述像素电路阵列之间，所述第二空白电路阵列位于所述像素电路阵列和所述第二驱动电路阵列之间；
所述第一空白电路阵列中靠近弧形显示边界的至少部分空白电路呈弧形状排布；所述第二空白电路阵列中靠近弧形显示边界的至少部分空白电路呈弧形状排布。
在一些可能的实现方式中，所述第一驱动电路阵列和第二驱动电路阵列均包括：扫描驱动电路和发光驱动电路；位于同一驱动电路阵列中的扫描驱动电路和发光驱动电路沿行方向排布；
或者，所述第一驱动电路阵列包括：扫描驱动电路，所述第二驱动电路阵列包括：发光驱动电路。
在一些可能的实现方式中，所述像素电路阵列包括：沿行方向依次排布的第一像素电路阵列和第二像素电路阵列；所述驱动电路阵列包括：沿行方向依次排布的第一驱动电路阵列、第二驱动电路阵列和第三驱动电路阵列；
所述第一像素电路阵列位于所述第一驱动电路阵列和所述第二驱动电路阵列之间，所述第二像素电路阵列位于第二驱动电路阵列和所述第三驱动电路阵列之间；
所述第一驱动电路阵列中靠近弧形显示边界的至少部分驱动电路呈弧形状排布；所述第三驱动电路阵列中靠近弧形显示边界的至少部分驱动电路呈弧形状排布；所述第二驱动电路阵列多个驱动电路呈直线型排布。
在一些可能的实现方式中，所述第一驱动电路阵列和所述第三驱动电路阵列包括：扫描驱动电路，所述第二驱动电路阵列包括：发光驱动电路。
在一些可能的实现方式中，所述驱动结构层还包括空白电路阵列时，所述空白电路阵列包括：第一空白电路阵列、第二空白电路阵列、第三空白电路阵列和第四空白电路阵列；
所述第一空白电路阵列位于所述第一驱动电路阵列和所述第一像素电路阵列之间，所述第二空白电路阵列位于所述第一像素电路阵列和所述第二驱动电路阵列之间，所述第三空白电路阵列位于所述第二驱动电路阵列和所述第二像素电路阵列之间，所述第四空白电路阵列位于所述第二像素电路阵列和所述第三驱动电路阵列之间；
所述第一空白电路阵列中靠近弧形显示边界的至少部分空白电路呈弧形状排布；第二空白电路阵列和第三空白电路阵列中的多个空白电路呈直线型排布，所述第四空白电路阵列中靠近弧形显示边界的至少部分空白电路呈弧形状排布。
在一些可能的实现方式中，还包括：沿列方向延伸的第一电源线、第二电源线和数据信号线以及沿行方向延伸的复位信号线和初始信号线，所述发光结构与第二电源线电连接；
每个像素电路的尺寸相同，所述像素电路包括：第一像素晶体管至第七像素晶体管和第一像素电容；其中，第一像素晶体管的控制极与复位信号线电连接，第一像素晶体管的第一极与第一像素节点电连接，第一像素晶体管的第二极与初始信号线电连接；第二像素晶体管的控制极与扫描信号线电连接，第二像素晶体管的第一极与第一像素节点电连接，第二像素晶体管的第二极与第二像素节点电连接；第三像素晶体管的控制极与第一像素节点电连 接，第三像素晶体管的第一极与第三像素节点电连接，第三像素晶体管的第二极与第二像素节点电连接；第四像素晶体管的控制极与扫描信号线电连接，第四像素晶体管的第一极与数据信号线电连接，第四像素晶体管的第二极与第三像素节点电连接；第五像素晶体管的控制极与发光信号线电连接，第五像素晶体管的第一极与第一电源线电连接，第五像素晶体管的第二极与第三像素节点电连接；第六像素晶体管的控制极与发光信号线电连接，第六像素晶体管的第一极与第二像素节点电连接，第六像素晶体管的第二极与发光结构电连接；第七像素晶体管的控制极与扫描信号线电连接，第七像素晶体管的第一极与初始信号线电连接，第七像素晶体管的第二极与发光结构电连接；第一像素电容的第一极板与第一像素节点电连接，第一像素电容的第二极板与第一电源线电连接。
在一些可能的实现方式中，还包括：沿列方向延伸的第一电源线以及沿行方向延伸的复位信号线和初始信号线；
所述空白电路包括：第一空白晶体管至第七空白晶体管和第一空白电容；其中，第一空白晶体管的控制极与复位信号线电连接，第一空白晶体管的第一极与第一空白节点电连接，第一空白晶体管的第二极与初始信号线电连接；第二空白晶体管的控制极与扫描信号线电连接，第二空白晶体管的第一极与第一空白节点电连接，第二空白晶体管的第二极与第二空白节点电连接；第三空白晶体管的控制极与第一空白节点电连接，第三空白晶体管的第一极与第三空白节点电连接，第三空白晶体管的第二极与第二空白节点电连接；第四空白晶体管的控制极与扫描信号线电连接，第四空白晶体管的第一极浮接，第四空白晶体管的第二极与第三空白节点电连接；第五空白晶体管的控制极与发光信号线电连接，第五空白晶体管的第一极与第一电源线电连接，第五空白晶体管的第二极与第三空白节点电连接；第六空白晶体管的控制极与发光信号线电连接，第六空白晶体管的第一极与第二空白节点电连接，第六空白晶体管的第二极浮接或者与第一电源线电连接；第七空白晶体管的控制极与扫描信号线电连接，第七空白晶体管的第一极与初始信号线电连接，第七空白晶体管的第二极浮接或者与第一电源线电连接；第一空白电容的第一极板与第一空白节点电连接，第一空白电容的第二极板与第一电源线电连接。
在一些可能的实现方式中，还包括：沿列方向延伸的第三电源线、第四电源线、第一扫描时钟信号线、第二扫描时钟信号线和扫描初始信号线；
所述扫描驱动电路包括：沿列方向依次排布的多个级联的第一移位寄存器，每个第一移位寄存器包括：第一扫描晶体管至第八扫描晶体管、第一扫描电容、第二扫描电容、扫描信号输入端、扫描信号输出端、第一扫描时钟信号端、第二扫描时钟信号端、第一扫描电源端和第二扫描电源端；
第一扫描晶体管的控制极与第一扫描时钟信号端电连接，第一扫描晶体管的第一极与扫描信号输入端电连接，第一扫描晶体管的第二极与第一扫描节点电连接；第二扫描晶体管的控制极与第一扫描节点电连接，第二扫描晶体管的第一极与第一扫描时钟信号端电连接，第二扫描晶体管的第二极与第二扫描节点电连接；第三扫描晶体管的控制极与第一扫描时钟信号端电连接，第三扫描晶体管的第一极与第二扫描电源端电连接，第三扫描晶体管的第二极与第二扫描节点电连接；第四扫描晶体管的控制极与第二扫描节点电连接，第四扫描晶体管的第一极与第一扫描电源端电连接，第四扫描晶体管的第二极与扫描信号输出端电连接，第五扫描晶体管的控制极与第三扫描节点电连接，第五扫描晶体管的第一极与扫描信号输出端电连接，第五扫描晶体管的第二极与第二扫描时钟信号端电连接；第六扫描晶体管的控制极与第二扫描节点电连接，第六扫描晶体管的第一极与第一扫描电源端电连接，第六扫描晶体管的第二极与第七扫描晶体管的第一极电连接；第七扫描晶体管的控制极与第二扫描时钟信号端电连接，第七扫描晶体管的第二极与第一扫描节点电连接；第八扫描晶体管的控制极与第二扫描电源端电连接，第八扫描晶体管的第一极与第一扫描节点电连接，第八扫描晶体管的第二极与第三扫描节点电连接；第一扫描电容的第一极板与第一扫描电源端电连接，第一扫描电容的第二极板与第二扫描节点电连接；第二扫描电容的第一极板与扫描信号输出端电连接，第二扫描电容的第二极板与第三扫描节点电连接；
第一级第一移位寄存器的扫描信号输入端与扫描初始信号线电连接，第i-1级第一移位寄存器的扫描信号输出端与第i级第一移位寄存器的扫描信号输入端电连接，所有第一移位寄存器的第一扫描电源端与第三电源线电连接，所述第一移位寄存器的第二扫描电源端与第四电源线电连接，奇数级第一移 位寄存器的第一扫描时钟信号端与第一扫描时钟信号线电连接，奇数级第一移位寄存器的第二扫描时钟信号端与第二扫描时钟信号线电连接，偶数级第一移位寄存器的第一扫描时钟信号端与第二扫描时钟信号线电连接，偶数级第一移位寄存器的第二扫描时钟信号端与第一扫描时钟信号线电连接，第一移位寄存器的扫描信号输出端与扫描信号线电连接，其中，i为大于或等于2的正整数。
在一些可能的实现方式中，还包括：沿列方向延伸的第三电源线、第四电源线、第一发光时钟信号线、第二发光时钟信号线和发光初始信号线；
所述发光驱动电路包括：沿列方向依次排布的多个级联的第二移位寄存器，每个第二移位寄存器包括：第一发光晶体管至第十发光晶体管、第一发光电容至第三发光电容、发光信号输入端、发光信号输出端、第一发光时钟信号端、第二发光时钟信号端、第一发光电源端和第二发光电源端；
第一发光晶体管的控制极与第一发光时钟信号端电连接，第一发光晶体管的第一极与发光信号输入端电连接，第一发光晶体管的第二极与第一发光节点电连接；所述第二发光晶体管的控制极与第一发光节点电连接，所述第二发光晶体管的第一极与第一发光时钟信号端电连接，所述第二发光晶体管的第二极与第二发光节点电连接；所述第三发光晶体管的控制极与第一发光时钟信号端电连接，第三发光晶体管的第一极与第二发光电源端电连接，第三发光晶体管的第二极与第二发光节点电连接；第四发光晶体管的控制极与第二发光时钟信号端电连接，第四发光晶体管的第一极与第一发光节点电连接，第四发光晶体管的第二极与第五发光晶体管的第一极电连接；第五发光晶体管的控制极与第二发光节点电连接，第五发光晶体管的第二极与第一发光电源端电连接；第六发光晶体管的控制极与第二发光节点电连接，第六发光晶体管的第一极与第二发光时钟信号端电连接，第六发光晶体管的第二极与第三发光节点电连接；第七发光晶体管的控制极与第二发光时钟信号端电连接，第七发光晶体管的第一极与第三发光节点电连接，第七发光晶体管的第二极与第四发光节点电连接；第八发光晶体管的控制极与第一发光节点电连接，第八发光晶体管的第一极与第一发光电源端电连接，第八发光晶体管的第二极与第四发光节点电连接；第九发光晶体管的控制极与第四发光节点 电连接，第九发光晶体管的第一极与发光信号输出端电连接，第九发光晶体管的第二极与第一发光电源端电连接；第十发光晶体管的控制极与第一发光节点电连接，第十发光晶体管的第一极与第二发光电源端电连接，第十发光晶体管的第二极与发光信号输出端电连接；第一发光电容的第一极板与第二发光节点电连接，第一发光电容的第二极板与第三发光节点电连接；第二发光电容的第一极板与第一发光节点电连接，第二发光电容的第二极板与第二发光时钟信号端电连接；第三发光电容的第一极板与第四发光节点电连接，第三发光电容的第二极板与第一发光电源端电连接；
第一级第二移位寄存器的发光信号输入端与发光初始信号线电连接，第i-1级第二移位寄存器的发光信号输出端与第i级第二移位寄存器的发光信号输入端电连接，所有第二移位寄存器的第一发光电源端与第三电源线电连接，所述第二移位寄存器的第二发光电源端与第四电源线电连接，奇数级第二移位寄存器的第一发光时钟信号端与第一发光时钟信号线电连接，奇数级第二移位寄存器的第二发光时钟信号端与第二发光时钟信号线电连接，偶数级第二移位寄存器的第一发光时钟信号端与第二发光时钟信号线电连接，偶数级第二移位寄存器的第二发光时钟信号端与第一发光时钟信号线电连接，第二移位寄存器的发光信号输出端与发光信号线电连接，其中，i为大于或等于2的正整数。
在一些可能的实现方式中，所述发光结构层包括：依次叠设在驱动结构层上的第一电极层、像素界定层、发光层和第二电极层；所述第一电极层包括：多个第一电极，所述发光层包括：多个有机发光层，所述第二电极层包括：多个第二电极，每个发光结构包括：第一电极、有机发光层和第二电极；
对于每个像素电路，第六像素晶体管的第二极在衬底基板上的正投影与所述像素电路所连接的发光结构中的第一电极在衬底基板上的正投影不存在重叠区域；
所述驱动结构层还包括：连接电极，所述连接电极位于所述像素电路和发光结构之间，且分别与像素电路中的第六像素晶体管的第二极和发光结构中的第一电极电连接。
在一些可能的实现方式中，所述连接电极包括：第一连接部和第二连接 部；
所述第一连接部设置在所述第二连接部靠近所述衬底基板的一侧，所述第一连接部分别与像素电路中的第六像素晶体管的第二极和所述第二连接部电连接，所述第二连接部与发光结构中的第一电极电连接；
所述第一连接部和所述第二连接部为一体成型结构，或者所述第一连接部为金属电极，所述第二连接部为透明电极。
在一些可能的实现方式中，所述显示基板还包括：封装层和隔垫物；
所述封装层设置在发光结构层远离衬底基板的一侧，所述隔垫物设置在所述封装层远离衬底基板的一侧。
在一些可能的实现方式中，当所述第一连接部和所述第二连接部为一体成型结构时，所述驱动结构层包括：依次叠设在所述衬底基板上的第一绝缘层、半导体层、第二绝缘层、第一金属层、第三绝缘层、第二金属层、第四绝缘层、第三金属层、第五绝缘层、第一平坦层、第四金属层、第二平坦层、第五金属层和第三平坦层；
所述半导体层包括：多个像素晶体管的有源层、多个空白晶体管的有源层、多个扫描晶体管的有源层和多个发光晶体管的有源层；所述第一金属层包括：发光信号线、扫描信号线、复位信号线、第一像素电容的第一极板，第一扫描电容的第二极板、第二扫描电容的第二极板、第一发光电容的第一极板、第二发光电容的第二极板、第三发光电容的第三极板、多个像素晶体管的控制极、多个空白晶体管的控制极、多个扫描晶体管的控制极和多个发光晶体管的控制极；所述第二金属层包括：初始信号线，第一像素电容的第二极板、第一扫描电容的第一极板、第二扫描电容的第二极板、第一发光电容的第二极板、第二发光电容的第二极板和第三发光电容的第二极板；所述第三金属层包括：第三电源线、第四电源线、第一扫描时钟信号线、第二扫描时钟信号线、第一发光时钟信号线、第二发光时钟信号线、扫描初始信号线和发光初始信号线、多个像素晶体管的第一极和第二极、多个空白晶体管的第一极和第二极、多个扫描晶体管的第一极和第二极以及多个发光晶体管的第一极和第二极；所述第四金属层包括：数据信号线和第一电源线；所述第五金属层包括：连接电极；
所述第一电源线在衬底基板上的正投影与所述第六像素电容在衬底基板上的正投影至少部分重叠。
在一些可能的实现方式中，当所述第一连接部为金属电极，所述第二连接部为透明电极时，所述驱动结构层包括：依次叠设在所述衬底基板上的第一绝缘层、半导体层、第二绝缘层、第一金属层、第三绝缘层、第二金属层、第四绝缘层、第三金属层、第五绝缘层、第一平坦层、第四金属层、第二平坦层、第五金属层、透明导电层和第三平坦层；
所述半导体层包括：多个像素晶体管的有源层、多个空白晶体管的有源层、多个扫描晶体管的有源层和多个发光晶体管的有源层；所述第一金属层包括：发光信号线、扫描信号线、复位信号线、第一像素电容的第一极板，第一扫描电容的第二极板、第二扫描电容的第二极板、第一发光电容的第一极板、第二发光电容的第二极板、第三发光电容的第三极板、多个像素晶体管的控制极、多个空白晶体管的控制极、多个扫描晶体管的控制极和多个发光晶体管的控制极；所述第二金属层包括：初始信号线，第一像素电容的第二极板、第一扫描电容的第一极板、第二扫描电容的第二极板、第一发光电容的第二极板、第二发光电容的第二极板和第三发光电容的第二极板；所述第三金属层包括：第三电源线、第四电源线、第一扫描时钟信号线、第二扫描时钟信号线、第一发光时钟信号线、第二发光时钟信号线、扫描初始信号线和发光初始信号线、多个像素晶体管的第一极和第二极、多个空白晶体管的第一极和第二极、多个扫描晶体管的第一极和第二极以及多个发光晶体管的第一极和第二极；所述第四金属层包括：数据信号线和第一电源线；所述第五金属层包括：第一连接部，所述透明导电层包括：第二连接部；
所述第一电源线在衬底基板上的正投影与所述第六像素电容在衬底基板上的正投影至少部分重叠。
第二方面，本公开还提供了一种显示装置，包括上述显示基板。
第三方面，本公开还提供一种显示基板的制作方法，设置为制作上述显示基板，所述方法包括：
提供一衬底基板；
在衬底基板上形成M行扫描信号线和M行发光信号线以及位于显示区 的驱动结构层；所述驱动结构层包括：沿列方向延伸的像素电路阵列和驱动电路阵列；所述像素电路阵列和所述驱动电路阵列沿行方向依次排布；所述像素电路阵列包括：M行N列像素电路，第i行像素电路与第i行扫描信号线和第i行发光信号线电连接，1≤i≤M；所述驱动电路阵列包括：至少一个扫描驱动电路和至少一个发光驱动电路，所述扫描驱动电路设置为向所述扫描信号线提供驱动信号，所述发光驱动电路设置为向所述发光信号线提供驱动信号；
在驱动结构层上形成发光结构层；所述发光结构层包括：M行N列发光结构，像素电路和发光结构一一对应，且与对应的发光结构电连接。
在一些可能的实现方式中，在衬底基板上形成位于显示区的驱动结构层包括：
在衬底基板上依次形成第一绝缘层、半导体层、第二绝缘层、第一金属层、第三绝缘层、第二金属层、第四绝缘层、第三金属层、第五绝缘层、第一平坦层、第四金属层、第二平坦层、第五金属层和第三平坦层；
或者，在所述衬底基板上依次形成第一绝缘层、半导体层、第二绝缘层、第一金属层、第三绝缘层、第二金属层、第四绝缘层、第三金属层、第五绝缘层、第一平坦层、第四金属层、第二平坦层、第五金属层、透明导电层和第三平坦层；
所述在驱动结构层上形成发光结构层包括：
在驱动结构层上依次形成第一电极层、像素界定层、发光层和第二电极层；
所述在驱动结构层上形成发光结构层之后，所述方法还包括：
在发光结构层上形成封装层和隔垫物。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方 案的限制。
图1为一种显示基板的结构示意图；
图2为本公开实施例提供的显示基板的结构示意图；
图3为图1提供显示基板中的像素电路与图2提供的显示基板中的像素电路的尺寸对比图一；
图4为图1提供显示基板中的像素电路与图2提供的显示基板中的像素电路的尺寸对比图二
图5为一种示例性实施例提供的显示区的结构示意图；
图6为一种示例性实施例提供的显示基板的截面图；
图7为一种示例性实施例提供的显示基板的结构示意图一；
图8为图7沿A-A’方向的截面图；
图9为一种示例性实施例提供的显示基板的结构示意图二；
图10为图9沿A-A’方向的截面图；
图11为一种示例性实施例提供的显示基板的结构示意图三；
图12为图11沿A-A’方向的截面图；
图13为一种示例性实施例提供的显示基板的结构示意图四；
图14为图13沿A-A’方向的截面图；
图15为一种示例性实施例提供的显示基板的结构示意图五；
图16为图15沿A-A’方向的截面图；
图17为一种示例性实施例提供的显示基板的结构示意图六；
图18为图17沿A-A’方向的截面图；
图19为一种示例性实施例提供的像素电路的等效电路图；
图20为图19提供的一种像素电路的工作时序图；
图21为一种示例性实施例提供的空白电路的结构示意图；
图22为一种示例性实施例提供的扫描驱动电路的结构示意图；
图23为一种示例性实施例提供的第一移位寄存器的等效电路图；
图24为一种示例性实施例提供的第一移位寄存器的工作时序图；
图25为一种示例性实施例提供的发光驱动电路的结构示意图；
图26为一种示例性实施例提供的第二移位寄存器的等效电路图；
图27为一种示例性实施例提供的第二移位寄存器的工作时序图；
图28为一种示例性实施例提供的显示基板的截面图一；
图29为一种示例性实施例提供的显示基板的截面图二。
具体实施方式
本公开描述了多个实施例，但是该描述是示例性的，而不是限制性的，并且对于本领域的普通技术人员来说，在本公开所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在具体实施方式中进行了讨论，但是所公开的特征的许多其它组合方式也是可能的。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
本公开包括并设想了与本领域普通技术人员已知的特征和元件的组合。本公开已经公开的实施例、特征和元件也可以与任何常规特征或元件组合，以形成由权利要求限定的技术方案。任何实施例的任何特征或元件也可以与来自其它技术方案的特征或元件组合，以形成另一个由权利要求限定的技术方案。因此，应当理解，在本公开中示出和/或讨论的任何特征可以单独地或以任何适当的组合来实现。因此，除了根据所附权利要求及其等同替换所做的限制以外，实施例不受其它限制。此外，可以在所附权利要求的保护范围内进行各种修改和改变。
除非另外定义，本公开公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排 除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述的对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示基板的结构示意图。如图1所示，显示基板包括显示区和非显示区。显示基板可以包括设置在基板上，且位于非显示区的时序控制器、数据驱动电路、扫描驱动电路、发光驱动电路和像素阵列，显示基板还可以包括多个扫描信号线(G1到Gm)、多个数据信号线(D1到Dn)、多个发光信号线(E1到Em)和多个子像素PA。
在一种示例性实施例中，时序控制器可以将适合于数据驱动电路的规格 的灰度值和控制信号提供到数据驱动电路，可以将适合于扫描驱动电路的规格的时钟信号、扫描起始信号等提供到扫描驱动电路，可以将适合于发光驱动电路的规格的时钟信号、发射停止信号等提供到发光驱动电路。数据驱动电路可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动电路可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动电路可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线G1、G2、G3、……和Gm的扫描信号。例如，扫描驱动电路可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线G1至Gm。例如，扫描驱动电路可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动电路可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Em的发射信号。例如，发光驱动电路可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Em。例如，发光驱动电路可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发光停止信号传输到下一级电路的方式产生发光信号。每个子像素可以连接到对应的数据信号线、对应的扫描信号线和对应的发光信号线。
在一种示例性实施例中，每个子像素包括：像素电路和发光结构。像素电路与发光结构电连接，设置为驱动发光结构发光。
在一种显示基板中，发光驱动电路和扫描驱动电路设置在非显示区，使得显示基板无法实现窄边框。
图2为本公开实施例提供的显示基板的结构示意图。如图2所示，本公开实施例提供的一种显示基板可以包括：显示区AA和非显示区。显示基板包括：衬底基板10以及依次叠设在衬底基板10上，且位于显示区AA的驱动结构层20和发光结构层30。显示基板还包括：M行扫描信号线和M行发光信号线。驱动结构层20包括：沿列方向延伸的像素电路200阵列100和驱动电路阵列200，像素电路阵列100和驱动电路阵列200沿行方向依次排布。 发光结构层30包括：M行N列发光结构。
像素电路阵列可以包括：M行N列像素电路。像素电路和发光结构一一对应，且与对应的发光结构电连接，第i行像素电路与第i行扫描信号线和第i行发光信号线电连接，1≤i≤M。驱动电路阵列包括：至少一个扫描驱动电路和至少一个发光驱动电路，扫描驱动电路设置为向扫描信号线提供驱动信号，发光驱动电路设置为向发光信号线提供驱动信号。
在一种示例性实施例中，衬底基板10可以为刚性基底或柔性基底，其中，刚性基底可以为但不限于玻璃、金属萡片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在一种示例性实施例中，扫描信号线和发光信号线可以设置在显示区中。
在一种示例性实施例中，行方向与列方向相交指的是行方向与列方向之间的夹角约为70度至90度。行方向和列方向可以位于同一平面内。例如，行方向可以为行方向，平行于扫描线的延伸方向；列方向可以为列方向，平行于数据线的延伸方向。
在一种示例性实施例中，像素电路和发光结构可以构成子像素。子像素可以为红色(R)子像素、绿色(G)子像素、蓝色(B)子像素、白色子像素中的任一种，本公开在此不做限定。当显示面板中包括红色(R)子像素，绿色(G)子像素和蓝色(B)子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列。当显示面板中包括红色(R)子像素，绿色(G)子像素、蓝色(B)子像素和白色子像素时，四个子像素可以采用水平并列、竖直并列或阵列方式排列，本公开在此不做限定。
在一种示例性实施例中，发光结构可以是有机电致发光二极管(OLED)。
图3为图1提供显示基板中的像素电路与图2提供的显示基板中的像素电路的尺寸对比图一，图4为图1提供显示基板中的像素电路与图2提供的显示基板中的像素电路的尺寸对比图二。如图3和图4，图2提供的显示基板与图1提供的显示基板相比，发光结构保持不变，为了可以在显示区中可 以设置驱动电路阵列，图2中像素电路是对图1中的像素电路进行了等比例压缩的。其中，等比例压缩可以包括：沿行方向等比例压缩或者沿行方向和列方向进行等比例压缩。图3是图2提供的像素电路PE2是对图1提供的显示基板中的像素电路PE1进行了行方向和列方向等比例压缩后形成的。L3＝L1×k，L4＝L2×k。图4是图2提供的像素电路PE2是对图1提供的显示基板中的像素电路PE1进行了行方向等比例压缩后形成的。L3＝L1×k，L4＝L2。其中，L1为PE1沿行方向的长度，L2为PE1沿列方向的长度，L3为PE2沿行方向的长度，L4为PE2沿列方向的长度，k为压缩比例，0<k≤1。
本公开实施例提供的显示基板包括：显示区和非显示区，显示基板包括：衬底基板以及依次叠设在衬底基板上，且位于显示区的驱动结构层和发光结构层，显示基板还包括：M行扫描信号线和M行发光信号线；发光结构层包括：M行N列发光结构，驱动结构层包括：沿列方向延伸的像素电路阵列和驱动电路阵列；像素电路阵列和驱动电路阵列沿行方向依次排布；像素电路阵列包括：M行N列像素电路，像素电路和发光结构一一对应，且与对应的发光结构电连接，第i行像素电路与第i行扫描信号线和第i行发光信号线电连接，1≤i≤M；驱动电路阵列包括：至少一个扫描驱动电路和至少一个发光驱动电路，扫描驱动电路设置为向扫描信号线提供驱动信号，发光驱动电路设置为向发光信号线提供驱动信号。本公开实施例将驱动电路阵列设置在显示区，减少了非显示区的宽度，可以实现窄边框。
在一种示例性实施例中，每个像素电路的面积可以相同，保证了每个像素电路的负载相同，可以较大程度避免异常显示的风险。
在一些示例性实施例中，图5为一种示例性实施例提供的显示区的结构示意图。如图5所示，显示区包括弧形显示边界，显示区可以包括：相对设置的第一边界AL1和第二边界AL2及相对设置的第三边界AL3和第四边界AL4。第一边界AL1的长度大于第三边界AL3的长度。其中，第一边界AL1和第二边界AL2沿列方向延伸，且为非直线型结构，弧形显示边界位于第一边界AL1和第二边界AL2中，第三边界AL3和第四边界AL4沿行方向延伸，且为直线型结构。
在一种示例性实施例中，靠近弧形显示边界的至少部分像素电路呈弧形 状排布。
在一种示例性实施例中，显示区AA的形状可以为圆角矩形，本公开对此不作任何限定。
图6为一种示例性实施例提供的显示基板的截面图。如图6所示，在一些示例性实施例中，驱动结构层还包括：空白电路阵列300。空白电路阵列设置在像素电路阵列100和驱动电路阵列200之间。其中，空白电路阵列包括：多个空白电路，空白电路与扫描信号线和发光信号线电连接。本公开设置空白电路阵列可以充分保证像素电路驱动显示的均一性。
在一种示例性实施例中，显示基板可以包括：M行K列空白电路，第i行空白电路与第i行扫描信号线和第i行发光信号线电连接。
在一种示例性实施例中，K的取值可以根据显示基板的尺寸以及各个信号线的信号确定。
图7为一种示例性实施例提供的显示基板的结构示意图一，图8为图7沿A-A’方向的截面图。如图7和图8所示，一种示例性实施例中，像素电路阵列包括：沿行方向依次排布的第二像素电路阵列PR2、第一像素电路阵列PR1和第三像素电路阵列PR3。驱动电路阵列包括：沿行方向排布的第一驱动电路阵列GR1和第二驱动电路阵列GR2。其中，第一驱动电路阵列GR1位于第一像素电路阵列PR1和第二像素电路阵列PR2之间，第二驱动电路阵列GR2位于第一像素电路阵列PR1和第三像素电路阵列PR3之间。
在一种示例性实施例中，第一像素电路阵列可以包括：M行N1列像素电路，第二像素电路阵列可以包括：M行N2列像素电路，第三像素电路阵列可以包括：M行N3列像素电路，N1+N2+N3＝N，其中，N1、N2和N3的取值根据实际需求确定。
在一种示例性实施例中，第一驱动电路阵列和第二驱动电路阵列中的多个驱动电路可以呈直线型排布。
在一种示例性实施例中，第一驱动电路阵列和第二驱动电路阵列可以包括：扫描驱动电路和发光驱动电路；位于同一驱动电路阵列中的扫描驱动电路和发光驱动电路沿行方向排布，或者，第一驱动电路阵列包括：扫描驱动 电路，第二驱动电路阵列包括：发光驱动电路，或者，第一驱动电路阵列包括：发光驱动电路，第二驱动电路阵列包括：扫描驱动电路。
图9为一种示例性实施例提供的显示基板的结构示意图二，图10为图9沿A-A’方向的截面图。如图9和图10所示，一种示例性实施例中，当驱动结构层还包括：空白电路阵列时，空白电路阵列包括：第一空白电路阵列BR1、第二空白电路阵列BR2、第三空白电路阵列BR3和第四空白电路阵列BR4。其中，第一空白电路阵列BR1位于第二像素电路阵列PR2和第一驱动电路阵列GR1之间，第二空白电路阵列BR2位于第一驱动电路阵列GR1和第一像素电路阵列PR1之间，第三空白电路阵列BR4位于第一像素电路阵列PR1和第二驱动电路阵列GR2，第四空白电路阵列BR4位于第二驱动电路阵列GR2和第三像素电路阵列PR3之间。
在一种示例性实施例中，第一空白电路阵列、第二空白电路阵列、第三空白电路阵列和第四空白电路阵列的多个空白电路可以呈直线型排布
图11为一种示例性实施例提供的显示基板的结构示意图三，图12为图11沿A-A’方向的截面图。如图11和图12所示，一种示例性实施例中，驱动电路阵列包括：沿行方向依次排布的第一驱动电路阵列GR1和第二驱动电路阵列GR2。其中，第一驱动电路阵列GR1设置在像素电路阵列PR靠近显示区的第一边界的一侧，第二驱动电路阵列GR2设置在像素电路阵列PR靠近显示区的第二边界的一侧。
一种示例性实施例中，第一驱动电路阵列中靠近弧形显示边界的至少部分驱动电路呈弧形状排布。
一种示例性实施例中，第二驱动电路阵列中靠近弧形显示边界的至少部分驱动电路呈弧形状排布。
在一种示例性实施例中，第一驱动电路阵列和第二驱动电路阵列可以包括：扫描驱动电路和发光驱动电路；位于同一驱动电路阵列中的扫描驱动电路和发光驱动电路沿行方向排布，或者，第一驱动电路阵列包括：扫描驱动电路，第二驱动电路阵列包括：发光驱动电路，或者，第一驱动电路阵列包括：发光驱动电路，第二驱动电路阵列包括：扫描驱动电路。
图13为一种示例性实施例提供的显示基板的结构示意图四，图14为图 13沿A-A’方向的截面图。如图13和图14所示，一种示例性实施例中，当驱动结构层还包括：空白电路阵列时，空白电路阵列包括：第一空白电路阵列BR1和第二空白电路阵列BR2。其中，第一空白电路阵列BR1位于第一驱动电路阵列GR1和像素电路阵列PR之间，第二空白电路阵列BR2位于像素电路阵列PR和第二驱动电路阵列GR2之间。
一种示例性实施例中，第一空白电路阵列中靠近弧形显示边界的至少部分空白电路呈弧形状排布。
一种示例性实施例中，第二空白电路阵列中靠近弧形显示边界的至少部分空白电路呈弧形状排布。
图15为一种示例性实施例提供的显示基板的结构示意图五，图16为图15沿A-A’方向的截面图。如图15和图16所示，像素电路阵列包括：沿行方向依次排布的第一像素电路阵列PR1和第二像素电路阵列PR2。驱动电路阵列包括：沿行方向依次排布的第一驱动电路阵列GR1、第二驱动电路阵列GR2和第三驱动电路阵列GR3。其中，第一像素电路阵列PR1位于第一驱动电路阵列GR1和第二驱动电路阵列GR2之间，第二像素电路阵列PR2位于第二驱动电路阵列GR2和第三驱动电路阵列GR3之间。
一种示例性实施例中，第一像素电路阵列包括：M行N4列像素电路，第二像素电路阵列包括：M行N5列像素电路，N4+N5＝N。
一种示例性实施例中，第一驱动电路阵列中靠近弧形显示边界的至少部分驱动电路呈弧形状排布。
一种示例性实施例中，第三驱动电路阵列中靠近弧形显示边界的至少部分驱动电路呈弧形状排布。
一种示例性实施例中，第二驱动电路阵列中多个驱动电路呈直线型排布。
一种示例性实施例中，第一驱动电路阵列和第三驱动电路阵列可以包括：扫描驱动电路，第二驱动电路阵列可以包括：发光驱动电路，本公开将发光驱动电路置于显示中间，采用单边驱动的方式，有利于收窄显示产品的左右边框；
图17为一种示例性实施例提供的显示基板的结构示意图六，图18为图 17沿A-A’方向的截面图。如图17和图18所示，当驱动结构层还包括：空白电路阵列时，空白电路阵列包括：第一空白电路阵列BR1、第二空白电路阵列BR2、第三空白电路阵列BR3和第四空白电路阵列BR4。其中，第一空白电路阵列BR1位于第一驱动电路阵列GR1和第一像素电路阵列PR1之间，第二空白电路阵列BR2位于第一像素电路阵列PR1和第二驱动电路阵列GR2之间，第三空白电路阵列BR3位于第二驱动电路阵列GR2和第二像素电路阵列PR2之间，第四空白电路阵列BR4位于第二像素电路阵列PR2和第三驱动电路阵列GR3之间。
一种示例性实施例中，第一空白电路阵列中靠近弧形显示边界的至少部分空白电路呈弧形状排布。
一种示例性实施例中，第二空白电路阵列中的多个空白电路呈直线型排布。
一种示例性实施例中，第三空白电路阵列中的多个空白电路呈直线型排布。
一种示例性实施例中，第四空白电路阵列中靠近弧形显示边界的至少部分空白电路呈弧形状排布。
一种示例性实施例中，显示基板还可以包括：沿列方向延伸的第一电源线、第二电源线、第三电源线、第四电源线、数据信号线、第一扫描时钟信号线、第二扫描时钟信号线、第一发光时钟信号线、第二发光时钟信号线、扫描初始信号线和发光初始信号线以及沿行方向延伸的复位信号线和初始信号线。
在一种示例性实施例中，发光结构与第二电源线电连接。
在一种示例性实施例中，第一电源线和第三电源线持续提供高电平信号，第二电源线和第三电源线持续提供低电平信号。
在一种示例性实施例中，像素电路可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C结构。
图19为一种示例性实施例提供的像素电路的等效电路图。如图19所示，一种示例性实施例提供的像素电路可以包括：第一像素晶体管PT1至第七像 素晶体管PT7和第一像素电容PC。其中，第一像素晶体管PT1的控制极与复位信号线RESET电连接，第一像素晶体管PT1的第一极与第一像素节点PN1电连接，第一像素晶体管PT1的第二极与初始信号线INIT电连接。第二像素晶体管PT2的控制极与扫描信号线GATE电连接，第二像素晶体管PT2的第一极与第一像素节点PN1电连接，第二像素晶体管PT2的第二极与第二像素节点PN2电连接。第三像素晶体管PT3的控制极与第一像素节点PN1电连接，第三像素晶体管PT3的第一极与第三像素节点PN3电连接，第三像素晶体管PT3的第二极与第二像素节点PN2电连接。第四像素晶体管PT4的控制极与扫描信号线G电连接，第四像素晶体管PT4的第一极与数据信号线D电连接，第四像素晶体管PT4的第二极与第三像素节点PN3电连接。第五像素晶体管PT5的控制极与发光信号线E电连接，第五像素晶体管PT5的第一极与第一电源线VDD电连接，第五像素晶体管PT5的第二极与第三像素节点PN3电连接。第六像素晶体管PT6的控制极与发光信号线E电连接，第六像素晶体管PT6的第一极与第二像素节点PN2电连接，第六像素晶体管PT6的第二极与发光结构L电连接。第七像素晶体管PT7的控制极与扫描信号线G电连接，第七像素晶体管PT7的第一极与初始信号线INIT电连接，第七像素晶体管PT7的第二极与发光结构L电连接。第一像素电容PC1的第一极板PC11与第一像素节点PN1电连接，第一像素电容PC1的第二极板PC12与第一电源线VDD电连接。
在一种示例性实施例中，第一像素晶体管PT1、第二像素晶体管PT2、第四像素晶体管PT4至第七像素晶体管PT7可以为开关晶体管。第三像素晶体管PT3可以为驱动晶体管。
在一种示例性实施例中，第一像素晶体管PT1到第七像素晶体管PT7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点。在示例性实施方式中，可以将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个 显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现高分辨率(Pixel Per Inch，简称PPI)，低频驱动，可以降低功耗，可以提高显示品质。
在一种示例性实施例中，第一像素晶体管PT1到第七像素晶体管PT7可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。在一种示例性实施例中，第一像素晶体管PT1到第七像素晶体管PT7可以包括P型晶体管和N型晶体管。
图20为图19提供的一种像素电路的工作时序图。下面以第一像素晶体管PT1到第七像素晶体管PT7为P型晶体管为例，通过图19示例的像素电路的工作过程说明本公开示例性实施例，图19中的像素电路包括7个晶体管(第一像素晶体管T1到第七像素晶体管T7)、1个电容(PC1)、7个信号线(数据信号线D、扫描信号线G、发光信号线E、初始信号线INIT和复位信号线RESET)和两个电源线(第一电源线VDD和第二电源线VSS)。像素电路的工作过程可以包括：
第一阶段A1，称为复位阶段，复位信号线RESET的信号为低电平信号，扫描信号线G和发光信号线E的信号为高电平信号。复位信号线RESET的信号为低电平信号，使第一像素晶体管T1导通，初始信号线INIT的信号提供至第一像素节点PN1，对第一像素电容PC1进行初始化，清除第一像素电容PC1中原有数据电压。扫描信号线G和发光信号线E的信号为高电平信号，使第二像素晶体管T2、第四像素晶体管T4、第五像素晶体管T5、第六像素晶体管T6和第七像素晶体管T7断开，此阶段发光结构L不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，扫描信号线G的信号为低电平信号，复位信号线RESET和发光信号线E的信号为高电平信号，数据信号线D输出数据电压。此阶段由于第一像素电容PC1的第二端为低电平，因此第三像素晶体管T3导通。扫描信号线G的信号为低电平信号使第二像素晶体管T2、第四像素晶体管T4和第七像素晶体管T7导通。第二像素晶体管T2和第四像素晶体管T4导通使得数据信号线D输出的数据电压经过第三像素节点N3、导通的第三像素晶体管T3、第二像素节点PN2、 导通的第二像素晶体管T2提供至第一像素节点PN1，并将数据信号线D输出的数据电压与第三像素晶体管T3的阈值电压之差充入第一像素电容PC1，第一像素节点PN1的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三像素晶体管T3的阈值电压。第七像素晶体管T7导通使得初始信号线INIT的初始电压提供至发光结构L的第一极，对发光结构L的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。复位信号线RESET的信号为高电平信号，使第一像素晶体管T1断开。发光信号线E的信号为高电平信号，使第五像素晶体管T5和第六像素晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E的信号为低电平信号，扫描信号线G和复位信号线RESET的信号为高电平信号。发光信号线E的信号为低电平信号，使第五像素晶体管T5和第六像素晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五像素晶体管T5、第三像素晶体管T3和第六像素晶体管T6向发光结构L的第一极提供驱动电压，驱动发光结构L发光。
在像素电路驱动过程中，流过第三像素晶体管T3(驱动像素晶体管)的驱动电流由其控制极和第一极之间的电压差决定。由于第一像素节点PN1的电压为Vdata-|Vth|，因而第三像素晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三像素晶体管T3的驱动电流，也就是驱动发光结构L的驱动电流，K为常数，Vgs为第三像素晶体管T3的控制极和第一极之间的电压差，Vth为第三像素晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
图21为一种示例性实施例提供的空白电路的结构示意图。如图21所示，一种示例性实施例提供的空白电路包括：第一空白晶体管BT1至第七空白晶体管BT7和第一空白电容BC1。其中，第一空白晶体管BT1的控制极与复位信号线RESET电连接，第一空白晶体管BT1的第一极与第一空白节点BN1电连接，第一空白晶体管BT1的第二极与初始信号线INIT电连接。第二空白晶体管BT2的控制极与扫描信号线G电连接，第二空白晶体管BT2的第 一极与第一空白节点BN1电连接，第二空白晶体管BT2的第二极与第二空白节点BN2电连接。第三空白晶体管BT3的控制极与第一空白节点BN1电连接，第三空白晶体管BT3的第一极与第三空白节点BN3电连接，第三空白晶体管BT3的第二极与第二空白节点BN2电连接。第四空白晶体管BT4的控制极与扫描信号线G电连接，第四空白晶体管BT4的第一极浮接，第四空白晶体管BT4的第二极与第三空白节点BN3电连接。第五空白晶体管BT5的控制极与发光信号线E电连接，第五空白晶体管BT5的第一极与第一电源线VDD电连接，第五空白晶体管BT5的第二极与第三空白节点BN3电连接。第六空白晶体管BT6的控制极与发光信号线E电连接，第六空白晶体管BT6的第一极与第二空白节点BN2电连接，第六空白晶体管BT6的第二极浮接或者与第一电源线电连接。第七空白晶体管BT7的控制极与扫描信号线G电连接，第七空白晶体管BT7的第一极与初始信号线INIT电连接，第七空白晶体管BT7的第二极与第六空白晶体管BT6的第二极电连接。第一空白电容BC1的第一极板BC11与第一空白节点BN1电连接，第一空白电容BC1的第二极板BC12与第一电源线VDD电连接。图21是以第六空白晶体管BT6的第二极浮接为例进行说明的。
在一种示例性实施例中，第一空白晶体管BT1至第七空白晶体管BT7可以为开关晶体管。第一空白晶体管BT1到第七空白晶体管BT7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点。在示例性实施方式中，可以将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现高分辨率(Pixel Per Inch，简称PPI)，低频驱动，可以降低功耗，可以提高显示品质。
图22为一种示例性实施例提供的扫描驱动电路的结构示意图，图23为一种示例性实施例提供的第一移位寄存器的等效电路图，图24为一种示例性 实施例提供的第一移位寄存器的工作时序图。如图22至24所示，一种示例性实施例提供的扫描驱动电路可以包括：沿列方向依次排布的多个级联的第一移位寄存器GOA。每个第一移位寄存器GOA包括：第一扫描晶体管GT1至第八扫描晶体管GT8、第一扫描电容GC1、第二扫描电容GC2、扫描信号输入端GIN、扫描信号输出端GOUT、第一扫描时钟信号端GCK1、第二扫描时钟信号端GCK2、第一扫描电源端GV1和第二扫描电源端GV2。
第一扫描晶体管GT1的控制极与第一扫描时钟信号端GCK1电连接，第一扫描晶体管GT1的第一极与扫描信号输入端GIN电连接，第一扫描晶体管GT1的第二极与第一扫描节点GN1电连接。第二扫描晶体管GT2的控制极与第一扫描节点GN1电连接，第二扫描晶体管GT2的第一极与第一扫描时钟信号端GCK1电连接，第二扫描晶体管GT2的第二极与第二扫描节点GN2电连接。第三扫描晶体管GT3的控制极与第一扫描时钟信号端GCK1电连接，第三扫描晶体管GT3的第一极与第二扫描电源端GV2电连接，第三扫描晶体管GT3的第二极与第二扫描节点GN2电连接。第四扫描晶体管GT4的控制极与第二扫描节点GN2电连接，第四扫描晶体管GT4的第一极与第一扫描电源端电连接，第四扫描晶体管GT4的第二极与扫描信号输出端GOUT电连接，第五扫描晶体管GT5的控制极与第三扫描节点电连接，第五扫描晶体管GT5的第一极与扫描信号输出端GOUT电连接，第五扫描晶体管GT5的第二极与第二扫描时钟信号端GCK2电连接。第六扫描晶体管GT6的控制极与第二扫描节点GN2电连接，第六扫描晶体管GT6的第一极与第一扫描电源端GV1电连接，第六扫描晶体管GT6的第二极与第七扫描晶体管GT7的第一极电连接。第七扫描晶体管GT7的控制极与第二扫描时钟信号端GCK2电连接，第七扫描晶体管GT7的第二极与第一扫描节点GN1电连接。第八扫描晶体管GT8的控制极与第二扫描电源端GV2电连接，第八扫描晶体管GT8的第一极与第一扫描节点GN1电连接，第八扫描晶体管GT8的第二极与第三扫描节点GN3电连接。第一扫描电容GC1的第一极板GC11与第一扫描电源端GV1电连接，第一扫描电容GC1的第二极板GC12与第二扫描节点GN2电连接。第二扫描电容GC2的第一极板GC21与扫描信号输出端GOUT电连接，第二扫描电容GC2的第二极板GC22与第三扫描节点GN3电连接。
第一级第一移位寄存器GOA(1)的扫描信号输入端GIN与扫描初始信号线GSTV电连接，第i-1级第一移位寄存器GOA(i-1)的扫描信号输出端GOUT与第i级第一移位寄存器GOA(i)的扫描信号输入端GIN电连接，所有第一移位寄存器的第一扫描电源端GV1与第三电源线VGH电连接，所述第一移位寄存器的第二扫描电源端GV2与第四电源线VGL电连接，奇数级第一移位寄存器的第一扫描时钟信号端GCK1与第一扫描时钟信号线GCK电连接，奇数级第一移位寄存器的第二扫描时钟信号端GCK2与第二扫描时钟信号线GCB电连接，偶数级第一移位寄存器的第一扫描时钟信号端GCK1与第二扫描时钟信号线GCB电连接，偶数级第一移位寄存器的第二扫描时钟信号端GCK2与第一扫描时钟信号线GCK电连接，第一移位寄存器的扫描信号输出端与扫描信号线电连接，其中，i为大于或等于2的正整数。
在一种示例性实施例中，第一扫描晶体管GT1至第八扫描晶体管GT8可以为开关晶体管。第一扫描晶体管GT1到第八扫描晶体管GT8可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点。在示例性实施方式中，可以将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现高分辨率(Pixel Per Inch，简称PPI)，低频驱动，可以降低功耗，可以提高显示品质。
在一种示例性实施例中，第一移位寄存器的个数可以为M。
下面以第一扫描晶体管GT1至第八扫描晶体管GT8为P型晶体管为例，通过图23示例的第一移位寄存器的工作过程结合图24说明本公开示例性实施例。第一移位寄存器的工作过程可以包括以下阶段：
在输入阶段t1，第一扫描时钟信号线GCK1的信号为低电平信号，第二扫描时钟信号线GCK2的信号为高电平信号，扫描信号输入端GIN的信号为低电平信号。由于第一扫描时钟信号端GCK1的信号为低电平信号，第一扫 描晶体管GT1导通，扫描信号输入端GIN的信号经由第一扫描晶体管GT1传输至第一扫描节点GN1。由于第八扫描晶体管GT8的信号接收第二扫描电源端GV2的低电平信号，从而第八扫描晶体管GT8处于开启状态。第三扫描节点GN3的电平信号可以控制第五扫描晶体管GT5导通，第二扫描时钟信号端GCK2的信号经由第五扫描晶体管GT5传输至扫描信号输出端GOUT，即在输入阶段t1，扫描信号输出端GOUT为高电平信号的第二扫描时钟信号端GCK2的信号。另外，由于第一扫描时钟信号端GCK1的信号为低电平信号，第三扫描晶体管GT3导通，第二扫描电源端GV2的低电平信号经由第三扫描晶体管GT3传输至第二扫描节点GN2。此时，第四扫描晶体管GT4和第六扫描晶体管GT6均导通。由于第二扫描时钟信号端GCK2的信号为高电平信号，第七扫描晶体管GT7截止。
在输出阶段t2，第一扫描时钟信号端GCK1的信号为高电平信号，第二扫描时钟信号端GCK2的信号为低电平信号，扫描信号输入端GIN的信号为高电平信号。第五扫描晶体管GT5导通，第二扫描时钟信号端GCK2的信号经由第五扫描晶体管GT5作为扫描信号输出端GOUT的信号。在输出阶段t2，第二扫描电容GC2的连接扫描信号输出端GOUT的一端的电平信号变为第二扫描电源端GV2的信号，由于第二扫描电容GC2的自举作用，第八扫描晶体管GT8截止，第五扫描晶体管GT5可以更好地打开，信号输出端OUT的信号为低电平信号。另外，第一扫描时钟信号端GCK1的信号为高电平信号，从而第一扫描晶体管GT1和第三扫描晶体管GT3均截止。第二扫描晶体管GT2导通，第一扫描时钟信号端GCK1的高电平信号经由第二扫描晶体管GT2传输至第二扫描节点GN2，由此，第四扫描晶体管GT4和第六扫描晶体管GT6均截止。由于第二扫描时钟信号端GCK2的信号为低电平信号，第七扫描晶体管GT7导通。
在缓冲阶段t3，第一扫描时钟信号端GCK1和第二扫描时钟信号端GCK2的信号均为高电平信号，扫描信号输入端GIN的信号为高电平信号，第五扫描晶体管GT5导通，第二扫描时钟信号端GCK2的信号经由第五扫描晶体管GT5作为扫描信号输出端GOUT的信号，此时，扫描信号输出端GOUT为高电平信号。由于第二扫描电容GC2的自举作用，第一扫描节点GN1的电 平信号变为VGL-VthN1。另外，第一扫描时钟信号端GCK1的信号为高电平信号，从而第一扫描晶体管GT1和第三扫描晶体管GT3均截止，第八扫描晶体管GT8导通，第二扫描晶体管GT2导通，第一扫描时钟信号端GCK1的高电平信号经由第二扫描晶体管GT2传输至第二扫描节点GN2，由此，第四扫描晶体管GT4和第六扫描晶体管GT6均截止。由于第二扫描时钟信号端GCK2的信号为高电平信号，第七扫描晶体管GT7截止。
在稳定阶段t4的第一子阶段t41中，第一扫描时钟信号端GCK1的信号为低电平信号，第二时钟信号CB的信号为高电平信号，扫描信号输入端GIN的信号为高电平信号。由于第一扫描时钟信号端GCK1的信号为低电平信号，第一扫描晶体管GT1导通，扫描信号输入端GIN的信号经由第一扫描晶体管GT1传输至第一扫描节点GN1，第二扫描晶体管GT2截止。由于第八扫描晶体管GT8处于开启状态，第五扫描晶体管GT5截止。由于第一扫描时钟信号端GCK1的信号为低电平信号，第三扫描晶体管GT3导通，第四扫描晶体管GT4和第六扫描晶体管GT6均导通，第一扫描电源端GV1的高电平信号经由第四扫描晶体管GT4传输至扫描信号输出端GOUT，即栅极输出信号为高电平信号。
在稳定阶段t4的第二子阶段t42中，第一扫描时钟信号端GCK1的信号为高电平信号，第二时钟信号CB的信号为低电平信号，扫描信号输入端GIN的信号为高电平信号。第五扫描晶体管GT5和第二扫描晶体管GT2均截止。第一扫描时钟信号端GCK1的信号为高电平信号，从而第一扫描晶体管GT1和第三扫描晶体管GT3均截止，由于第一扫描电容C1的保持作用下，第四扫描晶体管GT4和第六扫描晶体管GT6均导通，高电平信号经由第四扫描晶体管GT4传输至扫描信号输出端GOUT，即栅极输出信号为高电平信号。
在第二子阶段t42中，由于第二扫描时钟信号端GCK2的信号为低电平信号，第七扫描晶体管GT7导通，从而高电平信号经由第六扫描晶体管GT6和第七扫描晶体管GT7被传输至第三扫描节点GN3和第一扫描节点GN1，以使第三扫描节点GN3和第一扫描节点GN1的信号保持为高电平信号。
在第三子阶段t43中，第一扫描时钟信号端GCK1和第二扫描时钟信号端GCK2的信号均为高电平信号，扫描信号输入端GIN的信号为高电平信号。 第五扫描晶体管GT5和第二扫描晶体管GT2截止。第一扫描时钟信号端GCK1的信号为高电平信号，从而第一扫描晶体管GT1和第三扫描晶体管GT3均截止，第四扫描晶体管GT4和第六扫描晶体管GT6均导通。高电平信号经由第四扫描晶体管GT4至扫描信号输出端GOUT，即栅极输出信号为高电平信号。
图25为一种示例性实施例提供的发光驱动电路的结构示意图，图26为一种示例性实施例提供的第二移位寄存器的等效电路图，图27为一种示例性实施例提供的第二移位寄存器的工作时序图。如图25至27所示，一种示例性实施例提供的发光驱动电路包括：沿列方向依次排布的多个级联的第二移位寄存器EOA，每个第二移位寄存器包括：第一发光晶体管ET1至第十发光晶体管ET10、第一发光电容EC1至第三发光电容EC3、发光信号输入端EIN、发光信号输出端EOUT、第一发光时钟信号端ECK1、第二发光时钟信号端ECK2、第一发光电源端EV1和第二发光电源端EV2。
第一发光晶体管ET1的控制极与第一发光时钟信号端ECK1电连接，第一发光晶体管ET1的第一极与发光信号输入端EIN电连接，第一发光晶体管ET1的第二极与第一发光节点EN1电连接。第二发光晶体管ET2的控制极与第一发光节点EN1电连接，第二发光晶体管ET2的第一极与第一发光时钟信号端ECK1电连接，第二发光晶体管ET2的第二极与第二发光节点EN2电连接。第三发光晶体管ET3的控制极与第一发光时钟信号端ECK1电连接，第三发光晶体管ET3的第一极与第二发光电源端EV2电连接，第三发光晶体管ET3的第二极与第二发光节点EN2电连接。第四发光晶体管ET4的控制极与第二发光时钟信号端ECK2电连接，第四发光晶体管ET4的第一极与第一发光节点EN1电连接，第四发光晶体管ET4的第二极与第五发光晶体管ET5的第一极电连接。第五发光晶体管ET5的控制极与第二发光节点EN2电连接，第五发光晶体管ET5的第二极与第一发光电源端EV1电连接。第六发光晶体管ET6的控制极与第二发光节点EN2电连接，第六发光晶体管ET6的第一极与第二发光时钟信号端ECK2电连接，第六发光晶体管ET6的第二极与第三发光节点EN3电连接。第七发光晶体管ET7的控制极与第二发光时钟信号端ECK2电连接，第七发光晶体管ET7的第一极与第三发光节 点EN3电连接，第七发光晶体管ET7的第二极与第四发光节点EN4电连接。第八发光晶体管ET8的控制极与第一发光节点EN1电连接，第八发光晶体管ET8的第一极与第一发光电源端EV1电连接，第八发光晶体管ET8的第二极与第四发光节点EN4电连接。第九发光晶体管ET9的控制极与第四发光节点EN4电连接，第九发光晶体管ET9的第一极与发光信号输出端EOUT电连接，第九发光晶体管ET9的第二极与第一发光电源端EV1电连接。第十发光晶体管ET10的控制极与第一发光节点EN1电连接，第十发光晶体管ET10的第一极与第二发光电源端EV2电连接，第十发光晶体管ET10的第二极与发光信号输出端EOUT电连接。第一发光电容EC1的第一极板EC11与第二发光节点EN2电连接，第一发光电容EC1的第二极板EC12与第三发光节点EN3电连接；第二发光电容EC2的第一极板EC21与第一发光节点EN1电连接，第二发光电容EC2的第二极板EC22与第二发光时钟信号端ECK2电连接；第三发光电容EC3的第一极板EC31与第四发光节点EN4电连接，第三发光电容EC3的第二极板EC32与第一发光电源端EV1电连接。
第一级第二移位寄存器EOA(1)的发光信号输入端EIN与发光初始信号线ESTV电连接，第i-1级第二移位寄存器EOA(i-1)的发光信号输出端EOUT与第i级第二移位寄存器EOA(i)的发光信号输入端EIN电连接，所有第二移位寄存器的第一发光电源端EV1与第三电源线VGH电连接，所述第二移位寄存器的第二发光电源端EV2与第四电源线VGL电连接，奇数级第二移位寄存器的第一发光时钟信号端ECK1与第一发光时钟信号线GCK电连接，奇数级第二移位寄存器的第二发光时钟信号端ECK2与第二发光时钟信号线GCB电连接，偶数级第二移位寄存器的第一发光时钟信号端ECK1与第二发光时钟信号线GCB电连接，偶数级第二移位寄存器的第二发光时钟信号端ECK2与第一发光时钟信号线GCK电连接。第二移位寄存器的发光信号输出端EOUT与发光信号线E电连接，其中，i为大于或等于2的正整数。
在一种示例性实施例中，第二移位寄存器的个数可以为M，或者可以为M/2。
在一种示例性实施例中，第一发光晶体管ET1至第十发光晶体管ET10 可以为开关晶体管。第一发光晶体管ET1至第十发光晶体管ET10可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点。在示例性实施方式中，可以将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现高分辨率(Pixel Per Inch，简称PPI)，低频驱动，可以降低功耗，可以提高显示品质。
下面以第一发光晶体管ET1至第十发光晶体管ET10为P型晶体管为例，通过图27示例的第二移位寄存器的工作过程结合图26说明本公开示例性实施例。第二移位寄存器的工作过程可以包括以下阶段：
第一阶段P1，发光信号输入端EIN的信号为高电平信号，第一发光时钟信号端ECK1的信号为低电平信号，第一发光晶体管ET1和第三发光晶体管ET3导通，发光信号输入端EIN的信号被写入至第一发光节点EN1，此时，第一发光节点EN1为高电平，第二电源端VL2的信号被写入至第二发光节点EN2，此时，第二发光节点EN2为低电平。由于第一发光节点EN1为高电平，第二发光晶体管ET2、第八发光晶体管ET8和第十发光晶体管ET10截止。第二发光时钟信号端ECK2的信号为高电平信号，第四发光晶体管ET4和第七发光晶体管ET7截止。由于第二发光节点EN2为低电平，第五发光晶体管ET5和第六发光晶体管ET6导通，第二发光时钟信号端ECK2的信号被写入至第三发光节点EN3。由于电容两端电压不会突变，所以第四发光节点EN4节点维持上一帧高电平，第九发光晶体管ET9截止，发光信号输出端EOUT的输出信号维持上一帧低电平。
第二阶段P2，发光信号输入端EIN的信号和第一发光时钟信号端ECK1的信号为高电平信号，第一发光晶体管ET1和第三发光晶体管ET3截止，第一发光节点EN1保持高电平，第二发光晶体管ET2、第八发光晶体管ET10和第十发光晶体管ET10截止，第二发光节点EN2保持低电平，第五发光晶 体管ET5和第六发光晶体管ET6导通，由于第二发光时钟信号端ECK2的信号为低电平信号，第四发光晶体管ET4和第七发光晶体管ET7导通，第二发光时钟信号端ECK2的信号被写入第三发光节点EN3，第三发光节点EN3由高电平变为低电平，第三发光节点EN3的信号写入第四发光节点EN4，第四发光节点EN4为低电平，第九发光晶体管ET9导通，发光信号输出端EOUT输出第一电源端VL1的高电平信号。
第三阶段P3，发光信号输入端EIN的信号为高电平信号，第一发光时钟信号端ECK1的信号为低电平信号，第一发光晶体管ET1和第三发光晶体管ET3导通，第一发光节点EN1为高电平，第二发光晶体管ET2、第八发光晶体管ET10和第十发光晶体管ET10截止，第二发光节点EN2保持低电平，第五发光晶体管ET5和第六发光晶体管ET6导通，第二发光时钟信号端ECK2的信号写入第三发光节点EN3，由于第二发光时钟信号端ECK2的信号为高电平信号，第三发光节点EN3由上一阶段的低电平转变为高电平，第四发光晶体管ET4和第七发光晶体管ET7截止，第四发光节点EN4保持低电平，第九发光晶体管ET9导通，发光信号输出端EOUT输出第一电源端VL1的高电平信号。
第四阶段P4，发光信号输入端EIN的信号为低电平信号，第一发光时钟信号端ECK1的信号为高电平信号，第一发光晶体管ET1和第三发光晶体管ET3截止，第一发光节点EN1保持高电平，第二发光晶体管ET2、第八发光晶体管ET10和第十发光晶体管ET10截止，第二发光节点EN2保持低电平，第五发光晶体管ET5和第六发光晶体管ET6导通，第二发光时钟信号端ECK2的信号写入第三发光节点EN3，由于第二发光时钟信号端ECK2的信号为低电平信号，第三发光节点EN3由上一阶段的高电平转变为低电平，第四发光晶体管ET4和第七发光晶体管ET7导通，第三发光节点EN3的信号写入第四发光节点EN4，第四发光节点EN4保持低电平，第九发光晶体管ET9导通，发光信号输出端EOUT输出第一电源端VL1的高电平信号。
第五阶段P5，发光信号输入端EIN的信号和第一发光时钟信号端ECK1的信号为低电平信号，第一发光晶体管ET1和第三发光晶体管ET3导通，第一发光节点EN1由高电平转变为低电平，第二发光晶体管ET2、第八发光晶 体管ET10和第十发光晶体管ET10导通，第二发光节点EN2保持低电平，第五发光晶体管ET5和第六发光晶体管ET6导通，第二发光时钟信号端ECK2的信号写入第三发光节点EN3，由于第二发光时钟信号端ECK2的信号为高电平信号，第三发光节点EN3由上一阶段的低电平转变为高电平，第四发光晶体管ET4和第七发光晶体管ET7截止，由于第八发光晶体管ET8导通，第一电源端VL1的高电平信号写入第四发光节点EN4中，第四发光节点EN4变为高电平，第九发光晶体管ET9截止，由于第十发光晶体管ET10导通，第二电源端VL2的低电平信号写入发光信号输出端EOUT，发光信号输出端EOUT输出低电平信号。
第六阶段P6，发光信号输入端EIN的信号为低电平信号，第一发光时钟信号端ECK1的信号为高电平信号，第一发光晶体管ET1和第三发光晶体管ET3截止，第一发光节点EN1保持低电平，第二发光晶体管ET2、第八发光晶体管ET10和第十发光晶体管ET10导通，第一发光节点EN1的信号写入第二发光节点EN2，第二发光节点EN2由低电平转变为高电平，第五发光晶体管ET5和第六发光晶体管ET6截止，第三发光节点EN3保持高电平，由于第二发光时钟信号端ECK2的信号为低电平信号，第四发光晶体管ET4和第七发光晶体管ET7导通，第三发光节点EN3的信号写入第四发光节点EN4，第四发光节点EN4保持高电平，第九发光晶体管ET9截止，由于第十发光晶体管ET10导通，第二电源端VL2的低电平信号写入发光信号输出端EOUT，发光信号输出端EOUT输出低电平信号。
第七阶段P7，发光信号输入端EIN的信号为低电平信号，第一发光时钟信号端ECK1的信号为低电平信号，第一发光晶体管ET1和第三发光晶体管ET3导通，第一发光节点EN1保持低电平，第二发光晶体管ET2、第八发光晶体管ET10和第十发光晶体管ET10导通，第一发光节点EN1的信号写入第二发光节点EN2，第二发光节点EN2为低电平，第五发光晶体管ET5和第六发光晶体管ET6导通，第二发光时钟信号端ECK2的信号写入第三发光节点EN3，由于第二发光时钟信号端ECK2的信号为高电平信号，第四发光晶体管ET4和第七发光晶体管ET7截止，第四发光节点EN4保持高电平，第九发光晶体管ET9截止，由于第十发光晶体管ET10导通，第二电源端VL2 的低电平信号写入发光信号输出端EOUT，发光信号输出端EOUT输出低电平信号。
第八阶段P8，发光信号输入端EIN的信号为低电平信号，第一发光时钟信号端ECK1的信号为高电平信号，第一发光晶体管ET1和第三发光晶体管ET3截止，第一发光节点EN1保持低电平，第二发光晶体管ET2、第八发光晶体管ET10和第十发光晶体管ET10导通，第一发光节点EN1的信号写入第二发光节点EN2，第二发光节点EN2由低电平转变为高电平，第五发光晶体管ET5和第六发光晶体管ET6截止，第三发光节点EN3保持高电平，由于第二发光时钟信号端ECK2的信号为低电平信号，第四发光晶体管ET4和第七发光晶体管ET7导通，第三发光节点EN3的信号写入第四发光节点EN4，第四发光节点EN4保持高电平，第九发光晶体管ET9截止，由于第十发光晶体管ET10导通，第二电源端VL2的低电平信号写入发光信号输出端EOUT，发光信号输出端EOUT输出低电平信号。
在第一阶段P7之后，第七阶段P7和第八阶段P8循环往复，第八发光晶体管ET8持续导通，第九发光晶体管ET9截止，第一发光晶体管ET1周期性地给第二电容C2充电，第一发光节点EN1保持低电平，第十发光晶体管ET10持续导通，发光信号输出端EOUT输出低电平信号，直到下一帧发光信号输入端EIN的脉冲进入。
图28为一种示例性实施例提供的显示基板的截面图一，图29为一种示例性实施例提供的显示基板的截面图二。如图28和图29所示，发光结构层30包括：依次叠设在驱动结构层20上的第一电极层、像素界定层34、发光层和第二电极层。其中，第一电极层包括：多个第一电极31，所述发光层包括：多个有机发光层32，所述第二电极层包括：多个第二电极33，每个发光结构包括：第一电极、有机发光层和第二电极。
在一种示例性实施例中，有机发光层可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称 EIL)。在示例性实施方式中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，所有子像素的电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，相邻子像素的电子阻挡层可以有少量的交叠，或者可以是隔离的。
如图28和图29所示，第六像素晶体管PT6可以包括：有源层61、控制极62、第一极63和第二极64。对于每个像素电路，第六像素晶体管PT6的第二极64在衬底基板10上的正投影与像素电路所连接的发光结构中的第一电极31在衬底基板10上的正投影不存在重叠区域，即像素电路与发光结构错开设置。
在一种示例性实施例中，像素界定层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。
在一种示例性实施例中，第一电极层可以采用氧化铟锡(ITO)或氧化铟锌(IZO)等透明导电材料。
在一种示例性实施例中，第二电极层可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或更多种，或采用上述金属中任意一种或多种制成的合金。
在一种示例性实施例中，如图28和图29所示，驱动结构层20包括：连接电极21，连接电极21位于像素电路和发光结构之间，且与像素电路中的第六像素晶体管的第二极64和发光结构中的第一电极31电连接。
在一种示例性实施例中，连接电极21包括：第一连接部210和第二连接部220。第一连接部设置在第二连接部220靠近衬底基板10的一侧，第一连接部210分别与像素电路中的第六像素晶体管的第二极64和第二连接部220电连接，第二连接部220与发光结构中的第一电极31电连接。
在一种示例性实施例中，如图28所示，第一连接部可以为金属电极，第二连接部可以为透明电极。本实施例中，第一连接部为金属电极，第二连接部为透明电极，使得连接电极不容易看到，可以保证显示基板的显示效果。
在一种示例性实施例中，如图29所示，第一连接部和第二连接部可以为一体成型结构。本实施例中，第一连接部和第二连接部为一体成型结构可以简化显示基板的制作工艺，节省显示基板的制作成本。
在一种示例性实施例中，如图28和图29所示，显示基板还可以包括：封装层40和隔垫物50。其中，封装层40设置在发光结构层30远离衬底基板10的一侧，隔垫物50设置在封装层40远离衬底基板10的一侧。
在一种示例性实施例中，封装层可以采用无机材料/有机材料/无机材料的叠层结构，有机材料层设置在两个无机材料层之间。
在一种示例性实施例中，如图28所示，当第一连接部为金属电极，第二连接部为透明电极时，驱动结构层还可以包括：依次叠设在衬底基板上的第一绝缘层22、半导体层、第二绝缘层23、第一金属层、第三绝缘层24、第二金属层、第四绝缘层25、第三金属层、第五绝缘层26、第一平坦层27、第四金属层、第二平坦层28、第五金属层、透明导电层和第三平坦层29。
在一种示例性实施例中，半导体层包括：多个像素晶体管的有源层、多个空白晶体管的有源层、多个扫描晶体管的有源层和多个发光晶体管的有源层；第一金属层包括：发光信号线、扫描信号线、复位信号线、第一像素电容的第一极板PC11，第一扫描电容的第二极板、第二扫描电容的第二极板、第一发光电容的第一极板、第二发光电容的第二极板、第三发光电容的第三极板、多个像素晶体管的控制极、多个空白晶体管的控制极、多个扫描晶体管的控制极和多个发光晶体管的控制极；第二金属层包括：初始信号线，第一像素电容的第二极板PC22、第一扫描电容的第一极板、第二扫描电容的第二极板、第一发光电容的第二极板、第二发光电容的第二极板和第三发光电容的第二极板；第三金属层包括：第三电源线、第四电源线、第一扫描时钟信号线、第二扫描时钟信号线、第一发光时钟信号线、第二发光时钟信号线、扫描初始信号线和发光初始信号线、多个像素晶体管的第一极和第二极、多个空白晶体管的第一极和第二极、多个扫描晶体管的第一极和第二极以及多个发光晶体管的第一极和第二极；第四金属层包括：数据信号线和第一电源线VDD；第五金属层包括：第一连接部210，透明导电层包括：第二连接部220。
在一种示例性实施例中，如图29所示，当第一连接部和第二连接部为一体成型结构时，驱动结构层20还包括：依次叠设在衬底基板10上的第一绝缘层22、半导体层、第二绝缘层23、第一金属层、第三绝缘层24、第二金属层、第四绝缘层25、第三金属层、第五绝缘层26、第一平坦层27、第四金属层、第二平坦层28、第五金属层和第三平坦层29。其中，半导体层包括：多个像素晶体管的有源层、多个空白晶体管的有源层、多个扫描晶体管的有源层和多个发光晶体管的有源层；第一金属层包括：发光信号线、扫描信号线、复位信号线、第一像素电容的第一极板PC11，第一扫描电容的第二极板、第二扫描电容的第二极板、第一发光电容的第一极板、第二发光电容的第二极板、第三发光电容的第三极板、多个像素晶体管的控制极、多个空白晶体管的控制极、多个扫描晶体管的控制极和多个发光晶体管的控制极；第二金属层包括：初始信号线，第一像素电容的第二极板PC12、第一扫描电容的第一极板、第二扫描电容的第二极板、第一发光电容的第二极板、第二发光电容的第二极板和第三发光电容的第二极板；第三金属层包括：第三电源线、第四电源线、第一扫描时钟信号线、第二扫描时钟信号线、第一发光时钟信号线、第二发光时钟信号线、扫描初始信号线和发光初始信号线、多个像素晶体管的第一极和第二极、多个空白晶体管的第一极和第二极、多个扫描晶体管的第一极和第二极以及多个发光晶体管的第一极和第二极；第四金属层包括：数据信号线和第一电源线VDD；第五金属层包括：连接电极21。
如图28和图29提供的显示基板中第一电源线在衬底基板上的正投影覆盖第一像素电容在衬底基板上的正投影。显示基板中第一电源线在衬底基板上的正投影覆盖第一像素电容在衬底基板上的正投影可以减少像素电路所占用的面积。
在一种示例性实施例中，第一电源线和数据信号线还可以设置在第三金属层。
在一种示例性实施例中，第一金属层、第二金属层、第三金属层、第四金属层和第五金属层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如 Mo/Cu/Mo等。
在一种示例性实施例中，第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层称之为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层称之为栅绝缘(GI)层，第四绝缘层称之为层间绝缘(ILD)层，第五绝缘层称之为钝化(PVX)层。
在一种示例性实施例中，第一平坦层至第三平坦层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。
本公开实施例还提供了一种显示装置，包括显示基板。
在一种示例性实施例中，显示装置可以为液晶显示装置(Liquid Crystal Display，简称LCD)或有机发光二极管(Organic Light Emitting Diode，简称OLED)显示装置。该显示装置可以为：液晶面板、电子纸、OLED面板、有源矩阵有机发光二极管(active-matrix organic light emitting diode，简称AMOLED)面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
显示基板为上述实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
本公开实施例还提供了一种显示基板的制作方法，设置为制作显示基板，本公开实施例提供的显示基板的制作方法包括：
步骤S1、提供一衬底基板。
步骤S2、在衬底基板上形成M行扫描信号线和M行发光信号线以及位于显示区的驱动结构层。
在一种示例性实施例中，驱动结构层包括：沿列方向延伸的像素电路阵列和驱动电路阵列。其中，像素电路阵列和驱动电路阵列沿行方向依次排布。像素电路阵列包括：M行N列像素电路，第i行像素电路与第i行扫描信号线和第i行发光信号线电连接。驱动电路阵列包括：多个驱动电路，驱动电路设置为向扫描信号线和发光信号线提供驱动信号。
步骤S3、在驱动结构层上形成发光结构层。
在一种示例性实施例中，发光结构层包括：M行N列发光结构，像素电路和发光结构一一对应，且与对应的发光结构电连接。
本实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶等处理。本实施例中所说的“光刻工艺”包括涂覆膜层、掩模曝光、显影等处理。沉积可以采用选自溅射、蒸镀和化学气相沉积中的任意一种或多种。涂覆可以采用选自喷涂和旋涂中的任意一种或多种。刻蚀可以采用选自干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程当中“薄膜”无需构图工艺，则“薄膜”还可以称为“层”。当在整个制作过程当中“薄膜”还需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。
在一种示例性实施例中，在所述衬底基板上依次形成第一绝缘层、半导体层、第二绝缘层、第一金属层、第三绝缘层、第二金属层、第四绝缘层、第三金属层、第五绝缘层、第一平坦层、第四金属层、第二平坦层、第五金属层、透明导电层和第三平坦层。
在一种示例性实施例中，在衬底基板上依次形成第一绝缘层、半导体层、第二绝缘层、第一金属层、第三绝缘层、第二金属层、第四绝缘层、第三金属层、第五绝缘层、第一平坦层、第四金属层、第二平坦层、第五金属层、透明导电层和第三平坦层可以包括：在衬底基板上依次沉积第一绝缘薄膜和半导体薄膜，通过构图工艺对第一绝缘薄膜和半导体薄膜进行构图，形成第一绝缘层图案和半导体层图案；在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一金属薄膜，通过构图工艺对第二绝缘薄膜和第一金属薄膜进行构图，形成第二绝缘层图案以及位于第二绝缘层上的第一金属层图案；在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二金属薄膜，通过构图工艺对第三绝缘薄膜和第二金属薄膜进行构图，形成第三绝缘层图案以及位于第三绝缘层上的第二金属层图案；在形成前述图案的基底上，依次沉积第四绝缘薄膜和第三金属薄膜，通过构图工艺对第四绝缘薄膜和第三金属薄膜进行构图，形成第四绝缘层图案以及位于第四绝缘层上的第三金属层图案；在 形成前述图案的基底上，依次沉积第三绝缘薄膜和第二金属薄膜，通过构图工艺对第五绝缘薄膜进行构图，形成第五绝缘层图案；在形成前述图案的基底上，涂覆第一平坦薄膜，通过光刻工艺形成第一平坦层图案；在形成前述图案的基底上，沉积第四金属薄膜，通过构图工艺形成第四金属层图案；在形成前述图案的基底上，涂覆第二平坦薄膜，通过光刻工艺形成第二平坦层图案；在形成前述图案的基底上，沉积第五金属薄膜，通过构图工艺形成第五金属层图案；在形成前述图案的基底上，沉积透明导电薄膜，通过构图工艺形成透明导电层图案；在形成前述图案的基底上，涂覆第三平坦薄膜，通过光刻工艺形成第三平坦层图案。
在一种示例性实施例中，在衬底基板上形成位于显示区的驱动结构层可以包括：在衬底基板上依次形成第一绝缘层、半导体层、第二绝缘层、第一金属层、第三绝缘层、第二金属层、第四绝缘层、第三金属层、第五绝缘层、第一平坦层、第四金属层、第二平坦层、第五金属层和第三平坦层。
在一种示例性实施例中，在衬底基板上依次形成第一绝缘层、半导体层、第二绝缘层、第一金属层、第三绝缘层、第二金属层、第四绝缘层、第三金属层、第五绝缘层、第一平坦层、第四金属层、第二平坦层、第五金属层和第三平坦层可以包括：在衬底基板上依次沉积第一绝缘薄膜和半导体薄膜，通过构图工艺对第一绝缘薄膜和半导体薄膜进行构图，形成第一绝缘层图案和半导体层图案；在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一金属薄膜，通过构图工艺对第二绝缘薄膜和第一金属薄膜进行构图，形成第二绝缘层图案以及位于第二绝缘层上的第一金属层图案；在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二金属薄膜，通过构图工艺对第三绝缘薄膜和第二金属薄膜进行构图，形成第三绝缘层图案以及位于第三绝缘层上的第二金属层图案；在形成前述图案的基底上，依次沉积第四绝缘薄膜和第三金属薄膜，通过构图工艺对第四绝缘薄膜和第三金属薄膜进行构图，形成第四绝缘层图案以及位于第四绝缘层上的第三金属层图案；在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二金属薄膜，通过构图工艺对第五绝缘薄膜进行构图，形成第五绝缘层图案；在形成前述图案的基底上，涂覆第一平坦薄膜，通过光刻工艺形成第一平坦层图案；在形成前述图案的基底上， 沉积第四金属薄膜，通过构图工艺形成第四金属层图案；在形成前述图案的基底上，涂覆第二平坦薄膜，通过光刻工艺形成第二平坦层图案；在形成前述图案的基底上，沉积第五金属薄膜，通过构图工艺形成第五金属层图案；在形成前述图案的基底上，涂覆第三平坦薄膜，通过光刻工艺形成第三平坦层图案。
在一种示例性实施例中，在驱动结构层上形成发光结构层包括：在驱动结构层上依次形成第一电极层、像素界定层、发光层和第二电极层。在驱动结构层上依次形成第一电极层、像素界定层、发光层和第二电极层可以包括：在形成第三平坦层图案的基底上涂覆第一电极薄膜，通过构图工艺形成第一电极层图案，在形成前述图案的基底上涂覆像素界定薄膜，通过掩膜、曝光、显影工艺，形成像素界定(PDL)层图案，像素界定层上开设有像素开口，像素开口内的像素界定薄膜被显影掉，暴露出第一电极的表面。像素界定层上开设有第一开孔，第一开孔内的像素定义薄膜被显影掉，暴露出连接电极的表面；在形成前述图案的基底上依次形成发光层和第二电极层。
在一种示例性实施例中，在驱动结构层上形成发光结构层之后，显示基板的制作方法还可以包括：在发光结构层上形成封装层和隔垫物。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (23)

  1. 一种显示基板，包括：显示区和非显示区，所述显示基板包括：衬底基板以及依次叠设在所述衬底基板上，且位于所述显示区的驱动结构层和发光结构层，所述显示基板还包括：M行扫描信号线和M行发光信号线；所述发光结构层包括：M行N列发光结构，所述驱动结构层包括：沿列方向延伸的像素电路阵列和驱动电路阵列；所述像素电路阵列和所述驱动电路阵列沿行方向依次排布；
    所述像素电路阵列包括：M行N列像素电路，像素电路和发光结构一一对应，且与对应的发光结构电连接，第i行像素电路与第i行扫描信号线和第i行发光信号线电连接，1≤i≤M；
    所述驱动电路阵列包括：至少一个扫描驱动电路和至少一个发光驱动电路，所述扫描驱动电路设置为向所述扫描信号线提供驱动信号，所述发光驱动电路设置为向所述发光信号线提供驱动信号。
  2. 根据权利要求1所述的显示基板，其中，所述驱动结构层还包括：空白电路阵列；所述空白电路阵列设置在所述像素电路阵列和所述驱动电路阵列之间；
    所述空白电路阵列包括：多个空白电路，空白电路与扫描信号线和发光信号线电连接。
  3. 根据权利要求1或2所述的显示基板，其中，所述显示区包括：至少一端弧形显示边界，所述显示区包括：相对设置的第一边界和第二边界及相对设置的第三边界和第四边界；所述第一边界的长度大于所述第三边界的长度；
    所述第一边界和所述第二边界沿列方向延伸，且为非直线型结构，所述弧形显示边界位于所述第一边界和所述第二边界中，所述第三边界和所述第四边界沿行方向延伸，且为直线型结构；
    靠近弧形显示边界的至少部分像素电路呈弧形状排布。
  4. 根据权利要求1至3任一项所述的显示基板，其中，所述像素电路阵列包括：沿行方向依次排布的第二像素电路阵列、第一像素电路阵列和第三 像素电路阵列；所述驱动电路阵列包括：沿行方向排布的第一驱动电路阵列和第二驱动电路阵列；
    所述第一驱动电路阵列位于所述第一像素电路阵列和所述第二像素电路阵列之间，所述第二驱动电路阵列位于所述第一像素电路阵列和所述第三像素电路阵列之间；
    所述第一驱动电路阵列和所述第二驱动电路阵列中的多个驱动电路呈直线型排布。
  5. 根据权利要求4所述的显示基板，其特征在于，所述驱动结构层还包括空白电路阵列时，所述空白电路阵列包括：第一空白电路阵列、第二空白电路阵列、第三空白电路阵列和第四空白电路阵列；
    所述第一空白电路阵列位于所述第二像素电路阵列和所述第一驱动电路阵列之间，所述第二空白电路阵列位于所述第一驱动电路阵列和所述第一像素电路阵列之间，所述第三空白电路阵列位于所述第一像素电路阵列和所述第二驱动电路阵列，所述第四空白电路阵列位于所述第二驱动电路阵列和所述第三像素电路阵列之间；
    所述第一空白电路阵列、所述第二空白电路阵列、所述第三空白电路阵列和所述第四空白电路阵列的多个空白电路呈直线型排布。
  6. 根据权利要求1至3任一项所述的显示基板，其中，所述驱动电路阵列包括：沿行方向依次排布的第一驱动电路阵列和第二驱动电路阵列；
    所述第一驱动电路阵列设置在所述像素电路阵列靠近所述显示区的第一边界的一侧，所述第二驱动电路阵列设置在所述像素电路阵列靠近所述显示区的第二边界的一侧；
    所述第一驱动电路阵列中靠近弧形显示边界的至少部分驱动电路呈弧形状排布；所述第二驱动电路阵列中靠近弧形显示边界的至少部分驱动电路呈弧形状排布。
  7. 根据权利要求6所述的显示基板，其中，所述驱动结构层还包括空白电路阵列时，所述空白电路阵列包括：第一空白电路阵列和第二空白电路阵列；
    所述第一空白电路阵列位于所述第一驱动电路阵列和所述像素电路阵列之间，所述第二空白电路阵列位于所述像素电路阵列和所述第二驱动电路阵列之间；
    所述第一空白电路阵列中靠近弧形显示边界的至少部分空白电路呈弧形状排布；所述第二空白电路阵列中靠近弧形显示边界的至少部分空白电路呈弧形状排布。
  8. 根据权利要求4至7任一所述的显示基板，其中，所述第一驱动电路阵列和第二驱动电路阵列均包括：扫描驱动电路和发光驱动电路；位于同一驱动电路阵列中的扫描驱动电路和发光驱动电路沿行方向排布；
    或者，所述第一驱动电路阵列包括：扫描驱动电路，所述第二驱动电路阵列包括：发光驱动电路。
  9. 根据权利要求1至3任一项所述的显示基板，其中，所述像素电路阵列包括：沿行方向依次排布的第一像素电路阵列和第二像素电路阵列；所述驱动电路阵列包括：沿行方向依次排布的第一驱动电路阵列、第二驱动电路阵列和第三驱动电路阵列；
    所述第一像素电路阵列位于所述第一驱动电路阵列和所述第二驱动电路阵列之间，所述第二像素电路阵列位于第二驱动电路阵列和所述第三驱动电路阵列之间；
    所述第一驱动电路阵列中靠近弧形显示边界的至少部分驱动电路呈弧形状排布；所述第三驱动电路阵列中靠近弧形显示边界的至少部分驱动电路呈弧形状排布；所述第二驱动电路阵列中多个驱动电路呈直线型排布。
  10. 根据权利要求9所述的显示基板，其中，所述第一驱动电路阵列和所述第三驱动电路阵列包括：扫描驱动电路，所述第二驱动电路阵列包括：发光驱动电路。
  11. 根据权利要求9或10所述的显示基板，其中，所述驱动结构层还包括空白电路阵列时，所述空白电路阵列包括：第一空白电路阵列、第二空白电路阵列、第三空白电路阵列和第四空白电路阵列；
    所述第一空白电路阵列位于所述第一驱动电路阵列和所述第一像素电路 阵列之间，所述第二空白电路阵列位于所述第一像素电路阵列和所述第二驱动电路阵列之间，所述第三空白电路阵列位于所述第二驱动电路阵列和所述第二像素电路阵列之间，所述第四空白电路阵列位于所述第二像素电路阵列和所述第三驱动电路阵列之间；
    所述第一空白电路阵列中靠近弧形显示边界的至少部分空白电路呈弧形状排布；第二空白电路阵列和第三空白电路阵列中的多个空白电路呈直线型排布；所述第四空白电路阵列中靠近弧形显示边界的至少部分空白电路呈弧形状排布。
  12. 根据权利要求2至11任一项所述的显示基板，还包括：沿列方向延伸的第一电源线、第二电源线和数据信号线以及沿行方向延伸的复位信号线和初始信号线，所述发光结构与第二电源线电连接；
    所述像素电路包括：第一像素晶体管至第七像素晶体管和第一像素电容；其中，第一像素晶体管的控制极与复位信号线电连接，第一像素晶体管的第一极与第一像素节点电连接，第一像素晶体管的第二极与初始信号线电连接；第二像素晶体管的控制极与扫描信号线电连接，第二像素晶体管的第一极与第一像素节点电连接，第二像素晶体管的第二极与第二像素节点电连接；第三像素晶体管的控制极与第一像素节点电连接，第三像素晶体管的第一极与第三像素节点电连接，第三像素晶体管的第二极与第二像素节点电连接；第四像素晶体管的控制极与扫描信号线电连接，第四像素晶体管的第一极与数据信号线电连接，第四像素晶体管的第二极与第三像素节点电连接；第五像素晶体管的控制极与发光信号线电连接，第五像素晶体管的第一极与第一电源线电连接，第五像素晶体管的第二极与第三像素节点电连接；第六像素晶体管的控制极与发光信号线电连接，第六像素晶体管的第一极与第二像素节点电连接，第六像素晶体管的第二极与发光结构电连接；第七像素晶体管的控制极与扫描信号线电连接，第七像素晶体管的第一极与初始信号线电连接，第七像素晶体管的第二极与发光结构电连接；第一像素电容的第一极板与第一像素节点电连接，第一像素电容的第二极板与第一电源线电连接。
  13. 根据权利要求2至11任一项所述的显示基板，还包括：沿列方向延伸的第一电源线以及沿行方向延伸的复位信号线和初始信号线；
    所述空白电路包括：第一空白晶体管至第七空白晶体管和第一空白电容；其中，第一空白晶体管的控制极与复位信号线电连接，第一空白晶体管的第一极与第一空白节点电连接，第一空白晶体管的第二极与初始信号线电连接；第二空白晶体管的控制极与扫描信号线电连接，第二空白晶体管的第一极与第一空白节点电连接，第二空白晶体管的第二极与第二空白节点电连接；第三空白晶体管的控制极与第一空白节点电连接，第三空白晶体管的第一极与第三空白节点电连接，第三空白晶体管的第二极与第二空白节点电连接；第四空白晶体管的控制极与扫描信号线电连接，第四空白晶体管的第一极浮接，第四空白晶体管的第二极与第三空白节点电连接；第五空白晶体管的控制极与发光信号线电连接，第五空白晶体管的第一极与第一电源线电连接，第五空白晶体管的第二极与第三空白节点电连接；第六空白晶体管的控制极与发光信号线电连接，第六空白晶体管的第一极与第二空白节点电连接，第六空白晶体管的第二极浮接或者与第一电源线电连接；第七空白晶体管的控制极与扫描信号线电连接，第七空白晶体管的第一极与初始信号线电连接，第七空白晶体管的第二极浮接或者与第一电源线电连接；第一空白电容的第一极板与第一空白节点电连接，第一空白电容的第二极板与第一电源线电连接。
  14. 根据权利要求1至11任一项所述的显示基板，还包括：沿列方向延伸的第三电源线、第四电源线、第一扫描时钟信号线、第二扫描时钟信号线和扫描初始信号线；
    所述扫描驱动电路包括：沿列方向依次排布的多个级联的第一移位寄存器，每个第一移位寄存器包括：第一扫描晶体管至第八扫描晶体管、第一扫描电容、第二扫描电容、扫描信号输入端、扫描信号输出端、第一扫描时钟信号端、第二扫描时钟信号端、第一扫描电源端和第二扫描电源端；
    第一扫描晶体管的控制极与第一扫描时钟信号端电连接，第一扫描晶体管的第一极与扫描信号输入端电连接，第一扫描晶体管的第二极与第一扫描节点电连接；第二扫描晶体管的控制极与第一扫描节点电连接，第二扫描晶体管的第一极与第一扫描时钟信号端电连接，第二扫描晶体管的第二极与第二扫描节点电连接；第三扫描晶体管的控制极与第一扫描时钟信号端电连接，第三扫描晶体管的第一极与第二扫描电源端电连接，第三扫描晶体管的第二 极与第二扫描节点电连接；第四扫描晶体管的控制极与第二扫描节点电连接，第四扫描晶体管的第一极与第一扫描电源端电连接，第四扫描晶体管的第二极与扫描信号输出端电连接，第五扫描晶体管的控制极与第三扫描节点电连接，第五扫描晶体管的第一极与扫描信号输出端电连接，第五扫描晶体管的第二极与第二扫描时钟信号端电连接；第六扫描晶体管的控制极与第二扫描节点电连接，第六扫描晶体管的第一极与第一扫描电源端电连接，第六扫描晶体管的第二极与第七扫描晶体管的第一极电连接；第七扫描晶体管的控制极与第二扫描时钟信号端电连接，第七扫描晶体管的第二极与第一扫描节点电连接；第八扫描晶体管的控制极与第二扫描电源端电连接，第八扫描晶体管的第一极与第一扫描节点电连接，第八扫描晶体管的第二极与第三扫描节点电连接；第一扫描电容的第一极板与第一扫描电源端电连接，第一扫描电容的第二极板与第二扫描节点电连接；第二扫描电容的第一极板与扫描信号输出端电连接，第二扫描电容的第二极板与第三扫描节点电连接；
    第一级第一移位寄存器的扫描信号输入端与扫描初始信号线电连接，第i-1级第一移位寄存器的扫描信号输出端与第i级第一移位寄存器的扫描信号输入端电连接，所有第一移位寄存器的第一扫描电源端与第三电源线电连接，所述第一移位寄存器的第二扫描电源端与第四电源线电连接，奇数级第一移位寄存器的第一扫描时钟信号端与第一扫描时钟信号线电连接，奇数级第一移位寄存器的第二扫描时钟信号端与第二扫描时钟信号线电连接，偶数级第一移位寄存器的第一扫描时钟信号端与第二扫描时钟信号线电连接，偶数级第一移位寄存器的第二扫描时钟信号端与第一扫描时钟信号线电连接，第一移位寄存器的扫描信号输出端与扫描信号线电连接，其中，i为大于或等于2的正整数。
  15. 根据权利要求1至11任一项所述的显示基板，还包括：沿列方向延伸的第三电源线、第四电源线、第一发光时钟信号线、第二发光时钟信号线和发光初始信号线；
    所述发光驱动电路包括：沿列方向依次排布的多个级联的第二移位寄存器，每个第二移位寄存器包括：第一发光晶体管至第十发光晶体管、第一发光电容至第三发光电容、发光信号输入端、发光信号输出端、第一发光时钟 信号端、第二发光时钟信号端、第一发光电源端和第二发光电源端；
    第一发光晶体管的控制极与第一发光时钟信号端电连接，第一发光晶体管的第一极与发光信号输入端电连接，第一发光晶体管的第二极与第一发光节点电连接；所述第二发光晶体管的控制极与第一发光节点电连接，所述第二发光晶体管的第一极与第一发光时钟信号端电连接，所述第二发光晶体管的第二极与第二发光节点电连接；所述第三发光晶体管的控制极与第一发光时钟信号端电连接，第三发光晶体管的第一极与第二发光电源端电连接，第三发光晶体管的第二极与第二发光节点电连接；第四发光晶体管的控制极与第二发光时钟信号端电连接，第四发光晶体管的第一极与第一发光节点电连接，第四发光晶体管的第二极与第五发光晶体管的第一极电连接；第五发光晶体管的控制极与第二发光节点电连接，第五发光晶体管的第二极与第一发光电源端电连接；第六发光晶体管的控制极与第二发光节点电连接，第六发光晶体管的第一极与第二发光时钟信号端电连接，第六发光晶体管的第二极与第三发光节点电连接；第七发光晶体管的控制极与第二发光时钟信号端电连接，第七发光晶体管的第一极与第三发光节点电连接，第七发光晶体管的第二极与第四发光节点电连接；第八发光晶体管的控制极与第一发光节点电连接，第八发光晶体管的第一极与第一发光电源端电连接，第八发光晶体管的第二极与第四发光节点电连接；第九发光晶体管的控制极与第四发光节点电连接，第九发光晶体管的第一极与发光信号输出端电连接，第九发光晶体管的第二极与第一发光电源端电连接；第十发光晶体管的控制极与第一发光节点电连接，第十发光晶体管的第一极与第二发光电源端电连接，第十发光晶体管的第二极与发光信号输出端电连接；第一发光电容的第一极板与第二发光节点电连接，第一发光电容的第二极板与第三发光节点电连接；第二发光电容的第一极板与第一发光节点电连接，第二发光电容的第二极板与第二发光时钟信号端电连接；第三发光电容的第一极板与第四发光节点电连接，第三发光电容的第二极板与第一发光电源端电连接；
    第一级第二移位寄存器的发光信号输入端与发光初始信号线电连接，第i-1级第二移位寄存器的发光信号输出端与第i级第二移位寄存器的发光信号输入端电连接，所有第二移位寄存器的第一发光电源端与第三电源线电连接， 所述第二移位寄存器的第二发光电源端与第四电源线电连接，奇数级第二移位寄存器的第一发光时钟信号端与第一发光时钟信号线电连接，奇数级第二移位寄存器的第二发光时钟信号端与第二发光时钟信号线电连接，偶数级第二移位寄存器的第一发光时钟信号端与第二发光时钟信号线电连接，偶数级第二移位寄存器的第二发光时钟信号端与第一发光时钟信号线电连接，第二移位寄存器的发光信号输出端与发光信号线电连接，其中，i为大于或等于2的正整数。
  16. 根据权利要求12所述的显示基板，其中，所述发光结构层包括：依次叠设在驱动结构层上的第一电极层、像素界定层、发光层和第二电极层；所述第一电极层包括：多个第一电极，所述发光层包括：多个有机发光层，所述第二电极层包括：多个第二电极，每个发光结构包括：第一电极、有机发光层和第二电极；
    对于每个像素电路，第六像素晶体管的第二极在衬底基板上的正投影与所述像素电路所连接的发光结构中的第一电极在衬底基板上的正投影不存在重叠区域；
    所述驱动结构层还包括：连接电极，所述连接电极位于所述像素电路和发光结构之间，且分别与像素电路中的第六像素晶体管的第二极和发光结构中的第一电极电连接。
  17. 根据权利要求16所述的显示基板，其中，所述连接电极包括：第一连接部和第二连接部；
    所述第一连接部设置在所述第二连接部靠近所述衬底基板的一侧，所述第一连接部分别与像素电路中的第六像素晶体管的第二极和所述第二连接部电连接，所述第二连接部与发光结构中的第一电极电连接；
    所述第一连接部和所述第二连接部为一体成型结构，或者所述第一连接部为金属电极，所述第二连接部为透明电极。
  18. 根据权利要求1至17任一项所述的显示基板，还包括：封装层和隔垫物；
    所述封装层设置在发光结构层远离衬底基板的一侧，所述隔垫物设置在 所述封装层远离衬底基板的一侧。
  19. 根据权利要求17所述的显示基板，其中，当所述第一连接部和所述第二连接部为一体成型结构时，所述驱动结构层包括：依次叠设在所述衬底基板上的第一绝缘层、半导体层、第二绝缘层、第一金属层、第三绝缘层、第二金属层、第四绝缘层、第三金属层、第五绝缘层、第一平坦层、第四金属层、第二平坦层、第五金属层和第三平坦层；
    所述半导体层包括：多个像素晶体管的有源层、多个空白晶体管的有源层、多个扫描晶体管的有源层和多个发光晶体管的有源层；所述第一金属层包括：发光信号线、扫描信号线、复位信号线、第一像素电容的第一极板，第一扫描电容的第二极板、第二扫描电容的第二极板、第一发光电容的第一极板、第二发光电容的第二极板、第三发光电容的第三极板、多个像素晶体管的控制极、多个空白晶体管的控制极、多个扫描晶体管的控制极和多个发光晶体管的控制极；所述第二金属层包括：初始信号线，第一像素电容的第二极板、第一扫描电容的第一极板、第二扫描电容的第二极板、第一发光电容的第二极板、第二发光电容的第二极板和第三发光电容的第二极板；所述第三金属层包括：第三电源线、第四电源线、第一扫描时钟信号线、第二扫描时钟信号线、第一发光时钟信号线、第二发光时钟信号线、扫描初始信号线和发光初始信号线、多个像素晶体管的第一极和第二极、多个空白晶体管的第一极和第二极、多个扫描晶体管的第一极和第二极以及多个发光晶体管的第一极和第二极；所述第四金属层包括：数据信号线和第一电源线；所述第五金属层包括：连接电极；
    所述第一电源线在衬底基板上的正投影与所述第六像素电容在衬底基板上的正投影至少部分重叠。
  20. 根据权利要求17所述的显示基板，其中，当所述第一连接部为金属电极，所述第二连接部为透明电极时，所述驱动结构层包括：依次叠设在所述衬底基板上的第一绝缘层、半导体层、第二绝缘层、第一金属层、第三绝缘层、第二金属层、第四绝缘层、第三金属层、第五绝缘层、第一平坦层、第四金属层、第二平坦层、第五金属层、透明导电层和第三平坦层；
    所述半导体层包括：多个像素晶体管的有源层、多个空白晶体管的有源 层、多个扫描晶体管的有源层和多个发光晶体管的有源层；所述第一金属层包括：发光信号线、扫描信号线、复位信号线、第一像素电容的第一极板，第一扫描电容的第二极板、第二扫描电容的第二极板、第一发光电容的第一极板、第二发光电容的第二极板、第三发光电容的第三极板、多个像素晶体管的控制极、多个空白晶体管的控制极、多个扫描晶体管的控制极和多个发光晶体管的控制极；所述第二金属层包括：初始信号线，第一像素电容的第二极板、第一扫描电容的第一极板、第二扫描电容的第二极板、第一发光电容的第二极板、第二发光电容的第二极板和第三发光电容的第二极板；所述第三金属层包括：第三电源线、第四电源线、第一扫描时钟信号线、第二扫描时钟信号线、第一发光时钟信号线、第二发光时钟信号线、扫描初始信号线和发光初始信号线、多个像素晶体管的第一极和第二极、多个空白晶体管的第一极和第二极、多个扫描晶体管的第一极和第二极以及多个发光晶体管的第一极和第二极；所述第四金属层包括：数据信号线和第一电源线；所述第五金属层包括：第一连接部，所述透明导电层包括：第二连接部；
    所述第一电源线在衬底基板上的正投影与所述第六像素电容在衬底基板上的正投影至少部分重叠。
  21. 一种显示装置，包括：如权利要求1至20任一项所述的显示基板。
  22. 一种显示基板的制作方法，设置为制作如权利要求1至20任一项所述的显示基板，所述方法包括：
    提供一衬底基板；
    在衬底基板上形成M行扫描信号线和M行发光信号线以及位于显示区的驱动结构层；所述驱动结构层包括：沿列方向延伸的像素电路阵列和驱动电路阵列；所述像素电路阵列和所述驱动电路阵列沿行方向依次排布；所述像素电路阵列包括：M行N列像素电路，第i行像素电路与第i行扫描信号线和第i行发光信号线电连接，1≤i≤M；所述驱动电路阵列包括：至少一个扫描驱动电路和至少一个发光驱动电路，所述扫描驱动电路设置为向所述扫描信号线提供驱动信号，所述发光驱动电路设置为向所述发光信号线提供驱动信号；
    在驱动结构层上形成发光结构层；所述发光结构层包括：M行N列发光 结构，像素电路和发光结构一一对应，且与对应的发光结构电连接。
  23. 根据权利要求22所述的方法，其中，所述在衬底基板上形成位于显示区的驱动结构层包括：
    在衬底基板上依次形成第一绝缘层、半导体层、第二绝缘层、第一金属层、第三绝缘层、第二金属层、第四绝缘层、第三金属层、第五绝缘层、第一平坦层、第四金属层、第二平坦层、第五金属层和第三平坦层；
    或者，在所述衬底基板上依次形成第一绝缘层、半导体层、第二绝缘层、第一金属层、第三绝缘层、第二金属层、第四绝缘层、第三金属层、第五绝缘层、第一平坦层、第四金属层、第二平坦层、第五金属层、透明导电层和第三平坦层；
    所述在驱动结构层上形成发光结构层包括：
    在驱动结构层上依次形成第一电极层、像素界定层、发光层和第二电极层；
    所述在驱动结构层上形成发光结构层之后，所述方法还包括：
    在发光结构层上形成封装层和隔垫物。
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