WO2024040442A1 - 移位寄存器及其驱动方法、显示基板、显示装置 - Google Patents

移位寄存器及其驱动方法、显示基板、显示装置 Download PDF

Info

Publication number
WO2024040442A1
WO2024040442A1 PCT/CN2022/114317 CN2022114317W WO2024040442A1 WO 2024040442 A1 WO2024040442 A1 WO 2024040442A1 CN 2022114317 W CN2022114317 W CN 2022114317W WO 2024040442 A1 WO2024040442 A1 WO 2024040442A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
node
terminal
electrode
signal
Prior art date
Application number
PCT/CN2022/114317
Other languages
English (en)
French (fr)
Inventor
王志冲
刘鹏
冯京
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/114317 priority Critical patent/WO2024040442A1/zh
Priority to CN202280002802.9A priority patent/CN117940984A/zh
Publication of WO2024040442A1 publication Critical patent/WO2024040442A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present disclosure relates to but is not limited to the field of display technology, and in particular, to a shift register and a driving method thereof, a display substrate, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • embodiments of the present disclosure provide a shift register, which includes a first control subcircuit, a second control subcircuit, a third control subcircuit, a first output subcircuit, and a second output subcircuit;
  • the first control sub-circuit is respectively connected to the signal input terminal, the first node, the second node, the first clock signal terminal, the second clock signal terminal and the first power supply terminal, and is configured to connect to the first clock signal terminal. , providing the signal of the signal input terminal to the first node under the control of the second clock signal terminal, the second node and the first power terminal, and maintaining the potential of the first node;
  • the second control subcircuit is respectively connected to the second power terminal, the first clock signal terminal, the first node and the second node, and is arranged to connect between the first clock signal terminal and the first node. Under the control of, provide the signal of the second power terminal or the first clock signal terminal to the second node;
  • the third control subcircuit is respectively connected to the first node, the second node, the fourth node, the second clock signal terminal and the first power supply terminal, and is configured to operate on the second clock Under the control of the signal terminal, the first node, and the second node, provide the signal of the second clock signal terminal or the first power terminal to the fourth node, and maintain the potential of the fourth node ;
  • the first output sub-circuit is respectively connected to the first power terminal, the second power terminal, the first node, the fourth node and the first signal output terminal, and is configured to operate on the first Provide the signal of the first power terminal or the second power terminal to the first signal output terminal under the control of the node and the fourth node;
  • the second output sub-circuit is respectively connected to the first signal output terminal, the third control sub-circuit, the first power supply terminal, the second power supply terminal and the second signal output terminal, and is set to Under the control of the third control sub-circuit and the first signal output terminal, the signal of the first power supply terminal or the second power supply terminal is provided to the second signal output terminal.
  • the first control sub-circuit includes a first transistor, a fourth transistor, a fifth transistor and a first capacitor, the first capacitor includes a first plate and a second plate;
  • the control electrode of the first transistor is connected to the first clock signal terminal, the first electrode of the first transistor is connected to the signal input terminal, and the second electrode of the first transistor is connected to the first node. connect;
  • the control electrode of the fourth transistor is connected to the second node, the first electrode of the fourth transistor is connected to the first power supply terminal, and the second electrode of the fourth transistor is connected to the seventh node;
  • the control electrode of the fifth transistor is connected to the second clock signal terminal, the first electrode of the fifth transistor is connected to the seventh node, and the second electrode of the fifth transistor is connected to the first node. connect;
  • the first plate of the first capacitor is connected to the first node, and the second plate of the first capacitor is connected to the second clock signal terminal.
  • the first control sub-circuit includes a first transistor, a fourth transistor, a fifth transistor, a first capacitor and a fourth capacitor, the first capacitor includes a first plate and a second plate , the fourth capacitor includes a first plate and a second plate;
  • the control electrode of the first transistor is connected to the first clock signal terminal, the first electrode of the first transistor is connected to the signal input terminal, and the second electrode of the first transistor is connected to the first node. connect;
  • the control electrode of the fourth transistor is connected to the second node, the first electrode of the fourth transistor is connected to the first power supply terminal, and the second electrode of the fourth transistor is connected to the seventh node;
  • the control electrode of the fifth transistor is connected to the first node, the first electrode of the fifth transistor is connected to the second clock signal terminal, and the second electrode of the fifth transistor is connected to the seventh node. connect;
  • the first plate of the first capacitor is connected to the first node, and the second plate of the first capacitor is connected to the first signal output terminal;
  • the first plate of the fourth capacitor is connected to the seventh node, and the second plate of the fourth capacitor is connected to the first node.
  • the second control subcircuit includes a second transistor and a third transistor
  • the control electrode of the second transistor is connected to the first clock signal terminal, the first electrode of the second transistor is connected to the second power supply terminal, and the second electrode of the second transistor is connected to the second power supply terminal. Node connection;
  • the control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the first clock signal terminal, and the second electrode of the third transistor is connected to the second node. connect.
  • the third control sub-circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a second capacitor, and a third capacitor;
  • the control electrode of the sixth transistor is connected to the second node, the first electrode of the sixth transistor is connected to the second clock signal terminal, and the second electrode of the sixth transistor is connected to the third node;
  • the control electrode of the seventh transistor is connected to the second clock signal terminal, the first electrode of the seventh transistor is connected to the third node, and the second electrode of the seventh transistor is connected to the fourth node. connect;
  • the control electrode of the eighth transistor is connected to the first node, the first electrode of the eighth transistor is connected to the first power supply terminal, and the second electrode of the eighth transistor is connected to the fourth node. ;
  • the first plate of the second capacitor is connected to the second node, and the second plate of the second capacitor is connected to the third node;
  • the first plate of the third capacitor is connected to the fourth node, and the second plate of the third capacitor is connected to the first power terminal.
  • the first output sub-circuit includes a ninth transistor and a tenth transistor
  • the control electrode of the ninth transistor is connected to the fourth node, the first electrode of the ninth transistor is connected to the first power supply terminal, and the second electrode of the ninth transistor is connected to the first signal output. terminal connection;
  • the control electrode of the tenth transistor is connected to the first node, the first electrode of the tenth transistor is connected to the second power supply terminal, and the second electrode of the tenth transistor is connected to the first signal output. end connection.
  • the second output sub-circuit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor;
  • the control electrode of the eleventh transistor is connected to the third control sub-circuit, the first electrode of the eleventh transistor is connected to the second power supply terminal, and the second electrode of the eleventh transistor is connected to the third control sub-circuit.
  • the control electrode of the twelfth transistor is connected to the first signal output terminal, the first electrode of the twelfth transistor is connected to the first power supply terminal, and the second electrode of the twelfth transistor is connected to the first signal output terminal.
  • the sixth node is connected;
  • the control electrode of the thirteenth transistor is connected to the sixth node, the first electrode of the thirteenth transistor is connected to the second power terminal, and the second electrode of the thirteenth transistor is connected to the third node. Two signal output terminals are connected;
  • the control electrode of the fourteenth transistor is connected to the first signal output terminal, the first electrode of the fourteenth transistor is connected to the first power supply terminal, and the second electrode of the fourteenth transistor is connected to the first signal output terminal.
  • the second signal output terminal is connected.
  • the second output sub-circuit further includes a fifth capacitor, the fifth capacitor includes a first plate and a second plate;
  • the first plate of the fifth capacitor is connected to the sixth node, and the second plate of the fifth capacitor is connected to the first clock signal terminal or the second clock signal terminal.
  • the first control sub-circuit includes a first transistor, a fourth transistor, a fifth transistor and a first capacitor, the first capacitor includes a first plate and a second plate;
  • the third The second control sub-circuit includes a second transistor and a third transistor;
  • the third control sub-circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a second capacitor and a third capacitor;
  • the first output sub-circuit includes a Nine transistors and a tenth transistor;
  • the second output sub-circuit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor and a fourteenth transistor;
  • the control electrode of the first transistor is connected to the first clock signal terminal, the first electrode of the first transistor is connected to the signal input terminal, and the second electrode of the first transistor is connected to the first node. connect;
  • the control electrode of the second transistor is connected to the first clock signal terminal, the first electrode of the second transistor is connected to the second power supply terminal, and the second electrode of the second transistor is connected to the second power supply terminal. Node connection;
  • the control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the first clock signal terminal, and the second electrode of the third transistor is connected to the second node. connect;
  • the control electrode of the fourth transistor is connected to the second node, the first electrode of the fourth transistor is connected to the first power supply terminal, and the second electrode of the fourth transistor is connected to the seventh node;
  • the control electrode of the fifth transistor is connected to the second clock signal terminal, the first electrode of the fifth transistor is connected to the seventh node, and the second electrode of the fifth transistor is connected to the first node. connect;
  • the control electrode of the sixth transistor is connected to the second node, the first electrode of the sixth transistor is connected to the second clock signal terminal, and the second electrode of the sixth transistor is connected to the third node;
  • the control electrode of the seventh transistor is connected to the second clock signal terminal, the first electrode of the seventh transistor is connected to the third node, and the second electrode of the seventh transistor is connected to the fourth node. connect;
  • the control electrode of the eighth transistor is connected to the first node, the first electrode of the eighth transistor is connected to the first power supply terminal, and the second electrode of the eighth transistor is connected to the fourth node. ;
  • the control electrode of the ninth transistor is connected to the fourth node, the first electrode of the ninth transistor is connected to the first power supply terminal, and the second electrode of the ninth transistor is connected to the first signal output. terminal connection;
  • the control electrode of the tenth transistor is connected to the first node, the first electrode of the tenth transistor is connected to the second power supply terminal, and the second electrode of the tenth transistor is connected to the first signal output. terminal connection;
  • the control electrode of the eleventh transistor is connected to the third node or the fourth node, the first electrode of the eleventh transistor is connected to the second power supply terminal, and the first electrode of the eleventh transistor is connected to the second power supply terminal.
  • the second pole is connected to the sixth node;
  • the control electrode of the twelfth transistor is connected to the first signal output terminal, the first electrode of the twelfth transistor is connected to the first power supply terminal, and the second electrode of the twelfth transistor is connected to the first signal output terminal.
  • the sixth node is connected;
  • the control electrode of the thirteenth transistor is connected to the sixth node, the first electrode of the thirteenth transistor is connected to the second power terminal, and the second electrode of the thirteenth transistor is connected to the third node. Two signal output terminals are connected;
  • the control electrode of the fourteenth transistor is connected to the first signal output terminal, the first electrode of the fourteenth transistor is connected to the first power supply terminal, and the second electrode of the fourteenth transistor is connected to the first signal output terminal.
  • the second signal output terminal is connected;
  • the first plate of the first capacitor is connected to the first node, and the second plate of the first capacitor is connected to the second clock signal terminal;
  • the first plate of the second capacitor is connected to the second node, and the second plate of the second capacitor is connected to the third node;
  • the first plate of the third capacitor is connected to the fourth node, and the second plate of the third capacitor is connected to the first power terminal.
  • the first to fourteenth transistors are P-type transistors.
  • the signal output by the first signal output terminal and the signal output by the second signal output terminal are mutually inverted signals.
  • inventions of the present disclosure also provide a display substrate.
  • the display substrate includes a substrate and a circuit structure layer disposed on the substrate.
  • the circuit structure layer includes a light-emitting driving circuit.
  • the light-emitting driving circuit includes a plurality of stages. linked shift register;
  • the first signal output terminal of the i-th stage shift register is electrically connected to the signal input terminal of the i+1-th stage shift register, 1 ⁇ i ⁇ M-1, M is the total number of stages of the shift register;
  • At least one shift register includes: a first control subcircuit, a second control subcircuit, a third control subcircuit, a first output subcircuit, and a second output subcircuit;
  • the first control sub-circuit is respectively connected to the signal input terminal, the first node, the second node, the first clock signal terminal, the second clock signal terminal and the first power supply terminal, and is configured to connect to the first clock signal terminal. , providing the signal of the signal input terminal to the first node under the control of the second clock signal terminal, the second node and the first power terminal, and maintaining the potential of the first node;
  • the second control subcircuit is respectively connected to the second power terminal, the first clock signal terminal, the first node and the second node, and is arranged to connect between the first clock signal terminal and the first node. Under the control of, provide the signal of the second power terminal or the first clock signal terminal to the second node;
  • the third control subcircuit is respectively connected to the first node, the second node, the fourth node, the second clock signal terminal and the first power supply terminal, and is configured to operate on the second clock Under the control of the signal terminal, the first node, and the second node, provide the signal of the second clock signal terminal or the first power terminal to the fourth node, and maintain the potential of the fourth node ;
  • the first output sub-circuit is respectively connected to the first power terminal, the second power terminal, the first node, the fourth node and the first signal output terminal, and is configured to operate on the first Provide the signal of the first power terminal or the second power terminal to the first signal output terminal under the control of the node and the fourth node;
  • the second output sub-circuit is respectively connected to the first signal output terminal, the third control sub-circuit, the first power supply terminal, the second power supply terminal and the second signal output terminal, and is set to Under the control of the third control sub-circuit and the first signal output terminal, the signal of the first power supply terminal or the second power supply terminal is provided to the second signal output terminal.
  • the display substrate further includes: an initial signal line, a first clock signal line, a second clock signal line, a second power supply line and a third power supply line extending along the second direction, the initial signal line, the first The clock signal line, the second clock signal line, the third power line and the second power line are arranged along a first direction, and the first direction intersects the second direction;
  • the signal input end of the first-stage shift register is electrically connected to the initial signal line, the first power end of all shift registers is electrically connected to the third power line, and the second power end of all shift registers is electrically connected to the second power line.
  • the first clock signal terminal of the odd-numbered stage shift register is connected to the first clock signal line
  • the second clock signal terminal of the odd-numbered stage shift register is connected to the second clock signal line
  • the first clock signal terminal of the even-numbered stage shift register is connected Connected to the second clock signal line
  • the second clock signal end of the even-numbered shift register is connected to the first clock signal line.
  • the circuit structure layer includes: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer and a third insulating layer sequentially stacked on the substrate.
  • the semiconductor layer includes: an active layer located in all transistors of the light-emitting driving circuit;
  • the first conductive layer includes: control electrodes of all transistors of the light-emitting driving circuit and first plates of the first capacitor to first plates of the third capacitor;
  • the second conductive layer includes: the second plate of the first capacitor of the light-emitting driving circuit to the second plate of the third capacitor;
  • the third conductive layer includes: an initial signal line, a first clock signal line, a second clock signal line, a first power line, and a second power line.
  • the third conductive layer further includes first electrodes and second electrodes of all transistors of the light emitting driving circuit.
  • the shift register includes: first to fourteenth transistors
  • all transistors and capacitors are located between the third power line and the second power line.
  • the second capacitor is located between the third power line and the eighth transistor.
  • the transistor is located between the second capacitor and the ninth and tenth transistors.
  • the ninth and tenth transistors are located between the eighth transistor and the eleventh and twelfth transistors.
  • the eleventh transistor and the tenth transistor are Twelve transistors are located between the ninth transistor and the tenth transistor and the thirteenth and fourteenth transistors.
  • the thirteenth transistor and the fourteenth transistor are located between the eleventh and twelfth transistors.
  • the third capacitor, the ninth transistor, the tenth transistor, and the first capacitor are arranged in sequence along the second direction, and the twelfth transistor and the eleventh transistor are arranged in sequence along the second direction.
  • the fourteenth transistor and the thirteenth transistor are arranged sequentially along the second direction.
  • the first conductive layer further includes a first power line; the first power line is in the shape of a zigzag line, and the first power line is connected to the first power terminal and extends along the first direction. extend;
  • the first power line On a plane parallel to the display substrate, in the first direction, the first power line is located on the side of the third capacitor away from the control electrode of the eighth transistor; in the second direction, the first power line
  • the control electrode of the fourteenth transistor is located on a side away from the control electrode of the thirteenth transistor.
  • the orthographic projection of the first power line on the substrate is respectively the same as the first pole of the ninth transistor, the first pole of the twelfth transistor, and the first pole of the fourteenth transistor on the substrate. Orthographic projections at least partially overlap;
  • the first pole of the eighth transistor and the first pole of the ninth transistor in the third conductive layer are integrally formed.
  • the first conductive layer further includes a first signal output line and a second signal output line; the first signal output line is in a strip shape and extends along the first direction, and the second signal output line is The shape of the signal output line is "L" shaped;
  • the first signal output line is located between the control electrode of the thirteenth transistor and the first power line, and the first signal output line and the tenth
  • the control pole of the four transistors has an integrated structure, and the second signal output line is located on the side of the first power line away from the first signal output line; in the first direction, the first signal output line is located on the fourteenth
  • the control electrode of the transistor is on a side away from the control electrode of the twelfth transistor, and the second signal output line is on a side of the first plate of the third capacitor away from the control electrode of the eighth transistor.
  • the first conductive layer further includes a second connection line, and the second connection line, the first plate of the third capacitor, and the control electrode of the ninth transistor have an integrated structure,
  • the shape of the control electrode of the eleventh transistor is "L" shaped;
  • the third conductive layer also includes a fourth connection line, first electrodes and second electrodes of the first to fourteenth transistors.
  • the fourth connection line is in the shape of a zigzag line and extends along the second direction.
  • the orthographic projection of the fourth connection line on the substrate at least partially overlaps with the orthographic projection of the control electrode of the eleventh transistor and the first plate of the third capacitor on the substrate respectively;
  • the second electrode of the ninth transistor includes a third structure and a fourth structure connected to each other.
  • the third structure is strip-shaped and extends along the first direction. It is located between the second electrode of the eighth transistor and the fourth structure.
  • the fourth connecting lines are connected to the fourth structure at one end close to the fourth connecting lines; the fourth structure is strip-shaped and extends along the second direction, close to the third One end of the structure is connected to a third structure.
  • the second electrode of the thirteenth transistor includes a fifth structure and a sixth structure connected to each other.
  • the fifth structure is strip-shaped and extends along the first direction and is located at the tenth between the first pole of the three transistors and the first pole of the fourteenth transistor;
  • the sixth structure is in an "L" shape and is located between the first pole of the fourteenth transistor and the second power line in the first direction , the side close to the first pole of the thirteenth transistor in the second direction is connected to the fifth structure, and the orthographic projection of the sixth structure on the substrate is the same as the orthogonal projection of the second signal output line on the substrate.
  • the projections overlap at least partially;
  • the first pole of the twelfth transistor and the first pole of the fourteenth transistor are both in an "L" shape and are located on the side of the fourth connection line away from the third power line.
  • the shift register includes: first to fourteenth transistors
  • all transistors and capacitors are located between the third power line and the second power line.
  • the second capacitor is located between the third power line and the eighth transistor.
  • the transistor is located between the second capacitor and the ninth and tenth transistors.
  • the ninth and tenth transistors are located between the eighth transistor and the second power line.
  • the eleventh and twelfth transistors are located between the third power line and the second power line.
  • the thirteenth transistor and the fourteenth transistor are located between the eleventh transistor and the twelfth transistor and the second power line; in the second direction, the thirteenth transistor, The fourteenth transistor, the third capacitor, the ninth transistor, the tenth transistor, and the first capacitor are arranged in sequence along the second direction.
  • the first conductive layer further includes a first power line, and the first power line is connected to the first power terminal; the first power line is in an "L" shape;
  • the first power line In the plane of the first conductive layer, in the first direction, the first power line is located on the side of the first plate of the third capacitor away from the first plate of the second capacitor; in the second direction , the first power line is located between the control electrode of the fourteenth transistor and the first plate of the first capacitor.
  • an orthographic projection of the first power line on the substrate at least partially overlaps an orthographic projection of the first electrode of the ninth transistor on the substrate;
  • the first pole of the eighth transistor and the first pole of the ninth transistor in the third conductive layer are integrally formed.
  • the first conductive layer further includes a power connection line
  • the second conductive layer further includes a first signal output line and a second signal output line
  • the first signal output line and the third signal output line The shapes of the two signal output lines are polygonal lines extending along the first direction;
  • the first signal output line is located between the second plate of the first capacitor and the second plate of the third capacitor.
  • the second plate of the third capacitor is located on a side away from the second plate of the first capacitor; in the first direction, the first signal output line and the second signal output line are both located on the third capacitor. The side of the second plate away from the second plate of the second capacitor;
  • the power connection line is of "n" type and is located on the side of the control electrode of the thirteenth transistor away from the control electrode of the fourteenth transistor in the second direction, and is provided with an opening on the side away from the thirteenth transistor.
  • the orthographic projection of the power connection line on the substrate at least partially overlaps with the orthographic projection of the second power line and the first electrode of the thirteenth transistor on the substrate respectively.
  • the first conductive layer further includes a second connection line, and the second connection line is connected to the first plate of the third capacitor, the control electrode of the ninth transistor, and the first plate of the third capacitor.
  • the control electrode of the eleventh transistor is integrally formed, the control electrode of the eleventh transistor is in an "n" shape, and is provided with an opening toward one side of the twelfth transistor;
  • the third conductive layer also includes first and second electrodes of the first to fourteenth transistors, and the second electrode of the ninth transistor includes third, fourth and ninth structures connected to each other,
  • the third structure is strip-shaped and extends along the first direction. It is located between the second pole of the eighth transistor and the second power line, between an end close to the second power line and the second power line.
  • the fourth structure is connected; the shape of the fourth structure is a strip, located on the side of the second power line close to the third power line, and extends along the second direction, close to one end of the third structure and the third structure Connection; the shape of the ninth structure is a strip, located on the side of the fourth structure away from the second power line, and the orthographic projection of the fourth structure on the substrate is consistent with the control electrode of the fourth transistor on the substrate. Orthographic projections overlap at least partially.
  • the second pole of the thirteenth transistor has a strip-shaped structure and extends along the first direction
  • the first pole of the thirteenth transistor includes a seventh structure and an eighth structure connected to each other, and the The seventh structure is strip-shaped and extends along the first direction. One end is connected to the first pole of the eleventh transistor, and the other end is connected to the eighth structure.
  • the eighth structure is a square structure and is integrated with the seventh structure. Molding, the orthographic projection of the eighth structure on the base at least partially overlaps the orthographic projection of the power connection line on the base;
  • the first poles of the twelfth transistor and the fourteenth transistor are strip structures extending along the first direction and connected to each other. One end of the first pole of the twelfth transistor is connected to the third power line, and the other end is connected to the third power line. The first pole of the fourteenth transistor is connected to the side of the first pole of the twelfth transistor away from the third power line. The first pole of the twelfth transistor is connected to the tenth power line.
  • the first pole of the four transistors and the third power line have an integrated structure.
  • the third conductive layer further includes a signal input line.
  • the signal input line is in the shape of a polygonal line and extends along the first direction. In the plane where the third conductive layer is located, in the first direction upward, the signal input line is located between the third power line and the second power line; in the second direction, the signal input line is located on the side of the tenth transistor away from the ninth transistor;
  • the second plate of the second capacitor and the first plate of the third capacitor are arranged along the first direction. In the second direction, the second plate of the second capacitor The second plate of the third capacitor and the second plate of the third capacitor are located on the same side of the second plate of the first capacitor;
  • the shape of the second plate of the first capacitor is a polygonal line and extends along the first direction.
  • the orthographic projection of the second plate of the first capacitor on the base is the same as the orthogonal projection of the first plate of the first capacitor on the base.
  • There is an overlapping area in the orthographic projection; the shape of the second plate of the second capacitor is square, and the orthographic projection of the second plate of the second capacitor on the substrate overlaps with the orthographic projection of the first plate of the second capacitor on the substrate.
  • area; the shape of the second electrode plate of the third capacitor may be strip-shaped and extend along the first direction, and the orthographic projection of the second electrode plate of the third capacitor on the substrate is in line with the first electrode plate of the third capacitor. Orthographic projections on the substrate have overlapping areas.
  • the signal input line and the first pole of the first transistor are integrally formed.
  • any one of the ninth transistor, the tenth transistor, the thirteenth transistor and the fourteenth transistor includes four sub-transistors connected in parallel, and in any one In the transistor, the active layers of the four sub-transistors are arranged independently of each other, the control poles of the four sub-transistors have an integrated structure, the first poles of the four sub-transistors have an integrated structure, and the second poles of the four sub-transistors have an integrated structure.
  • the first transistor, the fourth transistor to the seventh transistor are located between the third power line and the third power line. Between the two capacitors, the second transistor and the third transistor are located between the fifth transistor and the first capacitor.
  • the third conductive layer includes first and second electrodes of the first to fourteenth transistors, the second electrode of the sixth transistor and the first electrode of the seventh transistor. Sharing one electrode, the second pole of the ninth transistor and the second pole of the tenth transistor share one electrode, and the second pole of the thirteenth transistor and the second pole of the fourteenth transistor share one electrode .
  • the first power line and the second power line provide the same power signal.
  • an embodiment of the present disclosure further provides a display device, including the display substrate described in any of the above embodiments.
  • an embodiment of the present disclosure also provides a method for driving a shift register, which is configured to drive the shift register described in any of the above embodiments.
  • the method includes:
  • the first control sub-circuit Under the control of the first clock signal terminal, the second clock signal terminal, the second node and the first power terminal, the first control sub-circuit provides the signal of the signal input terminal to the first node and maintains the potential of the first node;
  • the second control subcircuit Under the control of the first clock signal terminal and the first node, the second control subcircuit provides the signal of the second power terminal or the first clock signal terminal to the second node;
  • the third control subcircuit Under the control of the second clock signal terminal, the first node, and the second node, the third control subcircuit provides the signal of the second clock signal terminal or the first power terminal to the fourth node, and maintains the potential of the fourth node;
  • the first output sub-circuit Under the control of the first node and the fourth node, the first output sub-circuit provides the signal of the first power terminal or the second power terminal to the first signal output terminal;
  • the second output sub-circuit Under the control of the third control sub-circuit and the first signal output terminal, the second output sub-circuit provides the signal of the first power terminal or the second power terminal to the second signal output terminal.
  • Figure 1 shows a schematic structural diagram of a display device
  • Figure 2 shows a schematic plan view of a display substrate
  • Figure 3 shows a schematic cross-sectional structural diagram of a display substrate
  • Figure 4 shows an equivalent circuit diagram of a pixel driving circuit
  • Figure 5 shows the working timing diagram of a pixel driving circuit
  • Figure 6 shows a schematic structural diagram of a shift register provided by an embodiment of the present disclosure
  • Figure 7 shows an equivalent circuit diagram of a shift register provided by an exemplary embodiment of the present disclosure
  • Figure 8 shows an operating timing diagram of a shift register provided by an exemplary embodiment of the present disclosure
  • Figure 9a shows an equivalent circuit diagram of a shift register provided by an exemplary embodiment of the present disclosure
  • Figure 9b shows an equivalent circuit diagram of a shift register provided by an exemplary embodiment of the present disclosure
  • Figure 9c shows an equivalent circuit diagram of a shift register provided by an exemplary embodiment of the present disclosure
  • Figure 10a shows an equivalent circuit diagram of a pixel driving circuit
  • Figure 10b shows the working timing diagram of a pixel driving circuit
  • Figure 11 shows a schematic diagram of a display substrate provided by an exemplary embodiment of the present disclosure after forming an active layer pattern
  • Figure 12a shows a schematic diagram of a display substrate provided by an exemplary embodiment of the present disclosure after forming a first conductive layer pattern
  • Figure 12b shows a schematic diagram of the first conductive layer in the display substrate provided by an exemplary embodiment of the present disclosure
  • Figure 13a shows a schematic diagram of a display substrate provided by an exemplary embodiment of the present disclosure after forming a second conductive layer pattern
  • Figure 13b shows a schematic diagram of the second conductive layer in the display substrate provided by an exemplary embodiment of the present disclosure
  • Figure 14 shows a schematic diagram of a third insulating layer pattern formed on a display substrate according to an exemplary embodiment of the present disclosure
  • Figure 15a shows a schematic diagram of a display substrate provided by an exemplary embodiment of the present disclosure after forming a third conductive layer pattern
  • Figure 15b shows a schematic diagram of the third conductive layer in the display substrate provided by an exemplary embodiment of the present disclosure
  • Figure 16 shows a schematic diagram of a display substrate provided by an exemplary embodiment of the present disclosure after forming an active layer pattern
  • Figure 17a shows a schematic diagram of a display substrate provided by an exemplary embodiment of the present disclosure after forming a first conductive layer pattern
  • Figure 17b shows a schematic diagram of the first conductive layer in the display substrate provided by an exemplary embodiment of the present disclosure
  • Figure 18a shows a schematic diagram of a display substrate provided by an exemplary embodiment of the present disclosure after forming a second conductive layer pattern
  • Figure 18b shows a schematic diagram of the second conductive layer in the display substrate provided by an exemplary embodiment of the present disclosure
  • Figure 19 shows a schematic diagram of the display substrate after forming a third insulating layer pattern
  • Figure 20a shows a schematic diagram of a display substrate provided by an exemplary embodiment of the present disclosure after forming a third conductive layer pattern
  • Figure 20b shows a schematic diagram of the third conductive layer in the display substrate provided by an exemplary embodiment of the present disclosure
  • FIG. 21 is a schematic diagram of the cascade relationship of multiple shift registers in a display substrate according to an exemplary embodiment of the present disclosure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode .
  • the channel region refers to the region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged with each other. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged with each other, and “source terminal” and “drain terminal” can be interchanged with each other.
  • the gate electrode may be called a control electrode.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • component having some electrical function There is no particular limitation on the “component having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • elements having some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • film and “layer” may be interchanged.
  • conductive layer may sometimes be replaced by “conductive film.”
  • insulating film may sometimes be replaced by “insulating layer”.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not strictly speaking. They can be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances. There can be leading angles, arc edges, deformations, etc.
  • FIG. 1 shows a schematic structural diagram of a display device.
  • the display substrate may include a timing controller, a data signal driver, a scanning signal driver, a light emitting signal driver and a pixel array.
  • the timing controller is connected to the data signal driver, scanning signal driver and light emitting device respectively.
  • the signal driver is connected, the data signal driver is connected to multiple data signal lines (D1 to Dn), the scanning signal driver is connected to multiple scanning signal lines (S1 to Sm), and the light-emitting signal driver is connected to multiple light-emitting signal lines (E1 to Eo) connection.
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit, and the circuit unit may include at least one scanning signal line, at least one data signal line, At least one light-emitting signal line and pixel driving circuit.
  • the timing controller may provide a gray value and a control signal suitable for the specifications of the data signal driver to the data signal driver, and may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan signal driver.
  • a clock signal, an emission stop signal, and the like suitable for the specifications of the light-emitting signal driver can be provided to the scanning signal driver.
  • the data signal driver may generate data voltages to be provided to the data signal lines D1, D2, D3, . . . and Dn using the grayscale values and control signals received from the timing controller. For example, the data signal driver may sample the grayscale value using a clock signal and apply a data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number.
  • the scan signal driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . . and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan signal driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm.
  • the scan signal driver may be configured in the form of a shift register, and may generate the scan in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-stage circuit under the control of a clock signal.
  • Signal, m can be a natural number.
  • the light-emitting signal driver may generate emission signals to be provided to the light-emitting signal lines E1, E2, E3, . . . and Eo by receiving a clock signal, an emission stop signal, or the like from the timing controller.
  • the light-emitting signal driver may sequentially provide emission signals with off-level pulses to the light-emitting signal lines E1 to Eo.
  • the light-emitting driver may be configured in the form of a shift register, and may generate the emission signal in a manner that sequentially transmits an emission stop signal provided in the form of a cut-off level pulse to a next-stage circuit under the control of a clock signal, o Can be a natural number.
  • Figure 2 is a schematic plan view of a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first sub-pixel P1 that emits light of a first color, and a second sub-pixel that emits light of a second color.
  • the sub-pixel P2 and the third sub-pixel P3 that emit light of the third color, the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 all include a pixel driving circuit and a light-emitting device.
  • the pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are respectively connected to the scanning signal line, the data signal line and the light-emitting signal line.
  • the pixel driving circuit is configured to connect the scanning signal line and the light-emitting signal line. Under the control of the data signal line, the data voltage transmitted by the data signal line is received, and a corresponding current is output to the light-emitting device.
  • the light-emitting devices in the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting devices are configured to emit corresponding signals in response to the current output by the pixel driving circuit of the sub-pixel. Brightness of light.
  • the pixel unit P may include red (R) sub-pixels, green (G) sub-pixels, and blue (B) sub-pixels.
  • R red
  • G green
  • B blue
  • the shape of the sub-pixels in the pixel unit may be rectangular, rhombus, pentagon or hexagon, and the three sub-pixels may be arranged horizontally, vertically or vertically. The present disclosure is here No restrictions.
  • Figure 3 is a schematic cross-sectional structural diagram of a display substrate, illustrating the structure of three sub-pixels of the OLED display substrate.
  • the display substrate may include a driving circuit layer 102 disposed on a substrate 101 , a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101 , and a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101 .
  • the structural layer 103 is away from the packaging layer 104 on one side of the substrate 101.
  • the display substrate may include other film layers, such as spacer pillars, etc., which are not limited in this disclosure.
  • substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit.
  • the light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304.
  • the anode 301 is connected to the drain electrode of the driving transistor 210 through a via hole
  • the organic light-emitting layer 303 is connected to the anode 301
  • the cathode 304 is connected to the organic light-emitting layer 301.
  • the layers 303 are connected, and the organic light-emitting layer 303 emits light of corresponding colors driven by the anode 301 and the cathode 304.
  • the encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403.
  • the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials
  • the second encapsulation layer 402 may be made of organic materials. material
  • the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.
  • the organic light-emitting layer 303 may include a stacked hole injection layer (Hole Injection Layer, referred to as HIL), a hole transport layer (Hole Transport Layer, referred to as HTL), and an electron blocking layer (Electron Block Layer, EBL for short), Emitting Layer (EML for short), Hole Block Layer (HBL for short), Electron Transport Layer (ETL for short) and Electron Injection Layer (EIL for short) .
  • HIL Hole Injection Layer
  • HTL hole transport layer
  • EBL Electron blocking layer
  • EBL Electron Transport Layer
  • EIL Electron Injection Layer
  • the hole injection layers of all sub-pixels may be a common layer connected together
  • the electron injection layers of all sub-pixels may be a common layer connected together
  • the hole transport layers of all sub-pixels may be A common layer connected together
  • the electron transport layer of all sub-pixels can be a common layer connected together
  • the hole blocking layer of all sub-pixels can be a common layer connected together
  • the light-emitting layers of adjacent sub-pixels can have a small amount of
  • the electron blocking layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure.
  • Figure 4 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 4, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C, and the pixel driving circuit may be connected to 7 signal lines (data signal line D, first scanning The signal line S1, the second scanning signal line S2, the light emitting signal line E, the initial signal line INIT, the first power supply line VDD and the second power supply line VSS) are connected.
  • the pixel driving circuit may include a first node N1, a second node N2, and a third node N3.
  • the first node N1 is respectively connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4 and the second pole of the fifth transistor T5, and the second node N2 is respectively connected to the second pole of the first transistor T1.
  • the first electrode of the second transistor T2, the control electrode of the third transistor T3 are connected to the second end of the storage capacitor C
  • the third node N3 is respectively connected to the second electrode of the second transistor T2 and the second electrode of the third transistor T3. is connected to the first pole of the sixth transistor T6.
  • the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the third transistor T3. Control pole connection.
  • the control electrode of the first transistor T1 is connected to the second scanning signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2.
  • the first transistor T1 transmits the initializing voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.
  • the control electrode of the second transistor T2 is connected to the first scanning signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, and the first electrode of the third transistor T3 is connected to the first node N1.
  • the second pole of T3 is connected to the third node N3.
  • the third transistor T3 may be called a driving transistor, and the third transistor T3 determines the amount of the driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.
  • the control electrode of the fourth transistor T4 is connected to the first scanning signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 may be called a switching transistor, a scanning transistor, or the like.
  • the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.
  • the control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device.
  • the fifth transistor T5 and the sixth transistor T6 may be called light emitting transistors.
  • the fifth and sixth transistors T5 and T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.
  • the control electrode of the seventh transistor T7 is connected to the first scanning signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device.
  • the seventh transistor T7 transmits the initializing voltage to the first pole of the light-emitting device, so that the amount of charge accumulated in the first pole of the light-emitting device is initialized or released to emit light. The amount of charge accumulated in the first pole of the device.
  • the second pole of the light-emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD continuously provides a high-level signal.
  • the first scanning signal line S1 is the scanning signal line in the pixel driving circuit of this display row
  • the second scanning signal line S2 is the scanning signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scanning signal line Line S1 is S(n), and the second scanning signal line S2 is S(n-1).
  • the second scanning signal line S2 of this display row is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display row. Signal lines can reduce the signal lines of the display panel and achieve a narrow frame of the display panel.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel drive circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.
  • the first scanning signal line S1, the second scanning signal line S2, the light emitting signal line E and the initial signal line INIT extend in the horizontal direction
  • the second power supply line VSS, the first power supply line VDD and the data signal line D extends in the vertical direction.
  • the light-emitting device may be an organic electroluminescent diode (OLED) including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode).
  • OLED organic electroluminescent diode
  • FIG. 5 is a working timing diagram of a pixel driving circuit. An exemplary embodiment will be described below through the working process of the pixel driving circuit illustrated in FIG. 4 .
  • the pixel driving circuit in FIG. 4 includes 7 transistors (first transistor T1 to seventh transistor T7 ), 1 storage capacitor C and 7 transistors.
  • signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, initial signal line INIT, first power supply line VDD and second power supply line VSS), 7 transistors are It is a P-type transistor.
  • the working process of the pixel driving circuit may include:
  • the first phase A1 is called the reset phase.
  • the signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals.
  • the signal of the second scanning signal line S2 is a low-level signal, turning on the first transistor T1.
  • the signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, causing the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 to turn off. At this stage, the OLED Not glowing.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scanning signal line S1 is a low-level signal
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are high-level signals
  • the data The signal line D outputs the data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scanning signal line S1 is a low-level signal, which turns on the second transistor T2, the fourth transistor T4 and the seventh transistor T7.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the second transistor through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2.
  • Node N2 and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C.
  • the voltage at the second end of the storage capacitor C (the second node N2) is Vd-
  • the seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is provided to the first pole of the OLED, initializing (resetting) the first pole of the OLED, clearing its internal pre-stored voltage, completing the initialization, and ensuring that the OLED does not emit light.
  • the signal of the second scanning signal line S2 is a high-level signal, causing the first transistor T1 to turn off.
  • the signal of the light-emitting signal line E is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to be turned off.
  • the third stage A3 is called the light-emitting stage.
  • the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals.
  • the signal of the light-emitting signal line E is a low-level signal, causing the fifth transistor T5 and the sixth transistor T6 to be turned on.
  • the power supply voltage output by the first power supply line VDD passes through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6.
  • the transistor T6 provides a driving voltage to the first pole of the OLED to drive the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the third transistor T3, that is, the driving current that drives the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3.
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power supply line VDD.
  • the luminescent signal driver usually uses an Emitting Gate Driver on Array (EM GOA) circuit.
  • EM GOA Emitting Gate Driver on Array
  • the commonly used EM GOA circuit usually outputs a luminescent signal (EM).
  • EM luminescent signal
  • OLED display The requirements for the driving signals generated by the product's driving circuit have also increased.
  • the commonly used EM GOA circuit cannot output different types of luminous signals and cannot meet the needs for different luminous signals in practical applications.
  • the shift register includes a first control subcircuit, a second control subcircuit, a third control subcircuit, a first output subcircuit, a second Output subcircuit;
  • the first control subcircuit is respectively connected to the signal input terminal IN, the first node N1, the second node N2, the first clock signal terminal CLK, the second clock signal terminal CLKB and the first power supply terminal VGH, and is configured to operate on the first clock Under the control of the signal terminal CLK, the second clock signal terminal CLKB, the second node N2 and the first power terminal VGH, the signal of the signal input terminal IN is provided to the first node N1, and the potential of the first node N1 is maintained;
  • the second control subcircuit is respectively connected to the second power terminal VGL, the first clock signal terminal CLK, the first node N1 and the second node N2, and is configured to be under the control of the first clock signal terminal CLK and the first node N1, Provide a signal of the second power terminal VGL or the first clock signal terminal CLK to the second node N2;
  • the third control sub-circuit is respectively connected to the first node N1, the second node N2, the fourth node N4, the second clock signal terminal CLKB and the first power terminal VGH, and is configured to operate between the second clock signal terminal CLKB and the first node Under the control of N1 and the second node N2, provide the signal of the second clock signal terminal CLKB or the first power terminal VGH to the fourth node N4, and maintain the potential of the fourth node N4;
  • the first output sub-circuit is respectively connected to the first power terminal VGH, the second power terminal VGL, the first node N1, the fourth node N4 and the first signal output terminal EM_OUT, and is configured to connect the first node N1 and the fourth node N4 Provide the signal of the first power terminal VGH or the second power terminal VGL to the first signal output terminal EM_OUT under the control of
  • the second output sub-circuit is respectively connected to the first signal output terminal EM_OUT, the third control sub-circuit, the first power terminal VGH, the second power terminal VGL and the second signal output terminal IEM_OUT, and is configured to connect between the third control sub-circuit and the second signal output terminal IEM_OUT.
  • the signal of the first power terminal VGH or the second power terminal VGL is provided to the second signal output terminal IEM_OUT.
  • the shift register provided by the embodiment of the present disclosure includes a first control subcircuit, a second control subcircuit, a third control subcircuit, a first output subcircuit, and a second output subcircuit.
  • the first output subcircuit can be in the first The node and the fourth node provide the signal of the first power terminal or the second power terminal to the first signal output terminal, and the second output sub-circuit can provide the second signal to the second signal output terminal under the control of the third control sub-circuit and the first signal output terminal.
  • the output terminal provides signals from the first power terminal or the second power terminal, and the first sub-output circuit and the second sub-output circuit output signals to the first signal output terminal and the second signal output terminal respectively, which can meet the needs for different signals. It overcomes the problem of being unable to meet the different signal requirements in practical applications.
  • the signal output by the first signal output terminal EM_OUT and the signal output by the second signal output terminal IEM_OUT are mutually inverted signals.
  • the signals output by the first signal output terminal EM_OUT and the second signal output terminal IEM_OUT are mutually inverted signals.
  • the shift register can be an Emitting Gate Driver on Array (EM GOA) circuit.
  • EM GOA Emitting Gate Driver on Array
  • the same EM GOA circuit can output different types of luminous signals to meet the needs for different luminous signals in practical applications.
  • the same EM GOA circuit can provide a pulse-width adjustable luminescence signal (EM signal) and a luminescence signal IEM signal that is inverse to the EM signal, which greatly improves the integration of the circuit. .
  • EM signal pulse-width adjustable luminescence signal
  • IEM signal luminescence signal
  • the first control sub-circuit may include a first transistor T1, a fourth transistor T4, a fifth transistor T5 and a first capacitor C1.
  • the first capacitor C1 It includes a first plate C11 and a second plate C12;
  • the control electrode of the first transistor T1 is connected to the first clock signal terminal CLK, the first electrode of the first transistor T1 is connected to the signal input terminal IN, and the second electrode of the first transistor T1 is connected to the first node N1;
  • the control electrode of the fourth transistor T4 is connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the first power terminal VGH, and the second electrode of the fourth transistor T4 is connected to the seventh node N7;
  • the control electrode of the fifth transistor T5 is connected to the second clock signal terminal CLKB, the first electrode of the fifth transistor T5 is connected to the seventh node N7, and the second electrode of the fifth transistor T5 is connected to the first node N1;
  • the first plate C11 of the first capacitor C1 is connected to the first node N1, and the second plate C12 of the first capacitor C1 is connected to the second clock signal terminal CLKB.
  • the first control sub-circuit may include a first transistor T1, a fourth transistor T4, a fifth transistor T5, a first capacitor C1 and a fourth capacitor C4.
  • the first capacitor C1 may Comprising a first plate C11 and a second plate C12
  • the fourth capacitor C4 may include a first plate C41 and a second plate C42;
  • the control electrode of the first transistor T1 is connected to the first clock signal terminal CLK, the first electrode of the first transistor T1 is connected to the signal input terminal IN, and the second electrode of the first transistor T1 is connected to the first node N1;
  • the control electrode of the fourth transistor T4 is connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the first power terminal VGH, and the second electrode of the fourth transistor T4 is connected to the seventh node N7;
  • the control electrode of the fifth transistor T5 is connected to the first node N1, the first electrode of the fifth transistor T5 is connected to the second clock signal terminal CLKB, and the second electrode of the fifth transistor T5 is connected to the seventh node N7;
  • the first plate C11 of the first capacitor C1 is connected to the first node N1, and the second plate C12 of the first capacitor C1 is connected to the first signal output terminal EM_OUT;
  • the first plate C41 of the fourth capacitor C4 is connected to the seventh node N7, and the second plate C42 of the fourth capacitor C4 is connected to the first node N1.
  • the second control sub-circuit may include a second transistor T2 and a third transistor T3;
  • the control electrode of the second transistor T2 is connected to the first clock signal terminal CLK, the first electrode of the second transistor T2 is connected to the second power supply terminal VGL, and the second electrode of the second transistor T2 is connected to the second node N2;
  • the control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the first clock signal terminal CLK, and the second electrode of the third transistor T3 is connected to the second node N2.
  • the third control sub-circuit may include a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a second capacitor C2 and a third capacitor C3. ;
  • the control electrode of the sixth transistor T6 is connected to the second node N2, the first electrode of the sixth transistor T6 is connected to the second clock signal terminal CLKB, and the second electrode of the sixth transistor T6 is connected to the third node N3;
  • the control electrode of the seventh transistor T7 is connected to the second clock signal terminal CLKB, the first electrode of the seventh transistor T7 is connected to the third node N3, and the second electrode of the seventh transistor T7 is connected to the fourth node N4;
  • the control electrode of the eighth transistor T8 is connected to the first node N1, the first electrode of the eighth transistor T8 is connected to the first power supply terminal VGH, and the second electrode of the eighth transistor T8 is connected to the fourth node N4;
  • the first plate C21 of the second capacitor C2 is connected to the second node N2, and the second plate C22 of the second capacitor C2 is connected to the third node N3;
  • the first plate C31 of the third capacitor C3 is connected to the fourth node N4, and the second plate C32 of the third capacitor C3 is connected to the first power terminal VGH.
  • the first output sub-circuit may include a ninth transistor T9 and a tenth transistor T10;
  • the control electrode of the ninth transistor T9 is connected to the fourth node N4, the first electrode of the ninth transistor T9 is connected to the first power supply terminal VGH, and the second electrode of the ninth transistor T9 is connected to the first signal output terminal EM_OUT;
  • the control electrode of the tenth transistor T10 is connected to the first node N1, the first electrode of the tenth transistor T10 is connected to the second power supply terminal VGL, and the second electrode of the tenth transistor T10 is connected to the first signal output terminal EM_OUT.
  • the second output sub-circuit may include an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14;
  • the control electrode of the eleventh transistor T11 is connected to the third control sub-circuit, the first electrode of the eleventh transistor T11 is connected to the second power supply terminal VGL, and the second electrode of the eleventh transistor T11 is connected to the sixth node N6; for example , the control electrode of the eleventh transistor T11 can be connected to the third node N3 (shown in Figure 7) or the fourth node N4 (shown in Figure 9a);
  • the control electrode of the twelfth transistor T12 is connected to the first signal output terminal EM_OUT, the first electrode of the twelfth transistor T12 is connected to the first power supply terminal VGH, and the second electrode of the twelfth transistor T12 is connected to the sixth node N6;
  • the control electrode of the thirteenth transistor T13 is connected to the sixth node N6, the first electrode of the thirteenth transistor T13 is connected to the second power supply terminal VGL, and the second electrode of the thirteenth transistor T13 is connected to the second signal output terminal IEM_OUT;
  • the control electrode of the fourteenth transistor T14 is connected to the first signal output terminal EM_OUT, the first electrode of the fourteenth transistor T14 is connected to the first power supply terminal VGH, and the second electrode of the fourteenth transistor T14 is connected to the second signal output terminal IEM_OUT. connect.
  • the second output sub-circuit may further include a fifth capacitor C5, and the fifth capacitor C5 includes a first plate C51 and a second plate C52;
  • the first plate C51 of the fifth capacitor C5 is connected to the sixth node N6, and the second plate C52 of the fifth capacitor C5 is connected to the first clock signal terminal CLK or the second clock signal terminal CLKB.
  • the first control sub-circuit may include a first transistor T1, a fourth transistor T4, a fifth transistor T5 and a first capacitor C1.
  • the first capacitor C1 includes a first Plate C11 and second plate C12;
  • the second control sub-circuit may include a second transistor T2 and a third transistor T3;
  • the third control sub-circuit may include a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, The second capacitor C2 and the third capacitor C3;
  • the first output sub-circuit may include a ninth transistor T9 and a tenth transistor T10;
  • the second output sub-circuit may include an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13. and the fourteenth transistor T14;
  • the control electrode of the first transistor T1 is connected to the first clock signal terminal CLK, the first electrode of the first transistor T1 is connected to the signal input terminal IN, and the second electrode of the first transistor T1 is connected to the first node N1;
  • the control electrode of the second transistor T2 is connected to the first clock signal terminal CLK, the first electrode of the second transistor T2 is connected to the second power supply terminal VGL, and the second electrode of the second transistor T2 is connected to the second node N2;
  • the control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the first clock signal terminal CLK, and the second electrode of the third transistor T3 is connected to the second node N2;
  • the control electrode of the fourth transistor T4 is connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the first power terminal VGH, and the second electrode of the fourth transistor T4 is connected to the seventh node N7;
  • the control electrode of the fifth transistor T5 is connected to the second clock signal terminal CLKB, the first electrode of the fifth transistor T5 is connected to the seventh node N7, and the second electrode of the fifth transistor T5 is connected to the first node N1;
  • the control electrode of the sixth transistor T6 is connected to the second node N2, the first electrode of the sixth transistor T6 is connected to the second clock signal terminal CLKB, and the second electrode of the sixth transistor T6 is connected to the third node N3;
  • the control electrode of the seventh transistor T7 is connected to the second clock signal terminal CLKB, the first electrode of the seventh transistor T7 is connected to the third node N3, and the second electrode of the seventh transistor T7 is connected to the fourth node N4;
  • the control electrode of the eighth transistor T8 is connected to the first node N1, the first electrode of the eighth transistor T8 is connected to the first power supply terminal VGH, and the second electrode of the eighth transistor T8 is connected to the fourth node N4;
  • the control electrode of the ninth transistor T9 is connected to the fourth node N4, the first electrode of the ninth transistor T9 is connected to the first power supply terminal VGH, and the second electrode of the ninth transistor T9 is connected to the first signal output terminal EM_OUT;
  • the control electrode of the tenth transistor T10 is connected to the first node N1, the first electrode of the tenth transistor T10 is connected to the second power supply terminal VGL, and the second electrode of the tenth transistor T10 is connected to the first signal output terminal EM_OUT;
  • the control electrode of the eleventh transistor T11 is connected to the third node N3 or the fourth node N4, the first electrode of the eleventh transistor T11 is connected to the second power supply terminal VGL, and the second electrode of the eleventh transistor T11 is connected to the sixth node. N6 connection;
  • the control electrode of the twelfth transistor T12 is connected to the first signal output terminal EM_OUT, the first electrode of the twelfth transistor T12 is connected to the first power supply terminal VGH, and the second electrode of the twelfth transistor T12 is connected to the sixth node N6;
  • the control electrode of the thirteenth transistor T13 is connected to the sixth node N6, the first electrode of the thirteenth transistor T13 is connected to the second power supply terminal VGL, and the second electrode of the thirteenth transistor T13 is connected to the second signal output terminal IEM_OUT;
  • the control electrode of the fourteenth transistor T14 is connected to the first signal output terminal EM_OUT, the first electrode of the fourteenth transistor T14 is connected to the first power supply terminal VGH, and the second electrode of the fourteenth transistor T14 is connected to the second signal output terminal IEM_OUT. connect;
  • the first plate C11 of the first capacitor C1 is connected to the first node N1, and the second plate C12 of the first capacitor C1 is connected to the second clock signal terminal CLKB;
  • the first plate C21 of the second capacitor C2 is connected to the second node N2, and the second plate C22 of the second capacitor C2 is connected to the third node N3;
  • the first plate C31 of the third capacitor C3 is connected to the fourth node N4, and the second plate C32 of the third capacitor C3 is connected to the first power terminal VGH.
  • the first to fourteenth transistors T1 to T14 are P-type transistors.
  • FIG. 7 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment
  • Figure 8 is a working timing diagram of a shift register provided by an exemplary embodiment, as shown in Figures 7 and 8.
  • An exemplary embodiment involves a shift register including: 14 switching transistors (T1 to T14), 3 capacitor units (C1, C2, and C3), 3 signal input terminals (CLK, CLKB, and IN), 2 Signal output terminals (EM_OUT and IEM_OUT), 2 power supply terminals (VGH and VGL).
  • the first to fourteenth transistors T1 to T14 shown in FIG. 7 may all be P-type transistors.
  • the signal of the first power terminal VGH is a high-level signal
  • the signal of the second power terminal VGL is a low-level signal
  • the signal output by the first signal output terminal EM_OUT and the signal output by the second signal output terminal IEM_OUT are both signals with adjustable pulse width, and are inverse signals of each other, that is, the two have the same period and the opposite voltage. , and the pulse width can be adjusted according to the signal input by the signal input IN.
  • the duration of the active level signal at the signal input terminal IN may be one or more times the period of the clock signal of the first clock signal terminal CLK.
  • the duration of the active level signal at the signal input terminal IN may be three times the period of the clock signal at the first clock signal terminal CLK.
  • the working process of the shift register may include: a first stage P1 to a fifth stage P5.
  • the first stage P1 the signals of the signal input terminal IN and the second clock signal terminal CLKB are high-level signals, and the signal of the first clock signal terminal CLK is a low-level signal.
  • the low-level signal of the first clock signal terminal CLK turns on the first transistor T1 and the second transistor T2.
  • the high-level signal input from the signal input terminal IN is written into the first node N1 through the first transistor T1.
  • the first node N1 is high level
  • the third transistor T3, the eighth transistor T8, and the tenth transistor T10 are turned off, the signal of the second power terminal VGL cannot be written to the fifth node N5 through the tenth transistor T10, and the fifth node N5 maintains the previous frame.
  • the first signal output terminal EM_OUT outputs a low level signal; since the second transistor T2 is turned on, the low level signal of the second power supply terminal VGL is written into the second node N2 through the second transistor T2, and the second node N2 is low level, the fourth transistor T4 and the sixth transistor T6 are turned on, the signal of the first power terminal VGH is written into the seventh node N7 through the fourth transistor T4, the seventh node N7 is high level, the second clock signal
  • the high-level signal of the terminal CLKB turns off the fifth transistor T5, and the signal of the seventh node N7 cannot be written to the first node N1 through the fifth transistor T5.
  • the high-level signal of the second clock signal terminal CLKB passes through the sixth transistor T6.
  • the third node N3 is high level, the eleventh transistor T11 is turned off, because the signal of the second clock signal terminal CLKB is a high level signal, the seventh transistor T7 is turned off, the third node N3
  • the high-level signal cannot be written to the fourth node N4 through the seventh transistor T7, the fourth node N4 maintains the high level of the previous frame, the ninth transistor T9 is turned off, and the signal of the first power terminal VGH cannot pass through the ninth transistor.
  • T9 is written to the fifth node N5; since the fifth node N5 is low level, the twelfth transistor T12 and the fourteenth transistor T14 are turned on, and the signal of the first power supply terminal VGH is transmitted to the second signal through the fourteenth transistor T14
  • the output terminal IEM_OUT and the second signal output terminal IEM_OUT output a high level signal.
  • the signal of the first power supply terminal VGH is written into the sixth node N6 through the twelfth transistor T12.
  • the sixth node N6 is at a high level, and the thirteenth transistor T13 is disconnected, the signal of the second power supply terminal VGL cannot be output to the second signal output terminal IEM_OUT through the thirteenth transistor T13.
  • the first signal output terminal EM_OUT outputs a low-level signal
  • the second signal output terminal IEM_OUT outputs a high-level signal.
  • Second stage P2 The signals of the signal input terminal IN and the first clock signal terminal CLK are high-level signals, and the signal of the second clock signal terminal CLKB is a low-level signal.
  • the high-level signal of the first clock signal terminal CLK turns off the first transistor T1 and the second transistor T2, and the high-level signal input from the signal input terminal IN cannot be written to the first node N1 through the first transistor T1; due to the second The transistor T2 is turned off, and the low level signal of the second power terminal VGL cannot be written to the second node N2 through the second transistor T2.
  • the second node N2 maintains the low level of the previous frame, and the fourth transistor T4 and the sixth transistor T6 is turned on.
  • the fifth transistor T5 is turned on, and the signal of the first power supply terminal VGH is written into the first node N1 through the fourth transistor T4 and the fifth transistor T5.
  • One node N1 is at a high level
  • the third transistor T3, the eighth transistor T8, and the tenth transistor T10 are turned off, and the signal of the second power supply terminal VGL cannot be written to the fifth node N5 through the tenth transistor T10, because the sixth transistor T6 is turned on, the low-level signal of the second clock signal terminal CLKB is written into the third node N3 through the sixth transistor T6, the third node N3 is low-level, and the low-level signal of the second clock signal terminal CLKB causes the seventh transistor to T7 is turned on, the low level signal of the third node N3 is written into the fourth node N4 through the seventh transistor T7, the fourth node N4 is low level, the ninth transistor T9 is turned on, and the signal of the first power supply terminal VGH
  • the ninth transistor T9 is written to the fifth node N5, the fifth node N5 is high level, and the first signal output terminal EM_OUT outputs a high level signal; because the fifth node N5 is high level, the twelfth transistor T12 and the fourteenth transistor T12 The transistor T14 is turned off, the signal of the first power terminal VGH cannot be transmitted to the second signal output terminal IEM_OUT through the fourteenth transistor T14, and the signal of the first power terminal VGH cannot be written to the sixth node N6 through the twelfth transistor T12.
  • the eleventh transistor T11 Since the third node N3 is low level, the eleventh transistor T11 is turned on, and the low level signal of the second power terminal VGL is written into the sixth node N6 through the eleventh transistor T11, and the sixth node N6 is low level.
  • the thirteenth transistor T13 is turned on, and the signal of the second power supply terminal VGL is transmitted to the second signal output terminal IEM_OUT through the thirteenth transistor T13.
  • the second signal output terminal IEM_OUT outputs a low level signal.
  • the first signal output terminal EM_OUT outputs a high-level signal
  • the second signal output terminal IEM_OUT outputs a low-level signal.
  • the third stage P3 the signals of the signal input terminal IN and the second clock signal terminal CLKB are high-level signals, and the signal of the first clock signal terminal CLK is a low-level signal.
  • the low-level signal of the first clock signal terminal CLK turns on the first transistor T1 and the second transistor T2.
  • the high-level signal input from the signal input terminal IN is written into the first node N1 through the first transistor T1.
  • the first node N1 is high level, the third transistor T3, the eighth transistor T8, and the tenth transistor T10 are turned off, and the signal of the second power terminal VGL cannot be written to the fifth node N5 through the tenth transistor T10; because the second transistor T2 is turned on, The low level signal of the second power terminal VGL is written into the second node N2 through the second transistor T2.
  • the second node N2 is low level, the fourth transistor T4 and the sixth transistor T6 are turned on, and the signal of the first power terminal VGH
  • the seventh node N7 is written through the fourth transistor T4.
  • the seventh node N7 is high level.
  • the high level signal of the second clock signal terminal CLKB turns off the fifth transistor T5.
  • the signal of the seventh node N7 cannot pass through the fifth transistor T5.
  • the transistor T5 writes the first node N1, and the high-level signal of the second clock signal terminal CLKB is written into the third node N3 through the sixth transistor T6.
  • the third node N3 is high-level, and the eleventh transistor T11 is turned off.
  • the signal of the second clock signal terminal CLKB is a high-level signal.
  • the seventh transistor T7 is turned off.
  • the high-level signal of the third node N3 cannot be written to the fourth node N4 through the seventh transistor T7.
  • the fourth node N4 maintains the previous state.
  • the ninth transistor T9 is turned on, and the signal of the first power supply terminal VGH is written into the fifth node N5 through the ninth transistor T9.
  • the fifth node N5 is at a high level, and the first signal output terminal EM_OUT outputs a high level. flat signal; since the fifth node N5 is at a high level, the twelfth transistor T12 and the fourteenth transistor T14 are disconnected, and the signal of the first power supply terminal VGH cannot be transmitted to the second signal output terminal IEM_OUT through the fourteenth transistor T14. The signal of the first power terminal VGH cannot be written to the sixth node N6 through the twelfth transistor T12. The sixth node N6 maintains the low level of the previous frame.
  • the thirteenth transistor T13 is turned on.
  • the signal of the second power terminal VGL passes through The thirteenth transistor T13 is transmitted to the second signal output terminal IEM_OUT, and the second signal output terminal IEM_OUT outputs a low level signal.
  • the first signal output terminal EM_OUT outputs a high-level signal
  • the second signal output terminal IEM_OUT outputs a low-level signal.
  • the fourth stage P4 The signal of the first clock signal terminal CLK is a high-level signal, and the signals of the signal input terminal IN and the second clock signal terminal CLKB are low-level signals.
  • the high-level signal of the first clock signal terminal CLK turns off the first transistor T1 and the second transistor T2, and the low-level signal input from the signal input terminal IN cannot be written to the first node N1 through the first transistor T1; due to the second The transistor T2 is turned off, and the low level signal of the second power terminal VGL cannot be written to the second node N2 through the second transistor T2.
  • the second node N2 maintains the low level of the previous frame, and the fourth transistor T4 and the sixth transistor T6 is turned on.
  • the fifth transistor T5 Since the signal of the second clock signal terminal CLKB is a low-level signal, the fifth transistor T5 is turned on, and the signal of the first power supply terminal VGH is written into the first node N1 through the fourth transistor T4 and the fifth transistor T5.
  • One node N1 is at a high level, the third transistor T3, the eighth transistor T8, and the tenth transistor T10 are disconnected, and the signal of the second power supply terminal VGL cannot be written to the fifth node N5 through the tenth transistor T10.
  • the second clock signal terminal The low-level signal of CLKB is written into the third node N3 through the sixth transistor T6.
  • the third node N3 is low-level
  • the eleventh transistor T11 is turned on
  • the low-level signal of the second clock signal terminal CLKB causes the seventh transistor to T7 is turned on
  • the low level signal of the third node N3 is written into the fourth node N4 through the seventh transistor T7
  • the fourth node N4 is low level
  • the ninth transistor T9 is turned on
  • the signal of the first power supply terminal VGH is written through the seventh transistor T7.
  • the ninth transistor T9 is written to the fifth node N5, the fifth node N5 is high level, and the first signal output terminal EM_OUT outputs a high level signal; because the fifth node N5 is high level, the twelfth transistor T12 and the fourteenth transistor T12 The transistor T14 is turned off, the signal of the first power terminal VGH cannot be transmitted to the second signal output terminal IEM_OUT through the fourteenth transistor T14, and the signal of the first power terminal VGH cannot be written to the sixth node N6 through the twelfth transistor T12. Since the eleventh transistor T11 is turned on, the low-level signal of the second power terminal VGL is written into the sixth node N6 through the eleventh transistor T11.
  • the sixth node N6 is low-level, and the thirteenth transistor T13 is turned on.
  • the signal of the second power terminal VGL is transmitted to the second signal output terminal IEM_OUT through the thirteenth transistor T13, and the second signal output terminal IEM_OUT outputs a low level signal.
  • the first signal output terminal EM_OUT outputs a high-level signal
  • the second signal output terminal IEM_OUT outputs a low-level signal.
  • the fifth stage P5 The signal of the second clock signal terminal CLKB is a high-level signal, and the signals of the signal input terminal IN and the first clock signal terminal CLK are low-level signals.
  • the low-level signal of the first clock signal terminal CLK turns on the first transistor T1 and the second transistor T2, and the low-level signal input from the signal input terminal IN is written into the first node N1, and the first node N1 is low level.
  • the third transistor T3, the eighth transistor T8, and the tenth transistor T10 are turned on, and the signal of the second power supply terminal VGL is written into the fifth node N5 through the tenth transistor T10.
  • the fifth node N5 is low level, and the first signal output terminal EM_OUT outputs a low-level signal; since the second transistor T2 is turned on, the low-level signal of the second power terminal VGL is written into the second node N2 through the second transistor T2, the second node N2 is low level, and the fourth transistor T4 , the sixth transistor T6 is turned on, the signal of the first power supply terminal VGH is written into the seventh node N7 through the fourth transistor T4, the seventh node N7 is high level, and the high level signal of the second clock signal terminal CLKB causes the fifth The transistor T5 is turned off, and the signal of the seventh node N7 cannot be written to the first node N1 through the fifth transistor T5.
  • the high-level signal of the second clock signal terminal CLKB is written to the third node N3 through the sixth transistor T6.
  • the third node N3 is high level, and the eleventh transistor T11 is turned off. Since the signal of the second clock signal terminal CLKB is a high level signal, the seventh transistor T7 is turned off, and the high level signal of the third node N3 cannot pass through the seventh transistor.
  • T7 is written to the fourth node N4. Since the eighth transistor T8 is turned on, the signal of the first power terminal VGH is written to the fourth node N4 through the eighth transistor T8.
  • the fourth node N4 is high level and the ninth transistor T9 is turned off.
  • the signal of the first power supply terminal VGH cannot be written to the fifth node N5 through the ninth transistor T9; because the fifth node N5 is low level, the twelfth transistor T12 and the fourteenth transistor T14 are turned on, and the first power supply terminal VGH The signal of is transmitted to the second signal output terminal IEM_OUT through the fourteenth transistor T14.
  • the second signal output terminal IEM_OUT outputs a high level signal.
  • the signal of the first power supply terminal VGH is written into the sixth node N6 through the twelfth transistor T12.
  • the sixth node N6 is high level, and the thirteenth transistor T13 is turned off.
  • the first signal output terminal EM_OUT outputs a low-level signal
  • the second signal output terminal IEM_OUT outputs a high-level signal.
  • the sixth stage P6 In this stage, the input signal of the signal input terminal IN remains a low-level signal, the signals of the first clock signal terminal CLK and the second clock signal terminal CLKB change periodically, the first signal output terminal EM_OUT and The signal output by the second signal output terminal IEM_OUT remains unchanged, that is, the first signal output terminal EM_OUT outputs a low-level signal, and the second signal output terminal IEM_OUT outputs a high-level signal.
  • the signal of the first clock signal terminal CLK is a high-level signal
  • the signal of the second clock signal terminal CLKB is a low-level signal.
  • the high-level signal of the first clock signal terminal CLK causes the first transistor T1 and the second transistor T2 to be disconnected.
  • the low-level signal input from the signal input terminal IN cannot be written to the first node N1 through the first transistor T1.
  • the second power supply The low-level signal at terminal VGL cannot be written to the second node N2 through the second transistor T2.
  • the first node N1 maintains the low level of the previous frame, and the third transistor T3, the eighth transistor T8, and the tenth transistor T10 are turned on.
  • the high level signal of the first clock signal terminal CLK is written into the second node N2 through the third transistor T3.
  • the second node N2 is high level.
  • the fourth transistor T4 and the sixth transistor T6 are disconnected.
  • the second clock signal terminal CLKB The low level cannot be written to the third node N3 through the sixth transistor T6.
  • the third node N3 maintains the high level of the previous frame.
  • the high level signal of the first power terminal VGH is written into the fourth node through the eighth transistor T8. N4, the ninth transistor T9 is turned off, and the high-level signal of the first power supply terminal VGH cannot be written to the fifth node N5 through the ninth transistor T9.
  • the eleventh transistor T10 Since the tenth transistor T10 is turned on, the low-level signal of the second power supply terminal VGL The fifth node N5 is written through the tenth transistor T10, the fifth node N5 is low level, and the first signal output terminal EM_OUT outputs a low level signal; since the third node N3 maintains the high level of the previous frame, the eleventh The transistor T11 is turned off, and the low-level signal of the second power terminal VGL cannot be written to the sixth node N6 through the eleventh transistor T11.
  • the fifth node N5 is low-level
  • the twelfth transistor T12 and the fourteenth transistor T14 is turned on
  • the high-level signal of the first power supply terminal VGH is written to the sixth node N6 through the twelfth transistor T12
  • the thirteenth transistor T13 is turned off
  • the low-level signal of the second power supply terminal VGL cannot pass through the thirteenth transistor T13
  • the high-level signal of the first power supply terminal VGH is transmitted to the second signal output terminal IEM_OUT through the fourteenth transistor T14 and is transmitted to the second signal output terminal IEM_OUT.
  • the signal output by the second signal output terminal IEM_OUT is a high-level signal.
  • Second sub-stage P62 the signal of the first clock signal terminal CLK is a low-level signal, and the signal of the second clock signal terminal CLKB is a high-level signal.
  • the low-level signal of the first clock signal terminal CLK turns on the first transistor T1 and the second transistor T2.
  • the low-level signal input from the signal input terminal IN is written into the first node N1 through the first transistor T1.
  • the second power terminal The low level signal of VGL is written into the second node N2 through the second transistor T2.
  • the first node N1 and the second node N2 are both low level.
  • the third transistor T3, the eighth transistor T8, the tenth transistor T10, the fourth The transistor T4 and the sixth transistor T6 are both turned on, the high level of the second clock signal terminal CLKB is written into the third node N3 through the sixth transistor T6, the third node N3 is a high level, and the high level of the first power terminal VGH The high-level signal of the first power supply terminal VGH cannot be written to the fifth node N5 through the ninth transistor T9 because the tenth transistor T10 is conductive.
  • the low-level signal of the second power supply terminal VGL is written into the fifth node N5 through the tenth transistor T10, the fifth node N5 is low-level, and the signal output by the first signal output terminal EM_OUT is a low-level signal; due to the The third node N3 is high level, the eleventh transistor T11 is turned off, and the low level signal of the second power terminal VGL cannot be written to the sixth node N6 through the eleventh transistor T11, because the fifth node N5 is low level.
  • the twelfth transistor T12 and the fourteenth transistor T14 are turned on, and the high-level signal of the first power terminal VGH is written into the sixth node N6 through the twelfth transistor T12.
  • the thirteenth transistor T13 is turned off, and the second power terminal VGL The low level cannot be transmitted to the second signal output terminal IEM_OUT through the thirteenth transistor T13, and the high level signal of the first power supply terminal VGH is transmitted to the second signal output terminal IEM_OUT through the fourteenth transistor T14.
  • the second signal output terminal The signal output by IEM_OUT is a high level signal.
  • the operation timing diagram of the shift register in the equivalent circuit diagram of the shift register shown in FIG. 9a is the same as that of FIG. 8 .
  • the working process of the shift register shown in Figure 9a may include the first stage H1 to the sixth stage H6, the signal input terminal IN of the first stage H1 to the sixth stage H6, the first clock signal terminal CLK, and the second clock signal terminal
  • the signals of CLKB, the first signal output terminal EM_OUT and the second signal output terminal IEM_OUT are the same as the first to sixth stages P1 to P6 in FIG. 8 .
  • the first stage H1 the signals of the signal input terminal IN and the second clock signal terminal CLKB are high-level signals, and the signal of the first clock signal terminal CLK is a low-level signal.
  • the low-level signal of the first clock signal terminal CLK turns on the first transistor T1 and the second transistor T2.
  • the high-level signal input from the signal input terminal IN is written into the first node N1 through the first transistor T1.
  • the first node N1 is high level
  • the third transistor T3, the eighth transistor T8, and the tenth transistor T10 are turned off, the signal of the second power terminal VGL cannot be written to the fifth node N5 through the tenth transistor T10, and the fifth node N5 maintains the previous frame.
  • the first signal output terminal EM_OUT outputs a low level signal; since the second transistor T2 is turned on, the low level signal of the second power supply terminal VGL is written into the second node N2 through the second transistor T2, and the second node N2 is low level, the fourth transistor T4 and the sixth transistor T6 are turned on, the signal of the first power terminal VGH is written into the seventh node N7 through the fourth transistor T4, the seventh node N7 is high level, the second clock signal
  • the high-level signal of the terminal CLKB turns off the fifth transistor T5, and the signal of the seventh node N7 cannot be written to the first node N1 through the fifth transistor T5.
  • the high-level signal of the second clock signal terminal CLKB passes through the sixth transistor T6.
  • the third node N3 is high level. Since the signal of the second clock signal terminal CLKB is a high level signal, the seventh transistor T7 is turned off, and the high level signal of the third node N3 cannot pass through the third node N3. The seventh transistor T7 writes to the fourth node N4. The fourth node N4 maintains the high level of the previous frame. The ninth transistor T9 and the eleventh transistor T11 are disconnected. The signal of the first power supply terminal VGH cannot be written through the ninth transistor T9.
  • the low-level signal of the second power terminal VGL cannot be written to the sixth node N6 through the eleventh transistor T11; because the fifth node N5 is low-level, the first signal output terminal EM_OUT outputs a low-level signal, the twelfth transistor T12 and the fourteenth transistor T14 are turned on, the signal of the first power supply terminal VGH is transmitted to the second signal output terminal IEM_OUT through the fourteenth transistor T14, and the second signal output terminal IEM_OUT outputs a high level signal, The signal of the first power terminal VGH is written to the sixth node N6 through the twelfth transistor T12.
  • the sixth node N6 is high level, the thirteenth transistor T13 is turned off, and the signal of the second power terminal VGL cannot pass through the thirteenth transistor. T13 is output to the second signal output terminal IEM_OUT. At this stage, the first signal output terminal EM_OUT outputs a low-level signal, and the second signal output terminal IEM_OUT outputs a high-level signal.
  • Second stage H2 The signals of the signal input terminal IN and the first clock signal terminal CLK are high-level signals, and the signals of the second clock signal terminal CLKB are low-level signals.
  • the high-level signal of the first clock signal terminal CLK turns off the first transistor T1 and the second transistor T2, and the high-level signal input from the signal input terminal IN cannot be written to the first node N1 through the first transistor T1; due to the second The transistor T2 is turned off, and the low level signal of the second power terminal VGL cannot be written to the second node N2 through the second transistor T2.
  • the second node N2 maintains the low level of the previous frame, and the fourth transistor T4 and the sixth transistor T6 is turned on.
  • the fifth transistor T5 Since the signal of the second clock signal terminal CLKB is a low-level signal, the fifth transistor T5 is turned on, and the signal of the first power supply terminal VGH is written into the first node N1 through the fourth transistor T4 and the fifth transistor T5.
  • One node N1 is at a high level
  • the third transistor T3, the eighth transistor T8, and the tenth transistor T10 are turned off, and the signal of the second power supply terminal VGL cannot be written to the fifth node N5 through the tenth transistor T10, because the sixth transistor T6 is turned on, the low-level signal of the second clock signal terminal CLKB is written into the third node N3 through the sixth transistor T6, the third node N3 is low-level, and the low-level signal of the second clock signal terminal CLKB causes the seventh transistor to T7 is turned on, the low level signal of the third node N3 is written into the fourth node N4 through the seventh transistor T7, the fourth node N4 is low level, the ninth transistor T9 and the eleventh transistor T
  • the fifth node N5 is high level, and the first signal output terminal EM_OUT outputs a high level signal; since the fifth node N5 is high level, the twelfth node N5 is at a high level.
  • the transistor T12 and the fourteenth transistor T14 are disconnected, the signal of the first power supply terminal VGH cannot be transmitted to the second signal output terminal IEM_OUT via the fourteenth transistor T14, and the signal of the first power supply terminal VGH cannot be written via the twelfth transistor T12.
  • the sixth node N6 is low-level, and the thirteenth transistor T13 is turned on, and the signal of the second power terminal VGL is transmitted to the second signal output terminal IEM_OUT through the thirteenth transistor T13, and the second signal output terminal IEM_OUT outputs a low level signal.
  • the first signal output terminal EM_OUT outputs a high-level signal
  • the second signal output terminal IEM_OUT outputs a low-level signal.
  • the third stage H3 the signals of the signal input terminal IN and the second clock signal terminal CLKB are high-level signals, and the signal of the first clock signal terminal CLK is a low-level signal.
  • the low-level signal of the first clock signal terminal CLK turns on the first transistor T1 and the second transistor T2.
  • the high-level signal input from the signal input terminal IN is written into the first node N1 through the first transistor T1.
  • the first node N1 is high level, the third transistor T3, the eighth transistor T8, and the tenth transistor T10 are turned off, and the signal of the second power terminal VGL cannot be written to the fifth node N5 through the tenth transistor T10; because the second transistor T2 is turned on, The low level signal of the second power terminal VGL is written into the second node N2 through the second transistor T2.
  • the second node N2 is low level, the fourth transistor T4 and the sixth transistor T6 are turned on, and the signal of the first power terminal VGH
  • the seventh node N7 is written through the fourth transistor T4.
  • the seventh node N7 is high level.
  • the high level signal of the second clock signal terminal CLKB turns off the fifth transistor T5.
  • the signal of the seventh node N7 cannot pass through the fifth transistor T5.
  • the transistor T5 writes the first node N1, and the high-level signal of the second clock signal terminal CLKB is written into the third node N3 through the sixth transistor T6.
  • the third node N3 is high-level, because the signal of the second clock signal terminal CLKB is a high level signal, the seventh transistor T7 is turned off, the high level signal of the third node N3 cannot be written to the fourth node N4 through the seventh transistor T7, the fourth node N4 maintains the low level of the previous frame, and the ninth
  • the transistor T9 and the eleventh transistor T11 are turned on, the signal of the first power supply terminal VGH is written into the fifth node N5 through the ninth transistor T9, the fifth node N5 is high level, and the first signal output terminal EM_OUT outputs a high level signal.
  • the twelfth transistor T12 and the fourteenth transistor T14 are disconnected, and the signal of the first power supply terminal VGH cannot be transmitted to the second signal output terminal IEM_OUT through the fourteenth transistor T14.
  • the first The signal of the power supply terminal VGH cannot be written to the sixth node N6 through the twelfth transistor T12. Since the eleventh transistor T11 is turned on, the low-level signal of the second power supply terminal VGL is written to the sixth node N6 through the eleventh transistor T11.
  • the sixth node N6 is low level
  • the thirteenth transistor T13 is turned on
  • the signal of the second power supply terminal VGL is transmitted to the second signal output terminal IEM_OUT through the thirteenth transistor T13
  • the second signal output terminal IEM_OUT outputs a low level Signal.
  • the first signal output terminal EM_OUT outputs a high-level signal
  • the second signal output terminal IEM_OUT outputs a low-level signal.
  • the fourth stage H4 The signal of the first clock signal terminal CLK is a high-level signal, and the signals of the signal input terminal IN and the second clock signal terminal CLKB are low-level signals.
  • the high-level signal of the first clock signal terminal CLK turns off the first transistor T1 and the second transistor T2.
  • the high-level signal input from the signal input terminal IN cannot be written to the first node N1 through the first transistor T1.
  • the third transistor T3, the eighth transistor T8, and the tenth transistor T10 are disconnected, and the signal of the second power terminal VGL cannot be written to the fifth node N5 through the tenth transistor T10; because the second transistor T2 is disconnected, the low voltage of the second power terminal VGL
  • the flat signal cannot be written to the second node N2 through the second transistor T2.
  • the second node N2 maintains the low level of the previous frame.
  • the fourth transistor T4 and the sixth transistor T6 are turned on because the signal of the second clock signal terminal CLKB is Low level signal, the fifth transistor T5 and the seventh transistor T7 are turned on, the signal of the first power terminal VGH is written into the first node N1 through the fourth transistor T4 and the fifth transistor T5, and the first node N1 maintains a high level, Since the sixth transistor T6 is turned on, the low-level signal of the second clock signal terminal CLKB is written into the third node N3 through the sixth transistor T6.
  • the third node N3 is low-level. Since the seventh transistor T7 is turned on, the third node N3 is turned on.
  • the low level signal of node N3 is written to the fourth node N4 through the seventh transistor T7.
  • the fourth node N4 is low level, the eleventh transistor T11 and the ninth transistor T9 are turned on, and the signal of the first power terminal VGH passes through the seventh transistor T7.
  • the ninth transistor T9 is written to the fifth node N5, the fifth node N5 is high level, and the first signal output terminal EM_OUT outputs a high level signal; because the fifth node N5 is high level, the twelfth transistor T12 and the fourteenth transistor T12 The transistor T14 is turned off, the signal of the first power terminal VGH cannot be transmitted to the second signal output terminal IEM_OUT through the fourteenth transistor T14, and the signal of the first power terminal VGH cannot be written to the sixth node N6 through the twelfth transistor T12. Since the eleventh transistor T11 is turned on, the low-level signal of the second power terminal VGL is written into the sixth node N6 through the eleventh transistor T11.
  • the sixth node N6 is low-level, and the thirteenth transistor T13 is turned on.
  • the signal of the second power terminal VGL is transmitted to the second signal output terminal IEM_OUT through the thirteenth transistor T13, and the second signal output terminal IEM_OUT outputs a low level signal.
  • the first signal output terminal EM_OUT outputs a high-level signal
  • the second signal output terminal IEM_OUT outputs a low-level signal.
  • the fifth stage H5 The signal of the second clock signal terminal CLKB is a high-level signal, and the signals of the signal input terminal IN and the first clock signal terminal CLK are low-level signals.
  • the low-level signal of the first clock signal terminal CLK turns on the first transistor T1 and the second transistor T2, and the low-level signal input from the signal input terminal IN is written into the first node N1, and the first node N1 is low level.
  • the third transistor T3, the eighth transistor T8, and the tenth transistor T10 are turned on, and the signal of the second power supply terminal VGL is written into the fifth node N5 through the tenth transistor T10.
  • the fifth node N5 is low level, and the first signal output terminal EM_OUT outputs a low-level signal; since the second transistor T2 is turned on, the low-level signal of the second power terminal VGL is written into the second node N2 through the second transistor T2, the second node N2 is low level, and the fourth transistor T4 , the sixth transistor T6 is turned on, the signal of the first power supply terminal VGH is written into the seventh node N7 through the fourth transistor T4, the seventh node N7 is high level, and the high level signal of the second clock signal terminal CLKB causes the fifth The transistor T5 is turned off, and the signal of the seventh node N7 cannot be written to the first node N1 through the fifth transistor T5.
  • the high-level signal of the second clock signal terminal CLKB is written to the third node N3 through the sixth transistor T6.
  • the third node N3 is high level. Since the signal of the second clock signal terminal CLKB is a high level signal, the seventh transistor T7 is turned off, and the high level signal of the third node N3 cannot be written to the fourth node N4 through the seventh transistor T7. Since the eighth transistor T8 is turned on, the signal of the first power terminal VGH is written into the fourth node N4 through the eighth transistor T8.
  • the fourth node N4 is at a high level, the ninth transistor T9 and the eleventh transistor T11 are turned off.
  • the signal of the first power terminal VGH cannot be written to the fifth node N5 through the ninth transistor T9; because the fifth node N5 is low level, the twelfth transistor T12 and the fourteenth transistor T14 are turned on, and the signal of the first power terminal VGH It is transmitted to the second signal output terminal IEM_OUT through the fourteenth transistor T14.
  • the second signal output terminal IEM_OUT outputs a high level signal.
  • the signal of the first power supply terminal VGH is written into the sixth node N6 through the twelfth transistor T12.
  • the sixth node N6 is high level, the thirteenth transistor T13 is turned off, and the signal of the second power supply terminal VGL cannot be transmitted to the second signal output terminal IEM_OUT through the thirteenth transistor T13.
  • the first signal output terminal EM_OUT outputs a low-level signal
  • the second signal output terminal IEM_OUT outputs a high-level signal.
  • the sixth stage H6 In this stage, the input signal of the signal input terminal IN remains unchanged as a low-level signal, the signals of the first clock signal terminal CLK and the second clock signal terminal CLKB change periodically, and the first signal output terminal EM_OUT and The signal output by the second signal output terminal IEM_OUT remains unchanged, that is, the first signal output terminal EM_OUT outputs a low-level signal, and the second signal output terminal IEM_OUT outputs a high-level signal.
  • the first sub-stage H61 the signal of the first clock signal terminal CLK is a high-level signal, and the signal of the second clock signal terminal CLKB is a low-level signal.
  • the high-level signal of the first clock signal terminal CLK causes the first transistor T1 and the second transistor T2 to be disconnected.
  • the low-level signal input from the signal input terminal IN cannot be written to the first node N1 through the first transistor T1.
  • the second power supply The low-level signal at terminal VGL cannot be written to the second node N2 through the second transistor T2.
  • the first node N1 maintains the low level of the previous frame, and the third transistor T3, the eighth transistor T8, and the tenth transistor T10 are turned on.
  • the high level signal of the first clock signal terminal CLK is written into the second node N2 through the third transistor T3.
  • the second node N2 is high level.
  • the fourth transistor T4 and the sixth transistor T6 are disconnected.
  • the second clock signal terminal CLKB The low level cannot be written to the third node N3 through the sixth transistor T6.
  • the third node N3 maintains the high level of the previous frame.
  • the high level signal of the first power terminal VGH is written into the fourth node through the eighth transistor T8. N4, the fourth node N4 is high level, the ninth transistor T9 and the eleventh transistor T11 are turned off, and the high level signal of the first power supply terminal VGH cannot be written to the fifth node N5 through the ninth transistor T9.
  • the transistor T10 is turned on, and the low-level signal of the second power supply terminal VGL is written into the fifth node N5 through the tenth transistor T10.
  • the fifth node N5 is low-level, and the first signal output terminal EM_OUT outputs a low-level signal; because the first signal output terminal EM_OUT outputs a low-level signal;
  • the eleventh transistor T11 is turned off, and the low-level signal of the second power terminal VGL cannot be written to the sixth node N6 through the eleventh transistor T11. Since the fifth node N5 is low-level, the twelfth transistor T12 and the fourteenth transistor T12 cannot be written to the sixth node N6.
  • the transistor T14 is turned on, and the high-level signal of the first power supply terminal VGH is transmitted to the second signal output terminal IEM_OUT through the fourteenth transistor T14.
  • the signal output by the second signal output terminal IEM_OUT is a high-level signal, and the first power supply terminal VGH
  • the high-level signal is written into the sixth node N6 through the twelfth transistor T12.
  • the sixth node N6 is high-level.
  • the thirteenth transistor T13 is turned off.
  • the low-level signal of the second power supply terminal VGL cannot pass through the thirteenth transistor T12.
  • the transistor T13 transmits to the second signal output terminal IEM_OUT.
  • the second sub-stage H62 the signal of the first clock signal terminal CLK is a low-level signal, and the signal of the second clock signal terminal CLKB is a high-level signal.
  • the low-level signal of the first clock signal terminal CLK turns on the first transistor T1 and the second transistor T2.
  • the low-level signal input from the signal input terminal IN is written into the first node N1 through the first transistor T1.
  • the second power terminal The low level signal of VGL is written into the second node N2 through the second transistor T2.
  • the first node N1 and the second node N2 are both low level.
  • the third transistor T3, the eighth transistor T8, the tenth transistor T10, the fourth The transistor T4 and the sixth transistor T6 are turned on, the high level of the second clock signal terminal CLKB is written into the third node N3 through the sixth transistor T6, the third node N3 is a high level, and the high level of the first power terminal VGH
  • the signal is written to the fourth node N4 through the eighth transistor T8, the ninth transistor T9 and the eleventh transistor T11 are turned off, and the high level signal of the first power supply terminal VGH cannot be written to the fifth node N5 through the ninth transistor T9, because The tenth transistor T10 is turned on, and the low-level signal of the second power supply terminal VGL is written into the fifth node N5 through the tenth transistor T10.
  • the fifth node N5 is low-level, and the signal output by the first signal output terminal EM_OUT is low-level. flat signal; because the eleventh transistor T11 is turned off, the low-level signal of the second power terminal VGL cannot be written to the sixth node N6 through the eleventh transistor T11. Since the fifth node N5 is low-level, the twelfth transistor T12 and the fourteenth transistor T14 are turned on, and the high-level signal of the first power supply terminal VGH is transmitted to the second signal output terminal IEM_OUT through the fourteenth transistor T14. The signal output by the second signal output terminal IEM_OUT is a high-level signal. The high level signal of the first power supply terminal VGH is written into the sixth node N6 through the twelfth transistor T12. The sixth node N6 is high level. The thirteenth transistor T13 is turned off. The low level signal of the second power supply terminal VGL It cannot be transmitted to the second signal output terminal IEM_OUT via the thirteenth transistor T13.
  • the operation timing diagram of the shift register in the equivalent circuit diagram of the shift register shown in FIG. 9b is the same as that of FIG. 8 .
  • a fifth capacitor is added based on the circuit diagram shown in Figure 7.
  • the control electrode of the eleventh transistor T11 is connected to the third node N3 or the fourth node N4, and the first electrode of the fifth capacitor C5
  • the plate C51 is connected to the sixth node N6, and the second plate C52 of the fifth capacitor C5 is connected to the first clock signal terminal CLK or the second clock signal terminal CLKB.
  • the operating timing diagram of the shift register in the equivalent circuit diagram of the shift register shown in Figure 9c is the same as Figure 8.
  • Figure 9c adds a fourth capacitor C4 on the basis of Figure 9b.
  • the working process of the shift register shown in Figure 9c may include the first stage M1 to the sixth stage M6, the signal input terminal IN of the first stage M1 to the sixth stage M6, the first clock signal terminal CLK, and the second clock signal terminal
  • the signals of CLKB and the signal output terminal OUT are the same as the first stage P1 to the sixth stage P6 in Figure 8.
  • the following is a detailed description of the multiple transistors in the shift register shown in FIG. 9c when the eleventh transistor T11 is connected to the fourth node N4 and the second plate C52 of the fifth capacitor C5 is connected to the first clock signal terminal CLK.
  • the working process of multiple capacitors in the first stage M1 to the sixth stage M6 :
  • the first stage M1 the signals of the signal input terminal IN and the second clock signal terminal CLKB are high-level signals, and the signal of the first clock signal terminal CLK is a low-level signal.
  • the low-level signal of the first clock signal terminal CLK turns on the first transistor T1 and the second transistor T2.
  • the high-level signal input from the signal input terminal IN is written into the first node N1 through the first transistor T1.
  • the first node N1 is high level
  • the third transistor T3, the fifth transistor T5, the eighth transistor T8, and the tenth transistor T10 are turned off, and the signal of the second power supply terminal VGL cannot be written to the fifth node N5 through the tenth transistor T10.
  • the fifth node N5 maintains the low level of the previous frame, and the first signal output terminal EM_OUT outputs a low level signal; since the second transistor T2 is turned on, the low level signal of the second power supply terminal VGL is written to the second node through the second transistor T2 N2, the second node N2 is low level, the fourth transistor T4 and the sixth transistor T6 are turned on, the signal of the first power terminal VGH is written into the seventh node N7 through the fourth transistor T4, and the seventh node N7 is high level. , the high level of the first node N1 turns off the fifth transistor T5, and the signal of the second clock signal terminal CLKB cannot be written to the seventh node N7 through the fifth transistor T5.
  • the high level signal of the second clock signal terminal CLKB passes through The sixth transistor T6 writes to the third node N3, and the third node N3 is a high level. Since the signal of the second clock signal terminal CLKB is a high level signal, the seventh transistor T7 is turned off, and the third node N3 is a high level. The signal cannot be written to the fourth node N4 through the seventh transistor T7. The fourth node N4 maintains the high level of the previous frame. The ninth transistor T9 and the eleventh transistor T11 are disconnected. The signal of the first power supply terminal VGH cannot pass through the seventh transistor T7.
  • the ninth transistor T9 writes to the fifth node N5, and the low-level signal of the second power terminal VGL cannot be written to the sixth node N6 through the eleventh transistor T11; because the fifth node N5 is low-level, the twelfth transistor T12, The fourteenth transistor T14 is turned on, and the signal of the first power terminal VGH is transmitted to the second signal output terminal IEM_OUT through the fourteenth transistor T14.
  • the second signal output terminal IEM_OUT outputs a high level signal, and the signal of the first power terminal VGH is transmitted through
  • the twelfth transistor T12 writes to the sixth node N6, the sixth node N6 is high level, the thirteenth transistor T13 is turned off, and the signal of the second power supply terminal VGL cannot be output to the second signal output terminal through the thirteenth transistor T13.
  • IEM_OUT At this stage, the first signal output terminal EM_OUT outputs a low-level signal, and the second signal output terminal IEM_OUT outputs a high-level signal.
  • Second stage M2 The signals of the signal input terminal IN and the first clock signal terminal CLK are high-level signals, and the signals of the second clock signal terminal CLKB are low-level signals.
  • the high-level signal of the first clock signal terminal CLK turns off the first transistor T1 and the second transistor T2.
  • the high-level signal input from the signal input terminal IN cannot be written to the first node N1 through the first transistor T1.
  • the first node N1 maintains the high level of the previous frame, the third transistor T3, the fifth transistor T5, the eighth transistor T8, and the tenth transistor T10 are disconnected, and the signal of the second power supply terminal VGL cannot be written to the fifth node through the tenth transistor T10.
  • the second transistor T2 Since the second transistor T2 is turned off, the low level signal of the second power terminal VGL cannot be written to the second node N2 through the second transistor T2.
  • the second node N2 maintains the low level of the previous frame, and the fourth transistor T4 , the sixth transistor T6 is turned on, the signal of the first power supply terminal VGH is written into the seventh node N7 through the fourth transistor T4, the seventh node N7 is high level, and the high level of the first node N1 turns off the fifth transistor T5.
  • the signal of the second clock signal terminal CLKB cannot be written to the seventh node N7 through the fifth transistor T5, and the low-level signal of the second clock signal terminal CLKB is written to the third node N3 through the sixth transistor T6.
  • the third node N3 is low level
  • the low level signal of the second clock signal terminal CLKB turns on the seventh transistor T7
  • the low level signal of the third node N3 is written into the fourth node N4 through the seventh transistor T7
  • the fourth node N4 is Low level
  • the ninth transistor T9 and the eleventh transistor T11 are turned on
  • the signal of the first power supply terminal VGH is written into the fifth node N5 through the ninth transistor T9
  • the fifth node N5 is high level
  • the first signal output terminal EM_OUT outputs a high level signal
  • since the fifth node N5 is at a high level
  • the twelfth transistor T12 and the fourteenth transistor T14 are disconnected, and the signal of the first power supply terminal VGH cannot be transmitted to the second signal through the fourteenth transistor T14.
  • the signal of the first power terminal VGH cannot be written to the sixth node N6 through the twelfth transistor T12; because the eleventh transistor T11 is turned on, the low-level signal of the second power terminal VGL passes through the eleventh transistor T11 Write to the sixth node N6, the sixth node N6 is low level, the thirteenth transistor T13 is turned on, the signal of the second power supply terminal VGL is transmitted to the second signal output terminal IEM_OUT through the thirteenth transistor T13, and the second signal output The terminal IEM_OUT outputs a low level signal.
  • the first signal output terminal EM_OUT outputs a high-level signal
  • the second signal output terminal IEM_OUT outputs a low-level signal.
  • the third stage M3 the signals of the signal input terminal IN and the second clock signal terminal CLKB are high-level signals, and the signal of the first clock signal terminal CLK is a low-level signal.
  • the low-level signal of the first clock signal terminal CLK turns on the first transistor T1 and the second transistor T2.
  • the high-level signal input from the signal input terminal IN is written into the first node N1 through the first transistor T1.
  • the first node N1 is high level, the third transistor T3, the fifth transistor T5, the eighth transistor T8, and the tenth transistor T10 are turned off, and the signal of the second power supply terminal VGL cannot be written to the fifth node N5 through the tenth transistor T10; due to the second The transistor T2 is turned on, the low-level signal of the second power terminal VGL is written into the second node N2 through the second transistor T2, the second node N2 is low-level, the fourth transistor T4 and the sixth transistor T6 are turned on, and the first The signal of the power terminal VGH is written into the seventh node N7 through the fourth transistor T4.
  • the seventh node N7 is high level.
  • the high level of the first node N1 turns off the fifth transistor T5.
  • the signal of the second clock signal terminal CLKB The seventh node N7 cannot be written through the fifth transistor T5, and the high level signal of the second clock signal terminal CLKB is written into the third node N3 through the sixth transistor T6.
  • the third node N3 is high level, because the second clock signal
  • the signal at terminal CLKB is a high-level signal
  • the seventh transistor T7 is turned off, the high-level signal of the third node N3 cannot be written to the fourth node N4 through the seventh transistor T7, and the fourth node N4 maintains the low level of the previous frame.
  • the ninth transistor T9 and the eleventh transistor T11 are turned on, the signal of the first power supply terminal VGH is written into the fifth node N5 through the ninth transistor T9, the fifth node N5 is high level, and the first signal output terminal EM_OUT outputs High level signal; since the fifth node N5 is high level, the twelfth transistor T12 and the fourteenth transistor T14 are disconnected, and the signal of the first power supply terminal VGH cannot be transmitted to the second signal output terminal through the fourteenth transistor T14. IEM_OUT, the signal of the first power supply terminal VGH cannot be written to the sixth node N6 through the twelfth transistor T12.
  • the eleventh transistor T11 Since the eleventh transistor T11 is turned on, the low level signal of the second power supply terminal VGL is written through the eleventh transistor T11.
  • the sixth node N6 is low level, the thirteenth transistor T13 is turned on, and the signal of the second power supply terminal VGL is transmitted to the second signal output terminal IEM_OUT through the thirteenth transistor T13.
  • the second signal output terminal IEM_OUT Output low level signal.
  • the first signal output terminal EM_OUT outputs a high-level signal
  • the second signal output terminal IEM_OUT outputs a low-level signal.
  • the fourth stage M4 The signal of the first clock signal terminal CLK is a high-level signal, and the signals of the signal input terminal IN and the second clock signal terminal CLKB are low-level signals.
  • the high-level signal of the first clock signal terminal CLK turns off the first transistor T1 and the second transistor T2.
  • the high-level signal input from the signal input terminal IN cannot be written to the first node N1 through the first transistor T1.
  • the first node N1 maintains the high level of the previous frame, the third transistor T3, the fifth transistor T5, the eighth transistor T8, and the tenth transistor T10 are disconnected, and the signal of the second power supply terminal VGL cannot be written to the fifth node through the tenth transistor T10.
  • the second transistor T2 Since the second transistor T2 is turned off, the low level signal of the second power terminal VGL cannot be written to the second node N2 through the second transistor T2.
  • the second node N2 maintains the low level of the previous frame, and the fourth transistor T4 , the sixth transistor T6 is turned on, the signal of the first power supply terminal VGH is written into the seventh node N7 through the fourth transistor T4, the seventh node N7 is high level, and the high level of the first node N1 turns off the fifth transistor T5. is on, the signal of the second clock signal terminal CLKB cannot be written to the seventh node N7 through the fifth transistor T5.
  • the sixth transistor T6 Since the sixth transistor T6 is turned on, the low-level signal of the second clock signal terminal CLKB is written to the seventh node N7 through the sixth transistor T6.
  • Three nodes N3, the third node N3 is low level, because the signal of the second clock signal terminal CLKB is a low level signal, the seventh transistor T7 is turned on, and the low level signal of the third node N3 is written through the seventh transistor T7 Enter the fourth node N4, the fourth node N4 is low level, the eleventh transistor T11 and the ninth transistor T9 are turned on, the signal of the first power supply terminal VGH is written into the fifth node N5 through the ninth transistor T9, and the fifth node N5 is high level, and the first signal output terminal EM_OUT outputs a high level signal; because the fifth node N5 is high level, the twelfth transistor T12 and the fourteenth transistor T14 are disconnected, and the signal of the first power supply terminal VGH cannot After being transmitted to the second signal output terminal IEM_OUT via the fourteen
  • the eleventh transistor T11 Since the eleventh transistor T11 is turned on, the low-level signal of the second power terminal VGL is written into the sixth node N6 through the eleventh transistor T11.
  • the sixth node N6 is low-level, and the thirteenth transistor T13 is turned on.
  • the signal of the second power terminal VGL is transmitted to the second signal output terminal IEM_OUT through the thirteenth transistor T13, and the second signal output terminal IEM_OUT outputs a low level signal.
  • the first signal output terminal EM_OUT outputs a high-level signal
  • the second signal output terminal IEM_OUT outputs a low-level signal.
  • the fifth stage M5 the signal of the second clock signal terminal CLKB is a high-level signal, and the signals of the signal input terminal IN and the first clock signal terminal CLK are low-level signals.
  • the low-level signal of the first clock signal terminal CLK turns on the first transistor T1 and the second transistor T2, and the low-level signal input from the signal input terminal IN is written into the first node N1, and the first node N1 is low level.
  • the third transistor T3, the fifth transistor T5, the eighth transistor T8, and the tenth transistor T10 are turned on, and the signal of the second power terminal VGL is written into the fifth node N5 through the tenth transistor T10, and the fifth node N5 is low level.
  • the first signal output terminal EM_OUT outputs a low-level signal; since the second transistor T2 is turned on, the low-level signal of the second power terminal VGL is written into the second node N2 through the second transistor T2, and the second node N2 is low level. , the fourth transistor T4 and the sixth transistor T6 are turned on, the signal of the first power supply terminal VGH is written into the seventh node N7 through the fourth transistor T4, the seventh node N7 is high level, and the high level of the second clock signal terminal CLKB The flat signal is written into the third node N3 through the sixth transistor T6, and the third node N3 is a high level.
  • the seventh transistor T7 Since the signal of the second clock signal terminal CLKB is a high level signal, the seventh transistor T7 is turned off, and the third node N3 The high-level signal cannot be written to the fourth node N4 through the seventh transistor T7. Since the eighth transistor T8 is turned on, the signal of the first power supply terminal VGH is written to the fourth node N4 through the eighth transistor T8, and the fourth node N4 is high.
  • the ninth transistor T9 and the eleventh transistor T11 are disconnected, and the signal of the first power supply terminal VGH cannot be written to the fifth node N5 through the ninth transistor T9; because the fifth node N5 is low level, the twelfth transistor T12 and the fourteenth transistor T14 are turned on, and the signal of the first power terminal VGH is transmitted to the second signal output terminal IEM_OUT through the fourteenth transistor T14.
  • the second signal output terminal IEM_OUT outputs a high level signal, and the signal of the first power terminal VGH is The signal is written into the sixth node N6 via the twelfth transistor T12, the sixth node N6 is high level, and the thirteenth transistor T13 is turned off. At this stage, the first signal output terminal EM_OUT outputs a low-level signal, and the second signal output terminal IEM_OUT outputs a high-level signal.
  • the sixth stage M6 In this stage, the input signal of the signal input terminal IN remains a low-level signal, the signals of the first clock signal terminal CLK and the second clock signal terminal CLKB change periodically, and the first signal output terminal EM_OUT and The signal output by the second signal output terminal IEM_OUT remains unchanged, that is, the first signal output terminal EM_OUT outputs a low-level signal, and the second signal output terminal IEM_OUT outputs a high-level signal.
  • the first sub-stage M61 the signal of the first clock signal terminal CLK is a high-level signal, and the signal of the second clock signal terminal CLKB is a low-level signal.
  • the high-level signal of the first clock signal terminal CLK causes the first transistor T1 and the second transistor T2 to be disconnected.
  • the low-level signal input from the signal input terminal IN cannot be written to the first node N1 through the first transistor T1.
  • the second power supply The low level signal of terminal VGL cannot be written to the second node N2 through the second transistor T2.
  • the first node N1 maintains the low level of the previous frame.
  • the third transistor T3, the fifth transistor T5, the eighth transistor T8, and the tenth transistor The transistor T10 is turned on, and the high-level signal of the first clock signal terminal CLK is written into the second node N2 through the third transistor T3.
  • the second node N2 is at a high level.
  • the fourth transistor T4 and the sixth transistor T6 are turned off.
  • the low level of the second clock signal terminal CLKB cannot be written to the third node N3 through the sixth transistor T6.
  • the third node N3 maintains the high level of the previous frame.
  • the high level signal of the first power supply terminal VGH passes through the eighth transistor T8.
  • the fourth node N4 is high level, the ninth transistor T9 and the eleventh transistor T11 are disconnected, and the high level signal of the first power supply terminal VGH cannot be written to the fifth node through the ninth transistor T9 N5, since the tenth transistor T10 is turned on, the low-level signal of the second power terminal VGL is written into the fifth node N5 through the tenth transistor T10.
  • the fifth node N5 is low-level, and the first signal output terminal EM_OUT outputs a low-level signal. flat signal; because the eleventh transistor T11 is turned off, the low-level signal of the second power terminal VGL cannot be written to the sixth node N6 through the eleventh transistor T11.
  • the twelfth transistor T12 and the fourteenth transistor T14 are turned on, and the high-level signal of the first power supply terminal VGH is transmitted to the second signal output terminal IEM_OUT through the fourteenth transistor T14.
  • the signal output by the second signal output terminal IEM_OUT is a high-level signal.
  • the high level signal of the first power supply terminal VGH is written into the sixth node N6 through the twelfth transistor T12.
  • the sixth node N6 is high level.
  • the thirteenth transistor T13 is turned off.
  • the low level signal of the second power supply terminal VGL Unable to be transmitted to the second signal output IEM_OUT.
  • Second sub-stage M62 the signal of the first clock signal terminal CLK is a low-level signal, and the signal of the second clock signal terminal CLKB is a high-level signal.
  • the low-level signal of the first clock signal terminal CLK turns on the first transistor T1 and the second transistor T2.
  • the low-level signal input from the signal input terminal IN is written into the first node N1 through the first transistor T1.
  • the second power terminal The low-level signal of VGL is written into the second node N2 through the second transistor T2.
  • the first node N1 and the second node N2 are both low-level.
  • the third transistor T3, the fifth transistor T5, the eighth transistor T8, and the tenth transistor The transistor T10 and the sixth transistor T6 are turned on, the high level of the second clock signal terminal CLKB is written into the third node N3 through the sixth transistor T6, the third node N3 is a high level, and the high level of the first power terminal VGH The signal is written into the fourth node N4 through the eighth transistor T8. The fourth node N4 is high level.
  • the ninth transistor T9 and the eleventh transistor T11 are disconnected. The high level signal of the first power supply terminal VGH cannot pass through the ninth transistor. T9 is written to the fifth node N5.
  • the tenth transistor T10 Since the tenth transistor T10 is turned on, the low level signal of the second power supply terminal VGL is written to the fifth node N5 through the tenth transistor T10.
  • the fifth node N5 is low level, and the first signal The signal output by the output terminal EM_OUT is a low-level signal; because the eleventh transistor T11 is turned off, the low-level signal of the second power supply terminal VGL cannot be written to the sixth node N6 through the eleventh transistor T11, because the fifth node N5 is low level, the twelfth transistor T12 and the fourteenth transistor T14 are turned on, and the high level signal of the first power supply terminal VGH is transmitted to the second signal output terminal IEM_OUT through the fourteenth transistor T14.
  • the second signal output terminal IEM_OUT The output signal is a high-level signal.
  • the high-level signal of the first power supply terminal VGH is written into the sixth node N6 through the twelfth transistor T12.
  • the sixth node N6 is a high-level signal.
  • the thirteenth transistor T13 is turned off.
  • the low-level signal of the second power supply terminal VGL cannot be transmitted to the second signal output terminal IEM_OUT.
  • the luminescent signal EM and its inverted signal IEM can be provided through the shift register shown in FIGS. 7 and 9a to 9c.
  • the luminescent signal EM and the inverted signal IEM of the luminescent signal have the same period, and the voltage
  • the pulse width of the luminescence signal EM and its inverted signal IEM can be adjusted according to the input signal IN, that is, a GOA circuit shown in Figures 7, 9a to 9c can provide pulse Widely adjustable EM signal and its inverted IEM signal.
  • the degree of integration is high and the pulse width is adjustable. It can be applied to different pulse width requirements and different types of signal requirements. Wide range of applications.
  • the shift register shown in FIG. 7 and FIG. 9a to FIG. 9c can be applied to the pixel circuit shown in FIG. 10a.
  • the signal output by the first signal output terminal EM_OUT is used as the luminescence signal in the pixel circuit shown in FIG. 10a.
  • the signal output by the signal terminal EM and the second signal output terminal IEM_OUT is used as the input of the light-emitting signal terminal IEM in the pixel circuit shown in Figure 10a.
  • Figure 10b shows an operating timing diagram of the pixel circuit in Figure 10a.
  • Embodiments of the present disclosure also provide a display substrate.
  • the display substrate may include a substrate and a circuit structure layer disposed on the substrate.
  • the circuit structure layer includes a light-emitting drive circuit.
  • the light-emitting drive circuit includes a plurality of cascaded shift registers, as shown in Figure 21 shown.
  • the first signal output terminal EM_OUT of the i-th stage shift register is electrically connected to the signal input terminal IN of the i+1-th stage shift register, 1 ⁇ i ⁇ M-1 , M is the total number of stages of the shift register, and M can be a positive integer greater than or equal to 2.
  • the signal input terminal IN of the shift register of the first stage may be connected to the initial signal line STV.
  • At least one shift register in FIG. 21 may be as shown in FIG. 6 and may include: a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, a first output sub-circuit, second output subcircuit;
  • the first control subcircuit is respectively connected to the signal input terminal IN, the first node N1, the second node N2, the first clock signal terminal CLK, the second clock signal terminal CLKB and the first power supply terminal VGH, and is configured to operate on the first clock Under the control of the signal terminal CLK, the second clock signal terminal CLKB, the second node N2 and the first power terminal VGH, the signal of the signal input terminal IN is provided to the first node N1, and the potential of the first node N1 is maintained;
  • the second control subcircuit is respectively connected to the second power terminal VGL, the first clock signal terminal CLK, the first node N1 and the second node N2, and is configured to be under the control of the first clock signal terminal CLK and the first node N1, Provide a signal of the second power terminal VGL or the first clock signal terminal CLK to the second node N2;
  • the third control sub-circuit is respectively connected to the first node N1, the second node N2, the fourth node N4, the second clock signal terminal CLKB and the first power terminal VGH, and is configured to operate between the second clock signal terminal CLKB and the first node Under the control of N1 and the second node N2, provide the signal of the second clock signal terminal CLKB or the first power terminal VGH to the fourth node N4, and maintain the potential of the fourth node N4;
  • the first output sub-circuit is respectively connected to the first power terminal VGH, the second power terminal VGL, the first node N1, the fourth node N4 and the first signal output terminal EM_OUT, and is configured to connect the first node N1 and the fourth node N4 Provide the signal of the first power terminal VGH or the second power terminal VGL to the first signal output terminal EM_OUT under the control of
  • the second output sub-circuit is respectively connected to the first signal output terminal EM_OUT, the third control sub-circuit, the first power terminal VGH, the second power terminal VGL and the second signal output terminal IEM_OUT, and is configured to connect between the third control sub-circuit and the second signal output terminal IEM_OUT.
  • the signal of the first power terminal VGH or the second power terminal VGL is provided to the second signal output terminal IEM_OUT.
  • the first signal output terminal EM_OUT and the second signal output terminal IEM_OUT may be electrically connected to the pixel circuit of the display area in the display substrate.
  • the signal output by the first signal output terminal EM_OUT and the signal output by the second signal output terminal IEM_OUT may be mutually inverted signals.
  • the shift register may be a shift register provided in any of the foregoing embodiments.
  • the implementation principles and implementation effects are similar and will not be described again here.
  • each shift register drives several rows of sub-pixels, as long as a large-area device like this is changed, and after this change creates additional space, a simple translation of the small device is possible , stretching are all within the protection scope of the present disclosure.
  • the circuit schematic diagram of the shift register in the display substrate of the embodiment of the present disclosure may be any one of the circuit schematic diagrams shown in FIG. 7 and FIG. 9a to FIG. 9c, which will not be described again.
  • the display substrate of the present disclosure can be applied to a display device with a light-emitting driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot Light emitting diode display (QDLED), etc.
  • a light-emitting driving circuit such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot Light emitting diode display (QDLED), etc.
  • the embodiments of the present disclosure are not limited here.
  • the display substrate may further include: a light-emitting structure layer disposed on a side of the circuit structure layer away from the substrate.
  • the light-emitting structure layer includes: light-emitting elements arranged in an array in the display area.
  • the light-emitting element may be an organic electroluminescent diode (OLED) or a quantum dot light-emitting diode (QLED).
  • OLED organic electroluminescent diode
  • QLED quantum dot light-emitting diode
  • the OLED may include a stacked first electrode (anode), an organic light-emitting layer and a second electrode (cathode).
  • the layout structure corresponding to the circuit schematic diagram shown in FIG. 9a may be as shown in FIGS. 11 to 15b or as shown in FIGS. 16 to 20b.
  • the display substrate may further include: an initial signal line STV extending along the second direction Y, a first clock signal line CLK, a second clock
  • the signal line CLKB, the second power line VGL and the third power line VGH2 the initial signal line STV, the first clock signal line CLK, the second clock signal line CLKB, the third power line VGH2 and the second power line VGL are along the first direction.
  • X arrangement, the first direction X and the second direction Y intersect;
  • the signal input terminal IN of the first-stage shift register is electrically connected to the initial signal line STV
  • the first power terminal VGH of all shift registers is electrically connected to the third power line VGH2
  • the second power terminal VGL of all shift registers is electrically connected to the third power line VGH2.
  • the two power lines VGL are electrically connected, the clock signal terminal of the i-th stage shift register is electrically connected to one of the first clock signal line CLK and the second clock signal line CLKB, and the first clock signal of the odd-numbered stage shift register
  • the terminal CLK is connected to the first clock signal line CLK
  • the second clock signal terminal CLKB of the odd-numbered stage shift register is connected to the second clock signal line CLKB
  • the first clock signal terminal CLK of the even-numbered stage shift register is connected to the second clock signal line.
  • CLKB is connected
  • the second clock signal terminal CLKB of the even-numbered shift register is connected to the first clock signal line CLK.
  • the circuit structure layer may include: a semiconductor layer, a first insulating layer, a first conductive layer, a second an insulating layer, a second conductive layer, a third insulating layer and a third conductive layer;
  • the semiconductor layer may include: an active layer located in all transistors of the light emitting driving circuit;
  • the first conductive layer may include: control electrodes of all transistors of the light-emitting driving circuit and first plates of the first capacitor C1 to first plates of the third capacitor C3;
  • the second conductive layer may include: a second plate of the first capacitor C1 to a second plate of the third capacitor C3 of the light-emitting driving circuit;
  • the third conductive layer may include: an initial signal line STV, a first clock signal line CLK, a second clock signal line CLKB, a first power line VGH1, and a second power line VGL.
  • the third conductive layer may further include first electrodes and second electrodes of all transistors of the light emitting driving circuit.
  • the shift register may include: first to fourteenth transistors T1 to T14;
  • all transistors and capacitors are located between the third power line VGH2 and the second power line VGL.
  • the second capacitor C2 is located between the third power line VGH2 and the eighth transistor T8
  • the eighth transistor T8 is located between the second capacitor C2 and the ninth transistor T9 and the tenth transistor T10.
  • the ninth transistor T9 and the tenth transistor T10 are located between the eighth transistor T8 and the eleventh transistor T11 and the twelfth transistor T12.
  • the eleventh transistor T11 and the twelfth transistor T12 are located between the ninth transistor T9 and the tenth transistor T10 and the thirteenth transistor T13 and the fourteenth transistor T14, the thirteenth transistor T13 and the fourteenth transistor T14 Located between the eleventh transistor T11 and the twelfth transistor T12 and the second power line VGL; in the second direction Y, the third capacitor C3, the ninth transistor T9, the tenth transistor T10, and the first capacitor C1 along the second
  • the twelfth transistor T12 and the eleventh transistor T11 are arranged in sequence along the second direction Y
  • the fourteenth transistor T14 and the thirteenth transistor T13 are arranged in sequence along the second direction Y.
  • the first conductive layer may further include a first power line VGH1, and the first power line VGH1 may be connected to the first power terminal VGH; the first power line VGH1 may be in the shape of a zigzag line, and extends along the first direction X;
  • the first power line VGH1 On a plane parallel to the display substrate, in the first direction X, the first power line VGH1 may be located on a side of the third capacitor C3 away from the control electrode of the eighth transistor T8; in the second direction Y, the first power line VGH1 The power line VGH1 may be located on a side of the control electrode of the fourteenth transistor T14 away from the control electrode of the thirteenth transistor T13.
  • the orthographic projection of the first power line VGH1 on the substrate may be at the same position as the first pole of the ninth transistor T9 , the first pole of the twelfth transistor T12 , and the first pole of the fourteenth transistor T14 respectively. Orthographic projections on the substrate at least partially overlap;
  • the first electrode of the eighth transistor T8 and the first electrode of the ninth transistor T9 in the third conductive layer may be an integrally formed structure.
  • the first conductive layer may further include a first signal output line EM_OUT and a second signal output line IEM_OUT; the first signal output line EM_OUT may be in a strip shape and extend along the first signal output line EM_OUT. Extending in the direction X, the second signal output line IEM_OUT has an "L" shape;
  • the first signal output line EM_OUT is located between the control electrode of the thirteenth transistor T13 and the first power line VGH1, and the first signal output line EM_OUT and the fourteenth
  • the control electrode of the transistor T14 may have an integral structure, and the second signal output line IEM_OUT may be located on a side of the first power line VGH1 away from the first signal output line EM_OUT; in the first direction
  • the control electrode of the fourteenth transistor T14 is on the side away from the control electrode of the twelfth transistor T12, and the second signal output line IEM_OUT is located on the side of the first plate C31 of the third capacitor C3 away from the control electrode of the eighth transistor T8.
  • the first conductive layer may further include a second connection line CL2, a first plate C31 of the third capacitor C3, and a control electrode of the ninth transistor T9. It may be an integrally formed structure, and the gate shape of the eleventh transistor T11 may be in an "L" shape.
  • the third conductive layer may further include a fourth connection line CL4.
  • the shape of the fourth connection line may be a polygonal line and may extend along the second direction Y.
  • the fourth connection line The orthographic projection of CL4 on the substrate at least partially overlaps with the orthographic projection of the control electrode of the eleventh transistor T11 and the first plate C31 of the third capacitor C3 on the substrate respectively.
  • the second pole 392 of the ninth transistor T9 may include a third structure 392-1 and a fourth structure 392-2 connected to each other, and the shape of the third structure 392-1 may be It is strip-shaped and extends along the first direction
  • the structure 392-2 may be in a strip shape and extend along the second direction Y, and one end close to the third structure 392-1 is connected to the third structure 392-1.
  • the second pole 3132 of the thirteenth transistor T13 may include a fifth structure 3132-1 and a sixth structure 3132-2 connected to each other, the shape of the fifth structure 3132-1 It may be strip-shaped and extend along the first direction , between the first pole 3141 of the fourteenth transistor T14 and the second power line VGL in the first direction
  • the structures 3132-1 are connected, and the orthographic projection of the sixth structure 3132-2 on the substrate at least partially overlaps with the orthographic projection of the second signal output line IEM_OUT on the substrate.
  • the first pole 3121 of the twelfth transistor T12 and the first pole 3141 of the fourteenth transistor T14 are both in an "L" shape and are located away from the fourth connection line CL4 and the third One side of the power line VGH2.
  • the shift register may include: first to fourteenth transistors T1 to T14;
  • all transistors and capacitors are located between the third power line VGH2 and the second power line VGL.
  • the second capacitor C2 is located between the third power line VGH2 and the eighth transistor T8 During the period, the eighth transistor T8 is located between the second capacitor C2 and the ninth and tenth transistors T9 and T10.
  • the ninth and tenth transistors T9 and T10 are located between the eighth transistor T8 and the second power line VGL.
  • the transistor T11 and the twelfth transistor T12 are located between the third power line VGH2 and the thirteenth transistor T13 and the fourteenth transistor T14.
  • the thirteenth transistor T13 and the fourteenth transistor T14 are located between the eleventh transistor T11 and the twelfth transistor T11.
  • the thirteenth transistor T13, the fourteenth transistor T14, the third capacitor C3, the ninth transistor T9, the tenth transistor T10, and the first capacitor C1 along the The second direction Y is arranged in sequence.
  • the first conductive layer may also include a first power line VGH1, which may be connected to the first power terminal VGH; the first power line VGH1 may be in the shape of "L" type;
  • the first power line VGH1 may be located on the side of the first plate C31 of the third capacitor C3 away from the first plate C21 of the second capacitor C2; In the two directions Y, the first power line VGH1 may be located between the control electrode of the fourteenth transistor T14 and the first plate C11 of the first capacitor C1.
  • the orthographic projection of the first power line VGH1 on the substrate at least partially overlaps the orthographic projection of the first pole 391 of the ninth transistor T9 on the substrate.
  • the first pole 381 of the eighth transistor T8 and the first pole 391 of the ninth transistor T9 in the third conductive layer may be an integrally formed structure.
  • the first conductive layer may also include a power connection line VCL
  • the second conductive layer may also include a first signal output line EM_OUT and a second signal output line IEM_OUT;
  • the shapes of the first signal output line EM_OUT and the second signal output line IEM_OUT may both be polygonal lines extending along the first direction X;
  • the first signal output line EM_OUT may be located between the second plate C12 of the first capacitor C1 and the second plate C32 of the third capacitor C3.
  • the signal output line IEM_OUT may be located on a side of the second plate C32 of the third capacitor C3 away from the second plate C12 of the first capacitor C1; in the first direction X, the first signal output line EM_OUT and the second signal output line IEM_OUT is located on the side of the second plate C32 of the third capacitor C3 away from the second plate C22 of the second capacitor C2.
  • the power connection line VCL may be of "n" type, and may be located far away from the control electrode of the thirteenth transistor T13 and the control electrode of the fourteenth transistor T14 in the second direction Y. on one side, and is provided with an opening on the side away from the thirteenth transistor T13; in an exemplary embodiment, as shown in FIG. 17b and FIGS. 20a-20b, the orthographic projection of the power connection line VCL on the substrate can be respectively connected with the third transistor T13.
  • the orthographic projections of the second power line VGL and the first pole of the thirteenth transistor T13 on the substrate at least partially overlap.
  • the first conductive layer may further include a second connection line CL2, and the second connection line CL2 may be connected to the first plate C31 and the third plate C31 of the third capacitor C3.
  • the control electrode 29 of the ninth transistor T9 and the control electrode 211 of the eleventh transistor T11 are integrally formed.
  • the shape of the control electrode 211 of the eleventh transistor T11 can be in an "n" shape, and is provided with an opening toward the side of the twelfth transistor T12. .
  • the second pole 392 of the ninth transistor T9 may include a third structure 392-1, a fourth structure 392-2, and a ninth structure 392-3 connected to each other,
  • the third structure 392-1 may be in a strip shape and extend along the first direction X. It is located between the second pole 382 of the eighth transistor T8 and the second power line VGL.
  • the fourth structure 392-2 is connected; the fourth structure 392-2 may be in a strip shape, may be located on the side of the second power line VGL close to the third power line VGH2, and extend along the second direction Y, close to the third structure
  • One end of 392-1 is connected to the third structure 392-1; the ninth structure 392-3 is in the shape of a strip and is located on the side of the fourth structure 392-2 away from the second power line VGL.
  • the fourth structure 392-3 is on The orthographic projection on the substrate at least partially overlaps the orthographic projection of the control electrode 24 of the fourth transistor T4 on the substrate.
  • the second pole 3132 of the thirteenth transistor T13 may be a strip structure and extend along the first direction X
  • the first pole 3131 of the thirteenth transistor T13 may be It includes a seventh structure 3131-1 and an eighth structure 3131-2 connected to each other.
  • the shape of the seventh structure 3131-1 may be a strip and extends along the first direction X, with one end connected to the first electrode of the eleventh transistor T11. 3111 is connected, and the other end is connected to the eighth structure 3131-2; the eighth structure 3131-2 can be a square structure and can be integrally formed with the seventh structure 3131-1.
  • the orthographic projection and power supply of the eighth structure on the 3131-2 base The orthographic projections of the connecting lines VCL on the substrate at least partially overlap.
  • the first poles of the twelfth transistor T12 and the fourteenth transistor T14 may be strip structures extending along the first direction X and connected to each other. One end of the first pole 3121 of T12 is connected to the third power line VGH2, and the other end is connected to the first pole 3141 of the fourteenth transistor T14.
  • the first pole 3141 of the fourteenth transistor T14 may be located at the first pole of the twelfth transistor T12. On the side of the pole 3121 away from the third power line VGH2, the first pole 3121 of the twelfth transistor T12 may be integrated with the first pole 3141 of the fourteenth transistor T14 and the third power line VGH2.
  • the third conductive layer may further include a signal input line IN.
  • the signal input line IN may be in the shape of a polygonal line and extend along the first direction X. In the plane where the third conductive layer is located, in the first direction X, the signal input line IN may be located between the third power line VGH2 and the second power line VGL; in the second direction Y, the signal input line IN may be located in the tenth
  • the transistor T10 is on a side away from the ninth transistor T9.
  • the signal input line IN and the first pole 311 of the first transistor T1 may have an integrally formed structure.
  • the second plate C22 of the second capacitor C2 and the first plate C31 of the third capacitor C3 may be arranged along the first direction side;
  • the shape of the second plate C12 of the first capacitor C1 may be a polygonal line and extends along the first direction
  • the orthographic projection of plate C11 on the substrate has an overlapping area; the shape of the second plate C22 of the second capacitor C2 can be square, and the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate is consistent with the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate.
  • the second plate C32 of the third capacitor C3 There is an overlapping area between the orthographic projection on the substrate and the orthographic projection of the first plate C31 of the third capacitor C3 on the substrate.
  • the power line connected to the first power terminal VGH may include a first power line VGH1 and a third power line VGH2.
  • the first power terminal VGH It can include one power terminal or multiple power terminals.
  • the first power terminal VGH may include a first sub-power terminal and a second sub-power terminal, the first power line VGH1 may be connected to the first sub-power terminal, and the third power line VGH2 may be connected to the second sub-power terminal.
  • any one of the ninth transistor T9, the tenth transistor T10, the thirteenth transistor T13, and the fourteenth transistor T14 may include A plurality of sub-transistors are connected in parallel, and the active layers of the multiple sub-transistors are arranged independently of each other.
  • the control poles of the multiple sub-transistors have an integrated structure.
  • the first poles of the multiple sub-transistors have an integrated structure, and the second poles of the multiple sub-transistors are integrated. Molded structure.
  • any one of the ninth transistor T9, the tenth transistor T10, the thirteenth transistor T13, and the fourteenth transistor T14 may include four sub-transistors connected in parallel, and the active layers of the four sub-transistors are independent of each other.
  • the control pole of the sub-transistors has an integrated structure.
  • the first pole of the four sub-transistors has an integrated structure, and the second pole of the four sub-transistors has an integrated structure.
  • the ninth transistor T9 may include a first sub-transistor T9-1, a second sub-transistor T9-2, which are connected in parallel with each other.
  • the layers are respectively the first sub-active layer 19-1, the second sub-active layer 19-2, the third sub-active layer 19-3, the fourth sub-active layer 19-4, and the first sub-transistor T9-1
  • the control electrodes of the second sub-transistor T9-2, the third sub-transistor T9-3, and the fourth sub-transistor T9-4 are integrally formed and form the control electrode 29 of the ninth transistor T9, and the first sub-transistor T9-1
  • the first poles of the second sub-transistor T9-2, the third sub-transistor T9-3, and the fourth sub-transistor T9-4 are integrally formed and form the first pole 391 of the ninth transistor T9.
  • the tenth transistor T10 may include a fifth sub-transistor T10-1, a sixth sub-transistor T10-2, a seventh sub-transistor T10-3, and an eighth sub-transistor T10-4 connected in parallel with each other.
  • the active layers of the sixth sub-transistor T10-2, the seventh sub-transistor T10-3, and the eighth sub-transistor T10-4 are respectively the fifth sub-active layer 110-1, the sixth sub-active layer 110-2, and the seventh sub-transistor T10-2.
  • the control electrode has an integrated structure and forms the control electrode 210 of the tenth transistor T10, the first control electrode of the fifth sub-transistor T10-1, the sixth sub-transistor T10-2, the seventh sub-transistor T10-3, and the eighth sub-transistor T10-4.
  • the thirteenth transistor T13 may include a ninth sub-transistor T13-1, a tenth sub-transistor T13-2, an eleventh sub-transistor T13-3, a twelfth sub-transistor T13-4 connected in parallel with each other.
  • the active layers of the tenth sub-transistor T13-2, the eleventh sub-transistor T13-3, and the twelfth sub-transistor T13-4 are the ninth sub-active layer 113-1 and the tenth sub-active layer 113 respectively. -2.
  • the control electrode of the twelfth sub-transistor T13-4 has an integrated structure and forms the control electrode 213 of the thirteenth transistor T13, the ninth sub-transistor T13-1, the tenth sub-transistor T13-2, and the eleventh sub-transistor T13-3.
  • the first pole of the twelfth sub-transistor T13-4 has an integrated structure and forms the first pole 3131 of the thirteenth transistor T13, the ninth sub-transistor T13-1, the tenth sub-transistor T13-2, the eleventh sub-transistor T13-3 and the second pole of the twelfth sub-transistor T13-4 are integrally formed and form the second pole 3132 of the thirteenth transistor T13;
  • the fourteenth transistor T14 may include a thirteenth sub-transistor T14-1, a fourteenth sub-transistor T14-2, a fifteenth sub-transistor T14-3, a sixteenth sub-transistor T14-4 connected in parallel with each other.
  • the active layers of the transistor T14-1, the fourteenth sub-transistor T14-2, the fifteenth sub-transistor T14-3, and the sixteenth sub-transistor T14-4 are respectively the thirteenth sub-active layer 114-1 and the tenth sub-transistor T14-1.
  • the control electrodes of the fifteenth sub-transistor T14-3 and the sixteenth sub-transistor T14-4 can be integrally formed and form the control electrode 214 of the fourteenth transistor T14, and the thirteenth sub-transistor T14-1 and the fourteenth sub-transistor T14-4 can be formed in an integrated structure.
  • the first poles of T14-2, the fifteenth sub-transistor T14-3, and the sixteenth sub-transistor T14-4 may be integrally formed and form the first pole 3141 of the fourteenth transistor T14, and the thirteenth sub-transistor T14- 1.
  • the second poles of the fourteenth sub-transistor T14-2, the fifteenth sub-transistor T14-3, and the sixteenth sub-transistor T14-4 may be integrally formed and form the second pole 3142 of the fourteenth transistor T14.
  • the ninth transistor T9 and the tenth transistor T10 connected to the first output signal line EM_OUT are both connected in parallel by multiple sub-transistors, and the active layers of the multiple sub-transistors in any one transistor are set independently of each other.
  • the control poles of multiple sub-transistors are integrated, the first poles of multiple sub-transistors are integrated, and the second poles of multiple sub-transistors are integrated, which can improve the reliability of the output of the first output signal terminal EM_OUT of the shift register.
  • a large The transistor is divided into multiple small transistors, which can help dissipate heat.
  • the thirteenth transistor T13 and the fourteenth transistor T14 connected to the second output signal line IEM_OUT are both connected in parallel by multiple sub-transistors, and the active layers of the multiple sub-transistors in any one transistor are independent of each other. It is set that the control poles of multiple sub-transistors are integrally formed, the first poles of multiple sub-transistors are integrally formed, and the second poles of multiple sub-transistors are integrally formed, which can improve the reliability of the output of the first output signal terminal EM_OUT of the shift register. In addition, the Splitting a large transistor into multiple smaller transistors can help dissipate heat.
  • the first transistor T1 , the fourth transistor T4 to the seventh transistor T7 are located on the third power line VGH2 and the second capacitor C2, the second transistor T2 and the third transistor T3 are located between the fifth transistor T5 and the first capacitor C1.
  • the second electrode 362 of the sixth transistor T6 and the first electrode 71 of the seventh transistor T7 may share one electrode
  • the second electrode of the ninth transistor T9 The diode 392 and the second pole 3102 of the tenth transistor T10 may share one electrode
  • the second pole 3132 of the thirteenth transistor T13 and the second pole 3142 of the fourteenth transistor T14 may share one electrode.
  • two transistors share one electrode, which can save wiring space to a large extent.
  • the structures shown in Figure 15a and Figure 20a can be selected according to actual conditions, wherein the structure shown in Figure 20a can be applied to display substrates with higher PPI and can be suitable for narrow borders.
  • the structure shown in Figure 15a can be applied to a 1000PPI display substrate
  • the structure shown in Figure 20a can be applied to a 1200PPI display substrate.
  • the first power line VGH1 and the third power line VGH2 may provide the same power signal.
  • the above-mentioned first power terminal VGH may be electrically connected to the first power line VGH1 and the third power line VGH2.
  • the first direction X and the second direction Y intersect on a plane parallel to the display substrate.
  • the following is an exemplary description through the preparation process of the display substrate.
  • the "patterning process" mentioned in this disclosure includes processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist for metal materials, inorganic materials, or transparent conductive materials.
  • organic materials it includes Processes such as coating of organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them are not limited by this disclosure.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate (or substrate). If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged on the same layer” mentioned in this disclosure means that A and B are formed simultaneously through the same patterning process, and the “thickness” of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • “the orthographic projection of B is within the range of the orthographic projection of A” or "the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the orthographic projection of A. within the bounds of A, or the bounds of the orthographic projection of A overlap with the bounds of the orthographic projection of B.
  • the preparation process of the display substrate may include the following operations.
  • Form a semiconductor layer pattern on the substrate may include: depositing a semiconductor film on the substrate, patterning the semiconductor film through a patterning process, and forming a semiconductor layer pattern, as shown in FIG. 11 . Shown is a schematic diagram after forming a semiconductor layer pattern on a substrate.
  • the semiconductor layer pattern may include an active layer 11 of the first transistor T1 , an active layer 12 of the second transistor T2 , an active layer 13 of the third transistor T3 , a fourth The active layer 14 of the transistor T4, the active layer 15 of the fifth transistor T5, the active layer 16 of the sixth transistor T6, the active layer 17 of the seventh transistor T7, the active layer 18 of the eighth transistor T8, the ninth The active layer 19 of the transistor T9, the active layer 110 of the tenth transistor T10, the active layer 111 of the eleventh transistor T11, the active layer 112 of the twelfth transistor T12, and the active layer 113 of the thirteenth transistor T13 , the active layer 114 of the fourteenth transistor T14.
  • the active layer 111 of the eleventh transistor T11 and the side of the active layer 114 of the fourteenth transistor T14 in the plane where the semiconductor layer is located, in the first direction and the side of the active layer 110 of the tenth transistor T10 away from the active layer 113 of the thirteenth transistor T13 and the active layer 114 of the fourteenth transistor T14, the active layer 111 of the eleventh transistor T11 and the side of the active layer 114 of the fourteenth transistor T14.
  • the active layer 112 of the transistor T12 is located between the active layer 19 of the ninth transistor T9 and the active layer 113 of the thirteenth transistor T13, and the active layer 19 of the ninth transistor T9 and the active layer 110 of the tenth transistor T10 , the active layer 11 of the eleventh transistor T11, the active layer 112 of the twelfth transistor T12, the active layer 113 of the thirteenth transistor T13, and the active layer 114 of the fourteenth transistor T14 in sequence along the first direction X. arrangement.
  • the active layer 11 of the first transistor T1 to the active layer 18 of the eighth transistor T8 extend in the first direction X.
  • the active layer 14 of the fourth transistor T4 is located between the active layer 11 of the first transistor T1 and the active layer 16 of the sixth transistor T6, for example, the sixth transistor T4
  • the active layer 16 of the transistor T6, the active layer 14 of the fourth transistor T4, and the active layer 11 of the first transistor T1 are sequentially arranged along the second direction Y.
  • the active layer 14 of the fourth transistor T4, the active layer 15 of the fifth transistor T5, the active layer 13 of the third transistor T3, and the active layer 12 of the second transistor T2 are arranged along the first direction. X is arranged in sequence. In the second direction Y, the active layer 11 of the first transistor T1, the active layer 12 of the second transistor T2, the active layer 13 of the third transistor T3, and the active layer of the fifth transistor T5 15 is located on a side of the active layer 14 of the fourth transistor T4 away from the active layer 16 of the sixth transistor T6.
  • the active layer 16 of the sixth transistor T6, the active layer 17 of the seventh transistor T7, and the active layer 18 of the eighth transistor T8 are sequentially arranged along the first direction X.
  • the active layer 16 and the active layer 17 of the seventh transistor T7 may be an integrally formed structure.
  • the active layer 17 of the seventh transistor T7 and the active layer 18 of the eighth transistor T8 are located on the side of the active layer 16 of the sixth transistor T6 away from the active layer 11 of the first transistor T1.
  • the active layer 19 of the ninth transistor T9 is located on one side of the active layer 110 of the tenth transistor T10.
  • the active layer 19 of the ninth transistor T9, The active layers 110 of the transistors T10 are arranged along the second direction Y.
  • the active layer 19 of the ninth transistor T9 and the active layer 110 of the tenth transistor T10 are integrally formed structures.
  • the active layer 11 of the eleventh transistor T11 is located on one side of the active layer 112 of the twelfth transistor T12, for example, the active layer of the twelfth transistor T12 112.
  • the active layer 11 of the eleventh transistor T11 is arranged along the second direction Y.
  • the active layer 11 of the eleventh transistor T11 and the twelfth transistor T12 may be an integrally formed structure.
  • the active layer 113 of the thirteenth transistor T13 is located on one side of the active layer 114 of the fourteenth transistor T14 , for example, the active layer 113 of the fourteenth transistor T14 114.
  • the active layer 113 of the thirteenth transistor T13 is arranged along the second direction Y.
  • the active layer 113 of the thirteenth transistor T13 and the active layer 114 of the fourteenth transistor T14 may be an integrally formed structure.
  • the active layers of the first to fourteenth transistors T1 to T14 may have a rectangular structure.
  • the active layers of the first to fourteenth transistors T1 to T14 are semiconductor layers formed based on silicon technology.
  • the width of the active layer of the ninth transistor T9, the tenth transistor T10, the thirteenth transistor T13, and the fourteenth transistor T14 is larger than the width of the active layer of the other transistors, so that the ninth transistor The width-to-length ratio (W/L) of T9, the tenth transistor T10, the thirteenth transistor T13, and the fourteenth transistor T14 is relatively large.
  • the size of the active layer of the ninth transistor T9, the tenth transistor T10, the thirteenth transistor T13, and the fourteenth transistor T14 along the first direction X is larger than that of the active layer 111 of the eleventh transistor T11 along the first direction X. The size is large.
  • the active layers of the ninth transistor T9 , the tenth transistor T10 , the thirteenth transistor T13 and the fourteenth transistor T14 may each be configured to include a plurality of mutually separated active layer structures.
  • the active layer 19 of the ninth transistor T9 may include four mutually separated active layers, and the four mutually separated active layers of the ninth transistor T9 may include a first sub-active layer 19-1, a second sub-active layer 19-1 and a second sub-active layer 19-1.
  • the active layer 19-2, the third sub-active layer 19-3, the fourth sub-active layer 19-4, and the active layer 110 of the tenth transistor T10 may include four mutually separated active layers.
  • the tenth transistor The four mutually separated active layers of T10 may include a fifth sub-active layer 110-1, a sixth sub-active layer 110-2, a seventh sub-active layer 110-3, and an eighth sub-active layer 110- 4.
  • the fifth sub-active layer 110-1 and the first sub-active layer 19-1 can be integrally formed, and the sixth sub-active layer 110-2 and the second sub-active layer 19-2 can be integrally formed.
  • the seventh sub-active layer 110-3 and the third sub-active layer 19-3 can be an integrally formed rectangular structure, and the eighth sub-active layer 110-4 and the fourth sub-active layer 19-4 It can be a one-piece rectangular structure.
  • the active layer 113 of the thirteenth transistor T13 may include four mutually separated active layers, and the four mutually separated active layers of the thirteenth transistor T13 may include a ninth sub-active layer.
  • 113-1, the tenth sub-active layer 113-2, the eleventh sub-active layer 113-3, the twelfth sub-active layer 113-4, the active layer 114 of the fourteenth transistor T14 may include four Mutually separated active layers, the four mutually separated active layers of the fourteenth transistor T14 may include a thirteenth sub-active layer 114-1, a fourteenth sub-active layer 114-2, a fifteenth sub-active layer
  • the source layer 114-3, the sixteenth sub-active layer 114-4, the thirteenth sub-active layer 114-1 and the ninth sub-active layer 113-1 can be an integrally formed structure.
  • the fourteenth sub-active layer 114-2 and the tenth sub-active layer 113-2 can be an integrally formed rectangular structure, and the fifteenth sub-active layer 114-3 and the eleventh sub-active layer 113-3 can be an integrally formed rectangular structure.
  • the sixteenth sub-active layer 114-4 and the twelfth sub-active layer 113-4 may be an integrally formed rectangular structure.
  • the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal chips; the flexible substrate may be, but is not limited to, polyterephthalate. Ethylene glycol ester, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile One or more types of fiber.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer.
  • the first and second flexible material layers can be made of polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film.
  • the first and second inorganic materials The material of the layer can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., used to improve the water and oxygen resistance of the substrate.
  • the first and second inorganic material layers are also called barrier layers.
  • the materials of the semiconductor layer Amorphous silicon (a-si) can be used.
  • the preparation process may include: first coating a layer of polyimide on a glass substrate, and then curing to form a film.
  • a first flexible (PI1) layer then deposit a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then deposit a layer of amorphous silicon on the first barrier layer Thin film to form an amorphous silicon (a-si) layer covering the first barrier layer; then apply a layer of polyimide on the amorphous silicon layer, and solidify the film to form a second flexible (PI2) layer; then Deposit a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, completing the preparation of the substrate.
  • the first semiconductor layer may be polysilicon (p-Si), that is, the first to fourteenth transistors T1 to T14 may be LTPS thin film transistors.
  • patterning the first semiconductor film through a patterning process may include: first forming an amorphous silicon (a-si) film on the first insulating film, and performing dehydrogenation treatment on the amorphous silicon film , the dehydrogenated amorphous silicon film is crystallized to form a polycrystalline silicon film. Subsequently, the polysilicon film is patterned to form a first semiconductor layer pattern.
  • forming the first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on a substrate on which the foregoing pattern is formed, patterning the first conductive film through a patterning process, and forming The first insulating layer covering the semiconductor layer pattern, and the first conductive layer pattern disposed on the first insulating layer, are shown in Figures 12a and 12b.
  • Figure 12a shows a schematic diagram after the first conductive layer pattern is formed.
  • Figure 12b is a schematic plan view of the first conductive layer in FIG. 12a.
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern may include at least: a first plate C11 of the first capacitor C1, a first plate C21 of the second capacitor C2, a first plate C31 of the third capacitor C3,
  • the first plate C11 of the first capacitor C1, the control electrode 210 of the tenth transistor T10, the control electrode 28 of the eighth transistor T8, the first connection line CL1, and the control electrode 23 of the third transistor T3 It can be a one-piece structure.
  • the first plate C31 of the third capacitor C3, the second connection line CL2, and the control electrode 29 of the ninth transistor T9 may have an integrally formed structure.
  • the control electrode 25 of the fifth transistor T5, the third connection line CL3, and the control electrode 27 of the seventh transistor T7 may have an integrated structure.
  • the control electrode 24 of the fourth transistor T4 and the control electrode 26 of the sixth transistor T6 may have an integrally formed structure.
  • the control electrode 22 of the second transistor T2 and the control electrode 21 of the first transistor T2 may have an integrally formed structure.
  • the control electrode 212 of the twelfth transistor T12, the control electrode 214 of the fourteenth transistor T14, and the first output line EM_OUT may have an integrated structure.
  • the main body portion of the first plate C11 of the first capacitor C1 may be in a strip shape extending along the first direction X.
  • the first plate C11 of the first capacitor C1 may be The control electrode 210 of the tenth transistor T10 is located on a side away from the first plate C31 of the third capacitor C3.
  • the first plate C11 of the first capacitor C1 may be located on the control electrode of the eighth transistor T8. 28 is away from the side of the first plate C21 of the second capacitor C2.
  • a first connection portion C11-1 is provided on a side of the first plate C11 of the first capacitor C1 close to the control electrode 210 of the tenth transistor T10, and the first connection portion C11-1 is along the second direction. Y extends, one end is connected to the first plate C11 of the first capacitor C1, and the other end is connected to the control electrode 210 of the tenth transistor T10.
  • the shape of the first plate C21 of the second capacitor C2 may be square, and in the first direction X, the first plate C21 of the second capacitor C2 may be located at the control electrode 27 of the seventh transistor T7 In the second direction Y, between the control electrode 28 of the eighth transistor T8 and the first plate C21 of the second capacitor C2, the first plate C21 of the second capacitor C2 may be located at a point away from the control electrode 23 of the third transistor T3 and away from the control electrode 22 of the second transistor T2.
  • a protrusion is provided on the edge of the first plate C21 of the second capacitor C2 close to the control electrode 27 of the seventh transistor T7, and the first plate C21 of the second capacitor C2 is close to the control electrode 28 of the eighth transistor T8.
  • the edge on one side and the edge on the side close to the control electrode 23 of the third transistor T3 are stepped.
  • the shape of the first plate C31 of the third capacitor C3 may be a polygonal line and extend along the first direction X.
  • the first plate C31 of the third capacitor C3 may be The control electrode 29 of the ninth transistor T9 is located on a side away from the first plate C11 of the first capacitor C1; in the first direction X, the first plate C31 of the third capacitor C3 may be located on the control electrode of the eighth transistor T8. 28 is away from the side of the first plate C21 of the second capacitor C2.
  • one end of the first plate C31 of the third capacitor C3 close to the control electrode 28 of the eighth transistor T8 is connected to the second connection line CL2.
  • the shape of the control electrode 21 of the first transistor T1 may be a polygonal line shape and extend along the first direction X.
  • the control electrode 21 of the first transistor T1 in the second direction Y, may be located on a side of the control electrode 22 of the second transistor T2 away from the first plate of the first capacitor C1, and on a side close to the first plate of the first capacitor C1.
  • One side of the first plate of a capacitor C1 is connected to the control electrode 22 of the second transistor T2.
  • the shape of the control electrode 22 of the second transistor T2 may be "n" type, and may be provided with an opening toward the first plate C21 side of the second capacitor C2.
  • the control electrode 22 of the second transistor T2 in the second direction Y, may be located on a side of the control electrode 210 of the tenth transistor T10 away from the first plate C31 of the third capacitor C3, on the first In the direction One side of the control electrode 21 of T1 is connected to the control electrode 21 of the first transistor T1.
  • the control electrode 23 of the third transistor T3 may be located between the control electrode 22 of the second transistor T2 and the first plate C21 of the second capacitor C2. On the One side is connected to the control electrode 28 of the eighth transistor T8 through the first connection line CL1.
  • the shape of the third transistor T3 may be an inverted "n" type, and may be provided with an opening toward the control electrode 22 of the second transistor T2.
  • the control electrode 24 of the fourth transistor T4 may be located between the control electrode 21 of the first transistor T1 and the control electrode 26 of the sixth transistor T6.
  • the control electrode of the fourth transistor T4 The side of the electrode 24 away from the control electrode 21 of the first transistor T1 is connected to the control electrode 26 of the sixth transistor T6.
  • the shape of the control electrode 24 of the fourth transistor T4 may be an inverted "T" shape.
  • the control electrode 25 of the fifth transistor T5 may be located between the control electrode 27 of the seventh transistor T7 and the control electrode 22 of the second transistor T2.
  • the shape of the control electrode 25 of the fifth transistor T5 may be strip-shaped and may extend along the second direction Y.
  • the control electrode 25 of the fifth transistor T5 is far away from the control electrode 22 of the second transistor T2.
  • One end is connected to the third connection line CL3.
  • control electrode 26 of the sixth transistor T6 may be located on a side of the control electrode 24 of the fourth transistor T4 away from the control electrode 22 of the second transistor T2, and the control electrode 26 of the sixth transistor T6 is close to the second transistor T2.
  • One side of the control electrode 22 of the transistor T2 is connected to the control electrode 24 of the fourth transistor T4.
  • the shape of the control electrode 26 of the sixth transistor T6 may be a "T" shape.
  • control electrode 27 of the seventh transistor T7 may be located on a side of the first plate C21 of the second capacitor C2 away from the control electrode 28 of the eighth transistor T8. In the second direction Y, the seventh transistor The control electrode 27 of T7 may be located on a side of the control electrode 25 of the fifth transistor T5 away from the control electrode 21 of the first transistor T1.
  • control electrode 27 of the seventh transistor T7 may include a first connection structure 27-1 extending along the first direction X and a second connection structure 27-2 extending along the second direction Y. In the first In the direction between pole 26 and the first plate C21 of the second capacitor C2. One end of the second connection structure 27-2 is connected to the third connection line CL3, and the other end is connected to the first connection structure 27-1.
  • control electrode 28 of the eighth transistor T8 may be in a strip shape and extend along the second direction Y. In the first direction The control electrode 28 may be located on a side of the first connection line CL1 away from the control electrode 22 of the second transistor T2, and at an end close to the control electrode 22 of the second transistor T2, connected to the third connection line CL3 and the control of the tenth transistor T10. Pole 210 connection.
  • the control electrode 29 of the ninth transistor T9 may be in a strip shape and extend along the first direction X. In an exemplary embodiment, in the second direction Y, the control electrode 29 of the ninth transistor T9 may be located between the control electrode 210 of the tenth transistor T10 and the first plate C31 of the third capacitor C3, and passes through the second The connection line CL2 is connected to the first plate C31 of the third capacitor C3. In the first direction X, the control electrode 29 of the ninth transistor T9 may be located between the control electrode 28 of the eighth transistor T8 and the control electrode of the fourteenth transistor T14 214, and is connected to the second connection line CL2 at one end close to the control electrode 28 of the eighth transistor T8.
  • the orthographic projection of the control electrode 29 of the ninth transistor T9 on the substrate is consistent with the first sub-active layer 19-1, the second sub-active layer 19-2, and the third sub-active layer 19-1. 3.
  • the control electrode 210 of the tenth transistor T10 may have a strip structure and extend along the first direction X. In the second direction Y, the control electrode 210 of the tenth transistor T10 may be located on the ninth transistor T9 between the control electrode 29 and the first plate C11 of the first capacitor C1, and the edge on the side away from the first plate C11 of the first capacitor C1 may be stepped. In an exemplary embodiment, in the first direction X, one end of the control electrode 210 of the tenth transistor T10 is connected to the control electrode 28 of the eighth transistor T8, and the other end is connected to the first plate C11 of the first capacitor C1.
  • the orthographic projection of the control electrode 210 of the tenth transistor T10 on the substrate is consistent with the fifth sub-active layer 110-1, the sixth sub-active layer 110-2, and the seventh sub-active layer 110- 3. There is an overlapping area in the orthographic projection of the eighth sub-active layer 110-4 on the substrate.
  • control electrode 210 of the tenth transistor T10 is provided across the fifth sub-active layer 110-1, the sixth sub-active layer 110-2, the seventh sub-active layer 110-3, and the eighth sub-active layer 110 -4, a fifth sub-transistor T10-1, a sixth sub-transistor T10-2, a seventh sub-transistor T10-3, and an eighth sub-transistor T10-4 are formed in parallel with each other.
  • control electrode 211 of the eleventh transistor T11 may be located between the control electrode 210 of the tenth transistor T10 and the control electrode 213 of the thirteenth transistor T13 in the first direction X.
  • the control electrode 211 of the eleventh transistor T11 may be located on a side of the control electrode 212 of the twelfth transistor T12 away from the first power line VGH1.
  • the control electrode 211 of the eleventh transistor T11 may be in an "L" shape.
  • control electrode 212 of the twelfth transistor T12 may be in a zigzag shape and extend along the first direction X.
  • the main part of the control electrode 212 of the twelfth transistor T12 may be located between the control electrode 213 of the thirteenth transistor T13 and the first power line VGH1.
  • the control electrode 212 of the twelfth transistor T12 may be located between the control electrode 29 of the ninth transistor T9 and the control electrode 214 of the fourteenth transistor T14.
  • control electrode 213 of the thirteenth transistor T13 may be in an "L" shape, and in the first direction X, the control electrode 213 of the thirteenth transistor T13 may be located at the control electrode 211 of the eleventh transistor T11 On the side away from the control electrode 210 of the tenth transistor T10, in the second direction Y, the control electrode 213 of the thirteenth transistor T13 may be located on the side of the control electrode 214 of the fourteenth transistor T14 away from the first power line VGH1.
  • the orthographic projection of the control electrode 213 of the thirteenth transistor T13 on the substrate is in contact with the ninth sub-active layer 113-1, the tenth sub-active layer 113-2, and the eleventh sub-active layer 113. -3.
  • ninth sub-transistor T13-1, tenth sub-transistor T13-2, eleventh sub-transistor T13-3, and twelfth sub-transistor T13-4 are formed in parallel with each other.
  • the control electrode 214 of the fourteenth transistor T14 may be in a strip shape and extend in the first direction X. In an exemplary embodiment, in the first direction X, the control electrode 214 of the fourteenth transistor T14 may be located between the control electrode 212 of the twelfth transistor T12 and the first signal output line EM_OUT. The output line EM_OUT is connected, and the other end is connected to the control electrode 212 of the twelfth transistor T12. In the second direction Y, the control electrode 214 of the fourteenth transistor T14 can be located between the control electrode 213 of the thirteenth transistor T13 and the first power supply. between lines VGH1.
  • the orthographic projection of the control electrode 214 of the fourteenth transistor T14 on the substrate is in contact with the thirteenth sub-active layer 114-1, the fourteenth sub-active layer 114-2, the fifteenth sub-active layer There is an overlapping area in the orthographic projections of the layer 114-3 and the sixteenth sub-active layer 114-4 on the substrate. That is, the control electrode 214 of the fourteenth transistor T14 is disposed across the thirteenth sub-active layer 114-1, the fourteenth sub-active layer 114-2, the fifteenth sub-active layer 114-3, the sixteenth sub-active layer 114-1, and the sixteenth sub-active layer 114-2.
  • a thirteenth sub-transistor T14-1, a fourteenth sub-transistor T14-2, a fifteenth sub-transistor T14-3, and a sixteenth sub-transistor T14-4 are formed in parallel with each other.
  • the first connection line CL1 may be in a strip shape and extend along the first direction X. In the first direction X, the first connection line CL1 may be located between the control electrode 23 of the third transistor T3 and Between the control electrode 210 of the tenth transistor T10, one end is connected to the control electrode 23 of the third transistor T3, and the other end is connected to the control electrode 210 of the tenth transistor T10 and the control electrode 28 of the eighth transistor T8; in the second direction Y , the first connection line CL1 may be located between the control electrode of the second transistor T2 and the first plate C21 of the second capacitor C2.
  • the shape of the second connection line CL2 may include a first sub-connection structure CL21 and a second sub-connection structure CL22.
  • the first sub-connection structure CL21 may be in an "L" shape
  • the second sub-connection structure CL22 may be It is a strip structure extending along the first direction X. In the first direction One side of the control electrode 28 of the eighth transistor T8 is connected to the second sub-connection structure CL22.
  • the second sub-connection structure CL22 may be located between the control electrode 28 of the eighth transistor T8 and the first plate C31 of the third capacitor C3, and One end of the second sub-connection structure CL22 close to the control electrode 28 of the eighth transistor T8 is connected to the first sub-connection structure CL21, and the other end is connected to the first plate C31 of the third capacitor C3; in the second direction Y, the first The sub-connection structure CL21 may be located on the side of the control electrode 210 of the tenth transistor T10 away from the first plate C11 of a capacitor C1, and the second sub-connection structure CL22 may be located on the control electrode 29 of the ninth transistor T9 away from the side of the tenth transistor T10. One side of the control pole 210.
  • the shape of the third connection line CL3 may be square.
  • the third connection line CL3 may be located at the first plate C31 of the third capacitor C3 and the control electrode of the fourth transistor T4. 24, one end is connected to the control electrode 27 of the seventh transistor T7, and the other end is connected to the control electrode 25 of the fifth transistor T5.
  • the first signal output line EM_OUT may be in a strip shape and extend along the first direction X.
  • the first signal output line EM_OUT may be located under the control of the thirteenth transistor T13 Between the pole 213 and the first power line VGH1, and on the edge close to the first power line VGH1, the edge may be stepped.
  • One side of the control electrode 214 of T14 is connected to the control electrode 214 of the fourteenth transistor T14.
  • the second signal output line IEM_OUT may be in an "L" shape. In the second direction Y, the second signal output line IEM_OUT may be located away from the first power line VGH1 and away from the first output line EM_OUT. On one side, in the first direction X, the second output line IEM_OUT may be located on the side of the first plate C31 of the third capacitor C3 away from the control electrode 28 of the eighth transistor T8.
  • the first power line VGH1 may be in a polygonal shape and extend along the first direction X. In the second direction Y, the first power line VGH1 may be located between the first output signal line EM_OUT and the second Between the signal output lines IEM_OUT. In the first direction X, the first sub-power line VGH1 may be located on a side of the control electrode 29 of the ninth transistor T9 away from the control electrode 28 of the eighth transistor T8.
  • the control electrodes of the first to fourteenth transistors T1 to T14 are respectively disposed across the active layers of the first to fourteenth transistors T1 to T14 , that is, the first to fourteenth transistors T1 to T14
  • the orthographic projection of the control electrode of the transistor T14 on the substrate has an overlapping area with the orthographic projection of the active layer of the first to fourteenth transistors T1 to T14 respectively.
  • the extending directions of the control electrodes of the first to eighth transistors T1 to T8 and the eleventh to twelfth transistors T11 to T12 are respectively in the same direction as the first to eighth transistors T1 to T12 .
  • the extension directions of the active layers of the eighth transistor T8 and the eleventh to twelfth transistors T11 to T12 are vertical.
  • this process also includes a conductorization process.
  • the conductorization process is to use the control electrode 21 of the first transistor T1, the control electrode 22 of the second transistor T2, the control electrode 23 of the third transistor T3, the control electrode 24 of the fourth transistor T4, after forming the first conductive layer pattern.
  • the control electrode 210, the control electrode 211 of the eleventh transistor T11, the control electrode 212 of the twelfth transistor T12, the control electrode 213 of the thirteenth transistor T13, and the control electrode 214 of the fourteenth transistor T14 block the semiconductor layer in the area (i.e. The area where the semiconductor layer overlaps each control electrode) serves as the channel area of the transistor.
  • the semiconductor layer in the area not blocked by the first conductive layer is processed into a conductive layer to form a conductive source-drain electrode connection portion.
  • the first conductive film may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo). , or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, etc.
  • a metal material such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo).
  • alloy materials of the above metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, etc.
  • the first insulating film may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer or a multi-layer or composite layer.
  • the first insulating layer may be called a first gate insulating layer.
  • forming the second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on the substrate on which the foregoing pattern is formed, patterning the second conductive film using a patterning process, and forming The second insulating layer covering the first conductive layer, and the second conductive layer pattern disposed on the second insulating layer, are shown in Figures 13a to 13b.
  • Figure 13a shows a schematic diagram after the second conductive layer pattern is formed.
  • Figure 13b is a schematic plan view of the second conductive layer in Figure 13a.
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • GATE2 second gate metal
  • the second conductive layer pattern may include: a second plate C12 of the first capacitor C1, a second plate C22 of the second capacitor C2, and a second plate C22 of the third capacitor C3. Plate C32.
  • the second plate C22 of the second capacitor C2 and the second plate C32 of the third capacitor C3 are arranged along the first direction X, and the second plate C32 of the third capacitor C3 is arranged in the second direction Y.
  • the second plate C22 of the capacitor C2 and the second plate C32 of the third capacitor C3 may be located on the same side of the second plate C12 of the first capacitor C1.
  • the shape of the second plate C12 of the first capacitor C1 may be a polygonal line and extend along the first direction X. In an exemplary embodiment, there is an overlapping area between the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate and the orthographic projection of the first plate C11 of the first capacitor C1 on the substrate.
  • the first plate C12 of the first capacitor C1 may include a first connection part C121 and a second connection part C122 connected to each other, and the first connection part C121 may be along the first In the strip-shaped structure extending in the direction
  • the first connection portion C121 and the second connection portion C122 Arranged along the first direction
  • the shape of the second plate C22 of the second capacitor C2 may be square, and the edge of the second plate C22 of the second capacitor C2 may be stepped. In an exemplary embodiment, there is an overlapping area between the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate and the orthographic projection of the first plate C21 of the second capacitor C2 on the substrate.
  • the second plate C32 of the third capacitor C3 may be in a strip shape and extend along the first direction X.
  • the second plate C32 of the third capacitor C3 is close to the second plate C32 of the first capacitor C1.
  • the edge on one side of the electrode plate C12 may be in the form of a fold line.
  • the second conductive film may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo). , or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, etc.
  • a metal material such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo).
  • alloy materials of the above metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, etc.
  • the second insulating film may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer or a multi-layer or composite layer.
  • the first insulating layer may be called a second gate insulating layer.
  • forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the foregoing pattern is formed, patterning the third insulating film using a patterning process, and forming a pattern covering the second conductive layer.
  • the third insulating layer is provided with a plurality of via hole patterns, as shown in Figure 14.
  • Figure 14 is a schematic diagram of the planar structure after forming the third insulating layer pattern.
  • the plurality of via patterns may include: first to thirty-third vias V1 to V33, wherein the first to fourteenth vias V1 to V14 penetrate the first insulating layer, the The second insulating layer and the third insulating layer, the fifteenth via hole V15 to the thirtieth via hole V30 penetrate the second insulating layer and the third insulating layer, and the thirty-first via hole V31 to the thirty-third via hole V33 penetrate the second insulating layer.
  • the first via V1 exposes the active layer of the first transistor
  • the second via V2 exposes the active layer of the second transistor
  • the third via V3 exposes the active layer of the third transistor.
  • the fourth via V4 exposes the active layer of the fourth transistor
  • the fifth via V5 exposes the active layer of the fifth transistor
  • the sixth via V6 exposes the active layer of the sixth transistor
  • the seventh via V6 exposes the active layer of the sixth transistor.
  • Hole V7 exposes the active layer of the seventh transistor
  • eighth via hole V8 exposes the active layer of the eighth transistor
  • ninth via hole V9 exposes the active layer of the ninth transistor
  • tenth via hole V10 exposes the active layer of the ninth transistor.
  • the active layer of the tenth transistor, the eleventh via V11 exposes the active layer of the eleventh transistor, the twelfth via V12 exposes the active layer of the twelfth transistor, and the thirteenth via V13 exposes the active layer of the tenth transistor.
  • the active layer of the thirteenth transistor, the fourteenth via V14 exposes the active layer of the fourteenth transistor, the fifteenth via V15 and the sixteenth via V16 expose the control electrode 21 of the first transistor T1.
  • the seventeenth via V17 exposes the control electrode 23 of the third transistor T3, the eighteenth via V18 exposes the control electrode 24 of the fourth transistor T4, and the nineteenth via V19 to the twentieth via V20 expose the seventh transistor T3.
  • the control electrode 27 of the transistor T7, the twenty-first via V21 exposes the control electrode 211 of the eleventh transistor T11, the twenty-second via V22 exposes the control electrode 213 of the thirteenth transistor T13, and the twenty-third via hole V23 exposes the control electrode 212 of the twelfth transistor T12, the twenty-fourth via V24 to the twenty-sixth via V26 expose the first power line VGH1, and the twenty-seventh via V27 exposes the second signal output line IEM_OUT, the twenty-eighth via V28 exposes the second connection line CL2, the twenty-ninth via V29 exposes the first plate C21 of the second capacitor C2, and the thirtieth via V30 exposes the third capacitor C3
  • the first plate C31, the thirty-first via V31 exposes the second plate C22 of the second capacitor C2, the thirty-second via V32 exposes the second plate C32 of the third capacitor C3, and the thirty-third The via V33 exposes the second plate C12 of the first capacitor C1.
  • the number of the first to fourth via holes V1 to V4, the sixth to eighth via holes V6 to V8, the eleventh via hole V11, and the twelfth via hole V12 is two. , respectively configured to expose two electrode connection portions of the active layer of the transistor, wherein one of the eleventh via holes V11 and one of the twelfth via holes V12 are the same via hole.
  • the number of fifth via holes V5 is four, two of which expose the source electrode connection portion of the fifth transistor, and the other two via holes expose the drain electrode connection portion of the fifth transistor.
  • the number of the ninth via holes V9 and the tenth via hole V10 is multiple, and the multiple via holes are arranged in an array; the multiple ninth via holes V9 are arranged along the first direction X to form a plurality of via holes. Column via holes are arranged along the second direction Y to form two rows of via holes; a plurality of tenth via holes V10 are arranged along the first direction X to form multiple columns of via holes, and are arranged along the second direction Y to form two rows of via holes; Moreover, the ninth via hole V9 in one row and the tenth via hole V10 in one row are the same row of via holes.
  • the number of the thirteenth via holes V13 and the fourteenth via holes V14 is multiple, and the multiple via holes are arranged in an array; the multiple thirteenth via holes V13 are arranged along the first direction X A plurality of fourteenth via holes V14 are arranged along the first direction X to form multiple columns of via holes, and are arranged along the second direction Y to form two rows of via holes. rows of via holes; and one of the thirteenth via holes V13 and one of the fourteenth rows of via holes V14 are the same row of via holes.
  • the fifteenth via hole V15, the seventeenth via hole V17, the eighteenth via hole V18, the twentieth via hole V20 to the twenty-third via hole V23, and the twenty-sixth via hole V26 , the number of the twenty-seventh via hole V27, the twenty-ninth via hole V29 to the thirty-third via hole V33 may be one or more, for example, the fifteenth via hole V15, the sixteenth via hole V16, the The number of the eighteenth via hole V18 and the twenty-fourth via hole V24 to the thirty-third via hole V33 may be two, and the two via holes are arranged along the first direction X.
  • the number of the twenty-fourth to twenty-fifth via holes V24 to V25 and the twenty-eighth via hole V28 may be one or more.
  • the twenty-fourth to twenty-fifth via holes V24 to V28 may be one or more.
  • the number of the twenty-fifth via hole V25 and the twenty-eighth via hole V28 may be two, and the two via holes are arranged along the second direction Y.
  • the number of the sixteenth via hole V16 and the nineteenth via hole V19 may be one.
  • the third insulating film may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer or a multi-layer or composite layer.
  • the first insulating layer may be called a second gate insulating layer.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the foregoing pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive film disposed on the third insulating layer.
  • the third conductive layer is as shown in Figures 15a to 15b.
  • Figure 15a is a schematic view after the third conductive layer is formed
  • Figure 15b is a schematic plan view of the third conductive layer in Figure 15a.
  • the third conductive layer may be referred to as a source-drain metal (SD) layer.
  • SD source-drain metal
  • the third conductive layer pattern may include: an initial signal line STV, a signal input line IN, a first clock signal line CLK, a second clock signal line CLKB, a third power supply line VGH2, a second power supply line VGL , the first pole and the second pole of the first transistor T1 to the fourteenth transistor T14, and the fourth connection line CL4.
  • the first pole 311 of the first transistor T1 and the signal input line IN may be of an integrally formed structure
  • the second pole 312 of the first transistor T1 and the second pole of the fifth transistor T5 may be of an integrally formed structure.
  • the first pole 321 of the second transistor T2, the first pole 3101 of the tenth transistor T10, the first pole 3111 of the eleventh transistor T11, the first pole 3131 of the thirteenth transistor T13, and the second power line VGL may be integrated.
  • Molded structure: the second pole 322 of the second transistor T2 and the second pole 332 of the third transistor T3 may have an integrally molded structure.
  • the first pole 341 of the fourth transistor T4 and the third power line VGH2 may have an integrally formed structure
  • the second pole 342 of the fourth transistor T4 and the first pole 351 of the fifth transistor T5 may have an integrally formed structure
  • the second electrode 362 of the sixth transistor T6 and the first electrode 371 of the seventh transistor T7 may share an electrode.
  • the second pole 372 of the seventh transistor T7 and the second pole of the eighth transistor T8 may have an integrally formed structure
  • the first pole 381 of the eighth transistor T8 and the first pole 391 of the ninth transistor T9 may have an integrally formed structure.
  • the first pole 3121 of the twelfth transistor T12 and the first pole 3141 of the fourteenth transistor T14 may have an integrally formed structure.
  • the first pole 311 and the second pole 312 of the first transistor T1 are connected to the active layer 11 of the first transistor T1 through two first via holes V1 respectively.
  • the first pole 321 and the second pole 322 of the second transistor T2 are respectively connected to the active layer 12 of the second transistor T2 through two second via holes V2.
  • the first pole 331 and the second pole 332 of the third transistor T3 are respectively connected to the active layer 13 of the third transistor T3 through two third via holes V3.
  • the first pole 341 and the second pole 342 of the fourth transistor T4 are respectively connected to the active layer 14 of the fourth transistor T4 through two fourth via holes V4.
  • the first pole 351 and the second pole 352 of the fifth transistor T5 are respectively connected to the active layer 15 of the fifth transistor T5 through two fifth via holes V5.
  • the first pole 361 and the second pole 362 of the sixth transistor T6 are respectively connected to the active layer 16 of the sixth transistor T6 through two sixth via holes V6.
  • the first pole 371 of the seventh transistor T7 (also the second pole 362 of the sixth transistor T6) and the second pole 372 are respectively connected to the active layer 17 of the seventh transistor T7 through two seventh via holes V7.
  • the first pole 381 and the second pole 382 of the eighth transistor T8 are respectively connected to the active layer 18 of the eighth transistor T8 through two eighth via holes V8.
  • the first pole 391 and the second pole 392 of the ninth transistor T9 are respectively connected to the active layer 19 of the ninth transistor T9 through two ninth vias V9.
  • the first pole 3101 and the second pole 3102 of the tenth transistor T10 are respectively connected to the active layer 110 of the tenth transistor T10 through two tenth via holes V9.
  • the first pole 3111 and the second pole 3112 of the eleventh transistor T11 are respectively connected to the active layer 111 of the eleventh transistor T11 through two eleventh via holes V11. .
  • the first pole 3121 and the second pole 3122 of the twelfth transistor T12 are respectively connected to the active layer 112 of the twelfth transistor T12 through two twelfth via holes V12. .
  • the first pole 3131 and the second pole 3132 of the thirteenth transistor T13 are respectively connected to the active layer 113 of the thirteenth transistor T13 through two thirteenth via holes V13.
  • the first pole 3141 and the second pole 3142 of the fourteenth transistor T14 (also the second pole 3132 of the thirteenth transistor T13) are respectively connected to the active layer 114 of the fourteenth transistor T14 through two fourteenth vias V14. .
  • the third transistor T3 The first electrode 331 can be connected to the control electrode 22 of the second transistor T2 through the sixteenth via V16; the orthographic projection of the second electrode 352 of the fifth transistor T5 on the substrate is connected to the control electrode 23 of the third transistor T3 on the substrate. There is an overlapping area in the orthographic projection on the substrate.
  • the second electrode 352 of the fifth transistor T5 can be connected to the control electrode 23 of the third transistor T3 through the seventeenth via hole V17; the second electrode 332 of the third transistor T3 is on the positive side of the substrate. There is an overlapping area between the projection and the orthographic projection of the control electrode 24 of the fourth transistor T4 on the substrate.
  • the second electrode 332 of the third transistor T3 can be connected to the control electrode 24 of the fourth transistor T4 through the eighteenth via hole V18; sixth There is an overlapping area between the orthographic projection of the first electrode 361 of the transistor T6 on the substrate and the orthographic projection of the control electrode 27 of the seventh transistor T7 on the substrate.
  • the first electrode 361 of the sixth transistor T6 can be connected to the first electrode 361 of the sixth transistor T6 through the nineteenth via V19.
  • the control electrode 27 of the seventh transistor T7 is connected; there is an overlapping area between the orthographic projection of the second clock signal line CLKB on the substrate and the orthographic projection of the control electrode 27 of the seventh transistor T7 on the substrate.
  • the second clock signal line CLKB can pass through the third Twenty vias V20 are connected to the control electrode 27 of the seventh transistor T7; there is an overlapping area between the orthographic projection of the fourth connection line CL4 on the substrate and the orthographic projection of the control electrode 211 of the eleventh transistor T11 on the substrate, and the fourth connection Line CL4 can be connected to the control electrode 211 of the eleventh transistor T11 through the twenty-first via V21; the orthographic projection of the second electrode of the eleventh transistor T11 on the substrate is connected to the control electrode 213 of the thirteenth transistor T13. There is an overlapping area in the orthographic projection on the substrate.
  • the second electrode of the eleventh transistor T11 (also the second electrode 3122 of the twelfth transistor T12) can pass through the twenty-second via V22 and the control electrode 213 of the thirteenth transistor T13. Connection; there is an overlapping area between the orthographic projection of the second pole 392 of the ninth transistor T9 on the substrate and the orthographic projection of the control pole 212 of the twelfth transistor T12 on the substrate.
  • the second pole 392 of the ninth transistor T9 can pass through the second
  • the thirteenth via V23 is connected to the control electrode 212 of the twelfth transistor T12; there is an overlapping area between the orthographic projection of the first electrode 391 of the ninth transistor T9 on the substrate and the orthographic projection of the first power line VGH1 on the substrate.
  • the ninth The first pole 391 of the transistor T9 can be connected to the first power line VGH1 on the second conductive layer through the twenty-fourth via V24; the orthographic projection of the first pole 3121 of the twelfth transistor T12 on the substrate is connected to the first power supply line There is an overlapping area in the orthographic projection of line VGH1 on the substrate, and the first electrode 3121 of the twelfth transistor T12 can be connected to the first power line VGH1 on the second conductive layer through the twenty-fifth via V25; the fourteenth transistor T14 There is an overlapping area between the orthographic projection of the first pole 3141 on the substrate and the orthographic projection of the first power line VGH1 on the substrate.
  • the first pole 3141 of the fourteenth transistor T14 can be connected to the second conductive conductor through the twenty-sixth via V26.
  • the first power line VGH1 on the layer is connected; there is an overlapping area between the orthographic projection of the second pole 3142 of the fourteenth transistor T14 on the substrate and the orthographic projection of the second signal output line IEM_OUT on the substrate.
  • the second pole 3142 (also the second pole 3132 of the thirteenth transistor T13) can be connected to the second signal output line IEM_OUT through the twenty-seventh via V27; the orthographic projection of the second pole 382 of the eighth transistor T8 on the substrate is equal to There is an overlapping area in the orthographic projection of the second connection line CL2 on the substrate.
  • the second pole 382 of the eighth transistor T8 can be connected to the second connection line CL2 through the twenty-eighth via V28; the second pole 332 of the third transistor T3 There is an overlapping area between the orthographic projection on the substrate and the orthographic projection of the first plate C21 of the second capacitor C2 on the substrate.
  • the second electrode 332 of the third transistor T3 can communicate with the second capacitor C2 through the twenty-ninth via V29.
  • the first plate C21 is connected; there is an overlapping area between the orthographic projection of the fourth connection line CL4 on the substrate and the orthographic projection of the first plate C31 of the third capacitor C3 on the substrate, and the fourth connection line CL4 can pass through the thirtieth
  • the via V30 is connected to the first plate C31 of the third capacitor C3; the orthographic projection of the second electrode 362 of the sixth transistor T6 on the substrate overlaps with the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate.
  • the second pole 362 of the sixth transistor T6 (also the first pole 371 of the seventh transistor T7) can be connected to the second plate C22 of the second capacitor C2 through the thirty-first via V31; the ninth transistor T9 There is an overlapping area between the orthographic projection of the first electrode 391 on the substrate and the orthographic projection of the second plate C32 of the third capacitor C3 on the substrate.
  • the first electrode 391 of the ninth transistor T9 can be connected to the orthographic projection of the first electrode 391 through the thirty-second via V32.
  • the second plate C32 of the third capacitor C3 is connected; there is an overlapping area between the orthographic projection of the second clock signal line CLKB on the substrate and the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate.
  • the second clock signal line CLKB can be connected to the second plate C12 of the first capacitor C1 through the thirty-third via V33.
  • the second power line VGL in the first direction on one side of The second power line VGL may be located on a side of the fourteenth transistor T14 away from the third capacitor C3.
  • the orthographic projection of the second clock signal line CLKB on the substrate there is an overlapping area between the orthographic projection of the second clock signal line CLKB on the substrate and the orthographic projection of the second plate C12 of the first capacitor C1 and the control electrode 27 of the seventh transistor T7 on the substrate, and
  • the twentieth via V20 is connected to the control electrode 27 of the seventh transistor T7, and the thirty-third via V33 is connected to the second plate C12 of the first capacitor C1.
  • the initial signal line STV, the signal input line IN, the first clock signal line CLK, the second clock signal line CLKB, the third power supply line VGH2, and the second power supply line VGL may be in a strip shape, and extends along the second direction Y.
  • the initial signal line STV, the first clock signal line CLK, the second clock signal line CLKB, the third power line VGH2, and the second power line VGL are arranged in sequence along the first direction X.
  • the signal input line IN may be in an "L" shape, and the signal input line IN may be located on a side of the third power line VGH2 away from the second clock signal line CLKB, and on a side close to the third power line VGH2 One end is connected to the first pole 311 of the first transistor T1, and the other end away from the third power line VGH2 can be connected to the signal output line EM_OUT of the previous row or the initial signal line STV of the first row.
  • the first pole 311 of the first transistor T1 may be a strip-shaped structure extending along the second direction Y.
  • the first pole 311 of the first transistor T1 may be located between the third power line VGH2 and the second pole 312 of the first transistor T1.
  • the second pole 312 of the first transistor T1 may be in an "L" shape, located between the first pole 311 of the first transistor T1 and the second pole 352 of the fifth transistor T5, far away from the first pole 311 of the first transistor T1 One side is connected to the second pole 352 of the fifth transistor T5.
  • the first electrode 321 of the second transistor T2 may have a strip structure and extend along the second direction Y. In the first direction X, it may be located between the second electrode 322 of the second transistor T2 and the Between the first pole 3101 of the tenth transistor T10, the side away from the second pole 322 of the second transistor T2 is connected to the first pole 3101 of the tenth transistor T10.
  • the second electrode 322 of the second transistor T2 may be in the shape of a polygonal line extending along the first direction X.
  • the second electrode 322 of the second transistor T2 may be located between the first electrode 311 of the third transistor T1 and the Between the first poles 321 of the two transistors T2, one end away from the first pole 321 of the second transistor T2 is connected to the second pole 332 of the third transistor T3.
  • the first pole 321 of the second transistor T2 and the second pole 322 of the second transistor T2 may be located between the signal input line IN and the second pole 382 of the eighth transistor T8.
  • the first electrode 331 of the third transistor T3 may have a rectangular structure and is located between the second electrode 352 of the fifth transistor T5 and the second electrode 332 of the third transistor T3.
  • the second pole 332 of the third transistor T3 may be in the shape of a polygonal line extending along the first direction X, may be located between the third power line VGH2 and the third capacitor C3 in the first direction Between a capacitor C1 and a second capacitor C2, one end close to the capacitor C1 is connected to the second electrode 322 of the second transistor T2.
  • the first pole 341 of the fourth transistor T4 may be in an "L" shape and connected to the third power line VGH2, and the second pole 341 of the fourth transistor T4 may be in a square structure and connected to the fifth power line VGH2.
  • the first pole 351 of transistor T5 is connected.
  • the first pole 341 of the fourth transistor T4 and the second pole 341 of the fourth transistor T4 may be located between the signal input line IN and the second pole 332 of the third transistor T3.
  • the first pole 341 of the fourth transistor T4 and the second pole 342 of the fourth transistor T4 may be located between the third power line VGH2 and the second pole 352 of the fifth transistor T5.
  • the first pole 351 of the fifth transistor T5 may be in a "J" shape, and the second pole 352 of the fifth transistor T5 may be in an "L" shape.
  • the fifth transistor T5 In the second direction Y, the fifth transistor T5 The first pole 351 and the second pole 352 of the fifth transistor T5 may be located between the signal input line IN and the second pole 332 of the third transistor T3.
  • the first pole 351 of the fifth transistor T5 And the second pole 352 of the fifth transistor T5 may be located between the third power line VGH2 and the second pole 332 of the third transistor T3.
  • the first pole 361 of the sixth transistor T6 may be in an "L" shape and be located between the third power line VGH2 and the second pole 362 of the sixth transistor T6.
  • the pole 362 may be in a zigzag shape and is located between the second pole 382 of the eighth transistor T8 and the first pole 361 of the sixth transistor T6.
  • the first electrode 371 of the seventh transistor T7 and the second electrode 362 of the sixth transistor T6 share the same electrode, which can save wiring space.
  • the second pole 372 of the seventh transistor T7 may be in an "L" shape, located between the first pole 371 of the seventh transistor T7 and the second pole 382 of the eighth transistor T8, and connected with the second pole 382 of the eighth transistor T8. connect.
  • the first pole 381 of the eighth transistor T8 may have a zigzag shape extending along the first direction X and be located between the second capacitor C2 and the third capacitor C3.
  • the second pole 382 of the eighth transistor T8 may be of "n" type, may be located between the second capacitor C2 and the third capacitor C3 in the first direction X, and may be located away from the third transistor T3 in the second direction Y.
  • One side of a capacitor C1 is provided with an opening on the side away from the first capacitor C1, and the side away from the first capacitor C1 is connected to the second electrode 372 of the seventh transistor T7.
  • the first pole 391 of the ninth transistor T9 may include a first structure 391-1 and a second structure 391-2 connected to each other, and the shape of the first structure 391-1 may be a strip, along The first direction X extends, one end is connected to the first pole 381 of the eighth transistor T8, and the other end is connected to the second structure 391-2.
  • the second structure 391-2 may be in a "J" shape, may be located between the first structure 391-1 and the fourth connection line CL4, and be connected to the first structure 391-1 on a side away from the fourth connection line CL4.
  • the second pole 392 of the ninth transistor T9 may include a third structure 392-1 and a fourth structure 392-2 connected to each other, and the shape of the third structure 392-1 may be a strip, and may be formed along the The first direction
  • the shape of 2 may be a strip, located between the second pole 382 of the eighth transistor T8 and the fourth connection line CL4, and connected to the third structure 392-1 on a side close to the second pole 382 of the eighth transistor T8.
  • the first pole 3101 of the tenth transistor T10 may have a strip structure and extend along the first direction X. In the first direction between the first pole 3111 of the eleventh transistor T11, and both ends are respectively connected to the first pole 321 of the second transistor T2 and the first pole 3111 of the eleventh transistor T11.
  • the second electrode 3102 of the tenth transistor T10 may share an electrode with the second electrode 392 of the ninth transistor T9 to save wiring space.
  • the signal input line IN, the first pole 3101 of the tenth transistor T10 , the second pole 3102 of the tenth transistor T10 , and the first pole 391 of the ninth transistor T9 may be along the The opposite direction of the second direction Y is arranged sequentially.
  • the first pole 3111 of the eleventh transistor T11 may be in a strip shape and extend along the first direction X, with both ends connected to the first pole 3101 of the tenth transistor T10 and the thirteenth transistor The first pole of T13 is connected.
  • the second pole 3112 of the eleventh transistor T11 may be in an "L" shape and located on a side of the first pole 3111 of the eleventh transistor T11 away from the signal input line IN.
  • the first electrode 3121 of the twelfth transistor T12 may be in an "L" shape, located between the fourth connection line CL4 and the second electrode 3142 of the fourteenth transistor T14, and connected with the fourteenth transistor T14.
  • the second pole of T14 is connected at 3142.
  • the second electrode 3122 of the twelfth transistor T12 may share an electrode with the second electrode 3112 of the eleventh transistor T11 to save wiring space.
  • the first electrode 3131 of the thirteenth transistor T13 may have a strip structure and extend along the first direction X, with one end connected to the first electrode 3111 of the eleventh transistor T11 and the other end connected to the second Power cord VGL connection.
  • the second pole 3132 of the thirteenth transistor T13 may include fifth structures 3132-1 and sixth structures 3132-2 connected to each other.
  • the fifth structure 3132-1 may be a strip structure and extends along the first direction X, and is located between the first pole 3131 of the thirteenth transistor T13 and the first pole 3141 of the fourteenth transistor T14.
  • the sixth structure 3132-2 may be in an "L" shape, may be located between the first pole 3141 of the fourteenth transistor T14 and the second power line VGL in the first direction
  • the first pole 3131 of the third transistor T13 is connected to the fifth structure 3132-1 on a side away from the signal input line IN and close to the first pole 3131 of the thirteenth transistor T13.
  • the first pole 3141 of the fourteenth transistor T14 may be in an "L" shape, and may be located between the first pole 3121 of the twelfth transistor T12 and the second power line VGL in the first direction X. time, the side away from the second power line VGL is connected to the first pole 3121 of the twelfth transistor T12.
  • the second electrode 3142 of the fourteenth transistor T14 may share an electrode with the second electrode 3132 of the thirteenth transistor T13 to save wiring space.
  • the fourth connection line CL4 may have a zigzag structure and extend along the second direction Y.
  • the first pole 3111 of the eleventh transistor T11 may be located on the side away from the signal input line IN, and the end close to the first pole 3111 of the eleventh transistor T11 may pass through
  • the twenty-first via V21 is connected to the control electrode 211 of the eleventh transistor T11.
  • the end far away from the first electrode 3111 of the eleventh transistor T11 can pass through the thirtieth via V30 and the first plate of the third capacitor C3. C31 connection.
  • the third conductive film may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo). , or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, etc.
  • a metal material such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo).
  • alloy materials of the above metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, etc.
  • a preparation process of another display substrate may include the following operations.
  • the semiconductor layer pattern may include active layers of the first to fourteenth transistors T1 to T14 .
  • the shapes of the active layers of the first to fourteenth transistors T1 to T14 are respectively the same as the shapes of the active layers of the first to fourteenth transistors T14 in the above (101).
  • the relative positional relationship of the active layers of the transistor T10 is the same as the above (101), and the relative positional relationship of the active layers of the eleventh to fourteenth transistors T11 to T14 is the same as the above (101), which will not be described again here.
  • the difference between the semiconductor layer pattern and the semiconductor layer pattern formed in (101) above is that in the second direction Y, the active layers of the eleventh to fourteenth transistors T11 to T14 are located between the ninth transistor T9 and the tenth transistor T10. On one side, in the first direction X, the active layers of the eleventh transistor T11 and the twelfth transistor T12 are located on one side of the active layers of the thirteenth transistor T13 and the fourteenth transistor T14.
  • the active layers of the thirteenth transistor T13 and the fourteenth transistor T14, the ninth transistor T9 and the tenth transistor T10 are arranged along the second direction Y
  • the active layers of the eleventh transistor T11 and the twelfth transistor T12 , the active layers of the thirteenth transistor T13 and the fourteenth transistor T14 are arranged along the first direction X.
  • the active layer 111 of the eleventh transistor T11 and the active layer 112 of the twelfth transistor T12 are arranged along the second direction Y
  • the active layers 113 and 14th of the thirteenth transistor T13 are arranged along the second direction Y.
  • the active layer 114 of the transistor T14 is arranged along the second direction Y.
  • FIG. 17a is a schematic diagram after forming a first conductive layer pattern
  • FIG. 17b is a planar schematic diagram of the first conductive layer in FIG. 17a
  • the difference between the first conductive layer pattern and the first conductive layer pattern formed in (102) above is that: the control electrodes of the eleventh to fourteenth transistors T11 to T14 are located on the side of the third capacitor C3 away from the first capacitor C1;
  • the shape of the control electrode 211 of the eleventh transistor T11 is "n" type, and is provided with an opening toward the side of the twelfth transistor T12.
  • the side close to the third capacitor C3 is connected to the second connection line CL2 and is away from the third capacitor.
  • the control electrode 211 of the eleventh transistor T11 is connected with the second connection line CL2, the control electrode 29 of the ninth transistor T9, and the control electrode 29 of the ninth transistor T9.
  • the first plate C31 of the three capacitors C3 has an integral structure; the control electrodes of the twelfth transistor T12 and the fourteenth transistor T14 are located between the control electrode of the thirteenth transistor T13 and the third capacitor C3.
  • the first power line VGH1 is in an "L" shape and is located on the side of the third capacitor C3 away from the second capacitor C2. A new power connection line VCL is added.
  • the power connection line VCL is located on the side of the control electrode 23 of the thirteenth transistor T13 away from the control electrode 24 of the fourteenth transistor T14.
  • the power connection line VCL can be of "n" type and has a departure point.
  • the first power signal output line EM_OUT and the second power signal output line IEM_OUT are not provided.
  • FIG. 18a shows a schematic view after the second conductive layer pattern is formed
  • FIG. 18b is a schematic plan view of the second conductive layer in FIG. 18a
  • the difference between the second conductive layer pattern and the second conductive layer pattern formed in (103) above is that the first signal output line EM_OUT and the second signal output line IEM_OUT are provided.
  • the first signal output line EM_OUT can Located between the second plate C12 of the first capacitor C1 and the second plate C32 of the third capacitor C3, the second signal output line IEM_OUT may be located on the second plate C32 of the third capacitor C3 away from the first capacitor C1.
  • the first signal output line EM_OUT and the second signal output line IEM_OUT may be located on the side of the third capacitor C32 away from the second capacitor C2. Both the first signal output line EM_OUT and the second signal output line IEM_OUT may have a polygonal structure extending along the first direction X.
  • FIG. 19 is a schematic diagram of the planar structure after the third insulating layer pattern is formed.
  • the difference between the third insulating layer pattern and the third insulating layer pattern formed in (104) above is that the number of the eighteenth via hole V18 is one, and the twenty-fifth via hole V25 and the twenty-sixth via hole V26 are not provided.
  • the twenty-seventh via hole V27 is arranged to penetrate the third insulating layer, the thirty-fourth via hole V34 to the thirty-sixth via hole V36 are arranged; the thirty-fourth via hole V34 to the thirty-fifth via hole V35 are arranged to penetrate the second insulating layer.
  • the insulating layer and the third insulating layer expose the power connection line VCL, the number of the thirty-fourth via holes V34 is multiple, and the multiple thirty-fourth via holes V34 are arranged in an array; the number of the thirty-fifth via holes V35 There are multiple thirty-fifth via holes V35 arranged in an array; the thirty-sixth via hole V36 penetrates the third insulating layer to expose the first signal output line EM_OUT, and the number of the thirty-sixth via hole V36 can be multiple , the plurality of thirty-sixth via holes V36 may be arranged along the first direction X.
  • Figure 20a is a schematic view after the third conductive layer pattern is formed
  • Figure 20b is a schematic plan view of the third conductive layer in Figure 20a.
  • the difference between the third conductive layer pattern and the third conductive layer pattern formed in (105) above is that the first and second electrodes of the eleventh to fourteenth transistors T11 to T14 are located far away from the ninth transistor T9 and the tenth transistor T10 On one side of Between the second pole 3132 of the three transistors T13, the second pole 3142 of the fourteenth transistor T14 is located between the first pole 3141 of the fourteenth transistor T14 and the first pole 3131 of the thirteenth transistor T13 and the eleventh transistor T11 between the first poles 3111; the first pole 3121 of the twelfth transistor T12 is a strip structure extending along the first direction X, one end is connected to the third power line VGH2, and the other end is connected to the first pole of the fourteenth transistor T14
  • the first electrode 3111 of T11 is a strip structure extending along the first direction
  • One end of the first pole 3131 can be set independently;
  • the first pole 3131 of the thirteenth transistor T13 can include a seventh structure 3131-1 and an eighth structure 3131-2, and the seventh structure 3131-1 can be along the first direction X
  • One end of the extended strip structure is connected to the first pole 311 of the eleventh transistor T11, and the other end is connected to the eighth structure 3131-2.
  • the eighth structure 3131-2 can be a square structure and integrated with the seventh structure 3131-1.
  • the orthographic projection of the eighth structure 3131-2 on the substrate has an overlapping area with the orthographic projection of the power connection line VCL on the substrate, and is connected to the first power line VCL through the thirty-fourth via V34; the thirteenth transistor
  • the second pole 3132 of T13 (also the second pole 3142 of the fourteenth transistor T14) may be a strip structure extending along the first direction X.
  • the first pole 391 of the ninth transistor T9 also includes a ninth structure 392-3.
  • the ninth structure 392-3 may be a strip structure extending along the first direction X, and the fourth structure 392-2 is far away from the second power line VGL.
  • the present disclosure also provides a display device, including a display substrate.
  • the display substrate is the display substrate provided in any of the above embodiments. The implementation principles and implementation effects are similar and will not be described again here.
  • the display device may be a Liquid Crystal Display (LCD for short) or an Organic Light Emitting Diode (OLED for short) display device.
  • the display device can be: a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED for short) panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, and a digital photo frame. , navigator and other products or components with display functions.
  • An embodiment of the present disclosure also provides a method for driving a shift register, which is configured to drive the shift register of any of the above embodiments.
  • the method may include:
  • the first control sub-circuit Under the control of the first clock signal terminal, the second clock signal terminal, the second node and the first power terminal, the first control sub-circuit provides the signal of the signal input terminal to the first node and maintains the potential of the first node;
  • the second control subcircuit Under the control of the first clock signal terminal and the first node, the second control subcircuit provides the signal of the second power terminal or the first clock signal terminal to the second node;
  • the third control subcircuit Under the control of the second clock signal terminal, the first node, and the second node, the third control subcircuit provides the signal of the second clock signal terminal or the first power terminal to the fourth node, and maintains the potential of the fourth node;
  • the first output sub-circuit Under the control of the first node and the fourth node, the first output sub-circuit provides the signal of the first power terminal or the second power terminal to the first signal output terminal;
  • the second output sub-circuit Under the control of the third control sub-circuit and the first signal output terminal, the second output sub-circuit provides the signal of the first power terminal or the second power terminal to the second signal output terminal.
  • Embodiments of the present disclosure provide a shift register and a driving method thereof, a display substrate, and a display device.
  • the shift register includes a first control subcircuit, a second control subcircuit, a third control subcircuit, a first output subcircuit, a second control subcircuit, and a second control subcircuit.
  • Output sub-circuit, the first output sub-circuit can provide the signal of the first power terminal or the second power terminal to the first signal output terminal under the control of the first node and the fourth node; the second output sub-circuit can provide the signal of the first power terminal or the second power terminal under the control of the third control sub-circuit.
  • the signal of the first power terminal or the second power terminal is provided to the second signal output terminal, and the first sub-output circuit and the second sub-output circuit provide the first signal output terminal and the second signal output terminal respectively.
  • the output signal at the output end can meet the needs for different signals, overcoming the problem of being unable to meet the needs for different signals in practical applications.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种移位寄存器及其驱动方法、显示基板、显示装置，移位寄存器包括：第一控制子电路在第一时钟信号端、第二时钟信号端、第二节点和第一电源端的控制下向第一节点提供信号输入端的信号；第二控制子电路在第一时钟信号端和第一节点的控制下向第二节点提供第二电源端或者第一时钟信号端的信号；第三控制子电路在第二时钟信号端、第一节点、第二节点的控制下向第四节点提供第二时钟信号端或者第一电源端的信号并维持第四节点的电位；第一输出子电路在第一节点和第四节点的控制下向第一信号输出端提供第一电源端或者第二电源端的信号；第二输出子电路在第三控制子电路和第一信号输出端的控制下，向第二信号输出端提供第一电源端或者第二电源端的信号。

Description

移位寄存器及其驱动方法、显示基板、显示装置 技术领域
本公开涉及但不限于显示技术领域，尤其涉及一种移位寄存器及其驱动方法、显示基板、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。驱动电路是OLED中一种重要的辅助电路。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开实施例提供了一种移位寄存器，移位寄存器包括第一控制子电路、第二控制子电路、第三控制子电路、第一输出子电路、第二输出子电路；
所述第一控制子电路，分别与信号输入端、第一节点、第二节点、第一时钟信号端、第二时钟信号端和第一电源端连接，设置为在所述第一时钟信号端、所述第二时钟信号端、所述第二节点和所述第一电源端的控制下向所述第一节点提供所述信号输入端的信号，并维持所述第一节点的电位；
所述第二控制子电路，分别与第二电源端、所述第一时钟信号端、所述第一节点和第二节点连接，设置为在所述第一时钟信号端和所述第一节点的控制下，向所述第二节点提供所述第二电源端或者所述第一时钟信号端的信 号；
所述第三控制子电路，分别与所述第一节点、所述第二节点、第四节点、所述第二时钟信号端和所述第一电源端连接，设置为在所述第二时钟信号端、所述第一节点、所述第二节点的控制下，向所述第四节点提供所述第二时钟信号端或者所述第一电源端的信号，并维持所述第四节点的电位；
所述第一输出子电路，分别与所述第一电源端、所述第二电源端、所述第一节点、所述第四节点和第一信号输出端连接，设置为在所述第一节点和所述第四节点的控制下向所述第一信号输出端提供所述第一电源端或者所述第二电源端的信号；
所述第二输出子电路，分别与所述第一信号输出端、所述第三控制子电路、所述第一电源端、所述第二电源端和第二信号输出端连接，设置为在所述第三控制子电路和所述第一信号输出端的控制下，向所述第二信号输出端提供所述第一电源端或者所述第二电源端的信号。
在示例性实施方式中，所述第一控制子电路包括第一晶体管、第四晶体管、第五晶体管和第一电容，所述第一电容包括第一极板和第二极板；
所述第一晶体管的控制极与所述第一时钟信号端连接，所述第一晶体管的第一极与所述信号输入端连接，所述第一晶体管的第二极与所述第一节点连接；
所述第四晶体管的控制极与所述第二节点连接，所述第四晶体管的第一极与所述第一电源端连接，所述第四晶体管的第二极与第七节点连接；
所述第五晶体管的控制极与所述第二时钟信号端连接，所述第五晶体管的第一极与所述第七节点连接，所述第五晶体管的第二极与所述第一节点连接；
所述第一电容的第一极板与所述第一节点连接，所述第一电容的第二极板与所述第二时钟信号端连接。
在示例性实施方式中，所述第一控制子电路包括第一晶体管、第四晶体管、第五晶体管、第一电容和第四电容，所述第一电容包括第一极板和第二极板，所述第四电容包括第一极板和第二极板；
所述第一晶体管的控制极与所述第一时钟信号端连接，所述第一晶体管的第一极与所述信号输入端连接，所述第一晶体管的第二极与所述第一节点连接；
所述第四晶体管的控制极与所述第二节点连接，所述第四晶体管的第一极与所述第一电源端连接，所述第四晶体管的第二极与第七节点连接；
所述第五晶体管的控制极与所述第一节点连接，所述第五晶体管的第一极与所述第二时钟信号端连接，所述第五晶体管的第二极与所述第七节点连接；
所述第一电容的第一极板与所述第一节点连接，所述第一电容的第二极板与所述第一信号输出端连接；
所述第四电容的第一极板与所述第七节点连接，所述第四电容的第二极板与所述第一节点连接。
在示例性实施方式中，所述第二控制子电路包括第二晶体管和第三晶体管；
所述第二晶体管的控制极与所述第一时钟信号端连接，所述第二晶体管的第一极与所述第二电源端连接，所述第二晶体管的第二极与所述第二节点连接；
所述第三晶体管的控制极与所述第一节点连接，所述第三晶体管的第一极与所述第一时钟信号端连接，所述第三晶体管的第二极与所述第二节点连接。
在示例性实施方式中，所述第三控制子电路包括第六晶体管、第七晶体管、第八晶体管、第二电容和第三电容；
所述第六晶体管的控制极与所述第二节点连接，所述第六晶体管的第一极与所述第二时钟信号端连接，所述第六晶体管的第二极与第三节点连接；
所述第七晶体管的控制极与所述第二时钟信号端连接，所述第七晶体管的第一极与所述第三节点连接，所述第七晶体管的第二极与所述第四节点连接；
所述第八晶体管的控制极与所述第一节点连接，所述第八晶体管的第一 极与所述第一电源端连接，所述第八晶体管的第二极与所述第四节点连接；
所述第二电容的第一极板与所述第二节点连接，所述第二电容的第二极板与所述第三节点连接；
所述第三电容的第一极板与所述第四节点连接，所述第三电容的第二极板与所述第一电源端连接。
在示例性实施方式中，所述第一输出子电路包括第九晶体管和第十晶体管；
所述第九晶体管的控制极与所述第四节点连接，所述第九晶体管的第一极与所述第一电源端连接，所述第九晶体管的第二极与所述第一信号输出端连接；
所述第十晶体管的控制极与所述第一节点连接，所述第十晶体管的第一极与所述第二电源端连接，所述第十晶体管的第二极与所述第一信号输出端连接。
在示例性实施方式中，所述第二输出子电路包括第十一晶体管、第十二晶体管、第十三晶体管和第十四晶体管；
所述第十一晶体管的控制极与所述第三控制子电路连接，所述第十一晶体管的第一极与所述第二电源端连接，所述第十一晶体管的第二极与第六节点连接；
所述第十二晶体管的控制极与所述第一信号输出端连接，所述第十二晶体管的第一极与所述第一电源端连接，所述第十二晶体管的第二极与所述第六节点连接；
所述第十三晶体管的控制极与所述第六节点连接，所述第十三晶体管的第一极与所述第二电源端连接，所述第十三晶体管的第二极与所述第二信号输出端连接；
所述第十四晶体管的控制极与所述第一信号输出端连接，所述第十四晶体管的第一极与所述第一电源端连接，所述第十四晶体管的第二极与所述第二信号输出端连接。
在示例性实施方式中，所述第二输出子电路还包括第五电容，所述第五 电容包括第一极板和第二极板；
所述第五电容的第一极板与所述第六节点连接，所述第五电容的第二极板与所述第一时钟信号端或者所述第二时钟信号端连接。
在示例性实施方式中，所述第一控制子电路包括第一晶体管、第四晶体管、第五晶体管和第一电容，所述第一电容包括第一极板和第二极板；所述第二控制子电路包括第二晶体管和第三晶体管；所述第三控制子电路包括第六晶体管、第七晶体管、第八晶体管、第二电容和第三电容；所述第一输出子电路包括第九晶体管和第十晶体管；所述第二输出子电路包括第十一晶体管、第十二晶体管、第十三晶体管和第十四晶体管；
所述第一晶体管的控制极与所述第一时钟信号端连接，所述第一晶体管的第一极与所述信号输入端连接，所述第一晶体管的第二极与所述第一节点连接；
所述第二晶体管的控制极与所述第一时钟信号端连接，所述第二晶体管的第一极与所述第二电源端连接，所述第二晶体管的第二极与所述第二节点连接；
所述第三晶体管的控制极与所述第一节点连接，所述第三晶体管的第一极与所述第一时钟信号端连接，所述第三晶体管的第二极与所述第二节点连接；
所述第四晶体管的控制极与所述第二节点连接，所述第四晶体管的第一极与所述第一电源端连接，所述第四晶体管的第二极与第七节点连接；
所述第五晶体管的控制极与所述第二时钟信号端连接，所述第五晶体管的第一极与所述第七节点连接，所述第五晶体管的第二极与所述第一节点连接；
所述第六晶体管的控制极与所述第二节点连接，所述第六晶体管的第一极与所述第二时钟信号端连接，所述第六晶体管的第二极与第三节点连接；
所述第七晶体管的控制极与所述第二时钟信号端连接，所述第七晶体管的第一极与所述第三节点连接，所述第七晶体管的第二极与所述第四节点连接；
所述第八晶体管的控制极与所述第一节点连接，所述第八晶体管的第一极与所述第一电源端连接，所述第八晶体管的第二极与所述第四节点连接；
所述第九晶体管的控制极与所述第四节点连接，所述第九晶体管的第一极与所述第一电源端连接，所述第九晶体管的第二极与所述第一信号输出端连接；
所述第十晶体管的控制极与所述第一节点连接，所述第十晶体管的第一极与所述第二电源端连接，所述第十晶体管的第二极与所述第一信号输出端连接；
所述第十一晶体管的控制极与所述第三节点或者所述第四节点连接，所述第十一晶体管的第一极与所述第二电源端连接，所述第十一晶体管的第二极与第六节点连接；
所述第十二晶体管的控制极与所述第一信号输出端连接，所述第十二晶体管的第一极与所述第一电源端连接，所述第十二晶体管的第二极与所述第六节点连接；
所述第十三晶体管的控制极与所述第六节点连接，所述第十三晶体管的第一极与所述第二电源端连接，所述第十三晶体管的第二极与所述第二信号输出端连接；
所述第十四晶体管的控制极与所述第一信号输出端连接，所述第十四晶体管的第一极与所述第一电源端连接，所述第十四晶体管的第二极与所述第二信号输出端连接；
所述第一电容的第一极板与所述第一节点连接，所述第一电容的第二极板与所述第二时钟信号端连接；
所述第二电容的第一极板与所述第二节点连接，所述第二电容的第二极板与所述第三节点连接；
所述第三电容的第一极板与所述第四节点连接，所述第三电容的第二极板与所述第一电源端连接。
在示例性实施方式中，所述第一晶体管至第十四晶体管为P型晶体管。
在示例性实施方式中，所述第一信号输出端输出的信号与所述第二信号 输出端输出的信号为互为反相信号。
第二方面，本公开实施例还提供一种显示基板，显示基板包括基底以及设置在所述基底上的电路结构层，所述电路结构层包括发光驱动电路，所述发光驱动电路包括多个级联的移位寄存器；
第i级移位寄存器的第一信号输出端与第i+1级移位寄存器的信号输入端电连接，1≤i≤M-1，M为移位寄存器的总级数；
至少一个移位寄存器包括：第一控制子电路、第二控制子电路、第三控制子电路、第一输出子电路、第二输出子电路；
所述第一控制子电路，分别与信号输入端、第一节点、第二节点、第一时钟信号端、第二时钟信号端和第一电源端连接，设置为在所述第一时钟信号端、所述第二时钟信号端、所述第二节点和所述第一电源端的控制下向所述第一节点提供所述信号输入端的信号，并维持所述第一节点的电位；
所述第二控制子电路，分别与第二电源端、所述第一时钟信号端、所述第一节点和第二节点连接，设置为在所述第一时钟信号端和所述第一节点的控制下，向所述第二节点提供所述第二电源端或者所述第一时钟信号端的信号；
所述第三控制子电路，分别与所述第一节点、所述第二节点、第四节点、所述第二时钟信号端和所述第一电源端连接，设置为在所述第二时钟信号端、所述第一节点、所述第二节点的控制下，向所述第四节点提供所述第二时钟信号端或者所述第一电源端的信号，并维持所述第四节点的电位；
所述第一输出子电路，分别与所述第一电源端、所述第二电源端、所述第一节点、所述第四节点和第一信号输出端连接，设置为在所述第一节点和所述第四节点的控制下向所述第一信号输出端提供所述第一电源端或者所述第二电源端的信号；
所述第二输出子电路，分别与所述第一信号输出端、所述第三控制子电路、所述第一电源端、所述第二电源端和第二信号输出端连接，设置为在所述第三控制子电路和所述第一信号输出端的控制下，向所述第二信号输出端提供所述第一电源端或者所述第二电源端的信号。
在示例性实施方式中，显示基板还包括：沿第二方向延伸的初始信号线、第一时钟信号线、第二时钟信号线、第二电源线和第三电源线，初始信号线、第一时钟信号线、第二时钟信号线、第三电源线和第二电源线沿第一方向排布，所述第一方向与所述第二方向相交；
第一级移位寄存器的信号输入端与初始信号线电连接，所有移位寄存器的第一电源端与第三电源线电连接，所有移位寄存器的第二电源端与第二电源线电连接，奇数级移位寄存器的第一时钟信号端与第一时钟信号线连接，奇数级移位寄存器的第二时钟信号端与第二时钟信号线连接，偶数级移位寄存器的第一时钟信号端与第二时钟信号线连接，偶数级移位寄存器的第二时钟信号端与第一时钟信号线连接。
在示例性实施方式中，所述电路结构层包括：依次叠设在基底上的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层和第三导电层；
所述半导体层包括：位于发光驱动电路的所有晶体管的有源层；
所述第一导电层包括：位于发光驱动电路的所有晶体管的控制极以及第一电容的第一极板至第三电容的第一极板；
所述第二导电层包括：位于发光驱动电路的第一电容的第二极板至第三电容的第二极板；
所述第三导电层包括：初始信号线、第一时钟信号线、第二时钟信号线、第一电源线、第二电源线。
在示例性实施方式中，所述第三导电层还包括位于发光驱动电路的所有晶体管的第一极和第二极。
在示例性实施方式中，所述移位寄存器包括：第一晶体管至第十四晶体管；
在所述显示基板所在平面内，在第一方向上，所有晶体管以及电容均位于第三电源线与第二电源线之间，第二电容位于第三电源线与第八晶体管之间，第八晶体管位于第二电容与第九晶体管和第十晶体管之间，第九晶体管和第十晶体管位于第八晶体管与第十一晶体管和第十二晶体管之间，所述第 十一晶体管和所述第十二晶体管位于所述第九晶体管和所述第十晶体管与所述第十三晶体管和第十四晶体管之间，第十三晶体管和第十四晶体管位于第十一晶体管和第十二晶体管与第二电源线之间；在第二方向上，第三电容、第九晶体管、第十晶体管、第一电容沿第二方向依次排布，第十二晶体管、第十一晶体管沿第二方向依次排布，第十四晶体管、第十三晶体管沿第二方向依次排布。
在示例性实施方式中，所述第一导电层还包括第一电源线；所述第一电源线为折线状，所述第一电源线与所述第一电源端连接，并沿第一方向延伸；
在平行于所述显示基板的平面上，在第一方向上，所述第一电源线位于第三电容远离第八晶体管的控制极的一侧；在第二方向上，所述第一电源线位于第十四晶体管的控制极远离第十三晶体管的控制极的一侧。
在示例性实施方式中，所述第一电源线在基底上的正投影分别与第九晶体管的第一极、第十二晶体管的第一极、第十四晶体管的第一极在基底上的正投影至少部分交叠；
所述第三导电层中第八晶体管的第一极和第九晶体管的第一极为一体成型结构。
在示例性实施方式中，所述第一导电层还包括第一信号输出线和第二信号输出线；所述第一信号输出线的形状为条状并沿第一方向延伸，所述第二信号输出线的形状呈“L”型；
在所述第一导电层所在平面内，在第二方向上，所述第一信号输出线位于第十三晶体管的控制极与所述第一电源线之间，第一信号输出线与第十四晶体管的控制极为一体成型结构，第二信号输出线位于所述第一电源线远离所述第一信号输出线的一侧；在第一方向上，所述第一信号输出线位于第十四晶体管的控制极远离第十二晶体管的控制极的一侧，第二信号输出线位于第三电容的第一极板远离第八晶体管的控制极的一侧。
在示例性实施方式中，所述第一导电层还包括第二连接线，所述第二连接线、所述第三电容的第一极板、所述第九晶体管的控制极为一体成型结构，所述第十一晶体管的控制极形状呈“L”型；
所述第三导电层还包括第四连接线、第一晶体管至第十四晶体管的第一极和第二极，所述第四连接线的形状为折线状，并沿第二方向延伸，所述第四连接线在所述基底上的正投影分别与所述第十一晶体管的控制极和所述第三电容的第一极板在所述基底上的正投影至少部分重叠；
所述第九晶体管的第二极包括相互连接的第三结构和第四结构，所述第三结构的形状为条状，并沿第一方向延伸，位于所述第八晶体管的第二极与所述第四连接线之间，在靠近所述第四连接线的一端与所述第四结构连接；所述第四结构的形状为条状，并沿第二方向延伸，靠近所述第三结构的一端与第三结构连接。
在示例性实施方式中，所述第十三晶体管的第二极包括相互连接的第五结构和第六结构，所述第五结构的形状为条状，并沿第一方向延伸，位于第十三晶体管的第一极与第十四晶体管的第一极之间；所述第六结构呈“L”型，在第一方向上位于第十四晶体管的第一极与第二电源线之间，在第二方向上靠近第十三晶体管的第一极的一侧与所述第五结构连接，所述第六结构在基底上的正投影与所述第二信号输出线在基底上的正投影至少部分重叠；
所述第十二晶体管的第一极和所述第十四晶体管的第一极均呈“L”型，位于所述第四连接线远离第三电源线的一侧。
在示例性实施方式中，所述移位寄存器包括：第一晶体管至第十四晶体管；
在所述显示基板所在平面内，在第一方向上，所有晶体管以及电容均位于第三电源线与第二电源线之间，第二电容位于第三电源线与第八晶体管之间，第八晶体管位于第二电容与第九晶体管和第十晶体管之间，第九晶体管和第十晶体管位于第八晶体管与第二电源线之间，第十一晶体管和第十二晶体管位于第三电源线与第十三晶体管和第十四晶体管之间，第十三晶体管和第十四晶体管位于第十一晶体管和第十二晶体管与第二电源线之间；在第二方向上，第十三晶体管、第十四晶体管、第三电容、第九晶体管、第十晶体管、第一电容沿第二方向依次排布。
在示例性实施方式中，所述第一导电层还包括第一电源线，所述第一电 源线与所述第一电源端连接；所述第一电源线呈“L”型；
在所述第一导电层所在平面内，在第一方向上，所述第一电源线位于第三电容的第一极板远离第二电容的第一极板的一侧；在第二方向上，所述第一电源线位于第十四晶体管的控制极与第一电容的第一极板之间。
在示例性实施方式中，所述第一电源线在基底上的正投影与第九晶体管的第一极在基底上的正投影至少部分交叠；
所述第三导电层中第八晶体管的第一极和第九晶体管的第一极为一体成型结构。
在示例性实施方式中，所述第一导电层还包括电源连接线，所述第二导电层还包括第一信号输出线、第二信号输出线；所述第一信号输出线和所述第二信号输出线的形状均为沿第一方向延伸的折线状；
在所述第二导电层所在平面内，在第二方向上，所述第一信号输出线位于第一电容的第二极板与第三电容的第二极板之间，第二信号输出线位于所述第三电容的第二极板远离第一电容的第二极板的一侧；在第一方向上，所述第一信号输出线和所述第二信号输出线均位于第三电容的第二极板远离第二电容的第二极板的一侧；
所述电源连接线为“n”型，在第二方向上，位于第十三晶体管的控制极远离第十四晶体管的控制极的一侧，并设有背离第十三晶体管一侧的开口，所述电源连接线在基底上的正投影分别与所述第二电源线和所述第十三晶体管的第一极在基底上的正投影至少部分重叠。
在示例性实施方式中，所述第一导电层还包括第二连接线，所述第二连接线与所述第三电容的第一极板、所述第九晶体管的控制极、所述第十一晶体管的控制极一体成型，所述第十一晶体管的控制极形状呈“n”型，并设有朝向第十二晶体管一侧的开口；
所述第三导电层还包括第一晶体管至第十四晶体管的第一极和第二极，所述第九晶体管的第二极包括相互连接的第三结构、第四结构和第九结构，所述第三结构的形状为条状，并沿第一方向延伸，位于所述第八晶体管的第二极与所述第二电源线之间，在靠近所述第二电源线的一端与所述第四结构 连接；所述第四结构的形状为条状，位于第二电源线靠近第三电源线的一侧，并沿第二方向延伸，靠近所述第三结构的一端与第三结构连接；所述第九结构的形状为条状，位于第四结构远离第二电源线的一侧，所述第四结构在基底上的正投影与所述第四晶体管的控制极在基底上的正投影至少部分重叠。
在示例性实施方式中，所述第十三晶体管的第二极为条状结构，并沿第一方向延伸，第十三晶体管的第一极包括相互连接的第七结构和第八结构，所述第七结构的形状为条状，并沿第一方向延伸，一端与第十一晶体管的第一极连接，另一端与第八结构连接；所述第八结构为方形结构，与第七结构一体成型，所述第八结构在基底上的正投影与所述电源连接线在基底上的正投影至少部分重叠；
所述第十二晶体管和所述第十四晶体管的第一极为沿第一方向延伸且相互连接的条状结构，第十二晶体管的第一极一端与第三电源线连接，另一端与第十四晶体管的第一极连接，第十四晶体管的第一极位于第十二晶体管的第一极远离第三电源线的一侧，所述第十二晶体管的第一极与所述第十四晶体管的第一极、所述第三电源线为一体成型结构。
在示例性实施方式中，所述第三导电层还包括信号输入线，所述信号输入线为折线状，并沿第一方向延伸，在所述第三导电层所在平面内，在第一方向上，所述信号输入线位于第三电源线与所述第二电源线之间；在第二方向上，所述信号输入线位于第十晶体管远离第九晶体管的一侧；
在所述第二导电层所在平面内，所述第二电容的第二极板、所述第三电容的第一极板沿第一方向排布，在第二方向上，所述第二电容的第二极板和所述第三电容的第二极板位于第一电容的第二极板的同一侧；
所述第一电容的第二极板的形状为折线状，并沿第一方向延伸，第一电容的第二极板在基底上的正投影与第一电容的第一极板在基底上的正投影存在重叠区域；第二电容的第二极板的形状为方形，第二电容的第二极板在基底上的正投影与第二电容的第一极板在基底上的正投影存在重叠区域；所述第三电容的第二极板的形状可以为条状，并沿第一方向延伸，第三电容的第二极板在基底上的正投影与第三电容的第一极板在基底上的正投影存在重叠区域。
在示例性实施方式中，所述信号输入线与所述第一晶体管的第一极为一体成型结构。
在示例性实施方式中，所述第九晶体管、所述第十晶体管、所述第十三晶体管和所述第十四晶体管中的任意一个晶体管包括四个相互并联的子晶体管，并且在任意一个晶体管中，四个子晶体管的有源层相互独立设置，四个子晶体管的控制极为一体成型结构，四个子晶体管的第一极为一体成型结构，四个子晶体管的第二极为一体成型结构。
在示例性实施方式中，在所述显示基板所在平面内，在第一方向上，所述第一晶体管、所述第四晶体管至所述第七晶体管位于所述第三电源线与所述第二电容之间，所述第二晶体管和所述第三晶体管位于所述第五晶体管与所述第一电容之间。
在示例性实施方式中，所述第三导电层包括第一晶体管至第十四晶体管的第一极和第二极，所述第六晶体管的第二极和所述第七晶体管的第一极共用一个电极，所述第九晶体管的第二极和所述第十晶体管的第二极共用一个电极，所述第十三晶体管第二极和所述第十四晶体管的第二极共用一个电极。
在示例性实施方式中，所述第一电源线和所述第二电源线提供相同的电源信号。
第三方面，本公开实施例还提供一种显示装置，包括上述任一实施例所述的显示基板。
第四方面，本公开实施例还提供一种移位寄存器的驱动方法，设置为驱动上述任一实施例所述的移位寄存器，所述方法包括：
在第一时钟信号端、第二时钟信号端、第二节点和第一电源端的控制下，第一控制子电路向第一节点提供信号输入端的信号，并维持第一节点的电位；
在第一时钟信号端和第一节点的控制下，第二控制子电路向第二节点提供第二电源端或者第一时钟信号端的信号；
在第二时钟信号端、第一节点、第二节点的控制下，第三控制子电路向第四节点提供第二时钟信号端或者第一电源端的信号，并维持第四节点的电位；
在第一节点和第四节点的控制下，第一输出子电路向第一信号输出端提供第一电源端或者第二电源端的信号；
在第三控制子电路和第一信号输出端的控制下，第二输出子电路向第二信号输出端提供第一电源端或者第二电源端的信号。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中每个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1所示为一种显示装置的结构示意图；
图2所示为一种显示基板的平面结构示意图；
图3所示为一种显示基板的剖面结构示意图；
图4所示为一种像素驱动电路的等效电路示意图；
图5所示为一种像素驱动电路的工作时序图；
图6所示为本公开实施例提供的移位寄存器的结构示意图；
图7所示为本公开示例性实施例提供的移位寄存器的等效电路图；
图8所示为本公开示一种示例性实施例提供的移位寄存器的工作时序图；
图9a所示为本公开示例性实施例提供的一种移位寄存器的等效电路图；
图9b所示为本公开示例性实施例提供的一种移位寄存器的等效电路图；
图9c所示为本公开示例性实施例提供的一种移位寄存器的等效电路图；
图10a所示为一种像素驱动电路的等效电路图；
图10b所示为一种像素驱动电路的工作时序图；
图11所示为本公开示例性实施例提供的显示基板形成有源层图案后的示意图；
图12a所示为本公开示例性实施例提供的显示基板形成第一导电层图案后的示意图；
图12b所示为本公开示例性实施例提供的显示基板中第一导电层的示意图；
图13a所示为本公开示例性实施例提供的显示基板形成第二导电层图案后的示意图；
图13b所示为本公开示例性实施例提供的显示基板中第二导电层的示意图；
图14所示为本公开示例性实施例提供的显示基板形成第三绝缘层图案后的示意图；
图15a所示为本公开示例性实施例提供的显示基板形成第三导电层图案后的示意图；
图15b所示为本公开示例性实施例提供的显示基板中第三导电层的示意图；
图16所示为本公开示例性实施例提供的显示基板形成有源层图案后的示意图；
图17a所示为本公开示例性实施例提供的显示基板形成第一导电层图案后的示意图；
图17b所示为本公开示例性实施例提供的显示基板中第一导电层的示意图；
图18a所示为本公开示例性实施例提供的显示基板形成第二导电层图案后的示意图；
图18b所示为本公开示例性实施例提供的显示基板中第二导电层的示意图；
图19所示为本公开显示基板形成第三绝缘层图案后的示意图；
图20a所示为本公开示例性实施例提供的显示基板形成第三导电层图案后的示意图；
图20b所示为本公开示例性实施例提供的显示基板中第三导电层的示意图；
图21所示为本公开示例性实施例提供的显示基板中多个移位寄存器的级联关系示意图。
具体实施方式
下文中将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：每个膜层的厚度和间距、每个信号线的宽度和间距，可以根据实际情况进行调整。本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述每个构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接； 可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。在本公开实施例中，栅电极可以称为控制极。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开实施例中的“约”，是指不严格限定界限，允许工艺和测量误差范 围内的数值。
图1所示为一种显示装置的结构示意图，显示基板可以包括时序控制器、数据信号驱动器、扫描信号驱动器、发光信号驱动器和像素阵列，时序控制器分别与数据信号驱动器、扫描信号驱动器和发光信号驱动器连接，数据信号驱动器分别与多个数据信号线(D1到Dn)连接，扫描信号驱动器分别与多个扫描信号线(S1到Sm)连接，发光信号驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括至少一个扫描信号线、至少一个数据信号线、至少一个发光信号线和像素驱动电路。在示例性实施方式中，时序控制器可以将适合于数据信号驱动器的规格的灰度值和控制信号提供到数据信号驱动器，可以将适合于扫描信号驱动器的规格的时钟信号、扫描起始信号等提供到扫描信号驱动器，可以将适合于发光信号驱动器的规格的时钟信号、发射停止信号等提供到发光信号驱动器。数据信号驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据信号驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描信号驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描信号驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光信号驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光信号驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
图2为一种显示基板的平面结构示意图。如图2所示，显示基板可以包括以矩阵方式排布的多个像素单元P，多个像素单元P至少一个包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3，第一子像素P1、第二子像素P2和第三子像素P3均包括像素驱动电路和发光器件。第一子像素P1、第二子像素P2和第三子像素P3中的像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向所述发光器件输出相应的电流。第一子像素P1、第二子像素P2和第三子像素P3中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，像素单元P中可以包括红色(R)子像素、绿色(G)子像素和蓝色(B)子像素。在示例性实施方式中，像素单元中子像素的形状可以是矩形状、菱形、五边形或六边形，三个子像素可以采用水平并列、竖直并列或品字方式排列，本公开在此不做限定。
图3为一种显示基板的剖面结构示意图，示意了OLED显示基板三个子像素的结构。如图3所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底101一侧的发光结构层103以及设置在发光结构层103远离基底101一侧的封装层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层102可以包括构成像素驱动电路的多个晶体管和存储电容。发光结构层103可以包括阳极301、像素定义层302、有机发光层303和阴极304，阳极301通过过孔与驱动晶体管210的漏电极连接，有机发光层303与阳极301连接，阴极304与有机发光层303连接，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料， 第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，有机发光层303可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，所有子像素的电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，相邻子像素的电子阻挡层可以有少量的交叠，或者可以是隔离的。
在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C结构。图4为一种像素驱动电路的等效电路示意图。如图4所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)和1个存储电容C，像素驱动电路可以与7个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2和第三节点N3。其中，第一节点N1分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第二节点N2分别与第一晶体管T1的第二极、第二晶体管T2的第一极、第三晶体管T3的控制极和存储电容C的第二端连接，第三节点N3分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接。
在示例性实施方式中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的控制极连接。
第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的 第一极与初始信号线INIT连接，第一晶体管的第二极与第二节点N2连接。当导通电平扫描信号施加到第二扫描信号线S2时，第一晶体管T1将初始化电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的控制极与第二极连接。
第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的量。
第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据信号线D的数据电压输入到像素驱动电路。
第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管T7的控制极与第一扫描信号线S1连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与发光器件的第一极连接。当导通电平扫描信号施加到第一扫描信号线S1时，第七晶体管T7将初始化电压传输到发光器件的第一极，以使发光器件的第一极中累积的电 荷量初始化或释放发光器件的第一极中累积的电荷量。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。第一扫描信号线S1为本显示行像素驱动电路中的扫描信号线，第二扫描信号线S2为上一显示行像素驱动电路中的扫描信号线，即对于第n显示行，第一扫描信号线S1为S(n)，第二扫描信号线S2为S(n-1)，本显示行的第二扫描信号线S2与上一显示行像素驱动电路中的第一扫描信号线S1为同一信号线，可以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一扫描信号线S1、第二扫描信号线S2、发光信号线E和初始信号线INIT沿水平方向延伸，第二电源线VSS、第一电源线VDD和数据信号线D沿竖直方向延伸。
在示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
图5为一种像素驱动电路的工作时序图。下面通过图4示例的像素驱动电路的工作过程说明一种示例性实施例，图4中的像素驱动电路包括7个晶体管(第一晶体管T1到第七晶体管T7)、1个存储电容C和7个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)，7个晶体管均为P型晶体管。
在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1和发光信号线E的信号为高电平信号。第二扫描信号线 S2的信号为低电平信号，使第一晶体管T1导通，初始信号线INIT的信号提供至第二节点N2，对存储电容C进行初始化，清除存储电容中原有数据电压。第一扫描信号线S1和发光信号线E的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线E的信号为高电平信号，数据信号线D输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使得初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第二扫描信号线S2的信号为高电平信号，使第一晶体管T1断开。发光信号线E的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线E的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd)] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
发光信号驱动器通常采用发光阵列基板行驱动(Emitting Gate Driver on Array，EM GOA)电路，常用的EM GOA电路通常情况下输出一种发光信号(EM)，随着OLED显示技术的发展，对OLED显示产品的驱动电路产生的驱动信号的要求也随之提高，常用的EM GOA电路不能输出不同类型的发光信号，无法满足实际应用中对于不同发光信号的需求。
本公开示例性实施例提供了一种移位寄存器，如图6所示，移位寄存器包括第一控制子电路、第二控制子电路、第三控制子电路、第一输出子电路、第二输出子电路；
第一控制子电路，分别与信号输入端IN、第一节点N1、第二节点N2、第一时钟信号端CLK、第二时钟信号端CLKB和第一电源端VGH连接，设置为在第一时钟信号端CLK、第二时钟信号端CLKB、第二节点N2和第一电源端VGH的控制下向第一节点N1提供信号输入端IN的信号，并维持第一节点N1的电位；
第二控制子电路，分别与第二电源端VGL、第一时钟信号端CLK、第一节点N1和第二节点N2连接，设置为在第一时钟信号端CLK和第一节点N1的控制下，向第二节点N2提供第二电源端VGL或者第一时钟信号端CLK的信号；
第三控制子电路，分别与第一节点N1、第二节点N2、第四节点N4、第二时钟信号端CLKB和第一电源端VGH连接，设置为在第二时钟信号端CLKB、第一节点N1、第二节点N2的控制下，向第四节点N4提供第二时钟信号端CLKB或者第一电源端VGH的信号，并维持第四节点N4的电位；
第一输出子电路，分别与第一电源端VGH、第二电源端VGL、第一节点N1、第四节点N4和第一信号输出端EM_OUT连接，设置为在第一节点N1和第四节点N4的控制下向第一信号输出端EM_OUT提供第一电源端VGH或者第二电源端VGL的信号；
第二输出子电路，分别与第一信号输出端EM_OUT、第三控制子电路、第一电源端VGH、第二电源端VGL和第二信号输出端IEM_OUT连接，设置为在第三控制子电路和第一信号输出端EM_OUT的控制下，向第二信号输出端IEM_OUT提供第一电源端VGH或者第二电源端VGL的信号。
本公开实施例提供的移位寄存器，包括第一控制子电路、第二控制子电路、第三控制子电路、第一输出子电路、第二输出子电路，第一输出子电路可以在第一节点和第四节点的控制下向第一信号输出端提供第一电源端或者第二电源端的信号，第二输出子电路可以在第三控制子电路和第一信号输出端的控制下向第二信号输出端提供第一电源端或者第二电源端的信号，由第一子输出电路和第二子输出电路分别向第一信号输出端和第二信号输出端输出信号，可以满足对于不同信号的需求，克服了无法满足实际应用中对不同信号需求的问题。
在示例性实施方式中，所述第一信号输出端EM_OUT输出的信号与所述第二信号输出端IEM_OUT输出的信号为互为反相信号。本公开实施例提供的移位寄存器，第一信号输出端EM_OUT和第二信号输出端IEM_OUT输出的信号为互为反相信号，在实现控制信号输出端输出脉冲信号宽度的基础上，可以满足实际应用中对不同类型信号的需求。在本公开实施例中，同一个移位寄存器电路中同步提供脉冲信号宽度可调的不同类型的信号，例如，移位寄存器可以为发光阵列基板行驱动(Emitting Gate Driver on Array，EM GOA)电路，同一个EM GOA电路可以输出不同类型的发光信号，以满足实际应用中对于不同发光信号的需求。
在本公开实施例中，同一个EM GOA电路可以提供脉宽可调的发光信号(EM信号)以及与EM信号互为反相的发光信号IEM信号，在很大程度上提高了电路的集成度。
在示例性实施方式中，如图7、图9a-图9b所示，第一控制子电路可以包括第一晶体管T1、第四晶体管T4、第五晶体管T5和第一电容C1，第一电容C1包括第一极板C11和第二极板C12；
第一晶体管T1的控制极与第一时钟信号端CLK连接，第一晶体管T1的第一极与信号输入端IN连接，第一晶体管T1的第二极与第一节点N1连 接；
第四晶体管T4的控制极与第二节点N2连接，第四晶体管T4的第一极与第一电源端VGH连接，第四晶体管T4的第二极与第七节点N7连接；
第五晶体管T5的控制极与第二时钟信号端CLKB连接，第五晶体管T5的第一极与第七节点N7连接，第五晶体管T5的第二极与第一节点N1连接；
第一电容C1的第一极板C11与第一节点N1连接，第一电容C1的第二极板C12与第二时钟信号端CLKB连接。
在示例性实施方式中，如图9c所示，第一控制子电路可以包括第一晶体管T1、第四晶体管T4、第五晶体管T5、第一电容C1和第四电容C4，第一电容C1可以包括第一极板C11和第二极板C12，第四电容C4可以包括第一极板C41和第二极板C42；
第一晶体管T1的控制极与第一时钟信号端CLK连接，第一晶体管T1的第一极与信号输入端IN连接，第一晶体管T1的第二极与第一节点N1连接；
第四晶体管T4的控制极与第二节点N2连接，第四晶体管T4的第一极与第一电源端VGH连接，第四晶体管T4的第二极与第七节点N7连接；
第五晶体管T5的控制极与第一节点N1连接，第五晶体管T5的第一极与第二时钟信号端CLKB连接，第五晶体管T5的第二极与第七节点N7连接；
第一电容C1的第一极板C11与第一节点N1连接，第一电容C1的第二极板C12与第一信号输出端EM_OUT连接；
第四电容C4的第一极板C41与第七节点N7连接，第四电容C4的第二极板C42与第一节点N1连接。
在示例性实施方式中，如图7、图9a-图9c所示，第二控制子电路可以包括第二晶体管T2和第三晶体管T3；
第二晶体管T2的控制极与第一时钟信号端CLK连接，第二晶体管T2的第一极与第二电源端VGL连接，第二晶体管T2的第二极与第二节点N2连接；
第三晶体管T3的控制极与第一节点N1连接，第三晶体管T3的第一极 与第一时钟信号端CLK连接，第三晶体管T3的第二极与第二节点N2连接。
在示例性实施方式中，如图7、图9a-图9c所示，第三控制子电路可以包括第六晶体管T6、第七晶体管T7、第八晶体管T8、第二电容C2和第三电容C3；
第六晶体管T6的控制极与第二节点N2连接，第六晶体管T6的第一极与第二时钟信号端CLKB连接，第六晶体管T6的第二极与第三节点N3连接；
第七晶体管T7的控制极与第二时钟信号端CLKB连接，第七晶体管T7的第一极与第三节点N3连接，第七晶体管T7的第二极与第四节点N4连接；
第八晶体管T8的控制极与第一节点N1连接，第八晶体管T8的第一极与第一电源端VGH连接，第八晶体管T8的第二极与第四节点N4连接；
第二电容C2的第一极板C21与第二节点N2连接，第二电容C2的第二极板C22与第三节点N3连接；
第三电容C3的第一极板C31与第四节点N4连接，第三电容C3的第二极板C32与第一电源端VGH连接。
在示例性实施方式中，如图7、图9a-图9c所示，第一输出子电路可以包括第九晶体管T9和第十晶体管T10；
第九晶体管T9的控制极与第四节点N4连接，第九晶体管T9的第一极与第一电源端VGH连接，第九晶体管T9的第二极与第一信号输出端EM_OUT连接；
第十晶体管T10的控制极与第一节点N1连接，第十晶体管T10的第一极与第二电源端VGL连接，第十晶体管T10的第二极与第一信号输出端EM_OUT连接。
在示例性实施方式中，如图7、图9a所示，第二输出子电路可以包括第十一晶体管T11、第十二晶体管T12、第十三晶体管T13和第十四晶体管T14；
第十一晶体管T11的控制极与第三控制子电路连接，第十一晶体管T11的第一极与第二电源端VGL连接，第十一晶体管T11的第二极与第六节点N6连接；例如，第十一晶体管T11的控制极可以与第三节点N3(图7所示)或第四节点N4连接(图9a所示)；
第十二晶体管T12的控制极与第一信号输出端EM_OUT连接，第十二晶体管T12的第一极与第一电源端VGH连接，第十二晶体管T12的第二极与第六节点N6连接；
第十三晶体管T13的控制极与第六节点N6连接，第十三晶体管T13的第一极与第二电源端VGL连接，第十三晶体管T13的第二极与第二信号输出端IEM_OUT连接；
第十四晶体管T14的控制极与第一信号输出端EM_OUT连接，第十四晶体管T14的第一极与第一电源端VGH连接，第十四晶体管T14的第二极与第二信号输出端IEM_OUT连接。
在示例性实施方式中，如图9b和图9c所示，第二输出子电路还可以包括第五电容C5，第五电容C5包括第一极板C51和第二极板C52；
第五电容C5的第一极板C51与第六节点N6连接，第五电容C5的第二极板C52与第一时钟信号端CLK或者第二时钟信号端CLKB连接。
在示例性实施方式中，如图7和图9a所示，第一控制子电路可以包括第一晶体管T1、第四晶体管T4、第五晶体管T5和第一电容C1，第一电容C1包括第一极板C11和第二极板C12；第二控制子电路可以包括第二晶体管T2和第三晶体管T3；第三控制子电路可以包括第六晶体管T6、第七晶体管T7、第八晶体管T8、第二电容C2和第三电容C3；第一输出子电路可以包括第九晶体管T9和第十晶体管T10；第二输出子电路可以包括第十一晶体管T11、第十二晶体管T12、第十三晶体管T13和第十四晶体管T14；
第一晶体管T1的控制极与第一时钟信号端CLK连接，第一晶体管T1的第一极与信号输入端IN连接，第一晶体管T1的第二极与第一节点N1连接；
第二晶体管T2的控制极与第一时钟信号端CLK连接，第二晶体管T2的第一极与第二电源端VGL连接，第二晶体管T2的第二极与第二节点N2连接；
第三晶体管T3的控制极与第一节点N1连接，第三晶体管T3的第一极与第一时钟信号端CLK连接，第三晶体管T3的第二极与第二节点N2连接；
第四晶体管T4的控制极与第二节点N2连接，第四晶体管T4的第一极与第一电源端VGH连接，第四晶体管T4的第二极与第七节点N7连接；
第五晶体管T5的控制极与第二时钟信号端CLKB连接，第五晶体管T5的第一极与第七节点N7连接，第五晶体管T5的第二极与第一节点N1连接；
第六晶体管T6的控制极与第二节点N2连接，第六晶体管T6的第一极与第二时钟信号端CLKB连接，第六晶体管T6的第二极与第三节点N3连接；
第七晶体管T7的控制极与第二时钟信号端CLKB连接，第七晶体管T7的第一极与第三节点N3连接，第七晶体管T7的第二极与第四节点N4连接；
第八晶体管T8的控制极与第一节点N1连接，第八晶体管T8的第一极与第一电源端VGH连接，第八晶体管T8的第二极与第四节点N4连接；
第九晶体管T9的控制极与第四节点N4连接，第九晶体管T9的第一极与第一电源端VGH连接，第九晶体管T9的第二极与第一信号输出端EM_OUT连接；
第十晶体管T10的控制极与第一节点N1连接，第十晶体管T10的第一极与第二电源端VGL连接，第十晶体管T10的第二极与第一信号输出端EM_OUT连接；
第十一晶体管T11的控制极与第三节点N3或者第四节点N4连接，第十一晶体管T11的第一极与第二电源端VGL连接，第十一晶体管T11的第二极与第六节点N6连接；
第十二晶体管T12的控制极与第一信号输出端EM_OUT连接，第十二晶体管T12的第一极与第一电源端VGH连接，第十二晶体管T12的第二极与第六节点N6连接；
第十三晶体管T13的控制极与第六节点N6连接，第十三晶体管T13的第一极与第二电源端VGL连接，第十三晶体管T13的第二极与第二信号输出端IEM_OUT连接；
第十四晶体管T14的控制极与第一信号输出端EM_OUT连接，第十四晶体管T14的第一极与第一电源端VGH连接，第十四晶体管T14的第二极与第二信号输出端IEM_OUT连接；
第一电容C1的第一极板C11与第一节点N1连接，第一电容C1的第二极板C12与第二时钟信号端CLKB连接；
第二电容C2的第一极板C21与第二节点N2连接，第二电容C2的第二极板C22与第三节点N3连接；
第三电容C3的第一极板C31与第四节点N4连接，第三电容C3的第二极板C32与第一电源端VGH连接。
在示例性实施方式中，第一晶体管T1至第十四晶体管T14为P型晶体管。
下面通过移位寄存器的工作过程说明一种示例性实施例提供的移位寄存器。
如图7所示为一种示例性实施例提供的移位寄存器的等效电路图，图8为一种示例性实施例提供的移位寄存器的工作时序图，如图7和图8所示，一种示例性实施例涉及的移位寄存器包括：14个开关晶体管(T1至T14)，3个电容单元(C1、C2和C3)，3个信号输入端(CLK、CLKB和IN)、2个信号输出端(EM_OUT和IEM_OUT)、2个电源端(VGH和VGL)。其中图7所示第一晶体管T1至第十四晶体管T14可以均为P型晶体管。
在示例性实施方式中，第一电源端VGH的信号为高电平信号，第二电源端VGL的信号为低电平信号。
在示例性实施方式中，第一信号输出端EM_OUT输出的信号和第二信号输出端IEM_OUT输出的信号均为脉宽可调的信号，且互为反相信号，即两者周期相同，电压相反，并且可以根据信号输入IN输入的信号调整脉宽。
在示例性实施方式中，信号输入端IN为有效电平信号的持续时间可以是第一时钟信号端CLK的时钟信号的周期的一倍或多倍。例如，信号输入端IN为有效电平信号的持续时间可以是第一时钟信号端CLK的时钟信号的周期的3倍。
如图7和8所示，一种示例性实施例提供的移位寄存器的工作过程可以包括：第一阶段P1至第五阶段P5。
第一阶段P1：信号输入端IN和第二时钟信号端CLKB的信号为高电平 信号，第一时钟信号端CLK的信号为低电平信号。第一时钟信号端CLK的低电平信号使第一晶体管T1、第二晶体管T2导通，信号输入端IN输入的高电平信号经由第一晶体管T1写入第一节点N1，第一节点N1为高电平，第三晶体管T3、第八晶体管T8、第十晶体管T10断开，第二电源端VGL的信号无法经由第十晶体管T10写入第五节点N5，第五节点N5维持上一帧的低电平，第一信号输出端EM_OUT输出低电平信号；由于第二晶体管T2导通，第二电源端VGL的低电平信号经由第二晶体管T2写入第二节点N2，第二节点N2为低电平，第四晶体管T4、第六晶体管T6导通，第一电源端VGH的信号经由第四晶体管T4写入第七节点N7，第七节点N7为高电平，第二时钟信号端CLKB的高电平信号使第五晶体管T5断开，第七节点N7的信号无法经由第五晶体管T5写入第一节点N1，第二时钟信号端CLKB的高电平信号经由第六晶体管T6写入第三节点N3，第三节点N3为高电平，第十一晶体管T11断开，由于第二时钟信号端CLKB的信号为高电平信号，第七晶体管T7断开，第三节点N3的高电平信号无法经由第七晶体管T7写入第四节点N4，第四节点N4维持上一帧的高电平，第九晶体管T9断开，第一电源端VGH的信号无法经由第九晶体管T9写入第五节点N5；由于第五节点N5为低电平，第十二晶体管T12、第十四晶体管T14导通，第一电源端VGH的信号经由第十四晶体管T14传输至第二信号输出端IEM_OUT，第二信号输出端IEM_OUT输出高电平信号，第一电源端VGH的信号经由第十二晶体管T12写入第六节点N6，第六节点N6为高电平，第十三晶体管T13断开，第二电源端VGL的信号无法经由第十三晶体管T13输出至第二信号输出端IEM_OUT。在该阶段第一信号输出端EM_OUT输出低电平信号，第二信号输出端IEM_OUT输出高电平信号。
第二阶段P2：信号输入端IN和第一时钟信号端CLK的信号为高电平信号，第二时钟信号端CLKB的信号为低电平信号。第一时钟信号端CLK的高电平信号使第一晶体管T1、第二晶体管T2断开，信号输入端IN输入的高电平信号无法经由第一晶体管T1写入第一节点N1；由于第二晶体管T2断开，第二电源端VGL的低电平信号无法经由第二晶体管T2写入第二节点N2，第二节点N2维持上一帧的低电平，第四晶体管T4、第六晶体管T6导通，由于第二时钟信号端CLKB的信号为低电平信号，第五晶体管T5导通， 第一电源端VGH的信号经由第四晶体管T4、第五晶体管T5写入第一节点N1，第一节点N1为高电平，第三晶体管T3、第八晶体管T8、第十晶体管T10断开，第二电源端VGL的信号无法经由第十晶体管T10写入第五节点N5，由于第六晶体管T6导通，第二时钟信号端CLKB的低电平信号经由第六晶体管T6写入第三节点N3，第三节点N3为低电平，第二时钟信号端CLKB的低电平信号使第七晶体管T7导通，第三节点N3的低电平信号经由第七晶体管T7写入第四节点N4，第四节点N4为低电平，第九晶体管T9导通，第一电源端VGH的信号经由第九晶体管T9写入第五节点N5，第五节点N5为高电平，第一信号输出端EM_OUT输出高电平信号；由于第五节点N5为高电平，第十二晶体管T12、第十四晶体管T14断开，第一电源端VGH的信号无法经由第十四晶体管T14传输至第二信号输出端IEM_OUT，第一电源端VGH的信号无法经由第十二晶体管T12写入第六节点N6。由于第三节点N3为低电平，第十一晶体管T11导通，第二电源端VGL的低电平信号经由第十一晶体管T11写入第六节点N6，第六节点N6为低电平，第十三晶体管T13导通，第二电源端VGL的信号经由第十三晶体管T13传输至第二信号输出端IEM_OUT，第二信号输出端IEM_OUT输出低电平信号。在该阶段第一信号输出端EM_OUT输出高电平信号，第二信号输出端IEM_OUT输出低电平信号。
第三阶段P3：信号输入端IN和第二时钟信号端CLKB的信号为高电平信号，第一时钟信号端CLK的信号为低电平信号。第一时钟信号端CLK的低电平信号使第一晶体管T1、第二晶体管T2导通，信号输入端IN输入的高电平信号经由第一晶体管T1写入第一节点N1，第一节点N1为高电平，第三晶体管T3、第八晶体管T8、第十晶体管T10断开，第二电源端VGL的信号无法经由第十晶体管T10写入第五节点N5；由于第二晶体管T2导通，第二电源端VGL的低电平信号经由第二晶体管T2写入第二节点N2，第二节点N2为低电平，第四晶体管T4、第六晶体管T6导通，第一电源端VGH的信号经由第四晶体管T4写入第七节点N7，第七节点N7为高电平，第二时钟信号端CLKB的高电平信号使第五晶体管T5断开，第七节点N7的信号无法经由第五晶体管T5写入第一节点N1，第二时钟信号端CLKB的高电平信号经由第六晶体管T6写入第三节点N3，第三节点N3为高电平，第十一 晶体管T11断开，由于第二时钟信号端CLKB的信号为高电平信号，第七晶体管T7断开，第三节点N3的高电平信号无法经由第七晶体管T7写入第四节点N4，第四节点N4维持上一帧的低电平，第九晶体管T9导通，第一电源端VGH的信号经由第九晶体管T9写入第五节点N5，第五节点N5为高电平，第一信号输出端EM_OUT输出高电平信号；由于第五节点N5为高电平，第十二晶体管T12、第十四晶体管T14断开，第一电源端VGH的信号无法经由第十四晶体管T14传输至第二信号输出端IEM_OUT，第一电源端VGH的信号无法经由第十二晶体管T12写入第六节点N6，第六节点N6维持上一帧的低电平，第十三晶体管T13导通，第二电源端VGL的信号经由第十三晶体管T13传输至第二信号输出端IEM_OUT，第二信号输出端IEM_OUT输出低电平信号。在该阶段第一信号输出端EM_OUT输出高电平信号，第二信号输出端IEM_OUT输出低电平信号。
第四阶段P4：第一时钟信号端CLK的信号为高电平信号，信号输入端IN和第二时钟信号端CLKB的信号为低电平信号。第一时钟信号端CLK的高电平信号使第一晶体管T1、第二晶体管T2断开，信号输入端IN输入的低电平信号无法经由第一晶体管T1写入第一节点N1；由于第二晶体管T2断开，第二电源端VGL的低电平信号无法经由第二晶体管T2写入第二节点N2，第二节点N2维持上一帧的低电平，第四晶体管T4、第六晶体管T6导通，由于第二时钟信号端CLKB的信号为低电平信号，第五晶体管T5导通，第一电源端VGH的信号经由第四晶体管T4、第五晶体管T5写入第一节点N1，第一节点N1为高电平，第三晶体管T3、第八晶体管T8、第十晶体管T10断开，第二电源端VGL的信号无法经由第十晶体管T10写入第五节点N5，第二时钟信号端CLKB的低电平信号经由第六晶体管T6写入第三节点N3，第三节点N3为低电平，第十一晶体管T11导通，第二时钟信号端CLKB的低电平信号使第七晶体管T7导通，第三节点N3的低电平信号经由第七晶体管T7写入第四节点N4，第四节点N4为低电平，第九晶体管T9导通，第一电源端VGH的信号经由第九晶体管T9写入第五节点N5，第五节点N5为高电平，第一信号输出端EM_OUT输出高电平信号；由于第五节点N5为高电平，第十二晶体管T12、第十四晶体管T14断开，第一电源端VGH的信号无法经由第十四晶体管T14传输至第二信号输出端IEM_OUT，第一电 源端VGH的信号无法经由第十二晶体管T12写入第六节点N6。由于第十一晶体管T11导通，第二电源端VGL的低电平信号经由第十一晶体管T11写入第六节点N6，第六节点N6为低电平，第十三晶体管T13导通，第二电源端VGL的信号经由第十三晶体管T13传输至第二信号输出端IEM_OUT，第二信号输出端IEM_OUT输出低电平信号。在该阶段第一信号输出端EM_OUT输出高电平信号，第二信号输出端IEM_OUT输出低电平信号。
第五阶段P5：第二时钟信号端CLKB的信号为高电平信号，信号输入端IN和第一时钟信号端CLK的信号为低电平信号。第一时钟信号端CLK的低电平信号使第一晶体管T1、第二晶体管T2导通，信号输入端IN输入的低电平信号写入第一节点N1，第一节点N1为低电平，第三晶体管T3、第八晶体管T8、第十晶体管T10导通，第二电源端VGL的信号经由第十晶体管T10写入第五节点N5，第五节点N5为低电平，第一信号输出端EM_OUT输出低电平信号；由于第二晶体管T2导通，第二电源端VGL的低电平信号经由第二晶体管T2写入第二节点N2，第二节点N2为低电平，第四晶体管T4、第六晶体管T6导通，第一电源端VGH的信号经由第四晶体管T4写入第七节点N7，第七节点N7为高电平，第二时钟信号端CLKB的高电平信号使第五晶体管T5断开，第七节点N7的信号无法经由第五晶体管T5写入第一节点N1，第二时钟信号端CLKB的高电平信号经由第六晶体管T6写入第三节点N3，第三节点N3为高电平，第十一晶体管T11断开，由于第二时钟信号端CLKB的信号为高电平信号，第七晶体管T7断开，第三节点N3的高电平信号无法经由第七晶体管T7写入第四节点N4，由于第八晶体管T8导通，第一电源端VGH的信号经由第八晶体管T8写入第四节点N4，第四节点N4为高电平，第九晶体管T9断开，第一电源端VGH的信号无法经由第九晶体管T9写入第五节点N5；由于第五节点N5为低电平，第十二晶体管T12、第十四晶体管T14导通，第一电源端VGH的信号经由第十四晶体管T14传输至第二信号输出端IEM_OUT，第二信号输出端IEM_OUT输出高电平信号，第一电源端VGH的信号经由第十二晶体管T12写入第六节点N6，第六节点N6为高电平，第十三晶体管T13断开。在该阶段第一信号输出端EM_OUT输出低电平信号，第二信号输出端IEM_OUT输出高电平信号。
第六阶段P6：在该阶段，信号输入端IN的输入信号保持低电平信号不变，第一时钟信号端CLK和第二时钟信号端CLKB的信号周期性变化，第一信号输出端EM_OUT和第二信号输出端IEM_OUT输出的信号保持不变，即第一信号输出端EM_OUT输出低电平信号，第二信号输出端IEM_OUT输出高电平信号。下面以第一子阶段P61、第二子阶段P62为例进行说明:
第一子阶段P61：第一时钟信号端CLK的信号为高电平信号，第二时钟信号端CLKB的信号为低电平信号。第一时钟信号端CLK的高电平信号使第一晶体管T1和第二晶体管T2断开，信号输入端IN输入的低电平信号无法经由第一晶体管T1写入第一节点N1，第二电源端VGL的低电平信号无法经由第二晶体管T2写入第二节点N2，第一节点N1维持上一帧的低电平，第三晶体管T3、第八晶体管T8、第十晶体管T10导通，第一时钟信号端CLK的高电平信号经由第三晶体管T3写入第二节点N2，第二节点N2为高电平，第四晶体管T4和第六晶体管T6断开，第二时钟信号端CLKB的低电平无法经由第六晶体管T6写入第三节点N3，第三节点N3维持上一帧的高电平，第一电源端VGH的高电平信号经由第八晶体管T8写入第四节点N4，第九晶体管T9断开，第一电源端VGH的高电平信号无法经由第九晶体管T9写入第五节点N5，由于第十晶体管T10导通，第二电源端VGL的低电平信号经由第十晶体管T10写入第五节点N5，第五节点N5为低电平，第一信号输出端EM_OUT输出低电平信号；由于第三节点N3维持上一帧的高电平，第十一晶体管T11断开，第二电源端VGL的低电平信号无法经由第十一晶体管T11写入第六节点N6，由于第五节点N5为低电平，第十二晶体管T12和第十四晶体管T14导通，第一电源端VGH的高电平信号经由第十二晶体管T12写入第六节点N6，第十三晶体管T13断开，第二电源端VGL的低电平无法经由第十三晶体管T13传输至第二信号输出端IEM_OUT，第一电源端VGH的高电平信号经由第十四晶体管T14传输至第二信号输出端IEM_OUT，第二信号输出端IEM_OUT输出的信号为高电平信号。
第二子阶段P62：第一时钟信号端CLK的信号为低电平信号，第二时钟信号端CLKB的信号为高电平信号。第一时钟信号端CLK的低电平信号使第一晶体管T1和第二晶体管T2导通，信号输入端IN输入的低电平信号经 由第一晶体管T1写入第一节点N1，第二电源端VGL的低电平信号经由第二晶体管T2写入第二节点N2，第一节点N1和第二节点N2均为低电平，第三晶体管T3、第八晶体管T8、第十晶体管T10、第四晶体管T4、第六晶体管T6均导通，第二时钟信号端CLKB的高电平经由第六晶体管T6写入第三节点N3，第三节点N3为高电平，第一电源端VGH的高电平信号经由第八晶体管T8写入第四节点N4，第九晶体管T9断开，第一电源端VGH的高电平信号无法经由第九晶体管T9写入第五节点N5，由于第十晶体管T10导通，第二电源端VGL的低电平信号经由第十晶体管T10写入第五节点N5，第五节点N5为低电平，第一信号输出端EM_OUT输出的信号为低电平信号；由于第三节点N3为高电平，第十一晶体管T11断开，第二电源端VGL的低电平信号无法经由第十一晶体管T11写入第六节点N6，由于第五节点N5为低电平，第十二晶体管T12和第十四晶体管T14导通，第一电源端VGH的高电平信号经由第十二晶体管T12写入第六节点N6，第十三晶体管T13断开，第二电源端VGL的低电平无法经由第十三晶体管T13传输至第二信号输出端IEM_OUT，第一电源端VGH的高电平信号经由第十四晶体管T14传输至第二信号输出端IEM_OUT，第二信号输出端IEM_OUT输出的信号为高电平信号。
在示例性实施方式中，图9a所示的移位寄存器的等效电路图的移位寄存器的工作时序图与图8相同。图9a所示的移位寄存器的工作过程可以包括第一阶段H1至第六阶段H6，第一阶段H1至第六阶段H6的信号输入端IN、第一时钟信号端CLK、第二时钟信号端CLKB、第一信号输出端EM_OUT和第二信号输出端IEM_OUT的信号与图8中第一阶段P1至第六阶段P6相同。下面详细说明图9a所示的移位寄存器中多个晶体管和多个电容在第一阶段H1至第六阶段H6的工作过程：
第一阶段H1：信号输入端IN和第二时钟信号端CLKB的信号为高电平信号，第一时钟信号端CLK的信号为低电平信号。第一时钟信号端CLK的低电平信号使第一晶体管T1、第二晶体管T2导通，信号输入端IN输入的高电平信号经由第一晶体管T1写入第一节点N1，第一节点N1为高电平，第三晶体管T3、第八晶体管T8、第十晶体管T10断开，第二电源端VGL的 信号无法经由第十晶体管T10写入第五节点N5，第五节点N5维持上一帧的低电平，第一信号输出端EM_OUT输出低电平信号；由于第二晶体管T2导通，第二电源端VGL的低电平信号经由第二晶体管T2写入第二节点N2，第二节点N2为低电平，第四晶体管T4、第六晶体管T6导通，第一电源端VGH的信号经由第四晶体管T4写入第七节点N7，第七节点N7为高电平，第二时钟信号端CLKB的高电平信号使第五晶体管T5断开，第七节点N7的信号无法经由第五晶体管T5写入第一节点N1，第二时钟信号端CLKB的高电平信号经由第六晶体管T6写入第三节点N3，第三节点N3为高电平，由于第二时钟信号端CLKB的信号为高电平信号，第七晶体管T7断开，第三节点N3的高电平信号无法经由第七晶体管T7写入第四节点N4，第四节点N4维持上一帧的高电平，第九晶体管T9、第十一晶体管T11断开，第一电源端VGH的信号无法经由第九晶体管T9写入第五节点N5，第二电源端VGL的低电平信号无法经由第十一晶体管T11写入第六节点N6；由于第五节点N5为低电平，第一信号输出端EM_OUT输出低电平信号，第十二晶体管T12、第十四晶体管T14导通，第一电源端VGH的信号经由第十四晶体管T14传输至第二信号输出端IEM_OUT，第二信号输出端IEM_OUT输出高电平信号，第一电源端VGH的信号经由第十二晶体管T12写入第六节点N6，第六节点N6为高电平，第十三晶体管T13断开，第二电源端VGL的信号无法经由第十三晶体管T13输出至第二信号输出端IEM_OUT。在该阶段第一信号输出端EM_OUT输出低电平信号，第二信号输出端IEM_OUT输出高电平信号。
第二阶段H2：信号输入端IN和第一时钟信号端CLK的信号为高电平信号，第二时钟信号端CLKB的信号为低电平信号。第一时钟信号端CLK的高电平信号使第一晶体管T1、第二晶体管T2断开，信号输入端IN输入的高电平信号无法经由第一晶体管T1写入第一节点N1；由于第二晶体管T2断开，第二电源端VGL的低电平信号无法经由第二晶体管T2写入第二节点N2，第二节点N2维持上一帧的低电平，第四晶体管T4、第六晶体管T6导通，由于第二时钟信号端CLKB的信号为低电平信号，第五晶体管T5导通，第一电源端VGH的信号经由第四晶体管T4、第五晶体管T5写入第一节点N1，第一节点N1为高电平，第三晶体管T3、第八晶体管T8、第十晶体管 T10断开，第二电源端VGL的信号无法经由第十晶体管T10写入第五节点N5，由于第六晶体管T6导通，第二时钟信号端CLKB的低电平信号经由第六晶体管T6写入第三节点N3，第三节点N3为低电平，第二时钟信号端CLKB的低电平信号使第七晶体管T7导通，第三节点N3的低电平信号经由第七晶体管T7写入第四节点N4，第四节点N4为低电平，第九晶体管T9、第十一晶体管T11导通，第一电源端VGH的信号经由第九晶体管T9写入第五节点N5，第五节点N5为高电平，第一信号输出端EM_OUT输出高电平信号；由于第五节点N5为高电平，第十二晶体管T12、第十四晶体管T14断开，第一电源端VGH的信号无法经由第十四晶体管T14传输至第二信号输出端IEM_OUT，第一电源端VGH的信号无法经由第十二晶体管T12写入第六节点N6；由于第十一晶体管T11导通，第二电源端VGL的低电平信号经由第十一晶体管T11写入第六节点N6，第六节点N6为低电平，第十三晶体管T13导通，第二电源端VGL的信号经由第十三晶体管T13传输至第二信号输出端IEM_OUT，第二信号输出端IEM_OUT输出低电平信号。在该阶段第一信号输出端EM_OUT输出高电平信号，第二信号输出端IEM_OUT输出低电平信号。
第三阶段H3：信号输入端IN和第二时钟信号端CLKB的信号为高电平信号，第一时钟信号端CLK的信号为低电平信号。第一时钟信号端CLK的低电平信号使第一晶体管T1、第二晶体管T2导通，信号输入端IN输入的高电平信号经由第一晶体管T1写入第一节点N1，第一节点N1为高电平，第三晶体管T3、第八晶体管T8、第十晶体管T10断开，第二电源端VGL的信号无法经由第十晶体管T10写入第五节点N5；由于第二晶体管T2导通，第二电源端VGL的低电平信号经由第二晶体管T2写入第二节点N2，第二节点N2为低电平，第四晶体管T4、第六晶体管T6导通，第一电源端VGH的信号经由第四晶体管T4写入第七节点N7，第七节点N7为高电平，第二时钟信号端CLKB的高电平信号使第五晶体管T5断开，第七节点N7的信号无法经由第五晶体管T5写入第一节点N1，第二时钟信号端CLKB的高电平信号经由第六晶体管T6写入第三节点N3，第三节点N3为高电平，由于第二时钟信号端CLKB的信号为高电平信号，第七晶体管T7断开，第三节点N3的高电平信号无法经由第七晶体管T7写入第四节点N4，第四节点N4维 持上一帧的低电平，第九晶体管T9、第十一晶体管T11导通，第一电源端VGH的信号经由第九晶体管T9写入第五节点N5，第五节点N5为高电平，第一信号输出端EM_OUT输出高电平信号；由于第五节点N5为高电平，第十二晶体管T12、第十四晶体管T14断开，第一电源端VGH的信号无法经由第十四晶体管T14传输至第二信号输出端IEM_OUT，第一电源端VGH的信号无法经由第十二晶体管T12写入第六节点N6，由于第十一晶体管T11导通，第二电源端VGL的低电平信号经由第十一晶体管T11写入第六节点N6，第六节点N6为低电平，第十三晶体管T13导通，第二电源端VGL的信号经由第十三晶体管T13传输至第二信号输出端IEM_OUT，第二信号输出端IEM_OUT输出低电平信号。在该阶段第一信号输出端EM_OUT输出高电平信号，第二信号输出端IEM_OUT输出低电平信号。
第四阶段H4：第一时钟信号端CLK的信号为高电平信号，信号输入端IN和第二时钟信号端CLKB的信号为低电平信号。第一时钟信号端CLK的高电平信号使第一晶体管T1、第二晶体管T2断开，信号输入端IN输入的高电平信号无法经由第一晶体管T1写入第一节点N1，第三晶体管T3、第八晶体管T8、第十晶体管T10断开，第二电源端VGL的信号无法经由第十晶体管T10写入第五节点N5；由于第二晶体管T2断开，第二电源端VGL的低电平信号无法经由第二晶体管T2写入第二节点N2，第二节点N2维持上一帧的低电平，第四晶体管T4、第六晶体管T6导通，由于第二时钟信号端CLKB的信号为低电平信号，第五晶体管T5和第七晶体管T7导通，第一电源端VGH的信号经由第四晶体管T4、第五晶体管T5写入第一节点N1，第一节点N1维持高电平，由于第六晶体管T6导通，第二时钟信号端CLKB的低电平信号经由第六晶体管T6写入第三节点N3，第三节点N3为低电平，由于第七晶体管T7导通，第三节点N3的低电平信号经由第七晶体管T7写入第四节点N4，第四节点N4为低电平，第十一晶体管T11、第九晶体管T9导通，第一电源端VGH的信号经由第九晶体管T9写入第五节点N5，第五节点N5为高电平，第一信号输出端EM_OUT输出高电平信号；由于第五节点N5为高电平，第十二晶体管T12、第十四晶体管T14断开，第一电源端VGH的信号无法经由第十四晶体管T14传输至第二信号输出端IEM_OUT，第一电源端VGH的信号无法经由第十二晶体管T12写入第六节点N6。由于 第十一晶体管T11导通，第二电源端VGL的低电平信号经由第十一晶体管T11写入第六节点N6，第六节点N6为低电平，第十三晶体管T13导通，第二电源端VGL的信号经由第十三晶体管T13传输至第二信号输出端IEM_OUT，第二信号输出端IEM_OUT输出低电平信号。在该阶段第一信号输出端EM_OUT输出高电平信号，第二信号输出端IEM_OUT输出低电平信号。
第五阶段H5：第二时钟信号端CLKB的信号为高电平信号，信号输入端IN和第一时钟信号端CLK的信号为低电平信号。第一时钟信号端CLK的低电平信号使第一晶体管T1、第二晶体管T2导通，信号输入端IN输入的低电平信号写入第一节点N1，第一节点N1为低电平，第三晶体管T3、第八晶体管T8、第十晶体管T10导通，第二电源端VGL的信号经由第十晶体管T10写入第五节点N5，第五节点N5为低电平，第一信号输出端EM_OUT输出低电平信号；由于第二晶体管T2导通，第二电源端VGL的低电平信号经由第二晶体管T2写入第二节点N2，第二节点N2为低电平，第四晶体管T4、第六晶体管T6导通，第一电源端VGH的信号经由第四晶体管T4写入第七节点N7，第七节点N7为高电平，第二时钟信号端CLKB的高电平信号使第五晶体管T5断开，第七节点N7的信号无法经由第五晶体管T5写入第一节点N1，第二时钟信号端CLKB的高电平信号经由第六晶体管T6写入第三节点N3，第三节点N3为高电平，由于第二时钟信号端CLKB的信号为高电平信号，第七晶体管T7断开，第三节点N3的高电平信号无法经由第七晶体管T7写入第四节点N4，由于第八晶体管T8导通，第一电源端VGH的信号经由第八晶体管T8写入第四节点N4，第四节点N4为高电平，第九晶体管T9、第十一晶体管T11断开，第一电源端VGH的信号无法经由第九晶体管T9写入第五节点N5；由于第五节点N5为低电平，第十二晶体管T12、第十四晶体管T14导通，第一电源端VGH的信号经由第十四晶体管T14传输至第二信号输出端IEM_OUT，第二信号输出端IEM_OUT输出高电平信号，第一电源端VGH的信号经由第十二晶体管T12写入第六节点N6，第六节点N6为高电平，第十三晶体管T13断开，第二电源端VGL的信号无法经由第十三晶体管T13传输至第二信号输出端IEM_OUT。在该阶段第一信号输出端EM_OUT输出低电平信号，第二信号输出端IEM_OUT输出高电平信 号。
第六阶段H6：在该阶段，信号输入端IN的输入信号保持低电平信号不变，第一时钟信号端CLK和第二时钟信号端CLKB的信号周期性变化，第一信号输出端EM_OUT和第二信号输出端IEM_OUT输出的信号保持不变，即第一信号输出端EM_OUT输出低电平信号，第二信号输出端IEM_OUT输出高电平信号。下面以第一子阶段H61、第二子阶段H62为例进行说明:
第一子阶段H61：第一时钟信号端CLK的信号为高电平信号，第二时钟信号端CLKB的信号为低电平信号。第一时钟信号端CLK的高电平信号使第一晶体管T1和第二晶体管T2断开，信号输入端IN输入的低电平信号无法经由第一晶体管T1写入第一节点N1，第二电源端VGL的低电平信号无法经由第二晶体管T2写入第二节点N2，第一节点N1维持上一帧的低电平，第三晶体管T3、第八晶体管T8、第十晶体管T10导通，第一时钟信号端CLK的高电平信号经由第三晶体管T3写入第二节点N2，第二节点N2为高电平，第四晶体管T4和第六晶体管T6断开，第二时钟信号端CLKB的低电平无法经由第六晶体管T6写入第三节点N3，第三节点N3维持上一帧的高电平，第一电源端VGH的高电平信号经由第八晶体管T8写入第四节点N4，第四节点N4为高电平，第九晶体管T9、第十一晶体管T11断开，第一电源端VGH的高电平信号无法经由第九晶体管T9写入第五节点N5，由于第十晶体管T10导通，第二电源端VGL的低电平信号经由第十晶体管T10写入第五节点N5，第五节点N5为低电平，第一信号输出端EM_OUT输出低电平信号；由于第十一晶体管T11断开，第二电源端VGL的低电平信号无法经由第十一晶体管T11写入第六节点N6，由于第五节点N5为低电平，第十二晶体管T12和第十四晶体管T14导通，第一电源端VGH的高电平信号经由第十四晶体管T14传输至第二信号输出端IEM_OUT，第二信号输出端IEM_OUT输出的信号为高电平信号，第一电源端VGH的高电平信号经由第十二晶体管T12写入第六节点N6，第六节点N6为高电平，第十三晶体管T13断开，第二电源端VGL的低电平信号无法经由第十三晶体管T13传输至第二信号输出端IEM_OUT。
第二子阶段H62：第一时钟信号端CLK的信号为低电平信号，第二时钟 信号端CLKB的信号为高电平信号。第一时钟信号端CLK的低电平信号使第一晶体管T1和第二晶体管T2导通，信号输入端IN输入的低电平信号经由第一晶体管T1写入第一节点N1，第二电源端VGL的低电平信号经由第二晶体管T2写入第二节点N2，第一节点N1和第二节点N2均为低电平，第三晶体管T3、第八晶体管T8、第十晶体管T10、第四晶体管T4、第六晶体管T6导通，第二时钟信号端CLKB的高电平经由第六晶体管T6写入第三节点N3，第三节点N3为高电平，第一电源端VGH的高电平信号经由第八晶体管T8写入第四节点N4，第九晶体管T9、第十一晶体管T11断开，第一电源端VGH的高电平信号无法经由第九晶体管T9写入第五节点N5，由于第十晶体管T10导通，第二电源端VGL的低电平信号经由第十晶体管T10写入第五节点N5，第五节点N5为低电平，第一信号输出端EM_OUT输出的信号为低电平信号；由于第十一晶体管T11断开，第二电源端VGL的低电平信号无法经由第十一晶体管T11写入第六节点N6，由于第五节点N5为低电平，第十二晶体管T12、第十四晶体管T14导通，第一电源端VGH的高电平信号经由第十四晶体管T14传输至第二信号输出端IEM_OUT，第二信号输出端IEM_OUT输出的信号为高电平信号，第一电源端VGH的高电平信号经由第十二晶体管T12写入第六节点N6，第六节点N6为高电平，第十三晶体管T13断开，第二电源端VGL的低电平信号无法经由第十三晶体管T13传输至第二信号输出端IEM_OUT。
在示例性实施方式中，图9b所示的移位寄存器的等效电路图的移位寄存器的工作时序图与图8相同。在图9b所示电路图中，在图7所示电路图的基础上增加第五电容，第十一晶体管T11的控制极与第三节点N3或者第四节点N4连接，第五电容C5的第一极板C51与第六节点N6连接，第五电容C5的第二极板C52与第一时钟信号端CLK或者第二时钟信号端CLKB连接。图9b中第十一晶体管T11与第三节点N3连接的情况下，多个晶体管工作过程与上述第一阶段P1至第六阶段P6相同，第十一晶体管T11与第四节点N4连接的情况下，多个晶体管工作过程与上述第一阶段H1至第六阶段H6相同。
在示例性实施方式中，图9c所示的移位寄存器的等效电路图的移位寄存 器的工作时序图与图8相同，图9c在图9b的基础上增加了第四电容C4。图9c所示的移位寄存器的工作过程可以包括第一阶段M1至第六阶段M6，第一阶段M1至第六阶段M6的信号输入端IN、第一时钟信号端CLK、第二时钟信号端CLKB和信号输出端OUT的信号与图8中第一阶段P1至第六阶段P6相同。下面详细说明图9c所示的移位寄存器中在第十一晶体管T11与第四节点N4连接、第五电容C5的第二极板C52与第一时钟信号端CLK连接的情况下，多个晶体管和多个电容在第一阶段M1至第六阶段M6的工作过程：
第一阶段M1：信号输入端IN和第二时钟信号端CLKB的信号为高电平信号，第一时钟信号端CLK的信号为低电平信号。第一时钟信号端CLK的低电平信号使第一晶体管T1、第二晶体管T2导通，信号输入端IN输入的高电平信号经由第一晶体管T1写入第一节点N1，第一节点N1为高电平，第三晶体管T3、第五晶体管T5、第八晶体管T8、第十晶体管T10断开，第二电源端VGL的信号无法经由第十晶体管T10写入第五节点N5，第五节点N5维持上一帧的低电平，第一信号输出端EM_OUT输出低电平信号；由于第二晶体管T2导通，第二电源端VGL的低电平信号经由第二晶体管T2写入第二节点N2，第二节点N2为低电平，第四晶体管T4、第六晶体管T6导通，第一电源端VGH的信号经由第四晶体管T4写入第七节点N7，第七节点N7为高电平，第一节点N1的高电平使第五晶体管T5断开，第二时钟信号端CLKB的信号无法经由第五晶体管T5写入第七节点N7，第二时钟信号端CLKB的高电平信号经由第六晶体管T6写入第三节点N3，第三节点N3为高电平，由于第二时钟信号端CLKB的信号为高电平信号，第七晶体管T7断开，第三节点N3的高电平信号无法经由第七晶体管T7写入第四节点N4，第四节点N4维持上一帧的高电平，第九晶体管T9、第十一晶体管T11断开，第一电源端VGH的信号无法经由第九晶体管T9写入第五节点N5，第二电源端VGL的低电平信号无法经由第十一晶体管T11写入第六节点N6；由于第五节点N5为低电平，第十二晶体管T12、第十四晶体管T14导通，第一电源端VGH的信号经由第十四晶体管T14传输至第二信号输出端IEM_OUT，第二信号输出端IEM_OUT输出高电平信号，第一电源端VGH的信号经由第十二晶体管T12写入第六节点N6，第六节点N6为高电平，第 十三晶体管T13断开，第二电源端VGL的信号无法经由第十三晶体管T13输出至第二信号输出端IEM_OUT。在该阶段第一信号输出端EM_OUT输出低电平信号，第二信号输出端IEM_OUT输出高电平信号。
第二阶段M2：信号输入端IN和第一时钟信号端CLK的信号为高电平信号，第二时钟信号端CLKB的信号为低电平信号。第一时钟信号端CLK的高电平信号使第一晶体管T1、第二晶体管T2断开，信号输入端IN输入的高电平信号无法经由第一晶体管T1写入第一节点N1，第一节点N1维持上一帧的高电平，第三晶体管T3、第五晶体管T5、第八晶体管T8、第十晶体管T10断开，第二电源端VGL的信号无法经由第十晶体管T10写入第五节点N5；由于第二晶体管T2断开，第二电源端VGL的低电平信号无法经由第二晶体管T2写入第二节点N2，第二节点N2维持上一帧的低电平，第四晶体管T4、第六晶体管T6导通，第一电源端VGH的信号经由第四晶体管T4写入第七节点N7，第七节点N7为高电平，第一节点N1的高电平使第五晶体管T5断开，第二时钟信号端CLKB的信号无法经由第五晶体管T5写入第七节点N7，第二时钟信号端CLKB的低电平信号经由第六晶体管T6写入第三节点N3，第三节点N3为低电平，第二时钟信号端CLKB的低电平信号使第七晶体管T7导通，第三节点N3的低电平信号经由第七晶体管T7写入第四节点N4，第四节点N4为低电平，第九晶体管T9、第十一晶体管T11导通，第一电源端VGH的信号经由第九晶体管T9写入第五节点N5，第五节点N5为高电平，第一信号输出端EM_OUT输出高电平信号；由于第五节点N5为高电平，第十二晶体管T12、第十四晶体管T14断开，第一电源端VGH的信号无法经由第十四晶体管T14传输至第二信号输出端IEM_OUT，第一电源端VGH的信号无法经由第十二晶体管T12写入第六节点N6；由于第十一晶体管T11导通，第二电源端VGL的低电平信号经由第十一晶体管T11写入第六节点N6，第六节点N6为低电平，第十三晶体管T13导通，第二电源端VGL的信号经由第十三晶体管T13传输至第二信号输出端IEM_OUT，第二信号输出端IEM_OUT输出低电平信号。在该阶段第一信号输出端EM_OUT输出高电平信号，第二信号输出端IEM_OUT输出低电平信号。
第三阶段M3：信号输入端IN和第二时钟信号端CLKB的信号为高电平信号，第一时钟信号端CLK的信号为低电平信号。第一时钟信号端CLK的低电平信号使第一晶体管T1、第二晶体管T2导通，信号输入端IN输入的高电平信号经由第一晶体管T1写入第一节点N1，第一节点N1为高电平，第三晶体管T3、第五晶体管T5、第八晶体管T8、第十晶体管T10断开，第二电源端VGL的信号无法经由第十晶体管T10写入第五节点N5；由于第二晶体管T2导通，第二电源端VGL的低电平信号经由第二晶体管T2写入第二节点N2，第二节点N2为低电平，第四晶体管T4、第六晶体管T6导通，第一电源端VGH的信号经由第四晶体管T4写入第七节点N7，第七节点N7为高电平，第一节点N1的高电平使第五晶体管T5断开，第二时钟信号端CLKB的信号无法经由第五晶体管T5写入第七节点N7，第二时钟信号端CLKB的高电平信号经由第六晶体管T6写入第三节点N3，第三节点N3为高电平，由于第二时钟信号端CLKB的信号为高电平信号，第七晶体管T7断开，第三节点N3的高电平信号无法经由第七晶体管T7写入第四节点N4，第四节点N4维持上一帧的低电平，第九晶体管T9、第十一晶体管T11导通，第一电源端VGH的信号经由第九晶体管T9写入第五节点N5，第五节点N5为高电平，第一信号输出端EM_OUT输出高电平信号；由于第五节点N5为高电平，第十二晶体管T12、第十四晶体管T14断开，第一电源端VGH的信号无法经由第十四晶体管T14传输至第二信号输出端IEM_OUT，第一电源端VGH的信号无法经由第十二晶体管T12写入第六节点N6，由于第十一晶体管T11导通，第二电源端VGL的低电平信号经由第十一晶体管T11写入第六节点N6，第六节点N6为低电平，第十三晶体管T13导通，第二电源端VGL的信号经由第十三晶体管T13传输至第二信号输出端IEM_OUT，第二信号输出端IEM_OUT输出低电平信号。在该阶段第一信号输出端EM_OUT输出高电平信号，第二信号输出端IEM_OUT输出低电平信号。
第四阶段M4：第一时钟信号端CLK的信号为高电平信号，信号输入端IN和第二时钟信号端CLKB的信号为低电平信号。第一时钟信号端CLK的高电平信号使第一晶体管T1、第二晶体管T2断开，信号输入端IN输入的高电平信号无法经由第一晶体管T1写入第一节点N1，第一节点N1维持上一帧的高电平，第三晶体管T3、第五晶体管T5、第八晶体管T8、第十晶体 管T10断开，第二电源端VGL的信号无法经由第十晶体管T10写入第五节点N5；由于第二晶体管T2断开，第二电源端VGL的低电平信号无法经由第二晶体管T2写入第二节点N2，第二节点N2维持上一帧的低电平，第四晶体管T4、第六晶体管T6导通，第一电源端VGH的信号经由第四晶体管T4写入第七节点N7，第七节点N7为高电平，第一节点N1的高电平使第五晶体管T5断开，第二时钟信号端CLKB的信号无法经由第五晶体管T5写入第七节点N7，由于第六晶体管T6导通，第二时钟信号端CLKB的低电平信号经由第六晶体管T6写入第三节点N3，第三节点N3为低电平，由于第二时钟信号端CLKB的信号为低电平信号，第七晶体管T7导通，第三节点N3的低电平信号经由第七晶体管T7写入第四节点N4，第四节点N4为低电平，第十一晶体管T11、第九晶体管T9导通，第一电源端VGH的信号经由第九晶体管T9写入第五节点N5，第五节点N5为高电平，第一信号输出端EM_OUT输出高电平信号；由于第五节点N5为高电平，第十二晶体管T12、第十四晶体管T14断开，第一电源端VGH的信号无法经由第十四晶体管T14传输至第二信号输出端IEM_OUT，第一电源端VGH的信号无法经由第十二晶体管T12写入第六节点N6。由于第十一晶体管T11导通，第二电源端VGL的低电平信号经由第十一晶体管T11写入第六节点N6，第六节点N6为低电平，第十三晶体管T13导通，第二电源端VGL的信号经由第十三晶体管T13传输至第二信号输出端IEM_OUT，第二信号输出端IEM_OUT输出低电平信号。在该阶段第一信号输出端EM_OUT输出高电平信号，第二信号输出端IEM_OUT输出低电平信号。
第五阶段M5：第二时钟信号端CLKB的信号为高电平信号，信号输入端IN和第一时钟信号端CLK的信号为低电平信号。第一时钟信号端CLK的低电平信号使第一晶体管T1、第二晶体管T2导通，信号输入端IN输入的低电平信号写入第一节点N1，第一节点N1为低电平，第三晶体管T3、第五晶体管T5、第八晶体管T8、第十晶体管T10导通，第二电源端VGL的信号经由第十晶体管T10写入第五节点N5，第五节点N5为低电平，第一信号输出端EM_OUT输出低电平信号；由于第二晶体管T2导通，第二电源端VGL的低电平信号经由第二晶体管T2写入第二节点N2，第二节点N2为低电平，第四晶体管T4、第六晶体管T6导通，第一电源端VGH的信号经由 第四晶体管T4写入第七节点N7，第七节点N7为高电平，第二时钟信号端CLKB的高电平信号经由第六晶体管T6写入第三节点N3，第三节点N3为高电平，由于第二时钟信号端CLKB的信号为高电平信号，第七晶体管T7断开，第三节点N3的高电平信号无法经由第七晶体管T7写入第四节点N4，由于第八晶体管T8导通，第一电源端VGH的信号经由第八晶体管T8写入第四节点N4，第四节点N4为高电平，第九晶体管T9、第十一晶体管T11断开，第一电源端VGH的信号无法经由第九晶体管T9写入第五节点N5；由于第五节点N5为低电平，第十二晶体管T12、第十四晶体管T14导通，第一电源端VGH的信号经由第十四晶体管T14传输至第二信号输出端IEM_OUT，第二信号输出端IEM_OUT输出高电平信号，第一电源端VGH的信号经由第十二晶体管T12写入第六节点N6，第六节点N6为高电平，第十三晶体管T13断开。在该阶段第一信号输出端EM_OUT输出低电平信号，第二信号输出端IEM_OUT输出高电平信号。
第六阶段M6：在该阶段，信号输入端IN的输入信号保持低电平信号不变，第一时钟信号端CLK和第二时钟信号端CLKB的信号周期性变化，第一信号输出端EM_OUT和第二信号输出端IEM_OUT输出的信号保持不变，即第一信号输出端EM_OUT输出低电平信号，第二信号输出端IEM_OUT输出高电平信号。下面以第一子阶段M61、第二子阶段M62为例进行说明:
第一子阶段M61：第一时钟信号端CLK的信号为高电平信号，第二时钟信号端CLKB的信号为低电平信号。第一时钟信号端CLK的高电平信号使第一晶体管T1和第二晶体管T2断开，信号输入端IN输入的低电平信号无法经由第一晶体管T1写入第一节点N1，第二电源端VGL的低电平信号无法经由第二晶体管T2写入第二节点N2，第一节点N1维持上一帧的低电平，第三晶体管T3、第五晶体管T5、第八晶体管T8、第十晶体管T10导通，第一时钟信号端CLK的高电平信号经由第三晶体管T3写入第二节点N2，第二节点N2为高电平，第四晶体管T4和第六晶体管T6断开，第二时钟信号端CLKB的低电平无法经由第六晶体管T6写入第三节点N3，第三节点N3维持上一帧的高电平，第一电源端VGH的高电平信号经由第八晶体管T8写入第四节点N4，第四节点N4为高电平，第九晶体管T9、第十一晶体管 T11断开，第一电源端VGH的高电平信号无法经由第九晶体管T9写入第五节点N5，由于第十晶体管T10导通，第二电源端VGL的低电平信号经由第十晶体管T10写入第五节点N5，第五节点N5为低电平，第一信号输出端EM_OUT输出低电平信号；由于第十一晶体管T11断开，第二电源端VGL的低电平信号无法经由第十一晶体管T11写入第六节点N6，由于第五节点N5为低电平，第十二晶体管T12和第十四晶体管T14导通，第一电源端VGH的高电平信号经由第十四晶体管T14传输至第二信号输出端IEM_OUT，第二信号输出端IEM_OUT输出的信号为高电平信号，第一电源端VGH的高电平信号经由第十二晶体管T12写入第六节点N6，第六节点N6为高电平，第十三晶体管T13断开，第二电源端VGL的低电平信号无法传输至第二信号输出端IEM_OUT。
第二子阶段M62：第一时钟信号端CLK的信号为低电平信号，第二时钟信号端CLKB的信号为高电平信号。第一时钟信号端CLK的低电平信号使第一晶体管T1和第二晶体管T2导通，信号输入端IN输入的低电平信号经由第一晶体管T1写入第一节点N1，第二电源端VGL的低电平信号经由第二晶体管T2写入第二节点N2，第一节点N1和第二节点N2均为低电平，第三晶体管T3、第五晶体管T5、第八晶体管T8、第十晶体管T10、第六晶体管T6导通，第二时钟信号端CLKB的高电平经由第六晶体管T6写入第三节点N3，第三节点N3为高电平，第一电源端VGH的高电平信号经由第八晶体管T8写入第四节点N4，第四节点N4为高电平，第九晶体管T9、第十一晶体管T11断开，第一电源端VGH的高电平信号无法经由第九晶体管T9写入第五节点N5，由于第十晶体管T10导通，第二电源端VGL的低电平信号经由第十晶体管T10写入第五节点N5，第五节点N5为低电平，第一信号输出端EM_OUT输出的信号为低电平信号；由于第十一晶体管T11断开，第二电源端VGL的低电平信号无法经由第十一晶体管T11写入第六节点N6，由于第五节点N5为低电平，第十二晶体管T12、第十四晶体管T14导通，第一电源端VGH的高电平信号经由第十四晶体管T14传输至第二信号输出端IEM_OUT，第二信号输出端IEM_OUT输出的信号为高电平信号，第一电源端VGH的高电平信号经由第十二晶体管T12写入第六节点N6，第六节点N6为高电平，第十三晶体管T13断开，第二电源端VGL的低电平信号无 法传输至第二信号输出端IEM_OUT。
在本公开实施例中，通过上述图7、图9a至图9c所示的移位寄存器可以提供发光信号EM及其反相信号IEM，发光信号EM与发光信号的反相信号IEM周期相同，电压相反，根据图8时序图可以看出，发光信号EM及其反相信号IEM的脉宽可以根据输入信号IN进行调整，即通过图7、图9a至图9c所示的一个GOA电路可以提供脉宽可调的EM信号及与其反相的IEM信号，IEM信号和EM信号无需设置两个GOA电路，集成化程度高，脉宽可调，可以适用于不同脉宽需求以及不同类型的信号需求，应用范围广。
本公开实施例中图7、图9a至图9c所示的移位寄存器可以应用于如图10a所示的像素电路，第一信号输出端EM_OUT输出的信号作为图10a所示像素电路中的发光信号端EM的输入，第二信号输出端IEM_OUT输出的信号作为图10a所示像素电路中的发光信号端IEM的输入。图10b所示为图10a中像素电路的工作时序图。
本公开实施例还提供一种显示基板，显示基板可以包括基底以及设置在基底上的电路结构层，电路结构层包括发光驱动电路，发光驱动电路包括多个级联的移位寄存器，如图21所示。
在示例性实施方式中，如图21所示，第i级移位寄存器的第一信号输出端EM_OUT与第i+1级移位寄存器的信号输入端IN电连接，1≤i≤M-1，M为移位寄存器的总级数，M可以为大于或者等于2的正整数。在示例性实施方式中，第一级的移位寄存器的信号输入端IN可以与初始信号线STV连接。
在示例性实施方式中，图21中的至少一个移位寄存器可以如图6所示，可以包括：第一控制子电路、第二控制子电路、第三控制子电路、第一输出子电路、第二输出子电路；
第一控制子电路，分别与信号输入端IN、第一节点N1、第二节点N2、第一时钟信号端CLK、第二时钟信号端CLKB和第一电源端VGH连接，设置为在第一时钟信号端CLK、第二时钟信号端CLKB、第二节点N2和第一电源端VGH的控制下向第一节点N1提供信号输入端IN的信号，并维持第一节点N1的电位；
第二控制子电路，分别与第二电源端VGL、第一时钟信号端CLK、第一节点N1和第二节点N2连接，设置为在第一时钟信号端CLK和第一节点N1的控制下，向第二节点N2提供第二电源端VGL或者第一时钟信号端CLK的信号；
第三控制子电路，分别与第一节点N1、第二节点N2、第四节点N4、第二时钟信号端CLKB和第一电源端VGH连接，设置为在第二时钟信号端CLKB、第一节点N1、第二节点N2的控制下，向第四节点N4提供第二时钟信号端CLKB或者第一电源端VGH的信号，并维持第四节点N4的电位；
第一输出子电路，分别与第一电源端VGH、第二电源端VGL、第一节点N1、第四节点N4和第一信号输出端EM_OUT连接，设置为在第一节点N1和第四节点N4的控制下向第一信号输出端EM_OUT提供第一电源端VGH或者第二电源端VGL的信号；
第二输出子电路，分别与第一信号输出端EM_OUT、第三控制子电路、第一电源端VGH、第二电源端VGL和第二信号输出端IEM_OUT连接，设置为在第三控制子电路和第一信号输出端EM_OUT的控制下，向第二信号输出端IEM_OUT提供第一电源端VGH或者第二电源端VGL的信号。
在本公开实施例中，第一信号输出端EM_OUT和第二信号输出端IEM_OUT可以与显示基板中显示区域的像素电路电连接。在示例性实施方式中，第一信号输出端EM_OUT输出的信号和第二信号输出端IEM_OUT输出的信号可以为互为反相信号。
在示例性实施方式中，移位寄存器可以为前述任一个实施例提供的移位寄存器，实现原理和实现效果类似，在此不再赘述。
对于不同显示产品，发光驱动电路中多个移位寄存器的级联关系可能有所不同。无论多个移位寄存器的级联关系如何，每个移位寄存器驱动几行子像素，只要是类似这种大面积的器件发生改变，以及这种改变产生额外空间以后，小器件可能的简单平移、拉伸都在本公开的保护范围内。
在示例性实施方式中，本公开实施例显示基板中的移位寄存器的电路原理图可以如图7、图9a至图9c所示电路原理图中的任意一个，在此不再赘述。
在一种示例性实施例中，本公开实施例显示基板可以应用于具有发光驱动电路的显示装置中，如OLED、量子点显示(QLED)、发光二极管显示(Micro LED或Mini LED)或量子点发光二极管显示(QDLED)等，本公开实施例在此不做限定。
在一种示例性实施例中，显示基板还可以包括：设置在电路结构层远离基底一侧的发光结构层。发光结构层包括：位于显示区域的阵列排布的发光元件。
在一种示例性实施例中，发光元件可以是有机电致发光二极管(OLED)或者量子点发光二极管(QLED)。其中，OLED可以包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。在示例性实施方式中，与图9a所示电路原理图对应的版图结构可以如图11至图15b所示或者如图16至图20b所示。
在示例性实施方式中，如图15a-图15b、图20a-图20b所示，显示基板还可以包括：沿第二方向Y延伸的初始信号线STV、第一时钟信号线CLK、第二时钟信号线CLKB、第二电源线VGL和第三电源线VGH2，初始信号线STV、第一时钟信号线CLK、第二时钟信号线CLKB、第三电源线VGH2和第二电源线VGL沿第一方向X排布，第一方向X与第二方向Y相交；
第一级移位寄存器的信号输入端IN与初始信号线STV电连接，所有移位寄存器的第一电源端VGH与第三电源线VGH2电连接，所有移位寄存器的第二电源端VGL与第二电源线VGL电连接，第i级移位寄存器的时钟信号端与第一时钟信号线CLK和第二时钟信号线CLKB中的一条时钟信号线电连接，奇数级移位寄存器的第一时钟信号端CLK与第一时钟信号线CLK连接，奇数级移位寄存器的第二时钟信号端CLKB与第二时钟信号线CLKB连接，偶数级移位寄存器的第一时钟信号端CLK与第二时钟信号线连CLKB接，偶数级移位寄存器的第二时钟信号端CLKB与第一时钟信号线CLK连接。
在示例性实施方式中，如图15a-图15b、图20a-图20b所示，电路结构层可以包括：依次叠设在基底上的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层和第三导电层；
半导体层可以包括：位于发光驱动电路的所有晶体管的有源层；
第一导电层可以包括：位于发光驱动电路的所有晶体管的控制极以及第一电容C1的第一极板至第三电容C3的第一极板；
第二导电层可以包括：位于发光驱动电路的第一电容C1的第二极板至第三电容C3的第二极板；
第三导电层可以包括：初始信号线STV、第一时钟信号线CLK、第二时钟信号线CLKB、第一电源线VGH1、第二电源线VGL。
在示例性实施方式中，第三导电层还可以包括位于发光驱动电路的所有晶体管的第一极和第二极。
在示例性实施方式中，如图15a所示，移位寄存器可以包括：第一晶体管T1至第十四晶体管T14；
在显示基板所在平面内，在第一方向X上，所有晶体管以及电容均位于第三电源线VGH2与第二电源线VGL之间，第二电容C2位于第三电源线VGH2与第八晶体管T8之间，第八晶体管T8位于第二电容C2与第九晶体管T9和第十晶体管T10之间，第九晶体管T9和第十晶体管T10位于第八晶体管T8与第十一晶体管T11和第十二晶体管T12之间，第十一晶体管T11和第十二晶体管T12位于第九晶体管T9和第十晶体管T10与第十三晶体管T13和第十四晶体管T14之间，第十三晶体管T13和第十四晶体管T14位于第十一晶体管T11和第十二晶体管T12与第二电源线VGL之间；在第二方向Y上，第三电容C3、第九晶体管T9、第十晶体管T10、第一电容C1沿第二方向Y依次排布，第十二晶体管T12、第十一晶体管T11沿第二方向Y依次排布，第十四晶体管T14、第十三晶体管T13沿第二方向Y依次排布。
在示例性实施方式中，如图12b所示，第一导电层还可以包括第一电源线VGH1，第一电源线VGH1可以与第一电源端VGH连接；第一电源线VGH1可以为折线状，并沿第一方向X延伸；
在平行于所述显示基板的平面上，在第一方向X上，第一电源线VGH1可以位于第三电容C3远离第八晶体管T8的控制极的一侧；在第二方向Y上，第一电源线VGH1可以位于第十四晶体管T14的控制极远离第十三晶体 管T13的控制极的一侧。
在示例性实施方式中，第一电源线VGH1在基底上的正投影可以分别与第九晶体管T9的第一极、第十二晶体管T12的第一极、第十四晶体管T14的第一极在基底上的正投影至少部分交叠；
如图15b所示，第三导电层中第八晶体管T8的第一极和第九晶体管T9的第一极可以为一体成型结构。
在示例性实施方式中，如图12b所示，第一导电层还可以包括第一信号输出线EM_OUT和第二信号输出线IEM_OUT；第一信号输出线EM_OUT的形状可以为条状并沿第一方向X延伸，第二信号输出线IEM_OUT的形状呈“L”型；
在第一导电层所在平面内，在第二方向Y上，第一信号输出线EM_OUT位于第十三晶体管T13的控制极与第一电源线VGH1之间，第一信号输出线EM_OUT与第十四晶体管T14的控制极可以为一体成型结构，第二信号输出线IEM_OUT可以位于第一电源线VGH1远离第一信号输出线EM_OUT的一侧；在第一方向X上，第一信号输出线EM_OUT位于第十四晶体管T14的控制极远离第十二晶体管T12的控制极的一侧，第二信号输出线IEM_OUT位于第三电容C3的第一极板C31远离第八晶体管T8的控制极的一侧。
在示例性实施方式中，如图12b所示，第一导电层还可以包括第二连接线CL2，第二连接线CL2、第三电容C3的第一极板C31、第九晶体管T9的控制极可以为一体成型结构，第十一晶体管T11的控制极形状可以呈“L”型。
在示例性实施方式中，如图15b所示，第三导电层还可以包括第四连接线CL4，第四连接线的形状可以为折线状，并可以沿第二方向Y延伸，第四连接线CL4在基底上的正投影分别与第十一晶体管T11的控制极和第三电容C3的第一极板C31在基底上的正投影至少部分重叠。
在示例性实施方式中，如图15b所示，第九晶体管T9的第二极392可以包括相互连接的第三结构392-1和第四结构392-2，第三结构392-1的形状可以为条状，并沿第一方向X延伸，位于第八晶体管T8的第二极与第四连 接线CL4之间，在靠近第四连接线CL4的一端与第四结构392-2连接；第四结构的392-2形状可以为条状，并沿第二方向Y延伸，靠近第三结构392-1的一端与第三结构392-1连接。
在示例性实施方式中，如图15b所示，第十三晶体管T13的第二极3132可以包括相互连接的第五结构3132-1和第六结构3132-2，第五结构3132-1的形状可以为条状，并沿第一方向X延伸，位于第十三晶体管T13的第一极3131与第十四晶体管T14的第一极3141之间；第六结构3132-2可以呈“L”型，在第一方向X上位于第十四晶体管T14的第一极3141与第二电源线VGL之间，在第二方向Y上靠近第十三晶体管T13的第一极3131的一侧与第五结构3132-1连接，第六结构3132-2在基底上的正投影与第二信号输出线IEM_OUT在基底上的正投影至少部分重叠。
在示例性实施方式中，如图15b所示，第十二晶体管T12的第一极3121和第十四晶体管T14的第一极3141均呈“L”型，位于第四连接线CL4远离第三电源线VGH2的一侧。
在示例性实施方式中，如图20a所示，移位寄存器可以包括：第一晶体管T1至第十四晶体管T14；
在显示基板所在平面内，在第一方向X上，所有晶体管以及电容均位于第三电源线VGH2与第二电源线VGL之间，第二电容C2位于第三电源线VGH2与第八晶体管T8之间，第八晶体管T8位于第二电容C2与第九晶体管T9和第十晶体管T10之间，第九晶体管T9和第十晶体管T10位于第八晶体管T8与第二电源线VGL之间，第十一晶体管T11和第十二晶体管T12位于第三电源线VGH2与第十三晶体管T13和第十四晶体管T14之间，第十三晶体管T13和第十四晶体管T14位于第十一晶体管T11和第十二晶体管T12与第二电源线VGL之间；在第二方向Y上，第十三晶体管T13、第十四晶体管T14、第三电容C3、第九晶体管T9、第十晶体管T10、第一电容C1沿第二方向Y依次排布。
在示例性实施方式中，如图17b所示，第一导电层还可以包括第一电源线VGH1，第一电源线VGH1可以与第一电源端VGH连接；第一电源线VGH1可以呈“L”型；
在第一导电层所在平面内，在第一方向X上，第一电源线VGH1可以位于第三电容C3的第一极板C31远离第二电容C2的第一极板C21的一侧；在第二方向Y上，第一电源线VGH1可以位于第十四晶体管T14的控制极与第一电容C1的第一极板C11之间。
在示例性实施方式中，如图17b、图20a-图20b所示，第一电源线VGH1在基底上的正投影与第九晶体管T9的第一极391在基底上的正投影至少部分交叠。
在示例性实施方式中，如图20a-图20b所示，第三导电层中第八晶体管T8的第一极381和第九晶体管T9的第一极391可以为一体成型结构。
在示例性实施方式中，如图17b、图18b所示，第一导电层还可以包括电源连接线VCL，第二导电层还可以包括第一信号输出线EM_OUT、第二信号输出线IEM_OUT；第一信号输出线EM_OUT和第二信号输出线IEM_OUT的形状均可以为沿第一方向X延伸的折线状；
在第二导电层所在平面内，在第二方向Y上，第一信号输出线EM_OUT可以位于第一电容C1的第二极板C12与第三电容C3的第二极板C32之间，第二信号输出线IEM_OUT可以位于第三电容C3的第二极板C32远离第一电容C1的第二极板C12的一侧；在第一方向X上，第一信号输出线EM_OUT和第二信号输出线IEM_OUT均位于第三电容C3的第二极板C32远离第二电容C2的第二极板C22的一侧。
在示例性实施方式中，如图17b所示，电源连接线VCL可以为“n”型，在第二方向Y上，可以位于第十三晶体管T13的控制极远离第十四晶体管T14的控制极的一侧，并设有背离第十三晶体管T13一侧的开口；在示例性实施方式中，如图17b、图20a-20b所示，电源连接线VCL在基底上的正投影可以分别与第二电源线VGL和第十三晶体管T13的第一极在基底上的正投影至少部分重叠。
在示例性实施方式中，如图17b、图20a-20b所示，第一导电层还可以包括第二连接线CL2，第二连接线CL2可以与第三电容C3的第一极板C31、第九晶体管T9的控制极29、第十一晶体管T11的控制极211一体成型，第 十一晶体管T11的控制极211形状可以呈“n”型，并设有朝向第十二晶体管T12一侧的开口。
在示例性实施方式中，如图20a-20b所示，第九晶体管T9的第二极392可以包括相互连接的第三结构392-1、第四结构392-2和第九结构392-3，第三结构392-1的形状可以为条状，并沿第一方向X延伸，位于第八晶体管T8的第二极382与第二电源线VGL之间，在靠近第二电源线VGL的一端与第四结构392-2连接；第四结构392-2的形状可以为条状，可以位于第二电源线VGL靠近第三电源线VGH2的一侧，并沿第二方向Y延伸，靠近第三结构392-1的一端与第三结构392-1连接；第九结构392-3的形状为条状，位于第四结构392-2远离第二电源线VGL的一侧，第四结构392-3在基底上的正投影与第四晶体管T4的控制极24在基底上的正投影至少部分重叠。
在示例性实施方式中，如图20a-20b所示，第十三晶体管T13的第二极3132可以为条状结构，并沿第一方向X延伸，第十三晶体管T13的第一极3131可以包括相互连接的第七结构3131-1和第八结构3131-2，第七结构3131-1的形状可以为条状，并沿第一方向X延伸，一端与第十一晶体管T11的第一极3111连接，另一端与第八结构3131-2连接；第八结构3131-2可以为方形结构，可以与第七结构3131-1一体成型，第八结构在3131-2基底上的正投影与电源连接线VCL在基底上的正投影至少部分重叠。
在示例性实施方式中，如图20a-20b所示，第十二晶体管T12和第十四晶体管T14的第一极可以为沿第一方向X延伸且相互连接的条状结构，第十二晶体管T12的第一极3121一端与第三电源线VGH2连接，另一端与第十四晶体管T14的第一极3141连接，第十四晶体管T14的第一极3141可以位于第十二晶体管T12的第一极3121远离第三电源线VGH2的一侧，第十二晶体管T12的第一极3121可以与第十四晶体管T14的第一极3141、第三电源线VGH2为一体成型结构。
在示例性实施方式中，如图15a-15b、图20a-20b所示，第三导电层还可以包括信号输入线IN，信号输入线IN可以为折线状，并沿第一方向X延伸，在第三导电层所在平面内，在第一方向X上，信号输入线IN可以位于第三电源线VGH2与第二电源线VGL之间；在第二方向Y上，信号输入线IN 可以位于第十晶体管T10远离第九晶体管T9的一侧。
在示例性实施方式中，信号输入线IN可以与第一晶体管T1的第一极311可以为一体成型结构。
在示例性实施方式中，如图15a-15b、图20a-20b所示，在第二导电层所在平面内，第二电容C2的第二极板C22、第三电容C3的第一极板C31可沿第一方向X排布，在第二方向Y上，第二电容C2的第二极板C22和第三电容C3的第二极板C32位于第一电容C1的第二极板C12的同一侧；
第一电容C1的第二极板C12的形状可以为折线状，并沿第一方向X延伸，第一电容C1的第二极板C12在基底上的正投影与第一电容C1的第一极板C11在基底上的正投影存在重叠区域；第二电容C2的第二极板C22的形状可以为方形，第二电容C2的第二极板C22在基底上的正投影与第二电容C2的第一极板C21在基底上的正投影存在重叠区域；第三电容C3的第二极板C32的形状可以为条状，并沿第一方向X延伸，第三电容C3的第二极板C32在基底上的正投影与第三电容C3的第一极板C31在基底上的正投影存在重叠区域。
在示例性实施方式中，如图13b、图15a、17b、图20a所示，与第一电源端VGH连接的电源线可以包括第一电源线VGH1和第三电源线VGH2，第一电源端VGH可以包括一个电源端或者多个电源端。例如，第一电源端VGH可以包括第一子电源端和第二子电源端，第一电源线VGH1可以与第一子电源端连接，第三电源线VGH2可以与第二子电源端连接。
在示例性实施方式中，如图12a、图15a、图17a、图20a所示，第九晶体管T9、第十晶体管T10、第十三晶体管T13和第十四晶体管T14中的任意一个晶体管可以包括多个个相互并联的子晶体管，并且多个子晶体管的有源层相互独立设置，多个子晶体管的控制极为一体成型结构，多个子晶体管的第一极为一体成型结构，多个子晶体管的第二极为一体成型结构。例如，第九晶体管T9、第十晶体管T10、第十三晶体管T13和第十四晶体管T14中的任意一个晶体管可以包括四个相互并联的子晶体管，并且四个子晶体管的有源层相互独立，四个子晶体管的控制极为一体成型结构，四个子晶体管的第一极为一体成型结构、四个子晶体管的第二极为一体成型结构。
例如，如图11-12b、图15a-15b、图16-17b、图20a-20b所示，第九晶体管T9可以包括相互并联的第一子晶体管T9-1、第二子晶体管T9-2、第三子晶体管T9-3、第四子晶体管T9-4，第一子晶体管T9-1、第二子晶体管T9-2、第三子晶体管T9-3、第四子晶体管T9-4的有源层分别为第一子有源层19-1、第二子有源层19-2、第三子有源层19-3、第四子有源层19-4，第一子晶体管T9-1、第二子晶体管T9-2、第三子晶体管T9-3、第四子晶体管T9-4的控制极为一体成型结构并形成第九晶体管T9的控制极29，第一子晶体管T9-1、第二子晶体管T9-2、第三子晶体管T9-3、第四子晶体管T9-4的第一极为一体成型结构并形成第九晶体管T9的第一极391，第一子晶体管T9-1、第二子晶体管T9-2、第三子晶体管T9-3、第四子晶体管T9-4的第二极为一体成型结构并形成第九晶体管T9的第二极392；
第十晶体管T10可以包括相互并联的第五子晶体管T10-1、第六子晶体管T10-2、第七子晶体管T10-3、第八子晶体管T10-4，第五子晶体管T10-1、第六子晶体管T10-2、第七子晶体管T10-3、第八子晶体管T10-4的有源层分别为第五子有源层110-1、第六子有源层110-2、第七子有源层110-3、第八子有源层110-4，第五子晶体管T10-1、第六子晶体管T10-2、第七子晶体管T10-3、第八子晶体管T10-4的控制极为一体成型结构并形成第十晶体管T10的控制极210，第五子晶体管T10-1、第六子晶体管T10-2、第七子晶体管T10-3、第八子晶体管T10-4的第一极为一体成型结构并形成第十晶体管T10的第一极3101，第五子晶体管T10-1、第六子晶体管T10-2、第七子晶体管T10-3、第八子晶体管T10-4的第二极为一体成型结构并形成第十晶体管T10的第二极3102；
第十三晶体管T13可以包括相互并联的第九子晶体管T13-1、第十子晶体管T13-2、第十一子晶体管T13-3、第十二子晶体管T13-4，第九子晶体管T13-1、第十子晶体管T13-2、第十一子晶体管T13-3、第十二子晶体管T13-4的有源层分别为第九子有源层113-1、第十子有源层113-2、第十一子有源层113-3、第十二子有源层113-4，第九子晶体管T13-1、第十子晶体管T13-2、第十一子晶体管T13-3、第十二子晶体管T13-4的控制极为一体成型结构并形成第十三晶体管T13的控制极213，第九子晶体管T13-1、第十子晶体管 T13-2、第十一子晶体管T13-3、第十二子晶体管T13-4的第一极为一体成型结构并形成第十三晶体管T13的第一极3131，第九子晶体管T13-1、第十子晶体管T13-2、第十一子晶体管T13-3、第十二子晶体管T13-4的第二极为一体成型结构并形成第十三晶体管T13的第二极3132；
第十四晶体管T14可以包括相互并联的第十三子晶体管T14-1、第十四子晶体管T14-2、第十五子晶体管T14-3、第十六子晶体管T14-4，第十三子晶体管T14-1、第十四子晶体管T14-2、第十五子晶体管T14-3、第十六子晶体管T14-4的有源层分别为第十三子有源层114-1、第十四子有源层114-2、第十五子有源层114-3、第十六子有源层114-4，第十三子晶体管T14-1、第十四子晶体管T14-2、第十五子晶体管T14-3、第十六子晶体管T14-4的控制极可以为一体成型结构并形成第十四晶体管T14的控制极214，第十三子晶体管T14-1、第十四子晶体管T14-2、第十五子晶体管T14-3、第十六子晶体管T14-4的第一极可以为一体成型结构并形成第十四晶体管T14的第一极3141，第十三子晶体管T14-1、第十四子晶体管T14-2、第十五子晶体管T14-3、第十六子晶体管T14-4的第二极可以为一体成型结构并形成第十四晶体管T14的第二极3142。在本公开实施例中，与第一输出信号线EM_OUT连接的第九晶体管T9和第十晶体管T10均由多个子晶体管相互并联连接，任意一个晶体管中的多个子晶体管的有源层相互独立设置，多个子晶体管的控制极一体成型，多个子晶体管的第一极一体成型，多个子晶体管的第二极一体成型，可以提高移位寄存器第一输出信号端EM_OUT输出的可靠性，另外，将一个大的晶体管分割为多个小的晶体管，可以有利于散热。
在本公开实施例中，与第二输出信号线IEM_OUT连接的第十三晶体管T13和第十四晶体管T14均由多个子晶体管相互并联连接，任意一个晶体管中的多个子晶体管的有源层相互独立设置，多个子晶体管的控制极一体成型，多个子晶体管的第一极一体成型，多个子晶体管的第二极一体成型，可以提高移位寄存器第一输出信号端EM_OUT输出的可靠性，另外，将一个大的晶体管分割为多个小的晶体管，可以有利于散热。
在示例性实施方式中，如图15a和图20a所示，在显示基板所在平面内，在第一方向X上，第一晶体管T1、第四晶体管T4至第七晶体管T7位于第 三电源线VGH2与第二电容C2之间，第二晶体管T2和第三晶体管T3位于第五晶体管T5与第一电容C1之间。
在示例性实施方式中，如图15a-15b、图20a-20b所示，第六晶体管T6的第二极362和第七晶体管T7的第一极71可以共用一个电极，第九晶体管T9的第二极392和第十晶体管T10的第二极3102可以共用一个电极，第十三晶体管T13第二极3132和第十四晶体管T14的第二极3142可以共用一个电极。在本公开实施例中，两个晶体管共用一个电极，在很大程度上可以节省布线空间。
在本公开实施例中，可以根据实际情况选择图15a和图20a所示的结构，其中，图20a所示结构可以应用于PPI较高的显示基板中，并且可以适用于窄边框。例如，图15a所示的结构可以应用于1000PPI的显示基板，图20a所示的结构可以应用于1200PPI的显示基板。
在示例性实施方式中，第一电源线VGH1和第三电源线VGH2可以提供相同的电源信号。上述第一电源端VGH可以与第一电源线VGH1、第三电源线VGH2电连接。
在本公开实施例中，在平行于显示基板所在的平面上，第一方向X与第二方向Y相交。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底(或衬底基板)上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。 本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在一种示例性实施方式中，显示基板的制备过程可以包括如下操作。
(101)在基底上形成半导体层图案。在示例性实施方式中，在基底上形成有源层图案可以包括：在基底上沉积半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成半导体层图案，如图11所示，图11所示为在基底上形成半导体层图案后的示意图。
在示例性实施方式中，如图11所示，半导体层图案可以包括第一晶体管T1的有源层11、第二晶体管T2的有源层12、第三晶体管T3的有源层13、第四晶体管T4的有源层14、第五晶体管T5的有源层15、第六晶体管T6的有源层16、第七晶体管T7的有源层17、第八晶体管T8的有源层18、第九晶体管T9的有源层19、第十晶体管T10的有源层110、第十一晶体管T11的有源层111、第十二晶体管T12的有源层112、第十三晶体管T13的有源层113、第十四晶体管T14的有源层114。
在示例性实施方式中，在半导体层所在的平面内，在第一方向X上，第一晶体管T1的有源层至第八晶体管T8的有源层18位于第九晶体管T9的有源层19和第十晶体管T10的有源层110远离第十三晶体管T13的有源层113和第十四晶体管T14的有源层114的一侧，第十一晶体管T11的有源层111和第十二晶体管T12的有源层112位于第九晶体管T9的有源层19和第十三晶体管T13的有源层113之间，第九晶体管T9的有源层19和第十晶体管T10的有源层110、第十一晶体管T11的有源层11和第十二晶体管T12的有源层112、第十三晶体管T13的有源层113和第十四晶体管T14的有源层114沿第一方向X依次排列。
在示例性实施方式中，第一晶体管T1的有源层11至第八晶体管T8的有源层18沿第一方向X延伸。在示例性实施方式中，在第二方向Y上，第四晶体管T4的有源层14位于第一晶体管T1的有源层11和第六晶体管T6的有源层16之间，例如，第六晶体管T6的有源层16、第四晶体管T4的有源层14、第一晶体管T1的有源层11沿第二方向Y依次排布。
在示例性实施方式中，第四晶体管T4的有源层14、第五晶体管T5的有源层15、第三晶体管T3的有源层13、第二晶体管T2的有源层12沿第一方向X依次排布，在第二方向Y上，第一晶体管T1的有源层11、第二晶体管T2的有源层12、第三晶体管T3的有源层13、第五晶体管T5的有源层15位于第四晶体管T4的有源层14远离第六晶体管T6的有源层16的一侧。
在示例性实施方式中，第六晶体管T6的有源层16、第七晶体管T7的有源层17、第八晶体管T8的有源层18沿第一方向X依次排布，第六晶体管T6的有源层16与第七晶体管T7的有源层17可以为一体成型结构。在第二方向Y上，第七晶体管T7的有源层17、第八晶体管T8的有源层18位于第六晶体管T6的有源层16远离第一晶体管T1的有源层11的一侧。
在示例性实施方式中，在第二方向Y上，第九晶体管T9的有源层19位于第十晶体管T10的有源层110的一侧，例如，第九晶体管T9的有源层19、第十晶体管T10的有源层110沿第二方向Y排列。在示例性实施方式中，第九晶体管T9的有源层19、第十晶体管T10的有源层110为一体成型结构。
在示例性实施方式中，在第二方向Y上，第十一晶体管T11的有源层11位于第十二晶体管T12的有源层112的一侧，例如，第十二晶体管T12的有源层112、第十一晶体管T11的有源层11沿第二方向Y排列。在示例性实施方式中，第十一晶体管T11的有源层11和第十二晶体管T12可以为一体成型结构。
在示例性实施方式中，在第二方向Y上，第十三晶体管T13的有源层113位于第十四晶体管T14的有源层114的一侧，例如，第十四晶体管T14的有源层114、第十三晶体管T13的有源层113沿第二方向Y排列。在示例性实施方式中，第十三晶体管T13的有源层113、第十四晶体管T14的有源层114可以为一体成型结构。
在示例性实施方式中，第一晶体管T1至第十四晶体管T14的有源层可以为矩形结构。
在示例性实施方式中，第一晶体管T1至第十四晶体管T14的有源层是基于硅技术形成的半导体层。
在示例性实施方式中，第九晶体管T9、第十晶体管T10、第十三晶体管T13和第十四晶体管T14的有源层的宽度比其他晶体管的有源层的宽度大，以使第九晶体管T9、第十晶体管T10、第十三晶体管T13和第十四晶体管T14的宽长比(W/L)较大。例如，第九晶体管T9、第十晶体管T10、第十三晶体管T13和第十四晶体管T14的有源层沿第一方向X的尺寸比第十一晶体管T11的有源层111沿第一方向X的尺寸大。
在示例性实施方式中，第九晶体管T9、第十晶体管T10、第十三晶体管T13和第十四晶体管T14的有源层均可以设置为包括多个相互分离的有源层结构。例如，第九晶体管T9的有源层19可以包括四个相互分离的有源层，第九晶体管T9的四个相互分离的有源层可以包括第一子有源层19-1、第二子有源层19-2、第三子有源层19-3、第四子有源层19-4，第十晶体管T10的有源层110可以包括四个相互分离的有源层，第十晶体管T10的四个相互分离的有源层可以包括第五子有源层110-1、第六子有源层110-2、第七子有源层110-3、第八子有源层110-4，第五子有源层110-1与第一子有源层19-1可以为一体成型结构，第六子有源层110-2与第二子有源层19-2可以为一体成型的矩形结构，第七子有源层110-3与第三子有源层19-3可以为一体成型的矩形结构，第八子有源层110-4与第四子有源层19-4可以为一体成型的矩形结构。
在示例性实施方式中，第十三晶体管T13的有源层113可以包括四个相互分离的有源层，第十三晶体管T13的四个相互分离的有源层可以包括第九子有源层113-1、第十子有源层113-2、第十一子有源层113-3、第十二子有源层113-4，第十四晶体管T14的有源层114可以包括四个相互分离的有源层，第十四晶体管T14的四个相互分离的有源层可以包括第十三子有源层114-1、第十四子有源层114-2、第十五子有源层114-3、第十六子有源层114-4，第十三子有源层114-1与第九子有源层113-1可以为一体成型结构，第十四子有源层114-2与第十子有源层113-2可以为一体成型的矩形结构，第十五子有源层114-3与第十一子有源层113-3可以为一体成型的矩形结构，第十六子有源层114-4与第十二子有源层113-4可以为一体成型的矩形结构。
在示例性实施方式中，基底可以为刚性基底或柔性基底，其中，刚性基 底可以为但不限于玻璃、金属萡片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。在示例性实施方式中，以叠层结构PI1/Barrier1/a-si/PI2/Barrier2为例，其制备过程可以包括：先在玻璃载板上涂布一层聚酰亚胺，固化成膜后形成第一柔性(PI1)层；随后在第一柔性层上沉积一层阻挡薄膜，形成覆盖第一柔性层的第一阻挡(Barrier1)层；然后在第一阻挡层上沉积一层非晶硅薄膜，形成覆盖第一阻挡层的非晶硅(a-si)层；然后在非晶硅层上再涂布一层聚酰亚胺，固化成膜后形成第二柔性(PI2)层；然后在第二柔性层上沉积一层阻挡薄膜，形成覆盖第二柔性层的第二阻挡(Barrier2)层，完成基底的制备。
在示例性实施方式中，第一半导体层可以采用多晶硅(p-Si)，即第一晶体管T1至第十四晶体管T14可以为LTPS薄膜晶体管。在示例性实施方式中，通过图案化工艺对第一半导体薄膜进行图案化，可以包括：先在第一绝缘薄膜上形成非晶硅(a-si)薄膜，对非晶硅薄膜进行脱氢处理，对脱氢处理后的非晶硅薄膜进行结晶处理，形成多晶硅薄膜。随后，对多晶硅薄膜进行图案化，形成第一半导体层图案。
(102)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第一绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第一绝缘层，以及设置在第一绝缘层上的第一导电层图案，如图12a和图12b所示，图12a所示为形成第一导电层图案后的示意图，图12b为图12a中第一导电层的平面示意图。在示例性实施方式中，第一导电层可以称为第 一栅金属(GATE1)层。
在示例性实施方式中，第一导电层图案可以至少包括：第一电容C1的第一极板C11、第二电容C2的第一极板C21、第三电容C3的第一极板C31、第一晶体管T1的控制极21、第二晶体管T2的控制极22、第三晶体管T3的控制极23、第四晶体管T4的控制极24、第五晶体管T5的控制极25、第六晶体管T6的控制极26、第七晶体管T7的控制极27、第八晶体管T8的控制极28、第九晶体管T9的控制极29、第十晶体管T10的控制极210、第十一晶体管T11的控制极211、第十二晶体管T12的控制极212、第十三晶体管T13的控制极213、第十四晶体管T14的控制极214、第一连接线CL1、第二连接线CL2、第三连接线CL3、第一号输出线EM_OUT、第二信号输出线IEM_OUT、第一电源线VGH1。
在示例性实施方式中，第一电容C1的第一极板C11、第十晶体管T10的控制极210、第八晶体管T8的控制极28、第一连接线CL1、第三晶体管T3的控制极23可以为一体成型结构。第三电容C3的第一极板C31、第二连接线CL2、第九晶体管T9的控制极29可以为一体成型结构。第五晶体管T5的控制极25、第三连接线CL3、第七晶体管T7的控制极27可以为一体成型结构。第四晶体管T4的控制极24、第六晶体管T6的控制极26可以为一体成型结构。第二晶体管T2的控制极22、第一晶体管T2的控制极21可以为一体成型结构。第十二晶体管T12的控制极212、第十四晶体管T14的控制极214、第一号输出线EM_OUT可以为一体成型结构。
在示例性实施方式中，第一电容C1的第一极板C11的主体部分可以为沿第一方向X延伸的条状，在第二方向Y上，第一电容C1的第一极板C11可以位于第十晶体管T10的控制极210远离第三电容C3的第一极板C31的一侧，在第一方向X上，第一电容C1的第一极板C11可以位于第八晶体管T8的控制极28远离第二电容C2的第一极板C21的一侧。在示例性实施方式中，第一电容C1的第一极板C11靠近第十晶体管T10的控制极210的一侧设有第一连接部C11-1，第一连接部C11-1沿第二方向Y延伸，一端与第一电容C1的第一极板C11连接，另一端与第十晶体管T10的控制极210连接。
在示例性实施方式中，第二电容C2的第一极板C21的形状可以为方形，在第一方向X上，第二电容C2的第一极板C21可以位于第七晶体管T7的控制极27与第八晶体管T8的控制极28之间，在第二方向Y上，第二电容C2的第一极板C21可以位于第三晶体管T3的控制极23远离第二晶体管T2的控制极22的一侧，第二电容C2的第一极板C21靠近第七晶体管T7的控制极27一侧的边缘上设置有凸起，第二电容C2的第一极板C21靠近第八晶体管T8的控制极28一侧的边缘以及靠近第三晶体管T3的控制极23一侧的边缘呈阶梯状。
在示例性实施方式中，第三电容C3的第一极板C31的形状可以为折线状，且沿第一方向X延伸，在第二方向Y上，第三电容C3的第一极板C31可以位于第九晶体管T9的控制极29远离第一电容C1的第一极板C11的一侧；在第一方向X上，第三电容C3的第一极板C31可以位于第八晶体管T8的控制极28远离第二电容C2的第一极板C21的一侧。在示例性实施方式中，第三电容C3的第一极板C31靠近第八晶体管T8的控制极28的一端与第二连接线CL2连接。
在示例性实施方式中，第一晶体管T1的控制极21的形状可以为折线状，并沿第一方向X延伸。在示例性实施方式中，在第二方向Y上，第一晶体管T1的控制极21可以位于第二晶体管T2的控制极22远离第一电容C1的第一极板的一侧，并且在靠近第一电容C1的第一极板的一侧与第二晶体管T2的控制极22连接。
在示例性实施方式中，第二晶体管T2的控制极22的形状可以为“n”型，并设有朝向第二电容C2的第一极板C21一侧的开口。在示例性实施方式中，在第二方向Y上，第二晶体管T2的控制极22可以位于第十晶体管T10的控制极210远离第三电容C3的第一极板C31的一侧，在第一方向X上，第二晶体管T2的控制极22可以位于第一晶体管T1的控制极21与第一电容C1的第一极板C11之间，并且第二晶体管T2的控制极22在靠近第一晶体管T1的控制极21的一侧与第一晶体管T1的控制极21连接。
在示例性实施方式中，在第二方向Y上，第三晶体管T3的控制极23可以位于第二晶体管T2的控制极22与第二电容C2的第一极板C21之间，在 第一方向X上，第三晶体管T3的控制极23可以位于第一晶体管T1的控制极21与第五晶体管T5的控制极25之间，第三晶体管T3的控制极23远离第一晶体管T1的控制极21的一侧通过第一连接线CL1与第八晶体管T8的控制极28连接。其中，第三晶体管T3的形状可以为倒“n”型，且设置有朝向第二晶体管T2的控制极22的开口。
在示例性实施方式中，在第二方向Y上，第四晶体管T4的控制极24可以位于第一晶体管T1的控制极21与第六晶体管T6的控制极26之间，第四晶体管T4的控制极24远离第一晶体管T1的控制极21的一侧与第六晶体管T6的控制极26连接。其中，第四晶体管T4的控制极24的形状可以为倒“T”型。
在示例性实施方式中，在第二方向Y上，第五晶体管T5的控制极25可以位于第七晶体管T7的控制极27与第二晶体管T2的控制极22之间。其中，第五晶体管T5的控制极25的形状可以为条状并可以沿第二方向Y延伸，在第二方向Y上，第五晶体管T5的控制极25远离第二晶体管T2的控制极22的一端与第三连接线CL3连接。
在示例性实施方式中，第六晶体管T6的控制极26可以位于第四晶体管T4的控制极24远离第二晶体管T2的控制极22的一侧，且第六晶体管T6的控制极26靠近第二晶体管T2的控制极22的一侧与第四晶体管T4的控制极24连接。其中，第六晶体管T6的控制极26的形状可以为“T”型。
在示例性实施方式中，第七晶体管T7的控制极27可以位于第二电容C2的第一极板C21远离第八晶体管T8的控制极28的一侧，在第二方向Y上，第七晶体管T7的控制极27可以位于第五晶体管T5的控制极25远离第一晶体管T1的控制极21的一侧。
在示例性实施方式中，第七晶体管T7的控制极27可以包括沿第一方向X延伸的第一连接结构27-1和沿第二方向Y延伸的第二连接结构27-2，在第一方向X上，第一连接结构27-1可以位于第二连接结构27-2远离第二电容C2的第一极板C21的一侧，第二连接结构27-2可以位于第六晶体管T6的控制极26与第二电容C2的第一极板C21之间。第二连接结构27-2一端与第三连接线CL3连接，另一端与第一连接结构27-1连接。
在示例性实施方式中，第八晶体管T8的控制极28的形状可以为条状，并沿第二方向Y延伸。在第一方向X上，第八晶体管T8的控制极28可以位于第二电容C2的第一极板C21与第九晶体管T9的控制极29之间，在第二方向Y上，第八晶体管T8的控制极28可以位于第一连接线CL1远离第二晶体管T2的控制极22的一侧，并且在靠近第二晶体管T2的控制极22的一端与第三连接线CL3和第十晶体管T10的控制极210连接。
在示例性实施方式中，第九晶体管T9的控制极29的形状可以为条状，并沿第一方向X延伸。在示例性实施方式中，在第二方向Y上，第九晶体管T9的控制极29可以位于第十晶体管T10的控制极210与第三电容C3的第一极板C31之间，并通过第二连接线CL2与第三电容C3的第一极板C31连接，在第一方向X上，第九晶体管T9的控制极29可以位于第八晶体管T8的控制极28与第十四晶体管T14的控制极214之间，并且在靠近第八晶体管T8的控制极28的一端与第二连接线CL2连接。
在示例性实施方式中，第九晶体管T9的控制极29在基底上的正投影与第一子有源层19-1、第二子有源层19-2、第三子有源层19-3、第四子有源层19-4在基底上的正投影存在重叠区域。即，第九晶体管T9的控制极29跨设在第一子有源层19-1、第二子有源层19-2、第三子有源层19-3、第四子有源层19-4上，形成相互并联的第一子晶体管T9-1、第二子晶体管T9-2、第三子晶体管T9-3、第四子晶体管T9-4。
在示例性实施方式中，第十晶体管T10的控制极210可以为条状结构，并沿第一方向X延伸，在第二方向Y上，第十晶体管T10的控制极210可以位于第九晶体管T9的控制极29与第一电容C1的第一极板C11之间，并且在远离第一电容C1的第一极板C11一侧的边缘可以为阶梯状。在示例性实施方式中，在第一方向X上，第十晶体管T10的控制极210一端与第八晶体管T8的控制极28连接，另一端与第一电容C1的第一极板C11连接。
在示例性实施方式中，第十晶体管T10的控制极210在基底上的正投影与第五子有源层110-1、第六子有源层110-2、第七子有源层110-3、第八子有源层110-4在基底上的正投影存在重叠区域。即，第十晶体管T10的控制极210跨设在第五子有源层110-1、第六子有源层110-2、第七子有源层110-3、 第八子有源层110-4上，形成相互并联的第五子晶体管T10-1、第六子晶体管T10-2、第七子晶体管T10-3、第八子晶体管T10-4。
在示例性实施方式中，在第一方向X上，第十一晶体管T11的控制极211可以位于第十晶体管T10的控制极210与第十三晶体管T13的控制极213之间，在第二方向Y上，第十一晶体管T11的控制极211可以位于第十二晶体管T12的控制极212远离第一电源线VGH1的一侧。在示例性实施方式中，第十一晶体管T11的控制极211可以呈“L”型。
在示例性实施方式中，第十二晶体管T12的控制极212可以为折线状，并沿第一方向X延伸。在示例性实施方式中，在第二方向Y上，第十二晶体管T12的控制极212的主体部分可以位于第十三晶体管T13的控制极213与第一电源线VGH1之间，在第一方向X上，第十二晶体管T12的控制极212可以位于第九晶体管T9的控制极29与第十四晶体管T14的控制极214之间。
在示例性实施方式中，第十三晶体管T13的控制极213可以呈“L”型，在第一方向X上，第十三晶体管T13的控制极213可以位于第十一晶体管T11的控制极211远离第十晶体管T10的控制极210的一侧，在第二方向Y上，第十三晶体管T13的控制极213可以位于第十四晶体管T14的控制极214远离第一电源线VGH1的一侧。
在示例性实施方式中，第十三晶体管T13的控制极213在基底的正投影与第九子有源层113-1、第十子有源层113-2、第十一子有源层113-3、第十二子有源层113-4在基底上的正投影存在重叠区域。即，第十三晶体管T13的控制极213跨设在第九子有源层113-1、第十子有源层113-2、第十一子有源层113-3、第十二子有源层113-4上，形成相互并联的第九子晶体管T13-1、第十子晶体管T13-2、第十一子晶体管T13-3、第十二子晶体管T13-4。
在示例性实施方式中，第十四晶体管T14的控制极214的形状可以为条状，并第一方向X延伸。在示例性实施方式中，在第一方向X上，第十四晶体管T14的控制极214可以位于第十二晶体管T12的控制极212与第一信号输出线EM_OUT之间，其中一端与第一信号输出线EM_OUT连接，另一端与第十二晶体管T12的控制极212连接，在第二方向Y上，第十四晶体管T14的控制极214可以位于第十三晶体管T13的控制极213与第一电源线 VGH1之间。
在示例性实施方式中，第十四晶体管T14的控制极214在基底的正投影与第十三子有源层114-1、第十四子有源层114-2、第十五子有源层114-3、第十六子有源层114-4在基底上的正投影存在重叠区域。即，第十四晶体管T14的控制极214跨设在第十三子有源层114-1、第十四子有源层114-2、第十五子有源层114-3、第十六子有源层114-4上，形成相互并联的第十三子晶体管T14-1、第十四子晶体管T14-2、第十五子晶体管T14-3、第十六子晶体管T14-4。
在示例性实施方式中，第一连接线CL1的形状可以为条状，并沿第一方向X延伸，在第一方向X上，第一连接线CL1可以位于第三晶体管T3的控制极23与第十晶体管T10的控制极210之间，一端与第三晶体管T3的控制极23连接，另一端与第十晶体管T10的控制极210和第八晶体管T8的控制极28连接；在第二方向Y上，第一连接线CL1可以位于第二晶体管T2的控制极与第二电容C2的第一极板C21之间。
在示例性实施方式中，第二连接线CL2的形状可以包括第一子连接结构CL21和第二子连接结构CL22，第一子连接结构CL21可以为“L”型，第二子连接结构CL22可以为沿第一方向X延伸的条形结构，在第一方向X上，第一子连接结构CL21可以位于第八晶体管T8的控制极28与第九晶体管T9的控制极29之间,并且在远离第八晶体管T8的控制极28一侧与第二子连接结构CL22连接，第二子连接结构CL22可以位于第八晶体管T8的控制极28与第三电容C3的第一极板C31之间，并且第二子连接结构CL22靠近第八晶体管T8的控制极28的一端与第一子连接结构CL21连接，另一端与第三电容C3的第一极板C31连接；在第二方向Y上，第一子连接结构CL21可以位于第十晶体管T10的控制极210远离一电容C1的第一极板C11的一侧，第二子连接结构CL22可以位于第九晶体管T9的控制极29远离第十晶体管T10的控制极210的一侧。
在示例性实施方式中，第三连接线CL3的形状可以为方形，在第一方向X上，第三连接线CL3可以位于第三电容C3的第一极板C31与第四晶体管T4的控制极24之间，一端与第七晶体管T7的控制极27连接，另一端与第 五晶体管T5的控制极25连接。
在示例性实施方式中，第一信号输出线EM_OUT的形状可以为条状，并沿第一方向X延伸，在第二方向Y上，第一信号输出线EM_OUT可以位于第十三晶体管T13的控制极213与第一电源线VGH1之间，并且在靠近第一电源线VGH1一侧边缘可以呈阶梯状。在第一方向X上，第一信号输出线EM_OUT可以位于第十四晶体管T14的控制极214远离第十二晶体管T12的控制极212的一侧，并且第一信号输出线EM_OUT靠近第十四晶体管T14的控制极214的一侧与第十四晶体管T14的控制极214连接。
在示例性实施方式中，第二信号输出线IEM_OUT的形状可以呈“L”型，在第二方向Y上，第二信号输出线IEM_OUT可以位于第一电源线VGH1远离第一号输出线EM_OUT的一侧，在第一方向X上，第二号输出线IEM_OUT可以位于第三电容C3的第一极板C31远离第八晶体管T8的控制极28的一侧。
在示例性实施方式中，第一电源线VGH1的形状可以为折线状，并沿第一方向X延伸，在第二方向Y上，第一电源线VGH1可以位于第一输出信号线EM_OUT与第二信号输出线IEM_OUT之间。在第一方向X上，第一子电源线VGH1可以位于第九晶体管T9的控制极29远离第八晶体管T8的控制极28的一侧。
在示例性实施方式中，第一晶体管T1至第十四晶体管T14的控制极分别跨设在第一晶体管T1至第十四晶体管T14的有源层上，即，第一晶体管T1至第十四晶体管T14的控制极在基底上的正投影分别与第一晶体管T1至第十四晶体管T14的有源层的正投影存在重叠区域。在示例性实施方式中，在平行于基底所在平面上，第一晶体管T1至第八晶体管T8、第十一晶体管T11至第十二晶体管T12的控制极的延伸方向分别与第一晶体管T1至第八晶体管T8、第十一晶体管T11至第十二晶体管T12的有源层的延伸方向垂直。
在一种示例性实施例中，本次工艺还包括导体化处理。导体化处理是在形成第一导电层图案后，利用第一晶体管T1的控制极21、第二晶体管T2的控制极22、第三晶体管T3的控制极23、第四晶体管T4的控制极24、第 五晶体管T5的控制极25、第六晶体管T6的控制极26、第七晶体管T7的控制极27、第八晶体管T8的控制极28、第九晶体管T9的控制极29、第十晶体管T10的控制极210、第十一晶体管T11的控制极211、第十二晶体管T12的控制极212、第十三晶体管T13的控制极213、第十四晶体管T14的控制极214遮挡区域的半导体层(即半导体层与各个控制极重叠的区域)作为晶体管的沟道区，未被第一导电层遮挡区域的半导体层被处理成导体化层，形成导体化的源漏电极连接部。
在示例性实施方式中，第一导电薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。
在示例性实施方式中，第一绝缘薄膜可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层可以称为第一栅绝缘层。
(103)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层的第二绝缘层，以及设置在第二绝缘层上的第二导电层图案，如图13a至图13b所示，图13a所示为形成第二导电层图案后的示意图，图13b为图13a中第二导电层的平面示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，如图13所示，第二导电层图案可以包括：第一电容C1的第二极板C12、第二电容C2的第二极板C22、第三电容C3的第二极板C32。
在示例性实施方式中，如图13所示，第二电容C2的第二极板C22、第三电容C3的第二极板C32沿第一方向X排布，在第二方向Y上第二电容C2的第二极板C22和第三电容C3的第二极板C32可以位于第一电容C1的第二极板C12的同一侧。
在示例性实施方式中，第一电容C1的第二极板C12的形状可以为折线状，并沿第一方向X延伸。在示例性实施方式中，第一电容C1的第二极板C12在基底上的正投影与第一电容C1的第一极板C11在基底上的正投影存在重叠区域。
在示例性实施方式中，如图13所示，第一电容C1的第一极板C12可以包括相互连接的第一连接部C121和第二连接部C122，第一连接部C121可以为沿第一方向X延伸的条状结构，第二连接部C122的形状可以“几”字形，并设有朝向第二电容C2的第二极板C22一侧的开口。在示例性实施方式中，第一连接部C121在基底上的正投影与第一电容C1的第一极板C11在基底上的正投影存在重叠区域，第一连接部C121和第二连接部C122沿第一方向X排列，第二连接部C122在基底上的正投影与第第一晶体管T1的控制极21在基底上的正投影不存在重叠区域。
在示例性实施方式中，第二电容C2的第二极板C22的形状可以为方形，第二电容C2的第二极板C22的边缘可以呈阶梯状。在示例性实施方式中，第二电容C2的第二极板C22在基底上的正投影与第二电容C2的第一极板C21在基底上的正投影存在重叠区域。
在示例性实施方式中，第三电容C3的第二极板C32的形状可以为条状，并沿第一方向X延伸，第三电容C3的第二极板C32靠近第一电容C1的第二极板C12一侧的边缘可以呈折线。在示例性实施方式中，第三电容C3的第二极板C32在基底上的正投影与第三电容C3的第一极板C31在基底上的正投影存在重叠区域。
在示例性实施方式中，第二导电薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。
在示例性实施方式中，第二绝缘薄膜可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层可以称为第二栅绝缘层。
(104)形成第三绝缘层图案。在示例性实施例中，形成第三绝缘层图案可以包括：在形成前述图案的基底上，沉积第三绝缘薄膜，采用图案化工艺对第三绝缘薄膜进行图案化，形成覆盖第二导电层的第三绝缘层，第三绝缘层上设置有多个过孔图案，如图14所示，图14所示为形成第三绝缘层图案后的平面结构示意图。
在示例性实施方式中，多个过孔图案可以包括：第一过孔V1至第三十三过孔V33，其中，第一过孔V1至第十四过孔V14贯穿第一绝缘层、第二绝缘层和第三绝缘层，第十五过孔V15至第三十过孔V30贯穿第二绝缘层和第三绝缘层，第三十一过孔V31至第三十三过孔V33贯穿第三绝缘层。
在示例性实施方式中，第一过孔V1暴露出第一晶体管的有源层，第二过孔V2暴露出第二晶体管的有源层，第三过孔V3暴露出第三晶体管的有源层，第四过孔V4暴露出第四晶体管的有源层，第五过孔V5暴露出第五晶体管的有源层，第六过孔V6暴露出第六晶体管的有源层，第七过孔V7暴露出第七晶体管的有源层，第八过孔V8暴露出第八晶体管的有源层，第九过孔V9暴露出第九晶体管的有源层，第十过孔V10暴露出第十晶体管的有源层，第十一过孔V11暴露出第十一晶体管的有源层，第十二过孔V12暴露出第十二晶体管的有源层，第十三过孔V13暴露出第十三晶体管的有源层，第十四过孔V14暴露出第十四晶体管的有源层，第十五过孔V15、第十六过孔V16暴露出第一晶体管T1的控制极21，第十七过孔V17暴露出第三晶体管T3的控制极23，第十八过孔V18暴露出第四晶体管T4的控制极24，第十九过孔V19至第二十过孔V20暴露出第七晶体管T7的控制极27，第二十一过孔V21暴露出十一晶体管T11的控制极211，第二十二过孔V22暴露出第十三晶体管T13的控制极213，第二十三过孔V23暴露出第十二晶体管T12的控制极212，第二十四过孔V24至第二十六过孔V26暴露出第一电源线VGH1，第二十七过孔V27暴露出第二信号输出线IEM_OUT，第二十八过孔V28暴露出第二连接线CL2，第二十九过孔V29暴露出第二电容C2的第一极板C21，第三十过孔V30暴露出第三电容C3的第一极板C31，第三十一过孔V31暴露出第二电容C2的第二极板C22，第三十二过孔V32暴露出第三电容C3的第二极板C32，第三十三过孔V33暴露出第一电容C1的第二极板C12。
在示例性实施方式中，第一过孔V1至第四过孔V4、第六过孔V6至第八过孔V8、第十一过孔V11、第十二过孔V12的数量均为两个，分别设置为暴露出晶体管的有源层的两个电极连接部，其中，其中一个第十一过孔V11和其中一个第十二过孔V12为同一过孔。
在示例性实施方式中，第五过孔V5的数量为4个，其中两个过孔暴露出第五晶体管的源电极连接部，另外两个过孔暴露出第五晶体管的漏电极连接部。
在示例性实施方式中，第九过孔V9和第十过孔V10的数量均为多个，且多个过孔阵列排布；多个第九过孔V9沿第一方向X排布形成多列过孔，沿第二方向Y排布形成两行过孔；多个第十过孔V10沿第一方向X排布形成多列过孔，沿第二方向Y排布形成两行过孔；并且，其中一行第九过孔V9和其中一行第十过孔V10为同一行过孔。
在示例性实施方式中，第十三过孔V13和第十四过孔V14的数量均为多个，且多个过孔阵列排布；多个第十三过孔V13沿第一方向X排布形成多列过孔，沿第二方向Y排布形成两行过孔；多个第十四过孔V14沿第一方向X排布形成多列过孔，沿第二方向Y排布形成两行过孔；并且，其中一行第十三过孔V13和其中一行第十四过孔V14为同一行过孔。
在示例性实施方式中，第十五过孔V15、第十七过孔V17、第十八过孔V18、第二十过孔V20至第二十三过孔V23、第二十六过孔V26、第二十七过孔V27、第二十九过孔V29至第三十三过孔V33的数量可以为一个或多个，例如，第十五过孔V15、第十六过孔V16、第十八过孔V18、第二十四过孔V24至第三十三过孔V33的数量可以均为两个，且两个过孔沿第一方向X排布。
在示例性实施方式中，第二十四过孔V24至第二十五过孔V25、第二十八过孔V28的数量可以为一个或多个，例如，第二十四过孔V24至第二十五过孔V25、第二十八过孔V28的数量可以均为两个，且两个过孔沿第二方向Y排布。
在示例性实施方式中，第十六过孔V16和第十九过孔V19的数量可以为一个。
在示例性实施方式中，第三绝缘薄膜可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层可以称为第二栅绝缘层。
(105)形成第三导电层图案。在示例性实施例中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第三绝缘层上的第三导电层，如图15a至图15b所示，图15a为形成第三导电层后的示意图，图15b为图15a中第三导电层的平面示意图。在示例性实施方式中，第三导电层可以称为源漏金属(SD)层。
在示例性实施方式中，第三导电层图案可以包括：初始信号线STV、信号输入线IN、第一时钟信号线CLK、第二时钟信号线CLKB、第三电源线VGH2、第二电源线VGL、第一晶体管T1至第十四晶体管T14的第一极和第二极、第四连接线CL4。
在示例性实施方式中，第一晶体管T1的第一极311与信号输入线IN可以为一体成型结构，第一晶体管T1的第二极312、第五晶体管T5的第二极可以为一体成型结构。第二晶体管T2的第一极321、第十晶体管T10的第一极3101、第十一晶体管T11的第一极3111、第十三晶体管T13的第一极3131、第二电源线VGL可以为一体成型结构；第二晶体管T2的第二极322、第三晶体管T3的第二极332可以为一体成型结构。第四晶体管T4的第一极341与第三电源线VGH2可以为一体成型结构，第四晶体管T4的第二极342与第五晶体管T5的第一极351可以为一体成型结构。第六晶体管T6的第二极362与第七晶体管T7的第一极371可以共用一个电极。第七晶体管T7的第二极372、第八晶体管T8的第二极可以为一体成型结构，第八晶体管T8的第一极381、第九就晶体管T9的第一极391可以为一体成型结构。第十二晶体管T12的第一极3121、第十四晶体管T14的第一极3141可以为一体成型结构。
在示例性实施方式中，第一晶体管T1的第一极311和第二极312分别通过两个第一过孔V1与第一晶体管T1的有源层11连接。第二晶体管T2的第一极321和第二极322分别通过两个第二过孔V2与第二晶体管T2的有 源层12连接。第三晶体管T3的第一极331和第二极332分别通过两个第三过孔V3与第三晶体管T3的有源层13连接。第四晶体管T4的第一极341和第二极342分别通过两个第四过孔V4与第四晶体管T4的有源层14连接。第五晶体管T5的第一极351和第二极352分别通过两个第五过孔V5与第五晶体管T5的有源层15连接。第六晶体管T6的第一极361和第二极362(也是第七晶体管T7的第一极)分别通过两个第六过孔V6与第六晶体管T6的有源层16连接。第七晶体管T7的第一极371(也是第六晶体管T6的第二极362)和第二极372分别通过两个第七过孔V7与第七晶体管T7的有源层17连接。第八晶体管T8的第一极381和第二极382分别通过两个第八过孔V8与第八晶体管T8的有源层18连接。第九晶体管T9的第一极391和第二极392(也是第十晶体管T10的第二极3102)分别通过两个第九过孔V9与第九晶体管T9的有源层19连接。第十晶体管T10的第一极3101和第二极3102(也是第九晶体管T9的第二极392)分别通过两个第十过孔V9与第十晶体管T10的有源层110连接。第十一晶体管T11的第一极3111和第二极3112(也是第十二晶体管T12的第二极3122)分别通过两个第十一过孔V11与第十一晶体管T11的有源层111连接。第十二晶体管T12的第一极3121和第二极3122(也是第十一晶体管T11的第二极3112)分别通过两个第十二过孔V12与第十二晶体管T12的有源层112连接。第十三晶体管T13的第一极3131和第二极3132(也是第十四晶体管T14的第二极3142)分别通过两个第十三过孔V13与第十三晶体管T13的有源层113连接。第十四晶体管T14的第一极3141和第二极3142(也是第十三晶体管T13的第二极3132)分别通过两个第十四过孔V14与第十四晶体管T14的有源层114连接。
在示例性实施方式中，第一时钟信号线CLK在基底上的正投影与第一晶体管T1的控制极21在基底上的正投影存在重叠区域，第一时钟信号线CLK通过第十五过孔V15与第一晶体管T1的控制极21连接；第三晶体管T3的第一极331在基底上的正投影与第二晶体管T2的控制极22在基底上的正投影存在重叠区域，第三晶体管T3的第一极331可以通过第十六过孔V16与第二晶体管T2的控制极22连接；第五晶体管T5的第二极352在基底上的正投影与第三晶体管T3的控制极23在基底上的正投影存在重叠区域，第五晶体管T5的第二极352可以通过第十七过孔V17与第三晶体管T3的控制极 23连接；第三晶体管T3的第二极332在基底上的正投影与第四晶体管T4的控制极24在基底上的正投影存在重叠区域，第三晶体管T3的第二极332可以通过第十八过孔V18与第四晶体管T4的控制极24连接；第六晶体管T6的第一极361在基底上的正投影与第七晶体管T7的控制极27在基底上的正投影存在重叠区域，第六晶体管T6的第一极361可以通过第十九过孔V19与第七晶体管T7的控制极27连接；第二时钟信号线CLKB在基底上的正投影与第七晶体管T7的控制极27在基底上的正投影存在重叠区域，第二时钟信号线CLKB可以通过第二十过孔V20与第七晶体管T7的控制极27连接；第四连接线CL4在基底上的正投影与第十一晶体管T11的控制极211在基底上的正投影存在重叠区域，第四连接线CL4可以通过第二十一过孔V2 1与第十一晶体管T11的控制极211连接；第十一晶体管T11的第二极在基底上的正投影与第十三晶体管T13的控制极213在基底上的正投影存在重叠区域，第十一晶体管T11的第二极(也是第十二晶体管T12的第二极3122)可以通过第二十二过孔V22与第十三晶体管T13的控制极213连接；第九晶体管T9的第二极392在基底上的正投影与第十二晶体管T12的控制极212在基底上的正投影存在重叠区域，第九晶体管T9的第二极392可以通过第二十三过孔V23与第十二晶体管T12的控制极212连接；第九晶体管T9的第一极391在基底上的正投影与第一电源线VGH1在基底上的正投影存在重叠区域，第九晶体管T9的第一极391可以通过第二十四过孔V24与第二导电层上的第一电源线VGH1连接；第十二晶体管T12的第一极3121在基底上的正投影与第一电源线VGH1在基底上的正投影存在重叠区域，第十二晶体管T12的第一极3121可以通过第二十五过孔V25与第二导电层上的第一电源线VGH1连接；第十四晶体管T14的第一极3141在基底上的正投影与第一电源线VGH1在基底上的正投影存在重叠区域，第十四晶体管T14的第一极3141可以通过第二十六过孔V26与第二导电层上的第一电源线VGH1连接；第十四晶体管T14的第二极3142在基底上的正投影与第二信号输出线IEM_OUT在基底上的正投影存在重叠区域，第十四晶体管T14的第二极3142(也是第十三晶体管T13的第二极3132)可以通过第二十七过孔V27与第二信号输出线IEM_OUT连接；第八晶体管T8的第二极382在基底上的正投影与第二连接线CL2在基底上的正投影存在重叠区域，第八晶体管T8的第 二极382可以通过第二十八过孔V28与第二连接线CL2连接；第三晶体管T3的第二极332在基底上的正投影与第二电容C2的第一极板C21在基底上的正投影存在重叠区域，第三晶体管T3的第二极332可以通过第二十九过孔V29与第二电容C2的第一极板C21连接；第四连接线CL4在基底上的正投影与第三电容C3的第一极板C31在基底上的正投影存在重叠区域，第四连接线CL4可以通过第三十过孔V30与第三电容C3的第一极板C31连接；第六晶体管T6的第二极362在基底上的正投影与第二电容C2的第二极板C22在基底上的正投影存在重叠区域，第六晶体管T6的第二极362(也是第七晶体管T7的第一极371)可以通过第三十一过孔V31与第二电容C2的第二极板C22连接；第九晶体管T9的第一极391在基底上的正投影与第三电容C3的第二极板C32在基底上的正投影存在重叠区域，第九晶体管T9的第一极391可以通过第三十二过孔V32与第三电容C3的第二极板C32连接；第二时钟信号线CLKB在基底上的正投影与第一电容C1的第二极板C12在基底上的正投影存在重叠区域，第二时钟信号线CLKB可以通过第三十三过孔V33与第一电容C1的第二极板C12连接。
在示例性实施方式中，在第一方向X上，初始信号线STV可以位于第二电容C2远离第三电容C3的一侧，第一时钟信号线CLK可以位于初始信号线STV靠近第二电容C2的一侧，第二时钟信号线CLKB可以位于第一时钟信号线CLK靠近第二电容C2的一侧，第三电源线VGH2可以位于第二时钟信号线CLKB靠近第二电容C2的一侧，第二电源线VGL可以位于第十四晶体管T14远离第三电容C3的一侧。
在示例性实施方式中，第一时钟信号线CLK基底上的正投影与第一晶体管T1的控制极21在基底上的正投影存在重叠区域，且通过第十五过孔V15与第一晶体管T1的控制极21连接。
在示例性实施方式中，第二时钟信号线CLKB在基底上的正投影与第一电容C1的第二极板C12、第七晶体管T7的控制极27在基底上的正投影存在重叠区域，并通过第二十过孔V20与第七晶体管T7的控制极27，通过第三十三过孔V33与第一电容C1的第二极板C12连接。
在示例性实施方式中，初始信号线STV、信号输入线IN、第一时钟信号 线CLK、第二时钟信号线CLKB、第三电源线VGH2、第二电源线VGL的形状可以为条状，并沿第二方向Y延伸。初始信号线STV、第一时钟信号线CLK、第二时钟信号线CLKB、第三电源线VGH2、第二电源线VGL沿第一方向X依次排布。
在示例性实施方式中，信号输入线IN的形状可以呈“L”型，信号输入线IN可以位于第三电源线VGH2远离第二时钟信号线CLKB的一侧，在靠近第三电源线VGH2的一端与第一晶体管T1的第一极311连接，远离第三电源线VGH2的一端可以连接上一行的信号输出线EM_OUT或者首行的初始信号线STV。
在示例性实施方式中，第一晶体管T1的第一极311可以为沿第二方向Y延伸的条状结构。第一晶体管T1的第一极311可以位于第三电源线VGH2与第一晶体管T1的第二极312之间。第一晶体管T1的第二极312可以呈“L”型，位于第一晶体管T1的第一极311与第五晶体管T5的第二极352之间，在远离第一晶体管T1的第一极311的一侧与第五晶体管T5的第二极352连接。
在示例性实施方式中，第二晶体管T2的第一极321可以为条状结构，并沿第二方向Y延伸，在第一方向X上，可以位于第二晶体管T2的第二极322与第十晶体管T10的第一极3101之间，在远离第二晶体管T2的第二极322的一侧与第十晶体管T10的第一极3101连接。第二晶体管T2的第二极322可以为沿第一方向X延伸的折线状，在第一方向X上，第二晶体管T2的第二极322可以位于第三晶体管T1的第一极311与第二晶体管T2的第一极321之间，在远离第二晶体管T2的第一极321的一端与第三晶体管T3的第二极332连接。在第二方向Y上，第二晶体管T2的第一极321和第二晶体管T2的第二极322可以位于信号输入线IN与第八晶体管T8的第二极382之间。
在示例性实施方式中，第三晶体管T3的第一极331可以为矩形结构，位于第五晶体管T5的第二极352与第三晶体管T3的第二极332之间。第三晶体管T3的第二极332可以为沿第一方向X延伸的折线状，在第一方向X上可以位于第三电源线VGH2与第三电容C3之间，在第二方向上可以位于 第一电容C1与第二电容C2之间，在靠近一电容C1的一端与第二晶体管T2的第二极322连接。
在示例性实施方式中，第四晶体管T4的第一极341可以呈“L”型，并与第三电源线VGH2连接，第四晶体管T4的第二极341可以为方形结构，并与第五晶体管T5的第一极351连接。在第二方向Y上，第四晶体管T4的第一极341和第四晶体管T4的第二极341可以位于信号输入线IN与第三晶体管T3的第二极332之间，在第一方向X上，第四晶体管T4的第一极341和第四晶体管T4的第二极342可以位于第三电源线VGH2与第五晶体管T5的第二极352之间。
在示例性实施方式中，第五晶体管T5的第一极351可以呈“J”型，第五晶体管T5的第二极352可以呈“L”型，在第二方向Y上，第五晶体管T5的第一极351和第五晶体管T5的第二极352可以位于信号输入线IN与第三晶体管T3的第二极332之间，在第一方向X上，第五晶体管T5的第一极351和第五晶体管T5的第二极352可以位于第三电源线VGH2与第三晶体管T3的第二极332之间。
在示例性实施方式中，第六晶体管T6的第一极361可以呈“L”型，并位于第三电源线VGH2与第六晶体管T6的第二极362之间，第六晶体管T6的第二极362可以为折线形，并位于第八晶体管T8的第二极382与第六晶体管T6的第一极361之间。
在示例性实施方式中，第七晶体管T7的第一极371与第六晶体管T6的第二极362共用同一个电极，可以节省布线空间。第七晶体管T7的第二极372可以呈“L”型，位于第七晶体管T7的第一极371与第八晶体管T8的第二极382之间，并与第八晶体管T8的第二极382连接。
在示例性实施方式中，第八晶体管T8的第一极381可以为沿第一方向X延伸的折线形，并位于第二电容C2与第三电容C3之间。第八晶体管T8的第二极382可以呈“n”型，在第一方向X上可以位于第二电容C2与第三电容C3之间，在第二方向Y上可以位于第三晶体管T3远离第一电容C1的一侧，并设有背离第一电容C1一侧的开口，在远离第一电容C1的一侧与第七晶体管T7的第二极372连接。
在示例性实施方式中，第九晶体管T9的第一极391可以包括相互连接的第一结构391-1和第二结构391-2，第一结构391-1的形状可以为条状，并沿第一方向X延伸，一端与第八晶体管T8的第一极381连接，另一端与第二结构391-2连接。第二结构391-2可以呈“J”型，可以位于第一结构391-1与第四连接线CL4之间，在远离第四连接线CL4的一侧与第一结构391-1连接。
在示例性实施方式中，第九晶体管T9的第二极392可以包括相互连接的第三结构392-1和第四结构392-2，第三结构392-1的形状可以为条状，并沿第一方向X延伸，位于第八晶体管T8的第二极382与第四结构392-2之间，在靠近第四结构392-2的一端与第四结构392-2连接；第四结构392-2的形状可以为条状，位于第八晶体管T8的第二极382与第四连接线CL4之间，在靠近第八晶体管T8的第二极382的一侧与第三结构392-1连接。
在示例性实施方式中，第十晶体管T10的第一极3101可以为条状结构，并沿第一方向X延伸，在第一方向X上，可以位于第二晶体管T2的第一极321与第十一晶体管T11的第一极3111之间，并且两端分别与第二晶体管T2的第一极321、第十一晶体管T11的第一极3111连接。
在示例性实施方式中，第十晶体管T10的第二极3102可以与第九晶体管T9的第二极392共用一个电极，以节省布线空间。在示例性实施方式中，在第二方向Y上，信号输入线IN、第十晶体管T10的第一极3101、第十晶体管T10的第二极3102、第九晶体管T9的第一极391可以沿第二方向Y的反方向依次排布。
在示例性实施方式中，第十一晶体管T11的第一极3111的形状可以为条状，并沿第一方向X延伸，两端分别与第十晶体管T10的第一极3101和第十三晶体管T13的第一极3131连接。第十一晶体管T11的第二极3112可以呈“L”型，并位于第十一晶体管T11的第一极3111远离信号输入线IN的一侧。
在示例性实施方式中，第十二晶体管T12的第一极3121可以呈“L”型，位于第四连接线CL4与第十四晶体管T14的第二极3142之间，并与第十四晶体管T14的第二极3142连接。第十二晶体管T12的第二极3122可以与第 十一晶体管T11的第二极3112共用一个电极，以节省布线空间。
在示例性实施方式中，第十三晶体管T13的第一极3131可以为条状结构，并沿第一方向X延伸，一端与第十一晶体管T11的第一极3111连接，另一端与第二电源线VGL连接。第十三晶体管T13的第二极3132可以包括相互连接的第五结构3132-1和第六结构3132-2。第五结构3132-1可以为条状结构，并沿第一方向X延伸，位于第十三晶体管T13的第一极3131与第十四晶体管T14的第一极3141之间。第六结构3132-2可以呈“L”型，在第一方向X上可以位于第十四晶体管T14的第一极3141与第二电源线VGL之间，在第二方向Y上可以位于第十三晶体管T13的第一极3131远离信号输入线IN的一侧，在靠近第十三晶体管T13的第一极3131的一侧与第五结构3132-1连接。
在示例性实施方式中，第十四晶体管T14的第一极3141可以呈“L”型，在第一方向X上，可以位于第十二晶体管T12的第一极3121与第二电源线VGL之间，在远离第二电源线VGL的一侧与第十二晶体管T12的第一极3121连接。在示例性实施方式中，第十四晶体管T14的第二极3142可以与第十三晶体管T13的第二极3132可以共用一个电极，以节省布线空间。
在示例性实施方式中，第四连接线CL4可以为折线结构，并沿第二方向Y延伸，在第一方向X上可以位于第九晶体管T9的第二极392与第十一晶体管T11的第二极3112之间，在第二方向Y上可以位于第十一晶体管T11的第一极3111远离信号输入线IN的一侧，在靠近第十一晶体管T11的第一极3111的一端可以通过第二十一过孔V21与第十一晶体管T11的控制极211连接，在远离第十一晶体管T11的第一极3111的一端可以通过第三十过孔V30与第三电容C3的第一极板C31连接。
在示例性实施方式中，第三导电薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。
在示例性实施方式中，另一种显示基板的制备过程可以包括如下操作。
(201)在基底上形成半导体层图案。制备方式与上述(101)相同，这 里不再赘述。
在示例性实施方式中，如图16所示，半导体层图案可以包括第一晶体管T1至第十四晶体管T14的有源层。其中，第一晶体管T1至第十四晶体管T14的有源层的形状分别与上述(101)中的第一晶体管T1至第十四晶体管T14的有源层形状相同，第一晶体管T1至第十晶体管T10的有源层的相对位置关系与上述(101)相同，第十一晶体管T11至第十四晶体管T14的有源层的相对位置关系与上述(101)相同，在此不再赘述。
半导体层图案与上述(101)形成的半导体层图案的区别在于：在第二方向Y上，第十一晶体管T11至第十四晶体管T14的有源层位于第九晶体管T9和第十晶体管T10的一侧，在第一方向X上，第十一晶体管T11和第十二晶体管T12的有源层位于第十三晶体管T13和第十四晶体管T14的有源层的一侧。例如，第十三晶体管T13和第十四晶体管T14的有源层、第九晶体管T9和第十晶体管T10沿第二方向Y排布，第十一晶体管T11和第十二晶体管T12的有源层、第十三晶体管T13和第十四晶体管T14的有源层沿第一方向X排布。在第二方向Y上，第十一晶体管T11的有源层111、第十二晶体管T12的有源层112沿第二方向Y排布，第十三晶体管T13的有源层113、第十四晶体管T14的有源层114沿第二方向Y排布。
(202)形成第一导电层图案。制备方式与上述(102)相同，这里不再赘述。
在示例性实施方式中，如图17所示，图17a所示为形成第一导电层图案后的示意图，图17b为图17a中第一导电层的平面示意图。第一导电层图案与上述(102)形成的第一导电层图案的区别在于：第十一晶体管T11至第十四晶体管T14的控制极位于第三电容C3远离第一电容C1的一侧；第十一晶体管T11的控制极211的形状为“n”型，并设有朝向第十二晶体管T12一侧的开口，靠近第三电容C3的一侧与第二连接线CL2连接，远离第三电容C3的一侧在基底上的正投影与第十一晶体管T11的有源层存在重叠区域，第十一晶体管T11的控制极211与第二连接线CL2、第九晶体管T9的控制极29、第三电容C3的第一极板C31为一体成型结构；第十二晶体管T12和第十四晶体管T14的控制极位于第十三晶体管T13的控制极与第三电容C3 之间。第一电源线VGH1呈“L”型，并位于第三电容C3远离第二电容C2的一侧。新增电源连接线VCL，电源连接线VCL位于第十三晶体管T13的控制极23远离第十四晶体管T14的控制极24的一侧，电源连接线VCL可以为“n”型，并设有背离第三电容C3一侧的开口。未设置第一电源信号输出线EM_OUT和第二电源信号输出线IEM_OUT。
(203)形成第二导电层图案。制备方式与上述(102)相同，这里不再赘述。
在示例性实施方式中，如图18a和图18b所示，图18a所示为形成第二导电层图案后的示意图，图18b为图18a中第二导电层的平面示意图。第二导电层图案与上述(103)形成的第二导电层图案的区别在于：设置第一信号输出线EM_OUT和第二信号输出线IEM_OUT，在第二方向Y上，第一信号输出线EM_OUT可以位于第一电容C1的第二极板C12与第三电容C3的第二极板C32之间，第二信号输出线IEM_OUT可以位于第三电容C3的第二极板C32远离第一电容C1的第二极板C12的一侧，在第一方向X上，第一信号输出线EM_OUT和第二信号输出线IEM_OUT可以位于第三电容C32远离第二电容C2的一侧。第一信号输出线EM_OUT和第二信号输出线IEM_OUT均可以为沿第一方向X延伸的折线结构。
(204)形成第三绝缘层图案。制备方式与上述(104)相同，这里不再赘述。
在示例性实施方式中，如图19所示，图19所示为形成第三绝缘层图案后的平面结构示意图。第三绝缘层图案与上述(104)形成的第三绝缘层图案的区别在于：在第十八过孔V18数量为一个，未设置第二十五过孔V25、第二十六过孔V26，第二十七过孔V27设置为贯穿第三绝缘层，设置第三十四过孔V34至第三十六过孔V36；第三十四过孔V34至第三十五过孔V35贯穿第二绝缘层和第三绝缘层暴露出电源连接线VCL，第三十四过孔V34的数量为多个，且多个第三十四过孔V34阵列排布；第三十五过孔V35的数量为多个，多个第三十五过孔V35阵列排布；第三十六过孔V36贯穿第三绝缘层暴露出第一信号输出线EM_OUT，第三十六过孔V36数量可以为多个，多个第三十六过孔V36可以沿第一方向X排布。
(205)形成第三导电层图案。制备方式与上述(105)相同，这里不再赘述。
在示例性实施方式中，如图20a和图20b所示，图20a为形成第三导电层图案后的示意图，图20b为图20a中第三导电层的平面示意图。第三导电层图案与上述(105)形成的第三导电层图案的区别在于：第十一晶体管T11至第十四晶体管T14的第一极和第二极位于第九晶体管T9远离第十晶体管T10的一侧，第十二晶体管T12的第一极3121和第十四晶体管T14的第一极3141位于第九晶体管T9的第一极391与第十四晶体管T14的第二极3142(也是第十三晶体管T13的第二极3132)之间，第十四晶体管T14的第二极3142位于第十四晶体管T14的第一极3141与第十三晶体管T13的第一极3131和第十一晶体管T11的第一极3111之间；第十二晶体管T12的第一极3121为沿第一方向X延伸的条状结构，一端与第三电源线VGH2连接，另一端与第十四晶体管T14的第一极3141连接；第十四晶体管T14的第一极3141为沿第一方向X延伸的条状结构，一端与第十二晶体管T12的第一极3121连接，另一端可以独立设置；第十一晶体管T11的第一极3111为沿第一方向X延伸的条状结构，靠近第十三晶体管T13的第一极3131的一端与第十三晶体管T13的第一极3131连接，远离第十三晶体管T13的第一极3131的一端可以独立设置；第十三晶体管T13的第一极3131可以包括第七结构3131-1和第八结构3131-2，第七结构3131-1可以为沿第一方向X延伸的条状结构，一端与第十一晶体管T11的第一极311连接，另一端与第八结构3131-2连接，第八结构3131-2可以为方形结构并与第七结构3131-1一体成型，第八结构3131-2在基底上的正投影与电源连接线VCL在基底上的正投影存在重叠区域，并通过第三十四过孔V34与第一电源线VCL连接；第十三晶体管T13的第二极3132(也是第十四晶体管T14的第二极3142)可以为沿第一方向X延伸的条状结构。第九晶体管T9的第一极391还包括第九结构392-3，第九结构392-3可以为沿第一方向X延伸的条状结构，与第四结构392-2远离第二电源线VGL的一侧连接，在第二方向Y上，第九结构392-3可以位于第十三晶体管T13的第二极3132远离第十三晶体管T13的第一极3131的一侧，第九结构392-3在基底上的正投影与第十四晶体管T14的控制极214在基底上的正投影存在重叠区域，并可以通过第二十二过孔 V22与第十四晶体管T14的控制极214连接；第九晶体管T9的第二极392中的第四结构392-2在基底上的正投影与第一信号输出线EM_OUT在基底上的正投影存在重叠区域，并可以通过第三十六过孔V36与第一信号输出线EM_OUT连接。第二电源线VGL在基底上的正投影与电源连接线VCL在基底上的正投影存在重叠区域，并可以通过第三十五过孔V35与电源连接线VCL连接。
本公开还提供了一种显示装置，包括显示基板。显示基板为上述任一实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
在示例性实施方式中，显示装置可以为液晶显示装置(Liquid Crystal Display，简称LCD)或有机发光二极管(Organic Light Emitting Diode，简称OLED)显示装置。该显示装置可以为：液晶面板、电子纸、OLED面板、有源矩阵有机发光二极管(active-matrix organic light emitting diode，简称AMOLED)面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例还提供一种移位寄存器的驱动方法，设置为驱动上述任一实施例的移位寄存器，所述方法可以包括：
在第一时钟信号端、第二时钟信号端、第二节点和第一电源端的控制下，第一控制子电路向第一节点提供信号输入端的信号，并维持第一节点的电位；
在第一时钟信号端和第一节点的控制下，第二控制子电路向第二节点提供第二电源端或者第一时钟信号端的信号；
在第二时钟信号端、第一节点、第二节点的控制下，第三控制子电路向第四节点提供第二时钟信号端或者第一电源端的信号，并维持第四节点的电位；
在第一节点和第四节点的控制下，第一输出子电路向第一信号输出端提供第一电源端或者第二电源端的信号；
在第三控制子电路和第一信号输出端的控制下，第二输出子电路向第二信号输出端提供第一电源端或者第二电源端的信号。
本公开实施例提供的移位寄存器及其驱动方法、显示基板、显示装置， 移位寄存器包括第一控制子电路、第二控制子电路、第三控制子电路、第一输出子电路、第二输出子电路，第一输出子电路可以在第一节点和第四节点的控制下向第一信号输出端提供第一电源端或者第二电源端的信号；第二输出子电路可以在第三控制子电路和第一信号输出端的控制下向第二信号输出端提供第一电源端或者第二电源端的信号，由第一子输出电路和第二子输出电路分别向第一信号输出端和第二信号输出端输出信号，可以满足对于不同信号的需求，克服了无法满足实际应用中对不同信号需求的问题。
本公开实施例附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
在不冲突的情况下，本公开实施例即实施例中的特征可以相互组合以得到新的实施例。
虽然本公开实施例所揭露的实施方式如上，但的内容仅为便于理解本公开实施例而采用的实施方式，并非用以限定本公开实施例。任何本公开实施例所属领域内的技术人员，在不脱离本公开实施例所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开实施例的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (29)

  1. 一种移位寄存器，包括第一控制子电路、第二控制子电路、第三控制子电路、第一输出子电路、第二输出子电路；
    所述第一控制子电路，分别与信号输入端、第一节点、第二节点、第一时钟信号端、第二时钟信号端和第一电源端连接，设置为在所述第一时钟信号端、所述第二时钟信号端、所述第二节点和所述第一电源端的控制下向所述第一节点提供所述信号输入端的信号，并维持所述第一节点的电位；
    所述第二控制子电路，分别与第二电源端、所述第一时钟信号端、所述第一节点和第二节点连接，设置为在所述第一时钟信号端和所述第一节点的控制下，向所述第二节点提供所述第二电源端或者所述第一时钟信号端的信号；
    所述第三控制子电路，分别与所述第一节点、所述第二节点、第四节点、所述第二时钟信号端和所述第一电源端连接，设置为在所述第二时钟信号端、所述第一节点、所述第二节点的控制下，向所述第四节点提供所述第二时钟信号端或者所述第一电源端的信号，并维持所述第四节点的电位；
    所述第一输出子电路，分别与所述第一电源端、所述第二电源端、所述第一节点、所述第四节点和第一信号输出端连接，设置为在所述第一节点和所述第四节点的控制下向所述第一信号输端出提供所述第一电源端或者所述第二电源端的信号；
    所述第二输出子电路，分别与所述第一信号输出端、所述第三控制子电路、所述第一电源端、所述第二电源端和第二信号输出端连接，设置为在所述第三控制子电路和所述第一信号输出端的控制下，向所述第二信号输出端提供所述第一电源端或者所述第二电源端的信号。
  2. 根据权利要求1所述的移位寄存器，其中，所述第一控制子电路包括第一晶体管、第四晶体管、第五晶体管和第一电容，所述第一电容包括第一极板和第二极板；
    所述第一晶体管的控制极与所述第一时钟信号端连接，所述第一晶体管的第一极与所述信号输入端连接，所述第一晶体管的第二极与所述第一节点 连接；
    所述第四晶体管的控制极与所述第二节点连接，所述第四晶体管的第一极与所述第一电源端连接，所述第四晶体管的第二极与第七节点连接；
    所述第五晶体管的控制极与所述第二时钟信号端连接，所述第五晶体管的第一极与所述第七节点连接，所述第五晶体管的第二极与所述第一节点连接；
    所述第一电容的第一极板与所述第一节点连接，所述第一电容的第二极板与所述第二时钟信号端连接。
  3. 根据权利要求1所述的移位寄存器，其中，所述第一控制子电路包括第一晶体管、第四晶体管、第五晶体管、第一电容和第四电容，所述第一电容包括第一极板和第二极板，所述第四电容包括第一极板和第二极板；
    所述第一晶体管的控制极与所述第一时钟信号端连接，所述第一晶体管的第一极与所述信号输入端连接，所述第一晶体管的第二极与所述第一节点连接；
    所述第四晶体管的控制极与所述第二节点连接，所述第四晶体管的第一极与所述第一电源端连接，所述第四晶体管的第二极与第七节点连接；
    所述第五晶体管的控制极与所述第一节点连接，所述第五晶体管的第一极与所述第二时钟信号端连接，所述第五晶体管的第二极与所述第七节点连接；
    所述第一电容的第一极板与所述第一节点连接，所述第一电容的第二极板与所述第一信号输出端连接；
    所述第四电容的第一极板与所述第七节点连接，所述第四电容的第二极板与所述第一节点连接。
  4. 根据权利要求1所述的移位寄存器，其中，所述第二控制子电路包括第二晶体管和第三晶体管；
    所述第二晶体管的控制极与所述第一时钟信号端连接，所述第二晶体管的第一极与所述第二电源端连接，所述第二晶体管的第二极与所述第二节点连接；
    所述第三晶体管的控制极与所述第一节点连接，所述第三晶体管的第一极与所述第一时钟信号端连接，所述第三晶体管的第二极与所述第二节点连接。
  5. 根据权利要求1所述的移位寄存器，其中，所述第三控制子电路包括第六晶体管、第七晶体管、第八晶体管、第二电容和第三电容；
    所述第六晶体管的控制极与所述第二节点连接，所述第六晶体管的第一极与所述第二时钟信号端连接，所述第六晶体管的第二极与第三节点连接；
    所述第七晶体管的控制极与所述第二时钟信号端连接，所述第七晶体管的第一极与所述第三节点连接，所述第七晶体管的第二极与所述第四节点连接；
    所述第八晶体管的控制极与所述第一节点连接，所述第八晶体管的第一极与所述第一电源端连接，所述第八晶体管的第二极与所述第四节点连接；
    所述第二电容的第一极板与所述第二节点连接，所述第二电容的第二极板与所述第三节点连接；
    所述第三电容的第一极板与所述第四节点连接，所述第三电容的第二极板与所述第一电源端连接。
  6. 根据权利要求1所述的移位寄存器，其中，所述第一输出子电路包括第九晶体管和第十晶体管；
    所述第九晶体管的控制极与所述第四节点连接，所述第九晶体管的第一极与所述第一电源端连接，所述第九晶体管的第二极与所述第一信号输出端连接；
    所述第十晶体管的控制极与所述第一节点连接，所述第十晶体管的第一极与所述第二电源端连接，所述第十晶体管的第二极与所述第一信号输出端连接。
  7. 根据权利要求1所述的移位寄存器，其中，所述第二输出子电路包括第十一晶体管、第十二晶体管、第十三晶体管和第十四晶体管；
    所述第十一晶体管的控制极与所述第三控制子电路连接，所述第十一晶体管的第一极与所述第二电源端连接，所述第十一晶体管的第二极与第六节 点连接；
    所述第十二晶体管的控制极与所述第一信号输出端连接，所述第十二晶体管的第一极与所述第一电源端连接，所述第十二晶体管的第二极与所述第六节点连接；
    所述第十三晶体管的控制极与所述第六节点连接，所述第十三晶体管的第一极与所述第二电源端连接，所述第十三晶体管的第二极与所述第二信号输出端连接；
    所述第十四晶体管的控制极与所述第一信号输出端连接，所述第十四晶体管的第一极与所述第一电源端连接，所述第十四晶体管的第二极与所述第二信号输出端连接。
  8. 根据权利要求7所述的移位寄存器，其中，所述第二输出子电路还包括第五电容，所述第五电容包括第一极板和第二极板；
    所述第五电容的第一极板与所述第六节点连接，所述第五电容的第二极板与所述第一时钟信号端或者所述第二时钟信号端连接。
  9. 根据权利要求1所述的移位寄存器，其中，所述第一控制子电路包括第一晶体管、第四晶体管、第五晶体管和第一电容，所述第一电容包括第一极板和第二极板；所述第二控制子电路包括第二晶体管和第三晶体管；所述第三控制子电路包括第六晶体管、第七晶体管、第八晶体管、第二电容和第三电容；所述第一输出子电路包括第九晶体管和第十晶体管；所述第二输出子电路包括第十一晶体管、第十二晶体管、第十三晶体管和第十四晶体管；
    所述第一晶体管的控制极与所述第一时钟信号端连接，所述第一晶体管的第一极与所述信号输入端连接，所述第一晶体管的第二极与所述第一节点连接；
    所述第二晶体管的控制极与所述第一时钟信号端连接，所述第二晶体管的第一极与所述第二电源端连接，所述第二晶体管的第二极与所述第二节点连接；
    所述第三晶体管的控制极与所述第一节点连接，所述第三晶体管的第一极与所述第一时钟信号端连接，所述第三晶体管的第二极与所述第二节点连 接；
    所述第四晶体管的控制极与所述第二节点连接，所述第四晶体管的第一极与所述第一电源端连接，所述第四晶体管的第二极与第七节点连接；
    所述第五晶体管的控制极与所述第二时钟信号端连接，所述第五晶体管的第一极与所述第七节点连接，所述第五晶体管的第二极与所述第一节点连接；
    所述第六晶体管的控制极与所述第二节点连接，所述第六晶体管的第一极与所述第二时钟信号端连接，所述第六晶体管的第二极与第三节点连接；
    所述第七晶体管的控制极与所述第二时钟信号端连接，所述第七晶体管的第一极与所述第三节点连接，所述第七晶体管的第二极与所述第四节点连接；
    所述第八晶体管的控制极与所述第一节点连接，所述第八晶体管的第一极与所述第一电源端连接，所述第八晶体管的第二极与所述第四节点连接；
    所述第九晶体管的控制极与所述第四节点连接，所述第九晶体管的第一极与所述第一电源端连接，所述第九晶体管的第二极与所述第一信号输出端连接；
    所述第十晶体管的控制极与所述第一节点连接，所述第十晶体管的第一极与所述第二电源端连接，所述第十晶体管的第二极与所述第一信号输出端连接；
    所述第十一晶体管的控制极与所述第三节点或者所述第四节点连接，所述第十一晶体管的第一极与所述第二电源端连接，所述第十一晶体管的第二极与第六节点连接；
    所述第十二晶体管的控制极与所述第一信号输出端连接，所述第十二晶体管的第一极与所述第一电源端连接，所述第十二晶体管的第二极与所述第六节点连接；
    所述第十三晶体管的控制极与所述第六节点连接，所述第十三晶体管的第一极与所述第二电源端连接，所述第十三晶体管的第二极与所述第二信号输出端连接；
    所述第十四晶体管的控制极与所述第一信号输出端连接，所述第十四晶体管的第一极与所述第一电源端连接，所述第十四晶体管的第二极与所述第二信号输出端连接；
    所述第一电容的第一极板与所述第一节点连接，所述第一电容的第二极板与所述第二时钟信号端连接；
    所述第二电容的第一极板与所述第二节点连接，所述第二电容的第二极板与所述第三节点连接；
    所述第三电容的第一极板与所述第四节点连接，所述第三电容的第二极板与所述第一电源端连接。
  10. 根据权利要求9所述的移位寄存器，其中，所述第一晶体管至第十四晶体管为P型晶体管。
  11. 根据权利要求1至10任一项所述的移位寄存器，其中，所述第一信号输出端输出的信号与所述第二信号输出端输出的信号为互为反相信号。
  12. 一种显示基板，包括基底以及设置在所述基底上的电路结构层，所述电路结构层包括发光驱动电路，所述发光驱动电路包括多个级联的移位寄存器；
    第i级移位寄存器的第一信号输出端与第i+1级移位寄存器的信号输入端电连接，1≤i≤M-1，M为移位寄存器的总级数；
    至少一个移位寄存器包括：第一控制子电路、第二控制子电路、第三控制子电路、第一输出子电路、第二输出子电路；
    所述第一控制子电路，分别与信号输入端、第一节点、第二节点、第一时钟信号端、第二时钟信号端和第一电源端连接，设置为在所述第一时钟信号端、所述第二时钟信号端、所述第二节点和所述第一电源端的控制下向所述第一节点提供所述信号输入端的信号，并维持所述第一节点的电位；
    所述第二控制子电路，分别与第二电源端、所述第一时钟信号端、所述第一节点和第二节点连接，设置为在所述第一时钟信号端和所述第一节点的控制下，向所述第二节点提供所述第二电源端或者所述第一时钟信号端的信号；
    所述第三控制子电路，分别与所述第一节点、所述第二节点、第四节点、所述第二时钟信号端和所述第一电源端连接，设置为在所述第二时钟信号端、所述第一节点、所述第二节点的控制下，向所述第四节点提供所述第二时钟信号端或者所述第一电源端的信号，并维持所述第四节点的电位；
    所述第一输出子电路，分别与所述第一电源端、所述第二电源端、所述第一节点、所述第四节点和第一信号输出端连接，设置为在所述第一节点和所述第四节点的控制下向所述第一信号输出端提供所述第一电源端或者所述第二电源端的信号；
    所述第二输出子电路，分别与所述第一信号输出端、所述第三控制子电路、所述第一电源端、所述第二电源端和第二信号输出端连接，设置为在所述第三控制子电路和所述第一信号输出端的控制下，向所述第二信号输出端提供所述第一电源端或者所述第二电源端的信号。
  13. 根据权利要求12所述的显示基板，还包括：沿第二方向延伸的初始信号线、第一时钟信号线、第二时钟信号线、第二电源线和第三电源线，初始信号线、第一时钟信号线、第二时钟信号线、第三电源线和第二电源线沿第一方向排布，所述第一方向与所述第二方向相交；
    第一级移位寄存器的信号输入端与初始信号线电连接，所有移位寄存器的第一电源端与第三电源线电连接，所有移位寄存器的第二电源端与第二电源线电连接，奇数级移位寄存器的第一时钟信号端与第一时钟信号线连接，奇数级移位寄存器的第二时钟信号端与第二时钟信号线连接，偶数级移位寄存器的第一时钟信号端与第二时钟信号线连接，偶数级移位寄存器的第二时钟信号端与第一时钟信号线连接。
  14. 根据权利要求13所述的显示基板，其中，所述电路结构层包括：依次叠设在基底上的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层和第三导电层；
    所述半导体层包括：位于发光驱动电路的所有晶体管的有源层；
    所述第一导电层包括：位于发光驱动电路的所有晶体管的控制极以及第一电容的第一极板至第三电容的第一极板；
    所述第二导电层包括：位于发光驱动电路的第一电容的第二极板至第三电容的第二极板；
    所述第三导电层包括：初始信号线、第一时钟信号线、第二时钟信号线、第一电源线、第二电源线。
  15. 根据权利要求14所述的显示基板，其中，所述移位寄存器包括：第一晶体管至第十四晶体管；
    在所述显示基板所在平面内，在第一方向上，所有晶体管以及电容均位于第三电源线与第二电源线之间，第二电容位于第三电源线与第八晶体管之间，第八晶体管位于第二电容与第九晶体管和第十晶体管之间，第九晶体管和第十晶体管位于第八晶体管与第十一晶体管和第十二晶体管之间，所述第十一晶体管和所述第十二晶体管位于所述第九晶体管和所述第十晶体管与所述第十三晶体管和第十四晶体管之间，第十三晶体管和第十四晶体管位于第十一晶体管和第十二晶体管与第二电源线之间；在第二方向上，第三电容、第九晶体管、第十晶体管、第一电容沿第二方向依次排布，第十二晶体管、第十一晶体管沿第二方向依次排布，第十四晶体管、第十三晶体管沿第二方向依次排布。
  16. 根据权利要求15所述的显示基板，其中，所述第一导电层还包括第一电源线，所述第一电源线与所述第一电源端连接；所述第一电源线为折线状，并沿第一方向延伸；
    在平行于所述显示基板的平面上，在第一方向上，所述第一电源线位于第三电容远离第八晶体管的控制极的一侧；在第二方向上，所述第一电源线位于第十四晶体管的控制极远离第十三晶体管的控制极的一侧。
  17. 根据权利要求16所述的显示基板，其中，所述第一导电层还包括第一信号输出线和第二信号输出线；所述第一信号输出线的形状为条状并沿第一方向延伸，所述第二信号输出线的形状呈“L”型；
    在所述第一导电层所在平面内，在第二方向上，所述第一信号输出线位于第十三晶体管的控制极与所述第一电源线之间，第一信号输出线与第十四晶体管的控制极为一体成型结构，第二信号输出线位于所述第一电源线远离 所述第一信号输出线的一侧；在第一方向上，所述第一信号输出线位于第十四晶体管的控制极远离第十二晶体管的控制极的一侧，第二信号输出线位于第三电容的第一极板远离第八晶体管的控制极的一侧。
  18. 根据权利要求17所述的显示基板，其中，所述第一导电层还包括第二连接线，所述第二连接线、所述第三电容的第一极板、所述第九晶体管的控制极为一体成型结构，所述第十一晶体管的控制极形状呈“L”型；
    所述第三导电层还包括第四连接线、第一晶体管至第十四晶体管的第一极和第二极，所述第四连接线的形状为折线状，并沿第二方向延伸，所述第四连接线在所述基底上的正投影分别与所述第十一晶体管的控制极和所述第三电容的第一极板在所述基底上的正投影至少部分重叠；
    所述第九晶体管的第二极包括相互连接的第三结构和第四结构，所述第三结构的形状为条状，并沿第一方向延伸，位于所述第八晶体管的第二极与所述第四连接线之间，在靠近所述第四连接线的一端与所述第四结构连接；所述第四结构的形状为条状，并沿第二方向延伸，靠近所述第三结构的一端与第三结构连接。
  19. 根据权利要求14所述的显示基板，其中，所述移位寄存器包括：第一晶体管至第十四晶体管；
    在所述显示基板所在平面内，在第一方向上，所有晶体管以及电容均位于第三电源线与第二电源线之间，第二电容位于第三电源线与第八晶体管之间，第八晶体管位于第二电容与第九晶体管和第十晶体管之间，第九晶体管和第十晶体管位于第八晶体管与第二电源线之间，第十一晶体管和第十二晶体管位于第三电源线与第十三晶体管和第十四晶体管之间，第十三晶体管和第十四晶体管位于第十一晶体管和第十二晶体管与第二电源线之间；在第二方向上，第十三晶体管、第十四晶体管、第三电容、第九晶体管、第十晶体管、第一电容沿第二方向依次排布。
  20. 根据权利要求19所述的显示基板，其中，所述第一导电层还包括第一电源线，所述第一电源线与所述第一电源端连接；所述第一电源线呈“L”型；
    在所述第一导电层所在平面内，在第一方向上，所述第一电源线位于第三电容的第一极板远离第二电容的第一极板的一侧；在第二方向上，所述第一电源线位于第十四晶体管的控制极与第一电容的第一极板之间。
  21. 根据权利要求20所述的显示基板，其中，所述第一导电层还包括电源连接线，所述第二导电层还包括第一信号输出线、第二信号输出线；所述第一信号输出线和所述第二信号输出线的形状均为沿第一方向延伸的折线状；
    在所述第二导电层所在平面内，在第二方向上，所述第一信号输出线位于第一电容的第二极板与第三电容的第二极板之间，第二信号输出线位于所述第三电容的第二极板远离第一电容的第二极板的一侧；在第一方向上，所述第一信号输出线和所述第二信号输出线均位于第三电容的第二极板远离第二电容的第二极板的一侧；
    所述电源连接线为“n”型，在第二方向上，位于第十三晶体管的控制极远离第十四晶体管的控制极的一侧，并设有背离第十三晶体管一侧的开口，所述电源连接线在基底上的正投影分别与所述第二电源线和所述第十三晶体管的第一极在基底上的正投影至少部分重叠。
  22. 根据权利要求20所述的显示基板，其中，所述第一导电层还包括第二连接线，所述第二连接线与所述第三电容的第一极板、所述第九晶体管的控制极、所述第十一晶体管的控制极一体成型，所述第十一晶体管的控制极形状呈“n”型，并设有朝向第十二晶体管一侧的开口；
    所述第三导电层还包括第一晶体管至第十四晶体管的第一极和第二极，所述第九晶体管的第二极包括相互连接的第三结构、第四结构和第九结构，所述第三结构的形状为条状，并沿第一方向延伸，位于所述第八晶体管的第二极与所述第二电源线之间，在靠近所述第二电源线的一端与所述第四结构连接；所述第四结构的形状为条状，位于第二电源线靠近第三电源线的一侧，并沿第二方向延伸，靠近所述第三结构的一端与第三结构连接；所述第九结构的形状为条状，位于第四结构远离第二电源线的一侧，所述第四结构在基底上的正投影与所述第四晶体管的控制极在基底上的正投影至少部分重叠。
  23. 根据权利要求15至22任一项所述的显示基板，其中，所述第三导 电层还包括信号输入线，所述信号输入线为折线状，并沿第一方向延伸，在所述第三导电层所在平面内，在第一方向上，所述信号输入线位于第三电源线与所述第二电源线之间；在第二方向上，所述信号输入线位于第十晶体管远离第九晶体管的一侧；
    在所述第二导电层所在平面内，所述第二电容的第二极板、所述第三电容的第一极板沿第一方向排布，在第二方向上，所述第二电容的第二极板和所述第三电容的第二极板位于第一电容的第二极板的同一侧；
    所述第一电容的第二极板的形状为折线状，并沿第一方向延伸，第一电容的第二极板在基底上的正投影与第一电容的第一极板在基底上的正投影存在重叠区域；第二电容的第二极板的形状为方形，第二电容的第二极板在基底上的正投影与第二电容的第一极板在基底上的正投影存在重叠区域；所述第三电容的第二极板的形状可以为条状，并沿第一方向延伸，第三电容的第二极板在基底上的正投影与第三电容的第一极板在基底上的正投影存在重叠区域。
  24. 根据权利要求15至22任一项所述的显示基板，其中，所述第九晶体管、所述第十晶体管、所述第十三晶体管和所述第十四晶体管中的任意一个晶体管包括四个相互并联的子晶体管，并且在任意一个晶体管中，四个子晶体管的有源层相互独立设置，四个子晶体管的控制极为一体成型结构，四个子晶体管的第一极为一体成型结构，四个子晶体管的第二极为一体成型结构。
  25. 根据权利要求15至22任一项所述的显示基板，其中，在所述显示基板所在平面内，在第一方向上，所述第一晶体管、所述第四晶体管至所述第七晶体管位于所述第三电源线与所述第二电容之间，所述第二晶体管和所述第三晶体管位于所述第五晶体管与所述第一电容之间。
  26. 根据权利要求15至22任一项所述的显示基板，其中，所述第三导电层包括第一晶体管至第十四晶体管的第一极和第二极，所述第六晶体管的第二极和所述第七晶体管的第一极共用一个电极，所述第九晶体管的第二极和所述第十晶体管的第二极共用一个电极，所述第十三晶体管第二极和所述第十四晶体管的第二极共用一个电极。
  27. 根据权利要求16至18、20至22任一项所述的显示基板，其中，所述第一电源线和所述第二电源线提供相同的电源信号。
  28. 一种显示装置，包括如权利要求12至27任一项所述的显示基板。
  29. 一种移位寄存器的驱动方法，设置为驱动如权利要求1至11任一项所述的移位寄存器，所述方法包括：
    在第一时钟信号端、第二时钟信号端、第二节点和第一电源端的控制下，第一控制子电路向第一节点提供信号输入端的信号，并维持第一节点的电位；
    在第一时钟信号端和第一节点的控制下，第二控制子电路向第二节点提供第二电源端或者第一时钟信号端的信号；
    在第二时钟信号端、第一节点、第二节点的控制下，第三控制子电路向第四节点提供第二时钟信号端或者第一电源端的信号，并维持第四节点的电位；
    在第一节点和第四节点的控制下，第一输出子电路向第一信号输出端提供第一电源端或者第二电源端的信号；
    在第三控制子电路和第一信号输出端的控制下，第二输出子电路向第二信号输出端提供第一电源端或者第二电源端的信号。
PCT/CN2022/114317 2022-08-23 2022-08-23 移位寄存器及其驱动方法、显示基板、显示装置 WO2024040442A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2022/114317 WO2024040442A1 (zh) 2022-08-23 2022-08-23 移位寄存器及其驱动方法、显示基板、显示装置
CN202280002802.9A CN117940984A (zh) 2022-08-23 2022-08-23 移位寄存器及其驱动方法、显示基板、显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/114317 WO2024040442A1 (zh) 2022-08-23 2022-08-23 移位寄存器及其驱动方法、显示基板、显示装置

Publications (1)

Publication Number Publication Date
WO2024040442A1 true WO2024040442A1 (zh) 2024-02-29

Family

ID=90012171

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/114317 WO2024040442A1 (zh) 2022-08-23 2022-08-23 移位寄存器及其驱动方法、显示基板、显示装置

Country Status (2)

Country Link
CN (1) CN117940984A (zh)
WO (1) WO2024040442A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110292007A1 (en) * 2009-04-08 2011-12-01 Sharp Kabushiki Kaisha Shift register, display device provided with same, and method of driving shift register
CN105304013A (zh) * 2015-06-30 2016-02-03 上海天马有机发光显示技术有限公司 移位寄存器、移位寄存电路和显示装置
CN111540313A (zh) * 2020-05-11 2020-08-14 京东方科技集团股份有限公司 移位寄存器及驱动方法、驱动电路、显示基板和装置
CN214541584U (zh) * 2021-02-01 2021-10-29 京东方科技集团股份有限公司 移位寄存器单元、扫描驱动电路、显示基板和显示装置
CN113920924A (zh) * 2021-10-19 2022-01-11 京东方科技集团股份有限公司 显示基板及其驱动方法、显示装置
CN114299884A (zh) * 2022-01-10 2022-04-08 合肥京东方卓印科技有限公司 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN114333706A (zh) * 2022-01-10 2022-04-12 合肥京东方卓印科技有限公司 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110292007A1 (en) * 2009-04-08 2011-12-01 Sharp Kabushiki Kaisha Shift register, display device provided with same, and method of driving shift register
CN105304013A (zh) * 2015-06-30 2016-02-03 上海天马有机发光显示技术有限公司 移位寄存器、移位寄存电路和显示装置
CN111540313A (zh) * 2020-05-11 2020-08-14 京东方科技集团股份有限公司 移位寄存器及驱动方法、驱动电路、显示基板和装置
CN214541584U (zh) * 2021-02-01 2021-10-29 京东方科技集团股份有限公司 移位寄存器单元、扫描驱动电路、显示基板和显示装置
CN113920924A (zh) * 2021-10-19 2022-01-11 京东方科技集团股份有限公司 显示基板及其驱动方法、显示装置
CN114299884A (zh) * 2022-01-10 2022-04-08 合肥京东方卓印科技有限公司 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN114333706A (zh) * 2022-01-10 2022-04-12 合肥京东方卓印科技有限公司 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置

Also Published As

Publication number Publication date
CN117940984A (zh) 2024-04-26

Similar Documents

Publication Publication Date Title
EP4152307A1 (en) Display substrate and preparation method therefor, and display apparatus
WO2023241490A1 (zh) 显示基板和显示装置
WO2023221762A1 (zh) 显示基板及其驱动方法和制备方法、显示装置
CN113920924B (zh) 显示基板及其驱动方法、显示装置
CN113555404A (zh) 显示基板及其制备方法、显示装置
US20240081115A1 (en) Display substrate, manufacturing method thereof, and display device
WO2024040442A1 (zh) 移位寄存器及其驱动方法、显示基板、显示装置
WO2022227085A1 (zh) 显示基板及其制作方法、显示装置
WO2023004763A1 (zh) 显示基板及其制备方法、显示装置
WO2022227005A1 (zh) 显示基板及其制备方法、显示装置
WO2023206409A1 (zh) 显示基板和显示装置
WO2024031315A1 (zh) 显示基板及其制备方法、显示装置
WO2022227478A1 (zh) 一种显示基板及其制作方法、显示装置
WO2024020867A1 (zh) 显示基板及其工作方法、显示装置
WO2023178612A1 (zh) 显示基板及其制备方法、显示装置
WO2024050839A1 (zh) 显示基板、显示装置
WO2024065388A1 (zh) 像素电路及其驱动方法、显示基板和显示装置
WO2024036629A1 (zh) 显示基板及其驱动方法、显示装置
WO2023245438A1 (zh) 显示基板和显示装置
WO2023206462A1 (zh) 显示基板及其制备方法、显示装置
WO2024031240A1 (zh) 显示基板及其制备方法、显示装置
WO2023230912A1 (zh) 显示基板及其制备方法、显示装置
WO2023142110A1 (zh) 显示基板和显示装置
WO2024065629A1 (zh) 显示基板及其制备方法、显示装置
WO2024036574A1 (zh) 显示基板及其制备方法、显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202280002802.9

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22955991

Country of ref document: EP

Kind code of ref document: A1