WO2024082964A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2024082964A1
WO2024082964A1 PCT/CN2023/123204 CN2023123204W WO2024082964A1 WO 2024082964 A1 WO2024082964 A1 WO 2024082964A1 CN 2023123204 W CN2023123204 W CN 2023123204W WO 2024082964 A1 WO2024082964 A1 WO 2024082964A1
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line
transistor
sub
electrode
switch unit
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PCT/CN2023/123204
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English (en)
French (fr)
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WO2024082964A9 (zh
Inventor
温为舒
李祥艺
张润鑫
翁鸿韬
汪锐
刘一帆
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2024082964A1 publication Critical patent/WO2024082964A1/zh
Publication of WO2024082964A9 publication Critical patent/WO2024082964A9/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

Definitions

  • the present disclosure relates to but is not limited to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT thin film transistors
  • an exemplary embodiment of the present disclosure provides a display substrate, comprising a display area and a binding area located at one side of the display area, wherein the display area at least comprises a plurality of sub-pixels constituting a plurality of pixel columns and a plurality of data signal lines, and the binding area at least comprises a detection circuit; the plurality of pixel columns at least comprises a first pixel column and a second pixel column, the first pixel column comprises a plurality of first sub-pixels emitting a first color light, the second pixel column comprises a plurality of second sub-pixels emitting a second color light and a plurality of third sub-pixels emitting a third color light; the plurality of data signal lines at least comprises a first data signal line and a second data signal line, the first data signal line is electrically connected to a plurality of first sub-pixels in the first pixel column, and the second data signal line is electrically connected to a plurality of second sub-pixels and a third sub
  • an extension length of the first transmission line is smaller than an extension length of the second transmission line.
  • the first sub-pixel includes a green sub-pixel emitting green light
  • the second sub-pixel includes a blue sub-pixel emitting blue light
  • the third sub-pixel includes a red sub-pixel emitting red light.
  • the detection circuit also includes a first control line and a first detection line; the first control line is connected to the control end of the first switch unit, the first detection line is connected to the input end of the first switch unit, the output end of the first switch unit is connected to the first transmission line, and the first switch unit is configured to send the signal transmitted by the first detection line to the first data signal line through the first transmission line under the control of the first control line.
  • the first switch unit includes at least one first transistor, the first control line is connected to a gate electrode of the first transistor, the first detection line is connected to a first electrode of the first transistor, and a second electrode of the first transistor is connected to the first transmission line.
  • the first transmission line is disposed on a side of the gate electrode of the first transistor close to the display area
  • the first detection line is disposed on a side of the gate electrode of the first transistor away from the display area
  • the first control line is disposed on a side of the first detection line away from the display area.
  • the first switch unit further includes a first gate connection line, a first end of the first gate connection line is connected to the gate electrode of the first transistor, and a second end of the first gate connection line is connected to the first control line through a via after extending in a direction away from the display area.
  • the first switch unit further includes a first connection electrode, a first end of the first connection electrode is connected to the first electrode of the first transistor through a via hole, and a second end of the first connection electrode is connected to the first transmission line through a via hole.
  • the detection circuit further includes a second control line, a third control line, a second detection line and a third detection line;
  • the second control line is respectively connected to the control end of the second switch unit in the odd detection unit and the control end of the third switch unit in the even detection unit, and the third control line is respectively connected to the control end of the third switch unit in the odd detection unit and the control end of the second switch unit in the even detection unit;
  • the second detection line is connected to the input end of the second switch unit, and the third detection line is connected to the input end of the third switch unit;
  • the output end of the second switch unit is connected to the second transmission line, and the output end of the third switch unit is connected to the second transmission line;
  • the second switch unit is configured to, under the control of the second control line and the third control line, send the signal transmitted by the second detection line to the second data signal line through the second transmission line, and
  • the third switch unit is configured to, under the control of the second control line and the third control line, send the signal transmitted by the third detection line to
  • the second switching unit includes at least one second transistor and at least one third transistor
  • the third switching unit includes at least one fourth transistor and at least one fifth transistor
  • the second control line is respectively connected to the gate electrode of the second transistor and the gate electrode of the third transistor in the odd detection unit, and the gate electrode of the fourth transistor and the gate electrode of the fifth transistor in the even detection unit
  • the third control line is respectively connected to the gate electrode of the fourth transistor and the gate electrode of the fifth transistor in the odd detection unit, and the gate electrode of the second transistor and the gate electrode of the third transistor in the even detection unit
  • the second detection line is respectively connected to the first electrode of the second transistor and the first electrode of the third transistor
  • the third detection line is respectively connected to the first electrode of the fourth transistor and the first electrode of the fifth transistor
  • the second electrode of the second transistor, the second electrode of the third transistor, the second electrode of the fourth transistor, and the second electrode of the fifth transistor are connected to the second transmission line.
  • the third transistor is disposed on a side of the second transistor away from the display area
  • the fourth transistor is disposed on a side of the third transistor away from the display area
  • the fifth transistor is disposed on a side of the fourth transistor away from the display area.
  • the second detection line includes a first sub-line and a second sub-line; the first sub-line is arranged on a side of the second transistor close to the display area and connected to the first electrode of the second transistor; the second sub-line is arranged on a side of the third transistor away from the display area and connected to the first electrode of the third transistor; the second control line is arranged on a side of the second sub-line away from the display area.
  • the second switching unit further includes a second gate connection line, a first end of the second gate connection line is respectively connected to the gate electrode of the second transistor and the gate electrode of the third transistor, and a second end of the second gate connection line is extended in a direction away from the display area and is connected to the second control line or the third control line through a via.
  • the second switch unit further includes a second connection electrode, and the second connection electrode is respectively connected to the second electrode of the second transistor, the second electrode of the third transistor, and the second transmission line through via holes.
  • the second switch unit further includes a second connection block, the second connection block is connected to the second transmission line, the second connection electrode is connected to the second connection block through a via, the second connection block and the second transmission line are arranged in the same layer and are an integrated structure connected to each other.
  • the third detection line includes a third sub-line and a fourth sub-line; the third sub-line is arranged on a side of the fourth transistor close to the display area and connected to the first electrode of the fourth transistor; the fourth sub-line is arranged on a side of the fifth transistor away from the display area and connected to the first electrode of the fifth transistor.
  • the third control line is arranged on a side of the third sub-line close to the display area.
  • the third switching unit also includes a third gate connection line, a first end of the third gate connection line is respectively connected to the gate electrode of the fourth transistor and the gate electrode of the fifth transistor, and a second end of the third gate connection line is extended in a direction close to the display area and is connected to the second control line or the third control line through a via.
  • the third switch unit further includes a third connection electrode, and the third connection electrode is respectively connected to the second electrode of the fourth transistor, the second electrode of the fifth transistor, and the second transmission line through via holes.
  • the third switch unit further includes a third connection block, the third connection block is connected to the second transmission line, the third connection electrode is connected to the third connection block through a via, the third connection block and the second transmission line are arranged on the same layer and are an integrated structure connected to each other.
  • an exemplary embodiment of the present disclosure further provides a display device, comprising any one of the above-mentioned display substrates.
  • the exemplary embodiments of the present disclosure further provide a method for preparing a display substrate, the display substrate comprising a display area and a binding area located on one side of the display area, the display area at least comprising a plurality of sub-pixels and a plurality of data signal lines constituting a plurality of pixel columns, the binding area at least comprising a detection circuit; the plurality of pixel columns at least comprising a first pixel column and a second pixel column, the first pixel column comprising a plurality of first sub-pixels emitting a first color light, the second pixel column comprising a plurality of second sub-pixels emitting a second color light and a plurality of third sub-pixels emitting a third color light; the plurality of data signal lines at least comprising a first data signal line and a second data signal line, the first data signal line being electrically connected to a plurality of first sub-pixels in the first pixel column, and the second data signal line being electrically connected to
  • the detection circuit is formed in the binding area, and the detection circuit includes a plurality of detection units.
  • At least one detection unit includes a first switch unit, a second switch unit, a third switch unit, a first transmission line, and a second transmission line.
  • the first switch unit is connected to the first data signal line through the first transmission line
  • the second switch unit and the third switch unit are connected to the second data signal line through the second transmission line.
  • the second switch unit and the third switch unit are arranged on a side of the first switch unit away from the display area.
  • FIG1 is a schematic structural diagram of a display device
  • FIG2 is a schematic structural diagram of a display substrate
  • FIG3 is a schematic diagram of a planar structure of a display area in a display substrate
  • FIG4 is a schematic diagram of a cross-sectional structure of a display area in a display substrate
  • FIG5 is an equivalent circuit diagram of a pixel driving circuit
  • FIG6 is a schematic diagram showing a planar structure of a binding area in a display substrate
  • FIG7 is a schematic diagram of a display substrate undergoing CT testing
  • FIG8 is a schematic diagram of an equivalent circuit of a detection circuit according to an exemplary embodiment of the present disclosure.
  • FIG9 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure.
  • FIG10 is a schematic diagram of a semiconductor layer pattern formed according to an embodiment of the present disclosure.
  • FIG11 is a schematic diagram of an embodiment of the present disclosure after forming a first conductive layer pattern
  • FIG12 is a schematic diagram of an embodiment of the present disclosure after forming a second conductive layer pattern
  • FIG13 is a schematic diagram of an embodiment of the present disclosure after forming a fourth insulating layer pattern
  • FIG. 14 is a schematic diagram of an embodiment of the present disclosure after forming a third conductive layer pattern.
  • 10 detection unit
  • 11 first active layer
  • 12 second active layer
  • 13 third active layer
  • 14 fourth active layer
  • 15 fifth active layer
  • 20 control line
  • 21 first gate electrode
  • 22 second gate electrode
  • 23 third grid electrode
  • 24 fourth grid electrode
  • 25 fifth grid electrode
  • 30 detection line
  • 61 first gate connection line
  • 62 second gate connection line
  • 63 third gate connection line
  • 71 first transmission line
  • 72 second transmission line
  • 81 first connection block
  • 82 second connection block
  • 83 third connection block
  • 91 first connecting electrode
  • 92 second connecting electrode
  • 93 third connecting electrode
  • 100 display area
  • 101 substrate
  • 102 driving circuit layer
  • 103 light emitting structure layer
  • 104 encapsulation structure layer
  • 200 binding area
  • 110 first control line
  • 120 second control line
  • 130 third control line
  • 210 first detection line
  • 220 second detection line
  • 220-1 first detection line
  • 220 second detection line
  • the proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values shown in the drawings.
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed should be understood in a broad sense.
  • it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the "source electrode” and the “drain electrode” may be interchanged.
  • connection includes the case where components are connected together through an element having some kind of electrical function.
  • element having some kind of electrical function There is no particular limitation on the "element having some kind of electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • Examples of “element having some kind of electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film”.
  • insulating film may be replaced by “insulating layer”.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.
  • FIG1 is a schematic diagram of the structure of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, wherein the timing controller is connected to the data driver, the scan driver, and the light emitting driver, respectively, the data driver is connected to a plurality of data signal lines (D1 to Dn), respectively, the scan driver is connected to a plurality of scan signal lines (S1 to Sm), respectively, and the light emitting driver is connected to a plurality of light emitting signal lines (E1 to Eo), respectively.
  • the timing controller is connected to the data driver, the scan driver, and the light emitting driver, respectively
  • the data driver is connected to a plurality of data signal lines (D1 to Dn), respectively
  • the scan driver is connected to a plurality of scan signal lines (S1 to Sm), respectively
  • the light emitting driver is connected to a plurality of light emitting signal lines (E1 to Eo), respectively.
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is connected to the scan signal line, the light emitting signal line, and the data signal line, respectively.
  • the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, may provide a clock signal suitable for the specifications of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specifications of the light emitting driver, an emission stop signal, etc.
  • the data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using grayscale values and control signals received from the timing controller. For example, the data driver can sample grayscale values using a clock signal, and apply data voltages corresponding to grayscale values to data signal lines D1 to Dn in units of pixel rows, where n can be a natural number.
  • the scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm.
  • the scan driver can be constructed in the form of a shift register, and can sequentially transmit scan start signals provided in the form of on-level pulses to the next level circuit under the control of a clock signal to generate scan signals, where m can be a natural number.
  • the light-emitting driver can generate emission signals to be provided to light-emitting signal lines E1, E2, E3, ... and Eo by receiving clock signals, emission stop signals, etc. from the timing controller.
  • the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo.
  • the light emitting driver may be constructed in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number.
  • FIG2 is a schematic diagram of a structure of a display substrate.
  • the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100.
  • the display area 100 may be a flat area including a plurality of sub-pixels Pxij constituting a pixel array, wherein the plurality of sub-pixels Pxij are configured to display a dynamic picture or a still image, and the display area 100 may be referred to as an effective area. Domain (AA).
  • the display substrate may employ a flexible substrate, and thus the display substrate may be deformable, for example, curled, bent, folded, or rolled.
  • the binding area 200 may include a fan-out area, a bending area, a detection circuit area, a driving chip area, and a binding pin area, which are sequentially arranged in a direction away from the display area.
  • the fan-out area is connected to the display area 100 and may include at least a data transmission line, and the plurality of data transmission lines are configured to connect the data signal lines of the display area in a fan-out routing manner.
  • the bending area is connected to the fan-out area and may include at least a composite insulating layer provided with a groove, which is configured to bend the binding area to the back of the display area.
  • the detection circuit area may include at least a detection circuit
  • the driving chip area may include at least an integrated circuit (IC), which is configured to be connected to a plurality of data transmission lines.
  • the binding pin area may include at least a plurality of pins (PINs), and the plurality of pins are configured to be bound and connected to an external flexible printed circuit (FPC).
  • the frame area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area, which are sequentially arranged in a direction away from the display area 100.
  • the circuit area is connected to the display area 100 and may include at least a plurality of cascaded gate drive circuits, which are connected to a plurality of scan lines of the pixel drive circuit in the display area 100.
  • the power line area is connected to the circuit area and may include at least a frame power lead, which extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area 100.
  • the crack dam area is connected to the power line area and may include at least a plurality of cracks arranged on the composite insulating layer.
  • the cutting area is connected to the crack dam area and may include at least a cutting groove arranged on the composite insulating layer, and the cutting groove is configured so that after all the film layers of the display substrate are prepared, the cutting equipment cuts along the cutting groove respectively.
  • the fan-out area in the binding area 200 and the power line area in the border area 300 may be provided with a first isolation dam and a second isolation dam, and the first isolation dam and the second isolation dam may extend in a direction parallel to the edge of the display area to form an annular structure surrounding the display area 100, and the edge of the display area is the edge on one side of the display area binding area or the border area.
  • FIG3 is a schematic diagram of a planar structure of a display area in a display substrate.
  • the display area may include a plurality of pixel units P arranged in a matrix manner, and at least one pixel unit P may include a sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light.
  • Each sub-pixel may include a circuit unit and a light-emitting unit, and the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to a scanning signal line, a data signal line, and a light-emitting signal line, and the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device.
  • the light-emitting unit may include at least a light-emitting device, and the light-emitting device is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.
  • the first sub-pixel P1 may be a green sub-pixel (G) emitting green light
  • the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light
  • the third sub-pixel P3 may be a red sub-pixel (R) emitting red light.
  • the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal, and the three sub-pixels may be arranged in a horizontal parallel, vertical parallel or triangular manner, which is not limited in the present disclosure.
  • a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.
  • FIG4 is a schematic diagram of a cross-sectional structure of a display area in a display substrate, illustrating the structure of three sub-pixels in the display area.
  • the display area may include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101.
  • the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.
  • the substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 may include a plurality of circuit units, and the circuit units may include at least a pixel driving circuit, and the pixel driving circuit may include
  • the encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer.
  • the first encapsulation layer and the third encapsulation layer may be made of inorganic materials
  • the second encapsulation layer may be made of organic materials
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material/organic material/inorganic material laminated structure, which can ensure that external water vapor cannot enter the light emitting structure layer 103.
  • FIG5 is a schematic diagram of an equivalent circuit of a pixel driving circuit.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • the pixel driving circuit may include 7 transistors (a first transistor T1 to a seventh transistor T7) and a storage capacitor C, and the pixel driving circuit is respectively connected to 6 signal lines (a data signal line D, a first scanning signal line S1, a second scanning signal line S2, a light emitting signal line E, an initial signal line INIT and a first power line VDD).
  • the pixel driving circuit may include a first node N1, a second node N2, and a third node N3.
  • the first node N1 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, the second node N2 is respectively connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, and the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6.
  • a first end of the storage capacitor C is connected to the second node N2 , and a second end of the storage capacitor C is connected to the first power line VDD.
  • a gate electrode of the first transistor T1 is connected to the second scan signal line S2, a first electrode of the first transistor T1 is connected to the initial signal line INIT, and a second electrode of the first transistor is connected to the second node N2.
  • the first transistor T1 transmits a first initial voltage to the gate electrode of the third transistor T3 to initialize the charge amount of the gate electrode of the third transistor T3.
  • a gate electrode of the second transistor T2 is connected to the first scan signal line S1
  • a first electrode of the second transistor T2 is connected to the second node N2
  • a second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the gate electrode of the third transistor T3 to the second electrode.
  • the gate electrode of the third transistor T3 is connected to the second node N2, that is, the gate electrode of the third transistor T3 is connected to the first end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the third transistor T3 can be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS according to the potential difference between its gate electrode and the first electrode.
  • the gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 can be called a switching transistor, a scan transistor, etc. When the on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 enables the data voltage of the data signal line D to be input to the pixel driving circuit.
  • the gate electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the gate electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device.
  • the fifth transistor T5 and the sixth transistor T6 can be called light emitting transistors. When the on-level light emitting signal is applied to the light emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power line VDD and the second power line VSS to make the light emitting device emit light.
  • the gate electrode of the seventh transistor T7 is connected to the first scanning signal line S1, and the first electrode of the seventh transistor T7 is connected to the initial
  • the first scanning signal line S1 is connected to the first scanning signal line S2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device.
  • the seventh transistor T7 transmits the second initial voltage to the first electrode of the light emitting device to initialize or release the charge accumulated in the first electrode of the light emitting device.
  • the light emitting device EL may be an OLED including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode).
  • the second electrode of the light emitting device EL is connected to the second power line VSS, the signal of the second power line VSS is a continuously provided low level signal, and the signal of the first power line VDD is a continuously provided high level signal.
  • the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.
  • the first transistor T1 to the seventh transistor T7 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor.
  • the active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide).
  • LTPS low-temperature polysilicon
  • Oxide oxide semiconductor
  • the low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current.
  • the low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate, which can take advantage of the advantages of both, realize low-frequency driving, reduce power consumption, and improve display quality.
  • LTPO low-temperature polycrystalline oxide
  • the operation process of the pixel driving circuit may include:
  • the signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals.
  • the signal of the second scanning signal line S2 is a low-level signal, which turns on the first transistor T1, and the signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, which turns off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7, and the OLED does not emit light in this stage.
  • the signal of the first scanning signal line S1 is a low level signal
  • the signals of the second scanning signal line S2 and the light emitting signal line E are high level signals
  • the data signal line D outputs a data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scanning signal line S1 is a low level signal, which turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C, and the voltage of the second end (the second node N2) of the storage capacitor C is Vd-
  • the seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is provided to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and the OLED is ensured not to emit light.
  • the signal of the second scanning signal line S2 is a high-level signal, which turns off the first transistor T1.
  • the signal of the light-emitting signal line E is a high-level signal, which turns off the fifth transistor T5 and the sixth transistor T6.
  • the signal of the light-emitting signal line E is a low-level signal
  • the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals.
  • the fifth transistor T5 and the sixth transistor T6 are turned on, and the power voltage output from the first power line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vd-
  • )-Vth] 2 K*[Vdd-Vd] 2
  • I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the threshold voltage of the third transistor T3
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power supply line VDD.
  • FIG6 is a schematic diagram of a planar structure of a binding area in a display substrate.
  • the binding area 200 in a plane parallel to the display substrate, the binding area 200 may be located on one side of the display area 100, and along the direction away from the display area 100, the binding area 200 may include a fan-out area B1, a bending area B2, a detection circuit area B3, a driver chip area B4 and a binding pin area B5 arranged in sequence.
  • the first fan-out area B1 may include at least a first power line VDD, a second power line VSS and a plurality of data transmission lines, the plurality of data transmission lines are configured to connect to the data signal lines of the display area 100, the first power line VDD is configured to connect to the high-level power line of the display area 100, and the second power line VSS is configured to connect to the low-level power line of the frame area.
  • the bending area B2 may include a composite insulating layer provided with a groove, and the groove is configured to bend the binding area 200 to the back of the display area 100.
  • the detection circuit area B3 may be provided with a detection circuit (Cell Test, CT for short) for detecting the display substrate.
  • the detection circuit CT may be connected to the corresponding signal lines of the display area, so as to realize the detection of the display substrate.
  • the driver chip area B4 may be provided with an integrated circuit IC, which is connected to the data signal lines of the display area through the data transmission lines in the first fan-out area B1.
  • the integrated circuit IC is configured to generate a driving signal required for driving the sub-pixel, and provide the driving signal to the data signal line of the display area.
  • the driving signal may be a data signal for driving the luminous brightness of the sub-pixel.
  • the binding pin area B5 may be provided with a plurality of pins PIN, and the plurality of pins are configured to be bound and connected to an external flexible circuit board FPC.
  • the binding area may include other circuits and signal lines, such as an anti-static circuit, a multiplexing circuit (MUX), etc., which are not limited in the present disclosure.
  • the display substrate preparation process requires multiple tests, one of which is an important test using a test circuit CT to perform screen testing, also known as CT testing.
  • CT testing is to input a test signal to the display substrate before the display substrate is bound to a driver chip (IC) and a flexible circuit board (FPC) for inputting display signals, so that its pixels present colors, and to check whether each pixel is good through a defect detection device to confirm whether the display substrate has defects.
  • IC driver chip
  • FPC flexible circuit board
  • FIG7 is a schematic diagram of a display substrate for CT detection.
  • the display substrate may include a display area 100 and a binding area 200 located on one side of the display area 100.
  • the display area 100 may include a plurality of sub-pixels constituting a plurality of pixel rows and a plurality of pixel columns and a plurality of data signal lines D.
  • the sub-pixels may include a circuit unit and a light-emitting device.
  • the circuit unit may include at least a pixel driving circuit.
  • the light-emitting device may be connected to the pixel driving circuit of the corresponding circuit unit.
  • the plurality of data signal lines D may extend along the second direction Y and be sequentially arranged at set intervals along the first direction X.
  • Each data signal line D is electrically connected to the pixel driving circuit of a plurality of sub-pixels in a pixel column.
  • the second direction Y and the first direction X intersect each other.
  • the second direction Y may be a pixel column direction
  • the first direction X may be a pixel row direction
  • the second direction Y may be a pixel column direction
  • the first direction X and the second direction Y may be perpendicular to each other.
  • the binding area 200 may include a detection circuit, which may include at least a plurality of detection units 10, a control line 20, and a detection line 30.
  • the plurality of detection units 10 may be sequentially arranged at set intervals along the first direction X, and the positions of the plurality of detection units 10 may correspond one-to-one to the positions of the plurality of data signal lines D in the display area 100.
  • Each detection unit 10 may include a control terminal, an input terminal, and an output terminal.
  • One end of the control line 20 may be connected to a pin of the binding pin area, and the other end of the control line 20 may be connected to a control terminal of the plurality of detection units 10.
  • the control line 20 is configured to control the conduction or disconnection of the plurality of detection units 10.
  • the detection unit 10 is configured to output the signal output by the detection line 30 to the data signal line D of the display area 100 under the control of the control line 20, so as to realize the CT detection of the display substrate.
  • the CT detection process of the detection circuit is as follows: before the display substrate is bound to the driving chip (IC) and the flexible circuit board (FPC), an external device is connected to the pins of the binding area, and the external device outputs a control signal and a detection signal to the detection circuit through the pins.
  • the control signal controls the conduction of multiple detection units, and the multiple detection units output the detection signals to the multiple data signal lines of the display area, and CT detection is performed on the red sub-pixel, the blue sub-pixel, and the green sub-pixel, respectively.
  • An exemplary embodiment of the present disclosure provides a display substrate, comprising a display area and a binding area located at one side of the display area, wherein the display area at least comprises a plurality of sub-pixels constituting a plurality of pixel columns and a plurality of data signal lines, and the binding area at least comprises a detection circuit; the plurality of pixel columns at least comprises a first pixel column and a second pixel column, the first pixel column comprises a plurality of first sub-pixels emitting a first color light, the second pixel column comprises a plurality of second sub-pixels emitting a second color light and a plurality of third sub-pixels emitting a third color light; the plurality of data signal lines at least comprises a first data signal line and a second data signal line, the first data signal line is electrically connected to a plurality of first sub-pixels in the first pixel column, and the second data signal line is electrically connected to a plurality of second sub-pixels and a third sub-pixel in the
  • an extension length of the first transmission line is smaller than an extension length of the second transmission line.
  • the first sub-pixel includes a green sub-pixel emitting green light
  • the second sub-pixel includes a blue sub-pixel emitting blue light
  • the third sub-pixel includes a red sub-pixel emitting red light.
  • FIG8 is a schematic diagram of an equivalent circuit of a detection circuit of an exemplary embodiment of the present disclosure.
  • the display area 100 may include a plurality of sub-pixels constituting a plurality of pixel rows and a plurality of pixel columns and a plurality of data signal lines
  • the binding area 200 may include a detection circuit.
  • the plurality of pixel columns may include at least a first pixel column (odd pixel column) and a second pixel column (even pixel column), the first pixel column may include a plurality of green (G) sub-pixels emitting green light, the second pixel column may include a plurality of blue (B) sub-pixels emitting blue light and a plurality of red (R) sub-pixels emitting red light, and the first pixel column and the second pixel column are alternately arranged along the first direction X.
  • G green
  • B blue
  • R red
  • the plurality of data signal lines may include at least a first data signal line D1 and a second data signal line D2, the position of the first data signal line D1 corresponds to the position of the first pixel column, the first data signal line D1 is electrically connected to a plurality of G sub-pixels in the first pixel column, the position of the second data signal line D2 corresponds to the position of the second pixel column, the second data signal line D2 is electrically connected to a plurality of B sub-pixels and a plurality of R sub-pixels in the second pixel column, and the first data signal line D1 and the second data signal line D2 are alternately arranged along the first direction X.
  • the data signal line being electrically connected to a plurality of sub-pixels in a pixel column means that the data signal line is electrically connected to pixel driving circuits of the plurality of sub-pixels in the pixel column.
  • the detection circuit may include a plurality of detection units sequentially arranged along the first direction X, the positions of the plurality of detection units corresponding to the positions of the plurality of pixel columns, the plurality of detection units may include a plurality of odd detection units and a plurality of even detection units, the plurality of odd detection units and the plurality of even detection units are arranged at intervals, and the odd detection units
  • the even detection unit is connected to the data signal line in the odd pixel column
  • the even detection unit is connected to the data signal line in the even pixel column.
  • At least one detection unit may include a first switch unit E1, a second switch unit E2, a third switch unit E3, a first transmission line 71, and a second transmission line 72.
  • a first end of the first transmission line 71 is connected to the first switch unit E1, and a second end of the first transmission line 71 is connected to a first data signal line D1 of the display area 100, that is, the first switch unit E1 is connected to the first data signal line D1 through the first transmission line 71.
  • a first end of the second transmission line 72 is connected to the second switch unit E2 and the third switch unit E3, respectively, and a second end of the second transmission line 72 is connected to the second data signal line D2 of the display area 100, that is, the second switch unit E2 and the third switch unit E3 are connected to the second data signal line D2 through the second transmission line 72.
  • the second switching unit E2 and the third switching unit E3 may be disposed on a side of the first switching unit E1 away from the display area 100 .
  • the second switch unit E2 can be arranged on a side of the first switch unit E1 away from the display area 100
  • the third switch unit E3 can be arranged on a side of the second switch unit E2 away from the display area 100, that is, the first switch unit E1, the second switch unit E2 and the third switch unit E3 can be arranged in sequence along the direction away from the display area, and each switch unit can include a control end, an input end and an output end.
  • the extension length of the first transmission line 71 extending toward the direction close to the display area is smaller than the extension length of the second transmission line 72 extending toward the direction close to the display area.
  • the detection circuit may further include a plurality of signal lines, which may include at least a first control line 110, a second control line 120, a third control line 130, a first detection line 210, a second detection line 220, and a third detection line 230, wherein the first ends of the above-mentioned signal lines are respectively connected to the pins of the binding pin area, and the second ends of the above-mentioned signal lines extend to the detection circuit area where the detection circuit is located, and are respectively connected to the corresponding detection units.
  • a plurality of signal lines which may include at least a first control line 110, a second control line 120, a third control line 130, a first detection line 210, a second detection line 220, and a third detection line 230, wherein the first ends of the above-mentioned signal lines are respectively connected to the pins of the binding pin area, and the second ends of the above-mentioned signal lines extend to the detection circuit area where the detection circuit is located, and are respectively connected to the corresponding
  • the first control line 110 can be connected to the control ends of multiple first switch units E1
  • the first detection line 210 can be connected to the input ends of multiple first switch units E1
  • the output end of each first switch unit E1 is connected to the first transmission line 71.
  • the first switch unit E1 is configured to, under the control of the first control line 110, send the signal transmitted by the first detection line 210 to the first data signal line D1 through the first transmission line 71, so that the data signal line sends the signal to the pixel driving circuit of the G sub-pixel.
  • the second control line 120 may be connected to the control end of the second switch unit E2 of the odd detection unit and the control end of the third switch unit E3 of the even detection unit, respectively, and the third control line 130 may be connected to the control end of the third switch unit E3 of the odd detection unit and the control end of the second switch unit E2 of the even detection unit, respectively.
  • the second detection line 220 may be connected to the input end of a plurality of second switch units E2, and the third detection line 230 may be connected to the input end of a plurality of third switch units E3.
  • the output end of each second switch unit E2 is connected to the second transmission line 72, and the output end of each third switch unit is connected to the second transmission line 72.
  • the second switch unit E2 is configured to, under the control of the second control line 120 and the third control line 130, transmit the signal transmitted by the second detection line 220 to the second data signal line D2 through the second transmission line 72, so that the data signal line sends the signal to the pixel driving circuit of the B sub-pixel.
  • the third switch unit E3 is configured to send the signal transmitted by the third detection line 230 to the second data signal line D2 through the second transmission line 72 under the control of the second control line 120 and the third control line 130, so that the data signal line sends the signal to the pixel driving circuit of the R sub-pixel.
  • the second control line 120 may be disposed on a side of the first control line 110 away from the display area 100
  • the third control line 130 may be disposed on a side of the second control line 120 away from the display area 100 .
  • the first inspection line 210 can be set on a side of the first control line 110 close to the display area 100
  • the second inspection line 220 can be set between the first control line 110 and the second control line 120
  • the third inspection line 230 can be set on a side of the third control line 130 away from the display area 100.
  • the G sub-pixel may be used as the first sub-pixel of the present disclosure
  • the B sub-pixel may be used as the second sub-pixel of the present disclosure
  • the R sub-pixel may be used as the third sub-pixel of the present disclosure.
  • the working process of the detection circuit of this exemplary embodiment for performing CT detection is as follows:
  • the external device When performing CT detection on the G sub-pixels in the display area, the external device causes the first control line 110 to output the first control signal through a plurality of pins, and the first detection line 210 to output the lighting voltage signal or the aging voltage signal.
  • the on-signal output by the first control line 110 turns on a plurality of first switch units E1, and the lighting voltage signal or the aging voltage signal output by the first detection line 210 is output to the first data signal line D1 connected to the G sub-pixels in the display area through the turned-on first switch units E1, so that CT detection is performed on the G sub-pixels in the display area.
  • the external device When performing CT detection on the B sub-pixel in the display area, the external device causes the second control line 120 to output the second control signal and the third control line 130 to output the third control signal through multiple pins, and the second detection line 220 outputs a lighting voltage signal or an aging voltage signal.
  • the conduction signals output by the second control line 120 and the third control line 130 turn on the multiple second switch units E2, and the lighting voltage signal or the aging voltage signal output by the second detection line 220 is output to the second data signal line D2 connected to the B sub-pixel in the display area through the turned-on second switch unit E2, and the CT detection is performed on the B sub-pixel in the display area.
  • the external device When performing CT detection on the R sub-pixel in the display area, the external device causes the second control line 120 to output the second control signal and the third control line 130 to output the third control signal through multiple pins, and the second detection line 230 outputs a lighting voltage signal or an aging voltage signal.
  • the conduction signals output by the second control line 120 and the third control line 130 turn on the multiple third switch units E3, and the lighting voltage signal or the aging voltage signal output by the second detection line 230 is output to the second data signal line D2 connected to the R sub-pixel in the display area through the turned-on third switch unit E3, and CT detection is performed on the R sub-pixel in the display area.
  • FIG9 is a schematic diagram of the structure of a display substrate of an exemplary embodiment of the present disclosure, illustrating the planar structure of four detection units in the binding area.
  • the binding area may include at least a detection circuit
  • the detection circuit may include at least a plurality of detection units, a plurality of control lines, and a plurality of detection lines.
  • the plurality of detection units may be arranged in sequence at set intervals along the first direction X, and the positions of the plurality of detection units may correspond one-to-one to the positions of the plurality of data signal lines in the display area.
  • the shape of the plurality of control lines may be a line shape extending along the first direction X, and the plurality of control lines are respectively connected to the control ends of the plurality of detection units, and the shape of the plurality of detection lines may be a line shape extending along the first direction X, and the plurality of detection lines are respectively connected to the input ends of the plurality of detection units, and the output end of each detection unit is connected to the corresponding data signal line through a transmission line.
  • the plurality of control lines may include at least a first control line 110, a second control line 120, and a third control line 130, wherein the first ends of the first control line 110, the second control line 120, and the third control line 130 are respectively connected to the pins of the binding pin area, and the second ends of the first control line 110, the second control line 120, and the third control line 130 are respectively connected to the control ends of the plurality of detection units after extending to the area where the detection circuit is located.
  • the plurality of detection lines may include at least a first detection line 210, a second detection line 220, and a third detection line 230.
  • the first ends of the first detection line 210, the second detection line 220, and the third detection line 230 are respectively connected to the pins of the binding pin area. After the second ends of the first detection line 210, the second detection line 220, and the third detection line 230 extend to the area where the detection circuit is located, the input ends of the plurality of detection units are respectively connected accordingly.
  • At least one detection unit may include a first switch unit E1, a second switch unit E2, a third switch unit E3, a first transmission line 71 and a second transmission line 72, the second switch unit E2 may be disposed on a side of the first switch unit E1 away from the display area 100, and the third switch unit E3 may be disposed on a side of the second switch unit E2 away from the display area 100.
  • the first switching unit E1 may include at least one first transistor T1, a gate electrode of the first transistor T1 is connected to the first control line 110, a first electrode of the first transistor T1 is connected to the first detection line 210, a second electrode of the first transistor T1 is connected to a first end of a first transmission line 71, and a second end of the first transmission line 71 is connected to a data signal line (first data signal line) connecting a G sub-pixel in the display area.
  • the second switch unit E2 may include at least one second transistor T2 and at least one third transistor T3
  • the third switch unit E3 may include at least one fourth transistor T4 and at least one fifth transistor T5.
  • the gate electrode of the fourth transistor T4 and the gate electrode of the fifth transistor T5 of the unit are respectively connected to the second control line 120
  • the gate electrode of the second transistor T2 and the gate electrode of the third transistor T3 of the even detection unit are respectively connected to the third control line 130.
  • the first electrode of the second transistor T2 and the first electrode of the third transistor T3 of each detection unit are respectively connected to the second detection line 220
  • the first electrode of the fourth transistor T4 and the first electrode of the fifth transistor T5 of each detection unit are respectively connected to the third detection line 230
  • the second electrode of the second transistor T2, the second electrode of the third transistor T3, the second electrode of the fourth transistor T4 and the second electrode of the fifth transistor T5 of each detection unit are respectively connected to the first end of the second transmission line 72
  • the second end of the second transmission line 72 is connected to the data signal line (second data signal line) connecting the B sub-pixel and the R sub-pixel in the display area.
  • the first transmission line 71 can be set on the side of the gate electrode of the first transistor T1 close to the display area
  • the first detection line 210 can be set on the side of the gate electrode of the first transistor T1 away from the display area
  • the first control line 110 can be set on the side of the first detection line 210 away from the display area.
  • the first switching unit E1 may further include a first gate connection line 61, a first end of the first gate connection line 61 is connected to the gate electrode of the first transistor T1, and a second end of the first gate connection line 61 extends in a direction away from the display area and is connected to the first control line 110 through a via.
  • the first switching unit E1 may further include a first connection electrode 91, which may be disposed on a side of the gate electrode of the first transistor T1 close to the display area, wherein a first end of the first connection electrode 91 is connected to an active layer of the first transistor T1 through a via hole, and a second end of the first connection electrode 92 is connected to the first transmission line 71 through a via hole.
  • a first connection electrode 91 which may be disposed on a side of the gate electrode of the first transistor T1 close to the display area, wherein a first end of the first connection electrode 91 is connected to an active layer of the first transistor T1 through a via hole, and a second end of the first connection electrode 92 is connected to the first transmission line 71 through a via hole.
  • the second transistor T2 may be disposed on a side of the first transistor T1 away from the display area
  • the third transistor T3 may be disposed on a side of the second transistor T2 away from the display area
  • the fourth transistor T4 may be disposed on a side of the third transistor T3 away from the display area
  • the fifth transistor T5 may be disposed on a side of the fourth transistor T4 away from the display area, that is, along a direction away from the display area
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are disposed in sequence.
  • the second detection line 220 may include a first sub-line 220-1 and a second sub-line 220-2 connected to the same signal source.
  • the first sub-line 220-1 may be disposed on a side of the second transistor T2 close to the display area, and respectively connected to the first electrodes of the plurality of second transistors T2.
  • the second sub-line 220-2 may be disposed on a side of the third transistor T3 away from the display area, and respectively connected to the first electrodes of the plurality of third transistors T3.
  • the first control line 110 may be disposed between the first inspection line 210 and the first sub-line 220 - 1
  • the second control line 120 may be disposed on a side of the second sub-line 220 - 2 away from the display area.
  • the third detection line 230 may include a third sub-line 230-1 and a fourth sub-line 230-2 connected to the same signal source.
  • the third sub-line 230-1 may be disposed on a side of the fourth transistor T4 close to the display area, and respectively connected to the first electrodes of the plurality of fourth transistors T4.
  • the fourth sub-line 230-2 may be disposed on a side of the fifth transistor T5 away from the display area, and respectively connected to the first electrodes of the plurality of fifth transistors T5.
  • the second control line 120 and the third control line 130 may be disposed between the second sub-line 220 - 2 and the third sub-line 230 - 1 , and the third control line 130 may be disposed on a side of the second control line 120 away from the display area.
  • the second switch unit E2 may further include a second gate connection line 62, a first end of the second gate connection line 62 is respectively connected to the gate electrode of the second transistor T2 and the gate electrode of the third transistor T3, and a second end of the second gate connection line 62 is extended in a direction away from the display area and connected to the second control line 120 or the third control line 130 through a via hole.
  • the second gate connection line 62 of the odd detection unit is connected to the second control line 120
  • the second gate connection line 62 of the even detection unit is connected to the third control line 130.
  • the third switch unit E3 may further include a third gate connection line 63, a first end of the third gate connection line 63 is respectively connected to the gate electrode of the fourth transistor T4 and the gate electrode of the fifth transistor T5, and a second end of the third gate connection line 63 is extended in a direction close to the display area and connected to the second control line 120 or the gate electrode of the fifth transistor T5 through a via hole.
  • the third gate connection line 63 of the odd detection unit is connected to the third control line 130
  • the third gate connection line 63 of the even detection unit is connected to the second control line 120 .
  • the second switching unit E2 may further include a second connection electrode 92.
  • the second connection electrode 92 is respectively connected to the active layer of the second transistor T2 and the active layer of the third transistor T3 through vias, and on the other hand, the second connection electrode 92 is connected to the second transmission line 72 through vias.
  • the third switching unit E3 may further include a third connection electrode 93.
  • the third connection electrode 93 is connected to the active layer of the fourth transistor T4 and the active layer of the fifth transistor T5 through vias, respectively, and on the other hand, the third connection electrode 93 is connected to the second transmission line 72 through vias.
  • the second switch unit E2 may further include a second connection block 82
  • the third switch unit E3 may further include a third connection block 83.
  • the second connection block 82 and the third connection block 83 are both connected to the second transmission line 72
  • the second connection electrode 92 is connected to the second connection block 82 through a via
  • the third connection electrode 93 is connected to the third connection block 83 through a via.
  • the second connection block 82, the third connection block 83 and the second transmission line 72 can be arranged on the same layer, formed synchronously through the same patterning process, and are an integrated structure that is interconnected.
  • the display substrate may include a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially disposed on a base.
  • the semiconductor layer may include at least an active layer of a plurality of transistors
  • the first conductive layer may include at least a first transmission line 71 and gate electrodes of a plurality of transistors
  • the second conductive layer may include at least a second transmission line 72
  • the third conductive layer may include at least a first electrode and a second electrode of a plurality of transistors.
  • the first connection electrode 91, the second connection electrode 92, the third connection electrode 93, the first control line 110, the second control line 120, the third control line 130, the first detection line 210, the second detection line 220 and the third detection line 230 may be disposed in the third conductive layer.
  • the following is an exemplary description of the preparation process of the detection circuit.
  • the "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials.
  • Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition
  • coating can be any one or more of spraying, spin coating, and inkjet printing
  • etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure.
  • Thin film refers to a layer of thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the "A and B are arranged in the same layer” mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of A includes the orthographic projection of B" or "the orthographic projection of B is located within the "orthographic projection range of A” means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • the preparation process of the detection circuit may include the following operations.
  • Forming a semiconductor layer pattern on a substrate may include: sequentially depositing a first insulating film and a semiconductor film on the substrate, patterning the semiconductor film through a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer pattern disposed on the first insulating layer, as shown in FIG. 10 .
  • the semiconductor layer pattern of each detection unit may include at least a first active layer 11, a second active layer 12, a third active layer 13, a fourth active layer 14 and a fifth active layer 15 arranged in sequence along the second direction Y, and the shape of each active layer may be a strip shape extending along the second direction Y.
  • the first active layer 11 may serve as an active layer of the first transistor T1
  • the second active layer 12 may serve as an active layer of the second transistor T2
  • the third active layer 13 may serve as an active layer of the third transistor T3.
  • the fourth active layer 14 can be used as an active layer of the fourth transistor T4
  • the fifth active layer 15 can be used as an active layer of the fifth transistor T5.
  • the semiconductor patterns of the plurality of sensing units may be substantially the same.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process, forming a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG. 11.
  • the first conductive layer may be referred to as a first gate metal layer (GATE1).
  • the first conductive layer pattern of each detection unit includes at least: a plurality of gate electrodes, a plurality of gate connection lines, and a plurality of first transmission lines.
  • the multiple gate electrodes of each detection unit may include a first gate electrode 21, a second gate electrode 22, a third gate electrode 23, a fourth gate electrode 24 and a fifth gate electrode 25 arranged in sequence along the second direction Y, each gate electrode may be in the shape of a strip extending along the first direction X, may be located in the middle area of the corresponding active layer in the second direction Y, and the orthographic projections of the multiple gate electrodes on the substrate at least partially overlap with the orthographic projections of the multiple active layers on the substrate.
  • the first gate electrode 21 may serve as a gate electrode of the first transistor T1
  • the second gate electrode 22 may serve as a gate electrode of the second transistor T2
  • the third gate electrode 23 may serve as a gate electrode of the third transistor T3
  • the fourth gate electrode 24 may serve as a gate electrode of the fourth transistor T4
  • the fifth gate electrode 25 may serve as a gate electrode of the fifth transistor T5.
  • the plurality of gate connection lines of each detection unit may include a first gate connection line 61 , a second gate connection line 62 , and a third gate connection line 63 .
  • the shape of the first gate connection line 61 can be a line shape in which the main part extends along the second direction Y, the first end of the first gate connection line 61 close to the display area is connected to the first gate electrode 21, and the second end of the first gate connection line 61 extends along the second direction Y in a direction away from the display area, and the first gate connection line 61 is configured to be connected to a first control line formed subsequently.
  • the shape of the second gate connection line 62 can be a line shape in which the main part extends along the second direction Y, the first end of the second gate connection line 62 close to the display area is respectively connected to the second gate electrode 22 and the third gate electrode 23, the second end of the second gate connection line 62 extends along the second direction Y in a direction away from the display area, and the second gate connection line 62 is configured to be connected to a second control line formed subsequently.
  • the shape of the third gate connection line 63 can be a line shape in which the main part extends along the second direction Y, the first end of the third gate connection line 63 away from the display area is respectively connected to the fourth gate electrode 24 and the fifth gate electrode 25, the second end of the third gate connection line 63 extends along the second direction Y toward the direction close to the display area, and the third gate connection line 63 is configured to be connected to a third control line formed subsequently.
  • the first transmission line 71 of the detection unit can be in the shape of a line with a main portion extending along the second direction Y, and can be located on the side of the first active layer 11 in the opposite direction of the second direction Y (the side of the first active layer 11 away from the second active layer 12), and the first transmission line 71 is configured to be connected to the data signal line connecting the G sub-pixels in the display area.
  • the first transmission line 71 may be connected to a first connection block 81 located on a side of the first active layer 11 in the opposite direction of the second direction Y, and the first connection block 81 is configured to be connected to the first active layer 11 through a first connection electrode formed subsequently.
  • the first conductive layer patterns of the plurality of odd detection cells may be substantially the same, the first conductive layer patterns of the plurality of even detection cells may be substantially the same, but the first conductive layer patterns of the odd detection cells and the even detection cells may be different.
  • the shapes and positions of the first gate electrode 21 , the first gate connection line 61 , and the first transfer line 71 in the odd detection unit and the even detection unit are substantially the same.
  • the shapes and positions of the second gate electrode 22, the third gate electrode 23, the fourth gate electrode 24 and the fifth gate electrode 25 in the odd detection unit and the even detection unit are substantially the same, and the shapes of the second gate connection line 62 and the third gate connection line 63 in the odd detection unit and the even detection unit are different.
  • forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film through a patterning process, forming a third insulating layer covering the first conductive layer pattern, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG. 12.
  • the second conductive layer may be referred to as a second gate metal layer (GATE2).
  • the second conductive layer pattern of each detection unit includes at least a second transmission line 72 , a second connection block 82 , and a third connection block 83 .
  • the second transmission line 72 of the detection unit can be in the shape of a line with a main portion extending along the second direction Y, and can be located on the side opposite to the first direction X of the plurality of active layers, and the second transmission line 72 is configured to be connected to a data signal line connecting the B sub-pixels and the R sub-pixels in the display area.
  • the second transmission line 72 may be connected to a second connection block 82 and a third connection block 83, respectively, that is, the second connection block 82, the third connection block 83 and the second transmission line 72 may be formed simultaneously through the same patterning process, and are an integrated structure connected to each other.
  • the second connection block 82 may be disposed between the second active layer 12 and the third active layer 13, and the second connection block 82 is configured to be connected to the second active layer 12 and the third active layer 13 respectively through a second connection electrode formed subsequently.
  • the third connection block 83 may be disposed between the fourth active layer 14 and the fifth active layer 15, and the third connection block 83 is configured to be connected to the fourth active layer 14 and the fifth active layer 15 respectively through a third connection electrode formed subsequently.
  • the second conductive layer patterns of the plurality of sensing units may be substantially the same.
  • forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film through a patterning process to form a fourth insulating layer pattern covering the second conductive layer, wherein a plurality of vias are formed on the fourth insulating layer, as shown in FIG. 13 .
  • the multiple vias in each detection unit may include a first via K1, a second via K2, a third via K3, a fourth via K4, a fifth via K5, a sixth via K6, a seventh via K7, an eighth via K8, a ninth via K9, a tenth via K10, an eleventh via K11, a twelfth via K12, a thirteenth via K13, a fourteenth via K14, a fifteenth via K15 and a sixteenth via K16.
  • the orthographic projection of the first via hole K1 on the substrate may be located within the range of the orthographic projection of the first region of the first active layer 11 on the substrate, the second insulating layer, the third insulating layer, and the fourth insulating layer in the first via hole K1 are etched away to expose the surface of the first region of the first active layer 11, and the first via hole K1 is configured to connect a subsequently formed first detection line to the first region of the first active layer 11 through the via hole.
  • the orthographic projection of the second via hole K2 on the substrate may be located within the range of the orthographic projection of the second region of the first active layer 11 on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the second via hole K2 are etched away to expose the surface of the second region of the first active layer 11, and the second via hole K2 is configured to connect a subsequently formed first connecting electrode to the second region of the first active layer 11 through the via hole.
  • the orthographic projection of the third via hole K3 on the substrate may be located within the range of the orthographic projection of the first region of the second active layer 12 on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the third via hole K3 are etched away to expose the surface of the first region of the second active layer 12, and the third via hole K3 is configured to connect a subsequently formed second detection line to the first region of the second active layer 12 through the via hole.
  • the orthographic projection of the fourth via hole K4 on the substrate may be located within the range of the orthographic projection of the second region of the second active layer 12 on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the fourth via hole K4 are etched away to expose the surface of the second region of the second active layer 12, and the fourth via hole K4 is configured to connect a subsequently formed second connecting electrode to the second region of the second active layer 12 through the via hole.
  • the orthographic projection of the fifth via hole K5 on the substrate may be located within the range of the orthographic projection of the first region of the third active layer 13 on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the fifth via hole K5 are etched away to expose the surface of the first region of the third active layer 13, and the fifth via hole K5 is configured to connect a subsequently formed second detection line to the first region of the third active layer 13 through the via hole.
  • the orthographic projection of the sixth via hole K6 on the substrate may be located within the range of the orthographic projection of the second region of the third active layer 13 on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the sixth via hole K6 are etched away to expose the surface of the second region of the third active layer 13, and the sixth via hole K6 is configured to connect a subsequently formed second connecting electrode to the second region of the third active layer 13 through the via hole.
  • the orthographic projection of the seventh via hole K7 on the substrate may be located within the range of the orthographic projection of the first area of the fourth active layer 14 on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the seventh via hole K7 are etched away to expose the surface of the first area of the fourth active layer 14, and the seventh via hole K7 is configured to connect a subsequently formed third detection line to the first area of the fourth active layer 14 through the via hole.
  • the orthographic projection of the eighth via hole K8 on the substrate may be located within the range of the orthographic projection of the second region of the fourth active layer 14 on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the eighth via hole K8 are etched away to expose the surface of the second region of the fourth active layer 14, and the eighth via hole K8 is configured to connect a subsequently formed third connecting electrode to the second region of the fourth active layer 14 through the via hole.
  • the orthographic projection of the ninth via hole K9 on the substrate may be located within the range of the orthographic projection of the first region of the fifth active layer 15 on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the ninth via hole K9 are etched away to expose the surface of the first region of the fifth active layer 15, and the ninth via hole K9 is configured to connect a subsequently formed third detection line to the first region of the fifth active layer 15 through the via hole.
  • the orthographic projection of the tenth via hole K10 on the substrate may be located within the range of the orthographic projection of the second region of the fifth active layer 15 on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the tenth via hole K10 are etched away to expose the surface of the second region of the fifth active layer 15, and the tenth via hole K10 is configured to connect a subsequently formed third connecting electrode to the second region of the fifth active layer 15 through the via hole.
  • the orthographic projection of the eleventh via hole K11 on the substrate may be located within the range of the orthographic projection of the first connection block 81 of the first transmission line 71 on the substrate, the third insulating layer and the fourth insulating layer in the eleventh via hole K11 are etched away to expose the surface of the first connection block 81, and the eleventh via hole K11 is configured to connect a subsequently formed first connection electrode to the first connection block 81 through the via hole.
  • the orthographic projection of the twelfth via hole K12 on the substrate may be located within the range of the orthographic projection of the second connection block 82 of the second transmission line 72 on the substrate, the fourth insulating layer in the twelfth via hole K12 is etched away to expose the surface of the second connection block 82, and the twelfth via hole K12 is configured to connect the second connection electrode formed subsequently to the second connection block 82 through the via hole.
  • the orthographic projection of the thirteenth via hole K13 on the substrate may be located within the range of the orthographic projection of the third connection block 83 of the second transmission line 72 on the substrate, the fourth insulating layer in the thirteenth via hole K13 is etched away, exposing the surface of the third connection block 83, and the thirteenth via hole K13 is configured to connect the subsequently formed third connection electrode to the third connection block 83 through the via hole.
  • the orthographic projection of the fourteenth via hole K14 on the substrate may be located within the range of the orthographic projection of the first gate connection line 61 on the substrate, the third insulating layer and the fourth insulating layer in the fourteenth via hole K14 are etched away, exposing the surface of the second end of the first gate connection line 61, and the fourteenth via hole K14 is configured to connect the first control line formed subsequently to the first gate connection line 61 through the via hole.
  • the orthographic projection of the fifteenth via hole K15 on the substrate may be located at the second gate connection line 62 is within the range of the orthographic projection on the substrate, the third insulating layer and the fourth insulating layer in the fifteenth via hole K15 are etched away, exposing the surface of the second end of the second gate connection line 62, the fifteenth via hole K15 in the odd detection unit is configured to connect the second control line formed subsequently to the second gate connection line 62 through the via hole, and the fifteenth via hole K15 in the even detection unit is configured to connect the third control line formed subsequently to the second gate connection line 62 through the via hole.
  • the orthographic projection of the sixteenth via hole K16 on the substrate may be located within the range of the orthographic projection of the third gate connection line 63 on the substrate, the third insulating layer and the fourth insulating layer in the sixteenth via hole K16 are etched away, exposing the surface of the second end of the third gate connection line 63, the sixteenth via hole K16 in the odd detection unit is configured to connect the subsequently formed third control line to the third gate connection line 63 through the via hole, and the sixteenth via hole K16 in the even detection unit is configured to connect the subsequently formed second control line to the third gate connection line 63 through the via hole.
  • forming the third conductive layer pattern may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film through a patterning process, and forming a third conductive layer pattern on the fourth insulating layer, as shown in FIG. 14.
  • the third conductive layer may be referred to as a first source-drain metal layer (SD1).
  • the third conductive layer pattern may include first, second, and third control lines 110 , 120 , and 130 , first, second, and third sense lines 210 , 220 , and 230 , first, second, and third connection electrodes 91 , 92 , and 93 .
  • the shape of the first control line 110 may be a line shape extending along the first direction X.
  • the first end of the first control line 110 is connected to the pin of the binding pin area, and the second end of the first control line 110 extends to the detection circuit area and is connected to the first gate connection line 61 in each detection unit through a plurality of fourteenth vias K14. Since the first gate connection line 61 is connected to the first gate electrode 21, the first control signal transmitted by the first control line 110 can be transmitted to the first gate electrode 21 through the first gate connection line 61, respectively, to control the conduction and disconnection of the first transistor T1.
  • the shape of the second control line 120 may be a line shape extending along the first direction X.
  • the first end of the second control line 120 is connected to the pin of the binding pin area, and the second end of the second control line 120 extends to the detection circuit area, and is connected to the second gate connection line 62 through the fifteenth via K15 in the odd detection unit on the one hand, and is connected to the third gate connection line 63 through the sixteenth via K16 in the even detection unit on the other hand.
  • the second gate connection line 62 is connected to the second gate electrode 22 and the third gate electrode 23, the second control signal transmitted by the second control line 120 can control the conduction and disconnection of the second transistor T2 and the third transistor T3 in the odd detection unit.
  • the third gate connection line 63 is connected to the fourth gate electrode 24 and the fifth gate electrode 25, the second control signal transmitted by the second control line 120 can control the conduction and disconnection of the fourth transistor T4 and the fifth transistor T5 in the even detection unit.
  • the shape of the third control line 130 may be a line shape extending along the first direction X.
  • a first end of the third control line 130 is connected to a pin of the binding pin area, and a second end of the third control line 130 extends to the detection circuit area, and is connected to the third gate connection line 63 through the sixteenth via K16 in the odd detection unit on the one hand, and is connected to the second gate connection line 62 through the fifteenth via K15 in the even detection unit on the other hand.
  • the second gate connection line 62 is connected to the second gate electrode 22 and the third gate electrode 23, the third control signal transmitted by the third control line 130 can control the conduction and disconnection of the second transistor T2 and the third transistor T3 in the even detection unit.
  • the third gate connection line 63 is connected to the fourth gate electrode 24 and the fifth gate electrode 25, the third control signal transmitted by the third control line 130 can control the conduction and disconnection of the fourth transistor T4 and the fifth transistor T5 in the odd detection unit.
  • the shape of the first detection line 210 can be a line shape extending along the first direction X, the first end of the first detection line 210 is connected to the pin of the binding pin area, and the second end of the first detection line 210 extends to the detection circuit area and is connected to the first area of the first active layer 11 in each detection unit through the first via K1.
  • the second detection line 220 may include a first sub-line 220-1 and a second sub-line 220-2 connected to the same signal source.
  • the shape of the first sub-line 220-1 may be a line shape extending along the first direction X
  • the first sub-line 220-2 may be a line shape extending along the first direction X.
  • the first end of the first sub-line 220-1 is connected to the pin of the binding pin area, and the second end of the first sub-line 220-1 is extended to the detection circuit area, and then connected to the first area of the second active layer 12 in each detection unit through the third via K3.
  • the shape of the second sub-line 220-2 can be a line shape extending along the first direction X, and the first end of the second sub-line 220-2 is connected to the pin of the binding pin area, and the second end of the second sub-line 220-2 is extended to the detection circuit area, and then connected to the first area of the third active layer 13 in each detection unit through the fifth via K5.
  • the third detection line 230 may include a third sub-line 230-1 and a fourth sub-line 230-2 connected to the same signal source.
  • the shape of the third sub-line 230-1 may be a line shape extending along the first direction X, the first end of the third sub-line 230-1 is connected to the pin of the binding pin area, the second end of the third sub-line 230-1 is extended to the detection circuit area, and then connected to the first area of the fourth active layer 14 in each detection unit through the seventh via K7.
  • the shape of the fourth sub-line 230-2 may be a line shape extending along the first direction X, the first end of the fourth sub-line 230-2 is connected to the pin of the binding pin area, the second end of the fourth sub-line 230-2 is extended to the detection circuit area, and then connected to the first area of the fifth active layer 15 in each detection unit through the ninth via K9.
  • the first connection electrode 91 may be disposed on a side of the first gate electrode 21 of each detection unit in the opposite direction of the second direction Y (a side of the first gate electrode 21 away from the second gate electrode 22), and the shape of the first connection electrode 91 may be a strip shape extending along the second direction Y.
  • the first end of the first connection electrode 91 is connected to the second region of the first active layer 11 through the second via K2, and the second end of the first connection electrode 91 is connected to the first connection block 81 of the first transmission line 71 through the eleventh via K11, so that the first transistor T1 can control the conduction and disconnection between the first detection line 210 and the first transmission line 71.
  • the first transistor T1 When the first transistor T1 is turned on, the first signal transmitted by the first detection line 210 is transmitted to the first transmission line 71, and the first transmission line 71 transmits the first signal to the data signal line connected to the G sub-pixel in the display area.
  • the second connection electrode 92 may be disposed between the second gate electrode 22 and the third gate electrode 23 of each detection unit, and the shape of the second connection electrode 92 may be a strip extending along the second direction Y.
  • the first end of the second connection electrode 92 is connected to the second region of the second active layer 12 through the fourth via K4, the second end of the second connection electrode 92 is connected to the second region of the third active layer 13 through the sixth via K6, and the middle portion of the second connection electrode 92 (between the first end and the second end) is connected to the second connection block 82 of the second transmission line 72 through a plurality of twelfth vias K12, so that the second transistor T2 and the third transistor T3 can control the conduction and disconnection between the first sub-line 220-1 and the second sub-line 220-2 and the second transmission line 72.
  • the second transistor T2 and the third transistor T3 When the second transistor T2 and the third transistor T3 are turned on, the second signal transmitted by the first sub-line 220-1 and the second sub-line 220-2 is transmitted to the second transmission line 72, and the second transmission line 72 transmits the second signal to the data signal line connecting the B sub-pixel and the R sub-pixel in the display area.
  • the third connection electrode 93 may be disposed between the fourth gate electrode 24 and the fifth gate electrode 25 of each detection unit, and the shape of the third connection electrode 93 may be a strip shape extending along the second direction Y.
  • the first end of the third connection electrode 93 is connected to the second region of the fourth active layer 14 through the eighth via hole K8, the second end of the third connection electrode 93 is connected to the second region of the fifth active layer 15 through the tenth via hole K10, and the middle portion of the third connection electrode 93 (between the first end and the second end) is connected to the third connection block 83 of the second transmission line 72 through a plurality of thirteenth via holes K13, so that the fourth transistor T4 and the fifth transistor T5 can control the conduction and disconnection between the third sub-line 230-1 and the fourth sub-line 230-2 and the second transmission line 72.
  • the third signal transmitted by the third sub-line 230-1 and the fourth sub-line 230-2 is transmitted to the second transmission line 72, and the second transmission line 72 transmits the third signal to the data signal line connecting the B sub-pixel and the R sub-pixel in the display area.
  • the first detection line 210 may be disposed on one side of the first transistor T1 in the second direction Y (away from the display region).
  • the first sub-line 220-1 may be disposed on one side of the second transistor T2 in the opposite direction of the second direction Y (close to the display region), and the second sub-line 220-2 may be disposed on one side of the third transistor T3 in the second direction Y.
  • the third sub-line 230-1 may be disposed on one side of the fourth transistor T4 in the opposite direction of the second direction Y, and the fourth sub-line 230-2 may be disposed on one side of the fifth transistor T5 in the second direction Y.
  • the first control line 110 may be disposed between the first detection line 210 and the first sub-line 220-1.
  • the second control line 120 and the third control line 130 may be disposed between the second sub-line 220 - 2 and the third sub-line 230 - 1 , and the third control line 130 is disposed on one side of the second control line 120 in the second direction Y.
  • the detection circuit may include a plurality of detection units arranged in sequence along the first direction X, and at least one detection unit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5.
  • the gate electrode of the first transistor T1 is connected to the first control line 110, the first electrode of the first transistor T1 is connected to the first detection line 210, and the second electrode of the first transistor T1 is connected to the first transmission line 71.
  • the gate electrodes of the second transistor T2 and the third transistor T3 are connected to the second control line 120, the first electrodes of the second transistor T2 and the third transistor T3 are connected to the second detection line 220, and the second electrodes of the second transistor T2 and the third transistor T3 are connected to the second transmission line 72.
  • the gate electrodes of the fourth transistor T4 and the fifth transistor T5 are connected to the third control line 130, the first electrodes of the fourth transistor T4 and the fifth transistor T5 are connected to the third detection line 230, and the second electrodes of the fourth transistor T4 and the fifth transistor T5 are connected to the second transmission line 72.
  • the substrate may be a flexible substrate or a rigid substrate.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together.
  • the materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc.
  • the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, and the material of the semiconductor layer may be amorphous silicon (a-Si).
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.
  • the first insulating layer may be referred to as a buffer layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer and the third insulating layer may be referred to as a gate insulating (GI) layer
  • the fourth insulating layer may be referred to as an interlayer insulating (ILD) layer.
  • the first conductive layer, the second conductive layer and the third conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multilayer composite structure, such as Ti/Al/Ti, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the active layer film can be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene and the like, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.
  • a-IGZO amorphous indium gallium zinc oxide material
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • sexithiophene or polythiophene and the like that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.
  • the present disclosure effectively reduces the size of the detection unit by setting the first switch unit for controlling the G sub-pixel for detection on the side close to the display area.
  • the present disclosure sets the first switch unit for controlling the G sub-pixel for detection on the side close to the display area, which not only makes the second switch unit for controlling the R sub-pixel for detection and the third switch unit for controlling the B sub-pixel for detection only have the second transmission line connecting the data signal line in the R sub-pixel and the B sub-pixel, but no longer has the first transmission line connecting the data signal line in the G sub-pixel, which effectively reduces the width of the detection unit, and avoids signal interference between the first transmission line and the second transmission line, thereby improving the detection quality.
  • the width of the detection unit of the exemplary embodiment of the present disclosure can be reduced by about 20%, which can be reduced from about 53 ⁇ m of the existing structure to about 42 ⁇ m, effectively reducing the size of the detection unit, which is conducive to the realization of a narrowed binding area design.
  • the preparation process disclosed in the present invention can be realized by using mature preparation equipment, with minor process improvements, high compatibility, simple process realization, easy implementation, high production efficiency, low production cost, high yield rate, and good application prospects.
  • the display substrate includes a display area and a binding area located on one side of the display area, the display area at least includes a plurality of sub-pixels and a plurality of data signal lines constituting a plurality of pixel columns, the binding area at least includes a detection circuit; the plurality of pixel columns at least include a first pixel column and a second pixel column, the first pixel column includes a plurality of first sub-pixels emitting a first color light, the second pixel column includes a plurality of second sub-pixels emitting a second color light sub-pixels and a plurality of third sub-pixels emitting a third color light; the plurality of data signal lines at least include a first data signal line and a second data signal line, the first data signal line is electrically connected to a plurality of first sub-pixels in the first pixel column, and the second data signal line is
  • the detection circuit is formed in the binding area, the detection circuit includes a plurality of detection units, at least one detection unit includes a first switch unit, a second switch unit, a third switch unit, a first transmission line and a second transmission line, the first switch unit is connected to the first data signal line through the first transmission line, the second switch unit and the third switch unit are connected to the second data signal line through the second transmission line, and the second switch unit and the third switch unit are arranged on a side of the first switch unit away from the display area of the display device,
  • the exemplary embodiments of the present disclosure further provide a display device, including the display substrate of the above-mentioned embodiment.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator.

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  • Electroluminescent Light Sources (AREA)

Abstract

一种显示基板及其制备方法、显示装置。显示基板包括显示区域和绑定区域，显示区域包括多个像素列和多条数据信号线，绑定区域包括多个检测单元；多个像素列包括第一像素列和第二像素列，多条数据信号线包括第一数据信号线和第二数据信号线，第一数据信号线与第一像素列中多个子像素电连接，第二数据信号线与第二像素列中多个子像素电连接；检测单元包括第一开关单元、第二开关单元、第三开关单元、第一传输线和第二传输线，第一开关单元通过第一传输线与第一数据信号线连接，第二开关单元和第三开关单元通过第二传输线与第二数据信号线连接；第二开关单元和第三开关单元设置在第一开关单元远离显示区域的一侧。本公开有效减小了检测单元的尺寸。

Description

显示基板及其制备方法、显示装置
本申请要求于2022年10月20日提交CNIPA、申请号为202211285974.X、发明名称为“显示基板及其制备方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的显示装置已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开示例性实施例提供了一种显示基板，包括显示区域和位于所述显示区域一侧的绑定区域，所述显示区域至少包括构成多个像素列的多个子像素和多条数据信号线，所述绑定区域至少包括检测电路；所述多个像素列至少包括第一像素列和第二像素列，所述第一像素列包括多个出射第一颜色光线的第一子像素，所述第二像素列包括多个出射第二颜色光线的第二子像素和多个出射第三颜色光线的第三子像素；所述多条数据信号线至少包括第一数据信号线和第二数据信号线，所述第一数据信号线与所述第一像素列中的多个第一子像素电连接，所述第二数据信号线与所述第二像素列中的多个第二子像素和第三子像素电连接；所述检测电路包括多个检测单元，至少一个检测单元包括第一开关单元、第二开关单元、第三开关单元、第一传输线和第二传输线，所述第一开关单元通过所述第一传输线与所述第一数据信号线连接，所述第二开关单元和所述第三开关单元通过所述第二传输线与所述第二数据信号线连接；所述第二开关单元和所述第三开关单元设置在所述第一开关单元远离所述显示区域的一侧。
在示例性实施方式中，在所述绑定区域，所述第一传输线的延伸长度小于所述第二传输线的延伸长度。
在示例性实施方式中，所述第一子像素包括出射绿色光线的绿色子像素，所述第二子像素包括出射蓝色光线的蓝色子像素，所述第三子像素包括出射红色光线的红色子像素。
在示例性实施方式中，所述检测电路还包括第一控制线和第一检测线；所述第一控制线与所述第一开关单元的控制端连接，所述第一检测线与所述第一开关单元的输入端连接，所述第一开关单元的输出端与所述第一传输线连接，所述第一开关单元被配置为在所述第一控制线的控制下，将所述第一检测线传输的信号通过所述第一传输线发送给所述第一数据信号线。
在示例性实施方式中，所述第一开关单元包括至少一个第一晶体管，所述第一控制线与所述第一晶体管的栅电极连接，所述第一检测线与所述第一晶体管的第一极连接，所述第一晶体管的第二极与所述第一传输线连接。
在示例性实施方式中，所述第一传输线设置在所述第一晶体管的栅电极靠近所述显示区域的一侧，所述第一检测线设置在所述第一晶体管的栅电极远离所述显示区域的一侧，所述第一控制线设置在所述第一检测线远离所述显示区域的一侧。
在示例性实施方式中，所述第一开关单元还包括第一栅极连接线，所述第一栅极连接线的第一端与所述第一晶体管的栅电极连接，所述第一栅极连接线的第二端沿着远离所述显示区域的方向延伸后，通过过孔与所述第一控制线连接。
在示例性实施方式中，所述第一开关单元还包括第一连接电极，所述第一连接电极的第一端通过过孔与所述第一晶体管的第一极连接，所述第一连接电极的第二端通过过孔与所述第一传输线连接。
在示例性实施方式中，所述检测电路还包括第二控制线、第三控制线、第二检测线和第三检测线；所述第二控制线分别与奇数检测单元中第二开关单元的控制端和偶数检测单元中第三开关单元的控制端连接，所述第三控制线分别与奇数检测单元中第三开关单元的控制端和偶数检测单元中第二开关单元的控制端连接；所述第二检测线与所述第二开关单元的输入端连接，所述第三检测线与所述第三开关单元的输入端连接；所述第二开关单元的输出端与所述第二传输线连接，所述第三开关单元的输出端与所述第二传输线连接；所述第二开关单元被配置为在所述第二控制线和第三控制线的控制下，将所述第二检测线传输的信号通过所述第二传输线发送给所述第二数据信号线，所述第三开关单元被配置为在所述第二控制线和第三控制线的控制下，将所述第三检测线传输的信号通过所述第二传输线发送给所述第二数据信号线。
在示例性实施方式中，所述第二开关单元包括至少一个第二晶体管和至少一个第三晶体管，所述第三开关单元包括至少一个第四晶体管和至少一个第五晶体管；所述第二控制线分别与奇数检测单元中第二晶体管的栅电极和第三晶体管的栅电极、偶数检测单元中第四晶体管的栅电极和第五晶体管的栅电极连接；所述第三控制线分别与奇数检测单元中第四晶体管的栅电极和第五晶体管的栅电极、偶数检测单元中第二晶体管的栅电极和第三晶体管的栅电极连接；所述第二检测线分别与所述第二晶体管的第一极和所述第三晶体管的第一极连接，所述第三检测线分别与所述第四晶体管的第一极和所述第五晶体管的第一极连接；所述第二晶体管的第二极、所述第三晶体管的第二极、所述第四晶体管的第二极以及所述第五晶体管的第二极与所述第二传输线连接。
在示例性实施方式中，所述第三晶体管设置在所述第二晶体管远离所述显示区域的一侧，所述第四晶体管设置在所述第三晶体管远离所述显示区域的一侧，所述第五晶体管设置在所述第四晶体管远离所述显示区域的一侧。
在示例性实施方式中，所述第二检测线包括第一子线和第二子线；所述第一子线设置在所述第二晶体管靠近所述显示区域的一侧，且与所述第二晶体管的第一极连接；所述第二子线设置在所述第三晶体管远离所述显示区域的一侧，且与所述第三晶体管的第一极连接；所述第二控制线设置在所述第二子线远离所述显示区域的一侧。
在示例性实施方式中，所述第二开关单元还包括第二栅极连接线，所述第二栅极连接线的第一端分别与所述第二晶体管的栅电极和第三晶体管的栅电极连接，所述第二栅极连接线的第二端沿着远离所述显示区域的方向延伸后，通过过孔与所述第二控制线或者所述第三控制线连接。
在示例性实施方式中，所述第二开关单元还包括第二连接电极，所述第二连接电极通过过孔分别与所述第二晶体管的第二极、所述第三晶体管的第二极和所述第二传输线连接。
在示例性实施方式中，所述第二开关单元还包括第二连接块，所述第二连接块与所述第二传输线连接，所述第二连接电极通过过孔与所述第二连接块连接，所述第二连接块和所述第二传输线同层设置，且为相互连接的一体结构。
在示例性实施方式中，所述第三检测线包括第三子线和第四子线；所述第三子线设置在所述第四晶体管靠近所述显示区域的一侧，且与所述第四晶体管的第一极连接；所述第四子线设置在所述第五晶体管远离所述显示区域的一侧，且与所述第五晶体管的第一极连 接；所述第三控制线设置在所述第三子线靠近所述显示区域的一侧。
在示例性实施方式中，所述第三开关单元还包括第三栅极连接线，所述第三栅极连接线的第一端分别与所述第四晶体管的栅电极和第五晶体管的栅电极连接，所述第三栅极连接线的第二端沿着靠近所述显示区域的方向延伸后，通过过孔与所述第二控制线或者所述第三控制线连接。
在示例性实施方式中，所述第三开关单元还包括第三连接电极，所述第三连接电极通过过孔分别与所述第四晶体管的第二极、所述第五晶体管的第二极和所述第二传输线连接。
在示例性实施方式中，所述第三开关单元还包括第三连接块，所述第三连接块与所述第二传输线连接，所述第三连接电极通过过孔与所述第三连接块连接，所述第三连接块和所述第二传输线同层设置，且为相互连接的一体结构。
另一方面，本公开示例性实施例还提供了一种显示装置，包括前述任一项所述的显示基板。
又一方面，本公开示例性实施例还提供了一种显示基板的制备方法，所述显示基板包括显示区域和位于所述显示区域一侧的绑定区域，所述显示区域至少包括构成多个像素列的多个子像素和多条数据信号线，所述绑定区域至少包括检测电路；所述多个像素列至少包括第一像素列和第二像素列，所述第一像素列包括多个出射第一颜色光线的第一子像素，所述第二像素列包括多个出射第二颜色光线的第二子像素和多个出射第三颜色光线的第三子像素；所述多条数据信号线至少包括第一数据信号线和第二数据信号线，所述第一数据信号线与所述第一像素列中的多个第一子像素电连接，所述第二数据信号线与所述第二像素列中的多个第二子像素和第三子像素电连接；所述制备方法包括：
在所述绑定区域形成所述检测电路，所述检测电路包括多个检测单元，至少一个检测单元包括第一开关单元、第二开关单元、第三开关单元、第一传输线和第二传输线，所述第一开关单元通过所述第一传输线与所述第一数据信号线连接，所述第二开关单元和所述第三开关单元通过所述第二传输线与所述第二数据信号线连接，所述第二开关单元和所述第三开关单元设置在所述第一开关单元远离所述显示区域的一侧。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示装置的结构示意图；
图2为一种显示基板的结构示意图；
图3为一种显示基板中显示区域的平面结构示意图；
图4为一种显示基板中显示区域的剖面结构示意图；
图5为一种像素驱动电路的等效电路图；
图6为一种显示基板中绑定区域的平面结构示意图；
图7为一种显示基板进行CT检测的示意图；
图8为本公开示例性实施例一种检测电路的等效电路示意图；
图9为本公开示例性实施例一种显示基板的结构示意图；
图10为本公开实施例形成半导体层图案后的示意图；
图11为本公开实施例形成第一导电层图案后的示意图；
图12为本公开实施例形成第二导电层图案后的示意图；
图13为本公开实施例形成第四绝缘层图案后的示意图；
图14为本公开实施例形成第三导电层图案后的示意图。
附图标记说明:
10—检测单元；             11—第一有源层；             12—第二有源层；
13—第三有源层；           14—第四有源层；             15—第五有源层；
20—控制线；               21—第一栅电极；             22—第二栅电极；
23—第三栅电极；           24—第四栅电极；             25—第五栅电极；
30—检测线；               61—第一栅极连接线；         62—第二栅极连接线；
63—第三栅极连接线；       71—第一传输线；             72—第二传输线；
81—第一连接块；           82—第二连接块；             83—第三连接块；
91—第一连接电极；         92—第二连接电极；           93—第三连接电极；
100—显示区域；            101—基底；                  102—驱动电路层；
103—发光结构层；          104—封装结构层；            200—绑定区域；
110—第一控制线；          120—第二控制线；            130—第三控制线；
210—第一检测线；          220—第二检测线；            220-1—第一子线；
220-2—第二子线；          230—第三检测线；            230-1—第三子线；
230-2—第四子线；          300—边框区域。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、发光信号线和数据信号线连接。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
图2为一种显示基板的结构示意图。如图2所示，显示基板可以包括显示区域100、位于显示区域100一侧的绑定区域200以及位于显示区域100其它侧的边框区域300。在示例性实施方式中，显示区域100可以是平坦的区域，包括组成像素阵列的多个子像素Pxij，多个子像素Pxij被配置为显示动态图片或静止图像，显示区域100可以称为有效区 域(AA)。在示例性实施方式中，显示基板可以采用柔性基板，因而显示基板可以是可变形的，例如卷曲、弯曲、折叠或卷起。
在示例性实施方式中，绑定区域200可以包括沿着远离显示区域方向依次设置的扇出区、弯折区、检测电路区、驱动芯片区和绑定引脚区，扇出区连接到显示区域100，可以至少包括数据传输线，多条数据传输线被配置为以扇出走线方式连接显示区域的数据信号线。弯折区连接到扇出区，可以至少包括设置有凹槽的复合绝缘层，被配置为使绑定区域弯折到显示区域的背面。检测电路区可以至少包括检测电路，驱动芯片区可以至少包括集成电路(Integrated Circuit，简称IC)，集成电路被配置为与多条数据传输线连接。绑定引脚区可以至少包括多个引脚(PIN)，多个引脚被配置为与外部的柔性线路板(Flexible Printed Circuit，简称FPC)绑定连接。
在示例性实施方式中，边框区域300可以包括沿着远离显示区域100的方向依次设置的电路区、电源线区、裂缝坝区和切割区。电路区连接到显示区域100，可以至少包括多个级联的栅极驱动电路，栅极驱动电路与显示区域100中像素驱动电路的多条扫描线连接。电源线区连接到电路区，可以至少包括边框电源引线，边框电源引线沿着平行于显示区域边缘的方向延伸，与显示区域100中的阴极连接。裂缝坝区连接到电源线区，可以至少包括在复合绝缘层上设置的多个裂缝。切割区连接到裂缝坝区，可以至少包括在复合绝缘层上设置的切割槽，切割槽被配置为在显示基板的所有膜层制备完成后，切割设备分别沿着切割槽进行切割。
在示例性实施方式中，绑定区域200中的扇出区和边框区域300中的电源线区可以设置有第一隔离坝和第二隔离坝，第一隔离坝和第二隔离坝可以沿着平行于显示区域边缘的方向延伸，形成环绕显示区域100的环形结构，显示区域边缘是显示区域绑定区域或者边框区域一侧的边缘。
图3为一种显示基板中显示区域的平面结构示意图。如图3所示，显示区域可以包括以矩阵方式排布的多个像素单元P，至少一个像素单元P可以包括出射第一颜色光线的子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3。每个子像素可以均包括电路单元和发光单元，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光器件输出相应的电流。发光单元可以至少包括发光器件，发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射绿色光线的绿色子像素(G)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3可以是出射红色光线的红色子像素(R)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形，三个子像素可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
在示例性实施方式中，像素单元可以包括四个子像素，四个子像素可以采用水平并列、竖直并列或正方形等方式排列，本公开在此不做限定。
图4为一种显示基板中显示区域的剖面结构示意图，示意了显示区域中三个子像素的结构。如图4所示，在垂直于显示基板的平面上，显示区域可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底101一侧的发光结构层103以及设置在发光结构层103远离基底101一侧的封装结构层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。驱动电路层102可以包括多个电路单元，电路单元可以至少包括像素驱动电路，像素驱动电路可以包 括多个晶体管和存储电容，图4中仅以一个像素驱动电路包括一个晶体管和一个存储电容作为示例。发光结构层103可以包括多个发光单元，发光单元可以至少包括发光器件，发光器件可以包括阳极、有机发光层和阴极，阳极与像素驱动电路连接，有机发光层与阳极连接，阴极与有机发光层连接，有机发光层在阳极和阴极驱动下出射相应颜色的光线。封装结构层104可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，形成无机材料/有机材料/无机材料叠层结构，可以保证外界水汽无法进入发光结构层103。
图5为一种像素驱动电路的等效电路示意图。在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。如图5所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)和1个存储电容C，像素驱动电路分别与6个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT和第一电源线VDD)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2和第三节点N3。其中，第一节点N1分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第二节点N2分别与第一晶体管的第二极、第二晶体管T2的第一极、第三晶体管T3的栅电极和存储电容C的第一端连接，第三节点N3分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接。
在示例性实施方式中，存储电容C的第一端与第二节点N2连接，存储电容C的第二端与第一电源线VDD连接。
在示例性实施方式中，第一晶体管T1的栅电极与第二扫描信号线S2连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管的第二极与第二节点N2连接。当导通电平扫描信号施加到第二扫描信号线S2时，第一晶体管T1将第一初始电压传输到第三晶体管T3的栅电极，以使第三晶体管T3的栅电极的电荷量初始化。
在示例性实施方式中，第二晶体管T2的栅电极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的栅电极与第二极连接。
第三晶体管T3的栅电极与第二节点N2连接，即第三晶体管T3的栅电极与存储电容C的第一端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其栅电极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的量。
第四晶体管T4的栅电极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据信号线D的数据电压输入到像素驱动电路。
第五晶体管T5的栅电极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的栅电极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管T7的栅电极与第一扫描信号线S1连接，第七晶体管T7的第一极与初始 信号线INIT连接，第七晶体管T7的第二极与发光器件的第一极连接。当导通电平扫描信号施加到第一扫描信号线S1时，第七晶体管T7将第二初始电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
在示例性实施方式中，发光器件EL可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，或者可以是QLED，包括叠设的第一极(阳极)、量子点发光层和第二极(阴极)。
在示例性实施方式中，发光器件EL的第二极与第二电源线VSS连接，第二电源线VSS的信号为持续提供的低电平信号，第一电源线VDD的信号为持续提供的高电平信号。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在示例性实施方式中，以图5所示像素驱动电路中7个晶体管均为P型晶体管为例，像素驱动电路的工作过程可以包括：
第一阶段(可以称为复位阶段)，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1和发光信号线E的信号为高电平信号。第二扫描信号线S2的信号为低电平信号，使第一晶体管T1导通，初始信号线INIT的信号提供至第二节点N2，对存储电容C进行初始化，清除存储电容中原有数据电压。第一扫描信号线S1和发光信号线E的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段(可以称为数据写入阶段或者阈值补偿阶段)，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线E的信号为高电平信号，数据信号线D输出数据电压。此阶段由于存储电容C的第一端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使得初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第二扫描信号线S2的信号为高电平信号，使第一晶体管T1断开。发光信号线E的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段(可以称为发光阶段)，发光信号线E的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线E的信号为低电平信号， 使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vd-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth)2＝K*[(Vdd-Vd+|Vth|)-Vth]2＝K*[Vdd-Vd]2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
图6为一种显示基板中绑定区域的平面结构示意图。如图6所示，在示例性实施方式中，在平行于显示基板的平面内，绑定区域200可以位于显示区域100的一侧，沿着远离显示区域100的方向，绑定区域200可以包括依次设置的扇出区B1、弯折区B2、检测电路区B3、驱动芯片区B4和绑定引脚区B5。第一扇出区B1可以至少包括第一电源线VDD、第二电源线VSS和多条数据传输线，多条数据传输线被配置为连接显示区域100的数据信号线，第一电源线VDD被配置为连接显示区域100的高电平电源线，第二电源线VSS被配置为连接边框区域的低电平电源线。弯折区B2可以包括设置有凹槽的复合绝缘层，凹槽被配置为使绑定区域200弯折到显示区域100的背面。检测电路区B3可以设置有对显示基板进行检测的检测电路(Cell Test，简称CT)，检测电路CT可以与显示区域的相应信号线连接，可以实现显示基板的检测。驱动芯片区B4可以设置集成电路IC，集成电路IC通过第一扇出区B1中的数据传输线与显示区域的数据信号线连接，集成电路IC被配置为产生用于驱动子像素所需的驱动信号，并且将驱动信号提供给显示区域的数据信号线。例如，驱动信号可以是驱动子像素发光亮度的数据信号。绑定引脚区B5可以设置多个引脚PIN，多个引脚被配置为与外部的柔性电路板FPC绑定连接。在示例性实施方式中，绑定区域可以包括其它电路和信号线，如防静电电路、多路复用电路(MUX)等，本公开在此不做限定。
在示例性实施方式中，显示基板制备过程需要进行多个检测，其中一个重要的检测是利用检测电路CT进行画面检测，也称CT检测。CT检测是显示基板未绑定驱动芯片(IC)和输入显示信号的柔性电路板(FPC)之前，通过对显示基板输入检测信号，使其像素呈现色彩，通过缺陷检测装置检查各个像素是否良好，以确认显示基板是否存在缺陷。
图7为一种显示基板进行CT检测的示意图。如图7所示，显示基板可以包括显示区域100和位于显示区域100一侧的绑定区域200。显示区域100可以包括构成多个像素行和多个像素列的多个子像素以及多条数据信号线D，子像素可以包括电路单元和发光器件，电路单元可以至少包括像素驱动电路，发光器件可以与对应电路单元的像素驱动电路连接。多条数据信号线D可以沿着第二方向Y延伸，并沿着第一方向X以设定的间隔依次设置，每条数据信号线D与一个像素列中多个子像素的像素驱动电路电连接，第二方向Y和第一方向X相互交叉。在示例性实施方式中，第二方向Y可以是像素列方向，第一方向X可以是像素行方向，第二方向Y可以是像素列方向，第一方向X和第二方向Y可以相互垂直。
在示例性实施方式中，绑定区域200可以包括检测电路，检测电路可以至少包括多个检测单元10、控制线20和检测线30。多个检测单元10可以沿着第一方向X以设定的间隔依次设置，多个检测单元10的位置可以与显示区域100中多条数据信号线D的位置一一对应。每个检测单元10可以包括控制端、输入端和输出端，控制线20的一端与绑定引脚区的引脚对应连接，控制线20的另一端可以与多个检测单元10的控制端对应连接，控 制线20被配置为控制多个检测单元10的导通或者断开。检测线30的一端与绑定引脚区的引脚对应连接，检测线30的另一端可以与多个检测单元10的输入端对应连接，多个检测单元10的输出端可以与显示区域100的多条数据信号线D对应连接，检测单元10被配置为在控制线20的控制下，将检测线30输出的信号输出给显示区域100的数据信号线D，实现显示基板的CT检测。
在示例性实施方式中，检测电路的CT检测过程为：在显示基板绑定驱动芯片(IC)和柔性电路板(FPC)之前，将外部装置连接在绑定区域的引脚上，外部装置通过引脚向检测电路输出控制信号和检测信号，控制信号控制多个检测单元导通，多个检测单元将检测信号输出给显示区域的多条数据信号线，分别对红色子像素、蓝色子像素和绿色子像素进行CT检测。
随着OLED显示技术的发展，消费者对显示产品显示效果的要求越来越高，极窄边框甚至无边框设计成为显示产品发展的新趋势。由于检测电路区中检测电路的占用面积较大，因而减小检测电路的尺寸对于绑定区域窄化是十分必要的。
本公开示例性实施例提供了一种显示基板，包括显示区域和位于所述显示区域一侧的绑定区域，所述显示区域至少包括构成多个像素列的多个子像素和多条数据信号线，所述绑定区域至少包括检测电路；所述多个像素列至少包括第一像素列和第二像素列，所述第一像素列包括多个出射第一颜色光线的第一子像素，所述第二像素列包括多个出射第二颜色光线的第二子像素和多个出射第三颜色光线的第三子像素；所述多条数据信号线至少包括第一数据信号线和第二数据信号线，所述第一数据信号线与所述第一像素列中的多个第一子像素电连接，所述第二数据信号线与所述第二像素列中的多个第二子像素和第三子像素电连接；所述检测电路包括多个检测单元，至少一个检测单元包括第一开关单元、第二开关单元、第三开关单元、第一传输线和第二传输线，所述第一开关单元通过所述第一传输线与所述第一数据信号线连接，所述第二开关单元和所述第三开关单元通过所述第二传输线与所述第二数据信号线连接；所述第二开关单元和所述第三开关单元设置在所述第一开关单元远离所述显示区域的一侧。
在示例性实施方式中，在所述绑定区域，所述第一传输线的延伸长度小于所述第二传输线的延伸长度。
在示例性实施方式中，所述第一子像素包括出射绿色光线的绿色子像素，所述第二子像素包括出射蓝色光线的蓝色子像素，所述第三子像素包括出射红色光线的红色子像素。
图8为本公开示例性实施例一种检测电路的等效电路示意图。如图8所示，显示区域100可以包括构成多个像素行和多个像素列的多个子像素以及多条数据信号线，绑定区域200可以包括检测电路。多个像素列可以至少包括第一像素列(奇数像素列)和第二像素列(偶数像素列)，第一像素列可以包括多个出射绿色光线的绿色(G)子像素，第二像素列可以包括多个出射蓝色光线的蓝色(B)子像素和多个出射红色光线的红色(R)子像素，第一像素列和第二像素列沿着第一方向X交替设置。多条数据信号线可以至少包括第一数据信号线D1和第二数据信号线D2，第一数据信号线D1的位置与第一像素列的位置相对应，第一数据信号线D1与第一像素列中多个G子像素电连接，第二数据信号线D2的位置与第二像素列的位置相对应，第二数据信号线D2与第二像素列中多个B子像素和多个R子像素电连接，第一数据信号线D1和第二数据信号线D2沿着第一方向X交替设置。本公开中，数据信号线与像素列中多个子像素电连接是指，数据信号线与像素列中多个子像素的像素驱动电路电连接。
在示例性实施方式中，检测电路可以包括沿着第一方向X依次设置的多个检测单元，多个检测单元的位置与多个像素列的位置相对应，多个检测单元可以包括多个奇数检测单元和多个偶数检测单元，多个奇数检测单元和多个偶数检测单元间隔设置，奇数检测单元 与奇数像素列中的数据信号线连接，偶数检测单元与偶数像素列中的数据信号线连接。
在示例性实施方式中，至少一个检测单元可以包括第一开关单元E1、第二开关单元E2、第三开关单元E3、第一传输线71和第二传输线72。第一传输线71的第一端与第一开关单元E1连接，第一传输线71的第二端与显示区域100的第一数据信号线D1连接，即第一开关单元E1通过第一传输线71与第一数据信号线D1连接。第二传输线72的第一端与分别与第二开关单元E2和第三开关单元E3连接，第二传输线72的第二端与显示区域100的第二数据信号线D2连接，即第二开关单元E2和第三开关单元E3通过第二传输线72与第二数据信号线D2连接。
在示例性实施方式中，第二开关单元E2和第三开关单元E3可以设置在第一开关单元E1远离显示区域100的一侧。
在示例性实施方式中，第二开关单元E2可以设置在第一开关单元E1远离显示区域100的一侧，第三开关单元E3可以设置在第二开关单元E2远离显示区域100的一侧，即第一开关单元E1、第二开关单元E2和第三开关单元E3可以沿着远离显示区域的方向依次设置，每个开关单元可以均包括控制端、输入端和输出端。
在示例性实施方式中，由于第一开关单元E1与显示区域之间的距离小于第二开关单元E2与显示区域之间的距离，因而在绑定区域200，第一传输线71向着靠近显示区域的方向延伸的延伸长度小于第二传输线72向着靠近显示区域的方向延伸的延伸长度。
在示例性实施方式中，检测电路还可以包括多条信号线，多条信号线可以至少包括第一控制线110、第二控制线120、第三控制线130、第一检测线210、第二检测线220和第三检测线230，上述信号线的第一端分别与绑定引脚区的引脚对应连接，上述信号线的第二端延伸到检测电路所在的检测电路区，分别与对应的检测单元对应连接。
在示例性实施方式中，第一控制线110可以与多个第一开关单元E1的控制端连接，第一检测线210可以与多个第一开关单元E1的输入端连接，每个第一开关单元E1的输出端与第一传输线71连接，第一开关单元E1被配置为在第一控制线110的控制下，将第一检测线210传输的信号通过第一传输线71发送给第一数据信号线D1，使数据信号线将信号发送给G子像素的像素驱动电路。
在示例性实施方式中，第二控制线120可以分别与奇数检测单元的第二开关单元E2的控制端和偶数检测单元的第三开关单元E3的控制端连接，第三控制线130可以分别与奇数检测单元的第三开关单元E3的控制端和偶数检测单元的第二开关单元E2的控制端连接。第二检测线220可以与多个第二开关单元E2的输入端连接，第三检测线230可以与多个第三开关单元E3的输入端连接。每个第二开关单元E2的输出端与第二传输线72连接，每个第三开关单元的输出端与第二传输线72连接。第二开关单元E2被配置为在第二控制线120和第三控制线130的控制下，将第二检测线220传输的信号通过第二传输线72第二数据信号线D2，使数据信号线将信号发送给B子像素的像素驱动电路。第三开关单元E3被配置为在第二控制线120和第三控制线130的控制下，将第三检测线230传输的信号通过第二传输线72发送给第二数据信号线D2，使数据信号线将信号发送给R子像素的像素驱动电路。
在示例性实施方式中，第二控制线120可以设置在第一控制线110远离显示区域100的一侧，第三控制线130可以设置在第二控制线120远离显示区域100的一侧。
在示例性实施方式中，第一检测线210可以设置在第一控制线110靠近显示区域100的一侧，第二检测线220可以设置在第一控制线110和第二控制线120之间，第三检测线230可以设置在第三控制线130远离显示区域100的一侧。
在示例性实施方式中，G子像素可以作为本公开的第一子像素，B子像素可以作为本公开的第二子像素，R子像素可以作为本公开的第三子像素。
在示例性实施方式中，本示例性实施例检测电路进行CT检测的工作过程为：
对显示区域的G子像素进行CT检测时，外部装置通过多个引脚使第一控制线110输出第一控制信号，第一检测线210输出点灯电压信号或者老化电压信号。第一控制线110输出的导通信号使多个第一开关单元E1导通，第一检测线210输出的点灯电压信号或者老化电压信号通过导通的第一开关单元E1输出给显示区域中连接G子像素的第一数据信号线D1，对显示区域中的G子像素进行CT检测。
对显示区域的B子像素进行CT检测时，外部装置通过多个引脚使第二控制线120输出第二控制信号和第三控制线130输出第三控制信号，第二检测线220输出点灯电压信号或者老化电压信号。第二控制线120和第三控制线130输出的导通信号使多个第二开关单元E2导通，第二检测线220输出的点灯电压信号或者老化电压信号通过导通的第二开关单元E2输出给显示区域中连接B子像素的第二数据信号线D2，对显示区域中的B子像素进行CT检测。对显示区域的R子像素进行CT检测时，外部装置通过多个引脚使第二控制线120输出第二控制信号和第三控制线130输出第三控制信号，第二检测线230输出点灯电压信号或者老化电压信号。第二控制线120和第三控制线130输出的导通信号使多个第三开关单元E3导通，第二检测线230输出的点灯电压信号或者老化电压信号通过导通的第三开关单元E3输出给显示区域中连接R子像素的第二数据信号线D2，对显示区域中的R子像素进行CT检测。
图9为本公开示例性实施例一种显示基板的结构示意图，示意了绑定区域中四个检测单元的平面结构。如图9所示，绑定区域可以至少包括检测电路，检测电路可以至少包括多个检测单元、多条控制线和多条检测线。多个检测单元可以沿着第一方向X以设定的间隔依次设置，多个检测单元的位置可以与显示区域中多条数据信号线的位置一一对应。在检测电路所在区域，多条控制线的形状可以为沿着第一方向X延伸的线形状，多条控制线分别与多个检测单元的控制端对应连接，多条检测线的形状可以为沿着第一方向X延伸的线形状，多条检测线分别与多个检测单元的输入端对应连接，每个检测单元的输出端通过传输线与对应的数据信号线连接。
在示例性实施方式中，多条控制线可以至少包括第一控制线110、第二控制线120和第三控制线130，第一控制线110、第二控制线120和第三控制线130的第一端分别与绑定引脚区的引脚对应连接，第一控制线110、第二控制线120和第三控制线130的第二端延伸到检测电路所在区域后，分别与多个检测单元的控制端对应连接。
在示例性实施方式中，多条检测线可以至少包括第一检测线210、第二检测线220和第三检测线230，第一检测线210、第二检测线220和第三检测线230的第一端分别与绑定引脚区的引脚对应连接，第一检测线210、第二检测线220和第三检测线230的的第二端延伸到检测电路所在区域后，分别多个检测单元的输入端对应连接。
在示例性实施方式中，至少一个检测单元可以包括第一开关单元E1、第二开关单元E2、第三开关单元E3、第一传输线71和第二传输线72，第二开关单元E2可以设置在第一开关单元E1远离显示区域100的一侧，第三开关单元E3可以设置在第二开关单元E2远离显示区域100的一侧。
在示例性实施方式中，第一开关单元E1可以包括至少一个第一晶体管T1，第一晶体管T1的栅电极与第一控制线110连接，第一晶体管T1的第一极与第一检测线210连接，第一晶体管T1的第二极与第一传输线71的第一端连接，第一传输线71的第二端与显示区域中连接G子像素的数据信号线(第一数据信号线)连接。
在示例性实施方式中，第二开关单元E2可以包括至少一个第二晶体管T2和至少一个第三晶体管T3，第三开关单元E3可以包括至少一个第四晶体管T4和至少一个第五晶体管T5。奇数检测单元的第二晶体管T2的栅电极和第三晶体管T3的栅电极、偶数检测 单元的第四晶体管T4的栅电极和第五晶体管T5的栅电极分别与第二控制线120连接，奇数检测单元的第四晶体管T4的栅电极和第五晶体管T5的栅电极、偶数检测单元的第二晶体管T2的栅电极和第三晶体管T3的栅电极分别与第三控制线130连接。每个检测单元的第二晶体管T2的第一极和第三晶体管T3的第一极分别与第二检测线220连接，每个检测单元的第四晶体管T4的第一极和第五晶体管T5的第一极分别与第三检测线230连接，每个检测单元的第二晶体管T2的第二极、第三晶体管T3的第二极、第四晶体管T4的第二极和第五晶体管T5的第二极分别与第二传输线72的第一端连接，第二传输线72的第二端与显示区域中连接B子像素和R子像素的数据信号线(第二数据信号线)连接。
在示例性实施方式中，第一传输线71可以设置在第一晶体管T1的栅电极靠近显示区域的一侧，第一检测线210可以设置在第一晶体管T1的栅电极远离显示区域的一侧，第一控制线110可以设置在第一检测线210远离显示区域的一侧。
在示例性实施方式中，第一开关单元E1还可以包括第一栅极连接线61，第一栅极连接线61的第一端与第一晶体管T1的栅电极连接，第一栅极连接线61的第二端沿着远离显示区域的方向延伸后，通过过孔与第一控制线110连接。
在示例性实施方式中，第一开关单元E1还可以包括第一连接电极91，第一连接电极91可以设置在第一晶体管T1的栅电极靠近显示区域的一侧，第一连接电极91的第一端通过过孔与第一晶体管T1的有源层连接，第一连接电极92的第二端通过过孔与第一传输线71连接。
在示例性实施方式中，第二晶体管T2可以设置在第一晶体管T1远离显示区域的一侧，第三晶体管T3可以设置在第二晶体管T2远离显示区域的一侧，第四晶体管T4可以设置在第三晶体管T3远离显示区域的一侧，第五晶体管T5可以设置在第四晶体管T4远离显示区域的一侧，即沿着远离显示区域的方向，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5依次设置。
在示例性实施方式中，第二检测线220可以包括连接相同信号源的第一子线220-1和第二子线220-2。第一子线220-1可以设置在第二晶体管T2靠近显示区域的一侧，且分别与多个第二晶体管T2的第一极连接。第二子线220-2可以设置在第三晶体管T3远离显示区域的一侧，且分别与多个第三晶体管T3的第一极连接。
在示例性实施方式中，第一控制线110可以设置在第一检测线210与第一子线220-1之间，第二控制线120可以设置在第二子线220-2远离显示区域的一侧。
在示例性实施方式中，第三检测线230可以包括连接相同信号源的第三子线230-1和第四子线230-2。第三子线230-1可以设置在第四晶体管T4靠近显示区域的一侧，且分别与多个第四晶体管T4的第一极连接。第四子线230-2可以设置在第五晶体管T5远离显示区域的一侧，且分别与多个第五晶体管T5的第一极连接。
在示例性实施方式中，第二控制线120和第三控制线130可以设置在第二子线220-2与第三子线230-1之间，第三控制线130可以设置在第二控制线120远离显示区域的一侧。
在示例性实施方式中，第二开关单元E2还可以包括第二栅极连接线62，第二栅极连接线62的第一端分别与第二晶体管T2的栅电极和第三晶体管T3的栅电极连接，第二栅极连接线62的第二端沿着远离显示区域的方向延伸后，通过过孔与第二控制线120或者第三控制线130连接。在示例性实施方式中，奇数检测单元的第二栅极连接线62与第二控制线120连接，偶数检测单元的第二栅极连接线62与第三控制线130连接。
在示例性实施方式中，第三开关单元E3还可以包括第三栅极连接线63，第三栅极连接线63的第一端分别与第四晶体管T4的栅电极和第五晶体管T5的栅电极连接，第三栅极连接线63的第二端沿着靠近显示区域的方向延伸后，通过过孔与第二控制线120或者 第三控制线130连接。在示例性实施方式中，奇数检测单元的第三栅极连接线63与第三控制线130连接，偶数检测单元的第三栅极连接线63与第二控制线120连接。
在示例性实施方式中，第二开关单元E2还可以包括第二连接电极92，一方面，第二连接电极92通过过孔分别与第二晶体管T2的有源层和第三晶体管T3的有源层连接，另一方面，第二连接电极92通过过孔与第二传输线72连接。
在示例性实施方式中，第三开关单元E3还可以包括第三连接电极93，一方面，第三连接电极93通过过孔分别与第四晶体管T4的有源层和第五晶体管T5的有源层连接，另一方面，第三连接电极93通过过孔与第二传输线72连接。
在示例性实施方式中，第二开关单元E2还可以包括第二连接块82，第三开关单元E3还可以包括第三连接块83，第二连接块82和第三连接块83均与第二传输线72连接，第二连接电极92通过过孔与第二连接块82连接，第三连接电极93通过过孔与第三连接块83连接，第二连接块82、第三连接块83和第二传输线72可以同层设置，通过同一次图案化工艺同步形成，且为相互连接的一体结构。
在示例性实施方式中，在垂直于显示基板的平面上，显示基板可以包括在基底上依次设置的半导体层、第一导电层、第二导电层和第三导电层。半导体层可以至少包括多个晶体管的有源层，第一导电层可以至少包括第一传输线71和多个晶体管的栅电极，第二导电层可以至少包括第二传输线72，第三导电层可以至少包括多个晶体管的第一极和第二极。
在示例性实施方式中，第一连接电极91、第二连接电极92、第三连接电极93、第一控制线110、第二控制线120、第三控制线130、第一检测线210、第二检测线220和第三检测线230可以设置在第三导电层中。
下面通过检测电路的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“A的正投影包含B的正投影”或“B的正投影位于“A的正投影范围之内”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，检测电路的制备过程可以包括如下操作。
(1)在基底上形成半导体层图案。在示例性实施方式中，在基底上形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖基底的第一绝缘层，以及设置在第一绝缘层上的半导体层图案，如图10所示。
在示例性实施方式中，每个检测单元的半导体层图案可以至少包括沿着第二方向Y依次设置第一有源层11、第二有源层12、第三有源层13、第四有源层14和第五有源层15，每个有源层的形状可以为沿着第二方向Y延伸的条形状。
在示例性实施方式中，第一有源层11可以作为第一晶体管T1的有源层，第二有源层12可以作为第二晶体管T2的有源层，第三有源层13可以作为第三晶体管T3的有源 层，第四有源层14可以作为第四晶体管T4的有源层，第五有源层15可以作为第五晶体管T5的有源层。
在示例性实施方式中，多个检测单元的半导体图案可以基本上相同。
(2)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，如图11所示。在示例性实施方式中，第一导电层可以称为第一栅金属层(GATE1)。
在示例性实施方式中，每个检测单元的第一导电层图案至少包括：多个栅电极、多条栅极连接线和多条第一传输线。
在示例性实施方式中，每个检测单元的多个栅电极可以包括沿着第二方向Y依次设置第一栅电极21、第二栅电极22、第三栅电极23、第四栅电极24和第五栅电极25，每个栅电极可以为沿着第一方向X延伸的条形状，可以位于对应的有源层第二方向Y的中部区域，多个栅电极在基底上的正投影与多个有源层在基底上的正投影至少部分交叠。
在示例性实施方式中，第一栅电极21可以作为第一晶体管T1的栅电极，第二栅电极22可以作为第二晶体管T2的栅电极，第三栅电极23可以作为第三晶体管T3的栅电极，第四栅电极24可以作为第四晶体管T4的栅电极，第五栅电极25可以作为第五晶体管T5的栅电极。
在示例性实施方式中，每个检测单元的多条栅极连接线可以包括第一栅极连接线61、第二栅极连接线62和第三栅极连接线63。
在示例性实施方式中，第一栅极连接线61的形状可以为主体部分沿着第二方向Y延伸的线形状，第一栅极连接线61中靠近显示区域的第一端与第一栅电极21连接，第一栅极连接线61的第二端沿着第二方向Y向着远离显示区域的方向延伸，第一栅极连接线61被配置为与后续形成的第一控制线连接。
在示例性实施方式中，第二栅极连接线62的形状可以为主体部分沿着第二方向Y延伸的线形状，第二栅极连接线62中靠近显示区域的第一端分别与第二栅电极22和第三栅电极23连接，第二栅极连接线62的第二端沿着第二方向Y向着远离显示区域的方向延伸，第二栅极连接线62被配置为与后续形成的第二控制线连接。
在示例性实施方式中，第三栅极连接线63的形状可以为主体部分沿着第二方向Y延伸的线形状，第三栅极连接线63中远离显示区域的第一端分别与第四栅电极24和第五栅电极25连接，第三栅极连接线63的第二端沿着第二方向Y向着靠近显示区域的方向延伸，第三栅极连接线63被配置为与后续形成的第三控制线连接。
在示例性实施方式中，检测单元的第一传输线71可以为主体部分沿着第二方向Y延伸的线形状，可以位于第一有源层11第二方向Y的反方向的一侧(第一有源层11远离第二有源层12的一侧)，第一传输线71被配置为与显示区域中连接G子像素的数据信号线连接。
在示例性实施方式中，第一传输线71可以连接有第一连接块81，第一连接块81位于第一有源层11第二方向Y的反方向的一侧，第一连接块81被配置为通过后续形成的第一连接电极与第一有源层11连接。
在示例性实施方式中，多个奇数检测单元的第一导电层图案可以基本上相同，多个偶数检测单元的第一导电层图案可以基本上相同，但奇数检测单元和偶数检测单元的第一导电层图案可以不同。
在示例性实施方式中，奇数检测单元和偶数检测单元中的第一栅电极21、第一栅极连接线61和第一传输线71的形状和位置基本上相同。
在示例性实施方式中，奇数检测单元和偶数检测单元中的第二栅电极22、第三栅电极23、第四栅电极24和第五栅电极25的形状和位置基本上相同，奇数检测单元和偶数检测单元中第二栅极连接线62和第三栅极连接线63的形状不同。
(3)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上依次沉积第三绝缘薄膜和第二导电薄膜，通过图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层图案的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，如图12所示。在示例性实施方式中，第二导电层可以称为第二栅金属层(GATE2)。
在示例性实施方式中，每个检测单元的第二导电层图案至少包括：第二传输线72、第二连接块82和第三连接块83。
在示例性实施方式中，检测单元的第二传输线72可以为主体部分沿着第二方向Y延伸的线形状，可以位于多个有源层第一方向X的反方向的一侧，第二传输线72被配置为与显示区域中连接B子像素和R子像素的数据信号线连接。
在示例性实施方式中，第二传输线72上可以分别连接有第二连接块82和第三连接块83，即第二连接块82、第三连接块83和第二传输线72可以通过同一次图案化工艺同步形成，且为相互连接的一体结构。第二连接块82可以设置在第二有源层12和第三有源层13之间，第二连接块82被配置为通过后续形成的第二连接电极分别与第二有源层12和第三有源层13连接。第三连接块83可以设置在第四有源层14和第五有源层15之间，第三连接块83被配置为通过后续形成的第三连接电极分别与第四有源层14和第五有源层15连接。
在示例性实施方式中，多个检测单元的第二导电层图案可以基本上相同。
(4)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的基底上沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层图案，第四绝缘层上形成有多个过孔，如图13所示。
在示例性实施方式中，每个检测单元中的多个过孔可以包括第一过孔K1、第二过孔K2、第三过孔K3、第四过孔K4、第五过孔K5、第六过孔K6、第七过孔K7、第八过孔K8、第九过孔K9、第十过孔K10、第十一过孔K11、第十二过孔K12、第十三过孔K13、第十四过孔K14、第十五过孔K15和第十六过孔K16。
在示例性实施方式中，第一过孔K1在基底上的正投影可以位于第一有源层11的第一区在基底上的正投影的范围之内，第一过孔K1内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第一有源层11的第一区的表面，第一过孔K1被配置为使后续形成的第一检测线通过该过孔与第一有源层11的第一区连接。
在示例性实施方式中，第二过孔K2在基底上的正投影可以位于第一有源层11的第二区在基底上的正投影的范围之内，第二过孔K2内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第一有源层11的第二区的表面，第二过孔K2被配置为使后续形成的第一连接电极通过该过孔与第一有源层11的第二区连接。
在示例性实施方式中，第三过孔K3在基底上的正投影可以位于第二有源层12的第一区在基底上的正投影的范围之内，第三过孔K3内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第二有源层12的第一区的表面，第三过孔K3被配置为使后续形成的第二检测线通过该过孔与第二有源层12的第一区连接。
在示例性实施方式中，第四过孔K4在基底上的正投影可以位于第二有源层12的第二区在基底上的正投影的范围之内，第四过孔K4内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第二有源层12的第二区的表面，第四过孔K4被配置为使后续形成的第二连接电极通过该过孔与第二有源层12的第二区连接。
在示例性实施方式中，第五过孔K5在基底上的正投影可以位于第三有源层13的第一区在基底上的正投影的范围之内，第五过孔K5内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第三有源层13的第一区的表面，第五过孔K5被配置为使后续形成的第二检测线通过该过孔与第三有源层13的第一区连接。
在示例性实施方式中，第六过孔K6在基底上的正投影可以位于第三有源层13的第二区在基底上的正投影的范围之内，第六过孔K6内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第三有源层13的第二区的表面，第六过孔K6被配置为使后续形成的第二连接电极通过该过孔与第三有源层13的第二区连接。
在示例性实施方式中，第七过孔K7在基底上的正投影可以位于第四有源层14的第一区在基底上的正投影的范围之内，第七过孔K7内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第四有源层14的第一区的表面，第七过孔K7被配置为使后续形成的第三检测线通过该过孔与第四有源层14的第一区连接。
在示例性实施方式中，第八过孔K8在基底上的正投影可以位于第四有源层14的第二区在基底上的正投影的范围之内，第八过孔K8内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第四有源层14的第二区的表面，第八过孔K8被配置为使后续形成的第三连接电极通过该过孔与第四有源层14的第二区连接。
在示例性实施方式中，第九过孔K9在基底上的正投影可以位于第五有源层15的第一区在基底上的正投影的范围之内，第九过孔K9内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第五有源层15的第一区的表面，第九过孔K9被配置为使后续形成的第三检测线通过该过孔与第五有源层15的第一区连接。
在示例性实施方式中，第十过孔K10在基底上的正投影可以位于第五有源层15的第二区在基底上的正投影的范围之内，第十过孔K10内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第五有源层15的第二区的表面，第十过孔K10被配置为使后续形成的第三连接电极通过该过孔与第五有源层15的第二区连接。
在示例性实施方式中，第十一过孔K11在基底上的正投影可以位于第一传输线71的第一连接块81在基底上的正投影的范围之内，第十一过孔K11内的第三绝缘层和第四绝缘层被刻蚀掉，暴露出第一连接块81的表面，第十一过孔K11被配置为使后续形成的第一连接电极通过该过孔与第一连接块81连接。
在示例性实施方式中，第十二过孔K12在基底上的正投影可以位于第二传输线72的第二连接块82在基底上的正投影的范围之内，第十二过孔K12内的第四绝缘层被刻蚀掉，暴露出第二连接块82的表面，第十二过孔K12被配置为使后续形成的第二连接电极通过该过孔与第二连接块82连接。在示例性实施方式中，第十二过孔K12可以为多个，以增加连接可靠性。
在示例性实施方式中，第十三过孔K13在基底上的正投影可以位于第二传输线72的第三连接块83在基底上的正投影的范围之内，第十三过孔K13内的第四绝缘层被刻蚀掉，暴露出第三连接块83的表面，第十三过孔K13被配置为使后续形成的第三连接电极通过该过孔与第三连接块83连接。在示例性实施方式中，第十三过孔K13可以为多个，以增加连接可靠性。
在示例性实施方式中，第十四过孔K14在基底上的正投影可以位于第一栅极连接线61在基底上的正投影的范围之内，第十四过孔K14内的第三绝缘层和第四绝缘层被刻蚀掉，暴露出第一栅极连接线61的第二端的表面，第十四过孔K14被配置为使后续形成的第一控制线通过该过孔与第一栅极连接线61连接。在示例性实施方式中，第十四过孔K14可以为多个，以增加连接可靠性。
在示例性实施方式中，第十五过孔K15在基底上的正投影可以位于第二栅极连接线 62在基底上的正投影的范围之内，第十五过孔K15内的第三绝缘层和第四绝缘层被刻蚀掉，暴露出第二栅极连接线62的第二端的表面，奇数检测单元中的第十五过孔K15被配置为使后续形成的第二控制线通过该过孔与第二栅极连接线62连接，偶数检测单元中的第十五过孔K15被配置为使后续形成的第三控制线通过该过孔与第二栅极连接线62连接。在示例性实施方式中，第十五过孔K15可以为多个，以增加连接可靠性。
在示例性实施方式中，第十六过孔K16在基底上的正投影可以位于第三栅极连接线63在基底上的正投影的范围之内，第十六过孔K16内的第三绝缘层和第四绝缘层被刻蚀掉，暴露出第三栅极连接线63的第二端的表面，奇数检测单元中的第十六过孔K16被配置为使后续形成的第三控制线通过该过孔与第三栅极连接线63连接，偶数检测单元中的第十六过孔K16被配置为使后续形成的第二控制线通过该过孔与第三栅极连接线63连接。在示例性实施方式中，第十六过孔K16可以为多个，以增加连接可靠性。
(4)形成第三导电层图案。在示例性实施方式中，形成第三导电层图案可以包括：在形成前述图案的基底上沉积第三导电薄膜，通过图案化工艺对第三导电薄膜进行图案化，在第四绝缘层上形成第三导电层图案，如图14所示。在示例性实施方式中，第三导电层可以称为第一源漏金属层(SD1)。
在示例性实施方式中，第三导电层图案可以包括第一控制线110、第二控制线120、第三控制线130、第一检测线210、第二检测线220、第三检测线230、第一连接电极91、第二连接电极92和第三连接电极93。
在示例性实施方式中，第一控制线110的形状可以为沿着第一方向X延伸的线形状。第一控制线110的第一端与绑定引脚区的引脚连接，第一控制线110第二端延伸到检测电路区，通过多个第十四过孔K14与每个检测单元中的第一栅极连接线61连接。由于第一栅极连接线61与第一栅电极21连接，因而第一控制线110传输的第一控制信号可以分别通过第一栅极连接线61传输给第一栅电极21，控制第一晶体管T1的导通和断开。
在示例性实施方式中，第二控制线120的形状可以为沿着第一方向X延伸的线形状。第二控制线120的第一端与绑定引脚区的引脚连接，第二控制线120的第二端延伸到检测电路区，一方面通过奇数检测单元中的第十五过孔K15与第二栅极连接线62连接，另一方面通过偶数检测单元中的第十六过孔K16与第三栅极连接线63连接。由于第二栅极连接线62与第二栅电极22和第三栅电极23连接，因而第二控制线120传输的第二控制信号可以控制奇数检测单元中的第二晶体管T2和第三晶体管T3的导通和断开。由于第三栅极连接线63与第四栅电极24和第五栅电极25连接，因而第二控制线120传输的第二控制信号可以控制偶数检测单元中的第四晶体管T4和第五晶体管T5的导通和断开。
在示例性实施方式中，第三控制线130的形状可以为沿着第一方向X延伸的线形状。第三控制线130的第一端与绑定引脚区的引脚连接，第三控制线130的第二端延伸到检测电路区，一方面通过奇数检测单元中的第十六过孔K16与第三栅极连接线63连接，另一方面通过偶数检测单元中的第十五过孔K15与第二栅极连接线62连接。由于第二栅极连接线62与第二栅电极22和第三栅电极23连接，因而第三控制线130传输的第三控制信号可以控制偶数检测单元中的第二晶体管T2和第三晶体管T3的导通和断开。由于第三栅极连接线63与第四栅电极24和第五栅电极25连接，因而第三控制线130传输的第三控制信号可以控制奇数检测单元中的第四晶体管T4和第五晶体管T5的导通和断开。
在示例性实施方式中，第一检测线210的形状可以为沿着第一方向X延伸的线形状，第一检测线210的第一端与绑定引脚区的引脚连接，第一检测线210的第二端延伸到检测电路区后，通过第一过孔K1与每个检测单元中的第一有源层11的第一区连接。
在示例性实施方式中，第二检测线220可以包括连接相同信号源的第一子线220-1和第二子线220-2。第一子线220-1的形状可以为沿着第一方向X延伸的线形状，第一子线 220-1的第一端与绑定引脚区的引脚连接，第一子线220-1的第二端延伸到检测电路区后，通过第三过孔K3与每个检测单元中的第二有源层12的第一区连接。第二子线220-2的形状可以为沿着第一方向X延伸的线形状，第二子线220-2的第一端与绑定引脚区的引脚连接，第二子线220-2的第二端延伸到检测电路区后，通过第五过孔K5与每个检测单元中的第三有源层13的第一区连接。
在示例性实施方式中，第三检测线230可以包括连接相同信号源的第三子线230-1和第四子线230-2。第三子线230-1的形状可以为沿着第一方向X延伸的线形状，第三子线230-1的第一端与绑定引脚区的引脚连接，第三子线230-1的第二端延伸到检测电路区后，通过第七过孔K7与每个检测单元中的第四有源层14的第一区连接。第四子线230-2的形状可以为沿着第一方向X延伸的线形状，第四子线230-2的第一端与绑定引脚区的引脚连接，第四子线230-2的第二端延伸到检测电路区后，通过第九过孔K9与每个检测单元中的第五有源层15的第一区连接。
在示例性实施方式中，第一连接电极91可以设置在每个检测单元的第一栅电极21第二方向Y的反方向的一侧(第一栅电极21远离第二栅电极22的一侧)，第一连接电极91的形状可以为沿着第二方向Y延伸的条形状。第一连接电极91的第一端通过第二过孔K2与第一有源层11的第二区连接，第一连接电极91的第二端通过第十一过孔K11与第一传输线71的第一连接块81连接，实现了第一晶体管T1可以控制第一检测线210与第一传输线71之间的导通和断开。在第一晶体管T1导通时，第一检测线210传输的第一信号传输给第一传输线71，第一传输线71将第一信号传输给显示区域中连接G子像素的数据信号线。
在示例性实施方式中，第二连接电极92可以设置在每个检测单元的第二栅电极22和第三栅电极23之间，第二连接电极92的形状可以为沿着第二方向Y延伸的条形状。第二连接电极92的第一端通过第四过孔K4与第二有源层12的第二区连接，第二连接电极92的第二端通过第六过孔K6与第三有源层13的第二区连接，第二连接电极92的中部(第一端与第二端之间)通过多个第十二过孔K12与第二传输线72的第二连接块82连接，实现了第二晶体管T2和第三晶体管T3可以控制第一子线220-1和第二子线220-2与第二传输线72之间的导通和断开。在第二晶体管T2和第三晶体管T3导通时，第一子线220-1和第二子线220-2传输的第二信号传输给第二传输线72，第二传输线72将第二信号传输给显示区域中连接B子像素和R子像素的数据信号线。
在示例性实施方式中，第三连接电极93可以设置在每个检测单元的第四栅电极24和第五栅电极25之间，第三连接电极93的形状可以为沿着第二方向Y延伸的条形状。第三连接电极93的第一端通过第八过孔K8与第四有源层14的第二区连接，第三连接电极93的第二端通过第十过孔K10与第五有源层15的第二区连接，第三连接电极93的中部(第一端与第二端之间)通过多个第十三过孔K13与第二传输线72的第三连接块83连接，实现了第四晶体管T4和第五晶体管T5可以控制第三子线230-1和第四子线230-2与第二传输线72之间的导通和断开。在第四晶体管T4和第五晶体管T5导通时，第三子线230-1和第四子线230-2传输的第三信号传输给第二传输线72，第二传输线72将第三信号传输给显示区域中连接B子像素和R子像素的数据信号线。
在示例性实施方式中，第一检测线210可以设置在第一晶体管T1第二方向Y(远离显示区域)的一侧。第一子线220-1可以设置在第二晶体管T2第二方向Y的反方向(靠近显示区域)的一侧，第二子线220-2可以设置在第三晶体管T3第二方向Y的一侧。第三子线230-1可以设置在第四晶体管T4第二方向Y的反方向的一侧，第四子线230-2可以设置在第五晶体管T5第二方向Y的一侧。
在示例性实施方式中，第一控制线110可以设置在第一检测线210与第一子线220-1 之间，第二控制线120和第三控制线130可以设置在第二子线220-2与第三子线230-1之间，且第三控制线130设置在第二控制线120第二方向Y的一侧。
至此，制备完成检测电路。检测电路可以包括沿着第一方向X依次设置的多个检测单元，至少一个检测单元可以包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5。第一晶体管T1的栅电极与第一控制线110连接，第一晶体管T1的第一极与第一检测线210连接，第一晶体管T1的第二极与第一传输线71连接。第二晶体管T2和第三晶体管T3的栅电极与第二控制线120连接，第二晶体管T2和第三晶体管T3的第一极与第二检测线220连接，第二晶体管T2和第三晶体管T3的第二极与第二传输线72连接。第四晶体管T4和第五晶体管T5的栅电极与第三控制线130连接，第四晶体管T4和第五晶体管T5的第一极与第三检测线230连接，第四晶体管T4和第五晶体管T5的第二极与第二传输线72连接。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层可称为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层可称之为栅绝缘(GI)层，第四绝缘层可称之为层间绝缘(ILD)层。第一导电层、第二导电层和第三导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或多种，或者上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。有源层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。
通过本示例性实施例显示基板的结构和制备过程可以看出，本公开通过将控制G子像素进行检测的第一开关单元设置在靠近显示区域的一侧，有效减小了检测单元的尺寸。与控制G子像素进行检测的第一开关单元设置在远离显示区域一侧的现有方案相比，本公开通过将控制G子像素进行检测的第一开关单元设置在靠近显示区域的一侧，不仅使得控制R子像素进行检测的第二开关单元和控制B子像素进行检测的第三开关单元中仅设置有连接R子像素和B子像素中数据信号线的第二传输线，而不再设置连接G子像素中数据信号线的第一传输线，有效减小了检测单元的宽度，而且避免了第一传输线和第二传输线之间的信号干扰，提高了检测质量。在不增加图案化工艺的情况下，本公开示例性实施例检测单元的宽度可以减少约20％左右，可以从现有结构的53μm左右减小到42μm左右，有效减小了检测单元的尺寸，有利于实现绑定区域窄化设计。本公开制备工艺利用成熟的制备设备即可实现，工艺改进较小、兼容性高，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高，具有良好的应用前景。
本公开示例性实施例还提供了一种显示基板的制备方法，以制备前述的显示基板。在示例性实施方式中，所述显示基板包括显示区域和位于所述显示区域一侧的绑定区域，所述显示区域至少包括构成多个像素列的多个子像素和多条数据信号线，所述绑定区域至少包括检测电路；所述多个像素列至少包括第一像素列和第二像素列，所述第一像素列包括多个出射第一颜色光线的第一子像素，所述第二像素列包括多个出射第二颜色光线的第二 子像素和多个出射第三颜色光线的第三子像素；所述多条数据信号线至少包括第一数据信号线和第二数据信号线，所述第一数据信号线与所述第一像素列中的多个第一子像素电连接，所述第二数据信号线与所述第二像素列中的多个第二子像素和第三子像素电连接；所述制备方法可以包括：
在所述绑定区域形成所述检测电路，所述检测电路包括多个检测单元，至少一个检测单元包括第一开关单元、第二开关单元、第三开关单元、第一传输线和第二传输线，所述第一开关单元通过所述第一传输线与所述第一数据信号线连接，所述第二开关单元和所述第三开关单元通过所述第二传输线与所述第二数据信号线连接，所述第二开关单元和所述第三开关单元设置在所述第一开关单元远离所述显示区域的一侧显示装置，
本公开示例性实施例还提供了一种显示装置，包括前述实施例的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (21)

  1. 一种显示基板，包括显示区域和位于所述显示区域一侧的绑定区域，所述显示区域至少包括构成多个像素列的多个子像素和多条数据信号线，所述绑定区域至少包括检测电路；所述多个像素列至少包括第一像素列和第二像素列，所述第一像素列包括多个出射第一颜色光线的第一子像素，所述第二像素列包括多个出射第二颜色光线的第二子像素和多个出射第三颜色光线的第三子像素；所述多条数据信号线至少包括第一数据信号线和第二数据信号线，所述第一数据信号线与所述第一像素列中的多个第一子像素电连接，所述第二数据信号线与所述第二像素列中的多个第二子像素和第三子像素电连接；所述检测电路包括多个检测单元，至少一个检测单元包括第一开关单元、第二开关单元、第三开关单元、第一传输线和第二传输线，所述第一开关单元通过所述第一传输线与所述第一数据信号线连接，所述第二开关单元和所述第三开关单元通过所述第二传输线与所述第二数据信号线连接；所述第二开关单元和所述第三开关单元设置在所述第一开关单元远离所述显示区域的一侧。
  2. 根据权利要求1所述的显示基板，其中，在所述绑定区域，所述第一传输线的延伸长度小于所述第二传输线的延伸长度。
  3. 根据权利要求1所述的显示基板，其中，所述第一子像素包括出射绿色光线的绿色子像素，所述第二子像素包括出射蓝色光线的蓝色子像素，所述第三子像素包括出射红色光线的红色子像素。
  4. 根据权利要求1至3任一项所述的显示基板，其中，所述检测电路还包括第一控制线和第一检测线；所述第一控制线与所述第一开关单元的控制端连接，所述第一检测线与所述第一开关单元的输入端连接，所述第一开关单元的输出端与所述第一传输线连接，所述第一开关单元被配置为在所述第一控制线的控制下，将所述第一检测线传输的信号通过所述第一传输线发送给所述第一数据信号线。
  5. 根据权利要求4所述的显示基板，其中，所述第一开关单元包括至少一个第一晶体管，所述第一控制线与所述第一晶体管的栅电极连接，所述第一检测线与所述第一晶体管的第一极连接，所述第一晶体管的第二极与所述第一传输线连接。
  6. 根据权利要求5所述的显示基板，其中，所述第一传输线设置在所述第一晶体管的栅电极靠近所述显示区域的一侧，所述第一检测线设置在所述第一晶体管的栅电极远离所述显示区域的一侧，所述第一控制线设置在所述第一检测线远离所述显示区域的一侧。
  7. 根据权利要求5所述的显示基板，其中，所述第一开关单元还包括第一栅极连接线，所述第一栅极连接线的第一端与所述第一晶体管的栅电极连接，所述第一栅极连接线的第二端沿着远离所述显示区域的方向延伸后，通过过孔与所述第一控制线连接。
  8. 根据权利要求5所述的显示基板，其中，所述第一开关单元还包括第一连接电极，所述第一连接电极的第一端通过过孔与所述第一晶体管的第一极连接，所述第一连接电极的第二端通过过孔与所述第一传输线连接。
  9. 根据权利要求1至3任一项所述的显示基板，其中，所述检测电路还包括第二控制线、第三控制线、第二检测线和第三检测线；所述第二控制线分别与奇数检测单元中第二开关单元的控制端和偶数检测单元中第三开关单元的控制端连接，所述第三控制线分别与奇数检测单元中第三开关单元的控制端和偶数检测单元中第二开关单元的控制端连接；所述第二检测线与所述第二开关单元的输入端连接，所述第三检测线与所述第三开关单元的输入端连接；所述第二开关单元的输出端与所述第二传输线连接，所述第三开关单元的输出端与所述第二传输线连接；所述第二开关单元被配置为在所述第二控制线和第三控制线的控制下，将所述第二检测线传输的信号通过所述第二传输线发送给所述第二数据信号 线，所述第三开关单元被配置为在所述第二控制线和第三控制线的控制下，将所述第三检测线传输的信号通过所述第二传输线发送给所述第二数据信号线。
  10. 根据权利要求9所述的显示基板，其中，所述第二开关单元包括至少一个第二晶体管和至少一个第三晶体管，所述第三开关单元包括至少一个第四晶体管和至少一个第五晶体管；所述第二控制线分别与奇数检测单元中第二晶体管的栅电极和第三晶体管的栅电极、偶数检测单元中第四晶体管的栅电极和第五晶体管的栅电极连接；所述第三控制线分别与奇数检测单元中第四晶体管的栅电极和第五晶体管的栅电极、偶数检测单元中第二晶体管的栅电极和第三晶体管的栅电极连接；所述第二检测线分别与所述第二晶体管的第一极和所述第三晶体管的第一极连接，所述第三检测线分别与所述第四晶体管的第一极和所述第五晶体管的第一极连接；所述第二晶体管的第二极、所述第三晶体管的第二极、所述第四晶体管的第二极以及所述第五晶体管的第二极与所述第二传输线连接。
  11. 根据权利要求10所述的显示基板，其中，所述第三晶体管设置在所述第二晶体管远离所述显示区域的一侧，所述第四晶体管设置在所述第三晶体管远离所述显示区域的一侧，所述第五晶体管设置在所述第四晶体管远离所述显示区域的一侧。
  12. 根据权利要求10所述的显示基板，其中，所述第二检测线包括第一子线和第二子线；所述第一子线设置在所述第二晶体管靠近所述显示区域的一侧，且与所述第二晶体管的第一极连接；所述第二子线设置在所述第三晶体管远离所述显示区域的一侧，且与所述第三晶体管的第一极连接；所述第二控制线设置在所述第二子线远离所述显示区域的一侧。
  13. 根据权利要求10所述的显示基板，其中，所述第二开关单元还包括第二栅极连接线，所述第二栅极连接线的第一端分别与所述第二晶体管的栅电极和第三晶体管的栅电极连接，所述第二栅极连接线的第二端沿着远离所述显示区域的方向延伸后，通过过孔与所述第二控制线或者所述第三控制线连接。
  14. 根据权利要求10所述的显示基板，其中，所述第二开关单元还包括第二连接电极，所述第二连接电极通过过孔分别与所述第二晶体管的第二极、所述第三晶体管的第二极和所述第二传输线连接。
  15. 根据权利要求14所述的显示基板，其中，所述第二开关单元还包括第二连接块，所述第二连接块与所述第二传输线连接，所述第二连接电极通过过孔与所述第二连接块连接，所述第二连接块和所述第二传输线同层设置，且为相互连接的一体结构。
  16. 根据权利要求10所述的显示基板，其中，所述第三检测线包括第三子线和第四子线；所述第三子线设置在所述第四晶体管靠近所述显示区域的一侧，且与所述第四晶体管的第一极连接；所述第四子线设置在所述第五晶体管远离所述显示区域的一侧，且与所述第五晶体管的第一极连接；所述第三控制线设置在所述第三子线靠近所述显示区域的一侧。
  17. 根据权利要求16所述的显示基板，其中，所述第三开关单元还包括第三栅极连接线，所述第三栅极连接线的第一端分别与所述第四晶体管的栅电极和第五晶体管的栅电极连接，所述第三栅极连接线的第二端沿着靠近所述显示区域的方向延伸后，通过过孔与所述第二控制线或者所述第三控制线连接。
  18. 根据权利要求16所述的显示基板，其中，所述第三开关单元还包括第三连接电极，所述第三连接电极通过过孔分别与所述第四晶体管的第二极、所述第五晶体管的第二极和所述第二传输线连接。
  19. 根据权利要求18所述的显示基板，其中，所述第三开关单元还包括第三连接块，所述第三连接块与所述第二传输线连接，所述第三连接电极通过过孔与所述第三连接块连接，所述第三连接块和所述第二传输线同层设置，且为相互连接的一体结构。
  20. 一种显示装置，包括如权利要求1至19任一项所述的显示基板。
  21. 一种显示基板的制备方法，所述显示基板包括显示区域和位于所述显示区域一侧的绑定区域，所述显示区域至少包括构成多个像素列的多个子像素和多条数据信号线，所述绑定区域至少包括检测电路；所述多个像素列至少包括第一像素列和第二像素列，所述第一像素列包括多个出射第一颜色光线的第一子像素，所述第二像素列包括多个出射第二颜色光线的第二子像素和多个出射第三颜色光线的第三子像素；所述多条数据信号线至少包括第一数据信号线和第二数据信号线，所述第一数据信号线与所述第一像素列中的多个第一子像素电连接，所述第二数据信号线与所述第二像素列中的多个第二子像素和第三子像素电连接；所述制备方法包括：
    在所述绑定区域形成所述检测电路，所述检测电路包括多个检测单元，至少一个检测单元包括第一开关单元、第二开关单元、第三开关单元、第一传输线和第二传输线，所述第一开关单元通过所述第一传输线与所述第一数据信号线连接，所述第二开关单元和所述第三开关单元通过所述第二传输线与所述第二数据信号线连接，所述第二开关单元和所述第三开关单元设置在所述第一开关单元远离所述显示区域的一侧。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140240521A1 (en) * 2013-02-28 2014-08-28 Samsung Display Co., Ltd. Organic light emitting display panel
CN114120905A (zh) * 2021-11-12 2022-03-01 合肥京东方卓印科技有限公司 显示基板及其制备方法、显示装置
CN114495795A (zh) * 2022-02-21 2022-05-13 京东方科技集团股份有限公司 显示基板及显示装置
CN114613325A (zh) * 2022-02-21 2022-06-10 京东方科技集团股份有限公司 显示基板及显示装置
CN116056504A (zh) * 2022-10-20 2023-05-02 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140240521A1 (en) * 2013-02-28 2014-08-28 Samsung Display Co., Ltd. Organic light emitting display panel
CN114120905A (zh) * 2021-11-12 2022-03-01 合肥京东方卓印科技有限公司 显示基板及其制备方法、显示装置
CN114495795A (zh) * 2022-02-21 2022-05-13 京东方科技集团股份有限公司 显示基板及显示装置
CN114613325A (zh) * 2022-02-21 2022-06-10 京东方科技集团股份有限公司 显示基板及显示装置
CN116056504A (zh) * 2022-10-20 2023-05-02 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

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