WO2022104615A1 - 显示面板、驱动方法及显示装置 - Google Patents

显示面板、驱动方法及显示装置 Download PDF

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Publication number
WO2022104615A1
WO2022104615A1 PCT/CN2020/129900 CN2020129900W WO2022104615A1 WO 2022104615 A1 WO2022104615 A1 WO 2022104615A1 CN 2020129900 W CN2020129900 W CN 2020129900W WO 2022104615 A1 WO2022104615 A1 WO 2022104615A1
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WIPO (PCT)
Prior art keywords
base substrate
sub
orthographic projection
reset
transistor
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Application number
PCT/CN2020/129900
Other languages
English (en)
French (fr)
Inventor
王铸
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080002835.4A priority Critical patent/CN114830223A/zh
Priority to PCT/CN2020/129900 priority patent/WO2022104615A1/zh
Priority to US18/250,276 priority patent/US20240008326A1/en
Priority to GB2309034.3A priority patent/GB2616206A/en
Publication of WO2022104615A1 publication Critical patent/WO2022104615A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage

Definitions

  • the embodiments of the present disclosure relate to the field of display technology, and in particular, to a display panel, a driving method, and a display device.
  • organic light-emitting diode Organic Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • a base substrate including a plurality of sub-pixels
  • an active semiconductor layer located on the base substrate
  • a gate insulating layer located on the side of the active semiconductor layer away from the base substrate;
  • a first conductive layer located on the side of the gate insulating layer away from the base substrate;
  • an interlayer dielectric layer located on the side of the first conductive layer away from the base substrate;
  • a second conductive layer located on the side of the interlayer dielectric layer away from the base substrate;
  • a first interlayer insulating layer located on the side of the second conductive layer away from the base substrate;
  • the third conductive layer located on the side of the first interlayer insulating layer away from the base substrate; the third conductive layer includes a plurality of first signal lines arranged at intervals;
  • a second interlayer insulating layer located on the side of the third conductive layer away from the base substrate;
  • the fourth conductive layer located on the side of the second interlayer insulating layer away from the base substrate; the fourth conductive layer includes a plurality of second signal lines arranged at intervals;
  • the orthographic projection of the first signal line on the base substrate and the orthographic projection of the second signal line on the base substrate are arranged to intersect.
  • the first signal line is a data line
  • the second signal line is a power line
  • the first conductive layer includes a plurality of scan lines arranged at intervals; the extension direction of the scan lines is the same as the extension direction of the power supply lines;
  • the fourth conductive layer further includes a plurality of reset lines arranged at intervals; the extension direction of the reset lines is the same as the extension direction of the power lines;
  • the orthographic projection of the scan lines on the base substrate is located at the orthographic projection of the power lines on the base substrate and the reset line between the orthographic projections of the base substrate.
  • the pixel circuit includes: a drive transistor, a data write transistor, a reset transistor, and a storage capacitor;
  • the first pole of the driving transistor is electrically connected to the power supply line, and the second pole of the driving transistor is electrically connected to the light-emitting element;
  • the first plate of the storage capacitor is electrically connected to the gate of the drive transistor, and the second plate of the storage capacitor is electrically connected to the second pole of the drive transistor;
  • the gate of the data writing transistor is electrically connected to the scan line, the first pole of the data writing transistor is electrically connected to the data line, and the second pole of the data writing transistor is electrically connected to the driving transistor Grid electrical connection;
  • the gate of the reset transistor is electrically connected to the scan line, the first electrode of the reset transistor is electrically connected to the reset line, and the second electrode of the reset transistor is electrically connected to the second electrode of the driving transistor.
  • the active semiconductor layer includes an active region of the drive transistor; the first conductive layer includes a first plate of the storage capacitor; and the first plate of the storage capacitor is multiplexed is the gate of the drive transistor;
  • the orthographic projection of the first electrode plate of the storage capacitor on the base substrate and the orthographic projection of the active region of the driving transistor on the base substrate have an overlapping area ;
  • the channel region of the active region of the driving transistor includes a first driving channel region and a second driving channel region which are connected to each other; direction, the channel of the second driving region extends along the third direction, and the included angle ⁇ between the first direction and the third direction satisfies 0° ⁇ 90°.
  • the active semiconductor layer further includes an active region of the reset transistor; wherein the active region of the reset transistor extends along the first direction, and the active region of the reset transistor is located in the the second driving channel region of the driving transistor is away from the side of the first driving channel region;
  • the conductive drain region of the active region of the reset transistor is connected to the second driving channel region of the driving transistor.
  • the active semiconductor layer further includes an active region of the data writing transistor; the active region of the data writing transistor is respectively connected with the active region of the reset transistor and the driving transistor.
  • the active regions are arranged at intervals; wherein, the active regions of the data writing transistors extend along the first direction;
  • the orthographic projection of the active region of the data writing transistor in the second direction is located away from the orthographic projection of the second driving channel region of the driving transistor in the second direction One side of the orthographic projection of the active region of the reset transistor in the second direction.
  • the channel region of the active region of the data writing transistor and the channel region of the active region of the reset transistor are arranged along the second direction.
  • one row of sub-pixels corresponds to one scan line; in the same sub-pixel, the orthographic projection of the scan line on the base substrate is respectively the same as the channel of the active region of the data writing transistor.
  • the region has an overlapping region with the channel region of the active region of the reset transistor.
  • the second conductive layer includes a data transfer portion in each of the sub-pixels
  • the first electrode plate of the storage capacitor includes a first electrode plate body portion and a first electrode plate protrusion portion that are electrically connected to each other;
  • the first end of the data transfer portion is electrically connected to the conductive drain region of the active region of the data writing transistor through a first via hole, and the first end of the data transfer portion is electrically connected to the conductive drain region of the active region of the data writing transistor.
  • Two ends are electrically connected to the first plate protrusion through a second via hole; wherein the first via hole penetrates the gate insulating layer and the interlayer dielectric layer, and the second via hole penetrates the interlayer dielectric layer.
  • the second conductive layer further includes a second electrode plate of the storage capacitor; wherein, the second electrode plate of the storage capacitor includes a second electrode plate body portion and a second electrode plate that are electrically connected to each other. protrusion;
  • the second electrode plate protrusion is electrically connected to the conductive drain region of the active region of the reset transistor through a third via hole; wherein the third via hole penetrates the layer an intermediary dielectric layer and the gate insulating layer.
  • the orthographic projection of the first plate body portion on the base substrate overlaps with the orthographic projection of the second plate body portion on the base substrate area.
  • the second electrode plate of the storage capacitor further includes: a second electrode plate compensation portion electrically connected to the second electrode plate body portion and the second electrode plate protrusion portion, respectively; wherein the The second pole plate compensation part is located at the corner formed by the second pole plate main body part and the second pole plate protruding part;
  • the orthographic projection of the second electrode plate compensation portion on the base substrate and the orthographic projection of the first electrode plate main portion on the base substrate have an overlapping area.
  • the orthographic projection of the first electrode plate body portion on the base substrate and the orthographic projection of the second electrode plate protrusion portion on the base substrate are close to the base substrate.
  • the second plate body portion has an overlapping area at the edge of the orthographic projection of the base substrate.
  • one column of the sub-pixels corresponds to one of the data lines
  • the data line is electrically connected to the conductive source region of the active region of the data writing transistor through a fourth via hole, wherein the fourth via hole penetrates the first layer an interlayer insulating layer, the interlayer dielectric layer and the gate insulating layer, and the orthographic projection of the fourth via hole on the base substrate is located at the orthographic projection of the scan line on the base substrate away from the The first plate of the storage capacitor is on one side of the orthographic projection of the base substrate.
  • one of the power lines is arranged corresponding to at least one row of the sub-pixels
  • the third conductive layer further includes a plurality of power transfer parts arranged at intervals; wherein, in the same sub-pixel, the power line is electrically connected to the power transfer part through a fifth via hole, and the power transfer part is electrically connected to the power transfer part.
  • the connecting portion is electrically connected to the conductive source region of the active region of the driving transistor through a sixth via hole; wherein the fifth via hole penetrates the second interlayer insulating layer, and the sixth via hole penetrates the first interlayer insulating layer, the interlayer dielectric layer and the gate insulating layer.
  • one of the reset lines is set corresponding to at least one row of sub-pixels
  • the third conductive layer further includes a plurality of reset transfer parts arranged at intervals; in the same sub-pixel, the reset line is electrically connected to the reset transfer part through a seventh via hole, and the reset transfer part It is electrically connected to the conductive source region of the active region of the reset transistor through an eighth via hole; wherein the seventh via hole penetrates the second interlayer insulating layer, and the eighth via hole penetrates the a first interlayer insulating layer, the interlayer dielectric layer and the gate insulating layer.
  • the fourth conductive layer further includes a plurality of anode connection parts arranged at intervals;
  • the third conductive layer further includes a plurality of anode connection parts arranged at intervals; wherein, one of the sub-pixels includes one of all the anode connection part and one of the anode adapter parts;
  • the anode connecting portion is electrically connected to the first end of the anode transfer portion through a ninth via hole, and the second end of the anode transfer portion is electrically connected to the storage device through a tenth via hole.
  • the second electrode plate of the capacitor is electrically connected; wherein the ninth via hole penetrates the second interlayer insulating layer, and the tenth via hole penetrates the first interlayer insulating layer.
  • the orthographic projection of the ninth via hole on the base substrate and the orthographic projection of the tenth via hole on the base substrate are arranged along the first direction .
  • the orthographic projection of the tenth via hole on the base substrate is located at the orthographic projection of the ninth via hole on the base substrate away from the third via hole on the side of the orthographic projection of the base substrate.
  • the orthographic projection of the ninth via hole on the base substrate and the orthographic projection of the second plate compensation portion on the base substrate have an overlapping area.
  • an orthographic projection of the anode connection portion on the base substrate and an orthographic projection of the data line on the base substrate have an overlapping area.
  • the anode connection portion is at a corner between an orthographic projection of the base substrate and the first driving channel region and the second driving channel region
  • the orthographic projection of the base substrate has an overlapping area.
  • the overlapping area of the orthographic projection of the anode connecting portion on the base substrate and the orthographic projection of the second driving channel region on the base substrate is greater than An orthographic projection of the anode connection portion on the base substrate and an orthographic projection of the first driving channel region on the base substrate overlap region.
  • the orthographic projection of the portion of the anode transfer portion close to the ninth via on the base substrate is the same as the first driving channel region and the second driving channel region.
  • the corners between the drive channel regions have overlapping regions in the orthographic projection of the base substrate.
  • the anode connection parts are arranged along the first direction and are not arranged on the same straight line;
  • the anode connecting parts are arranged along the first direction and are not arranged on the same straight line.
  • the anode transfer parts are arranged on the same straight line along the first direction;
  • the anode transfer parts are arranged on the same straight line along the second direction.
  • the pixel circuits are arranged symmetrically in the orthographic projection of the base substrate.
  • two adjacent rows of sub-pixels are used as a row group, and different sub-pixels included in the row groups are different;
  • the two scan lines corresponding to the row group have a row symmetry axis along the row direction, and the orthographic projection of the pixel circuits in the sub-pixels of the same row group on the base substrate is mirror-symmetrical about the row symmetry axis.
  • two adjacent columns of sub-pixels in the same row group are used as a column group, and different sub-pixels included in the column groups are different;
  • the two data lines corresponding to the column group have a column symmetry axis along the column direction, and the orthographic projection of the pixel circuits in the sub-pixels of the same column group on the base substrate is mirror-symmetrical about the column symmetry axis .
  • the display panel further includes: a first electrode layer located on a side of the fourth conductive layer away from the base substrate; the first electrode layer includes an anode located in each sub-pixel;
  • a pixel defining layer located on the side of the first electrode layer away from the base substrate;
  • the pixel defining layer includes a plurality of opening regions, one of the anodes corresponds to one of the opening regions, and in the same sub-pixel, the orthographic projection of the opening regions on the base substrate is located in the corresponding opening region. the anode is in the orthographic projection of the base substrate;
  • the orthographic projection of the power supply line on the base substrate passes through the orthographic projection of the opening region in the at least two sub-pixels on the base substrate.
  • sub-pixels in the same row group share one of the power lines
  • the orthographic projections of the pixel circuits in the same column and located on both sides of the power supply line on the base substrate are symmetrically arranged with respect to the orthographic projection of the power supply line on the base substrate.
  • the active semiconductor layer further includes a plurality of driving protrusions; the conductive source regions of the driving transistors in the two sub-pixels in the same column of the row group are electrically connected to one driving protrusion; wherein the same In the driving transistor, the conductive source region and the first driving channel region are electrically connected, and the conductive source region and the first driving channel region that are electrically connected to each other extend in the same direction ;
  • the orthographic projection of the driving protrusion on the base substrate is located on the base substrate, and the orthographic projection of the conductive source region on the base substrate is away from the data line on the base substrate.
  • the power transfer portion is electrically connected to the driving protrusion electrically connected to the driving transistor through a sixth via hole, and the driving protrusion electrically connected to the driving transistor covers the sixth through the orthographic projection of the base substrate.
  • an extension line of the active region of the reset transistor in the column direction and the driving protrusion have an overlapping region.
  • the orthographic projection of the fifth via on the base substrate is located at an orthographic projection of the sixth via on the base substrate away from the data line. one side of the orthographic projection of the base substrate.
  • the drive transistors in the same column group share one of the power transitions.
  • the orthographic projection of the power line on the base substrate covers the orthographic projection of the electrically connected power adapter on the base substrate.
  • two adjacent rows of sub-pixels located in different row groups share a reset line
  • the orthographic projections of the pixel circuits in the same column and located on both sides of the reset line on the base substrate are symmetrically arranged with respect to the orthographic projection of the reset line on the base substrate.
  • two adjacent columns of sub-pixels in the two rows of sub-pixels share one reset transition portion.
  • the orthographic projection of the reset line on the base substrate covers the orthographic projection of the electrically connected reset transition portion on the base substrate.
  • the orthographic projection of the seventh via hole on the base substrate is located at a position away from the data line in the orthographic projection of the eighth via hole on the base substrate. one side of the orthographic projection of the base substrate.
  • the data signal on the data line is transmitted to the conductive source region of the active region of the data write transistor through the fourth via;
  • the data signal transmitted to the conductorized source region of the active region of the data writing transistor is transmitted to the conductor of the active region of the data writing transistor through the channel region of the active region of the data writing transistor the drain region;
  • the data signal transmitted to the conductive drain region of the active region of the data writing transistor is transmitted to the data transfer part through the first via hole;
  • the data is transmitted to the first plate of the storage capacitor through the second via hole.
  • the reset signal on the reset line is transmitted through the eighth via to the conductive source region of the active region of the reset transistor;
  • a reset signal transmitted to the conductive source region of the active region of the reset transistor is transmitted to the conductive drain region of the active region of the reset transistor through the channel region of the active region of the reset transistor;
  • the reset signal transmitted to the conductive drain region of the active region of the reset transistor is transmitted to the second plate of the storage capacitor through the third via hole;
  • the reset signal transmitted to the second plate of the storage capacitor is transmitted to the anode adapter through the tenth via hole;
  • the reset signal transmitted to the anode transfer part is transmitted to the anode connection part through the ninth via hole.
  • the power signal of the power line is transmitted to the power adapter through the fifth via;
  • the power signal transmitted to the power transfer part is transmitted to the driving protrusion to which the driving transistor is electrically connected through the sixth via hole.
  • the drive current generated by the drive transistor is transmitted to the second plate of the storage capacitor through a third via hole;
  • the driving current transmitted to the second plate of the storage capacitor is transmitted to the anode adapter through the tenth via hole;
  • the driving current transmitted to the anode transfer part is transmitted to the anode connection part through the ninth via hole.
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned display panel.
  • the turn-on control signal is loaded on each scan line, the reset signal is loaded on the reset line, and the initialization signal is loaded on the data line, so as to simultaneously initialize the gate of each driving transistor and reset each light-emitting element;
  • a turn-on control signal is sequentially applied to the scan line, a reset signal is applied to the reset line, and when the turn-on control signal is applied to the scan line, corresponding data is applied to the data line a signal to input a data signal to the gate of each of the driving transistors;
  • a cut-off control signal is simultaneously applied to each of the scanning lines, and each of the driving transistors generates a driving current to drive the electrically connected light-emitting elements to emit light.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure
  • FIG. 2a is a schematic structural diagram of some pixel circuits according to an embodiment of the present disclosure.
  • FIG. 2b is a signal timing diagram provided by an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of the layout structure of some display panels according to an embodiment of the present disclosure.
  • FIG. 4a is a schematic diagram of a layout structure of an active semiconductor layer provided by an embodiment of the present disclosure.
  • FIG. 4b is a schematic diagram of a layout structure of a first conductive layer provided by an embodiment of the present disclosure
  • FIG. 4c is a schematic diagram of a layout structure of a second conductive layer provided by an embodiment of the present disclosure.
  • FIG. 4d is a schematic diagram of a layout structure of a third conductive layer provided by an embodiment of the present disclosure.
  • FIG. 4e is a schematic diagram of a layout structure of a fourth conductive layer according to an embodiment of the present disclosure.
  • 5a is a schematic diagram of a stacked layout structure of an active semiconductor layer and a first conductive layer according to an embodiment of the present disclosure
  • 5b is a schematic diagram of a stacked layout structure of an active semiconductor layer, a first conductive layer, and a second conductive layer according to an embodiment of the present disclosure
  • 5c is a schematic diagram of a stacked layout structure of an active semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of the layout structure of further display panels according to an embodiment of the present disclosure.
  • FIG. 7a is a schematic diagram of a layout structure of a first electrode layer provided by an embodiment of the present disclosure.
  • FIG. 7b is a schematic diagram of a layout structure of a light-emitting layer according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a stacked layout structure of a fourth conductive layer, a first electrode layer, and a light-emitting layer according to an embodiment of the present disclosure.
  • the display panel provided by the embodiment of the present disclosure may include: a base substrate 10 .
  • the base substrate 10 includes a plurality of sub-pixels spx.
  • each sub-pixel spx may include: a pixel circuit 0121 and a light-emitting element 0120 .
  • the pixel circuit 0121 has a transistor and a capacitor, and generates an electrical signal through the interaction of the transistor and the capacitor, and the generated electrical signal is input to the anode of the light-emitting element 0120 .
  • a corresponding voltage is applied to the cathode of the light-emitting element 0120, so that the light-emitting element 0120 can be driven to emit light.
  • the sub-pixels may be arranged in an array on the base substrate. In this way, a plurality of sub-pixels can be arranged along the first direction F1 and the second direction F2 intersecting with the first direction, respectively.
  • the first direction F1 may be the column direction
  • the second direction F2 may be the row direction
  • the first direction F1 may be the row direction
  • the second direction F2 may be the column direction. The following description will be given by taking the first direction F1 as the column direction and the second direction F2 as the row direction as an example.
  • the pixel circuit 0121 includes: a driving transistor T3, a data writing transistor T1, a reset transistor T2, and a storage capacitor CST;
  • the first pole of the driving transistor T3 is electrically connected to the power line ELVDD, and the second pole of the driving transistor T3 is electrically connected to the light-emitting element;
  • the first plate CC1 of the storage capacitor CST is electrically connected to the gate of the drive transistor T3, and the second plate CC2 of the storage capacitor CST is electrically connected to the second pole of the drive transistor T3;
  • the gate of the data writing transistor T1 is electrically connected to the scan line GA, the first pole of the data writing transistor T1 is electrically connected to the data line DA, and the second pole of the data writing transistor T1 is electrically connected to the gate of the driving transistor T3;
  • the gate of the reset transistor T2 is electrically connected to the scan line GA, the first pole of the reset transistor T2 is electrically connected to the reset line VREF, and the second pole of the reset transistor T2 is electrically connected to the second pole of the driving transistor T3.
  • the light-emitting element 0120 can be configured as an electroluminescent diode, such as an organic light-emitting diode (Organic Light Emitting Diode, OLED), a quantum dot light-emitting diode (Quantum Dot Light Emitting Diodes, QLED), a micro light-emitting diode (Micro Light Emitting Diodes, Micro Light Emitting Diodes, Micro Light Emitting Diodes, Micro Light Emitting Diodes, Micro Light Emitting Diodes, Micro LED), at least one of Mini Light Emitting Diodes (Mini OLED).
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • Micro light-emitting diode Micro Light-emitting diode
  • Mini Light Emitting Diodes Mini OLED
  • the light-emitting element 0120 may include a stacked anode, a light-emitting layer, and a cathode. Further, the light-emitting layer may also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. Of course, in practical applications, the light-emitting element 0120 can be designed and determined according to the requirements of the actual application environment, which is not limited herein.
  • the power line ELVDD can transmit a constant first voltage, for example, the first voltage is a positive voltage; and the ELVSS terminal connected to the cathode of the light-emitting element 0120 can output a constant second voltage, for example, the second voltage is 0 or negative. voltage, etc.
  • the ELVSS terminal may be grounded.
  • the first electrode of the above transistor can be used as its source electrode, and the second electrode can be used as its drain electrode.
  • the first electrode of the transistor can be used as its drain electrode, and the second electrode can be used as its source electrode, which is not limited herein.
  • the above-mentioned driving method of the display panel provided by the embodiments of the present disclosure may include:
  • the turn-on control signal is loaded on each scan line, the reset signal is loaded on the reset line, and the initialization signal is loaded on the data line, so as to simultaneously initialize the gate of each driving transistor and reset each light-emitting element;
  • a turn-on control signal is applied to the scan line in turn, and a reset signal is applied to the reset line.
  • a cut-off control signal is simultaneously applied to each scanning line, and each driving transistor generates a driving current to drive the electrically connected light-emitting elements to emit light.
  • the above-mentioned driving method will be explained and described below through embodiments.
  • the signal timing diagram corresponding to the pixel circuit shown in FIG. 2a is shown in FIG. 2b.
  • the working process of the pixel circuit in the display panel can have three stages: T10 stage, T20 stage, and T30 stage.
  • ga-1 represents the signal transmitted on the scan line GA to which the pixel circuits in the first row of sub-pixels are electrically connected
  • ga-2 represents the signal transmitted on the scan line GA to which the pixel circuits in the second row of sub-pixels are electrically connected
  • ga-3 represents the signal transmitted on the scan line GA to which the pixel circuits in the third row of sub-pixels are electrically connected
  • ga-N represents the signal transmitted on the scan line GA to which the pixel circuits in the Nth row of sub-pixels are electrically connected.
  • N is the total number of rows of sub-pixels.
  • a turn-on control signal is loaded on each scan line GA
  • a reset signal is loaded on the reset line VREF
  • an initialization signal is loaded on the data line DA, so as to simultaneously initialize the gates of each driving transistor T3 and reset the Each light-emitting element is reset.
  • the signals transmitted on each scan line GA are all high-level signals (ie, turn-on control signals)
  • the data writing transistor T1 and the reset transistor T2 in the sub-pixels in the first row to the N-th row are all turned on. Pass.
  • the turned-on data writing transistor T1 inputs the initialization signal loaded on the data line DA to the gate of the driving transistor T3 to initialize the gate of the driving transistor T3.
  • the turned-on reset transistor T2 inputs the reset signal loaded on the reset line VREF to the anode of the light-emitting element to reset the anode of the light-emitting element.
  • the working process in the remaining sub-pixels is the same, which is not repeated here.
  • the scan line GA is loaded with the turn-on control signal
  • the reset line VREF is loaded with the reset signal
  • the data line DA is loaded with the corresponding data signal , to input a data signal to the gate of each driving transistor T3.
  • the T20 stage may include: the T21 stage, the T22 stage, the T23 stage, and the T2N stage that appear in sequence.
  • the signal ga-1 transmitted on the scan line GA to which the pixel circuits of the first row of sub-pixels are electrically connected is a high-level signal (ie, the turn-on control signal), and the signals from the second row of sub-pixels to the Nth row of sub-pixels are at a high level.
  • the signals ga-2 to ga-N transmitted on the scan line GA electrically connected to the pixel circuit are all low-level signals (ie, cut-off control signals), then the data writing transistor T1 and the reset transistor T2 in the first row of sub-pixels are both low-level signals. is turned on, the data writing transistor T1 and the reset transistor T2 in the sub-pixels in the second row to the N-th row are all turned off.
  • the data writing transistor T1 inputs the data signal loaded on the data line DA to the gate of the driving transistor T3, so that the voltage of the gate of the driving transistor T3 is the voltage Vda1 of the data signal.
  • the turned-on reset transistor T2 inputs the reset signal loaded on the reset line VREF to the anode of the light-emitting element to reset the anode of the light-emitting element.
  • the signal ga-2 transmitted on the scan line GA to which the pixel circuits of the second row of sub-pixels are electrically connected is a high-level signal (ie, the turn-on control signal).
  • the signals ga-1, ga-3 to ga-N transmitted on the scan line GA electrically connected to the pixel circuits of the sub-pixels in the Nth row are all low-level signals (ie, cut-off control signals), then the signals in the sub-pixels in the second row
  • the data writing transistor T1 and the reset transistor T2 are both turned on, the data writing transistor T1 and the reset transistor T2 in the first row of sub-pixels, the third row of sub-pixels to the Nth row of sub-pixels are all turned off, and the second row of sub-pixels is turned off.
  • the turned-on data writing transistor T1 inputs the data signal loaded on the data line DA to the gate of the driving transistor T3, so that the voltage of the gate of the driving transistor T3 is The voltage Vda2 of the data signal.
  • the turned-on reset transistor T2 inputs the reset signal loaded on the reset line VREF to the anode of the light-emitting element to reset the anode of the light-emitting element.
  • the signal ga-3 transmitted on the scan line GA to which the pixel circuits of the third row of sub-pixels are electrically connected is a high-level signal (that is, a turn-on control signal), and the first row of sub-pixels, the second row of sub-pixels,
  • the signals ga-1 to ga-2 and ga-4 to ga-N transmitted on the scan line GA electrically connected to the pixel circuits of the sub-pixels in the fourth row to the sub-pixels in the Nth row are all low-level signals (ie, cut-off control signals).
  • the data writing transistor T1 and the reset transistor T2 in the third row of sub-pixels are both turned on, and the data writing in the first row of sub-pixels, the second row of sub-pixels, the fourth row of sub-pixels to the N-th row of sub-pixels
  • the input transistor T1 and the reset transistor T2 are both turned off. Taking a sub-pixel in the third row of sub-pixels as an example, in this sub-pixel, the data writing transistor T1 that is turned on inputs the data signal loaded on the data line DA to the driving transistor.
  • the gate of T3 is set so that the voltage of the gate of the drive transistor T3 is the voltage Vda3 of the data signal.
  • the turned-on reset transistor T2 inputs the reset signal loaded on the reset line VREF to the anode of the light-emitting element to reset the anode of the light-emitting element.
  • the signal ga-N transmitted on the scan line GA to which the pixel circuits of the sub-pixels in the Nth row are electrically connected is a high-level signal (that is, a turn-on control signal).
  • the signals ga-1 to ga-N-1 transmitted on the scan line GA electrically connected to the pixel circuit of the pixel are all low-level signals (ie, cut-off control signals), then the data writing transistors T1 and The reset transistors T2 are all turned on, and the data writing transistors T1 and the reset transistors T2 in the sub-pixels in the first row to the sub-pixels in the N-1 row are all turned off.
  • the turned-on data writing transistor T1 inputs the data signal loaded on the data line DA to the gate of the driving transistor T3, so that the voltage of the gate of the driving transistor T3 is the voltage VdaN of the data signal.
  • the turned-on reset transistor T2 inputs the reset signal loaded on the reset line VREF to the anode of the light-emitting element to reset the anode of the light-emitting element.
  • the cut-off control signal is simultaneously applied to each scanning line GA, and each driving transistor T3 generates a driving current to drive the electrically connected light-emitting elements to emit light.
  • the signals transmitted on each scan line GA are all low-level signals (ie, turn-off control signals)
  • the data writing transistors T1 and the reset transistors T2 in the sub-pixels in the first row to the N-th row are all turned off.
  • the voltage of the gate of the driving transistor T3 is Vda1
  • the voltage of the first electrode of the driving transistor T3 is the voltage Vdd transmitted on the power line ELVDD
  • the driving current Ids is input to the light-emitting element, and the light-emitting element is driven to emit light.
  • the working processes of the pixel circuits in the other sub-pixels are the same, and will not be repeated here.
  • the display panel includes a base substrate 10, a transistor array layer disposed on the base substrate 10, a flat layer located on the side of the transistor array layer away from the base substrate 10, and a first layer located on the side of the flat layer away from the base substrate 10.
  • the transistor array layer may include pixel circuits located in each sub-pixel, that is, the transistor array layer may be used to form transistors and capacitors in the pixel circuit, and to form scan lines GA, reset lines VREF, power lines ELVDD, and the like.
  • the transistor array layer may include an active semiconductor layer 0310, a gate insulating layer, a first conductive layer 0320, an interlayer dielectric layer, a second conductive layer 0330, a first interlayer insulating layer, a third conductive layer 0340, a first Two interlayer insulating layers and a third conductive layer 0350 .
  • the active semiconductor layer 0310 of the pixel circuit 0121 is shown. And the active semiconductor layer 0310 is located on the base substrate.
  • the active semiconductor layer 0310 may be formed by patterning a semiconductor material.
  • the active semiconductor layer 0310 can be used to fabricate the above-mentioned active region T3-A of the driving transistor T3, the active region T1-A of the data writing transistor T1 and the active region T2-A of the reset transistor T2.
  • each active region may include a conductive source region, a conductive drain region, and a channel region between the conductive source region and the conductive drain region.
  • the active semiconductor layer 0310 may be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that, the above-mentioned conductive source region and conductive drain region may be conductive regions in which the active semiconductor layer 0310 is doped with n-type impurities or p-type impurities.
  • the channel region T3-A1 of the active region of the driving transistor T3 may include a first driving channel region T3-A11 and a first driving channel region T3-A11 and a first driving channel region T3-A11 and Two driving channel regions T3-A12; wherein, the first driving channel region T3-A11 extends along the first direction F1, the second driving channel region extends along the third direction F3, and the first direction F1 and the third direction F3
  • the value of the above-mentioned included angle ⁇ can be determined according to the requirements of practical applications, which is not limited here.
  • the active region of the reset transistor T2 extends along the first direction F1, and the active region of the reset transistor T2 is located in the second driving channel region T3-A12 of the driving transistor T3 away from One end of the first driving channel region T3-A11.
  • the conductive drain region of the active region of the reset transistor T2 is connected to the second driving channel region T3-A12 of the driving transistor T3.
  • the conductive drain region of the active region of the reset transistor T2 and the conductive drain region of the active region of the driving transistor T3 are shared, that is, provided in an integrated structure.
  • the active area of the data writing transistor T1 is spaced apart from the active area of the reset transistor T2 and the active area of the driving transistor T3, respectively;
  • the active region extends along the first direction F1.
  • the orthographic projection of the active region of the data writing transistor T1 in the second direction F2 is located in the orthographic projection of the second driving channel region T3-A12 of the driving transistor T3 in the second direction F2, away from the reset One side of the orthographic projection of the active region of the transistor T2 in the second direction F2.
  • the channel region T1-A1 of the active region of the data writing transistor T1 and the channel region T2-A1 of the active region of the reset transistor T2 are Arrangement in the second direction F2. Further, in a row of sub-pixels, the channel region T1-A1 of the active region of the data writing transistor T1 and the channel region T2-A1 of the active region of the reset transistor T2 are arranged along the second direction F2.
  • a gate insulating layer is formed on the above-mentioned active semiconductor layer 0310 for protecting the above-mentioned active semiconductor layer 0310 . That is, a gate insulating layer is formed on the side of the active semiconductor layer away from the base substrate. As shown in FIG. 3 , FIG. 4 b and FIG. 5 a , the first conductive layer 0320 of the pixel circuit 0121 is shown. The first conductive layer 0320 is disposed on the side of the gate insulating layer away from the base substrate 10 so as to be connected with the active semiconductor layer. 0310 Insulation.
  • the first conductive layer 0320 may include a first plate CC1 of the storage capacitor CST, a plurality of scan lines GA arranged at intervals, gates T1-G of the data writing transistor T1, and gates T2-G of the reset transistor T2.
  • the gate T1-G of the data writing transistor T1 may be the first part where the scan line GA overlaps with the active semiconductor layer 0310, and the gate T2-G of the reset transistor T2 G is the second portion where the scan line GA overlaps with the active semiconductor layer 0310 .
  • the first plate CC1 of the storage capacitor CST is multiplexed as the gate of the driving transistor T3.
  • each dotted line in FIG. 4a and FIG. 4b shows each part where the first conductive layer 0320 and the active semiconductor layer 0310 overlap.
  • the pixel circuits in one row of sub-pixels are electrically connected to one scan line GA correspondingly.
  • the scan lines GA are arranged along the first direction F1.
  • the scan line GA extends along the second direction F2.
  • the first plate CC1 of the storage capacitor CST is located between two adjacent scan lines GA.
  • the orthographic projection of the first plate CC1 of the storage capacitor CST on the base substrate and the channel region T3 of the active region of the driving transistor T3 -A1 has an overlapping area in the orthographic projection of the base substrate 10 .
  • the orthographic projection of the first plate CC1 of the storage capacitor CST on the base substrate 10 and the first driving channel region T3-A11 and the second driving channel region T3-A12 of the driving transistor T3 are in the same position.
  • the orthographic projections of the base substrate 10 each have overlapping regions.
  • the orthographic projection of the scan line GA on the base substrate 10 and the channel region T1 - A1 of the active region of the data writing transistor T1 are respectively It has an overlapping region with the channel region T2-A1 of the active region of the reset transistor T2. Therefore, the first part of the scan line GA is used as the gate of the data writing transistor T1, and the second part of the scan line GA is used as the gate of the reset transistor T2.
  • an interlayer dielectric layer is formed on the above-mentioned first conductive layer 0320 to protect the above-mentioned first conductive layer 0320 . That is, an interlayer dielectric layer is formed on the side of the first conductive layer 0320 away from the base substrate 10 .
  • a second conductive layer 0330 is formed on the side of the interlayer dielectric layer away from the base substrate 10 . As shown in FIG. 3 , FIG. 4 c and FIG. 5 b , the second conductive layer 0330 of the pixel circuit 120 a is shown.
  • the second conductive layer 0330 includes the second plate CC2 of the storage capacitor CST and the data transfer part DAZB. Wherein, one sub-pixel includes a second plate CC2 of a storage capacitor CST and a data transfer part DAZB.
  • the first plate CC1 of the storage capacitor CST may include a first plate body portion CC11 and a first plate protruding portion CC12 that are electrically connected to each other, that is, the first plate
  • the electrode plate body portion CC11 and the first electrode plate protruding portion CC12 have an integral structure to form the first electrode plate CC1 of the storage capacitor CST.
  • the first end of the data transfer portion DAZB is electrically connected to the conductive drain region of the active region of the data writing transistor T1 through the first via hole GK1, and the second end of the data transfer portion DAZB is electrically connected
  • the second via hole GK2 is electrically connected to the first plate protrusion CC12; wherein the first via hole GK1 penetrates the gate insulating layer and the interlayer dielectric layer, and the second via hole GK2 penetrates the interlayer dielectric layer.
  • the second pole plate CC2 of the storage capacitor CST can include the second pole plate main body portion CC21 and the second pole plate protruding portion CC22 that are electrically connected to each other, that is, the second pole plate
  • the electrode plate body portion CC21 and the second electrode plate protruding portion CC22 are integrally structured to form the second electrode plate CC2 of the storage capacitor CST.
  • the second electrode plate protrusion CC22 is electrically connected to the conductive drain region of the active region of the reset transistor T2 through the third via hole GK3; wherein the third via hole GK3 penetrates through the interlayer dielectric layer and gate insulating layer.
  • the second electrode plate CC2 of the storage capacitor CST and the first electrode plate CC1 of the storage capacitor CST at least partially overlap to form the storage capacitor CST.
  • the orthographic projection of the first electrode plate body portion CC11 on the base substrate 10 and the orthographic projection of the second electrode plate body portion CC21 on the base substrate 10 have an overlapping area.
  • the second plate CC2 of the storage capacitor CST can also include: Diode plate compensation portion CC23; wherein, the second electrode plate compensation portion CC23 is located at the corner formed by the second electrode plate body portion CC21 and the second electrode plate protruding portion CC22.
  • the orthographic projection of the second electrode plate compensation portion CC23 on the base substrate 10 and the orthographic projection of the first electrode plate main body portion CC11 on the base substrate 10 have an overlapping area. In this way, the area of the second plate CC2 of the storage capacitor CST can be increased. Therefore, the capacitance value of the storage capacitor CST can be increased, thereby improving the storage capacity of the storage capacitor CST.
  • the orthographic projection of the first electrode plate body portion CC11 on the base substrate 10 and the second electrode plate protruding portion CC22 on the base substrate 10 in the same sub-pixel, the orthographic projection of the first electrode plate body portion CC11 on the base substrate 10 and the second electrode plate protruding portion CC22 on the base substrate 10 .
  • the orthographic projection of the edge of the orthographic projection of the base substrate 10 close to the second plate body portion CC21 has an overlapping area. In this way, the area of the second plate CC2 of the storage capacitor CST can be further increased. Therefore, the capacitance value of the storage capacitor CST can be further improved, thereby further improving the storage capacity of the storage capacitor CST.
  • a first interlayer insulating layer is formed on the above-mentioned second conductive layer 0330 for protecting the above-mentioned second conductive layer 0330 . That is, a first interlayer insulating layer is formed on the side of the second conductive layer 0330 away from the base substrate 10 , and a third conductive layer 0340 is formed on the side of the first interlayer insulating layer away from the base substrate 10 . As shown in FIG. 3 , FIG. 4 d and FIG. 5 c , the third conductive layer 0340 of the pixel circuit 0121 is shown.
  • the third conductive layer 0340 may include a plurality of data lines DA arranged at intervals, a plurality of reset adapters RSZB arranged at intervals, a plurality of power adapters VDZB arranged at intervals, and a plurality of anode adapters YZB arranged at intervals .
  • one sub-pixel includes one anode transfer part YZB.
  • the data lines DA extend along the first direction F1 and are arranged along the second direction F2 .
  • One column of sub-pixels is electrically connected to one data line DA correspondingly.
  • the data line DA is electrically connected to the conductive source region of the active region of the data writing transistor T1 through the fourth via hole GK4, wherein the fourth via hole GK4 penetrates through the first interlayer insulating layer and the interlayer.
  • the dielectric layer and the gate insulating layer, and the orthographic projection of the fourth via hole GK4 on the base substrate 10 is located at the orthographic projection of the scan line GA on the base substrate 10 . side of the projection.
  • a second interlayer insulating layer may also be formed on the above-mentioned third conductive layer 0340 to protect the above-mentioned third conductive layer 0340 . That is, a second interlayer insulating layer is formed on the side of the third conductive layer 0340 away from the base substrate 10 , and a fourth conductive layer 0350 is formed on the side of the second interlayer insulating layer away from the base substrate 10 . As shown in FIG. 3 and FIG. 4e, the fourth conductive layer 0350 of the pixel circuit 0121 is shown.
  • the fourth conductive layer 0350 may include: a plurality of power supply lines ELVDD arranged at intervals, a plurality of reset lines VREF arranged at intervals, and a plurality of anode connection parts YLB arranged at intervals.
  • one sub-pixel includes one anode connection part YLB.
  • the anode connection part YLB is electrically connected to the first end of the anode transfer part YZB through the ninth via GK9
  • the second end of the anode transfer part YZB is electrically connected to the storage capacitor CST through the tenth via GK10.
  • the second plate CC2 is electrically connected; wherein, the ninth via hole GK9 penetrates the second interlayer insulating layer, and the tenth via hole GK10 penetrates the first interlayer insulating layer.
  • the extending direction of the scan line GA is the same as the extending direction of the power supply line ELVDD
  • the extending direction of the reset line VREF is the same as the extending direction of the power supply line ELVDD. That is, the scan line GA, the power line ELVDD and the reset line VREF extend along the second direction F2.
  • the orthographic projection of the ninth via GK9 on the base substrate 10 and the orthographic projection of the tenth via GK10 on the base substrate 10 are along the first direction F1. arrangement.
  • the orthographic projection of the tenth via hole GK10 on the base substrate 10 is located at the orthographic projection of the ninth via hole GK9 on the base substrate 10 and away from the third via hole GK3 is on the side of the orthographic projection of the base substrate 10 .
  • the orthographic projection of the ninth via GK9 on the base substrate 10 overlaps with the orthographic projection of the second plate compensation portion CC23 on the base substrate 10 . area.
  • the power line ELVDD extends along the second direction F2 and is arranged along the first direction F1.
  • one power line ELVDD is set corresponding to at least one row of sub-pixels.
  • one power supply line ELVDD is electrically connected to pixel circuits in two adjacent rows of sub-pixels.
  • the power line ELVDD is electrically connected to the power transfer part VDZB through the fifth via GK5
  • the power transfer part VDZB is connected to the driving transistor through the sixth via GK6
  • the conductive source region of the active region of T3 is electrically connected; wherein, the fifth via GK5 penetrates the second interlayer insulating layer, and the sixth via GK6 penetrates the first interlayer insulating layer, the interlayer dielectric layer and the gate insulating layer .
  • the pixel circuits are arranged symmetrically in the orthographic projection of the base substrate.
  • two adjacent rows of sub-pixels are taken as a row group, and the sub-pixels included in different row groups are different;
  • the orthographic projection of the pixel circuits in the sub-pixels in the same row group on the base substrate is mirror-symmetrical about the row symmetry axis.
  • two adjacent columns of sub-pixels in the same row group are regarded as one column group, and the sub-pixels included in different column groups are different; the two data lines corresponding to the column groups are It has a column symmetry axis along the column direction, and the orthographic projection of the pixel circuits in the sub-pixels in the same column group on the base substrate is mirror-symmetrical about the column symmetry axis.
  • the sub-pixels in the same row group share one power supply line ELVDD.
  • the orthographic projections of the pixel circuits in the same column and located on both sides of the power supply line ELVDD on the base substrate 10 are symmetrically arranged with respect to the orthographic projection of the power supply line ELVDD on the base substrate 10 .
  • the orthographic projections of the pixel circuits in the same column and located on both sides of the power supply line ELVDD on the base substrate 10 are substantially mirror-symmetrical with respect to the orthographic projection of the power supply line ELVDD on the base substrate 10 .
  • the active semiconductor layer 0310 further includes a plurality of driving protrusions TQ; the conductive source regions of the driving transistors T3 in the two sub-pixels in the same column of the row group One driving protrusion TQ is electrically connected; wherein, in the same driving transistor T3, the conductive source region and the first driving channel region T3-A11 are electrically connected, and the conductive source region that is electrically connected to each other is the first driving channel
  • the regions T3-A11 extend in the same direction.
  • the orthographic projection of the driving protrusion TQ on the base substrate 10 is located on the side of the orthographic projection of the conductive source region on the base substrate 10 away from the orthographic projection of the data line DA on the base substrate 10 .
  • the power adapter VDZB is electrically connected to the driving protrusion TQ electrically connected to the driving transistor T3 through the sixth via hole GK6, and the orthographic projection of the driving protrusion TQ of the driving transistor T3 to the base substrate 10 covers the sixth.
  • the orthographic projection of the via hole GK6 on the base substrate 10 is electrically connected to the driving protrusion TQ electrically connected to the driving transistor T3 through the sixth via hole GK6, and the orthographic projection of the driving protrusion TQ of the driving transistor T3 to the base substrate 10 covers the sixth.
  • the orthographic projection of the via hole GK6 on the base substrate 10 is the orthographic projection of the via hole GK6 on the base substrate 10 .
  • the extension line of the active region of the reset transistor in the column direction (ie, the first direction F1 ) has an overlapping area with the driving protrusion TQ.
  • the extension line of the channel region T2-A of the reset transistor in the column direction (ie, the first direction F1) and the driving protrusion TQ have an overlapping region.
  • the orthographic projection of the fifth via GK5 on the base substrate 10 is located at the orthographic projection of the sixth via GK6 on the base substrate 10 away from the data line DA.
  • One side of the orthographic projection of the base substrate 10 is located at the orthographic projection of the sixth via GK6 on the base substrate 10 away from the data line DA.
  • the two data lines DA corresponding to the column group have axes of symmetry along the column direction, and the pixel circuits in the sub-pixels of the same column group are located on the base plate 10 .
  • the orthographic projection is set symmetrically about the symmetry axis.
  • the driving transistors T3 in the same column group share one power switching part VDZB. In this way, the first voltage input by the driving transistors T3 in the same column group can be relatively stable.
  • the orthographic projection of the power line ELVDD on the base substrate 10 covers the orthographic projection of the electrically connected power adapter VDZB on the base substrate 10 .
  • the reset line VREF extends along the second direction F2 and is arranged along the first direction F1. Moreover, one reset line VREF is provided corresponding to at least one row of sub-pixels. For example, one reset line VREF is correspondingly electrically connected to pixel circuits in two adjacent rows of sub-pixels. Further, in the same sub-pixel, the reset line VREF is electrically connected to the reset transfer portion RSZB through the seventh via hole GK7, and the reset transfer portion RSZB is connected to the conductive source of the active region of the reset transistor T2 through the eighth via hole GK8. The regions are electrically connected; wherein, the seventh via hole GK7 penetrates the second interlayer insulating layer, and the eighth via hole GK8 penetrates the first interlayer insulating layer, the interlayer dielectric layer and the gate insulating layer.
  • two adjacent rows of sub-pixels located in different row groups share a reset line VREF; and the pixel circuits in the same column and located on both sides of the reset line VREF are on the base substrate.
  • the orthographic projection of VREF is symmetrically arranged with respect to the orthographic projection of the reset line VREF on the base substrate 10 .
  • the orthographic projections of the pixel circuits in the same column and on both sides of the reset line VREF on the base substrate 10 are substantially mirror-symmetrical with respect to the orthographic projection of the reset line VREF on the base substrate 10 .
  • the orthographic projection of the reset line VREF on the base substrate 10 covers the orthographic projection of the electrically connected reset transition portion RSZB on the base substrate 10 .
  • the orthographic projection of the seventh via hole GK7 on the base substrate 10 is located at the orthographic projection of the eighth via hole GK8 on the base substrate 10 away from the data line DA.
  • One side of the orthographic projection of the base substrate 10 is located at the orthographic projection of the eighth via hole GK8 on the base substrate 10 away from the data line DA.
  • the orthographic projection of the scanning line GA on the substrate 10 is located at the power supply line ELVDD on the substrate.
  • the orthographic projection of the substrate 10 is between the orthographic projection of the reset line VREF on the base substrate 10 .
  • a flat layer is formed on the above-mentioned fourth conductive layer 0350 for protecting the above-mentioned fourth conductive layer 0350 .
  • a first electrode layer 0360 is formed on the side of the flat layer facing away from the base substrate 10 .
  • the first electrode layer 0360 includes anodes located in each sub-pixel.
  • the anode in each sub-pixel is electrically connected to the anode connecting portion YLB through the anode via GK0.
  • the anode in each sub-pixel includes an anode main body portion and an anode protruding portion that are electrically connected to each other.
  • the main body portion of the anode is electrically connected to the protruding portion of the anode, and the protruding portion of the anode is electrically connected to the connecting portion YLB of the anode through the anode via GK0.
  • the anode via hole GK0 penetrates the flat layer. In this way, the driving current generated by the driving transistor T3 can be input into the anode of the light-emitting element.
  • the anode protrusions of each anode are in an irregular pattern.
  • the orthographic projection of the anode connecting portion YLB on the base substrate 10 and the orthographic projection of the data line DA on the base substrate 10 have an intersection. overlapping area. Further, in some sub-pixels, the orthographic projection of the anode connecting portion YLB on the base substrate 10 and the orthographic projection of the data line DA on the base substrate 10 have overlapping regions.
  • the orthographic projection of the anode connection part YLB on the base substrate 10 is the same as the first driving channel region T3-A11 and the second driving channel region T3-A11.
  • the corners between the track regions T3-A12 have overlapping regions in the orthographic projection of the base substrate 10.
  • the orthographic projection of the anode connection part YLB on the base substrate 10 and the second driving channel region T3-A12 on the base substrate The overlapping area of the orthographic projection of 10 is larger than the overlapping area of the orthographic projection of the anode connecting portion YLB on the base substrate 10 and the orthographic projection of the first driving channel region T3-A11 on the base substrate. Further, in some sub-pixels, the overlapping area of the orthographic projection of the anode connecting portion YLB on the base substrate 10 and the orthographic projection of the second driving channel region T3-A12 on the base substrate 10 is larger than that of the anode connecting portion YLB on the substrate.
  • the orthographic projection of the substrate 10 overlaps with the orthographic projection of the first driving channel region T3 - A11 on the base substrate 10 .
  • the anode connection parts are arranged along the first direction and are not arranged on the same straight line.
  • the anode connecting portions are arranged along the first direction and are not arranged on the same straight line.
  • the orthographic projection of the portion of the anode transition portion YZB close to the ninth via GK9 on the base substrate 10 is the same as the first driving channel.
  • the corner between the region T3-A11 and the second driving channel region T3-A12 has an overlapping region in the orthographic projection of the base substrate 10.
  • the anode transfer parts are arranged on the same straight line along the first direction. In the same row of sub-pixels, the anode transfer parts are arranged on the same straight line along the second direction.
  • the first electrode layer is further provided with a pixel defining layer on the side away from the base substrate, some pixel defining layers are further provided with a light-emitting layer away from the base substrate, and a cathode layer is further provided on the side of the light-emitting layer facing away from the base substrate.
  • the pixel defining layer may include a plurality of opening regions (eg, KK1 , KK2 , KK3 , KK4 ).
  • the light-emitting layer includes a plurality of light-emitting layers with different colors (eg FG1, FG2, FG0).
  • the orthographic projection of the opening area (eg: KK1, KK2, KK3, KK4) on the base substrate does not intersect with the orthographic projection of the anode via GK0 on the base substrate. stack.
  • the orthographic projection of the power supply line on the base substrate passes through the orthographic projection of the opening area in the at least two sub-pixels on the base substrate.
  • the anodes in the opening regions of these sub-pixels can be made as flat as possible to improve color uniformity.
  • the first signal line may be a data line
  • the second signal line may be a power line
  • the first signal line may also be a data line
  • the second signal line may also be a power line
  • the first signal line may also be a data line
  • the third conductive layer may also include a power line
  • the second signal line may also be a power line
  • the fourth conductive layer may also include a data line.
  • the design can be determined according to the requirements of practical applications, which is not limited here.
  • multiple sub-pixels in the display panel may form multiple repeating units.
  • the repeating unit may include four sub-pixels adjacent along the second direction F2.
  • the structure of the pixel circuit in each sub-pixel can be set with reference to the above description.
  • the four subpixels in the repeating unit may include a first subpixel, a second subpixel, a third subpixel, and a fourth subpixel along the second direction F2.
  • the light-emitting element in the first sub-pixel can emit red light
  • the light-emitting element in the second sub-pixel can emit green light
  • the light-emitting element in the third sub-pixel can emit blue light
  • the light-emitting element in the fourth sub-pixel can emit light. green light.
  • the repeating units are arranged in dislocation.
  • the anode of the second subpixel in one repeating unit and the anode of the fourth subpixel in the other repeating unit are along the first direction F1 arrangement.
  • the first sub-pixel may include an anode YG1 .
  • the anode YG1 may include an anode main body part YG11 and an anode protrusion part YG12.
  • the orthographic projection of the opening region KK1 on the base substrate 10 is located within the orthographic projection of the anode main body portion YG11 on the base substrate 10 .
  • the anode main body portion YG11 has a hexagonal shape, and the anode protruding portion YG12 has an irregular pattern.
  • the anode protrusion part YG12 is provided protruding from the anode main body part YG11 in the lower left corner direction.
  • the first sub-pixel may include a light-emitting layer FG1 , and the orthographic projection of the light-emitting layer FG1 on the base substrate 10 covers the orthographic projection of the anode body portion YG11 on the base substrate 10 .
  • the anode main body part YG11 may also be a quadrangle, a pentagon, a hexagon, an octagon, etc., which is not limited herein.
  • the opening area KK1 may also be a quadrangle, a pentagon, a hexagon, an octagon, or the like, which is not limited here.
  • the second sub-pixel may include an anode YG2 .
  • the anode YG2 may include an anode main body part YG21 and an anode protrusion part YG22.
  • the orthographic projection of the opening region KK2 on the base substrate 10 is located within the orthographic projection of the anode main body portion YG21 on the base substrate 10 .
  • the anode main body portion YG21 has a pentagon shape, and the anode protrusion portion YG22 has an irregular pattern.
  • the second sub-pixel may include a light-emitting layer FG2 , and the orthographic projection of the light-emitting layer FG2 on the base substrate 10 covers the orthographic projection of the anode main portion YG21 on the base substrate 10 .
  • the anode main body part YG21 may also be a quadrangle, a pentagon, a hexagon, an octagon, etc., which is not limited herein.
  • the opening area KK2 may also be a quadrangle, a pentagon, a hexagon, an octagon, or the like, which is not limited here.
  • the third sub-pixel may include an anode YG3 .
  • the anode YG3 may include an anode main body part YG31 and an anode protrusion part YG32.
  • the orthographic projection of the opening region KK3 on the base substrate 10 is located within the orthographic projection of the anode main body portion YG31 on the base substrate 10 .
  • the anode main body portion YG31 has a hexagonal shape, and the anode protruding portion YG32 has an irregular pattern.
  • the anode protrusion part YG32 is provided to protrude from the anode main body part YG31 in the lower right corner direction.
  • the third sub-pixel may include a light-emitting layer FG3 , and the orthographic projection of the light-emitting layer FG3 on the base substrate 10 covers the orthographic projection of the anode main portion YG31 on the base substrate 10 .
  • the anode main body part YG31 may also be a quadrangle, a pentagon, a hexagon, an octagon, etc., which is not limited herein.
  • the opening area KK3 may also be a quadrangle, a pentagon, a hexagon, an octagon, or the like, which is not limited here.
  • the fourth sub-pixel may include an anode YG4 .
  • the anode YG4 may include an anode main body part YG41 and an anode protruding part YG42.
  • the orthographic projection of the opening region KK4 on the base substrate 10 is located within the orthographic projection of the anode main body portion YG41 on the base substrate 10.
  • the anode main body portion YG41 has a pentagon shape
  • the anode protrusion portion YG42 has an irregular pattern.
  • the fourth sub-pixel may include a light-emitting layer FG4 , and the orthographic projection of the light-emitting layer FG4 on the base substrate 10 covers the orthographic projection of the anode body portion YG41 on the base substrate 10 .
  • the anode main body part YG41 may also be a quadrangle, a pentagon, a hexagon, an octagon, etc., which is not limited herein.
  • the opening area KK4 may also be a quadrangle, a pentagon, a hexagon, an octagon, or the like, which is not limited here.
  • the second sub-pixel in one repeating unit of the two repeating units is and the anode of the fourth sub-pixel in the other repeating unit are arranged along the first direction F1.
  • the light-emitting layer covering the anode main body portion of the anode of the second sub-pixel and the light-emitting layer covering the anode main body portion of the anode of the fourth sub-pixel are provided in an integrated structure. This reduces the difficulty of the mask.
  • the data signal on the data line DA is transferred to the conductive source region of the active region of the data writing transistor T1 through the fourth via GK4; transferred to the data writing transistor T1
  • the data signal of the conductive source region of the active region is transmitted to the conductive drain region of the active region of the data writing transistor T1 through the channel region of the active region of the data writing transistor T1;
  • the data signal of the conductive drain region of the active region of the transistor T1 is transmitted to the data switching part DAZB through the first via GK1; the data signal transmitted to the data switching part DAZB is transmitted to the first via GK2 of the storage capacitor CST.
  • Plate CC1 the data signal on the data line DA is transferred to the conductive source region of the active region of the data writing transistor T1 through the fourth via GK4; transferred to the data writing transistor T1
  • the data signal of the conductive source region of the active region is transmitted to the conductive drain region of the active region of the data writing transistor T1 through the channel region of the active region of the
  • the reset signal on reset line VREF is transmitted to the conductive source region of the active region of reset transistor T2 through the eighth via GK8; to the active region of reset transistor T2
  • the reset signal of the conductive source region of the reset transistor T2 is transmitted to the conductive drain region of the active region of the reset transistor T2 through the channel region of the active region of the reset transistor T2; transmitted to the conductive drain region of the active region of the reset transistor T2
  • the reset signal of the pole region is transmitted to the second plate CC2 of the storage capacitor CST through the third via GK3; the reset signal transmitted to the second plate CC2 of the storage capacitor CST is transmitted to the anode transfer part YZB through the tenth via GK10 ;
  • the reset signal transmitted to the anode connecting part YZB is transmitted to the anode connecting part YLB through the ninth via GK9.
  • the power signal of the power line ELVDD is transmitted to the power transfer part VDZB through the fifth via GK5 ; the power signal transmitted to the power transfer part VDZB is transmitted to the power transfer part VDZB through the sixth via GK6
  • the driving current generated by the driving transistor T3 is transmitted to the second plate CC2 of the storage capacitor CST through the third via GK3 ; the driving current transmitted to the second plate CC2 of the storage capacitor CST is driven The current is transmitted to the anode transfer part YZB through the tenth via hole GK10 ; the driving current transmitted to the anode transfer part YZB is transferred to the anode connection part YLB through the ninth via hole GK9 .
  • the above-mentioned via holes may be via holes with isotropic properties, or may be via holes with anisotropic properties.
  • the orthographic projection of the above-mentioned via hole on the base substrate may be a circle, a rectangle, a hexagon, etc., which is not limited herein.
  • an embodiment of the present disclosure further provides a display device, including the above-mentioned display panel provided by an embodiment of the present disclosure.
  • the display device can be any product or component with a display function, such as a smart watch, a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be regarded as a limitation of the present disclosure.

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Abstract

一种显示面板、驱动方法及显示装置，包括：衬底基板（10），有源半导体层（0310），位于衬底基板（10）上；栅绝缘层，位于有源半导体层（0310）背离衬底基板（10）一侧；第一导电层（0320），位于栅绝缘层背离衬底基板（10）一侧；层间介质层，位于第一导电层（0320）背离衬底基板（10）一侧；第二导电层（0330），位于层间介质层背离衬底基板（10）一侧；第一层间绝缘层，位于第二导电层（0330）背离衬底基板（10）一侧；第三导电层（0340），位于第一层间绝缘层背离衬底基板（10）一侧；第三导电层（0340）包括多条第一信号线；第二层间绝缘层，位于第三导电层（0340）背离衬底基板（10）一侧；第四导电层（0350），位于第二层间绝缘层背离衬底基板（10）一侧；第四导电层（0350）包括多条第二信号线；第一信号线在衬底基板（10）的正投与第二信号线在衬底基板（10）的正投影交叉设置。

Description

显示面板、驱动方法及显示装置 技术领域
本公开实施例涉及显示技术领域，特别涉及显示面板、驱动方法及显示装置。
背景技术
随着显示技术的不断发展，有机发光二极管(Organic Light Emitting Diode，OLED)显示面板因其自发光、广视角、高对比度、低功耗、高反应速度等优点，已经越来越多地被应用于各种电子设备中。
发明内容
本公开实施例提供的显示面板，包括：
衬底基板，包括多个子像素；
有源半导体层，位于所述衬底基板上；
栅绝缘层，位于所述有源半导体层背离所述衬底基板一侧；
第一导电层，位于所述栅绝缘层背离所述衬底基板一侧；
层间介质层，位于所述第一导电层背离所述衬底基板一侧；
第二导电层，位于所述层间介质层背离所述衬底基板一侧；
第一层间绝缘层，位于所述第二导电层背离所述衬底基板一侧；
第三导电层，位于所述第一层间绝缘层背离所述衬底基板一侧；所述第三导电层包括间隔设置的多条第一信号线；
第二层间绝缘层，位于所述第三导电层背离所述衬底基板一侧；
第四导电层，位于所述第二层间绝缘层背离所述衬底基板一侧；所述第四导电层包括间隔设置的多条第二信号线；
所述第一信号线在所述衬底基板的正投与所述第二信号线在所述衬底基板的正投影交叉设置。
在一些示例中，所述第一信号线为数据线，所述第二信号线为电源线。
在一些示例中，所述第一导电层包括间隔设置的多条扫描线；所述扫描线的延伸方向与所述电源线的延伸方向相同；
所述第四导电层还包括间隔设置的多条复位线；所述复位线的延伸方向与所述电源线的延伸方向相同；
针对一行所述子像素电路对应的电源线、扫描线以及复位线，所述扫描线在所述衬底基板的正投影位于所述电源线在所述衬底基板的正投影与所述复位线在所述衬底基板的正投影之间。
在一些示例中，所述像素电路包括：驱动晶体管、数据写入晶体管、复位晶体管以及存储电容；
所述驱动晶体管的第一极与所述电源线电连接，所述驱动晶体管的第二极与发光元件电连接；
所述存储电容的第一极板与所述驱动晶体管的栅极电连接，所述存储电容的第二极板与所述驱动晶体管的第二极电连接；
所述数据写入晶体管的栅极与所述扫描线电连接，所述数据写入晶体管的第一极与所述数据线电连接，所述数据写入晶体管的第二极与所述驱动晶体管的栅极电连接；
所述复位晶体管的栅极与所述扫描线电连接，所述复位晶体管的第一极与复位线电连接，所述复位晶体管的第二极与所述驱动晶体管的第二极电连接。
在一些示例中，所述有源半导体层包括所述驱动晶体管的有源区；所述第一导电层包括所述存储电容的第一极板；且所述存储电容的第一极板复用为所述驱动晶体管的栅极；
所述子像素中，所述存储电容的第一极板在所述衬底基板的正投影与所述驱动晶体管的有源区的沟道区在所述衬底基板的正投影具有交叠区域；
所述子像素中，所述驱动晶体管的有源区的沟道区包括相互连接设置的第一驱动沟道区和第二驱动沟道区；其中，所述第一驱动沟道区沿第一方向 延伸，所述第二驱动区沟道沿第三方向延伸，且所述第一方向与所述第三方向之间的夹角β满足0°<β≤90°。
在一些示例中，所述有源半导体层还包括所述复位晶体管的有源区；其中，所述复位晶体管的有源区沿所述第一方向延伸，且所述复位晶体管的有源区位于所述驱动晶体管的第二驱动沟道区背离第一驱动沟道区一侧；
同一所述子像素中，所述复位晶体管的有源区的导体化漏极区和所述驱动晶体管的第二驱动沟道区连接。
在一些示例中，所述有源半导体层还包括所述数据写入晶体管的有源区；所述数据写入晶体管的有源区分别与所述复位晶体管的有源区和所述驱动晶体管的有源区间隔设置；其中，所述数据写入晶体管的有源区沿所述第一方向延伸；
同一所述子像素中，所述数据写入晶体管的有源区在所述第二方向上的正投影位于所述驱动晶体管的第二驱动沟道区在所述第二方向上的正投影背离所述复位晶体管的有源区在所述第二方向上的正投影的一侧。
在一些示例中，同一所述子像素中，所述数据写入晶体管的有源区的沟道区与所述复位晶体管的有源区的沟道区沿所述第二方向排列。
在一些示例中，一行子像素对应一条所述扫描线；同一所述子像素中，所述扫描线在所述衬底基板的正投影分别与所述数据写入晶体管的有源区的沟道区与所述复位晶体管的有源区的沟道区具有交叠区域。
在一些示例中，所述第二导电层包括位于各所述子像素中的数据转接部；
所述存储电容的第一极板包括相互电连接的第一极板主体部和第一极板突出部；
同一所述子像素中，所述数据转接部的第一端通过第一过孔与所述数据写入晶体管的有源区的导体化漏极区电连接，所述数据转接部的第二端通过第二过孔与所述第一极板突出部电连接；其中，所述第一过孔贯穿所述栅绝缘层和所述层间介质层，所述第二过孔贯穿所述层间介质层。
在一些示例中，所述第二导电层还包括所述存储电容的第二极板；其中， 所述存储电容的第二极板包括相互电连接的第二极板主体部和第二极板突出部；
同一所述子像素中，所述第二极板突出部通过第三过孔与所述复位晶体管的有源区的导体化漏极区电连接；其中，所述第三过孔贯穿所述层间介质层和所述栅绝缘层。
在一些示例中，同一所述子像素中，所述第一极板主体部在所述衬底基板的正投影与所述第二极板主体部在所述衬底基板的正投影具有交叠区域。
在一些示例中，所述存储电容的第二极板还包括：分别与所述第二极板主体部和所述第二极板突出部电连接的第二极板补偿部；其中，所述第二极板补偿部位于所述第二极板主体部和所述第二极板突出部形成的拐角处；
同一所述子像素中，所述第二极板补偿部在所述衬底基板的正投影与所述第一极板主体部在所述衬底基板的正投影具有交叠区域。
在一些示例中，同一所述子像素中，所述第一极板主体部在所述衬底基板的正投影与所述第二极板突出部在所述衬底基板的正投影靠近所述第二极板主体部在所述衬底基板的正投影的边缘具有交叠区域。
在一些示例中，一列所述子像素对应一条所述数据线；
同一所述子像素中，所述数据线通过第四过孔与所述数据写入晶体管的有源区的导体化源极区电连接，其中，所述第四过孔贯穿所述第一层间绝缘层、所述层间介质层以及所述栅绝缘层，且所述第四过孔在所述衬底基板的正投影位于所述扫描线在所述衬底基板的正投影背离所述存储电容的第一极板在所述衬底基板的正投影的一侧。
在一些示例中，一条所述电源线与至少一行所述子像素对应设置；
所述第三导电层还包括间隔设置的多个电源转接部；其中，同一所述子像素中，所述电源线通过第五过孔与所述电源转接部电连接，所述电源转接部通过第六过孔与所述驱动晶体管的有源区的导体化源极区电连接；其中，所述第五过孔贯穿所述第二层间绝缘层，所述第六过孔贯穿所述第一层间绝缘层、所述层间介质层以及所述栅绝缘层。
在一些示例中，一条所述复位线与至少一行子像素对应设置；
所述第三导电层还包括间隔设置的多个复位转接部；同一所述子像素中，所述复位线通过第七过孔与所述复位转接部电连接，所述复位转接部通过第八过孔与所述复位晶体管的有源区的导体化源极区电连接；其中，所述第七过孔贯穿所述第二层间绝缘层，所述第八过孔贯穿所述第一层间绝缘层、所述层间介质层以及所述栅绝缘层。
在一些示例中，所述第四导电层还包括间隔设置的多个阳极连接部；所述第三导电层还包括间隔设置的多个阳极转接部；其中，一个所述子像素包括一个所述阳极连接部和一个所述阳极转接部；
同一所述子像素中，所述阳极连接部通过第九过孔与所述阳极转接部的第一端电连接，所述阳极转接部的第二端通过第十过孔与所述存储电容的第二极板电连接；其中，所述第九过孔贯穿所述第二层间绝缘层，所述第十过孔贯穿所述第一层间绝缘层。
在一些示例中，同一所述子像素中，所述第九过孔在所述衬底基板的正投影和所述第十过孔在所述衬底基板的正投影沿所述第一方向排列。
在一些示例中，同一所述子像素中，所述第十过孔在所述衬底基板的正投影位于所述第九过孔在所述衬底基板的正投影背离所述第三过孔在所述衬底基板的正投影的一侧。
在一些示例中，同一所述子像素中，所述第九过孔在所述衬底基板的正投影与所述第二极板补偿部在所述衬底基板的正投影具有交叠区域。
在一些示例中，至少一个子像素中，所述阳极连接部在所述衬底基板的正投影与所述数据线在所述衬底基板的正投影具有交叠区域。
在一些示例中，同一所述子像素中，所述阳极连接部在所述衬底基板的正投影与所述第一驱动沟道区和所述第二驱动沟道区之间的拐角处在所述衬底基板的正投影具有交叠区域。
在一些示例中，至少一个所述子像素中，所述阳极连接部在所述衬底基板的正投影与所述第二驱动沟道区在所述衬底基板的正投影的交叠区域大于 所述阳极连接部在所述衬底基板的正投影与所述第一驱动沟道区在所述衬底基板的正投影的交叠区域。
在一些示例中，同一所述子像素中，所述阳极转接部靠近所述第九过孔的部分在所述衬底基板的正投影与所述第一驱动沟道区和所述第二驱动沟道区之间的拐角处在所述衬底基板的正投影具有交叠区域。
在一些示例中，同一列所述子像素中，所述阳极连接部沿所述第一方向排列且未排列于同一直线上；
同一行所述子像素中，所述阳极连接部沿所述第一方向排列且未排列于同一直线上。
在一些示例中，同一列所述子像素中，所述阳极转接部沿所述第一方向排列于同一直线上；
同一行所述子像素中，所述阳极转接部沿所述第二方向排列于同一直线上。
在一些示例中，相邻两个子像素中，像素电路在所述衬底基板的正投影镜像对称设置。
在一些示例中，以相邻两行子像素为一个行组，且不同所述行组包括的子像素不同；
所述行组对应的两条扫描线具有沿行方向的行对称轴，同一所述行组的子像素中像素电路在所述衬底基板的正投影关于所述行对称轴镜像对称设置。
在一些示例中，以同一所述行组中的相邻两列子像素为一个列组，且不同所述列组包括的子像素不同；
所述列组对应的两条数据线具有沿所述列方向的列对称轴，同一所述列组的子像素中像素电路在所述衬底基板的正投影关于所述列对称轴镜像对称设置。
在一些示例中，所述显示面板还包括：第一电极层，位于所述第四导电层背离所述衬底基板一侧；所述第一电极层包括位于各子像素中的阳极；
像素限定层，位于所述第一电极层背离所述衬底基板一侧；
其中，所述像素限定层包括多个开口区域，一个所述阳极对应一个所述开口区域，且同一所述子像素中，所述开口区域在所述衬底基板的正投影位于对应的所述阳极在所述衬底基板的正投影内；
所述电源线在所述衬底基板的正投影穿过至少两个子像素中的开口区域在所述衬底基板的正投影。
在一些示例中，同一行组的子像素共用一条所述电源线；
同一列中且位于所述电源线两侧的像素电路在所述衬底基板的正投影关于所述电源线在所述衬底基板的正投影对称设置。
在一些示例中，所述有源半导体层还包括多个驱动突出部；所述行组的同一列的两个子像素中的驱动晶体管的导体化源极区电连接一个驱动突出部；其中，同一所述驱动晶体管中，所述导体化源极区和所述第一驱动沟道区电连接，且相互电连接的所述导体化源极区与所述第一驱动沟道区沿同一方向延伸；
同一列所述子像素中，所述驱动突出部在所述衬底基板的正投影位于所述导体化源极区在所述衬底基板的正投影背离所述数据线在所述衬底基板的正投影的一侧；
所述电源转接部通过第六过孔与所述驱动晶体管电连接的驱动突出部电连接，且所述驱动晶体管电连接的驱动突出部在所述衬底基板的正投影覆盖所述第六过孔在所述衬底基板的正投影。
在一些示例中，同一列所述子像素中，所述复位晶体管的有源区在所述列方向上的延长线与所述驱动突出部具有交叠区域。
在一些示例中，同一列所述子像素中，所述第五过孔在所述衬底基板的正投影位于所述第六过孔在所述衬底基板的正投影背离所述数据线在所述衬底基板的正投影的一侧。
在一些示例中，同一所述列组中的驱动晶体管共用一个所述电源转接部。
在一些示例中，所述电源线在所述衬底基板的正投影覆盖电连接的所述电源转接部在所述衬底基板的正投影。
在一些示例中，位于不同行组且相邻的两行子像素共用一条复位线；
同一列中且位于所述复位线两侧的像素电路在所述衬底基板的正投影关于所述复位线在所述衬底基板的正投影对称设置。
在一些示例中，针对共用同一所述复位线的两行子像素，所述两行子像素中的相邻两列子像素共用一个所述复位转接部。
在一些示例中，所述复位线在所述衬底基板的正投影覆盖电连接的所述复位转接部在所述衬底基板的正投影。
在一些示例中，同一列所述子像素中，所述第七过孔在所述衬底基板的正投影位于所述第八过孔在所述衬底基板的正投影背离所述数据线在所述衬底基板的正投影的一侧。
在一些示例中，数据线上的数据信号通过第四过孔传输到数据写入晶体管的有源区的导体化源极区；
传输到所述数据写入晶体管的有源区的导体化源极区的数据信号通过所述数据写入晶体管的有源区的沟道区传输到所述数据写入晶体管的有源区的导体化漏极区；
传输到所述数据写入晶体管的有源区的导体化漏极区的数据信号通过第一过孔传输到数据转接部；
传输到所述数据转接部通过第二过孔传输到所述存储电容的第一极板。
在一些示例中，复位线上的复位信号通过第八过孔传输到复位晶体管的有源区的导体化源极区；
传输到所述复位晶体管的有源区的导体化源极区的复位信号通过所述复位晶体管的有源区的沟道区传输到所述复位晶体管的有源区的导体化漏极区；
传输到所述复位晶体管的有源区的导体化漏极区的复位信号通过第三过孔传输到所述存储电容的第二极板；
传输到所述存储电容的第二极板的复位信号通过第十过孔传输到阳极转接部；
传输到所述阳极转接部的复位信号通过第九过孔传输到阳极连接部。
在一些示例中，电源线的电源信号通过第五过孔传输到电源转接部；
传输到所述电源转接部的电源信号通过第六过孔传输到驱动晶体管电连接的驱动突出部。
在一些示例中，所述驱动晶体管产生的驱动电流通过第三过孔传输到所述存储电容的第二极板；
传输到所述存储电容的第二极板的驱动电流通过第十过孔传输到阳极转接部；
传输到所述阳极转接部的驱动电流通过第九过孔传输到阳极连接部。
本公开实施例提供的显示装置，包括上述显示面板。
本公开实施例提供的显示面板的驱动方法，包括：
复位阶段，同时对各扫描线加载导通控制信号，对复位线加载复位信号，对数据线加载初始化信号，以同时对各驱动晶体管的栅极进行初始化以及对各发光元件进行复位；
数据写入阶段，依次对所述扫描线加载导通控制信号，对所述复位线加载复位信号，且在所述扫描线加载所述导通控制信号时，对所述数据线加载相应的数据信号，以对各所述驱动晶体管的栅极输入数据信号；
发光阶段，同时对各所述扫描线加载截止控制信号，各所述驱动晶体管产生驱动电流，以驱动电连接的发光元件发光。
附图说明
图1为本公开实施例提供的显示面板的结构示意图；
图2a为本公开实施例提供的一些像素电路的结构示意图；
图2b为本公开实施例提供的信号时序图；
图3为本公开实施例提供的一些显示面板的布局结构示意图；
图4a为本公开实施例提供的有源半导体层的布局结构示意图；
图4b为本公开实施例提供的第一导电层的布局结构示意图；
图4c为本公开实施例提供的第二导电层的布局结构示意图；
图4d为本公开实施例提供的第三导电层的布局结构示意图；
图4e为本公开实施例提供的第四导电层的布局结构示意图；
图5a为本公开实施例提供的有源半导体层和第一导电层的层叠布局结构示意图；
图5b为本公开实施例提供的有源半导体层、第一导电层以及第二导电层的层叠布局结构示意图；
图5c为本公开实施例提供的有源半导体层、第一导电层、第二导电层以及第三导电层的层叠布局结构示意图；
图6为本公开实施例提供的又一些显示面板的布局结构示意图；
图7a为本公开实施例提供的第一电极层的布局结构示意图；
图7b为本公开实施例提供的发光层的布局结构示意图；
图8为本公开实施例提供的第四导电层、第一电极层以及发光层的层叠布局结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者 机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
如图1所示，本公开实施例提供的显示面板，可以包括：衬底基板10。衬底基板10包括多个子像素spx。示例性地，结合图1与图2a所示，各子像素spx可以包括：像素电路0121和发光元件0120。其中，像素电路0121具有晶体管和电容，并通过晶体管和电容的相互作用产生电信号，产生的电信号输入到发光元件0120的阳极中。并且对发光元件0120的阴极加载相应的电压，可以驱动发光元件0120发光。
在一些示例中，子像素可以阵列排布于衬底基板上。这样可以分别沿第一方向F1和与第一方向相交的第二方向F2排列多个子像素。例如，第一方向F1可以为列方向，第二方向F2可以为行方向。第一方向F1可以为行方向，第二方向F2可以为列方向。下面以第一方向F1为列方向，第二方向F2为行方向为例进行说明。
在一些示例中，如图2a所示，像素电路0121包括：驱动晶体管T3、数据写入晶体管T1、复位晶体管T2以及存储电容CST；
驱动晶体管T3的第一极与电源线ELVDD电连接，驱动晶体管T3的第二极与发光元件电连接；
存储电容CST的第一极板CC1与驱动晶体管T3的栅极电连接，存储电容CST的第二极板CC2与驱动晶体管T3的第二极电连接；
数据写入晶体管T1的栅极与扫描线GA电连接，数据写入晶体管T1的第一极与数据线DA电连接，数据写入晶体管T1的第二极与驱动晶体管T3的栅极电连接；
复位晶体管T2的栅极与扫描线GA电连接，复位晶体管T2的第一极与复位线VREF电连接，复位晶体管T2的第二极与驱动晶体管T3的第二极电连接。
其中，发光元件0120可以设置为电致发光二极管，例如有机发光二极管(Organic Light Emitting Diode，OLED)、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)、微型发光二极管(Micro Light Emitting Diodes，Micro LED)，迷你发光二极管(Mini Light Emitting Diodes，Mini OLED)中的至少一种。其中，发光元件0120可以包括层叠设置的阳极、发光层、阴极。进一步地，发光层还可以包括空穴注入层、空穴传输层、电子传输层、电子注入层等膜层。当然，在实际应用中，发光元件0120可以根据实际应用环境的需求进行设计确定，在此不作限定。
示例性地，电源线ELVDD可以传输恒定的第一电压，例如第一电压为正电压；而发光元件0120的阴极连接的ELVSS端可以输出恒定的第二电压，例如第二电压为0或者为负电压等。例如，在一些示例中，ELVSS端可以接地。
示例性地，上述晶体管的第一极可以作为其源极，第二极可以作为其漏极。或者，上述晶体管的第一极可以作为其漏极，第二极可以作为其源极，在此不作限定。
在一些示例中，本公开实施例提供的上述显示面板的驱动方法，可以包括：
复位阶段，同时对各扫描线加载导通控制信号，对复位线加载复位信号，对数据线加载初始化信号，以同时对各驱动晶体管的栅极进行初始化以及对各发光元件进行复位；
数据写入阶段，依次对扫描线加载导通控制信号，对复位线加载复位信号，且在扫描线加载导通控制信号时，对数据线加载相应的数据信号，以对各驱动晶体管的栅极输入数据信号；
发光阶段，同时对各扫描线加载截止控制信号，各驱动晶体管产生驱动电流，以驱动电连接的发光元件发光。
下面通过实施例对上述驱动方法，进行解释说明。图2a所示的像素电路对应的信号时序图，如图2b所示。一帧显示时间中，显示面板中的像素电路 的工作过程可以具有三个阶段：T10阶段、T20阶段、T30阶段。其中，ga-1代表第一行子像素中的像素电路电连接的扫描线GA上传输的信号，ga-2代表第二行子像素中的像素电路电连接的扫描线GA上传输的信号，ga-3代表第三行子像素中的像素电路电连接的扫描线GA上传输的信号，ga-N代表第N行子像素中的像素电路电连接的扫描线GA上传输的信号。其中，N为子像素的总行数。
在T10阶段，即复位阶段，同时对各扫描线GA加载导通控制信号，对复位线VREF加载复位信号，对数据线DA加载初始化信号，以同时对各驱动晶体管T3的栅极进行初始化以及对各发光元件进行复位。具体地，各扫描线GA上传输的信号均为高电平信号(即导通控制信号)，则第一行子像素至第N行子像素中的数据写入晶体管T1和复位晶体管T2均导通。以一个子像素为例，该子像素中，导通的数据写入晶体管T1将数据线DA上加载的初始化信号输入到驱动晶体管T3的栅极，以对驱动晶体管T3的栅极进行初始化。导通的复位晶体管T2将复位线VREF上加载的复位信号输入端发光元件的阳极，以对发光元件的阳极进行复位。其余子像素中的工作过程与此相同，在此不作赘述。
在T20阶段，即数据写入阶段，依次对扫描线GA加载导通控制信号，对复位线VREF加载复位信号，且在扫描线GA加载导通控制信号时，对数据线DA加载相应的数据信号，以对各驱动晶体管T3的栅极输入数据信号。具体地，T20阶段可以包括：依次出现的T21阶段、T22阶段、T23阶段……T2N阶段。
在T21阶段，第一行子像素的像素电路电连接的扫描线GA上传输的信号ga-1为高电平信号(即导通控制信号)，第二行子像素至第N行子像素的像素电路电连接的扫描线GA上传输的信号ga-2～ga-N均为低电平信号(即截止控制信号)，则第一行子像素中的数据写入晶体管T1和复位晶体管T2均导通，第二行子像素至第N行子像素中的数据写入晶体管T1和复位晶体管T2均截止，以第一行子像素中的一个子像素为例，该子像素中，导通的数据写 入晶体管T1将数据线DA上加载的数据信号输入到驱动晶体管T3的栅极，以使驱动晶体管T3的栅极的电压为数据信号的电压Vda1。导通的复位晶体管T2将复位线VREF上加载的复位信号输入端发光元件的阳极，以对发光元件的阳极进行复位。
在T22阶段，第二行子像素的像素电路电连接的扫描线GA上传输的信号ga-2为高电平信号(即导通控制信号)，第一行子像素、第三行子像素至第N行子像素的像素电路电连接的扫描线GA上传输的信号ga-1、ga-3～ga-N均为低电平信号(即截止控制信号)，则第二行子像素中的数据写入晶体管T1和复位晶体管T2均导通，第一行子像素、第三行子像素至第N行子像素中的数据写入晶体管T1和复位晶体管T2均截止，以第二行子像素中的一个子像素为例，该子像素中，导通的数据写入晶体管T1将数据线DA上加载的数据信号输入到驱动晶体管T3的栅极，以使驱动晶体管T3的栅极的电压为数据信号的电压Vda2。导通的复位晶体管T2将复位线VREF上加载的复位信号输入端发光元件的阳极，以对发光元件的阳极进行复位。
在T23阶段，第三行子像素的像素电路电连接的扫描线GA上传输的信号ga-3为高电平信号(即导通控制信号)，第一行子像素、第二行子像素、第四行子像素至第N行子像素的像素电路电连接的扫描线GA上传输的信号ga-1～ga-2、ga-4～ga-N均为低电平信号(即截止控制信号)，则第三行子像素中的数据写入晶体管T1和复位晶体管T2均导通，第一行子像素、第二行子像素、第四行子像素至第N行子像素中的数据写入晶体管T1和复位晶体管T2均截止，以第三行子像素中的一个子像素为例，该子像素中，导通的数据写入晶体管T1将数据线DA上加载的数据信号输入到驱动晶体管T3的栅极，以使驱动晶体管T3的栅极的电压为数据信号的电压Vda3。导通的复位晶体管T2将复位线VREF上加载的复位信号输入端发光元件的阳极，以对发光元件的阳极进行复位。
并且，第四行子像素至第N行子像素的像素电路的工作过程依次类推，在此不作赘述。
在T2N阶段，第N行子像素的像素电路电连接的扫描线GA上传输的信号ga-N为高电平信号(即导通控制信号)，第一行子像素至第N-1行子像素的像素电路电连接的扫描线GA上传输的信号ga-1～ga-N-1均为低电平信号(即截止控制信号)，则第N行子像素中的数据写入晶体管T1和复位晶体管T2均导通，第一行子像素至第N-1行子像素中的数据写入晶体管T1和复位晶体管T2均截止，以第N行子像素中的一个子像素为例，该子像素中，导通的数据写入晶体管T1将数据线DA上加载的数据信号输入到驱动晶体管T3的栅极，以使驱动晶体管T3的栅极的电压为数据信号的电压VdaN。导通的复位晶体管T2将复位线VREF上加载的复位信号输入端发光元件的阳极，以对发光元件的阳极进行复位。
在T30阶段，即发光阶段，同时对各扫描线GA加载截止控制信号，各驱动晶体管T3产生驱动电流，以驱动电连接的发光元件发光。具体地，各扫描线GA上传输的信号均为低电平信号(即截止控制信号)，则第一行子像素至第N行子像素中的数据写入晶体管T1和复位晶体管T2均截止。以第一行子像素中的一个子像素为例，该子像素中，驱动晶体管T3的栅极的电压为Vda1，驱动晶体管T3的第一极的电压为电源线ELVDD上传输的电压Vdd，因此驱动晶体管T3产生驱动电流Ids，Ids＝K(Vdd-Vda1-Vth) 2。驱动电流Ids输入发光元件，驱动发光元件发光。其余各子像素中的像素电路的工作过程与此相同，在此不作赘述。
示例性地，显示面板包括衬底基板10、设置在衬底基板10上的晶体管阵列层，位于晶体管阵列层背离衬底基板10一侧的平坦层，位于平坦层背离衬底基板一侧的第一电极层，位于第一电极层背离衬底基板10一侧的发光层以及位于发光层背离衬底基板10一侧的阴极。其中，晶体管阵列层可以包括位于各子像素中的像素电路，即晶体管阵列层可以用于形成像素电路中的晶体管和电容，以及形成扫描线GA、复位线VREF、电源线ELVDD等。示例性地，晶体管阵列层可以包括有源半导体层0310、栅绝缘层、第一导电层0320、层间介质层、第二导电层0330、第一层间绝缘层、第三导电层0340、第二层 间绝缘层以及第三导电层0350。
示例性地，如图3与图4a示出了该像素电路0121的有源半导体层0310。且有源半导体层0310位于衬底基板上。其中，有源半导体层0310可采用半导体材料通过图案化形成。示例性地，有源半导体层0310可用于制作上述的驱动晶体管T3的有源区T3-A、数据写入晶体管T1的有源区T1-A和复位晶体管T2的有源区T2-A。并且，各有源区可包括导体化源极区、导体化漏极区以及导体化源极区和导体化漏极区之间的沟道区。
示例性地，有源半导体层0310可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的导体化源极区和导体化漏极区可为有源半导体层0310掺杂有n型杂质或p型杂质的导体化区域。
示例性地，如图3与图4a所示，在一个子像素中，驱动晶体管T3的有源区的沟道区T3-A1可以包括相互连接设置的第一驱动沟道区T3-A11和第二驱动沟道区T3-A12；其中，第一驱动沟道区T3-A11沿第一方向F1延伸，第二驱动区沟道沿第三方向F3延伸，且第一方向F1与第三方向F3之间的夹角β满足0°<β≤90°。示例性地，可以使β＝30°，或者也可以使β＝45°，或者也可以使β＝90°。当然，在实际应用中，上述夹角β的数值可以根据实际应用的需求进行确定，在此不作限定。
示例性地，如图3与图4a所示，复位晶体管T2的有源区沿第一方向F1延伸，且复位晶体管T2的有源区位于驱动晶体管T3的第二驱动沟道区T3-A12背离第一驱动沟道区T3-A11一端。并且，同一子像素中，复位晶体管T2的有源区的导体化漏极区和驱动晶体管T3的第二驱动沟道区T3-A12连接。示例性地，复位晶体管T2的有源区的导体化漏极区和驱动晶体管T3的有源区的导体化漏极区共用，即一体结构设置。
示例性地，如图3与图4a所示，数据写入晶体管T1的有源区分别与复位晶体管T2的有源区和驱动晶体管T3的有源区间隔设置；其中，数据写入晶体管T1的有源区沿第一方向F1延伸。并且，同一子像素中，数据写入晶体管T1的有源区在第二方向F2上的正投影位于驱动晶体管T3的第二驱动沟 道区T3-A12在第二方向F2上的正投影背离复位晶体管T2的有源区在第二方向F2上的正投影的一侧。
示例性地，如图3与图4a所示，同一子像素中，数据写入晶体管T1的有源区的沟道区T1-A1与复位晶体管T2的有源区的沟道区T2-A1沿第二方向F2排列。进一步地，一行子像素中，数据写入晶体管T1的有源区的沟道区T1-A1与复位晶体管T2的有源区的沟道区T2-A1沿第二方向F2排列。
示例性地，在上述的有源半导体层0310上形成有栅绝缘层，用于保护上述的有源半导体层0310。即位于有源半导体层背离衬底基板一侧形成有栅绝缘层。如图3、图4b以及图5a所示，示出了该像素电路0121的第一导电层0320，第一导电层0320设置在栅绝缘层背离衬底基板10一侧，从而与有源半导体层0310绝缘。第一导电层0320可以包括存储电容CST的第一极板CC1、间隔设置的多条扫描线GA、数据写入晶体管T1的栅极T1-G、复位晶体管T2的栅极T2-G。
例如，如图3、图4b以及图5a所示，数据写入晶体管T1的栅极T1-G可以为扫描线GA与有源半导体层0310交叠的第一部分，复位晶体管T2的栅极T2-G为扫描线GA与有源半导体层0310交叠的第二部分。并且，存储电容CST的第一极板CC1复用为驱动晶体管T3的栅极。
需要说明的是，图4a与图4b中的各虚线示出了第一导电层0320与有源半导体层0310交叠的各个部分。
示例性地，如图3与图4b所示，一行子像素中的像素电路对应电连接一条扫描线GA。其中，扫描线GA沿第一方向F1排布。且扫描线GA沿第二方向F2延伸。并且，在第一方向F1上，存储电容CST的第一极板CC1位于相邻两条扫描线GA之间。
示例性地，如图3、图4b以及图5a所示，各子像素中，存储电容CST的第一极板CC1在衬底基板的正投影与驱动晶体管T3的有源区的沟道区T3-A1在衬底基板10的正投影具有交叠区域。进一步地，各子像素中，存储电容CST的第一极板CC1在衬底基板10的正投影与驱动晶体管T3的第一驱 动沟道区T3-A11和第二驱动沟道区T3-A12在衬底基板10的正投影均具有交叠区域。
示例性地，如图3、图4b以及图5a所示，同一子像素中，扫描线GA在衬底基板10的正投影分别与数据写入晶体管T1的有源区的沟道区T1-A1与复位晶体管T2的有源区的沟道区T2-A1具有交叠区域。从而使扫描线GA的第一部分作为数据写入晶体管T1的栅极，扫描线GA的第二部分作为复位晶体管T2的栅极。
示例性地，在上述的第一导电层0320上形成有层间介质层，用于保护上述的第一导电层0320。即位于第一导电层0320背离衬底基板10一侧形成有层间介质层。位于层间介质层背离衬底基板10一侧形成有第二导电层0330。如图3、图4c以及图5b所示，示出了该像素电路120a的第二导电层0330，第二导电层0330包括存储电容CST的第二极板CC2和数据转接部DAZB。其中，一个子像素包括一个存储电容CST的第二极板CC2和一个数据转接部DAZB。
示例性地，如图3、图4c以及图5b所示，存储电容CST的第一极板CC1可以包括相互电连接的第一极板主体部CC11和第一极板突出部CC12，即第一极板主体部CC11和第一极板突出部CC12一体结构形成了存储电容CST的第一极板CC1。并且，同一子像素中，数据转接部DAZB的第一端通过第一过孔GK1与数据写入晶体管T1的有源区的导体化漏极区电连接，数据转接部DAZB的第二端通过第二过孔GK2与第一极板突出部CC12电连接；其中，第一过孔GK1贯穿栅绝缘层和层间介质层，第二过孔GK2贯穿层间介质层。这样通过数据转接部DAZB将数据写入晶体管T1的有源区的导体化漏极区与存储电容CST的第一极板CC1进行桥接，这样可以避免对栅绝缘层进行构图，从而可以减少一次Mask(掩膜版)的使用，进而可以减低工艺流程和成本。
示例性地，如图3、图4c以及图5b所示，存储电容CST的第二极板CC2可以包括相互电连接的第二极板主体部CC21和第二极板突出部CC22，即第 二极板主体部CC21和第二极板突出部CC22一体结构形成了存储电容CST的第二极板CC2。并且，同一子像素中，第二极板突出部CC22通过第三过孔GK3与复位晶体管T2的有源区的导体化漏极区电连接；其中，第三过孔GK3贯穿层间介质层和栅绝缘层。
示例性地，如图3、图4c以及图5b所示，存储电容CST的第二极板CC2与存储电容CST的第一极板CC1至少部分交叠以形成存储电容CST。进一步地，同一子像素中，第一极板主体部CC11在衬底基板10的正投影与第二极板主体部CC21在衬底基板10的正投影具有交叠区域。
示例性地，如图3、图4c以及图5b所示，存储电容CST的第二极板CC2还可以包括：分别与第二极板主体部CC21和第二极板突出部CC22电连接的第二极板补偿部CC23；其中，第二极板补偿部CC23位于第二极板主体部CC21和第二极板突出部CC22形成的拐角处。并且，同一子像素中，第二极板补偿部CC23在衬底基板10的正投影与第一极板主体部CC11在衬底基板10的正投影具有交叠区域。这样可以提高存储电容CST的第二极板CC2的面积。从而可以提高存储电容CST的电容值，进而提高存储电容CST的存储能力。
示例性地，如图3、图4c以及图5b所示，同一子像素中，第一极板主体部CC11在衬底基板10的正投影与第二极板突出部CC22在衬底基板10的正投影靠近第二极板主体部CC21在衬底基板10的正投影的边缘具有交叠区域。这样可以进一步提高存储电容CST的第二极板CC2的面积。从而可以进一步提高存储电容CST的电容值，进而进一步提高存储电容CST的存储能力。
示例性地，在上述的第二导电层0330上形成有第一层间绝缘层，用于保护上述的第二导电层0330。即位于第二导电层0330背离衬底基板10一侧形成有第一层间绝缘层，位于第一层间绝缘层背离衬底基板10一侧形成有第三导电层0340。如图3、图4d以及图5c所示，示出了该像素电路0121的第三导电层0340。其中，第三导电层0340可以包括间隔设置的多条数据线DA、间隔设置的多个复位转接部RSZB、间隔设置的多个电源转接部VDZB以及 间隔设置的多个阳极转接部YZB。其中，一个子像素包括一个阳极转接部YZB。
示例性地，如图3、图4d以及图5c所示，数据线DA沿第一方向F1延伸，且沿第二方向F2排列。一列子像素对应电连接一条数据线DA。同一子像素中，数据线DA通过第四过孔GK4与数据写入晶体管T1的有源区的导体化源极区电连接，其中，第四过孔GK4贯穿第一层间绝缘层、层间介质层以及栅绝缘层，且第四过孔GK4在衬底基板10的正投影位于扫描线GA在衬底基板10的正投影背离存储电容CST的第一极板CC1在衬底基板10的正投影的一侧。
示例性地，在上述的第三导电层0340还可以形成有第二层间绝缘层，用于保护上述的第三导电层0340。即位于第三导电层0340背离衬底基板10一侧形成有第二层间绝缘层，位于第二层间绝缘层背离衬底基板10一侧形成有第四导电层0350。如图3与图4e所示，示出了该像素电路0121的第四导电层0350。其中，第四导电层0350可以包括：间隔设置的多条电源线ELVDD、间隔设置的多条复位线VREF以及间隔设置的多个阳极连接部YLB。其中，一个子像素包括一个阳极连接部YLB。并且，同一子像素中，阳极连接部YLB通过第九过孔GK9与阳极转接部YZB的第一端电连接，阳极转接部YZB的第二端通过第十过孔GK10与存储电容CST的第二极板CC2电连接；其中，第九过孔GK9贯穿第二层间绝缘层，第十过孔GK10贯穿第一层间绝缘层。
示例性地，如图3与图4e所示，扫描线GA的延伸方向与电源线ELVDD的延伸方向相同，复位线VREF的延伸方向与电源线ELVDD的延伸方向相同。即扫描线GA、电源线ELVDD以及复位线VREF沿第二方向F2延伸。
示例性地，如图3与图4e所示，同一子像素中，第九过孔GK9在衬底基板10的正投影和第十过孔GK10在衬底基板10的正投影沿第一方向F1排列。
示例性地，如图3与图4e所示，同一子像素中，第十过孔GK10在衬底基板10的正投影位于第九过孔GK9在衬底基板10的正投影背离第三过孔GK3在衬底基板10的正投影的一侧。
示例性地，如图3与图4e所示，同一子像素中，第九过孔GK9在衬底基 板10的正投影与第二极板补偿部CC23在衬底基板10的正投影具有交叠区域。
示例性地，如图3与图4e所示，电源线ELVDD沿第二方向F2延伸，且沿第一方向F1排列。其中，一条电源线ELVDD与至少一行子像素对应设置。例如，一条电源线ELVDD与相邻的两行子像素中的像素电路电连接。
示例性地，如图3与图4e所示，同一子像素中，电源线ELVDD通过第五过孔GK5与电源转接部VDZB电连接，电源转接部VDZB通过第六过孔GK6与驱动晶体管T3的有源区的导体化源极区电连接；其中，第五过孔GK5贯穿第二层间绝缘层，第六过孔GK6贯穿第一层间绝缘层、层间介质层以及栅绝缘层。
示例性地，如图1、图3与图4e所示，相邻两个子像素中，像素电路在衬底基板的正投影镜像对称设置。示例性地，如图1、图3与图4e所示，以相邻两行子像素为一个行组，且不同行组包括的子像素不同；行组对应的两条扫描线具有沿行方向的行对称轴，同一行组的子像素中像素电路在衬底基板的正投影关于行对称轴镜像对称设置。
示例性地，如图1、图3与图4e所示，以同一行组中的相邻两列子像素为一个列组，且不同列组包括的子像素不同；列组对应的两条数据线具有沿列方向的列对称轴，同一列组的子像素中像素电路在衬底基板的正投影关于列对称轴镜像对称设置。
示例性地，如图1、图3与图4e所示，同一行组的子像素共用一条电源线ELVDD。并且，同一列中且位于电源线ELVDD两侧的像素电路在衬底基板10的正投影关于电源线ELVDD在衬底基板10的正投影对称设置。例如，同一列中且位于电源线ELVDD两侧的像素电路在衬底基板10的正投影关于电源线ELVDD在衬底基板10的正投影大致镜像对称设置。
示例性地，如图1、图3与图4e所示，有源半导体层0310还包括多个驱动突出部TQ；行组的同一列的两个子像素中的驱动晶体管T3的导体化源极区电连接一个驱动突出部TQ；其中，同一驱动晶体管T3中，导体化源极区和第一驱动沟道区T3-A11电连接，且相互电连接的导体化源极区与第一驱动 沟道区T3-A11沿同一方向延伸。以及，同一列子像素中，驱动突出部TQ在衬底基板10的正投影位于导体化源极区在衬底基板10的正投影背离数据线DA在衬底基板10的正投影的一侧。进一步地，电源转接部VDZB通过第六过孔GK6与驱动晶体管T3电连接的驱动突出部TQ电连接，且驱动晶体管T3电连接的驱动突出部TQ在衬底基板10的正投影覆盖第六过孔GK6在衬底基板10的正投影。
示例性地，如图3与图4e所示，同一列子像素中，复位晶体管的有源区在列方向(即第一方向F1)上的延长线与驱动突出部TQ具有交叠区域。进一步地，同一列子像素中，复位晶体管的沟道区T2-A在列方向(即第一方向F1)上的延长线与驱动突出部TQ具有交叠区域。
示例性地，如图3与图4e所示，同一列子像素中，第五过孔GK5在衬底基板10的正投影位于第六过孔GK6在衬底基板10的正投影背离数据线DA在衬底基板10的正投影的一侧。
示例性地，如图1、图3与图4e所示，其中，列组对应的两条数据线DA具有沿列方向的对称轴，同一列组的子像素中像素电路在衬底基板10的正投影关于对称轴对称设置。
示例性地，如图1、图3与图4e所示，同一列组中的驱动晶体管T3共用一个电源转接部VDZB。这样可以使同一列组中的驱动晶体管T3输入的第一电压可以较稳定。
示例性地，如图3与图4e所示，电源线ELVDD在衬底基板10的正投影覆盖电连接的电源转接部VDZB在衬底基板10的正投影。
示例性地，如图3与图4e所示，复位线VREF沿第二方向F2延伸，且沿第一方向F1排列。并且，一条复位线VREF与至少一行子像素对应设置。例如，一条复位线VREF与相邻两行子像素中的像素电路对应电连接。进一步地，同一子像素中，复位线VREF通过第七过孔GK7与复位转接部RSZB电连接，复位转接部RSZB通过第八过孔GK8与复位晶体管T2的有源区的导体化源极区电连接；其中，第七过孔GK7贯穿第二层间绝缘层，第八过孔 GK8贯穿第一层间绝缘层、层间介质层以及栅绝缘层。
示例性地，如图3与图4e所示，位于不同行组且相邻的两行子像素共用一条复位线VREF；并且，同一列中且位于复位线VREF两侧的像素电路在衬底基板的正投影关于复位线VREF在衬底基板10的正投影对称设置。例如，同一列中且位于复位线VREF两侧的像素电路在衬底基板10的正投影关于复位线VREF在衬底基板10的正投影大致呈镜像对称设置。
示例性地，如图3与图4e所示，针对共用同一复位线VREF的两行子像素，两行子像素中的相邻两列子像素共用一个复位转接部RSZB。这样可以使这四个子像素中的复位晶体管T2输入的复位信号的均一性提高。
示例性地，如图3与图4e所示，复位线VREF在衬底基板10的正投影覆盖电连接的复位转接部RSZB在衬底基板10的正投影。
示例性地，如图3与图4e所示，同一列子像素中，第七过孔GK7在衬底基板10的正投影位于第八过孔GK8在衬底基板10的正投影背离数据线DA在衬底基板10的正投影的一侧。
示例性地，如图3与图4e所示，针对一行子像素电路对应的电源线ELVDD、扫描线GA以及复位线VREF，扫描线GA在衬底基板10的正投影位于电源线ELVDD在衬底基板10的正投影与复位线VREF在衬底基板10的正投影之间。
示例性地，在上述的第四导电层0350形成有平坦层，用于保护上述的第四导电层0350。示例性地，如图3至图8所示，在平坦层背离衬底基板10一侧形成有第一电极层0360。其中，第一电极层0360包括位于各子像素中的阳极。其中，各子像素中的阳极通过阳极过孔GK0与阳极连接部YLB电连接。并且，各子像素中的阳极包括相互电连接的阳极主体部和阳极突出部。同一阳极中，阳极主体部与阳极突出部电连接，阳极突出部通过阳极过孔GK0与阳极连接部YLB电连接。并且，阳极过孔GK0贯穿平坦层。这样可以使驱动晶体管T3产生的驱动电流输入发光元件的阳极中。示例性地，各阳极的阳极突出部为非规则图形。
在一些示例中，示例性地，如图3至图8所示，至少一个子像素中，阳极连接部YLB在衬底基板10的正投影与数据线DA在衬底基板10的正投影具有交叠区域。进一步地，部分子像素中，阳极连接部YLB在衬底基板10的正投影与数据线DA在衬底基板10的正投影具有交叠区域。
在一些示例中，示例性地，如图3至图8所示，同一子像素中，阳极连接部YLB在衬底基板10的正投影与第一驱动沟道区T3-A11和第二驱动沟道区T3-A12之间的拐角处在衬底基板10的正投影具有交叠区域。
在一些示例中，示例性地，如图3至图8所示，至少一个子像素中，阳极连接部YLB在衬底基板10的正投影与第二驱动沟道区T3-A12在衬底基板10的正投影的交叠区域大于该阳极连接部YLB在衬底基板10的正投影与第一驱动沟道区T3-A11在衬底基板的正投影的交叠区域。进一步地，部分子像素中，阳极连接部YLB在衬底基板10的正投影与第二驱动沟道区T3-A12在衬底基板10的正投影的交叠区域大于阳极连接部YLB在衬底基板10的正投影与第一驱动沟道区T3-A11在衬底基板10的正投影的交叠区域。
在一些示例中，示例性地，如图3至图8所示，同一列子像素中，阳极连接部沿第一方向排列且未排列于同一直线上。同一行子像素中，阳极连接部沿第一方向排列且未排列于同一直线上。
在一些示例中，示例性地，如图3至图8所示，同一子像素中，阳极转接部YZB靠近第九过孔GK9的部分在衬底基板10的正投影与第一驱动沟道区T3-A11和第二驱动沟道区T3-A12之间的拐角处在衬底基板10的正投影具有交叠区域。
在一些示例中，示例性地，如图3至图8所示，同一列子像素中，阳极转接部沿第一方向排列于同一直线上。同一行子像素中，阳极转接部沿第二方向排列于同一直线上。
在一些示例中，第一电极层背离衬底基板一侧还设置有像素限定层，像素限定层背离衬底基板一些还设置有发光层，发光层背离衬底基板一侧还设置有阴极层。这样可以使阳极、发光层以及阴极形成发光元件。示例性地， 结合图7a和图8，像素限定层可以包括多个开口区域(如：KK1、KK2、KK3、KK4)。其中，一个阳极对应一个开口区域，该开口区域在衬底基板10的正投影位于对应的阳极的阳极主体部在衬底基板10的正投影内。发光层包括多个不同颜色的发光层(如FG1、FG2、FG0)。
示例性地，结合图7a和图8，各子像素中，开口区域(如：KK1、KK2、KK3、KK4)在衬底基板的正投影与阳极过孔GK0在衬底基板的正投影不交叠。
示例性地，结合图7a和图8，电源线在衬底基板的正投影穿过至少两个子像素中的开口区域在衬底基板的正投影。这样可以使这些子像素的开口区域中的阳极尽可能平坦，提高色均一性。
示例性地，如图3、图6至图8所示，第一信号线可以为数据线，第二信号线可以为电源线。或者，第一信号线也可以为数据线，第二信号线也可以为电源线。或者，第一信号线也可以为数据线，第三导电层也可以包括电源线。或者，第二信号线也可以为电源线，第四导电层也可以包括数据线。当然，在实际应用中，可以根据实际应用的需求进行设计确定，在此不作限定。
示例性地，显示面板中的多个子像素可以形成多个重复单元。例如，重复单元可以包括沿第二方向F2相邻的四个子像素。各子像素中的像素电路的结构可以参照上述描述进行设置。示例性地，重复单元中的四个子像素可以包括沿第二方向F2上的第一子像素、第二子像素、第三子像素以及第四子像素。其中，第一子像素中的发光元件可以发红光，第二子像素中的发光元件可以发绿光，第三子像素中的发光元件可以发蓝光，第四子像素中的发光元件可以发绿光。进一步地，相邻两行中，重复单元错位排列。例如，针对不同行中的相邻两个重复单元，这两个重复单元中的一个重复单元中的第二子像素的阳极和另一个重复单元中的第四子像素的阳极沿第一方向F1排列。
示例性地，如图3、图6至图8所示，第一子像素可以包括阳极YG1。其中，阳极YG1可以包括阳极主体部YG11和阳极突出部YG12。并且，开口区域KK1在衬底基板10的正投影位于阳极主体部YG11在衬底基板10的 正投影内。阳极主体部YG11为六边形，阳极突出部YG12为非规则图形。以及阳极突出部YG12向左下角方向突出阳极主体部YG11设置。进一步地，第一子像素可以包括发光层FG1，且发光层FG1在衬底基板10的正投影覆盖阳极主体部YG11在衬底基板10的正投影。示例性地，阳极主体部YG11也可以为四边形、五边形、六边形、八边形等，在此不作限定。开口区域KK1也可以为四边形、五边形、六边形、八边形等，在此不作限定。
示例性地，如图3、图6至图8所示，第二子像素可以包括阳极YG2。其中，阳极YG2可以包括阳极主体部YG21和阳极突出部YG22。并且，开口区域KK2在衬底基板10的正投影位于阳极主体部YG21在衬底基板10的正投影内。阳极主体部YG21为五边形，阳极突出部YG22为非规则图形。以及阳极突出部YG22向第一方向F1的箭头所指的方向突出阳极主体部YG21设置。进一步地，第二子像素可以包括发光层FG2，且发光层FG2在衬底基板10的正投影覆盖阳极主体部YG21在衬底基板10的正投影。示例性地，阳极主体部YG21也可以为四边形、五边形、六边形、八边形等，在此不作限定。开口区域KK2也可以为四边形、五边形、六边形、八边形等，在此不作限定。
示例性地，如图3、图6至图8所示，第三子像素可以包括阳极YG3。其中，阳极YG3可以包括阳极主体部YG31和阳极突出部YG32。并且，开口区域KK3在衬底基板10的正投影位于阳极主体部YG31在衬底基板10的正投影内。阳极主体部YG31为六边形，阳极突出部YG32为非规则图形。以及阳极突出部YG32向右下角方向突出阳极主体部YG31设置。进一步地，第三子像素可以包括发光层FG3，且发光层FG3在衬底基板10的正投影覆盖阳极主体部YG31在衬底基板10的正投影。示例性地，阳极主体部YG31也可以为四边形、五边形、六边形、八边形等，在此不作限定。开口区域KK3也可以为四边形、五边形、六边形、八边形等，在此不作限定。
示例性地，如图3、图6至图8所示，第四子像素可以包括阳极YG4。其中，阳极YG4可以包括阳极主体部YG41和阳极突出部YG42。并且，开 口区域KK4在衬底基板10的正投影位于阳极主体部YG41在衬底基板10的正投影内。阳极主体部YG41为五边形，阳极突出部YG42为非规则图形。以及阳极突出部YG42向与第一方向F1的箭头所指的方向相反的方面突出阳极主体部YG41设置。进一步地，第四子像素可以包括发光层FG4，且发光层FG4在衬底基板10的正投影覆盖阳极主体部YG41在衬底基板10的正投影。示例性地，阳极主体部YG41也可以为四边形、五边形、六边形、八边形等，在此不作限定。开口区域KK4也可以为四边形、五边形、六边形、八边形等，在此不作限定。
示例性地，如图3、图6至图8所示，针对不同行中的相邻两个重复单元沿第一方向F1排列，这两个重复单元中的一个重复单元中的第二子像素的阳极和另一个重复单元中的第四子像素的阳极沿第一方向F1排列。并且，覆盖该第二子像素的阳极的阳极主体部的发光层和覆盖第四子像素的阳极的阳极主体部的发光层一体结构设置。这样可以降低Mask难度。
在一些示例中，结合图3至图8，数据线DA上的数据信号通过第四过孔GK4传输到数据写入晶体管T1的有源区的导体化源极区；传输到数据写入晶体管T1的有源区的导体化源极区的数据信号通过数据写入晶体管T1的有源区的沟道区传输到数据写入晶体管T1的有源区的导体化漏极区；传输到数据写入晶体管T1的有源区的导体化漏极区的数据信号通过第一过孔GK1传输到数据转接部DAZB；传输到数据转接部DAZB通过第二过孔GK2传输到存储电容CST的第一极板CC1。
在一些示例中，结合图3至图8，复位线VREF上的复位信号通过第八过孔GK8传输到复位晶体管T2的有源区的导体化源极区；传输到复位晶体管T2的有源区的导体化源极区的复位信号通过复位晶体管T2的有源区的沟道区传输到复位晶体管T2的有源区的导体化漏极区；传输到复位晶体管T2的有源区的导体化漏极区的复位信号通过第三过孔GK3传输到存储电容CST的第二极板CC2；传输到存储电容CST的第二极板CC2的复位信号通过第十过孔GK10传输到阳极转接部YZB；传输到阳极转接部YZB的复位信号通过第 九过孔GK9传输到阳极连接部YLB。
在一些示例中，结合图3至图8，电源线ELVDD的电源信号通过第五过孔GK5传输到电源转接部VDZB；传输到电源转接部VDZB的电源信号通过第六过孔GK6传输到驱动晶体管T3电连接的驱动突出部TQ。
在一些示例中，结合图3至图8，驱动晶体管T3产生的驱动电流通过第三过孔GK3传输到存储电容CST的第二极板CC2；传输到存储电容CST的第二极板CC2的驱动电流通过第十过孔GK10传输到阳极转接部YZB；传输到阳极转接部YZB的驱动电流通过第九过孔GK9传输到阳极连接部YLB。
需要说明的是，上述过孔可以为具有各向同性特性的过孔，也可以为具有各向异性特性的过孔。例如，上述过孔在衬底基板的正投影可以为圆形、矩形、六边形等，在此不作限定。
基于同一发明构思，本公开实施例还提供了显示装置，包括本公开实施例提供的上述显示面板。该显示装置可以为：智能手表、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。该显示装置的实施可以参见上述电致发光显示面板的实施例，重复之处不再赘述。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (47)

  1. 一种显示面板，其中，包括：
    衬底基板，包括多个子像素；
    有源半导体层，位于所述衬底基板上；
    栅绝缘层，位于所述有源半导体层背离所述衬底基板一侧；
    第一导电层，位于所述栅绝缘层背离所述衬底基板一侧；
    层间介质层，位于所述第一导电层背离所述衬底基板一侧；
    第二导电层，位于所述层间介质层背离所述衬底基板一侧；
    第一层间绝缘层，位于所述第二导电层背离所述衬底基板一侧；
    第三导电层，位于所述第一层间绝缘层背离所述衬底基板一侧；所述第三导电层包括间隔设置的多条第一信号线；
    第二层间绝缘层，位于所述第三导电层背离所述衬底基板一侧；
    第四导电层，位于所述第二层间绝缘层背离所述衬底基板一侧；所述第四导电层包括间隔设置的多条第二信号线；
    所述第一信号线在所述衬底基板的正投与所述第二信号线在所述衬底基板的正投影交叉设置。
  2. 如权利要求1所述的显示面板，其中，所述第一信号线为数据线，所述第二信号线为电源线。
  3. 如权利要求2所述的显示面板，其中，所述第一导电层包括间隔设置的多条扫描线；所述扫描线的延伸方向与所述电源线的延伸方向相同；
    所述第四导电层还包括间隔设置的多条复位线；所述复位线的延伸方向与所述电源线的延伸方向相同；
    针对一行所述子像素电路对应的电源线、扫描线以及复位线，所述扫描线在所述衬底基板的正投影位于所述电源线在所述衬底基板的正投影与所述复位线在所述衬底基板的正投影之间。
  4. 如权利要求1-3任一项所述的显示面板，其中，所述像素电路包括： 驱动晶体管、数据写入晶体管、复位晶体管以及存储电容；
    所述驱动晶体管的第一极与所述电源线电连接，所述驱动晶体管的第二极与发光元件电连接；
    所述存储电容的第一极板与所述驱动晶体管的栅极电连接，所述存储电容的第二极板与所述驱动晶体管的第二极电连接；
    所述数据写入晶体管的栅极与所述扫描线电连接，所述数据写入晶体管的第一极与所述数据线电连接，所述数据写入晶体管的第二极与所述驱动晶体管的栅极电连接；
    所述复位晶体管的栅极与所述扫描线电连接，所述复位晶体管的第一极与复位线电连接，所述复位晶体管的第二极与所述驱动晶体管的第二极电连接。
  5. 如权利要求4所述的显示面板，其中，所述有源半导体层包括所述驱动晶体管的有源区；所述第一导电层包括所述存储电容的第一极板；且所述存储电容的第一极板复用为所述驱动晶体管的栅极；
    所述子像素中，所述存储电容的第一极板在所述衬底基板的正投影与所述驱动晶体管的有源区的沟道区在所述衬底基板的正投影具有交叠区域；
    所述子像素中，所述驱动晶体管的有源区的沟道区包括相互连接设置的第一驱动沟道区和第二驱动沟道区；其中，所述第一驱动沟道区沿第一方向延伸，所述第二驱动区沟道沿第三方向延伸，且所述第一方向与所述第三方向之间的夹角β满足0°<β≤90°。
  6. 如权利要求5所述的显示面板，其中，所述有源半导体层还包括所述复位晶体管的有源区；其中，所述复位晶体管的有源区沿所述第一方向延伸，且所述复位晶体管的有源区位于所述驱动晶体管的第二驱动沟道区背离第一驱动沟道区一侧；
    同一所述子像素中，所述复位晶体管的有源区的导体化漏极区和所述驱动晶体管的第二驱动沟道区连接。
  7. 如权利要求6所述的显示面板，其中，所述有源半导体层还包括所述 数据写入晶体管的有源区；所述数据写入晶体管的有源区分别与所述复位晶体管的有源区和所述驱动晶体管的有源区间隔设置；其中，所述数据写入晶体管的有源区沿所述第一方向延伸；
    同一所述子像素中，所述数据写入晶体管的有源区在所述第二方向上的正投影位于所述驱动晶体管的第二驱动沟道区在所述第二方向上的正投影背离所述复位晶体管的有源区在所述第二方向上的正投影的一侧。
  8. 如权利要求7所述的显示面板，其中，同一所述子像素中，所述数据写入晶体管的有源区的沟道区与所述复位晶体管的有源区的沟道区沿所述第二方向排列。
  9. 如权利要求4-8任一项所述的显示面板，其中，一行子像素对应一条所述扫描线；同一所述子像素中，所述扫描线在所述衬底基板的正投影分别与所述数据写入晶体管的有源区的沟道区与所述复位晶体管的有源区的沟道区具有交叠区域。
  10. 如权利要求3-9任一项所述的显示面板，其中，所述第二导电层包括位于各所述子像素中的数据转接部；
    所述存储电容的第一极板包括相互电连接的第一极板主体部和第一极板突出部；
    同一所述子像素中，所述数据转接部的第一端通过第一过孔与所述数据写入晶体管的有源区的导体化漏极区电连接，所述数据转接部的第二端通过第二过孔与所述第一极板突出部电连接；其中，所述第一过孔贯穿所述栅绝缘层和所述层间介质层，所述第二过孔贯穿所述层间介质层。
  11. 如权利要求10所述的显示面板，其中，所述第二导电层还包括所述存储电容的第二极板；其中，所述存储电容的第二极板包括相互电连接的第二极板主体部和第二极板突出部；
    同一所述子像素中，所述第二极板突出部通过第三过孔与所述复位晶体管的有源区的导体化漏极区电连接；其中，所述第三过孔贯穿所述层间介质层和所述栅绝缘层。
  12. 如权利要求11所述的显示面板，其中，同一所述子像素中，所述第一极板主体部在所述衬底基板的正投影与所述第二极板主体部在所述衬底基板的正投影具有交叠区域。
  13. 如权利要求12所述的显示面板，其中，所述存储电容的第二极板还包括：分别与所述第二极板主体部和所述第二极板突出部电连接的第二极板补偿部；其中，所述第二极板补偿部位于所述第二极板主体部和所述第二极板突出部形成的拐角处；
    同一所述子像素中，所述第二极板补偿部在所述衬底基板的正投影与所述第一极板主体部在所述衬底基板的正投影具有交叠区域。
  14. 如权利要求13所述的显示面板，其中，同一所述子像素中，所述第一极板主体部在所述衬底基板的正投影与所述第二极板突出部在所述衬底基板的正投影靠近所述第二极板主体部在所述衬底基板的正投影的边缘具有交叠区域。
  15. 如权利要求4-14任一项所述的显示面板，其中，一列所述子像素对应一条所述数据线；
    同一所述子像素中，所述数据线通过第四过孔与所述数据写入晶体管的有源区的导体化源极区电连接，其中，所述第四过孔贯穿所述第一层间绝缘层、所述层间介质层以及所述栅绝缘层，且所述第四过孔在所述衬底基板的正投影位于所述扫描线在所述衬底基板的正投影背离所述存储电容的第一极板在所述衬底基板的正投影的一侧。
  16. 如权利要求15所述的显示面板，其中，一条所述电源线与至少一行所述子像素对应设置；
    所述第三导电层还包括间隔设置的多个电源转接部；其中，同一所述子像素中，所述电源线通过第五过孔与所述电源转接部电连接，所述电源转接部通过第六过孔与所述驱动晶体管的有源区的导体化源极区电连接；其中，所述第五过孔贯穿所述第二层间绝缘层，所述第六过孔贯穿所述第一层间绝缘层、所述层间介质层以及所述栅绝缘层。
  17. 如权利要求4-16任一项所述的显示面板，其中，一条所述复位线与至少一行子像素对应设置；
    所述第三导电层还包括间隔设置的多个复位转接部；同一所述子像素中，所述复位线通过第七过孔与所述复位转接部电连接，所述复位转接部通过第八过孔与所述复位晶体管的有源区的导体化源极区电连接；其中，所述第七过孔贯穿所述第二层间绝缘层，所述第八过孔贯穿所述第一层间绝缘层、所述层间介质层以及所述栅绝缘层。
  18. 如权利要求4-17任一项所述的显示面板，其中，所述第四导电层还包括间隔设置的多个阳极连接部；所述第三导电层还包括间隔设置的多个阳极转接部；其中，一个所述子像素包括一个所述阳极连接部和一个所述阳极转接部；
    同一所述子像素中，所述阳极连接部通过第九过孔与所述阳极转接部的第一端电连接，所述阳极转接部的第二端通过第十过孔与所述存储电容的第二极板电连接；其中，所述第九过孔贯穿所述第二层间绝缘层，所述第十过孔贯穿所述第一层间绝缘层。
  19. 如权利要求18所述的显示面板，其中，同一所述子像素中，所述第九过孔在所述衬底基板的正投影和所述第十过孔在所述衬底基板的正投影沿所述第一方向排列。
  20. 如权利要求19所述的显示面板，其中，同一所述子像素中，所述第十过孔在所述衬底基板的正投影位于所述第九过孔在所述衬底基板的正投影背离所述第三过孔在所述衬底基板的正投影的一侧。
  21. 如权利要求20所述的显示面板，其中，同一所述子像素中，所述第九过孔在所述衬底基板的正投影与所述第二极板补偿部在所述衬底基板的正投影具有交叠区域。
  22. 如权利要求18-21任一项所述的显示面板，其中，至少一个子像素中，所述阳极连接部在所述衬底基板的正投影与所述数据线在所述衬底基板的正投影具有交叠区域。
  23. 如权利要求18-22任一项所述的显示面板，其中，同一所述子像素中，所述阳极连接部在所述衬底基板的正投影与所述第一驱动沟道区和所述第二驱动沟道区之间的拐角处在所述衬底基板的正投影具有交叠区域。
  24. 如权利要求23所述的显示面板，其中，至少一个所述子像素中，所述阳极连接部在所述衬底基板的正投影与所述第二驱动沟道区在所述衬底基板的正投影的交叠区域大于所述阳极连接部在所述衬底基板的正投影与所述第一驱动沟道区在所述衬底基板的正投影的交叠区域。
  25. 如权利要求18-24任一项所述的显示面板，其中，同一所述子像素中，所述阳极转接部靠近所述第九过孔的部分在所述衬底基板的正投影与所述第一驱动沟道区和所述第二驱动沟道区之间的拐角处在所述衬底基板的正投影具有交叠区域。
  26. 如权利要求18-25任一项所述的显示面板，其中，同一列所述子像素中，所述阳极连接部沿所述第一方向排列且未排列于同一直线上；
    同一行所述子像素中，所述阳极连接部沿所述第一方向排列且未排列于同一直线上。
  27. 如权利要求18-26任一项所述的显示面板，其中，同一列所述子像素中，所述阳极转接部沿所述第一方向排列于同一直线上；
    同一行所述子像素中，所述阳极转接部沿所述第二方向排列于同一直线上。
  28. 如权利要求1-27任一项所述的显示面板，其中，相邻两个子像素中，像素电路在所述衬底基板的正投影镜像对称设置。
  29. 如权利要求28所述的显示面板，其中，以相邻两行子像素为一个行组，且不同所述行组包括的子像素不同；
    所述行组对应的两条扫描线具有沿行方向的行对称轴，同一所述行组的子像素中像素电路在所述衬底基板的正投影关于所述行对称轴镜像对称设置。
  30. 如权利要求29所述的显示面板，其中，以同一所述行组中的相邻两列子像素为一个列组，且不同所述列组包括的子像素不同；
    所述列组对应的两条数据线具有沿所述列方向的列对称轴，同一所述列组的子像素中像素电路在所述衬底基板的正投影关于所述列对称轴镜像对称设置。
  31. 如权利要求1-30任一项所述的显示面板，其中，所述显示面板还包括：第一电极层，位于所述第四导电层背离所述衬底基板一侧；所述第一电极层包括位于各子像素中的阳极；
    像素限定层，位于所述第一电极层背离所述衬底基板一侧；
    其中，所述像素限定层包括多个开口区域，一个所述阳极对应一个所述开口区域，且同一所述子像素中，所述开口区域在所述衬底基板的正投影位于对应的所述阳极在所述衬底基板的正投影内；
    所述电源线在所述衬底基板的正投影穿过至少两个子像素中的开口区域在所述衬底基板的正投影。
  32. 如权利要求1-31任一项所述的显示面板，其中，同一行组的子像素共用一条所述电源线；
    同一列中且位于所述电源线两侧的像素电路在所述衬底基板的正投影关于所述电源线在所述衬底基板的正投影对称设置。
  33. 如权利要求32所述的显示面板，其中，所述有源半导体层还包括多个驱动突出部；所述行组的同一列的两个子像素中的驱动晶体管的导体化源极区电连接一个驱动突出部；其中，同一所述驱动晶体管中，所述导体化源极区和所述第一驱动沟道区电连接，且相互电连接的所述导体化源极区与所述第一驱动沟道区沿同一方向延伸；
    同一列所述子像素中，所述驱动突出部在所述衬底基板的正投影位于所述导体化源极区在所述衬底基板的正投影背离所述数据线在所述衬底基板的正投影的一侧；
    所述电源转接部通过第六过孔与所述驱动晶体管电连接的驱动突出部电连接，且所述驱动晶体管电连接的驱动突出部在所述衬底基板的正投影覆盖所述第六过孔在所述衬底基板的正投影。
  34. 如权利要求33所述的显示面板，其中，同一列所述子像素中，所述复位晶体管的有源区在所述列方向上的延长线与所述驱动突出部具有交叠区域。
  35. 如权利要求34所述的显示面板，其中，同一列所述子像素中，所述第五过孔在所述衬底基板的正投影位于所述第六过孔在所述衬底基板的正投影背离所述数据线在所述衬底基板的正投影的一侧。
  36. 如权利要求32-35任一项所述的显示面板，其中，同一所述列组中的驱动晶体管共用一个所述电源转接部。
  37. 如权利要求36所述的显示面板，其中，所述电源线在所述衬底基板的正投影覆盖电连接的所述电源转接部在所述衬底基板的正投影。
  38. 如权利要求1-37任一项所述的显示面板，其中，位于不同行组且相邻的两行子像素共用一条复位线；
    同一列中且位于所述复位线两侧的像素电路在所述衬底基板的正投影关于所述复位线在所述衬底基板的正投影对称设置。
  39. 如权利要求38所述的显示面板，其中，针对共用同一所述复位线的两行子像素，所述两行子像素中的相邻两列子像素共用一个所述复位转接部。
  40. 如权利要求39所述的显示面板，其中，所述复位线在所述衬底基板的正投影覆盖电连接的所述复位转接部在所述衬底基板的正投影。
  41. 如权利要求40所述的显示面板，其中，同一列所述子像素中，所述第七过孔在所述衬底基板的正投影位于所述第八过孔在所述衬底基板的正投影背离所述数据线在所述衬底基板的正投影的一侧。
  42. 如权利要求4-41任一项所述的显示面板，其中，数据线上的数据信号通过第四过孔传输到数据写入晶体管的有源区的导体化源极区；
    传输到所述数据写入晶体管的有源区的导体化源极区的数据信号通过所述数据写入晶体管的有源区的沟道区传输到所述数据写入晶体管的有源区的导体化漏极区；
    传输到所述数据写入晶体管的有源区的导体化漏极区的数据信号通过第 一过孔传输到数据转接部；
    传输到所述数据转接部通过第二过孔传输到所述存储电容的第一极板。
  43. 如权利要求4-42任一项所述的显示面板，其中，复位线上的复位信号通过第八过孔传输到复位晶体管的有源区的导体化源极区；
    传输到所述复位晶体管的有源区的导体化源极区的复位信号通过所述复位晶体管的有源区的沟道区传输到所述复位晶体管的有源区的导体化漏极区；
    传输到所述复位晶体管的有源区的导体化漏极区的复位信号通过第三过孔传输到所述存储电容的第二极板；
    传输到所述存储电容的第二极板的复位信号通过第十过孔传输到阳极转接部；
    传输到所述阳极转接部的复位信号通过第九过孔传输到阳极连接部。
  44. 如权利要求4-43任一项所述的显示面板，其中，电源线的电源信号通过第五过孔传输到电源转接部；
    传输到所述电源转接部的电源信号通过第六过孔传输到驱动晶体管电连接的驱动突出部。
  45. 如权利要求4-44任一项所述的显示面板，其中，所述驱动晶体管产生的驱动电流通过第三过孔传输到所述存储电容的第二极板；
    传输到所述存储电容的第二极板的驱动电流通过第十过孔传输到阳极转接部；
    传输到所述阳极转接部的驱动电流通过第九过孔传输到阳极连接部。
  46. 一种显示装置，其中，包括如权利要求1-45任一项所述的显示面板。
  47. 一种如权利要求1-45任一项所述的显示面板的驱动方法，其中，包括：
    复位阶段，同时对各扫描线加载导通控制信号，对复位线加载复位信号，对数据线加载初始化信号，以同时对各驱动晶体管的栅极进行初始化以及对各发光元件进行复位；
    数据写入阶段，依次对所述扫描线加载导通控制信号，对所述复位线加 载复位信号，且在所述扫描线加载所述导通控制信号时，对所述数据线加载相应的数据信号，以对各所述驱动晶体管的栅极输入数据信号；
    发光阶段，同时对各所述扫描线加载截止控制信号，各所述驱动晶体管产生驱动电流，以驱动电连接的发光元件发光。
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