WO2023231810A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2023231810A1
WO2023231810A1 PCT/CN2023/095317 CN2023095317W WO2023231810A1 WO 2023231810 A1 WO2023231810 A1 WO 2023231810A1 CN 2023095317 W CN2023095317 W CN 2023095317W WO 2023231810 A1 WO2023231810 A1 WO 2023231810A1
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Prior art keywords
active
transistor
signal line
coupled
substrate
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PCT/CN2023/095317
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English (en)
French (fr)
Inventor
沙一鸣
李锡平
李兴华
李海博
杨小燕
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2023231810A1 publication Critical patent/WO2023231810A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1229—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different crystal properties within a device or between different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.
  • TFT thin film transistor
  • AMOLED Active Matrix Organic Light Emitting Diode
  • the purpose of this disclosure is to provide a display substrate and a display device for improving the yield of the display substrate.
  • Embodiments of the present disclosure provide a display substrate, which includes: a substrate; a reflective layer located on one side of the substrate; and located on a side of the reflective layer away from the substrate and along a first direction.
  • a plurality of extended first signal lines; and, an active layer located on the side of the first signal line away from the reflective layer, the active layer includes a plurality of active pairs, the active pairs include two Active pattern; the distance between two adjacent active patterns belonging to the same active pair is less than the distance between two adjacent active patterns belonging to different active pairs; the active pattern is along the second direction Extend, the first direction intersects the second direction; the orthographic projection of the active pattern on the substrate partially overlaps the orthographic projection of the first signal line on the substrate, A portion of the active pair that does not overlap with the first signal line has a gap; an orthographic projection of the reflective layer on the substrate covers at least a portion of the gap of at least one active pair.
  • the active pattern includes: a first channel and a first connection pattern connected to a first end of the first channel, and the first signal line is on a positive side of the substrate.
  • the projection covers the orthographic projection of the first channel on the substrate; the orthographic projection of the first connection pattern on the substrate is identical to the orthographic projection of the first signal line on the substrate.
  • Overlap; the gap includes a first sub-gap between two adjacent first connection patterns in the active pair; the orthographic projection of the reflective layer on the substrate covers at least one of the first sub-gap.
  • the active pattern further includes: a second connection pattern connected to the second end of the first channel, the second connection pattern and the first connection pattern are arranged oppositely and located at the Both sides of the first signal line; the orthographic projection of the second connection pattern on the substrate does not overlap with the orthographic projection of the first signal line on the substrate; the gap also includes a The active center centers a second sub-gap between two adjacent second connection patterns; an orthographic projection of the reflective layer on the substrate covers at least one of the second sub-gaps.
  • the display substrate further includes: a plurality of second signal lines extending along the first direction, the second signal lines being arranged in the same layer as the first signal lines; the active pattern It also includes: a second channel connected to the first The third end of the second channel and the third connection pattern of the second connection pattern, and the fourth connection pattern connected to the fourth end of the second channel away from the third connection pattern; the second The orthographic projection of the signal line on the substrate covers the orthographic projection of the second channel on the substrate; the third connection pattern and the fourth connection pattern are located on both sides of the second signal line.
  • the orthographic projection of the third connection pattern and the fourth connection pattern on the substrate does not overlap with the orthographic projection of the second signal line on the substrate; on the same active pair , the distance between two adjacent first connection patterns, the distance between two adjacent second connection patterns, and the distance between two adjacent third connection patterns are all smaller than the distance between two adjacent fourth connection patterns.
  • the spacing between patterns; the gap also includes a third sub-gap between two adjacent third connection patterns in the active pair; the orthographic projection of the reflective layer on the substrate covers at least one At least a portion of the third sub-gap.
  • the reflective layer includes a plurality of reflective patterns, and an orthographic projection of one of the reflective patterns on the substrate covers at least a portion of a gap of an active pair.
  • At least two of the reflective patterns are connected to form an integrated structure.
  • the material of the active layer includes metal oxide.
  • the reflectivity of the reflective layer is greater than or equal to 85%.
  • the light absorption coefficient of the reflective layer ranges from 1.0 to 2.0.
  • the material of the reflective layer includes at least one of aluminum, copper, and molybdenum.
  • the display substrate further includes: a plurality of pixel circuits; the pixel circuit includes: a compensation transistor; the compensation transistor includes the first channel and a first gate pattern; the first gate The pole pattern is connected to the first signal line and forms an integrated structure.
  • the display substrate further includes: a plurality of pixel circuits; the pixel circuit includes: a first reset transistor, a first electrode of the first reset transistor is electrically connected to a first electrode of the compensation transistor. ;
  • the first reset transistor includes the second channel and a second gate pattern;
  • the second gate pattern is connected to the second signal line and forms an integrated structure.
  • the pixel circuit further includes: a writing transistor, a driving transistor, a second reset transistor, a first luminescence control transistor, a second luminescence control transistor, and a storage capacitor; the gate of the writing transistor is connected to the first luminescence control transistor.
  • a scan signal line is coupled, the first pole of the write transistor is coupled to the data signal line, the second pole of the write transistor is coupled to the first node; the gate of the drive transistor is coupled to the second node coupled, the first pole of the driving transistor is coupled to the first node, the second pole of the driving transistor is coupled to the third node; the second pole of the compensation transistor is coupled to the third node connected; the gate of the first light-emitting control transistor is coupled to the enable signal line, the first electrode of the first light-emitting control transistor is coupled to the voltage signal line, and the second electrode of the first light-emitting control transistor is coupled to The first node is coupled; the gate of the second light-emitting control transistor is coupled to the enable signal line, the first pole of the second light-emitting control transistor is coupled to the third node, and the The second electrode of the second light emission control transistor is coupled to the fourth node; the second electrode of the first reset transistor is coupled to the first initialization signal line; the gate electrode of the second reset transistor is coupled to the
  • the reset signal line is coupled, the first pole of the second reset transistor is coupled to the second initialization signal line, the second pole of the second reset transistor is coupled to the fourth node; the third pole of the storage capacitor is coupled One plate is coupled to the voltage signal line, and a second plate of the storage capacitor is coupled to the second node.
  • the compensation transistor and the first reset transistor are oxide transistors
  • the write transistor, the drive transistor, the second reset transistor, the first light emission control transistor and the The second light-emitting control transistors are all low-temperature polysilicon transistors.
  • An embodiment of the present disclosure also provides a display device, which includes: the display substrate as described in any one of the above embodiments.
  • the orthographic projection of the reflective layer on the substrate covers at least a part of the gap of at least one active pair. Therefore, when preparing the active pattern of the same active pair, from Part of the light irradiated by the opening pattern of the mask onto the reflective layer is reflected, and part of the reflected light is directed to the photoresist at at least a part of the gap corresponding position, which increases the amount of light irradiated to the photoresist at at least a part of the gap corresponding position, exacerbating the problem.
  • the photoresist between the two photolithography patterns is completely removed, and the active film is etched under the mask of the photolithography pattern.
  • the active film is etched under the mask of the photolithography pattern.
  • the beneficial effects that can be achieved by the display device provided by some embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the display substrate provided by some of the above embodiments, and will not be described again here.
  • Figure 1 is a structural diagram of a display device according to some embodiments of the present disclosure.
  • Figure 2 is a structural diagram of a display substrate according to some embodiments of the present disclosure.
  • Figure 3A is an equivalent diagram of a pixel circuit and a light-emitting device according to some embodiments of the present disclosure
  • Figure 3B is a structural diagram of a display substrate according to some embodiments of the present invention.
  • Figure 4 is a structural diagram of a display substrate according to some embodiments of the present disclosure.
  • Figure 5A is a schematic diagram of exposing photoresist during the production process of active patterns according to some embodiments of the present disclosure
  • Figure 5B shows the photoresist after being exposed and developed during the production process of active patterns according to some embodiments of the present disclosure.
  • Figure 6A is a top view of some film layers in a display substrate according to some embodiments of the present disclosure.
  • Figure 6B is a schematic diagram of exposing photoresist during the production process of active patterns in some embodiments of the present disclosure
  • 6C is a schematic diagram after the photoresist is exposed and developed during the production process of the active pattern in some embodiments of the present disclosure
  • Figure 6D is a partial view of a display substrate according to some embodiments of the present disclosure.
  • Figure 6E is a partial view of some film layers in a display substrate according to some embodiments of the present disclosure.
  • Figure 7A is a structural diagram of yet another display substrate according to some embodiments of the present disclosure.
  • Figure 7B is a structural diagram of yet another display substrate according to some embodiments of the present disclosure.
  • Figure 7C is a structural diagram of yet another display substrate according to some embodiments of the present disclosure.
  • Figure 7D is a structural diagram of yet another display substrate according to some embodiments of the present disclosure.
  • 8A is a schematic diagram of exposing photoresist during the production process of active patterns in some embodiments of the present disclosure
  • FIG. 8B is a schematic diagram after the photoresist is exposed and developed during the production process of active patterns in some embodiments of the present disclosure
  • FIG. 9 is a schematic diagram of exposing photoresist during the production of active patterns according to some embodiments of the present disclosure.
  • Coupled and its derivatives may be used.
  • some embodiments may be described using the term “coupled” to indicate that two or more components are in direct physical or electrical contact with each other.
  • the embodiments disclosed herein are not necessarily limited by the content herein.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • the transistors used in the circuit structure can be thin film transistors (Thin Film Transistor, TFT for short), field effect transistors (Metal Oxide Semiconductor, MOS for short) or other characteristics.
  • thin film transistors are used as examples in the embodiments of the present disclosure for description.
  • the first electrode of each transistor used is one of the source electrode and the drain electrode
  • the second electrode of each transistor is the other of the source electrode and the drain electrode. Since the source and drain of the transistor may be symmetrical in structure, the source and drain of the transistor may be structurally indistinguishable. That is to say, the first electrode and the third electrode of the transistor in the embodiment of the present disclosure
  • the two poles can be structurally indistinguishable.
  • the transistor is a P-type transistor
  • the first electrode of the transistor is the source electrode
  • the second electrode is the drain electrode
  • the first electrode of the transistor is the drain electrode
  • the second pole is the source.
  • nodes such as the first node and the second node do not represent actual existing components, but represent the meeting points of relevant couplings in the circuit diagram. That is to say, these nodes are formed by the relevant couplings in the circuit diagram.
  • the P-type transistor can be turned on under the control of a low-level signal
  • the N-type transistor can be turned on under the control of a high-level signal
  • some embodiments of the present disclosure provide a display device 2000 , which includes a display substrate 1000 .
  • the above-mentioned display device 2000 may be an OLED (Organic Light Emitting Diode, organic light emitting diode) display device.
  • OLED Organic Light Emitting Diode, organic light emitting diode
  • the display device 2000 also includes a frame, a display driver IC (Integrated Circuit, integrated circuit), and other electronic accessories.
  • a display driver IC Integrated Circuit, integrated circuit
  • the above-mentioned display device 2000 may be any display device that displays videos or still images. More specifically, it is contemplated that the display devices of the embodiments may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants, etc.
  • PDA handheld or portable computer
  • GPS receiver/navigator camera
  • MP4 video player video player
  • video camera game console
  • watch clock
  • calculator TV monitor
  • flat panel display computer monitor
  • automotive monitor e.g., odometer display, etc.
  • navigator cockpit controller and/or display
  • display of camera view e.g., display of rear view camera in vehicle
  • electronic photo electronic billboard or sign
  • projector construction Structure
  • packaging and aesthetic structure for example, for the display of an image of a piece of jewelry
  • the above-mentioned display substrate 1000 includes: a substrate 100 , a plurality of pixel circuits 200 disposed on one side of the substrate 100 , and a plurality of pixel circuits 200 disposed on a side away from the substrate 100 .
  • a plurality of light emitting devices 300 is shown in FIG. 2 .
  • the above-mentioned substrate 100 may be a flexible substrate or a rigid substrate.
  • the material of the substrate 100 may be dimethylsiloxane, PI (Polyimide, polyimide), PET (Polyethylene terephthalate, polyethylene terephthalate). Alcohol ester) and other highly elastic materials.
  • the material of the substrate 100 may be glass or the like.
  • the plurality of pixel circuits 200 and the plurality of light-emitting devices 300 may be coupled in one-to-one correspondence. In other examples, one pixel circuit 200 may be coupled with multiple light-emitting devices 300 , or multiple pixel circuits 200 may be coupled with one light-emitting device 300 .
  • the present disclosure schematically illustrates the structure of the display substrate 1000 by taking the coupling of a pixel circuit 200 and a light-emitting device 300 as an example.
  • the pixel circuit 200 may generate a driving signal.
  • Each light-emitting device 300 can emit light under the driving action of the corresponding pixel circuit 200.
  • the light emitted by the multiple light-emitting devices 300 cooperates with each other, so that the display substrate 1000 realizes the display function.
  • the above-mentioned light-emitting device 300 may be an OLED.
  • the pixel circuit 200 includes a variety of structures, and the settings can be selected according to actual needs.
  • the structure of the pixel circuit 200 may include a "6T1C", “7T1C”, “6T2C” or “7T2C” structure.
  • T represents a transistor
  • the number in front of “T” represents the number of transistors
  • C represents a storage capacitor
  • the number in front of “C” represents the number of storage capacitors.
  • the structure of the pixel circuit 200 is a “7T1C” structure.
  • FIG. 3A illustrates an equivalent circuit diagram of the pixel circuit 200 and the light-emitting device 300.
  • the display substrate 1000 includes: a plurality of first scanning signal lines GateP, a plurality of second scanning signal lines GateN, a plurality of data signal lines Data, a plurality of first reset signal lines ResetP, a plurality of second reset signal lines ResetN, a plurality of voltage signal lines VDD, a plurality of first initialization signal lines Vinit1, A plurality of second initialization signal lines Vinit2 and a plurality of enable signal lines EM.
  • the first scanning signal line GateP is used to transmit the first scanning signal
  • the second scanning signal line GateN is used to transmit the second scanning signal
  • the data signal line Data is used to transmit the data signal
  • the first reset signal line ResetP is used to transmit the third scanning signal.
  • a reset signal, the second reset signal line ResetN is used to transmit the second reset signal
  • the voltage signal line VDD is used to transmit the voltage signal
  • the first initialization signal line Vinit1 is used to transmit the first initialization signal
  • the second initialization signal line Vinit2 is used to The second initialization signal is transmitted
  • the enable signal line EM is used to transmit the enable signal.
  • the plurality of first scanning signal lines GateP, the plurality of second scanning signal lines GateN, the plurality of first reset signal lines ResetP, the plurality of second reset signal lines ResetN, the plurality of voltage signal lines VDD, the plurality of first The initialization signal line Vinit1, the plurality of second initialization signal lines Vinit2, and the plurality of enable signal lines EM may all extend along the first direction X, and the plurality of data signal lines Data may extend along the second direction Y.
  • the display substrate 1000 further includes: a plurality of common voltage signal lines VSS, and the common voltage signal lines VSS are used to transmit a common voltage.
  • the pixel circuit 200 includes: a first reset transistor T1, a second reset transistor T2, a writing transistor T3, a driving transistor T4, a compensation transistor T5, a first light emitting control transistor T6, a second light emitting transistor T6.
  • the gate of the first reset transistor T1 is coupled to the second reset signal line ResetN
  • the first electrode of the first reset transistor T1 is coupled to the second node N2
  • the first reset transistor T1 The second pole is coupled to the first initialization signal line Vinit1.
  • the first reset transistor T1 is configured to be turned on under the control of the second reset signal transmitted by the second reset signal line ResetN, and transmit the first initialization signal received at the first initialization signal line Vinit1 to the second Node N2 resets the second node N2.
  • the gate of the second reset transistor T2 is coupled to the first reset signal line ResetP
  • the first electrode of the second reset transistor T2 is coupled to the second initialization signal line Vinit2
  • the second reset The second electrode of the transistor T2 is coupled to the fourth node N4, that is, coupled to the light emitting device 300.
  • the second reset transistor T2 is configured to be turned on under the control of the first reset signal transmitted by the first reset signal line ResetP, and transmit the second initialization signal received at the second initialization signal line Vinit2 to the fourth Node N4, resets the fourth node N4.
  • the gate electrode of the writing transistor T3 is coupled to the first scanning signal line GateP, the first electrode of the writing transistor T3 is coupled to the data signal line Data, and the second electrode of the writing transistor T3 is coupled to the data signal line Data.
  • the first pole is coupled to the first node N1, that is, the first pole of the driving transistor T4 is coupled.
  • the writing transistor T3 is configured to be turned on under the control of the first scanning signal transmitted by the first scanning signal line GateP, and transmit the data signal received at the data signal line Data to the first node N1.
  • the gate of the driving transistor T4 is coupled to the second node N2, and the driving transistor T4
  • the first pole of the driving transistor T4 is coupled to the first node N1
  • the second pole of the driving transistor T4 is coupled to the third node N3.
  • the driving transistor T4 is configured to be turned on under the control of the voltage of the second node N2, and transmit the electrical signal (for example, a data signal) from the first node N1 to the third node N3.
  • the gate of the compensation transistor T5 is coupled to the second scanning signal line GateN, and the first electrode of the compensation transistor T5 is coupled to the second node N2, that is, to the gate of the driving transistor T4. Coupled; the second pole of the compensation transistor T5 is coupled to the third node N3, that is, coupled to the second pole of the driving transistor T4, wherein the compensation transistor T5 is configured to transmit on the second scanning signal line GateN It is turned on under the control of the second scan signal to transmit the electrical signal (for example, a data signal) from the third node N3 to the second node N2.
  • the electrical signal for example, a data signal
  • the gate of the first light-emitting control transistor T6 is coupled to the enable signal line EM
  • the first electrode of the first light-emitting control transistor T6 is coupled to the voltage signal line VDD
  • the first light-emitting control transistor T6 is coupled to the enable signal line EM.
  • the second pole of the transistor T6 is coupled to the first node N1.
  • the first light emitting control transistor T6 is configured to be turned on under the control of the enable signal transmitted by the enable signal line EM, and transmit the voltage signal received at the voltage signal line VDD to the first node N1.
  • the gate of the second light-emitting control transistor T7 is coupled to the enable signal line EM
  • the first electrode of the second light-emitting control transistor T7 is coupled to the third node N3
  • the second light-emitting control transistor T7 is coupled to the third node N3.
  • the second pole of the transistor T7 is coupled to the fourth node N4.
  • the second light emitting control transistor T7 is configured to be turned on under the control of the enable signal transmitted by the enable signal line EM, and transmit the electrical signal (eg voltage signal) from the third node N3 to the fourth node N4 .
  • the first plate of the storage capacitor Cst is coupled to the voltage signal line VDD; the second plate of the storage capacitor Cst is coupled to the second node N2.
  • the working process of the pixel circuit 200 includes a reset phase, a data writing and compensation phase, and a light emitting phase in sequence.
  • the first reset transistor T1 is turned on, transmits the first initialization signal to the second node N2, and resets the second node N2 . Since the second node N2 is coupled to the second plate of the storage capacitor Cst, the gate of the driving transistor T4 and the first pole of the compensation transistor T5, when the second node N2 is reset, the storage capacitor Cst can be synchronously reset. The second electrode of the drive transistor T4 and the first electrode of the compensation transistor T5 are reset. Wherein, the driving transistor T4 can be turned on under the control of the first initialization signal.
  • the second reset transistor T2 is turned on under the control of the first reset signal transmitted by the first reset signal line ResetP.
  • the second reset transistor T2 transmits the second initialization signal to the fourth node N4 to reset the fourth node N4. Since the fourth node N4 is coupled to the anode of the light-emitting device 300, when the fourth node N4 is reset, the anode of the light-emitting device 300 can be reset simultaneously.
  • the writing transistor T3 is turned on under the control of the first scanning signal transmitted by the first scanning signal line GateP
  • the compensation transistor T5 is turned on under the control of the second scanning signal transmitted by the second scanning signal line GateN. Conducted under control.
  • the write transistor T3 transmits the data signal to the first node N1, and the drive transistor T4 will transmit the data signal from the first node N1.
  • the data signal of node N1 is transmitted to the third node N3.
  • the compensation transistor T5 transmits the data signal from the third node N3 to the second node N2, and charges the driving transistor T4 until the compensation of the threshold voltage of the driving transistor T4 is completed.
  • the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are turned on at the same time under the control of the enable signal.
  • the first light emission control transistor T6 transmits a voltage signal to the first node N1.
  • the driving transistor T4 transmits the voltage signal from the first node N1 to the third node N3.
  • the second light emission control transistor T7 transmits the voltage signal from the third node N3 to the fourth node N4.
  • the light emitting device 300 emits light under the action of the voltage signal from the fourth node N4 and the common voltage from the common voltage line VSS.
  • the display substrate 1000 includes: a plurality of first signal lines 1 located on one side of the substrate 100 and extending along the first direction X, and the first signal lines 1 located away from the substrate 100 Active layer 2 on one side.
  • a first insulation layer is provided between the first signal line 1 and the active layer 2 .
  • the first insulating layer is used to electrically insulate the first signal line 1 and the active layer 2 .
  • the material of the first insulating layer includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide, and the present disclosure is not limited thereto.
  • the active layer 2 includes a plurality of active pairs 20 , and the active pairs 20 include two active patterns 21 .
  • the distance between two adjacent active patterns 21 belonging to the same active pair 20 is smaller than the distance between two adjacent active patterns 21 belonging to different active pairs 20 .
  • spacing between two adjacent active patterns 21 of the same active pair 20 refers to: the minimum distance between two adjacent active patterns 21 included in the same active pair 20. spacing.
  • the active pattern 21 extends along the second direction Y.
  • the orthographic projection of the active pattern 21 on the substrate 100 partially overlaps the orthographic projection of the first signal line 1 on the substrate 100 , and the portion of the active pair 20 that does not overlap with the first signal line 1 has a gap 23 .
  • the second direction Y intersects the first direction X.
  • the angle between the first direction X and the second direction Y can be selected and set according to actual needs.
  • the angle between the first direction X and the second direction Y is 85°, 88°, or 90°.
  • the first signal line 1 extends along the first direction X
  • the active pattern 21 extends along the second direction Y. Since the second direction Y intersects the first direction X, the first signal line 1 extends along the substrate 100
  • the part of the first signal line 1 located in the above-mentioned same overlapping pattern constitutes the gate pattern of some transistors
  • the part of the active pattern 21 connected to the above-mentioned same overlapping pattern constitutes the first electrode pattern of some transistors. Or the second pole.
  • the following steps can be performed: 1. Active thin film deposition; 2. Coat photoresist on the active film; 3. Expose and develop the photoresist to form a photoresist pattern; 4. Use the photoresist pattern as a mask to etch the active layer to form an active pattern; 5. Remove the photoresist.
  • a photoresist completely retained part and a photoresist completely removed part are formed through processes such as exposure and development, and the photoresist completely removed part is removed to obtain a photoresist pattern.
  • FIG. 5A is a schematic diagram of the photoresist 01 being exposed
  • FIG. 5B is a schematic diagram of the photoresist 01 after being exposed and developed.
  • the mask plate 02 includes a plurality of opening patterns.
  • Light is irradiated onto the photoresist 01 through the plurality of opening patterns to expose and develop the photoresist 01.
  • the photoresist 01 at corresponding positions of the plurality of opening patterns is completely removed, and the photoresist in other locations is retained, resulting in photoresist pattern 011. Therefore, when the active film 2' is etched, the portions of the active film 2' corresponding to the plurality of opening patterns are etched away to form the active pattern 21.
  • the pixel density is higher, resulting in a smaller spacing between the two active patterns 21 included in the active pair 20 .
  • FIG. 6B is a schematic diagram of the photoresist 01 being exposed
  • FIG. 6C is a schematic diagram of the photoresist 01 after being exposed and developed
  • FIG. 6D and FIG. 6E are partial views of the display substrate 1000.
  • the spacing between the two active patterns 21 included in the active pair 20 is small. Therefore, in the process of forming the active patterns 21, the two photoresist patterns 011 are formed after the photoresist 01 is exposed and developed. The spacing between them is smaller.
  • the width of the opening pattern 021 on the mask plate 02 is smaller.
  • the smaller width results in the amount of light irradiating onto the photoresist 01 through the opening pattern 021. is smaller, resulting in that the photoresist 01 corresponding to the opening pattern 021 is not completely removed (as shown in FIG. 6C). Therefore, when the active film 2' is etched to form the active pattern 21, the two Due to the residual photoresist 01 between the source patterns 21, the active film 2' is not sufficiently etched at this position, resulting in the existence of residual active film at this position, resulting in two active pairs in the active pair 20. There is a short circuit problem between patterns 21.
  • the active film is not sufficiently etched, and there is active film residue.
  • the display substrate 1000 provided by some embodiments of the present disclosure further includes a reflective layer 3 located between the substrate 100 and the first signal line 1 , as shown in FIGS. 7A to 7C .
  • a second insulating layer is provided between the first signal line 1 and the reflective layer 3 .
  • the second insulating layer is used to electrically insulate the first signal line 1 and the reflective layer 3 .
  • the material of the second insulating layer includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide, and the present disclosure is not limited thereto.
  • the orthographic projection of the reflective layer 3 on the substrate 100 covers at least a portion of the gap 23 of at least one active pair 21 .
  • the orthographic projection of the above-mentioned “reflective layer 3 on the substrate 100 at least covers at least one active pair 20 "At least part of the gap 23" includes: the orthographic projection of the reflective layer 3 on the substrate 100 covers a part of the gap 23 of at least one active pair 20, or completely covers the entire gap 23 of at least one active pair 20; and, the reflective layer 3.
  • the orthographic projection on the substrate 100 not only covers at least a part of the gap 23 of at least one active pair 20, but also covers the non-gap position of one active pair 20 and other situations.
  • FIG. 8A is a schematic diagram of the photoresist 01 being exposed
  • FIG. 8B is a schematic diagram of the photoresist 01 after being exposed and developed.
  • the light incident from the opening pattern 021 or other opening patterns of the mask 02 passes through the active film 2' and the second insulating layer 10 and is irradiated to the reflective layer 3. Part of the light irradiated to the reflective layer 3 is reflected, and part of the reflected light is reflected.
  • the photoresist 01 corresponding to the position of the opening pattern 021 is further exposed, so that the photoresist 01 corresponding to the position of the opening pattern 021 is completely removed.
  • the photoresist 01 corresponding to the position increases the amount of light irradiating the photoresist 01, intensifying the exposure of the photoresist 01 at this position, so that after the photoresist 01 is exposed and developed, the two photoresist patterns
  • the photoresist between 011 is completely removed, and the active film 2' is etched under the mask of the photoresist pattern 011.
  • the active film can be etched more fully. This avoids the residual active film material between the two active patterns 21 in the active pair 20 , reduces the probability of short circuit between the two active patterns 21 in the active pair 20 , and is beneficial to improving the performance of the display substrate 1000 Yield.
  • the orthographic projection of the reflective layer 3 on the substrate 100 overlaps with the orthographic projection of the active pattern 21 on the substrate 100 and the orthographic projection of the first signal line 1 on the substrate 100 . overlap.
  • the light incident from the opening pattern of the mask plate 02 passes through the active film 2 ′, the first insulating layer 11 and the second insulating layer 10 and irradiates the reflective layer 3 .
  • Part of the light from the reflective layer 3 is reflected, and part of the reflected light is directed to the overlapping pattern of the orthographic projection of the first signal line 1 on the substrate 100 and the orthographic projection of the active pattern 21 on the substrate 100 .
  • the material of the first signal line 1 includes conductive metal.
  • the conductive metal may include at least one of aluminum, copper, and molybdenum. Aluminum, copper, and molybdenum all have higher reflectivities. Therefore, the reflectivity of the first signal line 1 is high, and the light emitted to the overlapping pattern of the orthographic projection of the first signal line 1 on the substrate 100 and the orthographic projection of the active pattern 21 on the substrate 100, The part of the photoresist 01 that needs to be completely retained will not be affected by the first signal line 1.
  • the orthographic projection of the active pattern 21 on the substrate 100 is consistent with the first signal line 1. The width of the orthographic overlapping pattern on the substrate 100 is not affected, thus ensuring the uniformity of the transistor channel size.
  • the active pattern 21 includes: a first channel 210 and a first connection pattern 211 connected to the first end of the first channel 210 .
  • the orthographic projection of the first signal line 1 on the substrate 100 covers the orthographic projection of the first channel 210 on the substrate 100 , that is, the active pattern 21 is on
  • the orthographic projection on the substrate 100 has the same overlapping pattern as the orthographic projection of the first signal line 1 on the substrate 100 , and the active pattern 21 is located in the same overlapping pattern.
  • the part in the pattern is the first channel 210; the orthographic projection of the first connection pattern 211 on the substrate 100 does not overlap with the orthographic projection of the first signal line 1 on the substrate 100.
  • the first channel 210 constitutes the channel of part of the transistor
  • the first connection pattern 211 connected to the first channel 210 constitutes the first pole or the second pole of part of the transistor.
  • the gap 23 includes a first sub-gap 231 located between two adjacent first connection patterns 211 in the active pair 20 .
  • the orthographic projection of the reflective layer 3 on the substrate 100 covers at least one first sub-gap 231 .
  • the orthographic projection of the reflective layer 3 on the substrate 100 may cover one or more first sub-gaps 231 .
  • the orthographic projection of the reflective layer 3 on the substrate 100 may cover a plurality of first sub-gaps 231 .
  • part of the light irradiating the reflective layer 3 from the opening pattern 021 or other opening patterns of the mask 02 is reflected, and the part of the reflected light is directed to at least one first sub-gap 231, increasing
  • the exposure of the photoresist 01 is intensified, so that after the photoresist 01 is exposed and developed, it is in contact with the at least one first sub-gap 231.
  • the photoresist 01 corresponding to position 231 is completely removed, forming a photolithography pattern corresponding to the first connection pattern 211.
  • the active film is etched to form the first connection pattern.
  • the active layer film corresponding to at least one first sub-gap 231 can be more fully etched, avoiding the presence of residues of active film material at the first sub-gap 231, and reducing the number of active layers in the active pair 20.
  • the active pattern 21 will be short-circuited at the first sub-gap 231. Therefore, it is more conducive to improving the yield of the display substrate 1000.
  • the active pattern 21 further includes: a second connection pattern 212 connected to the second end of the first channel 210 .
  • the second connection pattern 212 and the first connection pattern 211 are arranged oppositely and located on both sides of the first signal line 1 .
  • the orthographic projection of the second connection pattern 212 on the substrate 100 does not overlap with the orthographic projection of the first signal line 1 on the substrate 100 .
  • the first connection pattern 211 constitutes a first pole of part of the transistor, and the second connection pattern 212 constitutes a second pole of the transistor. In other examples, the first connection pattern 211 constitutes the second pole of part of the transistor, and the second connection pattern 212 constitutes the first pole of the transistor, which is not limited in the embodiments of the present disclosure.
  • the gap 23 further includes a second sub-gap 232 located between two adjacent second connection patterns 212 in the active pair 20 .
  • the orthographic projection of the reflective layer 3 on the substrate 100 covers at least one second sub-gap 232 .
  • the orthographic projection of the reflective layer 3 on the substrate 100 may cover one or more second sub-gaps 232 .
  • the orthographic projection of the reflective layer 3 on the substrate 100 may cover a plurality of second sub-gaps 232 .
  • part of the light irradiating the reflective layer 3 from the opening pattern 021 or other opening patterns of the mask 02 is reflected, and the part of the reflected light is directed to at least one second sub-gap 232, increasing The amount of light irradiated to the photoresist 01 is increased, and the exposure of the photoresist 01 is intensified, so that after the photoresist 01 is exposed and developed, the photoresist 01 corresponding to the position of at least one second sub-gap 232 is completely removed. , forming a photolithography pattern corresponding to the second connection pattern 212, and etching the active film under the mask of the photolithography pattern.
  • the second connection pattern 212 When the second connection pattern 212 is formed, it can be made to correspond to at least one second sub-substrate.
  • the active film at the gap 232 is etched more fully to avoid the presence of residual active film material at the second sub-gap 232 , thereby reducing the risk of the two active patterns 21 in the active pair 20 at the second sub-gap 232
  • the probability of short circuit occurrence is therefore more conducive to improving the yield of the display substrate 1000 .
  • the display substrate 1000 further includes a plurality of second signal lines 12 extending along the first direction X.
  • the second signal line 12 is arranged on the same layer as the first signal line 1 .
  • “same layer” refers to a layer structure formed by using the same film formation process to form a film layer for forming a specific pattern, and then using the same mask to form a patterning process.
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights. Or have different thicknesses. In this way, the patterns of the second signal line 12 and the first signal line 1 can be produced at the same time, which is beneficial to simplifying the manufacturing process of the display substrate 1000 .
  • the active pattern 21 further includes: a second channel 220 , a third connection pattern 221 connecting the third end of the second channel 220 and the second connection pattern 212 , and a fourth connection pattern 222 connected to the fourth end of the second channel 220 away from the third connection pattern 221.
  • the orthographic projection of the second signal line 12 on the substrate 100 covers the orthographic projection of the second channel 220 on the substrate 100 .
  • the third connection pattern 221 and the fourth connection pattern 222 are located on both sides of the second signal line 12 , and the third connection pattern 221 and the fourth connection pattern 222 are on the substrate.
  • the orthographic projection on the substrate 100 does not overlap with the orthographic projection of the second signal line 12 on the substrate 100 .
  • the second channel 220 constitutes the channel of part of the transistor; the third connection pattern 221 and the fourth connection pattern 222 constitute the first pole or the second pole of part of the transistor.
  • the third connection pattern 221 constitutes the first pole of some transistors, and the fourth connection pattern 222 constitutes the second pole of some transistors; or the third connection pattern 221 constitutes the second pole of some transistors, and the fourth connection pattern 222 constitutes a part of the first pole of the transistor.
  • the first pole of the transistor is not limited in the embodiments of the present disclosure.
  • the spacing between two adjacent first connection patterns 211 , the spacing between two adjacent second connection patterns 212 and The distance between two adjacent third connection patterns 221 is smaller than the distance between two adjacent fourth connection patterns 222 .
  • the spacing between two adjacent first connection patterns 211 , the spacing between two adjacent second connection patterns 212 and the spacing between two adjacent third connection patterns 221 can be equal or different. Equally, the embodiments of the present disclosure do not limit this.
  • the spacing between two adjacent first connection patterns 211 is equal to the spacing between two adjacent second connection patterns 212 .
  • the gap 23 further includes a third sub-gap 233 located between two adjacent third connection patterns 221 in the active pair 20 .
  • the orthographic projection of the reflective layer 3 on the substrate 100 covers at least a part of the at least one third sub-gap 233 .
  • the orthographic projection of the reflective layer 3 on the substrate 100 covers at least a part of at least one third sub-gap 233
  • the orthographic projection of the reflective layer 3 on the substrate 100 covers at least one third sub-gap.
  • a part of 233, or the orthographic projection of the reflective layer 3 on the substrate 100 covers at least the entire third sub-gap 233, and other situations.
  • the third connection pattern 221 includes a first sub-connection pattern 2211 and a second sub-connection pattern 2212. Among them, the first sub-connection pattern 2211 is closer to the second connection pattern 212 than the second sub-connection pattern 2212.
  • the distance between two adjacent first sub-connection patterns 2211 is smaller than the distance between two adjacent second sub-connection patterns 2212 .
  • the orthographic projection of the reflective layer 3 on the substrate 100 can cover the gap between the two adjacent first sub-connection patterns 2211, or the orthographic projection of the reflective layer 3 on the substrate 100 can cover the gap between the two adjacent first sub-connection patterns 2211.
  • part of the light irradiating the reflective layer 3 from the opening pattern 021 or other opening patterns of the mask 02 is reflected, and the part of the reflected light is directed to at least one third sub-gap 233.
  • the amount of light irradiated to the photoresist 01 is increased, and the exposure of the photoresist 01 is intensified, so that after the photoresist 01 is exposed and developed, the light corresponding to at least a part of the position of the at least one third sub-gap 233
  • the resist 01 is completely removed to form a photolithography pattern corresponding to the third connection pattern 221. Under the mask of the photolithography pattern, the active film is etched.
  • the corresponding The active film in at least a part of at least one third sub-gap 233 is more fully etched to avoid the presence of residual active film material in the third sub-gap 233 and reduce the risk of the two active patterns 21 in the active pair 20
  • the probability of short circuit occurring in the third sub-gap 233 is therefore more conducive to improving the yield of the display substrate 1000 .
  • the reflective layer 3 includes a plurality of reflective patterns 30 .
  • the orthographic projection of a reflective pattern 30 on the substrate 100 covers at least a portion of the gap 23 of an active pair 20 .
  • the orthographic projection of a reflective pattern 30 on the substrate 100 covers at least a part of the gap 23 of an active pair 20
  • the orthographic projection of a reflective pattern 30 on the substrate 100 covers an active pair 20 .
  • a part of the gap 23 of the pair 20; or, the orthographic projection of a reflective pattern 30 on the substrate 100 covers the entire gap 23 of an active pair 20, and other situations.
  • the orthographic projection of each reflective pattern 30 on the substrate 100 covers the first sub-gap 231, the second sub-gap 233, and the third sub-gap 233. At least one of the gap 232 and the third sub-gap 233.
  • the reflective layer 3 includes a plurality of reflective patterns 30 .
  • the orthographic projection of a reflective pattern 30 on the substrate 100 covers at least a part of the gap 23 of an active pair 20 .
  • the partially reflected light is directed to at least a part of the gap 23, so that the photoresist 01 corresponding to at least a part of the gap 23 is completely removed, forming a photolithography pattern corresponding to the active pattern 21.
  • the active film is etched to form the active pattern 21, which can make the etching of the active film corresponding to at least a part of the gap 23 more complete, and avoid the presence of active film in at least a part of the gap 23.
  • the residue of the thin film material reduces the probability that the two active patterns 21 in the active pair 20 are short-circuited at at least a portion of the gap 23 . Therefore, it is more conducive to improving the yield of the display substrate 1000 .
  • At least two reflective patterns 30 are connected to form an integrated structure.
  • one-piece structure means that two connected patterns are arranged on the same layer, and the two patterns are continuous and not separated. That is, in the present disclosure, at least two reflective patterns 30 are located on the same film layer, and at least two reflective patterns 30 are connected to each other.
  • At least two reflective patterns 30 are located on the same film layer, and at least two reflective patterns 30 are connected to each other, and the two are continuous and not separated. This can simplify the manufacturing process of the display substrate 1000.
  • the material of active layer 2 may include metal oxide.
  • the metal oxide can be IGZO (Indium Gallium Zinc Oxide) or other metal oxide semiconductor materials.
  • the transistor to which the first channel 210 belongs is a metal oxide thin film transistor.
  • the transistor to which the second channel 220 belongs is a metal oxide thin film transistor.
  • Metal oxide thin film transistors have lower leakage current.
  • the reflectivity of the reflective layer 3 is greater than or equal to 85%.
  • the reflectivity of the reflective layer 3 may be 85%, 88%, 91%, 94%, 97%, etc. Therefore, the reflectivity of the reflective layer 3 is relatively large, which can improve the reflection of light irradiating the reflective layer 3.
  • the orthographic projection of the reflective layer 3 on the substrate 100 covers at least a part of the gap 23 of one active pair 20,
  • the amount of light irradiating the photoresist 01 at at least a part of the corresponding position of the gap 23 is increased, and the exposure of the photoresist 01 at this position is intensified, so that after the photoresist 01 is exposed and developed, the two photoresist patterns 011 The photoresist between them is completely removed.
  • the light absorption coefficient of the reflective layer 3 ranges from 1.0 to 2.0.
  • the light absorption coefficient of the reflective layer 3 can be 1.2, 1.4, 1.6, 1.8, 2.0, etc. Therefore, part of the light that is not reflected by the reflective layer 3 or the light that is reflected by the first signal line 1 or the second signal line 12 and then strikes the reflective layer 3 again will be absorbed by the reflective layer 3 .
  • the material of the reflective layer 3 includes at least one of aluminum, copper, and molybdenum. Reflection of aluminum, copper, molybdenum The reflectivity of the reflective layer 3 to light is relatively high, which can improve the reflection of the light irradiating the reflective layer 3 .
  • the compensation transistor T5 in the pixel circuit includes the above-mentioned first channel 210 and the first gate pattern.
  • the first gate pattern is connected to the first signal line 1 to form an integrated structure.
  • the first gate pattern of the compensation transistor T5 and the first signal line 1 are located on the same film layer, and the first gate pattern and the first signal line 1 are coupled to each other, and they are continuous and not separated. This can simplify the manufacturing process of the display substrate 1000.
  • the first signal line 1 is the second scanning signal line GateN
  • the signal transmitted by the first signal line 1 is the second scanning signal.
  • the compensation transistor T5 may be turned on under the control of the second scan signal transmitted by the second scan signal line GateN.
  • the first connection pattern 211 constitutes the second pole of the compensation transistor T5; the second connection pattern 212 constitutes the first pole of the compensation transistor T5. At this time, the first connection pattern 211 is coupled to the third node, and the second connection pattern 212 is coupled to the second node N2.
  • the first reset transistor T1 includes the above-mentioned second channel 220 and the second gate pattern.
  • the second gate pattern and the second signal line 12 are connected to form an integrated structure.
  • the second gate pattern of the first reset transistor T1 and the second signal line 12 are located on the same film layer, and the second gate pattern and the second signal line 12 are coupled to each other, and they are continuous and not separated. This can simplify the manufacturing process of the display substrate 1000.
  • the second signal line 12 is the above-mentioned reset signal line ResetN, and the signal transmitted by the second signal line 12 is the reset signal.
  • the first reset transistor T1 may be turned on under the control of the reset signal transmitted by the reset signal line ResetN.
  • the third connection pattern 221 constitutes the first pole of the first reset transistor T1; the fourth connection pattern 222 constitutes the second pole of the first reset transistor T1. At this time, the third connection pattern 221 and the second connection pattern 212 are electrically connected, thereby realizing the electrical connection between the first reset transistor T1 and the compensation transistor T5.
  • the fourth connection pattern 222 is coupled to the first initialization signal line Vinit1.
  • the compensation transistor T5 and the first reset transistor T1 are both oxide transistors
  • the writing transistor T3, the driving transistor T4, the second reset transistor T2, the first lighting control transistor T6 and the second lighting control transistor T7 are all It is a low temperature polysilicon transistor.
  • setting the first reset transistor T1 as an oxide transistor can reduce the voltage of the first reset transistor T1 when it is in the off state after resetting the second node N2.
  • the leakage current of the second node N2 in the first reset transistor T1 makes the reset effect of the second node N2 better.
  • Setting the compensation transistor T5 as an oxide transistor can reduce the leakage current of the compensation transistor T5 during the data writing and compensation stages, avoid the leakage of the second node N2 through the compensation transistor and the first reset transistor, thereby ensuring the compensation effect of the driving transistor T4 , ensuring the stability of the voltage of the second node N2, thereby improving the performance of the display substrate 1000 Display quality. Since low-temperature polysilicon transistors have higher mobility, setting the driving transistor T4 and other transistors as low-temperature polysilicon transistors can speed up the charging speed of the storage capacitor, thereby further improving the display quality of the display substrate 1000 .
  • the orthographic projection of the reflective layer 3 on the substrate 100 covers at least a part of the gap 23 of the at least one active pair 21 .
  • the orthographic projection of the reflective layer 3 on the substrate 100 covers the entire gap 23 of at least one active pair 21 . Therefore, when the active pair 21 is formed, part of the light irradiated from the opening pattern of the mask to the reflective layer 3 is reflected, and part of the reflected light is directed to the photoresist corresponding to the position of the opening pattern of the mask, increasing This increases the amount of light irradiating the photoresist, intensifying the exposure of the photoresist 01 at this position, so that after the photoresist is exposed and developed, the photoresist at the position corresponding to the gap 23 is completely removed, forming an active
  • the photolithography pattern corresponding to pair 21 is etched under the mask of the photolithography pattern.
  • the active layer corresponding to at least one first sub-gap 231 can be formed.
  • the etching of the film is more complete, avoiding the presence of residual active film material in the gap 23, and reducing the probability of short circuit between the two active patterns 21 in the active pair 20. Therefore, it is more conducive to improving the performance of the display substrate 1000. Yield.

Abstract

本公开涉及显示技术领域，尤其涉及显示基板和显示装置，用于提高显示基板的良率。显示基板包括依次层叠设置的衬底、反光层、多条第一信号线、有源层。有源层包括多个有源对，有源对包括两个有源图案。有源图案在衬底上的正投影与第一信号线在衬底上的正投影部分交叠，有源对中未与第一信号线交叠的部分具有间隙；反光层在衬底上的正投影覆盖至少一个有源对的间隙的至少一部分。本公开提供的显示基板，通过设置反光层，增加照射到至少一部分间隙对应位置处的光刻胶的光量，使该位置处的光刻胶能够被完全去除，进而使得对应于至少一部分间隙处的有源薄膜的刻蚀更充分，降低有源对中的两个有源图案之间发生短路的概率，提高了显示基板的良率。

Description

显示基板和显示装置
本申请要求于2022年05月31日提交的、申请号为202210609879.4的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板和显示装置。
背景技术
目前，薄膜晶体管(Thin Film Transistor，TFT)是有机发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)的主要驱动元件。在TFT制作过程中，由于工艺的原因会导致薄膜晶体管之间发生短路，造成显示基板良率下降。
发明内容
本公开的目的在于提供一种显示基板和显示装置，用于提高显示基板的良率。
为达到上述目的，本公开实施例提供了如下技术方案：
本公开实施例提供了一种显示基板，所述显示基板包括：衬底；位于所述衬底一侧的反光层；位于所述反光层远离所述衬底的一侧、且沿第一方向延伸的多条第一信号线；以及，位于所述第一信号线远离所述反光层一侧的有源层，所述有源层包括多个有源对，所述有源对包括两个有源图案；属于同一有源对的相邻两个有源图案之间的间距小于，属于不同有源对的相邻两个有源图案之间的间距；所述有源图案沿第二方向延伸，所述第一方向与所述第二方向相交叉；所述有源图案在所述衬底上的正投影与所述第一信号线在所述衬底上的正投影部分交叠，所述有源对中未与所述第一信号线交叠的部分具有间隙；所述反光层在所述衬底上的正投影覆盖至少一个有源对的间隙的至少一部分。
在一些实施例中，所述有源图案包括：第一沟道和与所述第一沟道的第一端连接的第一连接图案，所述第一信号线在所述衬底上的正投影覆盖所述第一沟道在所述衬底上的正投影；所述第一连接图案在所述衬底上的正投影与所述第一信号线在所述衬底上的正投影无交叠；所述间隙包括位于所述有源对中相邻两个第一连接图案之间的第一子间隙；所述反光层在所述衬底上的正投影覆盖至少一个所述第一子间隙。
在一些实施例中，所述有源图案还包括：与所述第一沟道的第二端连接的第二连接图案，所述第二连接图案和所述第一连接图案相对设置，位于所述第一信号线的两侧；所述第二连接图案在所述衬底上的正投影与所述第一信号线在所述衬底上的正投影无交叠；所述间隙还包括位于所述有源对中相邻两个第二连接图案之间的第二子间隙；所述反光层在所述衬底上的正投影覆盖至少一个所述第二子间隙。
在一些实施例中，所述显示基板还包括：沿所述第一方向延伸的多条第二信号线，所述第二信号线与所述第一信号线同层设置；所述有源图案还包括：第二沟道、连接所述第 二沟道的第三端和所述第二连接图案的第三连接图案、及与所述第二沟道远离所述第三连接图案的第四端连接的第四连接图案；所述第二信号线在所述衬底上的正投影覆盖所述第二沟道在所述衬底上的正投影；所述第三连接图案和所述第四连接图案位于所述第二信号线的两侧，且所述第三连接图案和所述第四连接图案在所述衬底上的正投影与所述第二信号线在所述衬底上的正投影无交叠；在同一有源对中，相邻两个第一连接图案之间的间距、相邻两个第二连接图案之间的间距及相邻两个第三连接图案之间的间距，均小于相邻两个第四连接图案之间的间距；所述间隙还包括位于所述有源对中相邻两个第三连接图案之间的第三子间隙；所述反光层在所述衬底上的正投影覆盖至少一个所述第三子间隙的至少一部分。
在一些实施例中，所述反光层包括多个反光图案，一个所述反光图案在所述衬底上的正投影覆盖一个有源对的间隙的至少一部分。
在一些实施例中，至少两个所述反光图案相连接、呈一体结构。
在一些实施例中，所述有源层的材料包括金属氧化物。
在一些实施例中，所述反光层的反射率大于或等于85％。
在一些实施例中，所述反光层的吸光系数的范围为1.0～2.0。
在一些实施例中，所述反光层的材料包括铝、铜、钼中的至少一种。
在一些实施例中，所述显示基板还包括：多个像素电路；所述像素电路包括：补偿晶体管；所述补偿晶体管包括所述第一沟道和第一栅极图案；所述第一栅极图案与所述第一信号线相连接、呈一体结构。
在一些实施例中，所述显示基板还包括：多个像素电路；所述像素电路包括：第一复位晶体管，所述第一复位晶体管的第一极与所述补偿晶体管的第一极电连接；所述第一复位晶体管包括所述第二沟道和第二栅极图案；
所述第二栅极图案与所述第二信号线相连接、呈一体结构。
在一些实施例中，所述像素电路还包括：写入晶体管、驱动晶体管、第二复位晶体管、第一发光控制晶体管、第二发光控制晶体管以及存储电容器；所述写入晶体管的栅极与第一扫描信号线耦接，所述写入晶体管的第一极与数据信号线耦接，所述写入晶体管的第二极与第一节点耦接；所述驱动晶体管的栅极与第二节点耦接，所述驱动晶体管的第一极与所述第一节点耦接，所述驱动晶体管的第二极与第三节点耦接；所述补偿晶体管的第二极与所述第三节点耦接；所述第一发光控制晶体管的栅极与使能信号线耦接，所述第一发光控制晶体管的第一极与电压信号线耦接，所述第一发光控制晶体管的第二极与所述第一节点耦接；所述第二发光控制晶体管的栅极与所述使能信号线耦接，所述第二发光控制晶体管的第一极与所述第三节点耦接，所述第二发光控制晶体管的第二极与第四节点耦接；所述第一复位晶体管的第二极与第一初始化信号线耦接；所述第二复位晶体管的栅极与第一 复位信号线耦接，所述第二复位晶体管的第一极与第二初始化信号线耦接，所述第二复位晶体管的第二极与所述第四节点耦接；所述存储电容器的第一极板与所述电压信号线耦接，所述存储电容器的第二极板与所述第二节点耦接。
在一些实施例中，所述补偿晶体管和所述第一复位晶体管均为氧化物晶体管，所述写入晶体管、所述驱动晶体管、所述第二复位晶体管、所述第一发光控制晶体管和所述第二发光控制晶体管均为低温多晶硅晶体管。
本公开实施例还提供了一种显示装置，所述显示装置包括：如上述实施例中任一项所述的显示基板。
本公开提供的显示基板和显示装置具有如下有益效果：
本公开提供的显示基板，通过设置反光层，反光层在衬底上的正投影覆盖至少一个有源对的间隙的至少一部分，由此，在制备同一个有源对的有源图案时，从掩膜板的开口图案照射到反光层的部分光被反射，部分反射光射向至少一部分间隙对应位置处的光刻胶，增加了照射到至少一部分间隙对应位置处光刻胶的光量，加剧了对该位置处光刻胶的曝光，使得光刻胶被曝光、显影后，两个光刻图案之间的光刻胶被完全去除，在光刻图案的掩膜下，对有源薄膜进行刻蚀，形成有源图案时，可以使得有源薄膜的刻蚀更充分，避免一个有源对中的两个有源图案之间存在有源薄膜材料的残留，降低有源对中的两个有源图案之间发生短路的概率，因此，更有利于提高显示基板的良率。
本公开的一些实施例所提供的显示装置所能实现的有益效果，与上述一些实施例中提供的显示基板所能实现的有益效果相同，此处不再赘述。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据本公开一些实施例中一种显示装置的结构图；
图2为根据本公开一些实施例中一种显示基板的结构图；
图3A为根据本公开一些实施例中一种像素电路和发光器件的等效图；
图3B为根据本发明一些实施例中一种显示基板的结构图；
图4为根据本公开一些实施例中一种显示基板的结构图；
图5A为根据本公开一些实施例中有源图案的制作过程中，对光刻胶进行曝光的示意图；
图5B为根据本公开一些实施例中有源图案的制作过程中，光刻胶被曝光、显影后的 示意图；
图6A为根据本公开一些实施例中一种显示基板中一些膜层的俯视图；
图6B为根据本公开又一些实施例中有源图案的制作过程中，对光刻胶进行曝光的示意图；
图6C为根据本公开又一些实施例中有源图案的制作过程中，光刻胶被曝光、显影后的示意图；
图6D为根据本公开一些实施例中一种显示基板的局部图；
图6E为根据本公开一些实施例中一种显示基板中一些膜层的局部图；
图7A为根据本公开一些实施例中又一种显示基板的结构图；
图7B为根据本公开一些实施例中又一种显示基板的结构图；
图7C为根据本公开一些实施例中又一种显示基板的结构图；
图7D为根据本公开一些实施例中又一种显示基板的结构图；
图8A为根据本公开又一些实施例中有源图案的制作过程中，对光刻胶进行曝光的示意图；
图8B为根据本公开又一些实施例中有源图案的制作过程中，光刻胶被曝光、显影后的示意图；
图9为根据本公开又一些实施例中有源图案的制作过程中，对光刻胶进行曝光的示意图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
在描述一些实施例时，可能使用了“耦接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“被配置为”的使用意味着开放和包容性的语言，其不排除被配置为执行额外 任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
本文中术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
在本公开的实施例提供的电路结构(例如像素电路)中，电路结构所采用的晶体管可以为薄膜晶体管(Thin Film Transistor，简称TFT)、场效应晶体管(Metal Oxide Semiconductor，简称MOS)或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。
在本公开的实施例提供的电路结构中，所采用的各晶体管的第一极为源极和漏极中一者，各晶体管的第二极为源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性地，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性地，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
本公开的实施例提供的电路结构中，第一节点、第二节点等节点并非表示实际存在的部件，而是表示电路图中相关耦接的汇合点，也就是说，这些节点是由电路图中相关耦接的汇合点等效而成的节点。
在本公开中，P型晶体管可以在低电平信号的控制下导通，N型晶体管可以在高电平信号的控制下导通。
如图1所示，本公开的一些实施例提供了一种显示装置2000，该显示装置2000包括：显示基板1000。
在一些示例中，上述显示装置2000例如可以是OLED(Organic Light Emitting Diode，有机发光二极管)显示装置。
示例性的，显示装置2000还包括框架、显示驱动IC(Integrated Circuit，集成电路)以及其他电子配件等。
示例性的，上述显示装置2000可以是显示视频或者静止图像的任何显示装置。更明确地说，预期所述实施例的显示装置可实施应用在多种电子中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
在一些示例中，如图2所示，上述显示基板1000包括：衬底100、设置在衬底100一侧的多个像素电路200、设置在该多个像素电路200远离衬底100一侧的多个发光器件300。
示例性的，上述衬底100可以为柔性衬底，也可以为刚性衬底。
例如，在衬底100为柔性衬底的情况下，衬底100的材料可以为二甲基硅氧烷、PI(Polyimide，聚酰亚胺)、PET(Polyethylene terephthalate，聚对苯二甲酸乙二醇酯)等具有高弹性的材料。
又如，在衬底100为刚性衬底的情况下，衬底100的材料可以为玻璃等。
在一些示例中，上述多个像素电路200和多个发光器件300可以一一对应耦接。在另一些示例中，一个像素电路200可以与多个发光器件300耦接，或者，多个像素电路200可以与一个发光器件300耦接。
下面，本公开以一个像素电路200与一个发光器件300耦接为例，对显示基板1000的结构进行示意性说明。
示例性的，显示基板1000中，像素电路200可以生成驱动信号。各发光器件300可以在相应的像素电路200的驱动作用下发出光，多个发光器件300发出的光相互配合，从而使得显示基板1000实现显示功能。
示例性的，上述发光器件300可以为OLED。
在一些示例中，像素电路200的结构包括多种，可以根据实际需要选择设置。例如，像素电路200的结构可以包括“6T1C”、“7T1C”、“6T2C”或“7T2C”等结构。此处，“T”表示为晶体管，位于“T”前面的数字表示为晶体管的数量，“C”表示为存储电容器，位于“C”前面的数字表示为存储电容器的数量。
示例性的，本公开中以像素电路200的结构为“7T1C”结构为例进行说明。其中，图3A示意出了像素电路200和发光器件300的等效电路图。
可以理解的是，在像素电路200工作的过程中，需要不同的信号线为其提供相应的电信号。
示例性的，如图3B和图7D所示，显示基板1000包括：多条第一扫描信号线GateP、 多条第二扫描信号线GateN、多条数据信号线Data、多条第一复位信号线ResetP、多条第二复位信号线ResetN、多条电压信号线VDD、多条第一初始化信号线Vinit1、多条第二初始化信号线Vinit2、以及多条使能信号线EM。其中，第一扫描信号线GateP用于传输第一扫描信号，第二扫描信号线GateN用于传输第二扫描信号，数据信号线Data用于传输数据信号，第一复位信号线ResetP用于传输第一复位信号，第二复位信号线ResetN用于传输第二复位信号，电压信号线VDD用于传输电压信号，第一初始化信号线Vinit1用于传输第一初始化信号，第二初始化信号线Vinit2用于传输第二初始化信号，使能信号线EM用于传输使能信号。
例如，上述多条第一扫描信号线GateP、多条第二扫描信号线GateN、多条第一复位信号线ResetP、多条第二复位信号线ResetN、多条电压信号线VDD、多条第一初始化信号线Vinit1、多条第二初始化信号线Vinit2、多条使能信号线EM可以均沿第一方向X延伸，上述多条数据信号线Data可以沿第二方向Y延伸。
示例性的，显示基板1000还包括：多条公共电压信号线VSS，公共电压信号线VSS用于传输公共电压。
示例性的，如图3A所示，像素电路200包括：第一复位晶体管T1、第二复位晶体管T2、写入晶体管T3、驱动晶体管T4、补偿晶体管T5、第一发光控制晶体管T6、第二发光控制晶体管T7和存储电容器Cst。
示例性的，如图3A所示，第一复位晶体管T1的栅极与第二复位信号线ResetN耦接，第一复位晶体管T1的第一极与第二节点N2耦接，第一复位晶体管T1的第二极与第一初始化信号线Vinit1耦接。其中，第一复位晶体管T1被配置为，在第二复位信号线ResetN所传输的第二复位信号的控制下导通，将在第一初始化信号线Vinit1处接收的第一初始化信号传输至第二节点N2，对第二节点N2进行复位。
示例性的，如图3A所示，第二复位晶体管T2的栅极与第一复位信号线ResetP耦接，第二复位晶体管T2的第一极与第二初始化信号线Vinit2耦接，第二复位晶体管T2的第二极与第四节点N4耦接，也即与发光器件300耦接。其中，第二复位晶体管T2被配置为，在第一复位信号线ResetP所传输的第一复位信号的控制下导通，将在第二初始化信号线Vinit2处接收的第二初始化信号传输至第四节点N4，对第四节点N4进行复位。
示例性的，如图3A所示，写入晶体管T3的栅极与第一扫描信号线GateP耦接，写入晶体管T3的第一极与数据信号线Data耦接，写入晶体管T3的第二极与第一节点N1耦接，也即与驱动晶体管T4的第一极耦接。其中，写入晶体管T3被配置为，在第一扫描信号线GateP所传输的第一扫描信号的控制下导通，将在数据信号线Data处接收的数据信号传输至第一节点N1。
示例性的，如图3A所示，驱动晶体管T4的栅极与第二节点N2耦接，驱动晶体管T4 的第一极与第一节点N1耦接，驱动晶体管T4的第二极与第三节点N3耦接。其中，驱动晶体管T4被配置为，在第二节点N2的电压的控制下导通，将来自第一节点N1的电信号(例如为数据信号)传输至第三节点N3。
示例性的，如图3A所示，补偿晶体管T5的栅极与第二扫描信号线GateN耦接，补偿晶体管T5的第一极与第二节点N2耦接，也即与驱动晶体管T4的栅极耦接；补偿晶体管T5的第二极与第三节点N3耦接，也即与驱动晶体管T4的第二极耦接，其中，补偿晶体管T5被配置为，在第二扫描信号线GateN所传输的第二扫描信号的控制下导通，将来自第三节点N3的电信号(例如为数据信号)传输至第二节点N2。
示例性的，如图3A所示，第一发光控制晶体管T6的栅极与使能信号线EM耦接，第一发光控制晶体管T6的第一极与电压信号线VDD耦接，第一发光控制晶体管T6的第二极与第一节点N1耦接。其中，第一发光控制晶体管T6被配置为，在使能信号线EM所传输的使能信号的控制下导通，将在电压信号线VDD处接收的电压信号传输至第一节点N1。
示例性的，如图3A所示，第二发光控制晶体管T7的栅极与使能信号线EM耦接，第二发光控制晶体管T7的第一极与第三节点N3耦接，第二发光控制晶体管T7的第二极与第四节点N4耦接。其中，第二发光控制晶体管T7被配置为，在使能信号线EM所传输的使能信号的控制下导通，将来自第三节点N3的电信号(例如电压信号)传输至第四节点N4。
示例性的，如图3A所示，存储电容器Cst的第一极板与电压信号线VDD耦接；存储电容器Cst的第二极板与第二节点N2耦接。
示例性的，像素电路200的工作过程包括依次进行的复位阶段、数据写入及补偿阶段和发光阶段。
例如，在复位阶段，在第二复位信号线ResetN传输的第二复位信号的控制下，第一复位晶体管T1导通，将第一初始化信号传输至第二节点N2，对第二节点N2进行复位。由于第二节点N2与存储电容器Cst的第二极板、驱动晶体管T4的栅极及补偿晶体管T5的第一极耦接，因此，在对第二节点N2复位时，便可以同步对存储电容器Cst的第二极、驱动晶体管T4的栅极及补偿晶体管T5的第一极进行复位。其中，驱动晶体管T4可以在第一初始化信号的控制下导通。第二复位晶体管T2在第一复位信号线ResetP传输的第一复位信号的控制下导通，第二复位晶体管T2将第二初始化信号传输至第四节点N4，对第四节点N4进行复位。由于第四节点N4与发光器件300的阳极耦接，因此，在对第四节点N4进行复位时，便可以同步对发光器件300的阳极进行复位。
例如，在数据写入及补偿阶段，写入晶体管T3在第一扫描信号线GateP传输的第一扫描信号的控制下导通，补偿晶体管T5在第二扫描信号线GateN传输的第二扫描信号的控制下导通。写入晶体管T3将数据信号传输至第一节点N1，驱动晶体管T4将来自第一 节点N1的数据信号传输至第三节点N3。补偿晶体管T5将来自第三节点N3的数据信号传输至第二节点N2，对驱动晶体管T4进行充电，直至完成对驱动晶体管T4的阈值电压的补偿。
例如，在发光阶段，第一发光控制晶体管T6和第二发光控制晶体管T7在使能信号的控制下同时导通。第一发光控制晶体管T6将电压信号传输至第一节点N1。驱动晶体管T4将来自第一节点N1的电压信号传输至第三节点N3。第二发光控制晶体管T7将来自第三节点N3的电压信号传输至第四节点N4。
发光器件300在来自第四节点N4的电压信号和来自公共电压线VSS的公共电压的作用下发光。
在一些示例中，如图4所示，显示基板1000包括：位于衬底100一侧、且沿第一方向X延伸的多条第一信号线1，以及位于第一信号线1远离衬底100一侧的有源层2。
在一些示例中，第一信号线1和有源层2之间设置有第一绝缘层。第一绝缘层用于将第一信号线1和有源层2电绝缘。
例如，第一绝缘层的材料包括氮化硅、氮氧化硅和氧化硅的无机绝缘材料中的任一种，本公开不限于此。
在一些示例中，如图4所示，有源层2包括多个有源对20，有源对20包括两个有源图案21。
示例性的，属于同一有源对20的相邻两个有源图案21之间的间距小于，属于不同有源对20的相邻两个有源图案21之间的间距。
需要说明的是，上述“同一有源对20的相邻两个有源图案21之间的间距”，是指：同一有源对20所包括的相邻两个有源图案21之间的最小间距。
示例性的，有源图案21沿第二方向Y延伸。有源图案21在衬底100上的正投影与第一信号线1在衬底100上的正投影部分交叠，有源对20中未与第一信号线1交叠的部分具有间隙23。
示例性的，第二方向Y与第一方向X相交叉。此处，第一方向X和第二方向Y之间的夹角，可以根据实际需要选择设置。例如，第一方向X和第二方向Y之间的夹角为85°、88°或90°等。
例如，第一信号线1沿第一方向X延伸，有源图案21沿第二方向Y延伸，由于，第二方向Y与第一方向X相交叉，第一信号线1在衬底100上的正投影与有源图案21在衬底100上的正投影的交叉位置处存在交叠图案。其中，第一信号线1位于上述相同的交叠图案中的部分构成部分晶体管的栅极图案，有源图案21中，与上述相同的交叠图案相连接的部分，构成部分晶体管的第一极或第二极。
在一些示例中，在制备有源图案21时，可以通过如下步骤：1、有源薄膜沉积；2、在 有源薄膜上涂布光刻胶；3、对光刻胶进行曝光、显影形成光刻胶图案；4、以光刻胶图案作为掩膜，对有源层进行刻蚀，形成有源图案；5、去除光刻胶。
示例性的，通过曝光、显影等工艺形成光刻胶完全保留部分和光刻胶完全去除部分，并将光刻胶完全去除部分去除，即可得到光刻胶图案。
示例性的，如图5A和图5B所示，其中，图5A为对光刻胶01进行曝光的示意图；图5B为光刻胶01被曝光、显影后的示意图。
示例性的，掩膜板02包括多个开口图案，光线通过多个开口图案照射到光刻胶01上，对光刻胶01进行曝光、显影，该多个开口图案对应位置的光刻胶01被完全去除，其他位置的光刻胶被保留，从而得到光刻胶图案011。从而，在对有源薄膜2'进行刻蚀时，有源薄膜2'中与该多个开口图案对应位置的部分被刻蚀掉，形成有源图案21。
在一种实现方式中，像素密度较高，导致有源对20包括的两个有源图案21之间的间距较小。示例性的，如图6A所示。
示例性的，如图6B～图6E所示。其中，图6B为对光刻胶01进行曝光的示意图；图6C为光刻胶01被曝光、显影后的示意图；图6D和图6E为显示基板1000的局部图。
有源对20包括的两个有源图案21之间的间距较小，因此，在形成有源图案21的过程中，对光刻胶01进行曝光、显影后形成的两个光刻胶图案011之间的间距较小。
在此基础上，对光刻胶01进行曝光、显影时，掩膜板02上的开口图案021的宽度较小，较小的宽度导致通过该开口图案021处照射到光刻胶01上的光量较小，从而导致与该开口图案021对应位置的光刻胶01未被完全去除(如图6C所示)，从而在对有源薄膜2'进行刻蚀形成有源图案21时，两个有源图案21之间因为光刻胶01的残留导致有源薄膜2'在该位置处刻蚀不充分，导致有源薄膜在该位置处存在残留，从而导致有源对20中的两个有源图案21之间发生短路的问题。
示例性的，如图6D和图6E所示，位置A处，有源薄膜刻蚀不充分，存在有源薄膜残留。
基于此，本公开的一些实施例所提供的显示基板1000还包括位于衬底100和第一信号线1之间的反光层3，如图7A～图7C所示。
在一些示例中，第一信号线1和反光层3之间设置有第二绝缘层。第二绝缘层用于将第一信号线1和反光层3电绝缘。
例如，第二绝缘层的材料包括氮化硅、氮氧化硅和氧化硅的无机绝缘材料中的任一种，本公开不限于此。
在一些示例中，反光层3在衬底100上的正投影覆盖至少一个有源对21的间隙23的至少一部分。
需要说明的是，上述“反光层3在衬底100上的正投影至少覆盖至少一个有源对20的 间隙23的至少一部分”包括：反光层3在衬底100上的正投影覆盖至少一个有源对20的间隙23的一部分，或者完全覆盖至少一个有源对20的间隙23整体；以及，反光层3在衬底100上的正投影除覆盖至少一个有源对20的间隙23的至少一部分外，还覆盖一个有源对20的非间隙位置处等多种情况。
示例性的，如图8A和图8B所示，其中，图8A为对光刻胶01进行曝光的示意图；图8B为光刻胶01被曝光、显影后的示意图。从掩膜板02的开口图案021或其他开口图案入射的光，透过有源薄膜2'和第二绝缘层10照射到反光层3，照射到反光层3的部分光被反射，部分反射光射向与开口图案021位置相对应的光刻胶01，开口图案021位置对应的光刻胶01被进一步曝光，使得开口图案021位置对应的光刻胶01被完全去除。
采用上述设置，在制备有源图案21时，从掩膜板02的开口图案021或其他开口图案照射到反光层3的部分光被反射，部分反射光射向与掩膜板02的开口图案021位置相对应的光刻胶01，增加了照射到光刻胶01的光量，加剧了对该位置处光刻胶01的曝光，使得光刻胶01被曝光、显影后，两个光刻胶图案011之间的光刻胶被完全去除，在光刻胶图案011的掩膜下，对有源薄膜2'进行刻蚀，形成有源图案21时，可以使得有源薄膜的刻蚀更充分，避免有源对20中的两个有源图案21之间存在有源薄膜材料的残留，降低有源对20中的两个有源图案21之间发生短路的概率，有利于提高显示基板1000的良率。
在一些示例中，反光层3在衬底100上的正投影，与有源图案21在衬底100上的正投影与第一信号线1在衬底100上的正投影交叠的部分存在部分交叠。
示例性的，如图9所示，从掩膜板02的开口图案处入射的光，透过有源薄膜2'、第一绝缘层11以及第二绝缘层10照射到反光层3，照射到反光层3的部分光被反射，部分反射光射向第一信号线1在衬底100上的正投影与有源图案21在衬底100上的正投影的交叠图案处。
示例性的，第一信号线1的材料包括导电金属。该导电金属可以包括铝、铜、钼中的至少一种。铝、铜、钼的反射率都较高。由此，第一信号线1的反射率较高，射向第一信号线1在衬底100上的正投影与有源图案21在衬底100上的正投影的交叠图案处的光，不会透过第一信号线1对光刻胶01需要完全保留的部分造成影响，在刻蚀形成有源图案21时，有源图案21在衬底100上的正投影与第一信号线1在衬底100上的正投影的交叠图案处的宽度不会受到影响，进而保证了晶体管沟道尺寸的均一性。
在一些实施例中，如图7A～图7C所示，有源图案21包括：第一沟道210和与第一沟道210的第一端连接的第一连接图案211。
在一些示例中，如图7A～图7C所示，第一信号线1在衬底100上的正投影覆盖第一沟道210在衬底100上的正投影，也即，有源图案21在衬底100上的正投影在与第一信号线1在衬底100上的正投影存在相同的交叠图案，有源图案21中，位于该相同的交叠 图案中的部分为第一沟道210；第一连接图案211在衬底100上的正投影与第一信号线1在衬底100上的正投影无交叠。
示例性的，有源图案21中，第一沟道210构成部分晶体管的沟道，与第一沟道210相连接的第一连接图案211构成部分晶体管的第一极或第二极。
在一些示例中，如图7A～图7C所示，间隙23包括位于有源对20中相邻两个第一连接图案211之间的第一子间隙231。
示例性的，如图7A所示，反光层3在衬底100上的正投影覆盖至少一个第一子间隙231。
示例性的，反光层3在衬底100上的正投影可以覆盖一个或者多个第一子间隙231。例如，如图7A所示，反光层3在衬底100上的正投影可以覆盖多个第一子间隙231。
采用上述设置，在制备有源图案21时，从掩膜板02的开口图案021或其他开口图案照射到反光层3的部分光被反射，部分反射光射向至少一个第一子间隙231，增加了照射到与至少一个第一子间隙231对应位置处的光刻胶01的光量，加剧了对光刻胶01的曝光，使得光刻胶01被曝光、显影后，与至少一个第一子间隙231位置相对应的光刻胶01被完全去除，形成与第一连接图案211相对应的光刻图案，在该光刻图案的掩膜下，对有源薄膜进行刻蚀，形成第一连接图案211时，可以使得对应于至少一个第一子间隙231处的有源层薄膜的刻蚀更充分，避免在第一子间隙231处存在有源薄膜材料的残留，降低有源对20中的两个有源图案21在第一子间隙231处发生短路的概率，因此，更有利于提高显示基板1000的良率。
在一些实施例中，有源图案21还包括：与第一沟道210的第二端连接的第二连接图案212。
在一些示例中，如图7A～图7C所示，第二连接图案212和第一连接图案211相对设置，位于第一信号线1的两侧。第二连接图案212在衬底100上的正投影与第一信号线1在衬底100上的正投影无交叠。
在一些示例中，第一连接图案211构成部分晶体管的第一极，第二连接图案212构成该晶体管的第二极。在另一些示例中，第一连接图案211构成部分晶体管的第二极，第二连接图案212构成该晶体管的第一极，本公开的实施例对此不做限制。
在一些示例中，如图7A～图7C所示，间隙23还包括位于有源对20中相邻两个第二连接图案212之间的第二子间隙232。
示例性的，如图7B所示，反光层3在衬底100上的正投影覆盖至少一个第二子间隙232。
示例性的，反光层3在衬底100上的正投影可以覆盖一个或者多个第二子间隙232。例如，如图7B所示，反光层3在衬底100上的正投影可以覆盖多个第二子间隙232。
采用上述设置，在制备有源图案21时，从掩膜板02的开口图案021或其他开口图案照射到反光层3的部分光被反射，部分反射光射向至少一个第二子间隙232，增加了照射到光刻胶01的光量，加剧了对光刻胶01的曝光，使得光刻胶01被曝光、显影后，与至少一个第二子间隙232位置相对应的光刻胶01被完全去除，形成与第二连接图案212相对应的光刻图案，在该光刻图案的掩膜下，对有源薄膜进行刻蚀，形成第二连接图案212时，可以使得对应于至少一个第二子间隙232处的有源薄膜的刻蚀更充分，避免在第二子间隙232处存在有源薄膜材料的残留，从而降低有源对20中的两个有源图案21在第二子间隙232处发生短路的概率，因此，更有利于提高显示基板1000的良率。
在一些实施例中，如图7A～图7C所示，显示基板1000还包括沿第一方向X延伸的多条第二信号线12。
在一些示例中，如图7A～图7C所示，第二信号线12与第一信号线1同层设置。
需要说明的是，“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。这样可以同时制作第二信号线12与第一信号线1图案，有利于简化显示基板1000的制作工艺。
在一些示例中，如图7A～图7C所示，有源图案21还包括：第二沟道220、连接第二沟道220的第三端和第二连接图案212的第三连接图案221、及与第二沟道220远离第三连接图案221的第四端连接的第四连接图案222。
在一些示例中，如图7A～图7C所示，第二信号线12在衬底100上的正投影覆盖第二沟道220在衬底100上的正投影。
在一些示例中，如图7A～图7C所示，第三连接图案221和第四连接图案222位于第二信号线12的两侧，且第三连接图案221和第四连接图案222在衬底100上的正投影与第二信号线12在衬底100上的正投影无交叠。
示例性的，第二沟道220构成部分晶体管的沟道；第三连接图案221和第四连接图案222构成部分晶体管的第一极或第二极。例如，第三连接图案221构成部分晶体管的第一极，第四连接图案222构成部分晶体管的第二极；或者，第三连接图案221构成部分晶体管的第二极，第四连接图案222构成部分晶体管的第一极，本公开的实施例对此不做限制。
在一些示例中，如图7A～图7C所示，在同一有源对20中，相邻两个第一连接图案211之间的间距、相邻两个第二连接图案212之间的间距及相邻两个第三连接图案221之间的间距，均小于相邻两个第四连接图案222之间的间距。
示例性的，在同一有源对20中，相邻两个第一连接图案211之间的间距、相邻两个第二连接图案212之间的间距及相邻两个第三连接图案221之间的间距可以相等，也可以不 相等，本公开的实施例对此不做限制。
例如，如图7A～图7C所示，在同一有源对20中，相邻两个第一连接图案211之间的间距与相邻两个第二连接图案212之间的间距相等。
在一些示例中，如图7A～图7C所示，间隙23还包括位于有源对20中相邻两个第三连接图案221之间的第三子间隙233。
示例性的，如图7C所示，反光层3在衬底100上的正投影覆盖至少一个第三子间隙233的至少一部分。
需要说明的是，上述“反光层3在衬底100上的正投影覆盖至少一个第三子间隙233的至少一部分”包括：反光层3在衬底100上的正投影覆盖至少一个第三子间隙233的一部分，或者反光层3在衬底100上的正投影覆盖至少一个第三子间隙233整体等多种情况。
在一些示例中，如图7C所示，第三连接图案221包括第一子连接图案2211和第二子连接图案2212。其中，第一子连接图案2211与第二子连接图案2212相比，更接近第二连接图案212。
在同一有源对20中，相邻两个第一子连接图案2211之间的间距小于，相邻两个第二子连接图案2212之间的间距。此时，反光层3在衬底100上的正投影可以覆盖相邻两个第一子连接图案2211之间的间隙，或者反光层3在衬底100上的正投影覆盖相邻两个第一子连接图案2211之间的间隙及相邻两个第二子连接图案2212之间的间隙。
采用上述设置，在制备有源图案21时，从掩膜板02的开口图案021或其他开口图案照射到反光层3的部分光被反射，部分反射光射向至少一个第三子间隙233的至少一部分，增加了照射到光刻胶01的光量，加剧了对光刻胶01的曝光，使得光刻胶01被曝光、显影后，与至少一个第三子间隙233的至少一部分位置相对应的光刻胶01被完全去除，形成与第三连接图案221相对应的光刻图案，在该光刻图案的掩膜下，对有源薄膜进行刻蚀，形成第三连接图案221时，可以使得对应于至少一个第三子间隙233的至少一部分处的有源薄膜的刻蚀更充分，避免在第三子间隙233存在有源薄膜材料的残留，降低有源对20中的两个有源图案21在第三子间隙233发生短路的概率，因此，更有利于提高显示基板1000的良率。
在一些实施例中，如图7A～图7C所示，反光层3包括多个反光图案30。
在一些示例中，一个反光图案30在衬底100上的正投影覆盖一个有源对20的间隙23的至少一部分。
需要说明的是，上述“一个反光图案30在衬底100上的正投影覆盖一个有源对20的间隙23的至少一部分”包括：一个反光图案30在衬底100上的正投影覆盖一个有源对20的间隙23的一部分；或者，一个反光图案30在衬底100上的正投影覆盖一个有源对20的间隙23的整体等多种情况。
示例性的，在间隙23包括第一子间隙231、第二子间隙232、第三子间隙233时，每个反光图案30在衬底100上的正投影覆盖第一子间隙231、第二子间隙232、第三子间隙233中的至少一者。
本实施例中，反光层3包括多个反光图案30，一个反光图案30在衬底100上的正投影覆盖一个有源对20的间隙23的至少一部分，通过使照射到反光层3的部分光被反射，部分反射光射向间隙23的至少一部分，使得与间隙23的至少一部分位置相对应的光刻胶01被完全去除，形成与有源图案21相对应的光刻图案，在该光刻图案的掩膜下，对有源薄膜进行刻蚀，形成有源图案21时，可以使得对应于间隙23的至少一部分处的有源薄膜的刻蚀更充分，避免至少一部分间隙23处存在有源薄膜材料的残留，降低有源对20中的两个有源图案21在该至少一部分间隙23处发生短路的概率，因此，更有利于提高显示基板1000的良率。
在一些实施例中，至少两个反光图案30相连接、呈一体结构。
示例性的，“一体结构”指的是，相连接的两个图案同层设置，且该两个图案是连续的，未分隔开。也即，本公开中，至少两个反光图案30位于同一膜层，且至少两个反光图案30相互连接。
示例性的，本公开中，至少两个反光图案30位于同一膜层，且至少两个反光图案30相互连接，两者连续、未分隔开。这样可以简化显示基板1000的制作工艺。
在一些实施例中，有源层2的材料可以包括金属氧化物。
示例性的，该金属氧化物可以为IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)或其他金属氧化物半导体材料。
示例性的，本公开中，第一沟道210所属的晶体管为金属氧化物薄膜晶体管。第二沟道220所属的晶体管为金属氧化物薄膜晶体管。金属氧化物薄膜晶体管具有更低的泄漏电流。
在一些实施例中，反光层3的反射率大于或等于85％。例如，反光层3的反射率可以为85％、88％、91％、94％、97％等。因此，反光层3反射率较大，可以提高对照射到反光层3的光线的反射，在反光层3在衬底100上的正投影除覆盖一个有源对20的间隙23的至少一部分时，增加了照射到间隙23的至少一部分对应位置的光刻胶01的光量，加剧了对该位置处光刻胶01的曝光，使得光刻胶01被曝光、显影后，两个光刻胶图案011之间的光刻胶被完全去除。
在一些实施例中，反光层3的吸光系数的范围为1.0～2.0。例如，反光层3的吸光系数可以为1.2、1.4、1.6、1.8、2.0等。由此，部分未被反光层3反射的光线或者经过第一信号线1或者第二信号线12反射后再次射向反光层3的光线，会被反光层3吸收。
在一些实施例中，反光层3的材料包括铝、铜、钼中的至少一种。铝、铜、钼的反射 率都较高，反光层3对光线的反射率较高，可以提高对照射到反光层3的光线的反射。
在一些实施例中，像素电路中的补偿晶体管T5包括上述第一沟道210和第一栅极图案。
在一些示例中，第一栅极图案与第一信号线1相连接、呈一体结构。
例如，补偿晶体管T5的第一栅极图案与第一信号线1位于同一膜层，且第一栅极图案与第一信号线1相互耦接，两者连续、未分隔开。这样可以简化显示基板1000的制作工艺。此时，第一信号线1即为上述第二扫描信号线GateN，第一信号线1所传输的信号为第二扫描信号。补偿晶体管T5可以在第二扫描信号线GateN所传输的第二扫描信号的控制下导通。
在一些示例中，第一连接图案211构成补偿晶体管T5的第二极；第二连接图案212构成补偿晶体管T5的第一极。此时，第一连接图案211与第三节点耦接，第二连接图案212与第二节点N2耦接。
在一些实施例中，如图7A～图7D所示，第一复位晶体管T1包括上述第二沟道220和第二栅极图案。
在一些示例中，第二栅极图案和第二信号线12相连接、呈一体结构。
例如，第一复位晶体管T1的第二栅极图案与第二信号线12位于同一膜层，且第二栅极图案和第二信号线12相互耦接，两者连续、未分隔开。这样可以简化显示基板1000的制作工艺。此时，第二信号线12即为上述复位信号线ResetN，第二信号线12所传输的信号为复位信号。第一复位晶体管T1可以在复位信号线ResetN所传输的复位信号的控制下导通。
在一些示例中，第三连接图案221构成第一复位晶体管T1的第一极；第四连接图案222构成第一复位晶体管T1的第二极。此时，第三连接图案221和第二连接图案212电连接，从而实现了第一复位晶体管T1和补偿晶体管T5的电连接。第四连接图案222与第一初始化信号线Vinit1耦接。
在一些实施例中，补偿晶体管T5和第一复位晶体管T1均为氧化物晶体管，写入晶体管T3、驱动晶体管T4、第二复位晶体管T2、第一发光控制晶体管T6和第二发光控制晶体管T7均为低温多晶硅晶体管。
示例性的，由于氧化物晶体管具有较低的泄露电流，设置第一复位晶体管T1为氧化物晶体管，可以在第一复位晶体管T1对第二节点N2复位后、处于截止状态的情况下，降低第二节点N2在第一复位晶体管T1的泄露电流，从而使得第二节点N2的复位效果较好。设置补偿晶体管T5为氧化物晶体管，可以在数据写入及补偿阶段，减少补偿晶体管T5的漏电流，避免第二节点N2通过补偿晶体管和第一复位晶体管漏电，进而确保对驱动晶体管T4的补偿效果，确保第二节点N2电压的稳定性，进而可以提高显示基板1000的 显示质量。而低温多晶硅晶体管的迁移率较高，设置驱动晶体管T4等晶体管为低温多晶硅晶体管，可以加快对存储电容器的充电速度，进而可以进一步提高显示基板1000的显示质量。
在此基础上，反光层3在衬底100上的正投影覆盖至少一个有源对21的间隙23的至少一部分。
示例性的，如图7D所示，反光层3在衬底100上的正投影覆盖至少一个有源对21的间隙23整体。由此，在形成有源对21时，从掩膜板的开口图案照射到反光层3的部分光被反射，部分反射光射向与掩膜板的开口图案位置相对应的光刻胶，增加了照射到光刻胶的光量，加剧了对该位置处光刻胶01的曝光，使得光刻胶被曝光、显影后，对应于间隙23位置处的光刻胶被完全去除，形成与有源对21相对应的光刻图案，在该光刻图案的掩膜下，对有源薄膜进行刻蚀，形成有源对21时，可以使得对应于至少一个第一子间隙231处的有源层薄膜的刻蚀更充分，避免在间隙23处存在有源薄膜材料的残留，降低有源对20中的两个有源图案21之间发生短路的概率，因此，更有利于提高显示基板1000的良率。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (15)

  1. 一种显示基板，其特征在于，所述显示基板包括：
    衬底；
    位于所述衬底一侧的反光层；
    位于所述反光层远离所述衬底的一侧、且沿第一方向延伸的多条第一信号线；以及，
    位于所述第一信号线远离所述反光层一侧的有源层，所述有源层包括多个有源对，所述有源对包括两个有源图案；属于同一有源对的相邻两个有源图案之间的间距小于，属于不同有源对的相邻两个有源图案之间的间距；
    所述有源图案沿第二方向延伸，所述第一方向与所述第二方向相交叉；
    所述有源图案在所述衬底上的正投影与所述第一信号线在所述衬底上的正投影部分交叠，所述有源对中未与所述第一信号线交叠的部分具有间隙；
    所述反光层在所述衬底上的正投影覆盖至少一个有源对的间隙的至少一部分。
  2. 根据权利要求1所述的显示基板，其特征在于，
    所述有源图案包括：第一沟道和与所述第一沟道的第一端连接的第一连接图案，所述第一信号线在所述衬底上的正投影覆盖所述第一沟道在所述衬底上的正投影；所述第一连接图案在所述衬底上的正投影与所述第一信号线在所述衬底上的正投影无交叠；
    所述间隙包括位于所述有源对中相邻两个第一连接图案之间的第一子间隙；
    所述反光层在所述衬底上的正投影覆盖至少一个所述第一子间隙。
  3. 根据权利要求2所述的显示基板，其特征在于，
    所述有源图案还包括：与所述第一沟道的第二端连接的第二连接图案，所述第二连接图案和所述第一连接图案相对设置，位于所述第一信号线的两侧；
    所述第二连接图案在所述衬底上的正投影与所述第一信号线在所述衬底上的正投影无交叠；
    所述间隙还包括位于所述有源对中相邻两个第二连接图案之间的第二子间隙；
    所述反光层在所述衬底上的正投影覆盖至少一个所述第二子间隙。
  4. 根据权利要求3所述的显示基板，其特征在于，所述显示基板还包括：沿所述第一方向延伸的多条第二信号线，所述第二信号线与所述第一信号线同层设置；
    所述有源图案还包括：第二沟道、连接所述第二沟道的第三端和所述第二连接图案的第三连接图案、及与所述第二沟道远离所述第三连接图案的第四端连接的第四连接图案；
    所述第二信号线在所述衬底上的正投影覆盖所述第二沟道在所述衬底上的正投影；
    所述第三连接图案和所述第四连接图案位于所述第二信号线的两侧，且所述第三连接图案和所述第四连接图案在所述衬底上的正投影与所述第二信号线在所述衬底上的正投影无交叠；
    在同一有源对中，相邻两个第一连接图案之间的间距、相邻两个第二连接图案之间的 间距及相邻两个第三连接图案之间的间距，均小于相邻两个第四连接图案之间的间距；
    所述间隙还包括位于所述有源对中相邻两个第三连接图案之间的第三子间隙；
    所述反光层在所述衬底上的正投影覆盖至少一个所述第三子间隙的至少一部分。
  5. 根据权利要求4所述的显示基板，其特征在于，
    所述反光层包括多个反光图案，一个所述反光图案在所述衬底上的正投影覆盖一个有源对的间隙的至少一部分。
  6. 根据权利要求5所述的显示基板，其特征在于，
    至少两个所述反光图案相连接、呈一体结构。
  7. 根据权利要求1～6中任一项所述的显示基板，其特征在于，
    所述有源层的材料包括金属氧化物。
  8. 根据权利要求7所述的显示基板，其特征在于，
    所述反光层的反射率大于或等于85％。
  9. 根据权利要求8所述的显示基板，其特征在于，
    所述反光层的吸光系数的范围为1.0～2.0。
  10. 根据权利要求9所述的显示基板，其特征在于，
    所述反光层的材料包括铝、铜、钼中的至少一种。
  11. 根据权利要求4～6中任一项所述的显示基板，其特征在于，所述显示基板还包括：多个像素电路；
    所述像素电路包括：补偿晶体管；所述补偿晶体管包括所述第一沟道和第一栅极图案；
    所述第一栅极图案与所述第一信号线相连接、呈一体结构。
  12. 根据权利要求11所述的显示基板，其特征在于，所述显示基板还包括：多个像素电路；
    所述像素电路包括：第一复位晶体管，所述第一复位晶体管的第一极与所述补偿晶体管的第一极电连接；
    所述第一复位晶体管包括所述第二沟道和第二栅极图案；
    所述第二栅极图案与所述第二信号线相连接、呈一体结构。
  13. 根据权利要求12所述的显示基板，其特征在于，所述显示基板还包括：
    所述像素电路还包括：写入晶体管、驱动晶体管、第二复位晶体管、第一发光控制晶体管、第二发光控制晶体管以及存储电容器；
    所述写入晶体管的栅极与第一扫描信号线耦接，所述写入晶体管的第一极与数据信号线耦接，所述写入晶体管的第二极与第一节点耦接；
    所述驱动晶体管的栅极与第二节点耦接，所述驱动晶体管的第一极与所述第一节点耦接，所述驱动晶体管的第二极与第三节点耦接；
    所述补偿晶体管的第二极与所述第三节点耦接；
    所述第一发光控制晶体管的栅极与使能信号线耦接，所述第一发光控制晶体管的第一极与电压信号线耦接，所述第一发光控制晶体管的第二极与所述第一节点耦接；
    所述第二发光控制晶体管的栅极与所述使能信号线耦接，所述第二发光控制晶体管的第一极与所述第三节点耦接，所述第二发光控制晶体管的第二极与第四节点耦接；
    所述第一复位晶体管的第二极与第一初始化信号线耦接；
    所述第二复位晶体管的栅极与第一复位信号线耦接，所述第二复位晶体管的第一极与第二初始化信号线耦接，所述第二复位晶体管的第二极与所述第四节点耦接；
    所述存储电容器的第一极板与所述电压信号线耦接，所述存储电容器的第二极板与所述第二节点耦接。
  14. 根据权利要求13所述的显示基板，其特征在于，所述补偿晶体管和所述第一复位晶体管均为氧化物晶体管，所述写入晶体管、所述驱动晶体管、所述第二复位晶体管、所述第一发光控制晶体管和所述第二发光控制晶体管均为低温多晶硅晶体管。
  15. 一种显示装置，其特征在于，所述显示装置包括：如权利要求1～14中任一项所述的显示基板。
PCT/CN2023/095317 2022-05-31 2023-05-19 显示基板和显示装置 WO2023231810A1 (zh)

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