WO2022078093A1 - 显示面板、显示装置 - Google Patents

显示面板、显示装置 Download PDF

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Publication number
WO2022078093A1
WO2022078093A1 PCT/CN2021/115903 CN2021115903W WO2022078093A1 WO 2022078093 A1 WO2022078093 A1 WO 2022078093A1 CN 2021115903 W CN2021115903 W CN 2021115903W WO 2022078093 A1 WO2022078093 A1 WO 2022078093A1
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Prior art keywords
layer
display panel
signal line
base substrate
metal layer
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PCT/CN2021/115903
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English (en)
French (fr)
Inventor
朱健超
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/788,794 priority Critical patent/US20230030321A1/en
Publication of WO2022078093A1 publication Critical patent/WO2022078093A1/zh
Priority to US18/333,280 priority patent/US20230329057A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80515—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80521—Cathodes characterised by their shape

Definitions

  • the present disclosure generally relates to the field of display technology, and in particular, to a display panel and a display device including the display panel.
  • OLED Organic Light Emitting Diode
  • the organic light emitting diode When an organic light emitting diode is used in a display panel, the organic light emitting diode generally includes a first electrode layer, a second electrode layer, and a light emitting layer sandwiched between the two electrodes, and the second electrode layer of each light emitting unit is fabricated on the entire surface.
  • the purpose of the present application is to provide a display panel and a display device.
  • a display panel which has a display area and a peripheral area, and includes: a base substrate, on which an active layer, a first insulating layer, a first gate layer, and a second gate are stacked and disposed layer, a first metal layer and a second metal layer;
  • the first metal layer includes a second power signal line
  • the second metal layer includes an initialization voltage signal line, a first power supply signal line, and a data signal line;
  • the second power signal line and the second electrode layer are electrically connected in the peripheral region;
  • the organic light emitting diode device includes a first electrode layer, a light emitting layer and a second electrode layer sequentially arranged on the substrate;
  • the second power signal line includes a plurality of first-direction wirings and a plurality of second-direction wirings, and the first-direction wirings and the second-direction wirings are on the positive side of the base substrate. Projection intersection.
  • the wirings in the first direction and the wirings in the second direction are arranged on the same layer.
  • the traces in the first direction overlap with the orthographic projection of the second metal layer on the base substrate.
  • the first direction wiring and the orthographic projection of the initialization voltage signal line on the base substrate overlap.
  • the first direction wiring and the orthographic projection of the first power signal line on the base substrate overlap.
  • the first direction wiring and the orthographic projection of the data signal line on the base substrate overlap.
  • the second-direction traces overlap with the orthographic projection of the second gate layer on the base substrate.
  • N are positive integers.
  • the wiring in the first direction and the wiring in the second direction are arranged in different layers. .
  • a display device including the display panel provided by each embodiment of the present application.
  • FIG. 1 shows an exemplary structural diagram of a display panel according to an embodiment of the present application
  • FIG. 2 shows an exemplary top view of the first metal layer of FIG. 1;
  • FIG. 3 shows an exemplary top view of the first electrode of FIG. 1;
  • FIG. 4 shows an exemplary top view of the pixel opening of FIG. 1
  • FIG. 5 shows an exemplary top view of the stacked arrangement of the first metal layer, the first electrode and the pixel opening of FIG. 1;
  • FIG. 6 shows an exemplary schematic diagram of a pixel driving circuit of the display panel of FIG. 1;
  • FIG. 7 shows an exemplary schematic diagram of the TFT and capacitor layout of a sub-pixel
  • Figures 8 to 11 show plan views of the various layers in the layout of Figure 7;
  • FIG. 12 shows an exemplary flowchart of a method for manufacturing a display panel according to an embodiment of the present application
  • FIG. 13 shows an exemplary flowchart of a method for manufacturing a display panel according to another embodiment of the present application.
  • FIGS. 14 to 18 show specific exemplary schematic diagrams according to the manufacturing method of the display panel in FIGS. 12 and 13 ;
  • FIG. 19 shows an exemplary schematic diagram of the second power signal line and the display panel as a whole.
  • the current organic light emitting diode usually includes a first electrode layer, a second electrode layer and a light emitting layer sandwiched between the two electrodes, and the light emitting layer at least includes a hole transport layer, a light-emitting layer and an electron transport layer.
  • the semiconductor microcavity formed by the first electrode layer and the second electrode layer is an optical structure with a narrowed spectrum.
  • the photons generated in the light-emitting layer are confined in the cavity formed by the two mirror surfaces. Therefore, the light-emitting characteristics of the light-emitting diode are not only Depending on the inherent characteristics of the organic light-emitting material, the morphology of the first electrode layer, the second electrode layer, etc.
  • the first electrode layer or the second electrode layer has a certain correlation. Improper design of the first electrode layer or the second electrode layer will cause color shift or color separation. For example, in a sub-pixel unit, if the light intensity emitted by each part of the light-emitting layer is different, or the light intensity seen at the same viewing angle is different, the image seen by the viewer will have a color shift problem. In addition, after the external light is incident on the display panel, it is reflected by some metal layers (for example, the first electrode layer and the second electrode layer) to form reflected light. The image the viewer sees will have color separation issues. Therefore, a reasonable display panel structure is adopted, so that the light intensity emitted by the display panel at the same viewing angle is the same, and the light intensity reflected by the display panel at the same viewing angle is the same.
  • the present application provides the following display panel.
  • the display panel includes a plurality of sub-pixel units, and each sub-pixel unit includes a first metal layer 110, a first flat layer 111, a first electrode layer 112, a pixel definition layer 113, a light-emitting layer 114 and a second electrode layer, which are stacked in sequence. 115. in:
  • the first metal layer 110 includes at least one longitudinal trace 110 - 1 evenly distributed side by side; the first metal layer 110 , the first electrode layer 112 , the pixel definition layer 113 and the second electrode layer 115 adopt axisymmetric structures respectively.
  • the longitudinal wiring at the center is used as the symmetry axis 11 of the symmetrical structure; when the number of longitudinal wirings 110-1 is an even number, the two longitudinal wirings at the most edge are used as the axis of symmetry 11 of the symmetrical structure.
  • the center line between the lines serves as the symmetry axis 12 of the symmetrical structure.
  • a first flat layer 111 , a first electrode layer 112 , a pixel definition layer 113 , a light-emitting layer 114 , and a second electrode layer 115 are sequentially stacked on the first metal layer 110 , wherein the first electrode layer 112
  • the protrusion 112-1 is formed with the shape of the first metal layer 110, so that the thickness of the light-emitting layer 114 formed between the first electrode layer 112 and the second electrode layer 115 is uneven, thereby causing the light intensity emitted by the light-emitting layer 114
  • the light intensity of the external light reflected by the first electrode layer 112 will also be uneven.
  • the first metal layer 110 , the first electrode layer 112 , the pixel definition layer 113 and the second electrode layer 115 are respectively set as an axis-symmetric structure, so that the light intensity of the light emitted by the light-emitting layers on both sides of the symmetry axis is equal, such as the same as the symmetry axis.
  • the light intensity of light R1 and light R2 emitted at the same distance from 11 is equal, the light intensity of light B1 and light B2 emitted at the same distance from the axis of symmetry 12 is equal, and the reflected light R3 reflected from the position with the same distance from the axis of symmetry 11 is equal to
  • the light intensity of the reflected light ray R4 is the same, and the light intensity of the reflected light ray B3 and the reflected light ray B4 reflected from the position with the same distance from the symmetry axis 12 are equal.
  • Conformal here refers to two stacked layers, one of which changes with the structure of the other.
  • the first metal layer can transmit signals as required, for example, can transmit power signals in the pixel driving circuit, which is not limited here.
  • FIGS. 1 to 5 show an exemplary top view of the first metal layer of FIG. 1 ;
  • FIG. 3 shows an exemplary top view of the first electrode of FIG. 1 ;
  • FIG. 4 shows an exemplary top view of FIG. 1 An exemplary top view of the pixel opening of FIG. 5;
  • FIG. 5 shows an exemplary top view of the stacked arrangement of the first metal layer, the first electrode and the pixel opening of FIG. 1;
  • the first metal layer 110 of the sub-pixel unit 21 is provided with a vertical wiring 110-1; the first electrode layer 112 of the sub-pixel unit 21 includes a protrusion 112-1, the protrusion 112-1 An axisymmetric structure with the longitudinal wiring 110-1 as the axis of symmetry is adopted.
  • the symmetry axis 11 here can be understood as the center line of the longitudinal wiring 110-1.
  • the axis of symmetry can be considered as the longitudinal line 110-1.
  • the present application adopts the latter term for the convenience of explanation.
  • the reflected light formed by the external light through the first electrode layer 112 is symmetrical with the longitudinal line 110-1 as the axis of symmetry.
  • the reflected light R3 and the reflected light R4 at the same distance from the vertical line 110-1 have the same exit angle and the same light intensity. The occurrence of color separation is prevented.
  • the pixel definition layer 113 of the sub-pixel unit 21 includes a pixel opening 113-1, and the pixel opening 113-1 adopts an axisymmetric structure with the longitudinal line 110-1 as the axis of symmetry;
  • the second electrode layer 115 of the sub-pixel unit 21 includes a recess 115-1, and the recess 115-1 adopts an axisymmetric structure with the longitudinal line 110-1 as the axis of symmetry.
  • This embodiment shows the case where one sub-pixel unit includes one vertical line.
  • the protrusion 112-1, the recess 115-1, and the pixel opening 115-1 are respectively symmetrical with the vertical line 110-1 as the axis of symmetry.
  • the light emitting layer 114 between the first electrode layer 112 and the second electrode layer 115 is also symmetrical about the longitudinal line 110 - 1 as the axis of symmetry.
  • the sub-pixel unit 21 forms a light-emitting layer symmetrical with the longitudinal line 110-1 as the axis of symmetry. Therefore, the light intensity of the light emitted by the light-emitting layer is also symmetrical with the longitudinal line 110-1 as the axis of symmetry. Strongly equal. Prevents the appearance of color casts.
  • the orthographic projection of the pixel opening 115 - 1 on the first metal layer of the sub-pixel unit 21 covers the vertical wiring 110 - 1 .
  • FIG. 2 , FIG. 3 and FIG. 4 respectively show the top views of the first metal layer 110 , the first electrode layer 112 and the pixel opening 113 - 1
  • FIG. 5 shows the stacked structure diagram of the first three.
  • the first metal layer is provided with longitudinal traces 110-1 that are evenly arranged side by side.
  • the first electrode layer is provided with first electrode blocks 112-1.
  • the pixel The definition layer is provided with a pixel opening 113-1.
  • FIG. 1 and FIG. 5 the orthographic projection of the pixel opening 115 - 1 on the first metal layer of the sub-pixel unit 21 covers the vertical wiring 110 - 1 .
  • FIG. 2 , FIG. 3 and FIG. 4 respectively show the top views of the first metal layer 110 , the first electrode layer 112 and the pixel opening 113 - 1
  • FIG. 5 shows the stacked structure diagram of the
  • the pixel opening 113-1 and the first electrode block 112-2 of the sub-pixel unit 21 respectively adopt a symmetric structure with the longitudinal line 110-1 as the axis of symmetry, And the orthographic projection of the pixel opening 115-1 of the sub-pixel unit 21 on the first metal layer covers the vertical wiring 110-1 shown.
  • the first metal layer 110 of the sub-pixel unit 22 is provided with two vertical wirings; the first electrode layer 112 of the sub-pixel unit 22 includes two protrusions 112 - 1 , the protrusions 112 - 1 are respectively located directly above the longitudinal wires 110 .
  • This embodiment shows that, in the case where one sub-pixel unit includes two longitudinal wires, at this time, the reflected light formed by the external light through the first electrode layer is also symmetrical with the symmetry axis 12 as the symmetry axis.
  • the reflected light R3 and the reflected light R4 reflected at the same distance from the symmetry axis 12 have the same exit angle and the same light intensity. The occurrence of color separation is prevented.
  • the pixel definition layer 113 of the sub-pixel unit 22 includes a pixel opening 113-1, and the pixel opening 113-1 adopts an axisymmetric structure with the center line of the two longitudinal lines as the axis of symmetry;
  • the second electrode layer 115 of the sub-pixel unit 22 includes a recess 115-1, and the recess 115-1 adopts an axisymmetric structure in which the center line of the two longitudinal wires 110-1 is the axis of symmetry.
  • the protrusions 112-1, the depressions 115-1, and the pixel openings 113-1 are respectively symmetrical about the symmetry axis 12, so the light-emitting layer 114 between the first electrode layer 112 and the second electrode layer 115 is also symmetrical
  • the axis 12 is symmetrical about the axis of symmetry.
  • the light-emitting layer formed in the sub-pixel unit 22 is symmetrical with the symmetry axis 12 as the symmetry axis. Therefore, the light intensity of the light emitted by the light emitting layer 114 is also symmetrical with the symmetry axis 12 as the symmetry axis. Prevents the appearance of color casts.
  • the orthographic projection of the pixel opening 113 - 1 on the first metal layer of the sub-pixel unit 22 covers the two longitudinal traces 110 - 1 . 2, 3 and 4 respectively show the top views of the first metal layer 110, the first electrode layer 112 and the pixel opening 113-1, and FIG. 5 shows the stacked structure diagram of the first three.
  • the first metal layer is provided with longitudinal traces 110-1 that are evenly arranged side by side.
  • the first electrode layer is provided with first electrode blocks 112-1.
  • the pixel The definition layer is provided with a pixel opening 113-1.
  • FIG. 1 and FIG. 5 the orthographic projection of the pixel opening 113 - 1 on the first metal layer of the sub-pixel unit 22 covers the two longitudinal traces 110 - 1 . 2, 3 and 4 respectively show the top views of the first metal layer 110, the first electrode layer 112 and the pixel opening 113-1
  • FIG. 5 shows the stacked structure diagram of the first three.
  • the first metal layer is provided with longitudinal traces 110-1 that are evenly arranged
  • the pixel opening 113-1 of the sub-pixel unit 22 and the first electrode block 112-2 are respectively symmetrical about the axis of symmetry 12 between the longitudinal lines 110-1.
  • the axis is symmetrical, and the orthographic projection of the pixel opening 115-1 of the sub-pixel unit 22 on the first metal layer covers the two longitudinal traces 110-1 shown.
  • each sub-pixel unit of the display panel may include one longitudinal line, or each sub-pixel unit may include two longitudinal lines, or some sub-pixel units may include one longitudinal line, and some sub-pixel units may include one longitudinal line. Wire.
  • the above structure is not limited here, and is set according to the application scenario.
  • one sub-pixel unit further includes a plurality of vertical wirings, and in this case, the symmetry axis can be determined according to the number of vertical wirings.
  • the longitudinal trace at the center is used as the symmetry axis of the symmetrical structure.
  • the middle bus trace is used as the symmetry axis;
  • the center line between the two most edge longitudinal traces is used as the symmetry axis of the symmetrical structure.
  • the center line between the two bus traces is used The center line serves as the axis of symmetry.
  • the sub-pixel unit 21 includes one vertical wiring
  • the sub-pixel unit 22 includes two vertical wirings.
  • the display panel includes a base substrate 101 , a buffer layer 102 , a backplane, an electroluminescent device, an encapsulation layer 116 , a black matrix 117 and a color filter 118 , which are sequentially stacked.
  • the backplane includes an active layer 103, a first insulating layer 104, a first gate layer (not shown, located between the first insulating layer 104 and the second insulating layer 106), and a second insulating layer, which are stacked in sequence. 106.
  • the second gate layer (not shown, located between the second insulating layer 106 and the dielectric layer 108), the dielectric layer 108, the second metal layer 119, the second flat layer 109, the first metal layer 110, The first flat layer 111 .
  • the electroluminescent device includes a first electrode layer 112 , a pixel definition layer 113 , a light-emitting layer 114 and a second electrode layer 115 which are stacked in sequence.
  • the first electrode layer 112 is the first electrode layer
  • the second electrode layer 115 is the second electrode layer.
  • the second metal layer 119 is connected to the active layer 103 through the via hole 132 .
  • first electrode layer 112 , the pixel definition layer 113 , the light emitting layer 114 and the second electrode layer 115 of the sub-pixel unit 21 are arranged in a symmetrical structure with the longitudinal wiring 110 - 1 as the axis of symmetry.
  • the first electrode layer 112 , the pixel definition layer 113 , the light emitting layer 114 and the second electrode layer 115 of the sub-pixel unit 22 are arranged in a symmetrical structure with the center line 12 as the axis of symmetry. So that the display panel will not have the problem of color cast and color separation.
  • FIG. 6 shows an exemplary schematic diagram of a pixel driving circuit of the display panel of FIG. 1 .
  • the pixel driving circuit of the present application adopts an active matrix (AM) type organic light-emitting driving method with a 9T1C structure (ie, 9 transistors and 1 capacitor).
  • the pixel driving circuit includes a plurality of signal lines, a plurality of TFTs connected to the signal lines, a storage capacitor C1 and an organic light emitting diode D1. Signal lines may be shared among multiple sub-pixels.
  • AM active matrix
  • the plurality of TFTs include: a driving transistor T3, a first reset transistor T1, a second reset transistor T7, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second compensation transistor T9, and an initialization transistor T8 and the first compensation transistor T2.
  • the plurality of signal lines include: reset signal line 201 for transmitting reset signal Reset; gate signal line 202 for transmitting gate signal Gate; data signal line 208 for transmitting data signal Data; The light-emitting control signal line 203 of the signal EM; the initialization voltage signal line 207 for transmitting the initialization voltage signal Vint, and the reference voltage signal line 204 for transmitting the reference voltage signal Vref.
  • the power supply lines include a first power supply signal line 205 for transmitting the first power supply signal VDD, and a second power supply signal line 206 for transmitting the second power supply signal VSS.
  • the driving transistor T3 includes: a gate connected to the second node N2 of the energy storage capacitor C1; a first electrode used to receive the first power supply signal ELVDD; a second electrode connected to the second node N2 of the first compensation transistor T2; The second pole is the third node N3.
  • the first reset transistor T1 includes: a gate for receiving the reset signal Reset; a first pole connected to the second node of the energy storage capacitor C1 , namely the second node; and a second pole for receiving the initialization power signal Vint.
  • the second reset transistor T7 includes: a gate for receiving the reset signal Reset; a first pole for receiving the reference voltage signal Vref; and a second pole, connected to the first pole of the energy storage capacitor, that is, the first node N1.
  • the writing transistor T4 includes: a gate for receiving the gate signal Gata; a first pole, connected to the first node N1; and a second pole, for receiving the data signal Data.
  • the first light-emitting transistor T5 includes: a gate for receiving the light-emitting control signal EM; a first electrode for receiving the reference voltage signal Vref; and a second electrode for connecting to the first node N1.
  • the first light-emitting transistor T6 includes: a gate for receiving the light-emitting control signal EM; a first electrode, connected to the third node N3; and a second electrode, connected to the first electrode layer of the light-emitting diode D1.
  • the second compensation transistor T9 includes: a gate for receiving the light emission control signal EM; the first electrode is connected to the second electrode and is connected to the second node N2.
  • the second compensation transistor T9 can be regarded as a compensation capacitor to compensate the voltage of the point N2.
  • the initialization transistor T8 includes: a gate for receiving the gate signal Gate; a first electrode connected to the first electrode layer of the light emitting diode D1, and a second electrode for receiving the initialization signal Vint.
  • FIG. 7 shows an exemplary schematic diagram of a TFT and capacitor layout of a sub-pixel; FIGS. 8-11 show plan views of various layers in the FIG. 7 layout.
  • FIG. 8 to FIG. 11 illustrate embodiments of the same-layer wiring or semiconductor layer arrangement, wherein FIG. 8 is a plan view of the active layer 203 , FIG. 9 is a plan view of the first gate layer, and FIG. 10 is the second gate layer.
  • a plan view of the gate layer, FIG. 11 is a plan view of the second metal layer 119 .
  • FIG. 7 also includes a plan view of the first metal layer 110 of FIG. 2 .
  • FIG. 1 is a cross-sectional view taken along the line AA′ of FIG. 7 .
  • the figures include a reset signal line 201 arranged in a row direction for transmitting a reset signal Reset; a gate signal line 202 for transmitting a gate signal Gate; and a light emission control for transmitting the light emission control signal EM Signal line 203; a reference voltage signal line 204 for transmitting the reference voltage signal Vref, and a first power signal line 205 for transmitting a high level.
  • the reset signal line 201, the gate signal line 202 and the light emission control signal line 203 are arranged on the first gate layer, and the reference voltage signal line 204 and the first power signal line 205 are arranged on the second gate layer.
  • the figure also includes an initialization voltage signal line 207 arranged in the column direction for transmitting the initialization voltage signal Vint, a data signal line 208 for transmitting the data signal Data, and a first power supply signal line 205 for transmitting the first power supply signal VDD. ;
  • the second power signal line 206 for transmitting a low level.
  • the initialization voltage signal line 207 , the data signal line 208 and the first power signal line 205 are arranged on the second metal layer 119 , and the second power signal line 206 is arranged on the first metal layer 110 .
  • the first compensation transistor T2 may be formed along the active layer in FIG. 8 .
  • the active layer has a curved or bent shape, including the active layer AC-T8 of the initialization transistor T8, the active layer AC-T1 of the first reset transistor T1, the active layer AC-T2 of the first compensation transistor T2, the driving transistor The active layer AC-T3 of T3, the active layer AC-T6 of the second light emission control transistor T6, the active layer AC-T7 of the second reset transistor T7, the active layer AC-T4 of the data writing transistor T4, the The active layer AC-T9 of the two compensation transistors T9, and the active layer AC-T5 of the first light-emitting control transistor T5.
  • the active layer may include a polysilicon material and include a channel region, a source region, and a drain region.
  • the channel region may not be doped with impurities and thus has semiconductor characteristics.
  • the source region and the drain region are on the respective sides of the channel region, and are doped with impurities and thus have conductivity. Impurities vary depending on whether the transistor is P-type or N-type.
  • the source region and the drain region can be understood as the first electrode or the second electrode of the transistor.
  • the energy storage capacitor includes a first energy storage capacitor plate 211 and a second energy storage capacitor plate 212, which are located at the first gate layer and the second gate layer, respectively.
  • the first energy storage capacitor plate 211 can be used as the gate of the driving transistor T3
  • the second energy storage capacitor plate 212 can be used as the first electrode or the second electrode of the second compensation transistor.
  • the display panel includes a display area AA and a peripheral area surrounding the display area; in the display panel, the second electrode layer 115 is often made of Mg/Ag with a relatively high resistance, which will cause the second electrode layer There is a large voltage drop (IR Drop) on 115, which will also lead to an increase in driving power consumption.
  • a second power signal line 206 is prepared in the first metal layer, and the second electrode layer 115 in the peripheral area and the second electrode layer 115.
  • the second power signal line 206 includes a plurality of first-direction wirings and a plurality of second-direction wirings, and the orthographic projections of the first-direction wirings and the second-direction wirings on the base substrate 101 intersect, that is, a grid
  • the first direction is the extending direction of the data signal lines, namely the vertical direction
  • the second direction is the extending direction of the gate signal lines, that is, the row direction.
  • the first direction of the second power signal line 206 and the second direction of the second power signal line 206 are selected to be routed.
  • the same layer setting means that the two directions are set on the same film layer, which can be made of the same material or different materials.
  • the first direction wiring of the second power signal line 206 is lined with the second metal layer.
  • the orthographic projections on the base substrate 101 overlap to reduce the influence of the wiring in the first direction on the light transmission area of the display area.
  • the first direction routing of the second power signal line 206 and the orthographic projection of the initialization voltage signal line 207 on the base substrate 101 overlap, reducing the first direction routing Influence on the light transmission area of the display area.
  • the first direction routing of the second power signal line 206 and the orthographic projection of the first power signal line 205 on the base substrate 101 overlap, reducing the first direction routing The influence of lines on the light transmission area of the display area.
  • the first direction wiring of the second power signal line 206 and the orthographic projection of the data signal line 208 on the base substrate 101 overlap, reducing the number of first direction wiring pairs The influence of the transmittance area of the display area.
  • the second-direction traces of the second power signal lines 206 overlap with the orthographic projection of the second gate layer on the base substrate, reducing the number of first-direction trace pairs The influence of the light transmission area of the display area; wherein, the orthographic projection of the reference voltage signal line 204 on the second gate layer or the first power signal line 205 on the second gate layer on the base substrate can be selected to overlap ; In order to avoid the influence of the interlayer capacitance on the load of the signal line, the optimal choice is to overlap with the orthographic projection of the second energy storage capacitor plate 212 on the second gate layer on the base substrate 101 .
  • M sub-pixel units between two adjacently arranged first-direction wirings; N sub-pixel units are arranged between two adjacently arranged second-direction wirings; M, N It is a positive integer; it is selected according to the actual process conditions.
  • the wiring in the first direction of the second power signal line 206 and the wiring in the second direction of the second power signal line 206 are selected to be arranged in different layers, so as to reduce the difficulty of the process and save the process cost, wherein The different layers are set so that the traces in two directions are located in different film layers.
  • the present application further provides a display device, including the display panel provided by each embodiment of the present application.
  • the present application also provides a manufacturing method of a display panel. As shown in Figure 12, the manufacturing method includes the following steps:
  • Step S101 forming a backplane on the base substrate, the backplane includes a first metal layer and a first flat layer that are stacked in sequence, and the first metal layer of a sub-pixel unit includes a vertical wiring.
  • Step S102 forming a first electrode layer, the first electrode layer includes a protrusion, and the protrusion takes the longitudinal line as the axis of symmetry;
  • Step S103 forming a pixel definition layer, the pixel definition layer is provided with a pixel opening, and the pixel opening takes the longitudinal alignment as the axis of symmetry;
  • Step S104 forming a light-emitting layer
  • Step S105 forming a second electrode layer, the second electrode layer includes a recess, and the recess takes the longitudinal line as the axis of symmetry.
  • the above manufacturing process will be described below with reference to FIGS. 14 to 18 .
  • the figure includes a sub-pixel unit 21 and a sub-pixel unit 22 , and the sub-pixel unit 21 is used as an example for description below.
  • a backplane is formed on the base substrate 101.
  • the backplane includes a first metal layer 110 and a first flat layer 111 that are stacked in sequence.
  • the first metal layer 110 of the sub-pixel unit 21 includes a longitudinal Line 110-1.
  • the backplane includes an active layer 103, a first insulating layer 104, a first gate layer (not shown, located between the first insulating layer 104 and the second insulating layer 106), and a second insulating layer, which are stacked in sequence. 106 .
  • a second gate layer (not shown, located between the second insulating layer 106 and the dielectric layer 108 ), the dielectric layer 108 , the second planarization layer 109 , the first metal layer 110 , and the first planarization layer 111 .
  • a first electrode layer 112 is formed on the first flat layer 111 in FIG. 14 , and the first electrode layer includes a protrusion 112 - 1 , and the protrusion 112 - 1 takes the longitudinal line as the axis of symmetry.
  • a pixel definition layer 113 is formed on the first electrode layer 112 of FIG. 15 .
  • the pixel definition layer 113 is provided with a pixel opening 113 - 1 , and the pixel opening takes the longitudinal line as the axis of symmetry.
  • a light-emitting layer 114 is formed on the pixel definition layer 113 of FIG. 16 , and the light-emitting layer of the sub-pixel unit 21 has a symmetrical structure, with the longitudinal line as the axis of symmetry.
  • a second electrode layer 115 is formed on the light emitting layer 114 of FIG. 17 , and the second electrode layer 115 includes a recess 115 - 1 , and the recess takes the longitudinal line as the axis of symmetry.
  • an encapsulation layer 116 On the second electrode layer 115 shown, an encapsulation layer 116 , a black matrix 117 , and a color filter 118 are sequentially formed to form the display panel shown in FIG. 1 .
  • each layer may adopt the existing process method, which will not be repeated here.
  • the present application also provides a manufacturing method of a display panel. As shown in Figure 13, the manufacturing method includes the following steps:
  • Step S201 forming a backplane on the base substrate, the backplane includes a first metal layer and a first flat layer that are stacked in sequence, and the first metal layer of a sub-pixel unit includes two longitudinal wirings;
  • Step S202 forming a first electrode layer, the first electrode layer includes two protrusions, and the protrusions are respectively located directly above the longitudinal wiring;
  • Step S203 forming a pixel definition layer, and the pixel definition layer is provided with a pixel opening, and the pixel opening takes the center line between the two longitudinal lines as the axis of symmetry;
  • Step S204 forming a light-emitting layer
  • Step S205 forming a second electrode layer, the second electrode layer includes a recess, and the recess takes the center line between the two longitudinal wirings as the axis of symmetry.
  • the above manufacturing process will be described below with reference to FIGS. 14 to 18 .
  • the figure includes a sub-pixel unit 21 and a sub-pixel unit 22, and the sub-pixel unit 22 is used as an example for description below.
  • a backplane is formed on the base substrate.
  • the backplane includes a first metal layer 110 and a first flat layer 111 that are stacked in sequence, and the first metal layer 110 of a sub-pixel unit 22 includes two longitudinal lines. Line 110-1.
  • the backplane includes an active layer 103, a first insulating layer 104, a first gate layer (not shown, located between the first insulating layer 104 and the second insulating layer 106), and a second insulating layer, which are stacked in sequence. 106 .
  • a second gate layer (not shown, located between the second insulating layer 106 and the dielectric layer 108 ), the dielectric layer 108 , the second planarization layer 109 , the first metal layer 110 , and the first planarization layer 111 .
  • a first electrode layer 112 is formed on the first flat layer 111 in FIG. 14 , and the first electrode layer includes two protrusions 112 - 1 , and the two protrusions 112 - 1 take the center line 12 as the axis of symmetry .
  • a pixel definition layer 113 is formed on the first electrode layer 112 of FIG. 15 , and the pixel definition layer 113 is provided with a pixel opening 113 - 1 , and the pixel opening takes the center line 12 as the axis of symmetry.
  • a light-emitting layer 114 is formed on the pixel defining layer 113 of FIG. 16 , and the light-emitting layer of the sub-pixel unit 21 has a symmetrical structure, with the center line 12 as the axis of symmetry.
  • a second electrode layer 115 is formed on the light-emitting layer 114 of FIG. 17 , and the second electrode layer 115 includes a recess 115 - 1 , and the recess takes the center line 12 as the axis of symmetry.
  • an encapsulation layer 116 On the second electrode layer 115 shown, an encapsulation layer 116 , a black matrix 117 , and a color filter 118 are sequentially formed to form the display panel shown in FIG. 1 .
  • each sub-pixel unit of a display panel may adopt a structure including one vertical line, or each sub-pixel unit may adopt a structure including two vertical lines, or some sub-pixel units may adopt a structure including one vertical line.
  • Structure of Lines Another part of the sub-pixel units adopts a structure including two vertical lines. The above structure is not limited here, and settings are adopted according to the application.

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Abstract

本申请公开了一种显示面板、以及显示装置。所述显示面板包括：衬底基板，衬底基板上层叠设置有源层、第一绝缘层、第一栅极层、第二栅极层、第一金属层及第二金属层；设置于所述第一金属层远离衬底基板一侧的若干有机发光二极管器件；第一金属层包括第二电源信号线；第二金属层包括初始化电压信号线、第二电源信号线、数据信号线；第二电源信号线与第二电极层在周边区电连接；有机发光二极管器件包括依次设置于所述衬底上的第一电极层、发光层和第二电极层；其中，第二电源信号线包括多条第一方向走线和多条第二方向走线，第一方向走线和第二方向走线在衬底基板上的正投影相交。本发明能够降低显示面板的功耗。

Description

显示面板、显示装置
本申请要求享有2020年10月16日提交的、申请号为202011110228.8、发明名称为“显示面板、显示装置”的中国发明专利申请的优先权。
技术领域
本公开一般涉及显示技术领域，尤其涉及一种显示面板、一种包括该显示面板的显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示器因其具有自发光、对比度高、厚度薄、视角广、响应速度快、可弯折以及使用温度范围广等优点成为研究的热点。
当有机发光二极管用于显示面板中时，有机发光二极管通常包括第一电极层、第二电极层和夹在两个电极之间的发光层，并且各个发光单元的第二电极层整面制作。
发明内容
本申请的目的在于提供一种显示面板以及一种显示装置。
第一方面，提供一种显示面板，具有显示区与周边区，包括：衬底基板，所述衬底基板上层叠设置有源层、第一绝缘层、第一栅极层、第二栅极层、第一金属层及第二金属层；
设置于所述第一金属层远离衬底基板一侧的若干有机发光二极管器件；
所述第一金属层包括第二电源信号线；
所述第二金属层包括初始化电压信号线、第一电源信号线、数据信号线；
所述第二电源信号线与所述第二电极层在所述周边区电连接；
所述有机发光二极管器件包括依次设置于所述衬底上的第一电极层、发光层和第二电极层；
其中，所述第二电源信号线包括多条第一方向走线和多条第二方向走线，所述第一方向走线和所述第二方向走线在所述衬底基板上的正投影相交。
在一些实施例中，第一方向走线和第二方向走线同层设置。
在一些实施例中，显示区内，第一方向走线与第二金属层在所述衬底基板上的正投影相交叠。
在一些实施例中，显示区内，第一方向走线与初始化电压信号线在所述衬底基板上的正投影相交叠。
在一些实施例中，显示区内，第一方向走线与第一电源信号线在所述衬底基板上的正投影相交叠。
在一些实施例中，显示区内，第一方向走线与数据信号线在所述衬底基板上的正投影相交叠。
在一些实施例中，显示区内，第二方向走线与第二栅极层在所述衬底基板上的正投影相交叠。
在一些实施例中，两相邻设置的第一方向走线间具有M个子像素单元；
两相邻设置的所述第二方向走线间具有N个子像素单元；
M，N为正整数。
在一些实施例中，第一方向走线和所述第二方向走线异层设置。。
第二方面、提供一种显示装置，包括本申请各实施例所提供的的显示面板。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显：
图1示出了根据本申请实施例的显示面板的示例性结构图；
图2示出了图1的第一金属层的示例性俯视图；
图3示出了图1的第一电极的示例性俯视图；
图4示出了图1的像素开口的示例性俯视图；
图5示出了图1的第一金属层、第一电极及像素开口叠设置的示例性俯视图；
图6示出了图1的显示面板的像素驱动电路的示例性示意图；
图7示出了子像素的TFT和电容器布局的示例性示意图；
图8至图11示出了图7布局中的各个层的平面图；
图12示出了根据本申请实施例的显示面板制造方法的示例性流程图；
图13示出了根据本申请另一实施例的显示面板制造方法的示例性流程图；
图14至图18示出了根据图12和图13中显示面板制造方法的的具体示例性示意图；
图19示出了第二电源信号线与显示面板整体示例性示意图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释相关发明，而非对该发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与发明相关的部分。
除非另外定义，本发明使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
发明人发现现有的显示面板有如下问题：目前有机发光二极管通常包括第一电极层、第二电极层和夹在两个电极之间的发光层，发光层至少包括一个空穴传输层、一个发光层和一个电子传输层。第一电极层和第二电极层形成的半导体微腔是一种窄化光谱的光学结构，发光层内产生的光子被限制在 由两个镜面形成的腔体内，因此，发光二极管的发光特性不仅依赖有机发光材料本身所固有的特性，第一电极层、第二电极层等的形貌有着一定相关性。不恰当的第一电极层、或者第二电极层的设计将产生色偏，或者产生色分离。例如，在一个子像素单元，如果发光层的各部分发射的光强不相同，或者相同视角处看到的光强不相同时，观看者看到的图像将有色偏问题。另外，外界光线入射到显示面板后，经部分金属层(例如，第一电极层、第二电极层)反射形成反射光，当该反射光在相同视角处看到的光强不相同时，观看者看到的图像将有色分离问题。因此，采用合理的显示面板结构，使得相同视角处显示面板出射的光强相同，以及相同视角处显示面板反射的光强相同。
为了解决上述技术问题，本申请提供如下显示面板。
请参考图1，给出一种显示面板的结构示意图。该显示面板包括多个子像素单元，各子像素单元分别包括依次层叠设置的第一金属层110、第一平坦层111、第一电极层112、像素定义层113、发光层114和第二电极层115。其中：
第一金属层110至少包括一根均匀并排分布的纵向走线110-1；第一金属层110、第一电极层112、像素定义层113和第二电极层115分别采用轴对称结构。其中，当纵向走线110-1的数量为奇数时，以中心位置的纵向走线为对称结构的对称轴11；当纵向走线110-1的数量为偶数时，以最边缘两根纵向走线之间的中心线作为对称结构的对称轴12。
如图1所示，第一金属层110上依次层叠设置有第一平坦层111、第一电极层112、像素定义层113、发光层114、第二电极层115，其中，第一电极层112形成有与第一金属层110随形的凸起112-1，使得第一电极层112与第二电极层115之间形成的发光层114的厚度不均，进而引起发光层114发射的光强的不均、第一电极层112所反射的外部光的光强也会不均。因此将第一金属层110、第一电极层112、像素定义层113和第二电极层115分别设置为轴对称结构，使得对称轴两侧发光层发射的光线的光强相等，如与对称轴11距离相同的位置发射的光线R1与光线R2的光强相等、与对称轴12距离相同的位置发射的光线B1与光线B2的光强相等，对称轴11距离相同的位置反射的反射光线R3与反射光线R4的光强相等、对称轴12距离相同的位置反 射的反射光线B3与反射光线B4的光强相等。这里的随形是指两个堆叠的层中，其中一层跟着另一层的结构变化而变化。第一金属层可根据需要传输信号，例如可传输像素驱动电路中的电源信号，这里不做限定。
请参考图1至图5，其中，图2示出了图1的第一金属层的示例性俯视图；图3示出了图1的第一电极的示例性俯视图；图4示出了图1的像素开口的示例性俯视图；图5示出了图1的第一金属层、第一电极及像素开口层叠设置的示例性俯视图；
在一些实施例中，子像素单元21的第一金属层110设置有一根纵向走线110-1；子像素单元21的第一电极层112包括一凸起112-1，该凸起112-1采用以纵向走线110-1为对称轴的轴对称结构。
需要说明的是，严格意义上来讲，这里的对称轴11可以理解为纵向走线110-1的中心线。当忽略纵向走线110-1的宽度时，可以认为对称轴为纵向走线110-1。本申请为了说明的便利采用后一种说法。
此时，外部光线经第一电极层112形成的反射光线以纵向走线110-1为对称轴对称。如与纵向走线110-1距离相同的位置的反射光R3与反射光R4的出射角相同且光强相等。防止了色分离的出现。
在一些实施例中，子像素单元21的像素定义层113包括一像素开口113-1，该像素开口113-1采用以纵向走线110-1为对称轴的轴对称结构；
子像素单元21的第二电极层115包括一凹陷115-1，该凹陷115-1采用以纵向走线110-1为对称轴的轴对称结构。
该实施例给出在一个子像素单元包括一根纵向走线的情况，此时，凸起112-1、凹陷115-1、像素开口115-1分别以纵向走线110-1为对称轴对称，因此第一电极层112与第二电极层115之间的发光层114也以纵向走线110-1为对称轴对称。此时，子像素单元21中形成以纵向走线110-1为对称轴对称的发光层。因此，发光层发出的光线的光强也以纵向走线110-1为对称轴而对称，如与纵向走线110-1距离相同的位置的出射光R1与出射光R2的出射角相同且光强相等。防止了色偏的出现。
如图1和图5所示，在一些实施例中，像素开口115-1在子像素单元21 的第一金属层的正投影覆盖纵向走线110-1。图2、图3和图4分别给出第一金属层110、第一电极层112和像素开口113-1的俯视图，图5给出前三者的层叠结构图。如图2所示，第一金属层设置有均匀并排设置的纵向走线110-1，如图3所示，第一电极层设置有第一电极块112-1，如图4所示，像素定义层设置有像素开口113-1，如图5所示，子像素单元21的像素开口113-1和第一电极块112-2分别采用以纵向走线110-1为对称轴的对称结构，且子像素单元21的像素开口115-1在第一金属层的正投影覆盖所示纵向走线110-1。
请参考图1至图5，在一些实施例中，子像素单元22的第一金属层110设置有两根纵向走线；子像素单元22的第一电极层112包括两个凸起112-1，该凸起112-1分别位于纵向走线110的正上方。
该实施例给出，在一个子像素单元包括两根纵向走线的情况，此时，外部光线经第一电极层形成的反射光线也以对称轴12为对称轴而对称。如与对称轴12距离相同的位置反射的反射光R3与反射光R4的出射角相同且光强相等。防止了色分离的出现。
在一些实施例中，子像素单元22的像素定义层113包括一像素开口113-1，该像素开口113-1采用以两根纵向走线的中心线为对称轴的轴对称结构；
子像素单元22的第二电极层115包括一凹陷115-1，该凹陷115-1采用两根纵向走线110-1的中心线为对称轴的轴对称结构。
此时，凸起112-1、凹陷115-1、像素开口113-1分别以对称轴12为对称轴对称，因此第一电极层112与第二电极层115之间的发光层114也以对称轴12为对称轴对称。此时，子像素单元22中形成的以对称轴12为对称轴对称的发光层。因此，发光层114发出的光线的光强也以对称轴12为对称轴而对称，如与对称轴12距离相同的位置出射的出射光B1与出射光B2的出射角相同且光强相等。防止了色偏的出现。
如图1和图5所示，在一些实施例中，像素开口113-1在子像素单元22的第一金属层的正投影覆盖两根纵向走线110-1。图2、图3和图4分别给出第一金属层110、第一电极层112和像素开口113-1的俯视图，图5给出前三 者的层叠结构图。如图2所示，第一金属层设置有均匀并排设置的纵向走线110-1，如图3所示，第一电极层设置有第一电极块112-1，如图4所示，像素定义层设置有像素开口113-1，如图5所示，子像素单元22的像素开口113-1和第一电极块112-2分别以纵向走线110-1之间的对称轴12为对称轴的对称结构，且子像素单元22的像素开口115-1在第一金属层的正投影覆盖所示两根纵向走线110-1。
需要说明的是，显示面板的各子像素单元可以包括一个纵向走线，或者各子像素单元包括两个纵向走线，或者部分子像素单元包括一个纵向走线另一部分子像素单元包括一个纵向走线。这里对上述结构不做限定，根据应用场景设定。
此外，一个子像素单元还包括多个纵向走线，此时，对称轴可根据纵向走线的数量来确定。当所述纵向走线的数量为奇数时，以中心位置的纵向走线为所述对称结构的对称轴，例如纵向走线为3个时，以中间的总线走线作为对称轴；当所述纵向走线的数量为偶数时，以最边缘的两根纵向走线之间的中心线作为所述对称结构的对称轴，例如纵向走线为2个时，以两根总线走线之间的中心线作为对称轴。
下面结合图1至图5给出一种显示面板的具体例子。其中，子像素单元21包括一根纵向走线，子像素单元22包括两根纵向走线。显示面板包括依次层叠设置的衬底基板101、缓冲层102、背板、电致发光器件、封装层116、黑矩阵117以及彩膜118。其中，背板包括依次层叠设置的有源层103、第一绝缘层104、第一栅极层(未标出，位于第一绝缘层104与第二绝缘层106之间)、第二绝缘层106、第二栅极层(未标出，位于第二绝缘层106与介电层108之间)、介电层108、第二金属层119、第二平坦层109、第一金属层110、第一平坦层111。电致发光器件包括依次层叠设置的第一电极层112、像素定义层113、发光层114和第二电极层115。其中，第一电极层112为第一电极层，第二电极层115为第二电极层。第二金属层119通过过孔132与有源层103连接。
另外，子像素单元21的第一电极层112、像素定义层113、发光层114 和第二电极层115设置成以纵向走线110-1为对称轴的对称结构。子像素单元22的第一电极层112、像素定义层113、发光层114和第二电极层115设置成以中心线12为对称轴的对称结构。使得显示面板不会出现色偏和色分离的问题。
图6示出了图1的显示面板的像素驱动电路的示例性示意图。本申请的像素驱动电路采用具有9T1C结构(即9个晶体管和1个电容)的有源矩阵(AM)型有机发光驱动方式。如图1所示，像素驱动电路包括多条信号线、连接至信号线的多个TFT、储能电容C1以及有机发光二极管D1。信号线可在多个子像素之间共享。
多个TFT包括：驱动晶体管T3、第一复位晶体管T1、第二复位晶体管T7、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6、第二补偿晶体管T9、初始化晶体管T8以及第一补偿晶体管T2。
多条信号线包括：用于传输复位信号Reset的复位信号线201；用于传输栅极信号Gate的栅极信号线202；用于传输发数据信号Data的数据信号线208；用于传输发光控制信号EM的发光控制信号线203；用于传输初始化电压信号Vint的初始化电压信号线207，用于传输参考电压信号Vref的参考电压信号线204。电源线包括用于传输第一电源信号VDD的第一电源信号线205、用于传输第二电源信号VSS的第二电源信号线206。
驱动晶体管T3包括：栅极，连接至储能电容C1的第二极即第二节点N2；第一极，用于接收第一电源信号ELVDD；第二极，连接至第一补偿晶体管T2的第二极即第三节点N3。
第一复位晶体管T1包括：栅极，用于接收复位信号Reset；第一极，连接至储能电容C1的第二极即第二节点；第二极，用于接收初始化电源信号Vint。
第二复位晶体管T7包括：栅极，用于接收复位信号Reset；第一极，用于接收参考电压信号Vref；第二极，连接至储能电容的第一极即第一节点N1。
写入晶体管T4包括：栅极，用于接收栅极信号Gata；第一极，连接至第一节点N1；第二极，用于接收数据信号Data。
第一发光晶体管T5包括：栅极，用于接收发光控制信号EM；第一极，用于接收参考电压信号Vref；第二极，连接至第一节点N1。
第一发光晶体管T6包括：栅极，用于接收发光控制信号EM；第一极，连接至第三节点N3；第二极，连接至发光二极管D1的第一电极层。
第二补偿晶体管T9包括：栅极，用于接收发光控制信号EM；第一极与第二极相连，连接至第二节点N2。实际上第二补偿晶体管T9可看作补偿电容，补偿N2点的电压。
初始化晶体管T8包括：栅极，用于接收栅极信号Gate；第一极，连接至发光二极管D1的第一电极层，第二极，用于接收初始化信号Vint。
图7示出了子像素的TFT和电容器布局的示例性示意图；图8至图11示出了图7布局中的各个层的平面图。具体地，图8至图11示出了同层布线或半导体层布置的实施方式，其中，图8为有源层203的平面图，图9为第一栅极层的平面图，图10为第二栅极层的平面图，图11为第二金属层119的平面图。另外，图7中还包括图2的第一金属层110的平面图。其中，第一栅极层位于第一绝缘层104与第二绝缘层106之间；第二栅极层位于第二绝缘层106与介电层108之间。如图7所示，图1是图7沿着AA'线的截面图。
参考图7至图11，图中包括行方向布置的用于传输复位信号Reset的复位信号线201；用于传输栅极信号Gate的栅极信号线202；用于传输发光控制信号EM的发光控制信号线203；用于传输参考电压信号Vref的参考电压信号线204，用于传输高电平的第一电源信号线205。其中，复位信号线201、栅极信号线202和发光控制信号线203设置在第一栅极层，参考电压信号线204和第一电源信号线205设置在第二栅极层。
图中还包括列方向布置的用于传输初始化电压信号Vint的初始化电压信号线207，用于传输发数据信号Data的数据信号线208；用于传输第一电源信号VDD的第一电源信号线205；用于传输低电平的第二电源信号线206。其中，初始化电压信号线207、数据信号线208和第一电源信号线205设置在 第二金属层119，第二电源信号线206设置在第一金属层110上。
图8所示，驱动晶体管T3、第一复位晶体管T1、第二复位晶体管T7、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6、第二补偿晶体管T9、初始化晶体管T8以及第一补偿晶体管T2可沿着图8中的有源层形成。有源层具有弯曲或弯折形状，包括初始化晶体管T8的有源层AC-T8、第一复位晶体管T1的有源层AC-T1、第一补偿晶体管T2的有源层AC-T2、驱动晶体管T3的有源层AC-T3、第二发光控制晶体管T6的有源层AC-T6、第二复位晶体管T7的有源层AC-T7、数据写入晶体管T4的有源层AC-T4、第二补偿晶体管T9的有源层AC-T9，以及第一发光控制晶体管T5有源层AC-T5。
有源层可包括多晶硅材料，并且包括沟道区、源极区和漏极区。沟道区可不掺杂有杂质，因此具有半导体特性。源极区和漏极区在沟道区的分别侧，且参杂有杂质，因此具有导电性。杂质根据晶体管是P型或N型而变化。源极区和漏极区可以被理解为晶体管的第一极或第二极。
储能电容包括第一储能电容板211和第二储能电容板212，分别位于第一栅极层和第二栅极层。其中，第一储能电容板211可作为驱动晶体管T3的栅极，第二储能电容板212可作为第二补偿晶体管的第一极或第二极。
如图19所示，显示面板包括显示区AA区以及环绕显示区的周边区；在显示面板中，第二电极层115常采用电阻较大的Mg/Ag制作，从而会导致在第二电极层115上有较大的压降(IR Drop)，进而也会导致增大驱动功耗，为解决上述问题，在第一金属层制备第二电源信号线206，在周边区与第二电极层115相连，相当于将第二电源信号线206与第二电极层115并联，因此可以减少第二电极层115的电阻，从而减小第二电源信号的压降，进而减小显示面板的驱动功耗；第二电源信号线206包括多条第一方向走线和多条第二方向走线，第一方向走线和第二方向走线在衬底基板101上的正投影相交，即为网格状的形状，为更好的减小显示面板的驱动功耗，其中第一方向为数据信号线延伸的方向，即纵方向；第二方向为栅极信号线延伸方向，即为行方向。
在本发明的一些实施例中，为减少显示面板的厚度，达到显示面板的轻薄化，选择将第二电源信号线206的第一方向走线和第二电源信号线206的第二方向走线同层设置，同层设置为两个方向走线设置在相同的膜层，可以使用相同材质或不同材质制成。
在本发明的一些实施例中，为减少第二电源信号线206对显示区透光面积的影响，在显示区内，第二电源信号线206的第一方向走线与第二金属层在衬底基板101上的正投影相交叠，减少第一方向走线对显示区透光面积的影响。
在本发明的一些实施例中，在显示区内，第二电源信号线206的第一方向走线与初始化电压信号线207在衬底基板101上的正投影相交叠，减少第一方向走线对显示区透光面积的影响。
在本发明的一些实施例中，在显示区内，第二电源信号线206的第一方向走线与第一电源信号线205在衬底基板101上的正投影相交叠，减少第一方向走线对显示区透光面积的影响。
在本发明的一些实施例中，在显示区内，第二电源信号线206的第一方向走线与数据信号线208在衬底基板101上的正投影相交叠，减少第一方向走线对显示区透光面积的影响。
在本发明的一些实施例中，在显示区内，第二电源信号线206的第二方向走线与第二栅极层在衬底基板上的正投影相交叠，减少第一方向走线对显示区透光面积的影响；其中，可以选择在第二栅极层上的参考电压信号线204或者在第二栅极层上的第一电源信号线205在衬底基板上的正投影相交叠；为避免产生层间电容对信号线负载产生影响，最优选择与在第二栅极层上的第二储能电容板212在衬底基板101上的正投影相交叠。
在本发明的一些实施例中，两相邻设置的所述第一方向走线间具有M个子像素单元；两相邻设置的所述第二方向走线间具有N个子像素单元；M，N为正整数；根据实际工艺条件进行选择。
在本发明的一些实施例中，选择将第二电源信号线206的第一方向走线和第二电源信号线206的第二方向走线异层设置，减少工艺难度，可以节省 工艺成本，其中异层设置为两个方向走线位于不同的膜层。
本申请还提供一种显示装置，包括本申请各实施例所提供的显示面板。
本申请还提供一种显示面板的制造方法。如图12所示，该制造方法包括如下步骤：
步骤S101：在衬底基板上形成背板，背板包括依次层叠设置的第一金属层和第一平坦层，一子像素单元的第一金属层包括一根纵向走线。
步骤S102：形成第一电极层，第一电极层包括一凸起，该凸起以纵向走线为对称轴；
步骤S103：形成像素定义层，像素定义层设置有像素开口，该像素开口以纵向走线为对称轴；
步骤S104：形成发光层；
步骤S105：形成第二电极层，第二电极层包括一凹陷，该凹陷以纵向走线为对称轴。
下面结合图14至图18说明上述制造过程。图中包括子像素单元21和子像素单元22，下面以子像素单元21为例进行说明。
如图14所示，在衬底基板101上形成背板，背板包括依次层叠设置的第一金属层110和第一平坦层111，子像素单元21的第一金属层110包括一根纵向走线110-1。其中，背板包括依次层叠设置的有源层103、第一绝缘层104、第一栅极层(未标出，位于第一绝缘层104与第二绝缘层106之间)、第二绝缘层106、第二栅极层(未标出，位于第二绝缘层106与介电层108之间)、介电层108、第二平坦层109、第一金属层110、第一平坦层111。
图15所示，在图14的第一平坦层111上形成第一电极层112，第一电极层包括一凸起112-1，该凸起112-1以纵向走线为对称轴。
如图16所示，在图15的第一电极层112上形成像素定义层113，像素定义层113设置有像素开口113-1，该像素开口以纵向走线为对称轴。
如图17所示，在图16的像素定义层113上形成发光层114，子像素单元21的发光层为对称结构，以纵向走线为对称轴。
如图18所示，在图17的发光层114上形成第二电极层115，第二电极层115包括一凹陷115-1，该凹陷以纵向走线为对称轴。
在所示第二电极层115上，依次形成封装层116、黑矩阵117、彩膜118后形成如图1所示的显示面板。
其中，各层的形成方法可采用现有工艺方法即可，这里不再赘述。
本申请还提供一种显示面板的制造方法。如图13所示，该制造方法包括如下步骤：
步骤S201：在衬底基板上形成背板，背板包括依次层叠设置的第一金属层和第一平坦层，一子像素单元的第一金属层包括两根纵向走线；
步骤S202：形成第一电极层，第一电极层包括两个凸起，该凸起分别位于纵向走线的正上方；
步骤S203：形成像素定义层，像素定义层设置有像素开口，该像素开口以两根纵向走线之间的中心线为对称轴；
步骤S204：形成发光层；
步骤S205：形成第二电极层，第二电极层包括一凹陷，该凹陷以两根纵向走线之间的中心线为对称轴。
下面结合图14至图18说明上述制造过程。图中包括子像素单元21和子像素单元22，下面以子像素单元22为例进行说明。
如图8所示，在衬底基板上形成背板，背板包括依次层叠设置的第一金属层110和第一平坦层111，一子像素单元22的第一金属层110包括两根纵向走线110-1。其中，背板包括依次层叠设置的有源层103、第一绝缘层104、第一栅极层(未标出，位于第一绝缘层104与第二绝缘层106之间)、第二绝缘层106、第二栅极层(未标出，位于第二绝缘层106与介电层108之间)、介电层108、第二平坦层109、第一金属层110、第一平坦层111。
图15所示，在图14的第一平坦层111上形成第一电极层112，第一电极层包括两个凸起112-1，该两个凸起112-1以中心线12为对称轴。
如图16所示，在图15的第一电极层112上形成像素定义层113，像素定义层113设置有像素开口113-1，该像素开口以中心线12为对称轴。
如图17所示，在图16的像素定义层113上形成发光层114，子像素单元21的发光层为对称结构，以中心线12为对称轴。
如图18所示，在图17的发光层114上形成第二电极层115，第二电极层115包括一凹陷115-1，该凹陷以中心线12为对称轴。
在所示第二电极层115上，依次形成封装层116、黑矩阵117、彩膜118后形成如图1所示的显示面板。
需要说明的是，一个显示面板的各子像素单元可以都采用包括一个纵向走线的结构，或者各子像素单元可以都采用包括两个纵向走线的结构，或者部分子像素单元采用包括一个纵向走线的结构另一部分子像素单元采用包括两个个纵向走线的结构。这里对上述结构不做限定，根据应用采用设定。
以上描述仅为本申请的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本申请中所涉及的发明范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离所述发明构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本申请中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。

Claims (10)

  1. 一种显示面板，具有显示区与周边区，其特征在于，包括：
    衬底基板，所述衬底基板上层叠设置有源层、第一绝缘层、第一栅极层、第二栅极层、第一金属层及第二金属层；
    设置于所述第一金属层远离衬底基板一侧的若干有机发光二极管器件；
    所述第一金属层包括第二电源信号线；
    所述第二金属层包括初始化电压信号线、第一电源信号线、数据信号线；
    所述第二电源信号线与所述第二电极层在所述周边区电连接；
    所述有机发光二极管器件包括依次设置于所述衬底上的第一电极层、发光层和第二电极层；
    其中，所述第二电源信号线包括多条第一方向走线和多条第二方向走线，所述第一方向走线和所述第二方向走线在所述衬底基板上的正投影相交。
  2. 根据权利要求1所述的显示面板，其特征在于，所述第一方向走线和所述第二方向走线同层设置。
  3. 根据权利要求2所述的显示面板，其特征在于，所述显示区内，所述第一方向走线与所述第二金属层在所述衬底基板上的正投影相交叠。
  4. 根据权利要求3所述的显示面板，其特征在于，所述显示区内，所述第一方向走线与所述初始化电压信号线在所述衬底基板上的正投影相交叠。
  5. 根据权利要求3所述的显示面板，其特征在于，所述显示区内，所述第一方向走线与所述第一电源信号线在所述衬底基板上的正投影相交叠。
  6. 根据权利要求3所述的显示面板，其特征在于，所述显示区内，所述第一方向走线与所述数据信号线在所述衬底基板上的正投影相交叠。
  7. 根据权利要求3所述的显示面板，其特征在于，所述显示区内，所述第二方向走线与所述第二栅极层在所述衬底基板上的正投影相交叠。
  8. 根据权利要求1-7中任意一项所述的显示面板，其特征在于，两相邻设置的所述第一方向走线间具有M个子像素单元；
    两相邻设置的所述第二方向走线间具有N个子像素单元；
    M，N为正整数。
  9. 根据权利要求1所述的显示面板，其特征在于，所述第一方向走线和所述第二方向走线异层设置。
  10. 一种显示装置，其特征在于，包括权利要求1-7，9任一项所述的显示面板。
PCT/CN2021/115903 2020-10-16 2021-09-01 显示面板、显示装置 WO2022078093A1 (zh)

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