WO2022226845A1 - 显示基板以及显示面板 - Google Patents

显示基板以及显示面板 Download PDF

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Publication number
WO2022226845A1
WO2022226845A1 PCT/CN2021/090732 CN2021090732W WO2022226845A1 WO 2022226845 A1 WO2022226845 A1 WO 2022226845A1 CN 2021090732 W CN2021090732 W CN 2021090732W WO 2022226845 A1 WO2022226845 A1 WO 2022226845A1
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Prior art keywords
sub
signal line
light
transistor
layer
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PCT/CN2021/090732
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English (en)
French (fr)
Inventor
韩林宏
王琦伟
王本莲
黄耀
黄炜赟
王智
王彬艳
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/090732 priority Critical patent/WO2022226845A1/zh
Priority to US17/640,546 priority patent/US20240078971A1/en
Priority to CN202180000958.9A priority patent/CN115605939A/zh
Priority to GB2304967.9A priority patent/GB2614200A/en
Publication of WO2022226845A1 publication Critical patent/WO2022226845A1/zh

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    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • Embodiments of the present disclosure relate to a display substrate and a display panel.
  • OLEDs organic light-emitting diodes
  • a display substrate including: a base substrate, a plurality of sub-pixels disposed on the base substrate, a first voltage line, a data line, a scan signal line, and a first light-emitting control signal line and a second light-emitting control signal line, wherein each sub-pixel includes a pixel circuit and a light-emitting element, the pixel circuit includes: a driving sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit and a data writing sub-circuit , the first light-emitting control sub-circuit is electrically connected to the first end of the driving sub-circuit, the first electrode of the light-emitting element and the first light-emitting control signal line, and is configured to emit light at the first Under the control of the first light-emitting control signal on the control signal line, the connection between the first end of the driving sub-circuit and the first electrode of the light-emitting element
  • the pixel circuit further includes a storage capacitor, the first electrode plate of the storage capacitor is electrically connected to the control terminal of the driving sub-circuit, and the first electrode plate of the storage capacitor is electrically connected to the control terminal of the driving sub-circuit, and the first electrode plate of the storage capacitor is The two electrode plates are electrically connected to the first voltage line, and in the second direction, the orthographic projection of the first light-emitting control signal line on the base substrate and the second light-emitting control signal line on the The orthographic projection on the base substrate is located on both sides of the orthographic projection of the second electrode plate of the storage capacitor on the base substrate.
  • the orthographic projection of the scanning signal line on the base substrate and the second light-emitting control signal line on the substrate is located on both sides of the orthographic projection of the second electrode plate of the storage capacitor on the base substrate.
  • the display substrate provided by some embodiments of the present disclosure further includes a reset signal line and an initial signal line disposed on the base substrate
  • the pixel circuit further includes a reset sub-circuit and a threshold compensation sub-circuit
  • the reset sub-circuit is electrically connected to the control terminal of the driving sub-circuit, the initial signal line, the first light-emitting control signal line and the reset signal line, and is configured to be connected between the first light-emitting control signal and the reset signal Under the control of the reset control signal on the initial signal line, the initial voltage on the initial signal line is transmitted to the control terminal of the driving sub-circuit
  • the threshold compensation sub-circuit is electrically connected to the control terminal of the driving sub-circuit and the first one end and the reset signal line, and is configured to control the connection between the first end of the driving sub-circuit and the control end of the driving sub-circuit to be turned on or off under the control of the reset control signal On
  • the reset signal line extends along the first direction, and in the second direction, the reset
  • the reset sub-circuit includes a first reset transistor, the first reset transistor includes a reset active layer, and the reset active layer includes a first reset active layer part
  • the threshold compensation sub-circuit includes a threshold compensation transistor, the threshold compensation transistor includes a compensation active layer, the compensation active layer includes a first compensation active layer part, and the first reset active layer part is The orthographic projection on the base substrate and the orthographic projection of the initial signal line on the base substrate at least partially overlap, and the orthographic projection of the first compensation active layer part on the base substrate and the Orthographic projections of the initial signal lines on the base substrate at least partially overlap.
  • the initial signal line includes a first sub-initial signal line, the first sub-initial signal line extends along the first direction, and the first reset active
  • the orthographic projection of the layer portion on the base substrate and the orthographic projection of the first compensation active layer portion on the base substrate are both located at the position of the first sub-initial signal line on the base substrate. in the orthographic projection.
  • the first reset active layer portion and the first compensation active layer portion are sequentially arranged in the first direction.
  • the initial signal line further includes a second sub-initial signal line, the second sub-initial signal line extends along the second direction, and the first sub-initial signal line extends along the second direction.
  • the signal line is electrically connected to the second sub-initial signal line.
  • the display substrate includes an active semiconductor layer, a first conductive layer, a second conductive layer, and a source-drain metal layer, in a direction perpendicular to the base substrate above, the active semiconductor layer is located between the base substrate and the first conductive layer, the first conductive layer is located between the active semiconductor layer and the second conductive layer, and the first conductive layer is located between the active semiconductor layer and the second conductive layer.
  • Two conductive layers are located between the first conductive layer and the source-drain metal layer, the first sub-initial signal line is located in the second conductive layer, and the second sub-initial signal line is located in the source and drain Extreme metal layer.
  • the reset active layer further includes a second reset active layer portion
  • the compensation active layer includes a second compensation active layer portion
  • the second reset active layer The orthographic projection of the active layer portion on the base substrate and the orthographic projection of the reset signal line on the base substrate at least partially overlap, and the second compensation active layer portion is on the base substrate
  • the orthographic projection of the reset signal line and the orthographic projection of the reset signal line on the base substrate at least partially overlap, and the second reset active layer portion and the second compensation active layer portion are sequentially in the first direction. arrangement.
  • the first reset transistor and the threshold compensation transistor are both dual-gate transistors.
  • the display substrate includes an active semiconductor layer and a first conductive layer, and in a direction perpendicular to the base substrate, the active semiconductor layer is located on the Between the base substrate and the first conductive layer, the reset signal line, the scan signal line, the first light emission control signal line and the second light emission control signal line are all located in the first conductive layer .
  • the initial voltage is passed through the reset sub-circuit, the threshold compensation sub-circuit and The first light emission control subcircuit is transmitted to the first electrode of the light emitting element.
  • the driving sub-circuit includes a driving transistor, the control end of the driving sub-circuit includes the gate of the driving transistor, and the first end of the driving circuit includes the The first pole of the drive transistor, the second end of the drive circuit includes the second pole of the drive transistor;
  • the first light-emitting control sub-circuit includes a first light-emitting control transistor, and the gate of the first light-emitting control transistor
  • the electrode is electrically connected to the first light-emitting control signal line, the first electrode of the first light-emitting control transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the first light-emitting control transistor is electrically connected to the The first electrode of the light-emitting element, the second electrode of the light-emitting element is electrically connected to the second voltage line;
  • the second light-emitting control sub-circuit includes a second light-emitting control transistor, the gate of the second light-emitting control transistor is electrically connected
  • the data writing sub-circuit includes a data writing transistor, the gate of the data writing transistor is electrically connected to the scan signal line, and the first electrode of the data writing transistor is electrically connected to the data line, the second pole of the data writing transistor is electrically connected to the second pole of the driving transistor;
  • the reset sub-circuit includes a first reset transistor and a second reset transistor, the gate of the first reset transistor is electrically connected connecting the reset signal line, the first pole of the first reset transistor is electrically connected to the initial signal line, and the second pole of the first reset transistor is electrically connected to the first pole of the second reset transistor;
  • the gate of the second reset transistor is electrically connected to the first light-emitting control signal line, and the second electrode of the second reset transistor is electrically connected to the gate of the driving transistor;
  • the threshold compensation sub-circuit includes threshold compensation a transistor, the gate of the threshold compensation transistor is electrically connected to the reset signal line, the first electrode of the threshold compensation transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of
  • the display substrate includes an active semiconductor layer, a first conductive layer, a second conductive layer, a source-drain metal layer, and a planarization layer.
  • the active semiconductor layer is located between the base substrate and the first conductive layer
  • the first conductive layer is located between the active semiconductor layer and the second conductive layer
  • the second conductive layer is located between the first conductive layer and the source-drain metal layer
  • the planarization layer is located on the side of the source-drain metal layer away from the base substrate, so
  • the second electrode of the first light-emitting control transistor is electrically connected to the first electrode of the light-emitting element through a first via hole penetrating the planarization layer, and in the second direction, the first via hole is located in the second direction.
  • the orthographic projection on the base substrate is located between the orthographic projection of the reset signal line on the base substrate and the orthographic projection of the second light-emitting control signal line on the
  • the display substrate further includes a first insulating layer, a second insulating layer, and a third insulating layer
  • the first insulating layer is located between the active semiconductor layer and the between the first conductive layers, the second insulating layer between the first conductive layer and the second conductive layer, and the third insulating layer between the second conductive layer and the source and drain
  • the portion of the active semiconductor layer corresponding to the second electrode of the first light emission control transistor passes through the first insulating layer, the second insulating layer and the third insulating layer.
  • the second via hole is electrically connected to the first connection electrode in the source-drain metal layer, the first connection electrode is electrically connected to the second electrode of the first light emission control transistor, and the first connection electrode It is electrically connected to the first electrode of the light emitting element through the first via hole.
  • the orthographic projection of the first via hole on the base substrate is located on the base substrate of the scan signal line between the orthographic projection on the substrate and the orthographic projection of the first light-emitting control signal line on the base substrate.
  • the first voltage line includes a first sub-voltage line and a second sub-voltage line, and the first sub-voltage line and the second sub-voltage line are electrically connected , the first sub-voltage line extends along the second direction, and the second sub-voltage line extends along the first direction.
  • the pixel circuits of the plurality of sub-pixels are arranged in an array along the first direction and the second direction.
  • the initial signal line includes a first sub-initial signal line and a second sub-initial signal line, and the first sub-initial signal line extends along the first direction,
  • the second sub-initial signal line extends along the second direction, the first sub-initial signal line and the second sub-initial signal line are electrically connected,
  • the data line extends along the second direction, the The first sub-voltage line, the data line and the second sub-initial signal line are located on the same layer, and the data line, the first sub-voltage line and the second sub-initial signal line are along the first direction are arranged, and in the first direction, the first sub-voltage line is located between the data line and the second sub-initial signal line.
  • the plurality of sub-pixels includes a plurality of sub-pixel pairs, the plurality of sub-pixel pairs are arranged in an array along the first direction and the second direction, and each sub-pixel For including two sub-pixels adjacent in the first direction, the pixel circuits of the two sub-pixels are mirror-symmetrical along an axis of symmetry parallel to the second direction.
  • the initial signal line includes a first sub-initial signal line and a second sub-initial signal line, and the first sub-initial signal line extends along the first direction,
  • the second sub-initial signal line extends along the second direction, the first sub-initial signal line and the second sub-initial signal line are electrically connected,
  • the data line extends along the second direction, the The first sub-voltage line, the data line and the second sub-initial signal line are located on the same layer, and the data line, the first sub-voltage line and the second sub-initial signal line are along the first direction are arranged, and in the first direction, the data line is located between the first sub-voltage line and the second sub-initial signal line.
  • the two sub-pixel pairs of the two sub-pixel pairs are in the first
  • the pixel circuits of the two sub-pixels adjacent to each other in the direction are electrically connected to the same first sub-voltage line.
  • the shape of the first light-emitting control signal line is a curved shape or a linear shape.
  • the first direction and the second direction are perpendicular to each other.
  • Some embodiments of the present disclosure further provide a display panel including the display substrate according to any one of the above embodiments.
  • FIG. 1 is a schematic block diagram of a display substrate according to some embodiments of the present disclosure
  • FIG. 2A is a schematic structural diagram of a pixel circuit provided by some embodiments of the present disclosure.
  • 2B is a circuit timing diagram of a pixel circuit according to some embodiments of the present disclosure.
  • FIG. 3 is a schematic layout diagram of a pixel circuit according to some embodiments of the present disclosure.
  • 4A-4M are schematic layout diagrams of various structural layers of a pixel circuit according to some embodiments of the present disclosure.
  • 4N is a schematic structural diagram of a source-drain metal layer according to other embodiments of the present disclosure.
  • FIG. 40 is a schematic structural diagram of a planarization layer provided by other embodiments of the present disclosure.
  • 4P is a schematic diagram of the stacking positional relationship of an active semiconductor layer, a first conductive layer, a second conductive layer, a third insulating layer, a source-drain metal layer, and a planarization layer provided by other embodiments of the present disclosure;
  • 5A is a schematic diagram of a cross-sectional structure at line A in FIG. 4M;
  • 5B is a schematic diagram of the cross-sectional structure at line B in FIG. 4M;
  • 6A-6M are schematic layout diagrams of various structural layers of a pixel circuit according to other embodiments of the present disclosure.
  • FIG. 7A is a schematic diagram of the cross-sectional structure at the line A' in FIG. 6M;
  • FIG. 7B is a schematic diagram of the cross-sectional structure at the line B' in FIG. 6M;
  • FIG. 8 is a schematic structural diagram of a first conductive layer provided by other embodiments of the present disclosure.
  • FIG. 9 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure.
  • the display substrate includes: a base substrate and a plurality of sub-pixels disposed on the base substrate, a first voltage line, a data line, a scan signal line, a first light emission The control signal line and the second light-emitting control signal line, each sub-pixel includes a pixel circuit and a light-emitting element
  • the pixel circuit includes: a driving sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit and a data writing sub-circuit
  • the first A light-emitting control sub-circuit is electrically connected to the first end of the driving sub-circuit, the first electrode of the light-emitting element and the first light-emitting control signal line, and is configured to control the first light-emitting control signal on the first light-emitting control signal line Under the control, the connection between the first end of the driving sub-circuit and the first electrode of the
  • Two light-emitting control signal lines are configured to control the connection between the second end of the driving sub-circuit and the first voltage line to be turned on or off under the control of the second light-emitting control signal on the second light-emitting control signal line
  • the data writing sub-circuit is electrically connected to the second end of the driving sub-circuit, the data line and the scanning signal line, and is configured to transmit the data voltage on the data line to the driving under the control of the scanning signal on the scanning signal line
  • the second end of the sub-circuit; the first light-emitting control signal line, the scanning signal line and the second light-emitting control signal line extend along the first direction, and are arranged along the second direction that is not parallel to the first direction, in the second direction , the scanning signal line is located between the first light-emitting control signal line and the second light-emitting control signal line.
  • the display substrate by extending the first light emitting control signal line, the scanning signal line and the second light emitting control signal line along the first direction, and arranging them in sequence along the second direction, the wiring can be reduced and the light transmission space can be increased , so that the photosensitive element under the pixel circuit can better photosensitive.
  • the display substrate has a simple structure, is easy to design and manufacture, and has a low cost.
  • FIG. 1 is a schematic block diagram of a display substrate provided by some embodiments of the present disclosure
  • FIG. 2A is a schematic structural diagram of a pixel circuit provided by some embodiments of the present disclosure
  • FIG. 2B is a schematic diagram of a pixel provided by some embodiments of the present disclosure The circuit timing diagram of the circuit.
  • a display substrate 100 provided by an embodiment of the present disclosure includes a base substrate 10 , a plurality of sub-pixels 12 , first voltage lines, data lines, scan signal lines, and a plurality of sub-pixels 12 disposed on the base substrate 10 .
  • a light-emitting control signal line and a second light-emitting control signal line are shown in FIG. 1 .
  • FIG. 1 does not show the first voltage line, the data line, the scan signal line, the first light emission control signal line and the second light emission control signal line.
  • the display substrate 100 may be applied to a display panel, such as an Active Matrix Organic Light Emitting Diode (AMOLED) display panel and the like.
  • the display substrate 100 may be an array substrate.
  • the base substrate 10 may be a flexible substrate or a rigid substrate.
  • the base substrate 10 may be made of glass, plastic, quartz or other suitable materials, which are not limited by the embodiments of the present disclosure.
  • each sub-pixel 12 includes a light-emitting element 121 and a pixel circuit 120 , and the light-emitting element 121 is located on a side of the pixel circuit 120 away from the base substrate 10 .
  • the pixel circuit 120 is configured to drive the light-emitting element 121 to emit light.
  • the pixel electrode and its working principle will be described below with reference to FIG. 2A and FIG. 2B .
  • the pixel circuit 120 includes a driving subcircuit 200 , a first light emission control subcircuit 210 , a second light emission control subcircuit 220 and a data writing subcircuit 230 .
  • the first light emission control sub-circuit 210 is electrically connected to the first end of the driving sub-circuit 200, the first electrode of the light-emitting element 121 and the first light emission control signal line EM1, and is configured to Under the control of the first light-emitting control signal on the light-emitting control signal line EM1, the connection between the first end of the driving sub-circuit 200 and the first end of the light-emitting element 121 is controlled to be turned on or off.
  • the second lighting control sub-circuit 220 is electrically connected to the second terminal of the driving sub-circuit 200, the first voltage line VDD and the second lighting control signal line EM2, and is configured to Under the control of the second lighting control signal on the signal line EM2, the connection between the second end of the driving sub-circuit 200 and the first voltage line VDD is controlled to be turned on or off.
  • the data writing subcircuit 230 is electrically connected to the second end of the driving subcircuit 200, the data line Vda and the scan signal line Ga, and is configured to control the scan signal on the scan signal line Ga Next, the data voltage on the data line Vda is transmitted to the second terminal of the driving sub-circuit 200 .
  • the second electrode of the light emitting element 121 is electrically connected to the second voltage line VSS.
  • the light emitting element 121 may be a light emitting diode or the like.
  • the light-emitting diode may be a micro light-emitting diode (Micro Light Emitting Diode, Micro LED), an organic light-emitting diode (Organic Light Emitting Diode, OLED), or a quantum dot light-emitting diode (Quantum Dot Light Emitting Diodes, QLED) and the like.
  • the light-emitting element 121 is configured to receive a light-emitting signal (for example, a driving current) during operation, and emit light with an intensity corresponding to the light-emitting signal.
  • a light-emitting signal for example, a driving current
  • the light emitting element 121 may include a first electrode, a second electrode, and a light emitting layer disposed between the first electrode and the second electrode.
  • the first electrode of the light emitting element 121 may be an anode
  • the second electrode of the light emitting diode may be a cathode.
  • the light-emitting layer of the light-emitting element may include the electroluminescent layer itself and other common layers on both sides of the electroluminescent layer, for example, a hole injection layer, a hole transport layer, Electron injection layer and electron transport layer, etc.
  • the light-emitting element 121 has an emission threshold voltage, and emits light when the voltage between the first electrode and the second electrode of the light-emitting element 121 is greater than or equal to the emission threshold voltage.
  • the specific structure of the light-emitting element 121 can be designed and determined according to the actual application environment, which is not limited herein.
  • the pixel circuit 120 further includes a storage capacitor Cst, the first electrode plate CC1 of the storage capacitor Cst is electrically connected to the control terminal of the driving sub-circuit 200, and the second electrode plate CC2 of the storage capacitor Cst is electrically connected to the first electrode plate CC2 of the storage capacitor Cst.
  • a voltage line VDD A voltage line
  • the display substrate 100 further includes a reset signal line Rt and an initial signal line Vinit disposed on the base substrate 10 .
  • the pixel circuit 120 also includes a reset subcircuit 240 and a threshold compensation subcircuit 250 .
  • the reset sub-circuit 240 is electrically connected to the control terminal of the driving sub-circuit 200, the initial signal line Vinit, the first light emission control signal line EM1 and the reset signal line Rt, and is configured to be connected between the first light emission control signal and the reset signal line Rt Under the control of the reset control signal on the Vinit, the initial voltage on the initial signal line Vinit is transmitted to the control terminal of the driving sub-circuit 200 .
  • the threshold compensation sub-circuit 250 is electrically connected to the control terminal and the first terminal of the driving sub-circuit 200 and the reset signal line Rt, and is configured to control the driving sub-circuit 200 under the control of the reset control signal on the reset signal line Rt
  • the connection between the first end of the drive sub-circuit 200 and the control end of the drive sub-circuit 200 is turned on or off.
  • the threshold compensation sub-circuit 250 is configured to is turned on under control, and at the same time, the first lighting control sub-circuit 210 is turned on under the control of the first lighting control signal, so that the initial voltage can be transmitted to the light-emitting element 121 via the threshold compensation sub-circuit 250 and the first lighting control sub-circuit 210 to initialize the first electrode of the light-emitting element 121 .
  • the initial voltage is transmitted to the control terminal of the driving sub-circuit 200 via the reset sub-circuit 240, and the initial voltage is transmitted via the reset sub-circuit 240, the threshold compensation sub-circuit 250 and the
  • the first light-emitting control sub-circuit 210 is transmitted to the first electrode of the light-emitting element 121 , so that the control terminal of the driving sub-circuit 200 and the first electrode of the light-emitting element 121 can be initialized at the same time.
  • the driving sub-circuit 200 includes the driving transistor T3, the control terminal of the driving sub-circuit 200 includes the gate of the driving transistor T3, the first terminal of the driving sub-circuit 20 includes the first electrode of the driving transistor T3, and the driving The second terminal of the sub-circuit 20 includes the second terminal of the drive transistor T3.
  • the gate of the driving transistor T3 is electrically connected to the first node N1, the second pole of the driving transistor T3 is electrically connected to the second node N2, and the first pole of the driving transistor T3 is electrically connected to the third node N3.
  • the first light-emitting control sub-circuit 210 includes a first light-emitting control transistor T6, the gate of the first light-emitting control transistor T6 is electrically connected to the first light-emitting control signal line EM1, and the first electrode of the first light-emitting control transistor T6 is electrically connected to the third node N3 is electrically connected to the first electrode of the driving transistor T3, the second electrode of the first light-emitting control transistor T6 is electrically connected to the fourth node N4, and the first electrode of the light-emitting element 121 is electrically connected to the fourth node N4, that is , the second electrode of the first light-emitting control transistor T6 is electrically connected to the first electrode of the light-emitting element 121 .
  • the second light-emitting control sub-circuit 220 includes a second light-emitting control transistor T5, the gate of the second light-emitting control transistor T5 is electrically connected to the second light-emitting control signal line EM2, and the first electrode of the second light-emitting control transistor T5 is electrically connected to the second node N2 is electrically connected to the second pole of the driving transistor T3, and the second pole of the second light-emitting control transistor T5 is electrically connected to the first voltage line VDD.
  • the data writing sub-circuit 230 includes a data writing transistor T4, the gate of the data writing transistor T4 is electrically connected to the scanning signal line Ga, the first electrode of the data writing transistor T4 is electrically connected to the data line Vda, and the gate of the data writing transistor T4 is electrically connected to the data line Vda.
  • the second pole is electrically connected to the second node N2, that is, electrically connected to the second pole of the driving transistor T3.
  • the reset sub-circuit 240 includes a first reset transistor T1 and a second reset transistor T7, the gate of the first reset transistor T1 is electrically connected to the reset signal line Rt, the first electrode of the first reset transistor T1 is electrically connected to the initial signal line Vinit, and the first reset transistor T1 is electrically connected to the initial signal line Vinit.
  • the second pole of a reset transistor T1 is electrically connected to the first pole of the second reset transistor T7; the gate of the second reset transistor T7 is electrically connected to the first light-emitting control signal line EM1, and the second pole of the second reset transistor T7 is electrically connected to the first node N1, that is, electrically connected to the gate of the driving transistor T3.
  • the threshold compensation sub-circuit 250 includes a threshold compensation transistor T2, the gate of the threshold compensation transistor T2 is electrically connected to the reset signal line Rt, and the first pole of the threshold compensation transistor T2 is electrically connected to the third node N3, that is, electrically connected to the third node of the driving transistor T3.
  • One pole, the second pole of the threshold compensation transistor T2 is electrically connected to the first node N1, that is, electrically connected to the gate of the driving transistor T3.
  • the first reset transistor T1 and the threshold compensation transistor T2 are both dual-gate transistors, so that the leakage current of the first reset transistor T1 and the threshold compensation transistor T2 electrically connected to the gate of the driving transistor T3 can be made Smaller, to ensure that the voltage of the gate of the driving transistor T3 is stable.
  • one of the voltage output by the first voltage line VDD and the voltage output by the second voltage line VSS is a high voltage, and the other is a low voltage.
  • the voltage output by the first voltage line VDD is a constant first voltage, and the first voltage is a positive voltage
  • the voltage output by the second voltage line VSS is a constant second voltage
  • the second voltage is a negative voltage or the like.
  • the second voltage line VSS may be grounded.
  • transistors can be divided into N-type transistors and P-type transistors.
  • the embodiments of the present disclosure take the transistors as P-type transistors (eg, P-type MOS transistors) as an example to illustrate the present disclosure in detail.
  • the two reset transistors T7 and the like can all be P-type transistors, so that the fabrication process can be reduced.
  • the transistors in the embodiments of the present disclosure are not limited to P-type transistors, and those skilled in the art can also use N-type transistors (eg, N-type MOS transistors) to implement the transistors in the embodiments of the present disclosure according to actual application environments.
  • the function is not limited here.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors, etc. .
  • the source and drain of the transistor may be symmetrical in structure, so the source and drain of the transistor may be indistinguishable in physical structure.
  • one of the gate electrodes is directly described as the first electrode and the other electrode is the second electrode.
  • the first and second poles are interchangeable as required.
  • the initial voltage V i output by the initial signal line Vinit and the voltage V s output by the second voltage line VSS may satisfy the following formula: V i -V s ⁇ VEL, so that it is possible to
  • the light-emitting element 121 is prevented from emitting light in a non-light-emitting stage (eg, an initialization stage p1 to be described below).
  • VEL represents the light emission threshold voltage of the light emitting element 121 .
  • Rt represents the reset control signal output by the reset signal line Rt
  • Ga represents the scan signal output by the scan signal line Ga
  • EM1 represents the first light-emitting control signal output by the first light-emitting control signal line EM1
  • EM2 represents the first light-emitting control signal output by the first light-emitting control signal line EM1.
  • the second lighting control signal output by the second lighting control signal line EM2.
  • the reference signs Rt, Ga, EM1, EM2, Vda, and VDD represent both signal lines and signals on the signal lines.
  • the working process of a pixel circuit in one display frame may include: initialization stage p1, data writing stage p2, first buffer stage p3, second buffer stage p4, and light-emitting stage p5.
  • the reset control signal Rt and the first light emission control signal EM1 are at a low level, and the second light emission control signal EM2 and the scan signal Ga are at a high level. Therefore, the first reset transistor T1 is at a low level of the reset control signal Rt. It is turned on under the control of the low level, and the second reset transistor T7 is also turned on under the control of the low level of the first light-emitting control signal EM1, so that the initial voltage V i output by the initial signal line Vinit can pass through the conduction.
  • the first reset transistor T1 and the second reset transistor T7 are provided to the gate of the driving transistor T3, that is, the third node N3, so that the voltage of the gate of the driving transistor T3 is the initial voltage Vi , and the gate of the driving transistor T3 is realized. to initialize.
  • the threshold compensation transistor T2 is turned on under the control of the low level of the reset control signal Rt, and the first light-emitting control transistor T6 is also turned on under the control of the low level of the first light-emitting control signal EM1, so that the initial signal
  • the initial voltage V i output from the line Vinit may be supplied to the first electrode of the light emitting element 121 through the turned-on threshold compensation transistor T2 and the first light emission control transistor T6 to initialize the first electrode of the light emitting element 121 .
  • the second light emission control transistor T5 is turned off under the control of the high level of the second light emission control signal EM2, and the data writing transistor T4 is turned off under the control of the high level of the scan signal Ga.
  • the reset control signal Rt and the scan signal Ga are at a low level, and the first light emission control signal EM1 and the second light emission control signal EM2 are at a high level, so that the data writing transistor T4 is at a low level at the scan signal Ga. It is turned on under the control of the low level, so as to provide the data voltage Vda on the data line Vda to the second pole of the driving transistor T3, that is, the second node N2, so that the voltage of the second pole of the driving transistor T3 is the data voltage Vda.
  • the threshold compensation transistor T2 is turned on under the control of the low level of the reset control signal Rt, which can make the driving transistor T3 form a diode connection, so that the voltage Vda of the second pole of the driving transistor T3 charges the gate of the driving transistor T3 Until the voltage of the gate of the driving transistor T3 becomes Vda+Vth, the voltage Vda+Vth of the gate of the driving transistor T3 is stored by the storage capacitor Cst.
  • the second reset transistor T7 and the first light emission control transistor T6 are turned off under the control of the high level of the first light emission control signal EM1, and the second light emission control transistor T5 is turned off under the control of the high level of the second light emission control signal EM2.
  • the scan signal Ga is at a low level
  • the reset control signal Rt, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at a high level
  • the data writing transistor T4 is at a low level at the scan signal Ga is turned on under the control of the low level, so as to provide the data voltage Vda on the data line Vda to the second pole of the driving transistor T3, so that the voltage of the second pole of the driving transistor T3 continues to be the data voltage Vda.
  • the first reset transistor T1 and the threshold compensation transistor T2 are turned off under the control of the high level of the reset control signal Rt, and the second reset transistor T7 and the first light emission control transistor T6 are under the control of the high level of the first light emission control signal EM1 When turned off, the second light emitting control transistor T5 is turned off under the control of the high level of the second light emitting control signal EM2.
  • the data writing transistor T4 can be continuously turned on, so as to make the charging more sufficient.
  • the second light-emitting control signal EM2 is at a low level
  • the reset control signal Rt the first light-emitting control signal EM1 and the scan signal Ga are at a high level
  • the second light-emitting control transistor T5 is at a second
  • the light-emitting control signal EM2 is turned on under the control of the high level, so that the second light-emitting control transistor T5 can provide the first voltage VDD output by the first voltage line VDD to the second pole of the driving transistor T3, so that the driving transistor T3
  • the voltage of the second pole is the first voltage VDD. In this way, the second electrode of the driving transistor T3 can be precharged through the first voltage line VDD.
  • the first reset transistor T1 and the threshold compensation transistor T2 are turned off under the control of the high level of the reset control signal Rt, and the second reset transistor T7 and the first light emission control transistor T6 are under the control of the high level of the first light emission control signal EM1 Off, the data writing transistor T4 is turned off under the control of the high level of the scan signal Ga.
  • the first light-emitting control transistor T6 can be controlled to be turned off, so that the voltage of the gate of the driving transistor T3 can be further stabilized. That is, the current generated by the driving transistor T3 is further stabilized before being supplied to the light-emitting element 121, so that the light-emitting stability of the light-emitting element 121 can be further improved.
  • the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at a low level, and the reset control signal Rt and the scanning signal Ga are at a high level, so that the second light-emitting control transistor T5 is in the second light-emitting control It is turned on under the control of the low level of the signal EM2, so that the second light-emitting control transistor T5 can provide the first voltage VDD output by the first voltage line VDD to the second pole of the driving transistor T3, so that the second The voltage of the pole is the first voltage VDD. At this time, the voltage of the second pole of the driving transistor T3 is the first voltage VDD.
  • the voltage of the gate of the driving transistor T3 is Vda+Vth, which can make the driving transistor T3 in a saturated state, thereby
  • the first light-emitting control transistor T6 is turned on under the control of the low level of the first light-emitting control signal EM1, so that the first light-emitting control transistor T6 can conduct the first electrode of the driving transistor T3 with the first electrode of the light-emitting element 121, Thus, the driving current Ids flows into the light-emitting element 121 to drive the light-emitting element 121 to emit light.
  • the first reset transistor T1 and the threshold compensation transistor T2 are turned off under the control of the high level of the reset control signal Rt, and the data writing transistor T4 is turned off under the control of the high level of the scan signal Ga.
  • circuit timing diagram shown in FIG. 2B provided by the present disclosure is only schematic, and the specific timing of the pixel circuit may be set according to the actual application scenario, which is not specifically limited in the present disclosure.
  • FIG. 3 is a schematic layout diagram of a pixel circuit according to some embodiments of the present disclosure.
  • the display substrate 100 may include an active semiconductor layer, a first conductive layer, a second conductive layer, a source-drain metal layer and an anode layer, for example, each pixel circuit 120 Including an active semiconductor layer, a first conductive layer, a second conductive layer, a source-drain metal layer and an anode layer, for example, various elements of the pixel circuit 120 (transistors T1-T7 and storage capacitors, etc.) and various signal lines are provided in the active semiconductor layer, the first conductive layer, the second conductive layer, the source-drain metal layer and the anode layer.
  • the active semiconductor layer is located between the base substrate 10 and the first conductive layer
  • the first conductive layer is located between the active semiconductor layer and the second conductive layer
  • the second conductive layer is located between the first conductive layer and the source-drain metal layer
  • the source-drain metal layer is located between the second conductive layer and the anode layer.
  • FIG. 3 only shows the stacking positional relationship among the active semiconductor layer, the first conductive layer, the second conductive layer, and the source-drain metal layer in one pixel circuit.
  • the first light emission control signal line EM1 , the scanning signal line Ga and the second light emission control signal line EM2 extend along the first direction X, and are arranged in the second direction Y which is not parallel to the first direction X
  • the scanning signal line Ga is located between the first light emission control signal line EM1 and the second light emission control signal line EM1.
  • first direction X and the second direction Y are perpendicular to each other.
  • the first direction X may be parallel to the horizontal direction
  • the second direction Y may be parallel to the vertical direction.
  • the orthographic projection of the first light emission control signal line EM1 on the base substrate 10 and the orthographic projection of the second light emission control signal line EM2 on the base substrate 10 are located in the memory
  • the second electrode plates CC2 of the capacitor Cst are on both sides of the orthographic projection on the base substrate 10 .
  • the orthographic projection of the scanning signal line Ga on the base substrate and the orthographic projection of the second light-emitting control signal line EM2 on the base substrate are located on the second electrode plate CC2 of the storage capacitor Cst on the substrate. Both sides of the orthographic projection on the substrate. That is to say, the orthographic projection of the first light emission control signal line EM1 on the base substrate and the orthographic projection of the scanning signal line Ga on the base substrate are located in the orthographic projection of the second electrode plate CC2 of the storage capacitor Cst on the base substrate On the same side, such as the upper side in FIG.
  • the orthographic projection of the second light-emitting control signal line EM2 on the base substrate is located on the other side of the orthographic projection of the second electrode plate CC2 of the storage capacitor Cst on the base substrate, For example, it is the lower side in FIG. 3 .
  • the reset signal line Rt extends along the first direction X, and in the second direction Y, the reset signal line Rt is located on the side of the first light emission control signal line EM1 away from the scanning signal line Ga, that is, That is, in the second direction, the orthographic projection of the first light emission control signal line EM1 on the base substrate 10 is located between the orthographic projection of the reset signal line Rt on the base substrate 10 and the orthographic projection of the scanning signal line Ga on the base substrate 10 between orthographic projections.
  • the reset signal line Rt, the first light emission control signal line EM1 , the scan signal line Ga and the second light emission control signal line EM2 are sequentially arranged.
  • the present disclosure is not limited thereto, in other embodiments, in the second direction Y, from bottom to top, the reset signal line Rt, the first light emission control signal line EM1, the scan signal line Ga and the second light emission control signal line EM2 in order.
  • each rectangular solid line frame in FIG. 3 shows each portion where the first conductive layer overlaps with the active semiconductor layer.
  • the reset signal line Rt, the first light emission control signal line EM1, the scan signal line Ga and the second light emission control signal line EM2 are all located in the first conductive layer.
  • the active semiconductor layers in each rectangular solid line frame are respectively the active layers of the transistors T1-T7.
  • the reset signal line Rt overlaps the active semiconductor layers to define the active layer and threshold compensation of the first reset transistor T1.
  • the active layer of the transistor T2 overlaps with the active semiconductor layer to define the active layer of the first light emission control transistor T6 and the active layer of the second reset transistor T7, the scan signal line Ga and the active layer of the second reset transistor T7.
  • the active semiconductor layers overlap to define the active layer of the data writing transistor T4, the second light emitting control signal line EM2 overlaps the active semiconductor layer to define the active layer of the second light emitting control transistor T5, and the storage capacitor Cst
  • the first electrode plate (not shown) of T3 overlaps the active semiconductor layer to define the active layer of the driving transistor T3.
  • the initial signal line Vinit includes a first sub-initial signal line Vinit1 and a second sub-initial signal line Vinit2, the first sub-initial signal line Vinit1 extends along the first direction X, and the second sub-initial signal line Vinit2 Extending along the second direction Y, the first sub-initial signal line Vinit1 and the second sub-initial signal line Vinit2 are electrically connected.
  • the initial signal lines Vinit are wired in a grid on the base substrate and have a network structure, that is, on the entire display substrate, the first sub-initial signal lines Vinit1 and the second sub-initial signal lines Vinit2 are arranged in a grid shape, so that The resistance of the initial signal line Vinit is small and the voltage drop (IR drop) is low, so that the distribution of the initial signal line Vinit on the substrate is more uniform, which can improve the stability of the initial voltage provided by the initial signal line Vinit and ensure initialization.
  • the first voltage line VDD includes a first sub-voltage line VDD1 and a second sub-voltage line VDD2, the first sub-voltage line VDD1 and the second sub-voltage line VDD2 are electrically connected, and the first sub-voltage line VDD1 Extending along the second direction Y, the second sub-voltage line VDD2 extends along the first direction X.
  • the first voltage line VDD is wired in a grid on the base substrate, that is, on the entire display substrate, the first sub-voltage line VDD1 and the second sub-voltage line VDD2 are arranged in a grid shape, so that the The resistance is smaller and the voltage drop is lower, thereby improving the stability of the power supply voltage provided by the first voltage line VDD.
  • the second sub-voltage line VDD2 and the second electrode plate CC2 of the storage capacitor Cst are integrally formed.
  • the data line Vda, the first sub-voltage line VDD1 and the second sub-initial signal line Vinit2 all extend along the second direction Y and are arranged along the first direction X.
  • the first sub-voltage line VDD1 is located between the data line Vda and the second sub-initial signal line Vinit2 .
  • 4A-4M are schematic layout diagrams of various structural layers of a pixel circuit according to some embodiments of the present disclosure.
  • the pixel circuits of the plurality of sub-pixels 12 are arranged in an array along the first direction X and the second direction Y.
  • the following describes the positional relationship of each element of the pixel circuit on the base substrate in this embodiment with reference to FIGS. 4A-4M .
  • the example shown in FIGS. 4A-4M takes the pixel circuit 120 shown in FIG. 2A as an example.
  • the part represented by the rectangular dotted-line box is an area corresponding to one pixel circuit 120
  • FIGS. 4A-4M show the layout of the area corresponding to eight pixel circuits arranged in two rows and four columns.
  • each pixel circuit 120 may include an active semiconductor layer 310, a first insulating layer (not shown), a first conductive layer 320, a second insulating layer (not shown), a first insulating layer (not shown), a Two conductive layers 330 , a third insulating layer 410 , a source-drain metal layer 340 , a planarization layer 420 and an anode layer 350 .
  • Active semiconductor layer 310, first insulating layer (not shown), first conductive layer 320, second insulating layer (not shown), second conductive layer 330, third insulating layer 410, source-drain metal layer 340 , the planarization layer 420 and the anode layer 350 are sequentially disposed on the base substrate.
  • the active semiconductor layer 310 is located between the base substrate and the first conductive layer 320
  • the first conductive layer 320 is located between the active semiconductor layer 310 and the second conductive layer 330
  • the second conductive layer 330 is located between the first conductive layer 320 and the source-drain metal layer 340
  • the planarization layer 420 is located on the side of the source-drain metal layer 340 away from the base substrate, that is, on the source-drain metal layer
  • the anode layer 350 is located on the side of the planarization layer 420 away from the source-drain metal layer 340 .
  • the first insulating layer is located between the active semiconductor layer 310 and the first conductive layer 320
  • the second insulating layer is located between the first conductive layer 320 and the second conductive layer 330
  • the third insulating layer 410 is located between the second conductive layer 330 and the second conductive layer 330. between the source and drain metal layers 340 .
  • the first insulating layer, the second insulating layer, the third insulating layer 410 and the planarization layer 420 are all made of insulating materials, such as inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, or other suitable materials.
  • the preparation materials of the first insulating layer, the second insulating layer, the third insulating layer 410 and the planarizing layer 420 may be the same, or, the materials of the first insulating layer, the second insulating layer, the third insulating layer 410 and the planarizing layer 420 may be the same.
  • the preparation materials of at least some of the layers are different, which is not limited in the present disclosure.
  • FIG. 4A shows the active semiconductor layers 310 of the plurality of pixel circuits 120 , and the active semiconductor layers 310 may be formed on the base substrate by patterning a semiconductor material.
  • the active semiconductor layer 310 can be used to fabricate the active layer of the driving transistor T3, the active layer of the first reset transistor T1, the active layer of the threshold compensation transistor T2, the active layer of the data writing transistor T4, and the second light-emitting control transistor.
  • the active layer of T5, the active layer of the first light emission control transistor T6, the active layer of the second reset transistor T7, the active layer of each transistor may include a source region, a drain region and a source region and a drain The channel region between regions, the channel region is used to form the channel of the transistor.
  • each solid rectangular box in FIG. 4A shows the active layer of each transistor T1-T7.
  • the active layers of the transistors T1-T7 are arranged on the same layer, and the active layers of the first reset transistor T1 and the active layers of the second reset transistor T7 are integrally arranged, and the active layer of the threshold compensation transistor T2 is The layer and the active layer of the first light emitting control transistor T6 are integrally arranged, and the active layer of the driving transistor T3, the active layer of the data writing transistor T4 and the active layer of the second light emitting control transistor T5 are integrally arranged.
  • the active layer of the first reset transistor T1, the active layer of the threshold compensation transistor T2, the active layer of the data writing transistor T4, and the first light emission control transistor T6 The active layer of the second reset transistor T7 and the active layer of the second reset transistor T7 are located on the first side of the active layer of the driving transistor T3, for example, the upper side shown in FIG. 4A; the active layer of the second light-emitting control transistor T5 is located on the driving The second side of the active layer of transistor T3, eg, the lower side shown in FIG. 4A.
  • the active semiconductor layer 310 can be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like.
  • the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the doped source region corresponds to the source of the transistor (eg, the first electrode of the transistor), and the doped drain region corresponds to the drain of the transistor (eg, the second electrode of the transistor).
  • a first insulating layer (not shown) is formed on the side of the above-mentioned active semiconductor layer 310 away from the base substrate for protecting the above-mentioned active semiconductor layer 310 .
  • 4B shows the first conductive layer 320 of the pixel circuit 120 , the first conductive layer 320 is disposed on the side of the first insulating layer away from the active semiconductor layer 310 so as to be insulated from the active semiconductor layer 310 .
  • each rectangular solid line frame in FIG. 4A shows each portion where the first conductive layer 320 and the active semiconductor layer 310 overlap.
  • the reset signal line Rt, the first light emission control signal line EM1 , the scan signal line Ga, and the second light emission control signal line EM2 are all located in the first conductive layer 320 .
  • the first conductive layer 320 may further include the first electrode plate CC1 of the storage capacitor Cst, the gate of the first reset transistor T1, the gate of the threshold compensation transistor T2, the gate of the data writing transistor T4, the second light emission control The gate of the transistor T5, the gate of the first light emission control transistor T6, the gate of the second reset transistor T7, and the gate of the driving transistor T3.
  • the reset signal line Rt, the first light emission control signal line EM1 , the scanning signal line Ga, and the second light emission control signal line EM2 all extend substantially along the first direction X.
  • the reset signal line Rt, the first light emission control signal line EM1, the scanning signal line Ga, and the second light emission control signal line EM2 are arranged in sequence. That is, the first light emission control signal line EM1 is located between the reset signal line Rt and the scan signal line Ga, and the scan signal line Ga is located between the first light emission control signal line EM1 and the second light emission control signal line EM2.
  • the shape of the reset signal line Rt and the shape of the scanning signal line Ga are substantially straight, and the shape of the first emission control signal line EM1 and the shape of the second emission control signal line EM2 are substantially curved shape, for example, the shape of a wavy line.
  • the reset signal line Rt is electrically connected to the gate of the first reset transistor T1 and the gate of the threshold compensation transistor T2 for controlling the first reset transistor T1 and the threshold compensation transistor T2 to be turned on or off;
  • the first lighting control signal The line EM1 is electrically connected to the gate of the first light-emitting control transistor T6 and the gate of the second reset transistor T7, so as to control the first light-emitting control transistor T6 and the second reset transistor T7 to be turned on or off;
  • the scanning signal line Ga is electrically connected.
  • the second light-emitting control signal line EM2 is electrically connected to the gate of the second light-emitting control transistor T5 for controlling The second light-emitting control transistor T5 is turned on or off.
  • FIG. 4C is a schematic diagram of the stacking positional relationship between the active semiconductor layer 310 and the first conductive layer 320 .
  • the reset signal line Rt at least partially overlaps with the active layer of the first reset transistor T1 and the active layer of the threshold compensation transistor T2; the first light emission control signal line EM1 and the first The active layer of the light-emitting control transistor T6 and the active layer of the second reset transistor T7 at least partially overlap; the scanning signal line Ga and the active layer of the data writing transistor T4 at least partially overlap; the second light-emitting control signal line EM2 and The active layers of the second light emission control transistor T5 at least partially overlap.
  • the reset signal line Rt, the gate of the first reset transistor T1 and the gate of the threshold compensation transistor T2 are integrally provided, and the part of the reset signal line Rt overlapping with the active semiconductor layer 310 is the first reset transistor
  • the gate of T1 and the gate of the threshold compensation transistor T2; the first light-emitting control signal line EM1, the gate of the first light-emitting control transistor T6 and the gate of the second reset transistor T7 are integrally arranged, and the first light-emitting control signal line EM1
  • the part overlapping with the active semiconductor layer 310 is the gate of the first light-emitting control transistor T6 and the gate of the second reset transistor T7; the scanning signal line Ga and the gate of the data writing transistor T4 are integrally arranged, and the scanning signal line Ga
  • the part overlapping with the active semiconductor layer 310 is the gate of the data writing transistor T4; the second light-emitting control signal line EM2 and the gate of the second light-emitting control transistor T5 are integrally provided, and
  • the first electrode plate CC1 of the storage capacitor Cst is located between the second light emission control signal line EM2 and the scan signal line Ga.
  • the part of the active semiconductor layer 310 covered by the first electrode plate CC1 of the storage capacitor Cst of the first conductive layer 320 is the active part of the driving transistor T3 layer, and the shape of the active layer of the driving transistor T3 is the shape of the Chinese character "ji".
  • the active layer of the first reset transistor T1 is a reset active layer, that is, the first reset transistor T1 includes a reset active layer, and the reset active layer includes a first reset active layer part T11 and a second reset active layer part T12.
  • the orthographic projection of the second reset active layer portion T12 on the base substrate and the orthographic projection of the reset signal line Rt on the base substrate at least partially overlap.
  • the portion of the active semiconductor layer 310 covered by the reset signal line Rt of the first conductive layer 320 includes the second reset active layer portion T12,
  • the second reset active layer part T12 includes two parts spaced apart from each other, that is, the first reset transistor T1 is a double-gate transistor.
  • the first reset active layer portion T11 and the second reset active layer portion T12 generally form a U-shape as a whole, that is, the first reset transistor T1 is a U-shaped double-gate transistor.
  • the active layer of the threshold compensation transistor T2 is a compensation active layer, that is, the threshold compensation transistor T2 includes a compensation active layer, and the compensation active layer includes a first compensation active layer part T21 and a second compensation active layer part T22.
  • the orthographic projection of the second compensation active layer portion T22 on the base substrate and the orthographic projection of the reset signal line Rt on the base substrate at least partially overlap.
  • the portion of the active semiconductor layer 310 covered by the reset signal line Rt of the first conductive layer 320 includes the second compensation active layer portion T22,
  • the second compensation active layer part T22 includes two parts spaced apart from each other, that is, the threshold compensation transistor T2 is a double-gate transistor.
  • the first compensation active layer portion T21 and the second compensation active layer portion T22 generally form a U-shape as a whole, that is, the threshold compensation transistor T2 is a U-shape double-gate transistor.
  • the first reset active layer portion T11 and the first compensation active layer portion T21 are sequentially arranged in the first direction X, and the center of the first reset active layer portion T11 and the first compensation active layer portion T21 are arranged in sequence in the first direction X.
  • the center of a compensation active layer portion T21 is substantially located on the same straight line, and the straight line is parallel to the first direction X, for example.
  • the shape of the first reset active layer portion T11 and the shape of the first compensation active layer portion T21 are substantially the same.
  • the first reset transistor T1 includes two gates
  • the threshold compensation transistor T2 includes two gates.
  • the reset signal line Rt and the active semiconductor layer 310 are mutually overlapping to form four overlapping portions, the four overlapping portions being the two gates of the first reset transistor T1 and the two gates of the threshold compensation transistor T2 respectively.
  • the second reset active layer part T12 includes first and second subsections T121 and T122 spaced apart from each other
  • the second compensation active layer part T22 includes third subsections T221 and T122 spaced apart from each other Fourth subsection T222.
  • the first sub-section T121, the second sub-section T122, the third sub-section T221 and the fourth sub-section T222 are sequentially arranged in the first direction X
  • the center of the first sub-section T121, the center of the second sub-section T122 , the center of the third sub-portion T221 and the center of the fourth sub-portion T222 are substantially located on the same straight line, and the straight line is parallel to the first direction X, for example.
  • the length of the first subsection T121, the length of the second subsection T122, the length of the third subsection T221, and the length of the fourth subsection T222 are substantially equal.
  • the length of the first subsection T121 is slightly smaller than the length of the second subsection T122, and the length of the third subsection T221 is slightly smaller than the length of the fourth subsection T222.
  • the shape of the first subsection T121, the shape of the second subsection T122, the shape of the third subsection T221, and the shape of the fourth subsection T222 are all rectangular.
  • the part of the active semiconductor layer 310 covered by the first light-emitting control signal line EM1 of the first conductive layer 320 is the part of the first light-emitting control transistor T6
  • the active layer and the active layer of the second reset transistor T7, and the shape of the active layer of the first light emission control transistor T6 and the shape of the active layer of the second reset transistor T7 are both rectangular.
  • the portion of the active semiconductor layer 310 covered by the scanning signal line Ga of the first conductive layer 320 is the active layer of the data writing transistor T4, and
  • the shapes of the active layers of the data writing transistors T4 are all rectangular.
  • the part of the active semiconductor layer 310 covered by the second light-emitting control signal line EM2 of the first conductive layer 320 is the part of the second light-emitting control transistor T5
  • the active layer of the second light-emitting control transistor T5 is rectangular in shape.
  • the gate of the first reset transistor T1, the gate of the threshold compensation transistor T2, the gate of the data writing transistor T4, and the gate of the first light emission control transistor T6 and the gate of the second reset transistor T7 are located on the first side of the gate of the driving transistor T3, for example, the upper side shown in FIG. 4C; the gate of the second light-emitting control transistor T5 is located on the first side of the gate of the driving transistor T3. Two sides, eg, the lower side shown in Figure 4C.
  • FIG. 4E is a schematic diagram of the stacking positional relationship of the active semiconductor layer 310 , the first conductive layer 320 and the second conductive layer 330 .
  • a second insulating layer (not shown) is formed on the side of the first conductive layer 320 away from the first insulating layer to protect the first conductive layer 320 .
  • 4D shows the second conductive layer 330 of the pixel circuit 120.
  • the second conductive layer 330 is formed on the side of the second insulating layer away from the first conductive layer 320.
  • the second conductive layer 330 includes the second conductive layer of the storage capacitor Cst.
  • the first sub-initial signal line Vinit1 and the second sub-voltage line VDD2 both extend along the first direction X and are arranged along the second direction Y.
  • the storage capacitor Cst In the direction perpendicular to the base substrate, the storage capacitor Cst The first electrode plate CC1 and the second electrode plate CC2 of the storage capacitor Cst at least partially overlap to form the storage capacitor Cst.
  • the second sub-voltage line VDD2 is integrally formed with the second electrode plate CC2 of the storage capacitor Cst.
  • the second electrode plate CC2 of the storage capacitor Cst includes a conductive layer via hole h11, and the second electrode of the threshold compensation transistor T2 and the second electrode of the second reset transistor T7 pass through the conductive layer
  • the via hole h11 is electrically connected to the first electrode plate CC1 of the storage capacitor Cst, that is, the gate of the driving transistor DT.
  • the orthographic projection of the first reset active layer portion T11 on the base substrate and the orthographic projection of the initial signal line Vinit on the base substrate at least partially overlap, and the orthographic projection of the first compensation active layer portion T21 on the base substrate
  • the projection and the orthographic projection of the initial signal line Vinit on the base substrate at least partially overlap.
  • the initial signal line Vinit includes a first sub-initial signal line Vinit1 , the orthographic projection of the first reset active layer part T11 on the base substrate and the first compensation active layer part Vinit1 in The orthographic projections on the base substrate are all located within the orthographic projections of the first sub-initial signal line Vinit1 on the base substrate.
  • the portion of the active layer of the first reset transistor T1 that is not blocked by the reset signal line Rt and the unreset portion of the active layer of the threshold compensation transistor T2 are simultaneously shielded by the first sub-initial signal line Vinit1
  • the part shielded by the signal line Rt does not need to be shielded by a shielding layer, and at the same time, the wiring on the display substrate can be reduced and the cost can be reduced.
  • the first sub-initial signal line Vinit1 is used to perform the first sub-initial signal line Vinit1 on the part of the active layer of the first reset transistor T1 that is not blocked by the reset signal line Rt and the part of the active layer of the threshold compensation transistor T2 that is not blocked by the reset signal line Rt. Shading can make the first reset transistor T1 and the threshold compensation transistor T2 more stable.
  • FIG. 4G is a schematic diagram of the stacking positional relationship of the active semiconductor layer 310 , the first conductive layer 320 , the second conductive layer 330 and the third insulating layer 410 .
  • a third insulating layer 410 is formed on the side of the second conductive layer 330 away from the second insulating layer to protect the second conductive layer 330.
  • a plurality of insulating layer via holes h21 - h31 are formed in the third insulating layer 410 .
  • the plurality of insulating layer via holes h21-h31 correspond to one pixel circuit.
  • the insulating layer vias h21 penetrate through the third insulating layer 410 to expose a part of the first sub-initial signal line Vinit1; the insulating layer vias h22-27 and the insulating layer vias 30-31 penetrate through The first insulating layer, the second insulating layer and the third insulating layer 410 thereby expose a part of the active semiconductor layer 310; the insulating layer via hole h28 penetrates the third insulating layer 410 to expose a part of the second electrode plate CC2 of the storage capacitor Cst; The insulating layer via hole h29 penetrates the second insulating layer and the third insulating layer 410 to expose a part of the first electrode plate CC1 of the storage capacitor Cst.
  • the orthographic projection of the insulating layer via hole h29 on the base substrate is located within the orthographic projection of the conductive layer via hole h11 on the base substrate.
  • FIG. 4H shows the source-drain metal layer 340 of the pixel circuit 120 , and the source-drain metal layer 340 is disposed on the side of the third insulating layer 410 away from the second conductive layer 330 .
  • FIG. 4I is a schematic diagram illustrating the stacking positional relationship of the active semiconductor layer 310 , the first conductive layer 320 , the second conductive layer 330 , the third insulating layer 410 , and the source-drain metal layer 340 .
  • the source-drain metal layer 340 includes a data line Vda, a first sub-voltage line VDD1, a second sub-initial signal line Vinit2, a first pole fc1 of the first reset transistor T1, and a
  • One pole fc6 and the second pole sc6 and the second pole sc7 of the second reset transistor T7 the first connection electrode Co1, the second connection electrode Co2 and the third connection electrode Co3.
  • the first pole fc1 of the first reset transistor T1 is connected to the second sub-initial signal line Vinit2, for example, the first pole fc1 of the first reset transistor T1 is the second sub-initial signal line Vinit2 Part of the initial signal line Vinit2.
  • the first electrode fc1 of the first reset transistor T1 is connected to a source region or a drain region corresponding to the first reset transistor T1 in the active semiconductor layer 310 through an insulating layer via h22.
  • the first electrode fc2 of the threshold compensation transistor T2 and the first electrode fc6 of the first light emission control transistor T6 are the same electrode, and are connected to the same electrode through the insulating layer via h24 A source region or a drain region corresponding to the threshold compensation transistor T2 and the first light emission control transistor T6 in the source semiconductor layer 310 .
  • the second electrode sc2 of the threshold compensation transistor T2 is connected to a source region or a drain region corresponding to the threshold compensation transistor T2 in the active semiconductor layer 310 through an insulating layer via h23.
  • the first electrode fc2 of the threshold compensation transistor T2 and the first electrode fc6 of the first light emission control transistor T6 are part of the third connection electrode Co3.
  • the second electrode sc2 of the threshold compensation transistor T2 is a part of the second connection electrode Co2.
  • the second electrode sc6 of the first light emission control transistor T6 is connected to the first connection electrode Co1, for example, the second electrode sc6 of the first light emission control transistor T6 is a part of the first connection electrode Co1.
  • the second electrode sc6 of the first light emission control transistor T6 is connected to a source region or a drain region corresponding to the first light emission control transistor T6 in the active semiconductor layer 310 through an insulating layer via h27.
  • the first electrode fc4 of the data writing transistor T4 is connected to the data line Vda, for example, the first electrode fc4 of the data writing transistor T4 is a part of the data line Vda, and the data The first electrode fc4 of the writing transistor T4 is connected to a source region or a drain region corresponding to the data writing transistor T4 in the active semiconductor layer 310 through an insulating layer via h25.
  • the first electrode fc5 of the second light-emitting control transistor T5 is connected to the first sub-voltage line VDD1, for example, the first electrode fc5 of the second light-emitting control transistor T5 is the first sub-voltage line VDD1 part of the voltage line VDD1.
  • the first electrode fc5 of the second light emitting control transistor T5 is connected to a source region or a drain region corresponding to the second light emitting control transistor T5 in the active semiconductor layer 310 through an insulating layer via h30.
  • the second electrode sc7 of the second reset transistor T7 is connected to the source region corresponding to the second reset transistor T7 in the active semiconductor layer 310 through the insulating layer via h26 or drain region.
  • the second electrode sc7 of the second reset transistor T7 is connected to the second connection electrode Co2, for example, the second electrode sc7 of the second reset transistor T7 is a part of the second connection electrode Co2.
  • the first electrode fc3 of the driving transistor T3 is connected to the source region or the drain region corresponding to the driving transistor T3 in the active semiconductor layer 310 through the insulating layer via h31 .
  • the first electrode fc3 of the driving transistor T3 is connected to the third connecting electrode Co3, for example, the first electrode fc3 of the driving transistor T3 is a part of the third connecting electrode Co3.
  • the second connection electrode Co2 is connected to the first electrode plate CC1 of the storage capacitor Cst, ie, the gate of the driving transistor T3 , through the insulating layer via h29 .
  • the second sub-initial signal line Vinit2 is electrically connected to the first sub-initial signal line Vinit1 through the insulating layer via hole h21 .
  • the first sub-voltage line VDD1 is electrically connected to the second sub-voltage line VDD2 through the insulating layer via hole h28 .
  • the second electrode of the data writing transistor T4, the first electrode of the second light emission control transistor T5, and the second electrode of the driving transistor T3 are integrally provided.
  • the first sub-voltage line VDD1 and the second sub-voltage line VDD2 are located in different layers
  • the second sub-voltage line VDD2 is located in the second conductive layer 330
  • the first sub-voltage line VDD1 is located in the source and drain Pole metal layer 340 .
  • the first sub-initial signal line Vinit1 and the second sub-initial signal line Vinit2 are located in different layers
  • the first sub-initial signal line Vinit1 is located in the second conductive layer 330
  • the second sub-initial signal line Vinit2 is located in the source-drain metal layer 340 .
  • the data line Vda extends substantially along the second direction Y
  • the first sub-voltage line VDD1 the data line Vda and the second sub-initial signal line Vinit2 are located in the same layer, that is, the source-drain metal layer 340
  • the first sub-voltage line VDD1 the data line Vda and the second sub-initial signal line Vinit2 are located in the same layer
  • data line Vda and second sub-initial signal line Vinit2 are arranged along the first direction X
  • the first sub-voltage line VDD1 is located on the data line Vda and the second sub-initial signal line Vinit2 between.
  • a planarization layer 420 is formed on the side of the source-drain metal layer 340 away from the third insulating layer 410 to protect the source-drain metal layer 340 .
  • the planarization layer 420 includes a first via hole h100 , and the first via hole h100 penetrates through the planarization layer 420 .
  • the second electrode of the first light emission control transistor T6 is electrically connected to the first electrode of the light emitting element 121 through the first via hole h100 penetrating the planarization layer 420 .
  • 4K is a schematic diagram of the stacking positional relationship of the active semiconductor layer 310 , the first conductive layer 320 , the second conductive layer 330 , the third insulating layer 410 , the source-drain metal layer 340 and the planarization layer 420 .
  • the orthographic projection of the first via hole h100 on the base substrate is at the orthographic projection of the reset signal line Rt on the base substrate and the second light-emitting control signal line EM2 is at between the orthographic projections on the base substrate, in the second direction Y, the first via hole h100 may be disposed at any position between the reset signal line Rt and the second light emission control signal line EM2, that is, in the present disclosure
  • the setting position of the first via hole h100 is more flexible, and can be adapted to pixel circuits with various pixel arrangements.
  • the position of the hole h100 makes the first via hole h100 closer to the first electrode of the light-emitting element 121, reducing the wiring of the first electrode of the light-emitting element 121, the first electrode of the light-emitting element 121 and the first light-emitting control transistor T6.
  • the connection between the two poles is more flexible.
  • the first via hole h100 is located near the scan signal line Ga, and in the second direction Y, the orthographic projection of the first via hole h100 on the base substrate is approximately located on the base substrate of the scan signal line Ga between the orthographic projection of and the orthographic projection of the second light-emitting control signal line EM2 on the base substrate.
  • the orthographic projection of the first via hole h100 on the base substrate is located within the orthographic projection of the first connection electrode Co1 on the base substrate, that is, the first via hole h100 exposes a part of the first connection electrode Co1 and emits light
  • the first electrode of the element 121 may be connected to the first connection electrode Co1 through the first via hole h100.
  • FIG. 4N is a schematic structural diagram of a source-drain metal layer according to other embodiments of the disclosure
  • FIG. 4O is a schematic structural diagram of a planarization layer according to other embodiments of the disclosure
  • FIG. 4P is another implementation of the disclosure.
  • the example provides a schematic diagram of the stacking position relationship of the active semiconductor layer, the first conductive layer, the second conductive layer, the third insulating layer, the source-drain metal layer and the planarization layer.
  • the orthographic projection of the first via hole on the base substrate is located at the orthographic projection of the scanning signal line on the base substrate and the orthographic projection of the first light-emitting control signal line on the substrate between orthographic projections on the substrate.
  • the orthographic projection of the first via hole h100 ′ on the base substrate is located between the orthographic projection of the scanning signal line Ga on the base substrate and the first light-emitting control signal line EM1 between orthographic projections on the base substrate.
  • FIG. 4N and FIG. 4O show schematic structural diagrams of the source-drain metal layer and the planarization layer in this embodiment.
  • the layout design of one or more layers in the pixel circuit can be changed accordingly, for example, compared with the source-drain metal layer 340 shown in FIG. As shown, the position of the first connection electrode Co1' in the source-drain metal layer 340' changes accordingly.
  • the first connection electrode Co1' is closer to the upper side of the figure, that is The side where the first pole fc2 of the threshold compensation transistor T2 and the first pole fc6 of the first light emission control transistor T6 are located.
  • a planarization layer 420 ′ is formed on the side of the source-drain metal layer 340 ′ shown in FIG. 4N away from the third insulating layer to protect the source-drain metal layer 340 ′.
  • the planarization layer 420 ′ includes a first via hole h100 ′, and the first via hole h100 ′ penetrates through the planarization layer 420 ′.
  • the second electrode of the first light emission control transistor T6 is electrically connected to the first electrode of the light emitting element 121 through the first via hole h100' penetrating the planarization layer 420'.
  • the orthographic projection of the first via hole h100' on the base substrate is located within the orthographic projection of the first connection electrode Co1' on the base substrate, that is, the first via hole h100' is exposed A part of the first connection electrode Co1'.
  • the specific position of the first connection electrode Co1' can be set according to the actual situation, as long as the position of the first connection electrode Co1' can satisfy such that the orthographic projection of the first via hole h100' on the substrate is located on the substrate of the first connection electrode Co1'.
  • the conditions in the orthographic projection on the substrate are sufficient.
  • FIG. 4L shows the anode layer 350 of the pixel circuit 120 , and the anode layer 350 includes the first electrode (ie, the anode) R/G/B of the light-emitting element 121 . It should be noted that, in FIG. 4L, only the electroluminescent layer in the light-emitting layer is shown, and other common layers are not shown.
  • a plurality of sub-pixels in each row are arranged in the manner of RGBGRGBG, and the sub-pixels in two adjacent rows are staggered by two sub-pixels, for example, as shown in FIG. 4L, in odd-numbered rows (the first row)
  • a plurality of sub-pixels of 1 are arranged in a manner of RGBGRGBG
  • a plurality of sub-pixels located in an even row (the second row) are arranged in a manner of BGRGRGBG.
  • the plurality of sub-pixels in the display panel may include red sub-pixels, blue sub-pixels and green sub-pixels.
  • B represents the first electrode of the light-emitting element in the blue sub-pixel
  • G represents green
  • R represents the first electrode of the light-emitting element in the red sub-pixel.
  • the area of the first pole of a blue sub-pixel B is larger than the area of the first pole of a green sub-pixel G, and also larger than the area of the first pole of a red sub-pixel R.
  • 4M is a schematic diagram of the stacking positional relationship of the active semiconductor layer 310 , the first conductive layer 320 , the second conductive layer 330 , the third insulating layer 410 , the source-drain metal layer 340 , the planarization layer 420 and the anode layer 350 .
  • the first electrode of the light emitting element 121 is connected to the first connection electrode Co1 through the first via hole h100.
  • the first connection electrode Co1 is connected to the second electrode sc6 of the first light emission control transistor T6, so that the first electrode of the light emitting element 121 is electrically connected to the second electrode sc6 of the first light emission control transistor T6.
  • FIG. 5A is a schematic diagram of a cross-sectional structure at line A in FIG. 4M
  • FIG. 5B is a schematic view of a cross-sectional structure at line B in FIG. 4M .
  • the base substrate 10 includes a multi-layer structure (eg, FIG. 5A shows a two-layer structure), and the multi-layer structure is made of flexible materials.
  • a buffer layer 11 is formed on the base substrate 10 to prevent external water vapor, oxygen and impurities from entering the pixel circuit 120 .
  • the material of the buffer layer 11 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or other suitable materials. Since the silicon nitride material has a high dielectric constant and a good hydrophobic function, it can well protect the pixel circuit from being corroded by water vapor.
  • an active semiconductor layer 310 is formed on the side of the buffer layer 11 away from the base substrate 10 , and the active semiconductor layer 310 shown in FIG. 5A includes the first reset active layer portion T11 and the first compensation active layer portion T21.
  • the active semiconductor layer 310 shown in FIG. 5B includes a portion of the active semiconductor layer 310 corresponding to the second electrode of the first light emission control transistor T6.
  • the first insulating layer 430 is formed on the side of the active semiconductor layer 310 away from the buffer layer 11 , and the first insulating layer 430 is formed on the side of the first insulating layer 430 away from the active semiconductor layer 310 .
  • a conductive layer 320 (not shown in FIG. 5A ), the first conductive layer 320 shown in FIG. 5B includes the scanning signal line Ga and a part of the first electrode plate CC1 of the storage capacitor Cst.
  • the second insulating layer 440 is formed on the side of the first conductive layer 320 away from the first insulating layer 430 , and the second insulating layer 440 is formed on the side of the second insulating layer 440 away from the first conductive layer 320 A second conductive layer 330 is formed.
  • the second conductive layer 330 shown in FIG. 5B includes a portion of the second electrode plate CC2 of the storage capacitor Cst.
  • the third insulating layer 410 is formed on the side of the second conductive layer 330 away from the second insulating layer 440 , and the third insulating layer 410 is formed on the side of the third insulating layer 410 away from the second conductive layer 330
  • a source-drain metal layer 340 is formed.
  • the source-drain metal layer 340 shown in FIG. 5A includes a first sub-voltage line VDD1 and a second sub-initial signal line Vinit2.
  • the second sub-initial signal line Vinit2 passes through the third insulating layer 410.
  • the insulating layer via hole h21 is connected to the first sub-initial signal line Vinit1 so that the first sub-initial signal line Vinit1 and the second sub-initial signal line Vinit2 are electrically connected to each other.
  • the source-drain metal layer 340 shown in FIG. 5B includes a first connection electrode Co1 , and the first connection electrode Co1 is electrically connected through the second via hole h200 penetrating the first insulating layer 430 , the second insulating layer 440 and the third insulating layer 410 to a portion of the active semiconductor layer 310 corresponding to the second pole of the first light emission control transistor T6.
  • a planarization layer 420 is formed on the side of the source-drain metal layer 340 away from the third insulating layer 410 , and the planarization layer 420 is formed on the side of the planarization layer 420 away from the source-drain metal layer 340
  • An anode layer 350 is formed, and a pixel defining layer 360 is formed on the side of the anode layer 350 away from the planarization layer 420 and on the planarization layer 420 .
  • the pixel defining layer 360 includes a plurality of pixel openings.
  • each pixel opening exposes at least a part of the first electrode R/G/B of the corresponding light-emitting element.
  • the area of the pixel opening of one blue sub-pixel is larger than the area of the pixel opening of one green sub-pixel, and is larger than the area of the pixel opening of one red sub-pixel.
  • the area of the pixel opening of one green sub-pixel may be approximately equal to the area of the pixel opening of one red sub-pixel. In other embodiments, the area of the pixel opening of one green sub-pixel is smaller than the area of the pixel opening of one red sub-pixel.
  • the first connection electrode Co1 is electrically connected to the second electrode of the first light-emitting control transistor T6, for example, provided integrally. As shown in FIG. 5B , the first connection electrode Co1 is electrically connected to the anode layer 350 through the first via hole h100. The first electrode of the light-emitting element 120 .
  • the jumper design is performed at the fourth node N4, that is, the part of the active semiconductor layer 310 corresponding to the second pole of the first light-emitting control transistor T6 is first connected to the first connection electrode Co1 through the second via hole h200, Then, the first connection electrode Co1 is electrically connected to the first electrode of the light emitting element 120 in the anode layer 350 through the first via hole h100, so that the arrangement position of the first via hole h100 can be more flexible.
  • the plurality of sub-pixels 12 includes a plurality of sub-pixel pairs, the plurality of sub-pixel pairs are arranged in an array along the first direction X and the second direction Y, and each sub-pixel pair includes adjacent ones in the first direction X of two sub-pixels, the pixel circuits of the two sub-pixels are mirror-symmetrical along a symmetry axis parallel to the second direction Y.
  • 6A-6M are schematic layout diagrams of various structural layers of a pixel circuit according to other embodiments of the present disclosure.
  • FIGS. 6A-6M take the pixel circuit 120 shown in FIG. 2A as an example.
  • the part represented by the rectangular dotted-line frame is the area corresponding to one pixel circuit 120
  • the part represented by the rectangular dot-dash-line frame is the area corresponding to the pixel circuit 120 of a sub-pixel pair.
  • FIGS. 6A-6M show The layout of the area corresponding to the pixel circuits of the four sub-pixel pairs arranged in the array of two rows and two columns shows the layout of the area corresponding to the eight pixel circuits of the array arranged in two rows and four columns.
  • FIGS. 6A-6M is basically the same as the example shown in FIGS. 4A-4M, the difference is that in the example shown in FIGS. 4A-4M multiple sub-pixel arrays are arranged, while FIG. 6A In the example shown in 6M, a plurality of sub-pixel pairs are arranged in an array, and the pixel circuits of the two sub-pixels in each pixel pair are arranged mirror-symmetrically. Only the parts of the example shown in FIGS. 6A-6M that are different from those shown in FIGS. 4A-4M will be described below, and similar descriptions will not be repeated.
  • each pixel circuit 120 may include an active semiconductor layer 510, a first insulating layer (not shown), a first conductive layer 520, a second insulating layer (not shown), a first insulating layer (not shown), a Two conductive layers 530 , a third insulating layer 610 , a source-drain metal layer 540 , a planarization layer 620 and an anode layer 550 .
  • Active semiconductor layer 510, first insulating layer (not shown), first conductive layer 520, second insulating layer (not shown), second conductive layer 530, third insulating layer 610, source-drain metal layer 540 , the planarization layer 620 and the anode layer 550 are sequentially disposed on the base substrate.
  • the first insulating layer, the second insulating layer, the third insulating layer 610 and the planarization layer 620 are all made of insulating materials, such as inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, or other suitable materials.
  • FIG. 6A shows the active semiconductor layers 510 of the plurality of pixel circuits 120
  • the rectangular dashed box shown in FIG. 6A shows the active semiconductor layers 510 of one subpixel in one subpixel pair.
  • the active semiconductor layer 510 can be used to fabricate the active layer of the driving transistor T3, the active layer of the first reset transistor T1, the active layer of the threshold compensation transistor T2, the active layer of the data writing transistor T4, and the second light-emitting control transistor.
  • Each solid rectangular box in FIG. 6A shows the active layer of each transistor T1-T7.
  • the relative positions of the active layers of the respective transistors T1 - T7 in the pixel circuit of each sub-pixel in the pair of sub-pixels are the same as those in the embodiment shown in FIG. 4A , and the repetition will not be repeated.
  • the pixel circuits of the two subpixels in each subpixel pair are mirror-symmetrical with respect to the symmetry axis RR', which is parallel to the second direction Y.
  • a first insulating layer (not shown) is formed on the side of the above-mentioned active semiconductor layer 510 away from the base substrate for protecting the above-mentioned active semiconductor layer 510 .
  • 6B shows the first conductive layer 520 of the pixel circuit 120 , the first conductive layer 520 is disposed on the side of the first insulating layer away from the active semiconductor layer 510 so as to be insulated from the active semiconductor layer 510 .
  • each rectangular solid line frame in FIG. 6A shows each portion where the first conductive layer 520 and the active semiconductor layer 510 overlap.
  • the reset signal line Rt, the first light emission control signal line EM1 , the scan signal line Ga, and the second light emission control signal line EM2 are all located in the first conductive layer 520 .
  • the first conductive layer 520 may further include a first electrode plate CC1 of the storage capacitor Cst, a first reset transistor T1, a threshold compensation transistor T2, a data writing transistor T4, a second light-emitting control transistor T5, and a first light-emitting control transistor T6 , the gates of the second reset transistor T7 and the drive transistor T3.
  • the reset signal line Rt, the first light emission control signal line EM1 , the scanning signal line Ga, and the second light emission control signal line EM2 all extend substantially along the first direction X.
  • the reset signal line Rt, the first light emission control signal line EM1, the scanning signal line Ga, and the second light emission control signal line EM2 are arranged in sequence.
  • FIG. 6C is a schematic diagram of the stacking positional relationship between the active semiconductor layer 510 and the first conductive layer 520 .
  • the active layer of the first reset transistor T1 is a reset active layer, that is, the first reset transistor T1 includes a reset active layer, and the reset active layer includes a first reset active layer part T11 and a second reset active layer part T12.
  • the orthographic projection of the second reset active layer portion T12 on the base substrate and the orthographic projection of the reset signal line Rt on the base substrate at least partially overlap.
  • the portion of the active semiconductor layer 510 covered by the reset signal line Rt of the first conductive layer 520 includes the second reset active layer portion T12
  • the second reset active layer part T12 includes two parts spaced apart from each other, and the first reset active layer part T11 and the second reset active layer part T12 generally form a U-shape as a whole, that is, the first reset transistor T1 is U-shaped Double gate transistor.
  • the active layer of the threshold compensation transistor T2 is a compensation active layer, that is, the threshold compensation transistor T2 includes a compensation active layer, and the compensation active layer includes a first compensation active layer part T21 and a second compensation active layer part T22.
  • the orthographic projection of the second compensation active layer portion T22 on the base substrate and the orthographic projection of the reset signal line Rt on the base substrate at least partially overlap.
  • the portion of the active semiconductor layer 510 covered by the reset signal line Rt of the first conductive layer 520 includes the second compensation active layer portion T22
  • the second compensation active layer part T22 includes two parts spaced apart from each other, the first compensation active layer part T21 and the second compensation active layer part T22 generally form a U-shape as a whole, that is, the threshold compensation transistor T2 is a U-shaped double gate transistor.
  • the shape of the first reset active layer portion T11 and the shape of the first compensation active layer portion T21 are substantially the same.
  • the second reset active layer part T12 includes first and second subsections T121 and T122 spaced apart from each other
  • the second compensation active layer part T22 includes third subsections T221 and T122 spaced apart from each other Fourth subsection T222.
  • the first sub-section T121, the second sub-section T122, the third sub-section T221 and the fourth sub-section T222 are sequentially arranged in the first direction X
  • the center of the first sub-section T121, the center of the second sub-section T122 , the center of the third sub-portion T221 and the center of the fourth sub-portion T222 are substantially located on the same straight line, and the straight line is parallel to the first direction X, for example.
  • FIG. 6E is a schematic diagram of the stacking positional relationship of the active semiconductor layer 310 , the first conductive layer 320 and the second conductive layer 330 .
  • a second insulating layer (not shown) is formed on the side of the first conductive layer 520 away from the first insulating layer to protect the first conductive layer 520 .
  • 6D shows the second conductive layer 530 of the pixel circuit 120.
  • the second conductive layer 530 is formed on the side of the second insulating layer away from the first conductive layer 520.
  • the second conductive layer 530 includes the second conductive layer of the storage capacitor Cst.
  • the first sub-initial signal line Vinit1 and the second sub-voltage line VDD2 both extend along the first direction X and are arranged along the second direction Y.
  • the first electrode plate CC1 and the second electrode plate CC2 of the storage capacitor Cst at least partially overlap to form the storage capacitor Cst.
  • the second sub-voltage line VDD2 is integrally formed with the second electrode plate CC2 of the storage capacitor Cst.
  • the second electrode plate CC2 of the storage capacitor Cst includes a conductive layer via hole h11, and the second electrode of the threshold compensation transistor T2 and the second electrode of the second reset transistor T7 pass through the conductive layer
  • the via hole h11 is electrically connected to the first electrode plate CC1 of the storage capacitor Cst, that is, the gate of the driving transistor DT.
  • the initial signal line Vinit includes a first sub-initial signal line Vinit1, the orthographic projection of the first reset active layer portion T11 on the base substrate and the first compensation active layer portion Vinit1 in The orthographic projections on the base substrate are all located within the orthographic projections of the first sub-initial signal line Vinit1 on the base substrate.
  • the portion of the active layer of the first reset transistor T1 that is not blocked by the reset signal line Rt and the unreset portion of the active layer of the threshold compensation transistor T2 are simultaneously shielded by the first sub-initial signal line Vinit1
  • the part shielded by the signal line Rt does not need to be shielded by a shielding layer, which can reduce the wiring on the display substrate, reduce the cost, and make the first reset transistor T1 and the threshold compensation transistor T2 more stable.
  • FIG. 6G is a schematic diagram of the stacking positional relationship of the active semiconductor layer 510 , the first conductive layer 520 , the second conductive layer 530 and the third insulating layer 610 .
  • a third insulating layer 610 is formed on the side of the second conductive layer 530 away from the second insulating layer to protect the second conductive layer 530 .
  • a plurality of insulating layer via holes h21 - h31 are formed in the third insulating layer 610 .
  • the plurality of insulating layer via holes h21-h31 correspond to one pixel circuit.
  • the insulating layer vias h21 penetrate through the third insulating layer 610 to expose a part of the first sub-initial signal line Vinit1; the insulating layer vias h22-27 and the insulating layer vias 30-31 penetrate through The first insulating layer, the second insulating layer and the third insulating layer 610 thereby expose a part of the active semiconductor layer 510; the insulating layer via hole h28 penetrates the third insulating layer 610 to expose a part of the second electrode plate CC2 of the storage capacitor Cst; The insulating layer via hole h29 penetrates the second insulating layer and the third insulating layer 610 to expose a part of the first electrode plate CC1 of the storage capacitor Cst.
  • the orthographic projection of the insulating layer via hole h29 on the base substrate is located within the orthographic projection of the conductive layer via hole h11 on the base substrate.
  • FIG. 6H shows the source-drain metal layer 540 of the pixel circuit 120 , and the source-drain metal layer 540 is disposed on the side of the third insulating layer 610 away from the second conductive layer 530 .
  • 6I is a schematic diagram showing the stacking positional relationship of the active semiconductor layer 510 , the first conductive layer 520 , the second conductive layer 530 , the third insulating layer 610 and the source-drain metal layer 540 .
  • the source-drain metal layer 540 includes a data line Vda, a first sub-voltage line VDD1, a second sub-initial signal line Vinit2, a first pole fc1 of the first reset transistor T1, a threshold compensation
  • the data line Vda, the first sub-voltage line VDD1, and the second sub-initial signal line Vinit2 are located in the same layer, that is, the source-drain metal layer 540, the data line Vda, the first sub-voltage line VDD1, and the second sub-initial signal line Vinit2 They are arranged along the first direction X and all extend along the second direction Y, and in the first direction X, the data lines Vda are located between the first sub-voltage line VDD1 and the second sub-initial signal line Vinit2 . It should be noted that the present disclosure is not limited thereto. In other embodiments, the first sub-voltage line VDD1 is located between the data line Vda and the second sub-initial signal line Vinit2.
  • a planarization layer 620 is formed on the side of the source-drain metal layer 540 away from the third insulating layer 610 to protect the source-drain metal layer 540 .
  • the planarization layer 620 includes a first via hole h100 , and the first via hole h100 penetrates through the planarization layer 420 .
  • the second electrode of the first light emission control transistor T6 is electrically connected to the first electrode of the light emitting element 121 through the first via hole h100 penetrating the planarization layer 420.
  • 6K is a schematic diagram of the stacking positional relationship of the active semiconductor layer 510 , the first conductive layer 520 , the second conductive layer 530 , the third insulating layer 610 , the source-drain metal layer 540 and the planarization layer 620 .
  • the orthographic projection of the first via hole h100 on the base substrate is located at the orthographic projection of the reset signal line Rt on the base substrate and the second light-emitting control signal line EM2
  • the setting position of the first via hole h100 is more flexible, and can be adapted to pixel circuits with various pixel arrangements.
  • the position of the first via hole h100 can be flexibly adjusted, so that the first via hole h100 is closer to the first electrode of the light-emitting element, reducing the wiring of the first electrode of the light-emitting element and emitting light.
  • the connection between the first electrode of the element and the second electrode of the first light emission control transistor T6 is more flexible. As shown in FIG.
  • the first via hole h100 is located near the scanning signal line Ga, and in the second direction Y, the orthographic projection of the first via hole h100 on the base substrate is approximately located on the base substrate by the scanning signal line Ga between the orthographic projection of and the orthographic projection of the second light-emitting control signal line EM2 on the base substrate.
  • the orthographic projection of the first via hole h100 on the base substrate is located at the orthographic projection of the scanning signal line Ga on the base substrate and the first light-emitting control signal Line EM1 is between orthographic projections on the base substrate.
  • FIG. 6L shows the anode layer 650 of the pixel circuit 120 , and the anode layer 650 includes the first electrode (ie, the anode) R/G/B of the light-emitting element 121 . It should be noted that, in FIG. 6L , only the electroluminescent layer in the light-emitting layer is shown, and other common layers are not shown.
  • the plurality of sub-pixel pairs includes a plurality of first sub-pixel pairs and a plurality of second sub-pixel pairs, each first sub-pixel pair includes a first sub-pixel and a second sub-pixel, and each second sub-pixel pair It includes a first subpixel and a third subpixel, the first subpixel may be a green subpixel, the second subpixel may be a red subpixel, and the third subpixel may be a blue subpixel.
  • each sub-pixel row (parallel to the first direction X), a plurality of first sub-pixel pairs and a plurality of second sub-pixel pairs are alternately arranged, and in each sub-pixel column (parallel to the second direction Y), a plurality of The first sub-pixel pair and the plurality of second sub-pixel pairs are also alternately arranged.
  • the four sub-pixel pairs located in two rows and two columns include two first sub-pixel pairs PP1 and two second sub-pixel pairs PP2, and the two first sub-pixel pairs PP1 are respectively located in the first row
  • the first column and the second row and the second column, the two second sub-pixel pairs PP2 are respectively located in the first row, the second column and the second row and the first column.
  • the first sub-pixel pair PP1 includes a red sub-pixel R and a green sub-pixel G
  • the second sub-pixel pair PP2 includes a blue sub-pixel B and a green sub-pixel G. That is, as shown in FIG.
  • a plurality of sub-pixel pairs located in odd-numbered rows are arranged in accordance with RG (first sub-pixel pair PP1 ) BG (second sub-pixel pair PP2 ) RG (first sub-pixel pair PP1 ) ) BG (the second sub-pixel pair PP2) are arranged in sequence, and the multiple sub-pixel pairs located in the even row (the second row) are arranged in accordance with (the second sub-pixel pair PP2) RG (the first sub-pixel pair PP1) BG (the second sub-pixel pair PP1) The sub-pixel pairs PP2) RG (the first sub-pixel pair PP1) are arranged in sequence.
  • the data line Vda is located between the first sub-voltage line VDD1 and the second sub-initial signal line Vinit2 in the first direction X
  • pixel circuits of two sub-pixels of the two sub-pixel pairs that are adjacent to each other in the first direction X are electrically connected to the same first sub-voltage line.
  • the two adjacent sub-pixel pairs in the first direction X are the first sub-pixel pair PP1 and the second sub-pixel pair PP2 located in the first row, respectively.
  • the two sub-pixels of the sub-pixel pair PP1 and the second sub-pixel pair PP2 that are adjacent to each other in the first direction X are respectively a green sub-pixel G in the first sub-pixel pair PP1 and a blue sub-pixel G in the second sub-pixel pair PP2.
  • Color sub-pixel B, the pixel circuit of the green sub-pixel G and the pixel circuit of the blue sub-pixel B are electrically connected to the same first sub-voltage line VDD1 ′, and the first sub-voltage line VDD1 ′ is located in the green sub-pixel G between the pixel circuit of the blue sub-pixel B and the pixel circuit of the blue sub-pixel B.
  • wirings can be saved.
  • the pixel circuit of the blue sub-pixel B in the first sub-pixel pair PP1 and the green sub-pixel G in the second sub-pixel pair located on the side of the first sub-pixel pair PP1 away from the second sub-pixel pair PP2 The pixel circuits are electrically connected to the same first sub-voltage line VDD1.
  • the pixel circuits are electrically connected to the same first sub-voltage line VDD1 ′′.
  • the two adjacent sub-pixel pairs in the first direction X are the first sub-pixel pair PP1 and the second sub-pixel pair PP2 located in the second row, respectively , the two sub-pixels of the first sub-pixel pair PP1 and the second sub-pixel pair PP2 that are adjacent to each other in the first direction X are respectively a green sub-pixel G in the second sub-pixel pair PP2 and a green sub-pixel G in the first sub-pixel pair PP1
  • a red sub-pixel R, the pixel circuit of the green sub-pixel G and the pixel circuit of the red sub-pixel R are electrically connected to the same first sub-voltage line VDD1 ′.
  • the second pole of the second light-emitting control transistor in the pixel circuit of the color sub-pixel B is the same, that is, the electrode sc5' shown in FIG. 6H.
  • the via holes h28 ′ and h30 ′ corresponding to the first sub-voltage line VDD1 ′ are also connected to the pixel circuit of the green sub-pixel G in the first sub-pixel pair PP1 electrically connected to the first sub-voltage line VDD1 ′ and The pixel circuits of the blue sub-pixel B in the second sub-pixel pair PP2 are shared.
  • the pixel circuits of the first sub-pixel pair PP1 and the pixel circuits of the second sub-pixel pair PP2 in the first row are approximately mirror-symmetrical with respect to the first sub-voltage line VDD1 ′, located in The pixel circuits of the first sub-pixel pair PP1 and the pixel circuits of the second sub-pixel pair PP2 in the second row are approximately mirror-symmetrical with respect to the first sub-voltage line VDD1 ′. That is, the pixel circuits located in the first column and the pixel circuits located in the second column are approximately mirror-symmetrical with respect to the first sub-voltage line VDD1 ′.
  • 6M is a schematic diagram of the stacking positional relationship of the active semiconductor layer 510 , the first conductive layer 520 , the second conductive layer 530 , the third insulating layer 610 , the source-drain metal layer 540 , the planarization layer 620 and the anode layer 550 .
  • the first electrode of the light emitting element 121 is connected to the first connection electrode Co1 through the first via hole h100.
  • the first connection electrode Co1 is connected to the second electrode sc6 of the first light emission control transistor T6, so that the first electrode of the light emitting element 121 is electrically connected to the second electrode sc6 of the first light emission control transistor T6.
  • FIG. 7A is a schematic diagram of the cross-sectional structure at the line A′ in FIG. 6M
  • FIG. 7B is a schematic diagram of the cross-sectional structure at the line B′ in FIG. 6M .
  • the base substrate 10 includes a multi-layer structure (for example, FIG. 7A shows a two-layer structure), and the multi-layer structures are all made of flexible materials.
  • a buffer layer 11 is formed on the base substrate 10 to prevent external water vapor, oxygen and impurities from entering the pixel circuit 120 .
  • the material of the buffer layer 11 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or other suitable materials.
  • an active semiconductor layer 510 is formed on the side of the buffer layer 11 away from the base substrate 10 , and the active semiconductor layer 510 shown in FIG. 7A includes the first reset active layer portion T11 and the first compensation active layer portion T21.
  • the active semiconductor layer 510 shown in FIG. 7B includes a portion of the active semiconductor layer 510 corresponding to the second electrode of the first light emission control transistor T6.
  • the first insulating layer 630 is formed on the side of the active semiconductor layer 510 away from the buffer layer 11 , and the first insulating layer 630 is formed on the side of the first insulating layer 630 away from the active semiconductor layer 510 .
  • a conductive layer 520 (not shown in FIG. 5A ), the first conductive layer 520 shown in FIG. 7B includes the scan signal line Ga and a part of the first electrode plate CC1 of the storage capacitor Cst.
  • the second insulating layer 640 is formed on the side of the first conductive layer 520 away from the first insulating layer 630 , and the second insulating layer 640 is formed on the side of the second insulating layer 640 away from the first conductive layer 520 A second conductive layer 530 is formed.
  • the third conductive layer 530 shown in FIG. 7B includes a portion of the second electrode plate CC2 of the storage capacitor Cst.
  • the third insulating layer 610 is formed on the side of the second conductive layer 530 away from the second insulating layer 640 , and the side of the third insulating layer 610 away from the second conductive layer 530 is formed.
  • a source-drain metal layer 540 is formed.
  • the source-drain metal layer 540 shown in FIG. 7A includes a data line Vda and a second sub-initial signal line Vinit2.
  • the second sub-initial signal line Vinit2 passes through the insulating layer penetrating the third insulating layer 610.
  • the hole h21 is connected to the first sub-initial signal line Vinit1 so that the first sub-initial signal line Vinit1 and the second sub-initial signal line Vinit2 are electrically connected to each other.
  • the source-drain metal layer 540 shown in FIG. 7B includes a first connection electrode Co1 , which is electrically connected through the second via hole h200 penetrating the first insulating layer 630 , the second insulating layer 640 and the third insulating layer 610 to a portion of the active semiconductor layer 510 corresponding to the second pole of the first light emission control transistor T6.
  • the planarization layer 620 is formed on the side of the source-drain metal layer 540 away from the third insulating layer 610 , and the planarization layer 620 is formed on the side of the planarization layer 620 away from the source-drain metal layer 540
  • An anode layer 550 is formed, and a pixel defining layer 560 is formed on the side of the anode layer 550 away from the planarization layer 620 and on the planarization layer 620 .
  • the pixel defining layer 560 includes a plurality of pixel openings. In a direction perpendicular to the base substrate, each pixel opening exposes at least a part of the first electrode R/G/B of the corresponding light-emitting element.
  • the first connection electrode Co1 is electrically connected to the second electrode of the first light-emitting control transistor T6, for example, provided integrally. As shown in FIG. 7B, the first connection electrode Co1 is electrically connected to the second electrode in the anode layer 550 through the first via hole h100. The first electrode of the light-emitting element 120 .
  • a jumper design is performed at the fourth node N4, that is, the part of the active semiconductor layer 510 corresponding to the second pole of the first light-emitting control transistor T6 is first connected to the first connection electrode Co1 through the second via hole h200, Then, the first connection electrode Co1 is electrically connected to the first electrode of the light emitting element 120 in the anode layer 550 through the first via hole h100, so that the arrangement position of the first via hole h100 can be more flexible.
  • FIG. 8 is a schematic structural diagram of a first conductive layer provided by other embodiments of the present disclosure,
  • the shape of the first light-emitting control signal line EM1 is substantially linear.
  • the first light-emitting control signal line EM1 The connection line between the center of the active layer of one light-emitting control transistor T6 and the center of the active layer of the second reset transistor T7 is not parallel to the first direction X, nor is it parallel to the second direction Y.
  • the solid rectangular frame shows the overlapping portion between the active layer of the first light emission control transistor T6 and the first conductive layer 320" and the active layer of the second reset transistor T7 and the first conductive layer 320". Based on this, it can be known that in the example shown in FIG. 8 , the connection between the center of the active layer of the first light-emitting control transistor T6 and the center of the active layer of the second reset transistor T7 is connected to the first The direction X is substantially parallel.
  • the area shown by the rectangular dotted line frame and the rectangular dot-dash line frame only represents the approximate area of the pixel circuit or the pixel circuit of the sub-pixel pair, and the actual area of the pixel circuit is different from the specific area in the pixel circuit.
  • the placement of the transistors and capacitors is related.
  • FIG. 9 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure.
  • the display panel 800 includes the display substrate 100 provided by any embodiment of the present disclosure, for example, the display substrate 100 shown in FIG. 1 .
  • the display panel 800 may be a liquid crystal display panel or an organic light emitting diode (OLED) display panel or the like.
  • the display substrate 100 may be an array substrate or a color filter substrate.
  • the display panel 800 is an organic light emitting diode display panel
  • the display substrate 100 may be an array substrate.
  • the display panel 800 may be a rectangular panel, a circular panel, an oval panel, a polygonal panel, or the like.
  • the display panel 800 can be not only a flat panel, but also a curved panel, or even a spherical panel.
  • the display panel 800 may also have a touch function, that is, the display panel 800 may be a touch display panel.
  • the display panel 800 can be applied to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display panel 800 may be a flexible display panel, so as to meet various practical application requirements, for example, the display panel 800 may be applied to a curved screen and the like.
  • the display panel 800 may further include other components, such as a data driving circuit, a timing controller, and the like, which are not limited in the embodiments of the present disclosure.
  • the embodiments of the present disclosure do not show all the constituent units of the display panel 800 .
  • those skilled in the art may provide or set other structures not shown according to specific needs, which are not limited in the embodiments of the present disclosure.

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Abstract

一种显示基板(100)和显示面板。显示基板(100)包括：衬底基板(10)、多个子像素(12)、第一电压线(VDD)、数据线(Vda)、扫描信号线(Ga)、第一发光控制信号线(EM1)和第二发光控制信号线(EM2)，每个子像素(12)包括像素电路(120)和发光元件(121)，像素电路(120)包括：驱动子电路(200)、第一发光控制子电路(210)、第二发光控制子电路(220)和数据写入子电路(230)，第一发光控制子电路(210)电连接至驱动子电路(200)的第一端、发光元件(121)的第一电极和第一发光控制信号线(EM1)；第二发光控制子电路(220)电连接至驱动子电路(200)的第二端、第一电压线(VDD)和第二发光控制信号线(EM2)；数据写入子电路(230)电连接至驱动子电路(200)的第二端、数据线(Vda)和扫描信号线(Ga)；第一发光控制信号线(EM1)、扫描信号线(Ga)和第二发光控制信号线(EM2)沿第一方向延伸，且沿第二方向排布，在第二方向上，扫描信号线(Ga)位于第一发光控制信号线(EM1)和第二发光控制信号线(EM2)之间。

Description

显示基板以及显示面板 技术领域
本公开的实施例涉及一种显示基板和显示面板。
背景技术
随着有机发光二极管(organic light-emitting diode，OLED)在显示领域的迅猛发展，人们对显示效果的要求越来越高。由于具有显示质量高等优点，高分辨率显示装置的应用范围也越来越广。在显示领域中，较为关键的技术是像素电路的布局(layout)设计。
发明内容
本公开一些实施例提供一种显示基板，该显示基板包括：衬底基板以及设置在所述衬底基板上的多个子像素、第一电压线、数据线、扫描信号线、第一发光控制信号线和第二发光控制信号线，其中，每个子像素包括像素电路和发光元件，所述像素电路包括：驱动子电路、第一发光控制子电路、第二发光控制子电路和数据写入子电路，所述第一发光控制子电路电连接至所述驱动子电路的第一端、所述发光元件的第一电极和所述第一发光控制信号线，且被配置为在所述第一发光控制信号线上的第一发光控制信号的控制下，控制所述驱动子电路的第一端和所述发光元件的第一电极之间的连接导通或断开；所述第二发光控制子电路电连接至所述驱动子电路的第二端、所述第一电压线和所述第二发光控制信号线，且被配置为在所述第二发光控制信号线上的第二发光控制信号的控制下，控制所述驱动子电路的第二端和所述第一电压线之间的连接导通或断开；所述数据写入子电路电连接至所述驱动子电路的第二端、所述数据线和所述扫描信号线，且被配置为在所述扫描信号线上的扫描信号的控制下，将所述数据线上的数据电压传输至所述驱动子电路的第二端；所述第一发光控制信号线、所述扫描信号线和所述第二发光控制信号线沿第一方向延伸，且沿与所述第一方向不平行的第二方向排布，在所述第二方向上，所述扫描信号线位于所述第一发光控制信号线和所述第二发光控制信号线之间。
例如，在本公开一些实施例提供的显示基板中，所述像素电路还包括存储电容，所述存储电容的第一电极板电连接至所述驱动子电路的控制端，所述存储电容的第二电极板电连接至所述第一电压线，在所述第二方向上，所述第一发光控制信号线在所述衬底基板上的正投影和所述第二发光控制信号线在所述衬底基板上的正投影位于所述存储电容的第二电极板在所述衬底基板上的正投影的两侧。
例如，在本公开一些实施例提供的显示基板中，在所述第二方向上，所述扫描信号线在所述衬底基板上的正投影和所述第二发光控制信号线在所述衬底基板上的正投影位于所述存储电容的第二电极板在所述衬底基板上的正投影的两侧。
例如，本公开一些实施例提供的显示基板还包括设置在所述衬底基板上的复位信号线 和初始信号线，所述像素电路还包括复位子电路和阈值补偿子电路，所述复位子电路电连接至所述驱动子电路的控制端、所述初始信号线、所述第一发光控制信号线和所述复位信号线，且被配置为在所述第一发光控制信号和所述复位信号线上的复位控制信号的控制下，将所述初始信号线上的初始电压传输至所述驱动子电路的控制端；所述阈值补偿子电路电连接至所述驱动子电路的控制端和第一端以及所述复位信号线，且被配置为在所述复位控制信号的控制下，控制所述驱动子电路的第一端和所述驱动子电路的控制端之间的连接导通或断开；所述复位信号线沿所述第一方向延伸，在所述第二方向上，所述复位信号线位于所述第一发光控制信号线的远离所述扫描信号线的一侧。
例如，在本公开一些实施例提供的显示基板中，所述复位子电路包括第一复位晶体管，所述第一复位晶体管包括复位有源层，所述复位有源层包括第一复位有源层部分，所述阈值补偿子电路包括阈值补偿晶体管，所述阈值补偿晶体管包括补偿有源层，所述补偿有源层包括第一补偿有源层部分，所述第一复位有源层部分在所述衬底基板上的正投影和所述初始信号线在所述衬底基板上的正投影至少部分重叠，所述第一补偿有源层部分在所述衬底基板上的正投影和所述初始信号线在所述衬底基板上的正投影至少部分重叠。
例如，在本公开一些实施例提供的显示基板中，所述初始信号线包括第一子初始信号线，所述第一子初始信号线沿所述第一方向延伸，所述第一复位有源层部分在所述衬底基板上的正投影和所述第一补偿有源层部分在所述衬底基板上的正投影均位于所述第一子初始信号线在所述衬底基板上的正投影内。
例如，在本公开一些实施例提供的显示基板中，所述第一复位有源层部分和所述第一补偿有源层部分在所述第一方向上依次排列。
例如，在本公开一些实施例提供的显示基板中，所述初始信号线还包括第二子初始信号线，所述第二子初始信号线沿所述第二方向延伸，所述第一子初始信号线和所述第二子初始信号线电连接。
例如，在本公开一些实施例提供的显示基板中，所述显示基板包括有源半导体层、第一导电层、第二导电层和源漏极金属层，在垂直于所述衬底基板的方向上，所述有源半导体层位于所述衬底基板与所述第一导电层之间，所述第一导电层位于所述有源半导体层和所述第二导电层之间，所述第二导电层位于所述第一导电层和所述源漏极金属层之间，所述第一子初始信号线位于所述第二导电层，所述第二子初始信号线位于所述源漏极金属层。
例如，在本公开一些实施例提供的显示基板中，所述复位有源层还包括第二复位有源层部分，所述补偿有源层包括第二补偿有源层部分，所述第二复位有源层部分在所述衬底基板上的正投影和所述复位信号线在所述衬底基板上的正投影至少部分重叠，所述第二补偿有源层部分在所述衬底基板上的正投影和所述复位信号线在所述衬底基板上的正投影至少部分重叠，所述第二复位有源层部分和所述第二补偿有源层部分在所述第一方向上依次排列。
例如，在本公开一些实施例提供的显示基板中，所述第一复位晶体管和所述阈值补偿晶体管均为双栅晶体管。
例如，在本公开一些实施例提供的显示基板中，所述显示基板包括有源半导体层和第一导电层，在垂直于所述衬底基板的方向上，所述有源半导体层位于所述衬底基板与所述第一导电层之间，所述复位信号线、所述扫描信号线、所述第一发光控制信号线和所述第二发光控制信号线均位于所述第一导电层。
例如，在本公开一些实施例提供的显示基板中，在所述第一发光控制信号和所述复位控制信号的控制下，所述初始电压经由所述复位子电路、所述阈值补偿子电路和所述第一发光控制子电路被传输至所述发光元件的第一电极。
例如，在本公开一些实施例提供的显示基板中，所述驱动子电路包括驱动晶体管，所述驱动子电路的控制端包括所述驱动晶体管的栅极，所述驱动电路的第一端包括所述驱动晶体管的第一极，所述驱动电路的第二端包括所述驱动晶体管的第二极；所述第一发光控制子电路包括第一发光控制晶体管，所述第一发光控制晶体管的栅极电连接所述第一发光控制信号线，所述第一发光控制晶体管的第一极电连接至所述驱动晶体管的第一极，所述第一发光控制晶体管的第二极电连接至所述发光元件的第一电极，所述发光元件的第二电极电连接至第二电压线；所述第二发光控制子电路包括第二发光控制晶体管，所述第二发光控制晶体管的栅极电连接所述第二发光控制信号线，所述第二发光控制晶体管的第一极电连接至所述驱动晶体管的第二极，所述第二发光控制晶体管的第二极电连接至所述第一电压线；所述数据写入子电路包括数据写入晶体管，所述数据写入晶体管的栅极电连接所述扫描信号线，所述数据写入晶体管的第一极电连接至所述数据线，所述数据写入晶体管的第二极电连接至所述驱动晶体管的第二极；所述复位子电路包括第一复位晶体管和第二复位晶体管，所述第一复位晶体管的栅极电连接所述复位信号线，所述第一复位晶体管的第一极电连接至所述初始信号线，所述第一复位晶体管的第二极电连接至所述第二复位晶体管的第一极；所述第二复位晶体管的栅极电连接所述第一发光控制信号线，所述第二复位晶体管的第二极电连接至所述驱动晶体管的栅极；所述阈值补偿子电路包括阈值补偿晶体管，所述阈值补偿晶体管的栅极电连接所述复位信号线，所述阈值补偿晶体管的第一极电连接至所述驱动晶体管的第一极，所述阈值补偿晶体管的第二极电连接至所述驱动晶体管的栅极。
例如，在本公开一些实施例提供的显示基板中，所述显示基板包括有源半导体层、第一导电层、第二导电层、源漏极金属层和平坦化层，在垂直于所述衬底基板的方向上，所述有源半导体层位于所述衬底基板与所述第一导电层之间，所述第一导电层位于所述有源半导体层和所述第二导电层之间，所述第二导电层位于所述第一导电层和所述源漏极金属层之间，所述平坦化层位于所述源漏极金属层的远离所述衬底基板的一侧，所述第一发光控制晶体管的第二极通过贯穿所述平坦化层的第一过孔电连接至所述发光元件的第一电极，在所述第二方向上，所述第一过孔在所述衬底基板上的正投影位于所述复位信号线在所述衬底基板上的正投影和所述第二发光控制信号线在所述衬底基板上的正投影之间。
例如，在本公开一些实施例提供的显示基板中，所述显示基板还包括第一绝缘层、第二绝缘层和第三绝缘层，所述第一绝缘层位于所述有源半导体层和所述第一导电层之间，所述 第二绝缘层位于所述第一导电层和所述第二导电层之间，所述第三绝缘层位于所述第二导电层和所述源漏极金属层之间，所述有源半导体层的与所述第一发光控制晶体管的第二极对应的部分通过贯穿所述第一绝缘层、所述第二绝缘层和所述第三绝缘层的第二过孔电连接至所述源漏极金属层中的第一连接电极，所述第一连接电极与所述所述第一发光控制晶体管的第二极电连接，所述第一连接电极通过所述第一过孔电连接至所述发光元件的第一电极。
例如，在本公开一些实施例提供的显示基板中，在所述第二方向上，所述第一过孔在所述衬底基板上的正投影位于所述扫描信号线在所述衬底基板上的正投影和所述第一发光控制信号线在所述衬底基板上的正投影之间。
例如，在本公开一些实施例提供的显示基板中，所述第一电压线包括第一子电压线和第二子电压线，所述第一子电压线和所述第二子电压线电连接，所述第一子电压线沿所述第二方向延伸，所述第二子电压线沿所述第一方向延伸。
例如，在本公开一些实施例提供的显示基板中，所述多个子像素的像素电路沿所述第一方向和所述第二方向阵列排布。
例如，在本公开一些实施例提供的显示基板中，所述初始信号线包括第一子初始信号线和第二子初始信号线，所述第一子初始信号线沿所述第一方向延伸，所述第二子初始信号线沿所述第二方向延伸，所述第一子初始信号线和所述第二子初始信号线电连接，所述数据线沿所述第二方向延伸，所述第一子电压线、所述数据线和所述第二子初始信号线位于同一层，所述数据线、所述第一子电压线和所述第二子初始信号线沿所述第一方向排列，且在所述第一方向上，所述第一子电压线位于所述数据线和所述第二子初始信号线之间。
例如，在本公开一些实施例提供的显示基板中，所述多个子像素包括多个子像素对，所述多个子像素对沿所述第一方向和所述第二方向阵列排布，每个子像素对包括在所述第一方向上相邻的两个子像素，所述两个子像素的像素电路沿平行于所述第二方向的对称轴镜像对称。
例如，在本公开一些实施例提供的显示基板中，所述初始信号线包括第一子初始信号线和第二子初始信号线，所述第一子初始信号线沿所述第一方向延伸，所述第二子初始信号线沿所述第二方向延伸，所述第一子初始信号线和所述第二子初始信号线电连接，所述数据线沿所述第二方向延伸，所述第一子电压线、所述数据线和所述第二子初始信号线位于同一层，所述数据线、所述第一子电压线和所述第二子初始信号线沿所述第一方向排列，且在所述第一方向上，所述数据线位于所述第一子电压线和所述第二子初始信号线之间。
例如，在本公开一些实施例提供的显示基板中，对于所述多个子像素对中的在所述第一方向上相邻的两个子像素对，所述两个子像素对的在所述第一方向彼此相邻的两个子像素的像素电路与同一条第一子电压线电连接。
例如，在本公开一些实施例提供的显示基板中，所述第一发光控制信号线的形状为弯曲形状或直线形状。
例如，在本公开一些实施例提供的显示基板中，所述第一方向和所述第二方向彼此垂直。
本公开一些实施例还提供一种显示面板，包括根据上述任一实施例所述的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一些实施例提供的一种显示基板的示意性框图；
图2A为本公开一些实施例提供的一种像素电路的结构示意图；
图2B为本公开一些实施例提供的一种像素电路的电路时序图；
图3为本公开一些实施例提供的一种像素电路的布局示意图；
图4A-4M为本公开一些实施例提供的一种像素电路的各个结构层的布局示意图；
图4N为本公开另一些实施例提供的一种源漏极金属层的结构示意图；
图4O为本公开另一些实施例提供的一种平坦化层的结构示意图；
图4P为本公开另一些实施例提供的有源半导体层、第一导电层、第二导电层、第三绝缘层、源漏极金属层和平坦化层的层叠位置关系的示意图；
图5A为图4M中直线A处的截面结构的示意图；
图5B为图4M中直线B处的截面结构的示意图；
图6A-6M为本公开另一些实施例提供的一种像素电路的各个结构层的布局示意图；
图7A为图6M中直线A'处的截面结构的示意图；
图7B为图6M中直线B'处的截面结构的示意图；
图8为本公开另一些实施例提供的一种第一导电层的结构示意图；
图9为本公开至少一实施例提供的一种显示面板的示意图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可 能相应地改变。
为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。
本公开至少一些实施例提供一种显示基板和显示面板，该显示基板包括：衬底基板以及设置在衬底基板上的多个子像素、第一电压线、数据线、扫描信号线、第一发光控制信号线和第二发光控制信号线，每个子像素包括像素电路和发光元件，像素电路包括：驱动子电路、第一发光控制子电路、第二发光控制子电路和数据写入子电路，第一发光控制子电路电连接至驱动子电路的第一端、发光元件的第一电极和第一发光控制信号线，且被配置为在第一发光控制信号线上的第一发光控制信号的控制下，控制驱动子电路的第一端和发光元件的第一电极之间的连接导通或断开；第二发光控制子电路电连接至驱动子电路的第二端、第一电压线和第二发光控制信号线，且被配置为在第二发光控制信号线上的第二发光控制信号的控制下，控制驱动子电路的第二端和第一电压线之间的连接导通或断开；数据写入子电路电连接至驱动子电路的第二端、数据线和扫描信号线，且被配置为在扫描信号线上的扫描信号的控制下，将数据线上的数据电压传输至驱动子电路的第二端；第一发光控制信号线、扫描信号线和第二发光控制信号线沿第一方向延伸，且沿与第一方向不平行的第二方向排布，在第二方向上，扫描信号线位于第一发光控制信号线和第二发光控制信号线之间。
在该显示基板中，通过将第一发光控制信号线、扫描信号线和第二发光控制信号线沿第一方向延伸，且沿第二方向依次排布，从而可以减少走线，增加透光空间，使得像素电路下方的感光元件可以更好地进行感光。另外，该显示基板结构简单，易于设计制造，成本较低。
下面结合附图对本公开的一些实施例进行详细说明，但是本公开并不限于这些具体的实施例。
图1为本公开一些实施例提供的一种显示基板的示意性框图，图2A为本公开一些实施例提供的一种像素电路的结构示意图，图2B为本公开一些实施例提供的一种像素电路的电路时序图。
例如，如图1所示，本公开的实施例提供的显示基板100包括衬底基板10以及设置在衬底基板10上的多个子像素12、第一电压线、数据线、扫描信号线、第一发光控制信号线和第二发光控制信号线。需要说明的是，图1没有示出第一电压线、数据线、扫描信号线、第一发光控制信号线和第二发光控制信号线。
例如，显示基板100可以应用于显示面板，例如有源矩阵有机发光二极管(AMOLED)显示面板等。显示基板100可以为阵列基板。
例如，该衬底基板10可以为柔性基板或刚性基板。例如，衬底基板10可以采用例如玻璃、塑料、石英或其他适合的材料，本公开的实施例对此不作限制。
例如，每个子像素12包括发光元件121和像素电路120，发光元件121位于像素电路120的远离衬底基板10的一侧。像素电路120被配置为驱动发光元件121发光。下面结合图2A和图2B对像素电极及其工作原理进行说明。
例如，如图2A所示，像素电路120包括驱动子电路200、第一发光控制子电路210、第二发光控制子电路220和数据写入子电路230。
例如，如图2A所示，第一发光控制子电路210电连接至驱动子电路200的第一端、发光元件121的第一电极和第一发光控制信号线EM1，且被配置为在第一发光控制信号线EM1上的第一发光控制信号的控制下，控制驱动子电路200的第一端和发光元件121的第一端之间的连接导通或断开。
例如，如图2A所示，第二发光控制子电路220电连接至驱动子电路200的第二端、第一电压线VDD和第二发光控制信号线EM2，且被配置为在第二发光控制信号线EM2上的第二发光控制信号的控制下，控制驱动子电路200的第二端和第一电压线VDD之间的连接导通或断开。
例如，如图2A所示，数据写入子电路230电连接至驱动子电路200的第二端、数据线Vda和扫描信号线Ga，且被配置为在扫描信号线Ga上的扫描信号的控制下，将数据线Vda上的数据电压传输至驱动子电路200的第二端。
例如，如图2A所示，发光元件121的第二电极电连接至第二电压线VSS。
例如，发光元件121可以为发光二极管等。发光二极管可以为微型发光二极管(Micro Light Emitting Diode，Micro LED)、有机发光二极管(Organic Light Emitting Diode，OLED)或量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)等。发光元件121被配置为在工作时接收发光信号(例如，可以为驱动电流)，并发出与该发光信号相对应强度的光。发光元件121可以包括第一电极、第二电极和设置在第一电极和第二电极之间的发光层。发光元件121的第一电极可以为阳极，发光二极管的第二电极可以为阴极。需要说明的是，在本公开的实施例中，发光元件的发光层可以包括电致发光层本身以及位于电致发光层两侧的其他公共层，例如，空穴注入层、空穴传输层、电子注入层以及电子传输层等等。一般发光元件121具有发光阈值电压，在发光元件121的第一电极和第二电极之间的电压大于或等于发光阈值电压时进行发光。在实际应用中，可以根据实际应用环境来设计确定发光元件121的具体结构，在此不作限定。
例如，如图2A所示，像素电路120还包括存储电容Cst，存储电容Cst的第一电极板CC1电连接至驱动子电路200的控制端，存储电容Cst的第二电极板CC2电连接至第一电压线VDD。
例如，如图2A所示，显示基板100还包括设置在衬底基板10上的复位信号线Rt和初始信号线Vinit。像素电路120还包括复位子电路240和阈值补偿子电路250。
例如，复位子电路240电连接至驱动子电路200的控制端、初始信号线Vinit、第一发光控制信号线EM1和复位信号线Rt，且被配置为在第一发光控制信号和复位信号线Rt上的复位控制信号的控制下，将初始信号线Vinit上的初始电压传输至驱动子电路200的控制端。
例如，阈值补偿子电路250电连接至驱动子电路200的控制端和第一端以及复位信号 线Rt，且被配置为在复位信号线Rt上的复位控制信号的控制下，控制驱动子电路200的第一端和驱动子电路200的控制端之间的连接导通或断开。
例如，在复位子电路240传输初始信号线Vinit输出的初始电压至驱动子电路200的控制端以对驱动子电路200的控制端进行初始化时，阈值补偿子电路250被配置为在复位控制信号的控制下导通，同时，第一发光控制子电路210在第一发光控制信号的控制下导通，从而初始电压可以经由阈值补偿子电路250和第一发光控制子电路210被传输至发光元件121的第一电极以对发光元件121的第一电极进行初始化。也就是说，在第一发光控制信号和复位控制信号的控制下，初始电压经由复位子电路240被传输至驱动子电路200的控制端，初始电压经由复位子电路240、阈值补偿子电路250和第一发光控制子电路210被传输至发光元件121的第一电极，从而可以同时对驱动子电路200的控制端和发光元件121的第一电极进行初始化。
例如，如图2A所示，驱动子电路200包括驱动晶体管T3，驱动子电路200的控制端包括驱动晶体管T3的栅极，驱动子电路20的第一端包括驱动晶体管T3的第一极，驱动子电路20的第二端包括驱动晶体管T3的第二极。驱动晶体管T3的栅极电连接到第一节点N1，驱动晶体管T3的第二极电连接到第二节点N2，驱动晶体管T3的第一极电连接到第三节点N3。
第一发光控制子电路210包括第一发光控制晶体管T6，第一发光控制晶体管T6的栅极电连接第一发光控制信号线EM1，第一发光控制晶体管T6的第一极电连接至第三节点N3，即电连接至驱动晶体管T3的第一极，第一发光控制晶体管T6的第二极电连接至第四节点N4，发光元件121的第一电极电连接至第四节点N4，也就是说，第一发光控制晶体管T6的第二极电连接至发光元件121的第一电极。
第二发光控制子电路220包括第二发光控制晶体管T5，第二发光控制晶体管T5的栅极电连接第二发光控制信号线EM2，第二发光控制晶体管T5的第一极电连接至第二节点N2，即电连接至驱动晶体管T3的第二极，第二发光控制晶体管T5的第二极电连接至第一电压线VDD。
数据写入子电路230包括数据写入晶体管T4，数据写入晶体管T4的栅极电连接扫描信号线Ga，数据写入晶体管T4的第一极电连接至数据线Vda，数据写入晶体管T4的第二极电连接至第二节点N2，即电连接至驱动晶体管T3的第二极。
复位子电路240包括第一复位晶体管T1和第二复位晶体管T7，第一复位晶体管T1的栅极电连接复位信号线Rt，第一复位晶体管T1的第一极电连接至初始信号线Vinit，第一复位晶体管T1的第二极电连接至第二复位晶体管T7的第一极；第二复位晶体管T7的栅极电连接第一发光控制信号线EM1，第二复位晶体管T7的第二极电连接至第一节点N1，即电连接至驱动晶体管T3的栅极。
阈值补偿子电路250包括阈值补偿晶体管T2，阈值补偿晶体管T2的栅极电连接复位信号线Rt，阈值补偿晶体管T2的第一极电连接至第三节点N3，即电连接至驱动晶体管T3 的第一极，阈值补偿晶体管T2的第二极电连接至第一节点N1，即电连接至驱动晶体管T3的栅极。
例如，在一些实施例中，第一复位晶体管T1和阈值补偿晶体管T2均为双栅晶体管，从而可以使得与驱动晶体管T3的栅极电连接的第一复位晶体管T1和阈值补偿晶体管T2的漏电流较小，保证驱动晶体管T3的栅极的电压稳定。
例如，第一电压线VDD输出的电压和第二电压线VSS输出的电压之一为高电压，另一个为低电压。例如，如图2A所示的实施例中，第一电压线VDD输出的电压为恒定的第一电压，第一电压为正电压；而第二电压线VSS输出的电压为恒定的第二电压，第二电压为负电压等。例如，在一些示例中，第二电压线VSS可以接地。
例如，按照晶体管的特性，晶体管可以分为N型晶体管和P型晶体管，为了清楚起见，本公开的实施例以晶体管为P型晶体管(例如，P型MOS晶体管)为例详细阐述了本公开的技术方案，也就是说，在本公开的描述中，驱动晶体管T3、数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T6、第二发光控制晶体管T5、第一复位晶体管T1和第二复位晶体管T7等均可以为P型晶体管，从而可以降低制备工艺。然而本公开的实施例的晶体管不限于P型晶体管，本领域技术人员还可以根据实际应用环境利用N型晶体管(例如，N型MOS晶体管)实现本公开的实施例中的一个或多个晶体管的功能，在此不作限定。
需要说明的是，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本公开的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。
例如，在具体实施时，在本公开实施例中，初始信号线Vinit输出的初始电压V i与第二电压线VSS输出的电压V s可以满足如下公式：V i-V s<VEL，从而可以避免发光元件121在非发光阶段(例如，下面将要描述的初始化阶段p1)发光。VEL代表发光元件121的发光阈值电压。
下面结合图2B描述图2A所示的像素电路的工作过程。
例如，如图2B所示，Rt代表复位信号线Rt输出的复位控制信号，Ga代表扫描信号线Ga输出的扫描信号，EM1代表第一发光控制信号线EM1输出的第一发光控制信号，EM2代表第二发光控制信号线EM2输出的第二发光控制信号。需要说明的是，在本公开的实施例中，附图标记Rt、Ga、EM1、EM2、Vda、VDD既表示信号线，也表示信号线上的信号。
例如，一个像素电路在一个显示帧中的工作过程，可以包括：初始化阶段p1、数据写入阶段p2、第一缓冲阶段p3、第二缓冲阶段p4、发光阶段p5。
在初始化阶段p1，复位控制信号Rt和第一发光控制信号EM1处于低电平，第二发光控制信号EM2和扫描信号Ga处于高电平，由此，第一复位晶体管T1在复位控制信号Rt 的低电平的控制下导通，且第二复位晶体管T7在第一发光控制信号EM1的低电平的控制下也导通，这样使得初始信号线Vinit输出的初始电压V i可以通过导通的第一复位晶体管T1和第二复位晶体管T7提供给驱动晶体管T3的栅极，即第三节点N3，从而使驱动晶体管T3的栅极的电压为初始电压V i，实现对驱动晶体管T3的栅极进行初始化。同时，阈值补偿晶体管T2在复位控制信号Rt的低电平的控制下导通，且第一发光控制晶体管T6在第一发光控制信号EM1的低电平的控制下也导通，这样使得初始信号线Vinit输出的初始电压V i可以通过导通的阈值补偿晶体管T2和第一发光控制晶体管T6提供给发光元件121的第一电极，以对发光元件121的第一电极进行初始化。第二发光控制晶体管T5在第二发光控制信号EM2的高电平的控制下截止，数据写入晶体管T4在扫描信号Ga的高电平的控制下截止。
在数据写入阶段p2，复位控制信号Rt和扫描信号Ga处于低电平，第一发光控制信号EM1和第二发光控制信号EM2处于高电平，由此，数据写入晶体管T4在扫描信号Ga的低电平的控制下导通，以将数据线Vda上的数据电压Vda提供给驱动晶体管T3的第二极，即第二节点N2，以使驱动晶体管T3的第二极的电压为数据电压Vda。阈值补偿晶体管T2在复位控制信号Rt的低电平的控制下导通，可以使驱动晶体管T3形成二极管连接方式，从而使驱动晶体管T3的第二极的电压Vda对驱动晶体管T3的栅极进行充电直到驱动晶体管T3的栅极的电压为Vda+Vth为止，驱动晶体管T3的栅极的电压Vda+Vth通过存储电容Cst进行存储。第二复位晶体管T7和第一发光控制晶体管T6在第一发光控制信号EM1的高电平的控制下截止，第二发光控制晶体管T5在第二发光控制信号EM2的高电平的控制下截止。
在第一缓冲阶段p3，扫描信号Ga处于低电平，复位控制信号Rt、第一发光控制信号EM1和第二发光控制信号EM2处于高电平，由此，数据写入晶体管T4在扫描信号Ga的低电平的控制下导通，以将数据线Vda上的数据电压Vda提供给驱动晶体管T3的第二极，以使驱动晶体管T3的第二极的电压继续为数据电压Vda。第一复位晶体管T1和阈值补偿晶体管T2在复位控制信号Rt的高电平的控制下截止，第二复位晶体管T7和第一发光控制晶体管T6在第一发光控制信号EM1的高电平的控制下截止，第二发光控制晶体管T5在第二发光控制信号EM2的高电平的控制下截止。
需要说明的是，通过在第一缓冲阶段p3中使扫描信号Ga为低电平，可以使数据写入晶体管T4继续打开，以使充电更充分。
在第二缓冲阶段p4，第二发光控制信号EM2处于低电平，复位控制信号Rt、第一发光控制信号EM1和扫描信号Ga处于高电平，由此，第二发光控制晶体管T5在第二发光控制信号EM2的高电平的控制下导通，从而第二发光控制晶体管T5可以将第一电压线VDD输出的第一电压VDD提供给驱动晶体管T3的第二极，以使驱动晶体管T3的第二极的电压为第一电压VDD。这样可以通过第一电压线VDD对驱动晶体管T3的第二极进行预充电。第一复位晶体管T1和阈值补偿晶体管T2在复位控制信号Rt的高电平的控制下截止，第二 复位晶体管T7和第一发光控制晶体管T6在第一发光控制信号EM1的高电平的控制下截止，数据写入晶体管T4在扫描信号Ga的高电平的控制下截止。
需要说明的是，通过在第二缓冲阶段p4中使第一发光控制信号EM1为高电平，可以控制第一发光控制晶体管T6截止，这样可以使驱动晶体管T3的栅极的电压进一步稳定后，也就是，使驱动晶体管T3产生的电流进一步稳定后再提供给发光元件121，从而可以进一步提高发光元件121的发光稳定性。
在发光阶段p5，第一发光控制信号EM1和第二发光控制信号EM2处于低电平，复位控制信号Rt和扫描信号Ga处于高电平，由此，第二发光控制晶体管T5在第二发光控制信号EM2的低电平的控制下导通，从而第二发光控制晶体管T5可以将第一电压线VDD输出的第一电压VDD提供给驱动晶体管T3的第二极，以使驱动晶体管T3的第二极的电压为第一电压VDD。此时，驱动晶体管T3的第二极的电压为第一电压VDD，基于存储电容Cst的保持作用，驱动晶体管T3的栅极的电压为Vda+Vth，这样可以使驱动晶体管T3处于饱和状态，从而使驱动晶体管T3产生驱动电流Ids：Ids＝K*((Vda+Vth-VDD)-Vth) 2＝K*(Vda-VDD) 2，K为与工艺和设计有关的结构常数。第一发光控制晶体管T6在第一发光控制信号EM1的低电平的控制下导通，从而第一发光控制晶体管T6可以将驱动晶体管T3的第一极与发光元件121的第一电极导通，从而使驱动电流Ids流入发光元件121，以驱动发光元件121发光。第一复位晶体管T1和阈值补偿晶体管T2在复位控制信号Rt的高电平的控制下截止，数据写入晶体管T4在扫描信号Ga的高电平的控制下截止。
需要说明的是，本公开提供的图2B所示的电路时序图仅仅是示意性的，像素电路的具体时序可以根据实际应用场景进行设置，本公开对此不作具体限定。
图3为本公开一些实施例提供的一种像素电路的布局示意图。
图3为图2A所示的像素电路的布局示意图，显示基板100可以包括有源半导体层、第一导电层、第二导电层、源漏极金属层和阳极层，例如，每个像素电路120包括有源半导体层、第一导电层、第二导电层、源漏极金属层和阳极层，例如，像素电路120的各个元件(晶体管T1-T7和存储电容等)以及各种信号线均设置在有源半导体层、第一导电层、第二导电层、源漏极金属层和阳极层中。在垂直于衬底基板10的方向上，有源半导体层位于衬底基板10与第一导电层之间，第一导电层位于有源半导体层和第二导电层之间，第二导电层位于第一导电层和源漏极金属层之间，源漏极金属层位于第二导电层和阳极层之间。需要说明的是，图3仅示出了一个像素电路中的有源半导体层、第一导电层、第二导电层、源漏极金属层之间的层叠位置关系。
例如，如图3所示，第一发光控制信号线EM1、扫描信号线Ga和第二发光控制信号线EM2沿第一方向X延伸，且沿与第一方向X不平行的第二方向Y排布，在第二方向Y上，扫描信号线Ga位于第一发光控制信号线EM1和第二发光控制信号线EM1之间。
例如，在一些实施例中，第一方向X和第二方向Y彼此垂直。第一方向X可以平行于水平方向，第二方向Y可以平行于竖直方向。
例如，如图3所示，在第二方向Y上，第一发光控制信号线EM1在衬底基板10上的正投影和第二发光控制信号线EM2在衬底基板10上的正投影位于存储电容Cst的第二电极板CC2在衬底基板10上的正投影的两侧。
例如，在第二方向Y上，扫描信号线Ga在衬底基板上的正投影和第二发光控制信号线EM2在衬底基板上的正投影位于存储电容Cst的第二电极板CC2在衬底基板上的正投影的两侧。也就是说，第一发光控制信号线EM1在衬底基板上的正投影和扫描信号线Ga在衬底基板上的正投影位于存储电容Cst的第二电极板CC2在衬底基板上的正投影的同一侧，例如图3中为上侧，第二发光控制信号线EM2在衬底基板上的正投影位于存储电容Cst的第二电极板CC2在衬底基板上的正投影的另一侧，例如图3中为下侧。
例如，如图3所示，复位信号线Rt沿第一方向X延伸，在第二方向Y上，复位信号线Rt位于第一发光控制信号线EM1的远离扫描信号线Ga的一侧，也就是说，在第二方向上，第一发光控制信号线EM1在衬底基板10上的正投影位于复位信号线Rt在衬底基板10上的正投影和扫描信号线Ga在衬底基板10上的正投影之间。
例如，如图3所示，在第二方向Y上，从上到下，复位信号线Rt、第一发光控制信号线EM1、扫描信号线Ga和第二发光控制信号线EM2依次排列。本公开不限于此，在另一些实施例中，在第二方向Y上，从下到上，复位信号线Rt、第一发光控制信号线EM1、扫描信号线Ga和第二发光控制信号线EM2依次排列。
例如，图3中的各矩形实线框示出了第一导电层与有源半导体层交叠的各个部分。复位信号线Rt、第一发光控制信号线EM1、扫描信号线Ga和第二发光控制信号线EM2均位于第一导电层。各个矩形实线框中的有源半导体层分别为晶体管T1-T7的有源层，例如，复位信号线Rt与有源半导体层交叠以限定了第一复位晶体管T1的有源层和阈值补偿晶体管T2的有源层，第一发光控制信号线EM1与有源半导体层交叠以限定了第一发光控制晶体管T6的有源层和第二复位晶体管T7的有源层，扫描信号线Ga与有源半导体层交叠以限定了数据写入晶体管T4的有源层，第二发光控制信号线EM2与有源半导体层交叠以限定了第二发光控制晶体管T5的有源层，存储电容Cst的第一电极板(未标出)与有源半导体层交叠以限定了驱动晶体管T3的有源层。
例如，如图3所示，初始信号线Vinit包括第一子初始信号线Vinit1和第二子初始信号线Vinit2，第一子初始信号线Vinit1沿第一方向X延伸，第二子初始信号线Vinit2沿第二方向Y延伸，第一子初始信号线Vinit1和第二子初始信号线Vinit2电连接。初始信号线Vinit在衬底基板上网格化布线，具有网状结构，也就是说，在整个显示基板上，第一子初始信号线Vinit1和第二子初始信号线Vinit2呈网格状排列，从而初始信号线Vinit的电阻较小、压降(IR drop)较低，使得初始信号线Vinit在衬底基板上的分布更加均匀，进而可以提高初始信号线Vinit提供的初始电压的稳定性，保证初始化阶段p1中对于驱动晶体管T3的栅极和发光元件121的第一电极的初始化效果。
例如，如图3所示，第一电压线VDD包括第一子电压线VDD1和第二子电压线VDD2， 第一子电压线VDD1和第二子电压线VDD2电连接，第一子电压线VDD1沿第二方向Y延伸，第二子电压线VDD2沿第一方向X延伸。第一电压线VDD在衬底基板上网格化布线，也就是说，在整个显示基板上，第一子电压线VDD1和第二子电压线VDD2呈网格状排列，从而第一电压线VDD的电阻较小、压降较低，进而可以提高第一电压线VDD提供的电源电压的稳定性。
例如，第二子电压线VDD2和存储电容Cst的第二电极板CC2一体形成。
例如，如图3所示，数据线Vda、第一子电压线VDD1和第二子初始信号线Vinit2均沿第二方向Y延伸，且沿第一方向X排列。在图3所示的示例中，在第一方向X上，第一子电压线VDD1位于数据线Vda和第二子初始信号线Vinit2之间。
图4A-4M为本公开一些实施例提供的一种像素电路的各个结构层的布局示意图。
例如，在一些实施例中，多个子像素12的像素电路沿第一方向X和第二方向Y阵列排布。下面结合附图4A-4M描述本实施例中的像素电路的各个元件在衬底基板上的位置关系，图4A-4M所示的示例以图2A所示的像素电路120为例。在图4A-4M中，矩形虚线框表示的部分为一个像素电路120对应的区域，图4A-4M示出了阵列排布为两行四列的八个像素电路对应的区域的版图。
例如，如图4A-4M所示，每个像素电路120可以包括有源半导体层310、第一绝缘层(未示出)、第一导电层320、第二绝缘层(未示出)、第二导电层330、第三绝缘层410、源漏极金属层340、平坦化层420和阳极层350。有源半导体层310、第一绝缘层(未示出)、第一导电层320、第二绝缘层(未示出)、第二导电层330、第三绝缘层410、源漏极金属层340、平坦化层420和阳极层350依次设置在衬底基板上。也就是说，在垂直于衬底基板的方向上，有源半导体层310位于衬底基板与第一导电层320之间，第一导电层320位于有源半导体层310和第二导电层330之间，第二导电层330位于第一导电层320和源漏极金属层340之间，平坦化层420位于源漏极金属层340的远离衬底基板的一侧，即位于源漏极金属层340和阳极层350之间，阳极层350位于平坦化层420的远离源漏极金属层340的一侧。第一绝缘层位于有源半导体层310和第一导电层320之间，第二绝缘层位于第一导电层320和第二导电层330之间，第三绝缘层410位于第二导电层330和源漏极金属层340之间。
例如，第一绝缘层、第二绝缘层、第三绝缘层410和平坦化层420均采用绝缘材料制备，例如氮化硅、氧化硅、氮氧化硅等无机绝缘材料，或其它适合的材料。第一绝缘层、第二绝缘层、第三绝缘层410和平坦化层420的制备材料可以相同，或者，第一绝缘层、第二绝缘层、第三绝缘层410和平坦化层420中的至少部分层的制备材料不相同，本公开对此不作限制。
图4A示出了该多个像素电路120的有源半导体层310，有源半导体层310可采用半导体材料图案化形成在衬底基板上。有源半导体层310可用于制作驱动晶体管T3的有源层、第一复位晶体管T1的有源层、阈值补偿晶体管T2的有源层、数据写入晶体管T4的有源 层、第二发光控制晶体管T5的有源层、第一发光控制晶体管T6的有源层、第二复位晶体管T7的有源层，每个晶体管的有源层可以包括源极区域、漏极区域和源极区域和漏极区域之间的沟道区，沟道区用于形成晶体管的沟道。
例如，图4A中的各矩形实线框示出了各个晶体管T1-T7的有源层。如图4A所示，各个晶体管T1-T7的有源层设置在同一层，且第一复位晶体管T1的有源层和第二复位晶体管T7的有源层一体设置，阈值补偿晶体管T2的有源层和第一发光控制晶体管T6的有源层一体设置，驱动晶体管T3的有源层、数据写入晶体管T4的有源层和第二发光控制晶体管T5的有源层一体设置。
例如，如图4A所示，在第二方向Y上，第一复位晶体管T1的有源层、阈值补偿晶体管T2的有源层、数据写入晶体管T4的有源层、第一发光控制晶体管T6的有源层和第二复位晶体管T7的有源层均位于驱动晶体管T3的有源层的第一侧，例如，图4A所示的上侧；第二发光控制晶体管T5的有源层位于驱动晶体管T3的有源层的第二侧，例如，图4A所示的下侧。
例如，有源半导体层310可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。在本公开实施例中，掺杂的源极区域对应晶体管的源极(例如晶体管的第一极)，掺杂的漏极区域对应晶体管的漏极(例如晶体管的第二极)。
例如，在上述有源半导体层310的远离衬底基板的一侧上形成第一绝缘层(未示出)，用于保护上述有源半导体层310。图4B示出了像素电路120的第一导电层320，第一导电层320设置在第一绝缘层的远离有源半导体层310的一侧上，从而与有源半导体层310绝缘。需要说明的是，图4A中的各矩形实线框示出了第一导电层320与有源半导体层310交叠的各个部分。
例如，复位信号线Rt、第一发光控制信号线EM1、扫描信号线Ga、第二发光控制信号线EM2均位于第一导电层320。此外，第一导电层320还可以包括存储电容Cst的第一电极板CC1以及第一复位晶体管T1的栅极、阈值补偿晶体管T2的栅极、数据写入晶体管T4的栅极、第二发光控制晶体管T5的栅极、第一发光控制晶体管T6的栅极、第二复位晶体管T7的栅极和驱动晶体管T3的栅极。
例如，如图4B所示，复位信号线Rt、第一发光控制信号线EM1、扫描信号线Ga、第二发光控制信号线EM2大致上均沿第一方向X延伸。在第二方向Y上，复位信号线Rt、第一发光控制信号线EM1、扫描信号线Ga、第二发光控制信号线EM2依次排列。也就是说，第一发光控制信号线EM1位于复位信号线Rt和扫描信号线Ga之间，扫描信号线Ga位于第一发光控制信号线EM1和第二发光控制信号线EM2之间。
例如，如图4B所示，复位信号线Rt的形状和扫描信号线Ga的形状大致上为直线形状，第一发光控制信号线EM1的形状和第二发光控制信号线EM2的形状大致上为弯曲形状，例如，波浪线形状。
例如，复位信号线Rt与第一复位晶体管T1的栅极以及阈值补偿晶体管T2的栅极电连接，以用于控制第一复位晶体管T1和阈值补偿晶体管T2导通或截止；第一发光控制信号线EM1与第一发光控制晶体管T6的栅极以及第二复位晶体管T7的栅极电连接，以用于控制第一发光控制晶体管T6和第二复位晶体管T7导通或截止；扫描信号线Ga电连接至数据写入晶体管T4的栅极，以用于控制数据写入晶体管T4的导通或截止；第二发光控制信号线EM2与第二发光控制晶体管T5的栅极电连接，以用于控制第二发光控制晶体管T5的导通或截止。
图4C为有源半导体层310和第一导电层320的层叠位置关系的示意图。
例如，在垂直于衬底基板的方向上，复位信号线Rt与第一复位晶体管T1的有源层以及阈值补偿晶体管T2的有源层至少部分交叠；第一发光控制信号线EM1与第一发光控制晶体管T6的有源层以及第二复位晶体管T7的有源层至少部分交叠；扫描信号线Ga与数据写入晶体管T4的有源层至少部分交叠；第二发光控制信号线EM2与第二发光控制晶体管T5的有源层至少部分交叠。
如图4C所示，复位信号线Rt、第一复位晶体管T1的栅极和阈值补偿晶体管T2的栅极一体设置，复位信号线Rt的与有源半导体层310交叠的部分为第一复位晶体管T1的栅极和阈值补偿晶体管T2的栅极；第一发光控制信号线EM1、第一发光控制晶体管T6的栅极和第二复位晶体管T7的栅极一体设置，第一发光控制信号线EM1的与有源半导体层310交叠的部分为第一发光控制晶体管T6的栅极和第二复位晶体管T7的栅极；扫描信号线Ga和数据写入晶体管T4的栅极一体设置，扫描信号线Ga的与有源半导体层310交叠的部分为数据写入晶体管T4的栅极；第二发光控制信号线EM2和第二发光控制晶体管T5的栅极一体设置，第二发光控制信号线EM2的与有源半导体层310交叠的部分为第二发光控制晶体管T5的栅极。驱动晶体管T3的栅极可为存储电容Cst的第一电极板CC1。
例如，如图4B所示，存储电容Cst的第一电极板CC1位于第二发光控制信号线EM2和扫描信号线Ga之间。例如，如图4C所示，在垂直于衬底基板的方向上，有源半导体层310的被第一导电层320的存储电容Cst的第一电极板CC1覆盖的部分为驱动晶体管T3的有源层，且驱动晶体管T3的有源层的形状为汉字“几”的形状。
例如，第一复位晶体管T1的有源层为复位有源层，即第一复位晶体管T1包括复位有源层，复位有源层包括第一复位有源层部分T11和第二复位有源层部分T12。例如，如图4C所示，第二复位有源层部分T12在衬底基板上的正投影和复位信号线Rt在衬底基板上的正投影至少部分重叠。
例如，如图4A和4C所示，在垂直于衬底基板的方向上，有源半导体层310的被第一导电层320的复位信号线Rt覆盖的部分包括第二复位有源层部分T12，第二复位有源层部分T12包括彼此间隔的两个部分，即第一复位晶体管T1为双栅晶体管。第一复位有源层部分T11和第二复位有源层部分T12整体上大致形成一个U形，即第一复位晶体管T1为U型双栅晶体管。
例如，阈值补偿晶体管T2的有源层为补偿有源层，即阈值补偿晶体管T2包括补偿有源层，补偿有源层包括第一补偿有源层部分T21和第二补偿有源层部分T22。例如，如图4C所示，第二补偿有源层部分T22在衬底基板上的正投影和复位信号线Rt在衬底基板上的正投影至少部分重叠。
例如，如图4A和4C所示，在垂直于衬底基板的方向上，有源半导体层310的被第一导电层320的复位信号线Rt覆盖的部分包括第二补偿有源层部分T22，第二补偿有源层部分T22包括彼此间隔的两个部分，即阈值补偿晶体管T2为双栅晶体管。第一补偿有源层部分T21和第二补偿有源层部分T22整体上大致形成一个U形，即阈值补偿晶体管T2为U型双栅晶体管。
例如，如图4A和图4C所示，第一复位有源层部分T11和第一补偿有源层部分T21在第一方向X上依次排列，且第一复位有源层部分T11的中心和第一补偿有源层部分T21的中心大致位于同一条直线上，该直线例如平行于第一方向X。
例如，第一复位有源层部分T11的形状和第一补偿有源层部分T21的形状大致相同。
例如，第一复位晶体管T1包括两个栅极，阈值补偿晶体管T2包括两个栅极，如图4C所示，在垂直于衬底基板的方向上，复位信号线Rt与有源半导体层310彼此交叠以形成四个交叠部分，该四个交叠部分分别为第一复位晶体管T1的两个栅极和阈值补偿晶体管T2的两个栅极。
例如，如图4A所示，第二复位有源层部分T12包括彼此间隔的第一子部分T121和第二子部分T122，第二补偿有源层部分T22包括彼此间隔的第三子部分T221和第四子部分T222。例如，第一子部分T121、第二子部分T122、第三子部分T221和第四子部分T222在第一方向X上依次排列，且第一子部分T121的中心、第二子部分T122的中心、第三子部分T221的中心和第四子部分T222的中心大致位于同一条直线上，该直线例如平行于第一方向X。在第二方向Y上，第一子部分T121的长度、第二子部分T122的长度、第三子部分T221的长度和第四子部分T222的长度大致相等。
例如，在第一方向X上，第一子部分T121的长度略小于第二子部分T122的长度，第三子部分T221的长度略小于第四子部分T222的长度。
例如，第一子部分T121的形状、第二子部分T122的形状、第三子部分T221的形状和第四子部分T222的形状均为矩形。
例如，如图4C所示，在垂直于衬底基板的方向上，有源半导体层310的被第一导电层320的第一发光控制信号线EM1覆盖的部分为第一发光控制晶体管T6的有源层和第二复位晶体管T7的有源层，且第一发光控制晶体管T6的有源层的形状和第二复位晶体管T7的有源层的形状均为矩形。
例如，如图4C所示，在垂直于衬底基板的方向上，有源半导体层310的被第一导电层320的扫描信号线Ga覆盖的部分为数据写入晶体管T4的有源层，且数据写入晶体管T4的有源层的形状均为矩形。
例如，如图4C所示，在垂直于衬底基板的方向上，有源半导体层310的被第一导电层320的第二发光控制信号线EM2覆盖的部分为第二发光控制晶体管T5的有源层，且第二发光控制晶体管T5的有源层的形状均为矩形。
例如，如图4C所示，在第二方向Y上，第一复位晶体管T1的栅极、阈值补偿晶体管T2的栅极、数据写入晶体管T4的栅极、第一发光控制晶体管T6的栅极和第二复位晶体管T7的栅极均位于驱动晶体管T3的栅极的第一侧，例如，图4C所示的上侧；第二发光控制晶体管T5的栅极位于驱动晶体管T3的栅极的第二侧，例如，图4C所示的下侧。
图4E为有源半导体层310、第一导电层320和第二导电层330的层叠位置关系的示意图。
例如，在上述第一导电层320的远离第一绝缘层的一侧上形成第二绝缘层(未示出)，用于保护上述第一导电层320。图4D示出了该像素电路120的第二导电层330，第二导电层330形成在第二绝缘层的远离第一导电层320的一侧，第二导电层330包括存储电容Cst的第二电极板CC2、第一子初始信号线Vinit1和第二子电压线VDD2。如图4E所示，第一子初始信号线Vinit1和第二子电压线VDD2均沿第一方向X延伸，且沿第二方向Y排列，在垂直于衬底基板的方向上，存储电容Cst的第一电极板CC1与存储电容Cst的第二电极板CC2至少部分重叠以形成存储电容Cst。例如，第二子电压线VDD2与存储电容Cst的第二电极板CC2一体形成。
例如，如图4D和图4E所示，存储电容Cst的第二电极板CC2中包括导电层过孔h11，阈值补偿晶体管T2的第二极和第二复位晶体管T7的第二极通过该导电层过孔h11与存储电容Cst的第一电极板CC1，即驱动晶体管DT的栅极，电连接。
例如，第一复位有源层部分T11在衬底基板上的正投影和初始信号线Vinit在衬底基板上的正投影至少部分重叠，第一补偿有源层部分T21在衬底基板上的正投影和初始信号线Vinit在衬底基板上的正投影至少部分重叠。
例如，如图4D和图4E所示，初始信号线Vinit包括第一子初始信号线Vinit1，第一复位有源层部分T11在衬底基板上的正投影和第一补偿有源层部分Vinit1在衬底基板上的正投影均位于第一子初始信号线Vinit1在衬底基板上的正投影内。在本公开的实施例中，通过第一子初始信号线Vinit1同时遮挡第一复位晶体管T1的有源层的未被复位信号线Rt遮挡的部分和阈值补偿晶体管T2的有源层的未被复位信号线Rt遮挡的部分，而不需单独设置遮挡层对其进行遮挡，同时也可以减少显示基板上的走线，降低成本。此外，利用第一子初始信号线Vinit1对第一复位晶体管T1的有源层的未被复位信号线Rt遮挡的部分和阈值补偿晶体管T2的有源层的未被复位信号线Rt遮挡的部分进行遮挡可以使得第一复位晶体管T1和阈值补偿晶体管T2更加稳定。
图4G为有源半导体层310、第一导电层320、第二导电层330和第三绝缘层410的层叠位置关系的示意图。
例如，如图4F所示，在上述第二导电层330的远离第二绝缘层的一侧上形成第三绝缘 层410，用于保护上述第二导电层330。在第三绝缘层410中形成有多个绝缘层过孔h21-h31。多个绝缘层过孔h21-h31对应于一个像素电路。
例如，如图4F和图4G所示，绝缘层过孔h21贯穿第三绝缘层410从而暴露第一子初始信号线Vinit1的一部分；绝缘层过孔h22-27和绝缘层过孔30-31贯穿第一绝缘层、第二绝缘层和第三绝缘层410从而暴露有源半导体层310的一部分；绝缘层过孔h28贯穿第三绝缘层410而暴露存储电容Cst的第二电极板CC2的一部分；绝缘层过孔h29贯穿第二绝缘层和第三绝缘层410从而暴露存储电容Cst的第一电极板CC1的一部分。例如，绝缘层过孔h29在衬底基板上的正投影位于导电层过孔h11在衬底基板上的正投影内。
图4H示出了该像素电路120的源漏极金属层340，源漏极金属层340设置在第三绝缘层410的远离第二导电层330的一侧。图4I示出了有源半导体层310、第一导电层320、第二导电层330、第三绝缘层410和源漏极金属层340的层叠位置关系的示意图。
例如，如图4H所示，源漏极金属层340包括数据线Vda、第一子电压线VDD1、第二子初始信号线Vinit2、第一复位晶体管T1的第一极fc1、阈值补偿晶体管T2的第一极fc2和第二极sc2、驱动晶体管T3的第一极fc3、数据写入晶体管T4的第一极fc4、第二发光控制晶体管T5的第二极sc5、第一发光控制晶体管T6的第一极fc6和第二极sc6和第二复位晶体管T7的第二极sc7、第一连接电极Co1、第二连接电极Co2和第三连接电极Co3。
例如，如图4F、图4H和图4I所示，第一复位晶体管T1的第一极fc1连接至第二子初始信号线Vinit2，例如，第一复位晶体管T1的第一极fc1为第二子初始信号线Vinit2的一部分。第一复位晶体管T1的第一极fc1通过绝缘层过孔h22连接至有源半导体层310中的与第一复位晶体管T1对应的源极区域或漏极区域。
例如，如图4F、图4H和图4I所示，阈值补偿晶体管T2的第一极fc2和第一发光控制晶体管T6的第一极fc6为同一个电极，且通过绝缘层过孔h24连接至有源半导体层310中的与阈值补偿晶体管T2和第一发光控制晶体管T6对应的源极区域或漏极区域。阈值补偿晶体管T2的第二极sc2通过绝缘层过孔h23连接至有源半导体层310中的与阈值补偿晶体管T2对应的源极区域或漏极区域。
例如，阈值补偿晶体管T2的第一极fc2和第一发光控制晶体管T6的第一极fc6为第三连接电极Co3的一部分。阈值补偿晶体管T2的第二极sc2为第二连接电极Co2的一部分。
例如，第一发光控制晶体管T6的第二极sc6连接至第一连接电极Co1，例如，第一发光控制晶体管T6的第二极sc6为第一连接电极Co1的一部分。例如，第一发光控制晶体管T6的第二极sc6通过绝缘层过孔h27连接至有源半导体层310中的与第一发光控制晶体管T6对应的源极区域或漏极区域。
例如，如图4F、图4H和图4I所示，数据写入晶体管T4的第一极fc4与数据线Vda连接，例如，数据写入晶体管T4的第一极fc4为数据线Vda的一部分，数据写入晶体管T4的第一极fc4通过绝缘层过孔h25连接至有源半导体层310中的与数据写入晶体管T4对应的源极区域或漏极区域。
例如，如图4F、4H和图4I所示，第二发光控制晶体管T5的第一极fc5连接至第一子电压线VDD1，例如，第二发光控制晶体管T5的第一极fc5为第一子电压线VDD1的一部分。第二发光控制晶体管T5的第一极fc5通过绝缘层过孔h30连接至有源半导体层310中的与第二发光控制晶体管T5对应的源极区域或漏极区域。
例如，如图4F、图4H和图4I所示，第二复位晶体管T7的第二极sc7通过绝缘层过孔h26连接至有源半导体层310中的与第二复位晶体管T7对应的源极区域或漏极区域。第二复位晶体管T7的第二极sc7连接至第二连接电极Co2，例如，第二复位晶体管T7的第二极sc7为第二连接电极Co2的一部分。
例如，如图4F、图4H和图4I所示，驱动晶体管T3的第一极fc3通过绝缘层过孔h31连接至有源半导体层310中的与驱动晶体管T3对应的源极区域或漏极区域。驱动晶体管T3的第一极fc3连接至第三连接电极Co3，例如，驱动晶体管T3的第一极fc3为第三连接电极Co3的一部分。
例如，如图4F和图4H所示，第二连接电极Co2通过绝缘层过孔h29连接至存储电容Cst的第一电极板CC1，即驱动晶体管T3的栅极。
例如，如图4F和图4H所示，第二子初始信号线Vinit2通过绝缘层过孔h21电连接至第一子初始信号线Vinit1。
例如，如图4F和图4H所示，第一子电压线VDD1通过绝缘层过孔h28电连接至第二子电压线VDD2。
例如，数据写入晶体管T4的第二极、第二发光控制晶体管T5的第一极和驱动晶体管T3的第二极一体设置。
例如，如图4D和图4H所示，第一子电压线VDD1和第二子电压线VDD2位于不同层，第二子电压线VDD2位于第二导电层330，第一子电压线VDD1位于源漏极金属层340。第一子初始信号线Vinit1和第二子初始信号线Vinit2位于不同层，第一子初始信号线Vinit1位于第二导电层330，第二子初始信号线Vinit2位于源漏极金属层340。
例如，如图4H所示，数据线Vda大致沿第二方向Y延伸，第一子电压线VDD1、数据线Vda和第二子初始信号线Vinit2位于同一层，即源漏极金属层340，第一子电压线VDD1、数据线Vda和第二子初始信号线Vinit2沿第一方向X排列，且在第一方向X上，第一子电压线VDD1位于数据线Vda和第二子初始信号线Vinit2之间。
例如，在上述源漏极金属层340的远离第三绝缘层410的一侧形成有平坦化层420，用于保护上述源漏极金属层340。如图4J所示，平坦化层420包括第一过孔h100，第一过孔h100贯穿平坦化层420。例如，第一发光控制晶体管T6的第二极通过贯穿平坦化层420的第一过孔h100电连接至发光元件121的第一电极。
图4K为有源半导体层310、第一导电层320、第二导电层330、第三绝缘层410、源漏极金属层340和平坦化层420的层叠位置关系的示意图。
例如，如图4K所示，在第二方向Y上，第一过孔h100在衬底基板上的正投影位于复 位信号线Rt在衬底基板上的正投影和第二发光控制信号线EM2在衬底基板上的正投影之间，在第二方向Y上，第一过孔h100可以设置在复位信号线Rt和第二发光控制信号线EM2之间的任意位置，也就是说，在本公开的实施例中，第一过孔h100的设置位置更加灵活，可以适应于各种像素排布的像素电路，此外，还可以根据发光元件121的第一电极的设置位置，灵活地调整第一过孔h100的位置，从而使得第一过孔h100更靠近发光元件121的第一电极，减少发光元件121的第一电极的走线，发光元件121的第一电极和第一发光控制晶体管T6的第二极之间的连接更加灵活。如图4K所示，第一过孔h100位于扫描信号线Ga附近，在第二方向Y上，第一过孔h100在衬底基板上的正投影大致上位于扫描信号线Ga在衬底基板上的正投影和第二发光控制信号线EM2在衬底基板上的正投影之间。
例如，第一过孔h100在衬底基板上的正投影位于第一连接电极Co1在衬底基板上的正投影内，也就是说，第一过孔h100暴露第一连接电极Co1的一部分，发光元件121的第一电极可以通过该第一过孔h100连接至第一连接电极Co1。
图4N为本公开另一些实施例提供的一种源漏极金属层的结构示意图，图4O为本公开另一些实施例提供的一种平坦化层的结构示意图，图4P为本公开另一些实施例提供的有源半导体层、第一导电层、第二导电层、第三绝缘层、源漏极金属层和平坦化层的层叠位置关系的示意图。
例如，在另一些实施例中，在第二方向Y上，第一过孔在衬底基板上的正投影位于扫描信号线在衬底基板上的正投影和第一发光控制信号线在衬底基板上的正投影之间。例如，如图4P所示，在第二方向Y上，第一过孔h100'在衬底基板上的正投影位于扫描信号线Ga在衬底基板上的正投影和第一发光控制信号线EM1在衬底基板上的正投影之间。
图4N和图4O示出该实施例中的源漏极金属层和平坦化层的结构示意图。
基于第一过孔h100'的位置的变化，像素电路中的某一层或多层的布局设计可以进行相应的改变，例如，相对于图4H所示的源漏极金属层340，如图4N所示，源漏极金属层340'中的第一连接电极Co1'的位置相应地发生改变。为了适应第一过孔h100'的位置变化，相对于图4H所示的第一连接电极Co1，如图4N所示，整体上，第一连接电极Co1'更靠近图示的上侧，即靠近阈值补偿晶体管T2的第一极fc2和第一发光控制晶体管T6的第一极fc6所在的一侧。
在图4N所示的源漏极金属层340'的远离第三绝缘层的一侧形成有平坦化层420'，用于保护上述源漏极金属层340'。如图4O所示，平坦化层420'包括包括第一过孔h100'，第一过孔h100'贯穿平坦化层420'。例如，第一发光控制晶体管T6的第二极通过贯穿平坦化层420'的第一过孔h100'电连接至发光元件121的第一电极。
例如，如图4P所示，第一过孔h100'在衬底基板上的正投影位于第一连接电极Co1'在衬底基板上的正投影内，也就是说，第一过孔h100'暴露第一连接电极Co1'的一部分。第一连接电极Co1'可以根据实际情况设置具体位置，只要第一连接电极Co1'的位置可以满足使得第一过孔h100'在衬底基板上的正投影位于第一连接电极Co1'在衬底基板上的正投影内的 条件即可。
需要说明的是，其余各层中的元件的位置可以根据实际情况设置，本公开不再赘述。
图4L示出了该像素电路120的阳极层350，阳极层350包括发光元件121的第一电极(即阳极)R/G/B。需要说明的是，在图4L中，仅示出了发光层中的电致发光层，而没有示出其他公共层。
例如，在一些实施例中，每一行的多个子像素按照RGBGRGBG的方式排列，相邻两行的子像素错开两个子像素的位置，例如，如图4L所示，位于奇数行(第一行)的多个子像素按照RGBGRGBG的方式排列，位于偶数行(第二行)的多个子像素按照BGRGRGBG的方式排列。需要说明的是，显示面板中的多个子像素可以包括红色子像素、蓝色子像素和绿色子像素，在图4L中，B表示蓝色子像素中的发光元件的第一电极，G表示绿色子像素中的发光元件的第一电极，R表示红色子像素中的发光元件的第一电极。例如，一个蓝色子像素B的第一极的面积大于一个绿色子像素G的第一极的面积，也大于一个红色子像素R的第一极的面积。
图4M为有源半导体层310、第一导电层320、第二导电层330、第三绝缘层410、源漏极金属层340、平坦化层420和阳极层350的层叠位置关系的示意图。例如，如图4M所示，发光元件121的第一电极通过第一过孔h100连接至第一连接电极Co1。第一连接电极Co1连接至第一发光控制晶体管T6的第二极sc6，从而发光元件121的第一电极与第一发光控制晶体管T6的第二极sc6电连接。
图5A为图4M中直线A处的截面结构的示意图，图5B为图4M中直线B处的截面结构的示意图。
例如，如图5A和图5B所示，衬底基板10包括多层结构(例如图5A示出为两层结构)，多层结构均为柔性材料制备。
例如，如图5A和图5B所示，在衬底基板10上形成一层缓冲层11以防止外界水汽、氧气和杂质等进入像素电路120中。例如，缓冲层11的材料可以包括氧化硅、氮化硅、氧氮化硅等无机绝缘材料，或其它合适的材料。由于氮化硅材料具有较高的介电常数且具有很好的疏水功能，能够很好的保护像素电路不被水汽腐蚀。
例如，如图5A和图5B所示，在缓冲层11的远离衬底基板10的一侧形成有源半导体层310，图5A所示的有源半导体层310包括第一复位有源层部分T11和第一补偿有源层部分T21。图5B所示的有源半导体层310包括有源半导体层310的与第一发光控制晶体管T6的第二极对应的部分。
例如，如图5A和图5B所示，在有源半导体层310的远离缓冲层11的一侧形成第一绝缘层430，在第一绝缘层430的远离有源半导体层310的一侧形成第一导电层320(图5A中未示出)，图5B所示的第一导电层320包括扫描信号线Ga和存储电容Cst的第一电极板CC1的一部分。
例如，如图5A和图5B所示，在第一导电层320的远离第一绝缘层430的一侧形成第 二绝缘层440，在第二绝缘层440的远离第一导电层320的一侧形成第二导电层330。图5A所示的第二导电层330包括第一子初始信号线Vinit1，第一复位有源层部分T11在衬底基板10上的正投影和第一补偿有源层部分T21在衬底基板10上的正投影均位于第一子初始信号线Vinit1在衬底基板10上的正投影内，从而在垂直于衬底基板10的方向上，第一子初始信号线Vinit1可以遮挡第一复位有源层部分T11和第一补偿有源层部分T21。图5B所示的第二导电层330包括存储电容Cst的第二电极板CC2的一部分。
例如，如图5A和图5B所示，在第二导电层330的远离第二绝缘层440的一侧形成第三绝缘层410，在第三绝缘层410的远离第二导电层330的一侧形成源漏极金属层340，图5A所示的源漏极金属层340包括第一子电压线VDD1和第二子初始信号线Vinit2，第二子初始信号线Vinit2通过贯穿第三绝缘层410的绝缘层过孔h21连接至第一子初始信号线Vinit1，从而第一子初始信号线Vinit1和第二子初始信号线Vinit2彼此电连接。图5B所示的源漏极金属层340包括第一连接电极Co1，第一连接电极Co1通过贯穿第一绝缘层430、第二绝缘层440和第三绝缘层410的第二过孔h200电连接至有源半导体层310的与第一发光控制晶体管T6的第二极对应的部分。
例如，如图5A和图5B所示，在源漏极金属层340的远离第三绝缘层410的一侧形成平坦化层420，在平坦化层420的远离源漏极金属层340的一侧形成阳极层350，在阳极层350的远离平坦化层420的一侧和平坦化层420上形成像素限定层360。像素限定层360包括多个像素开口。在垂直于衬底基板的方向上，每个像素开口暴露对应的发光元件的第一电极R/G/B的至少一部分。例如，一个蓝色子像素的像素开口的面积大于一个绿色子像素的像素开口的面积，且大于一个红色子像素的像素开口的面积。在一些实施例中，一个绿色子像素的像素开口的面积可以与一个红色子像素的像素开口的面积大致相等。在另外一些实施例中，一个绿色子像素的像素开口的面积小于一个红色子像素的像素开口的面积。
例如，第一连接电极Co1与第一发光控制晶体管T6的第二极电连接，例如一体设置，如图5B所示，第一连接电极Co1通过第一过孔h100电连接至阳极层350中的发光元件120的第一电极。由此，在第四节点N4处进行跳线设计，即有源半导体层310的与第一发光控制晶体管T6的第二极对应的部分首先通过第二过孔h200连接至第一连接电极Co1，然后，第一连接电极Co1通过第一过孔h100电连接至阳极层350中的发光元件120的第一电极，从而使得第一过孔h100的设置位置可以更加灵活。
例如，在另一些实施例中，多个子像素12包括多个子像素对，多个子像素对沿第一方向X和第二方向Y阵列排布，每个子像素对包括在第一方向X上相邻的两个子像素，两个子像素的像素电路沿平行于第二方向Y的对称轴镜像对称。
图6A-6M为本公开另一些实施例提供的一种像素电路的各个结构层的布局示意图。
下面结合附图6A-6M描述本实施例中的像素电路的各个元件在衬底基板上的位置关系，图6A-6M所示的示例以图2A所示的像素电路120为例。在图6A-6M中，矩形虚线框表示的部分为一个像素电路120对应的区域，矩形点划线框表示的部分为一个子像素对的像素 电路120对应的区域，图6A-6M示出了阵列排布为两行两列的四个子像素对的像素电路对应的区域的版图，即示出了阵列排布为两行四列的八个像素电路对应的区域的版图。
需要说明的是，图6A-6M所示的示例与图4A-4M所示的示例基本上相同，不同之处在于：图4A-4M所示的示例中多个子像素阵列排布，而图6A-6M所示的示例多个子像素对阵列排布，每个像素对中的两个子像素的像素电路镜像对称设置。下面仅描述图6A-6M所示的示例与图4A-4M所示不同的部分，类似的描述将不再重复。
例如，如图6A-6M所示，每个像素电路120可以包括有源半导体层510、第一绝缘层(未示出)、第一导电层520、第二绝缘层(未示出)、第二导电层530、第三绝缘层610、源漏极金属层540、平坦化层620和阳极层550。有源半导体层510、第一绝缘层(未示出)、第一导电层520、第二绝缘层(未示出)、第二导电层530、第三绝缘层610、源漏极金属层540、平坦化层620和阳极层550依次设置在衬底基板上。
例如，第一绝缘层、第二绝缘层、第三绝缘层610和平坦化层620均采用绝缘材料制备，例如氮化硅、氧化硅、氮氧化硅等无机绝缘材料，或其它适合的材料。
图6A示出了多个像素电路120的有源半导体层510，图6A所示的矩形虚线框示出了一个子像素对中的一个子像素的有源半导体层510。有源半导体层510可用于制作驱动晶体管T3的有源层、第一复位晶体管T1的有源层、阈值补偿晶体管T2的有源层、数据写入晶体管T4的有源层、第二发光控制晶体管T5的有源层、第一发光控制晶体管T6的有源层、第二复位晶体管T7的有源层。图6A中的各矩形实线框示出了各个晶体管T1-T7的有源层。子像素对中的每个子像素的像素电路中的各个晶体管T1-T7的有源层彼此之间的相对位置与图4A所示的实施例相同，重复之处不再赘述。
例如，如图6A所示，每个子像素对中的两个子像素的像素电路相对于对称轴RR’镜像对称，对称轴RR’平行于第二方向Y。
例如，在上述有源半导体层510的远离衬底基板的一侧上形成第一绝缘层(未示出)，用于保护上述有源半导体层510。图6B示出了像素电路120的第一导电层520，第一导电层520设置在第一绝缘层的远离有源半导体层510的一侧上，从而与有源半导体层510绝缘。需要说明的是，图6A中的各矩形实线框示出了第一导电层520与有源半导体层510交叠的各个部分。
例如，复位信号线Rt、第一发光控制信号线EM1、扫描信号线Ga、第二发光控制信号线EM2均位于第一导电层520。此外，第一导电层520还可以包括存储电容Cst的第一电极板CC1以及第一复位晶体管T1、阈值补偿晶体管T2、数据写入晶体管T4、第二发光控制晶体管T5、第一发光控制晶体管T6、第二复位晶体管T7和驱动晶体管T3的栅极。
例如，如图6B所示，复位信号线Rt、第一发光控制信号线EM1、扫描信号线Ga、第二发光控制信号线EM2大致上均沿第一方向X延伸。在第二方向Y上，复位信号线Rt、第一发光控制信号线EM1、扫描信号线Ga、第二发光控制信号线EM2依次排列。
图6C为有源半导体层510和第一导电层520的层叠位置关系的示意图。
例如，第一复位晶体管T1的有源层为复位有源层，即第一复位晶体管T1包括复位有源层，复位有源层包括第一复位有源层部分T11和第二复位有源层部分T12。例如，如图6C所示，第二复位有源层部分T12在衬底基板上的正投影和复位信号线Rt在衬底基板上的正投影至少部分重叠。
例如，如图6A和6C所示，在垂直于衬底基板的方向上，有源半导体层510的被第一导电层520的复位信号线Rt覆盖的部分包括第二复位有源层部分T12，第二复位有源层部分T12包括彼此间隔的两个部分，第一复位有源层部分T11和第二复位有源层部分T12整体上大致形成一个U形，即第一复位晶体管T1为U型双栅晶体管。
例如，阈值补偿晶体管T2的有源层为补偿有源层，即阈值补偿晶体管T2包括补偿有源层，补偿有源层包括第一补偿有源层部分T21和第二补偿有源层部分T22。例如，如图6C所示，第二补偿有源层部分T22在衬底基板上的正投影和复位信号线Rt在衬底基板上的正投影至少部分重叠。
例如，如图6A和6C所示，在垂直于衬底基板的方向上，有源半导体层510的被第一导电层520的复位信号线Rt覆盖的部分包括第二补偿有源层部分T22，第二补偿有源层部分T22包括彼此间隔的两个部分，第一补偿有源层部分T21和第二补偿有源层部分T22整体上大致形成一个U形，即阈值补偿晶体管T2为U型双栅晶体管。
例如，第一复位有源层部分T11的形状和第一补偿有源层部分T21的形状大致相同。
例如，如图6A所示，第二复位有源层部分T12包括彼此间隔的第一子部分T121和第二子部分T122，第二补偿有源层部分T22包括彼此间隔的第三子部分T221和第四子部分T222。例如，第一子部分T121、第二子部分T122、第三子部分T221和第四子部分T222在第一方向X上依次排列，且第一子部分T121的中心、第二子部分T122的中心、第三子部分T221的中心和第四子部分T222的中心大致位于同一条直线上，该直线例如平行于第一方向X。
图6E为有源半导体层310、第一导电层320和第二导电层330的层叠位置关系的示意图。
例如，在上述第一导电层520的远离第一绝缘层的一侧上形成第二绝缘层(未示出)，用于保护上述第一导电层520。图6D示出了该像素电路120的第二导电层530，第二导电层530形成在第二绝缘层的远离第一导电层520的一侧，第二导电层530包括存储电容Cst的第二电极板CC2、第一子初始信号线Vinit1和第二子电压线VDD2。如图6E所示，第一子初始信号线Vinit1和第二子电压线VDD2均沿第一方向X延伸，且沿第二方向Y排列，在垂直于衬底基板的方向上，存储电容Cst的第一电极板CC1与存储电容Cst的第二电极板CC2至少部分重叠以形成存储电容Cst。例如，第二子电压线VDD2与存储电容Cst的第二电极板CC2一体形成。
例如，如图6D和图6E所示，存储电容Cst的第二电极板CC2中包括导电层过孔h11，阈值补偿晶体管T2的第二极和第二复位晶体管T7的第二极通过该导电层过孔h11与存储 电容Cst的第一电极板CC1，即驱动晶体管DT的栅极，电连接。
例如，如图6D和图6E所示，初始信号线Vinit包括第一子初始信号线Vinit1，第一复位有源层部分T11在衬底基板上的正投影和第一补偿有源层部分Vinit1在衬底基板上的正投影均位于第一子初始信号线Vinit1在衬底基板上的正投影内。在本公开的实施例中，通过第一子初始信号线Vinit1同时遮挡第一复位晶体管T1的有源层的未被复位信号线Rt遮挡的部分和阈值补偿晶体管T2的有源层的未被复位信号线Rt遮挡的部分，而不需单独设置遮挡层对其进行遮挡，可以减少显示基板上的走线，降低成本，而且可以使得第一复位晶体管T1和阈值补偿晶体管T2更加稳定。
图6G为有源半导体层510、第一导电层520、第二导电层530和第三绝缘层610的层叠位置关系的示意图。
例如，如图6F所示，在上述第二导电层530的远离第二绝缘层的一侧上形成第三绝缘层610，用于保护上述第二导电层530。在第三绝缘层610中形成有多个绝缘层过孔h21-h31。多个绝缘层过孔h21-h31对应于一个像素电路。
例如，如图6F和图6G所示，绝缘层过孔h21贯穿第三绝缘层610从而暴露第一子初始信号线Vinit1的一部分；绝缘层过孔h22-27和绝缘层过孔30-31贯穿第一绝缘层、第二绝缘层和第三绝缘层610从而暴露有源半导体层510的一部分；绝缘层过孔h28贯穿第三绝缘层610而暴露存储电容Cst的第二电极板CC2的一部分；绝缘层过孔h29贯穿第二绝缘层和第三绝缘层610从而暴露存储电容Cst的第一电极板CC1的一部分。例如，绝缘层过孔h29在衬底基板上的正投影位于导电层过孔h11在衬底基板上的正投影内。
图6H示出了该像素电路120的源漏极金属层540，源漏极金属层540设置在第三绝缘层610的远离第二导电层530的一侧。图6I示出了有源半导体层510、第一导电层520、第二导电层530、第三绝缘层610和源漏极金属层540的层叠位置关系的示意图。
例如，如图6H和图6I所示，源漏极金属层540包括数据线Vda、第一子电压线VDD1、第二子初始信号线Vinit2、第一复位晶体管T1的第一极fc1、阈值补偿晶体管T2的第一极fc2和第二极sc2、驱动晶体管T3的第一极fc3、数据写入晶体管T4的第一极fc4、第二发光控制晶体管T5的第二极sc5、第一发光控制晶体管T6的第一极fc6和第二极sc6和第二复位晶体管T7的第二极sc7、第一连接电极Co1、第二连接电极Co2和第三连接电极Co3。
例如，数据线Vda、第一子电压线VDD1、第二子初始信号线Vinit2位于同一层，即源漏极金属层540，数据线Vda、第一子电压线VDD1、第二子初始信号线Vinit2沿第一方向X排列且均沿第二方向Y延伸，且在第一方向X上，数据线Vda位于第一子电压线VDD1和第二子初始信号线Vinit2之间。需要说明的是，本公开不限于此，在另一些实施例中，第一子电压线VDD1位于数据线Vda和第二子初始信号线Vinit2之间。
例如，在上述源漏极金属层540的远离第三绝缘层610的一侧形成有平坦化层620，用于保护上述源漏极金属层540。如图6J所示，平坦化层620包括第一过孔h100，第一过孔h100贯穿平坦化层420。例如，第一发光控制晶体管T6的第二极通过贯穿平坦化层420的 第一过孔h100电连接至发光元件121的第一电极。
图6K为有源半导体层510、第一导电层520、第二导电层530、第三绝缘层610、源漏极金属层540和平坦化层620的层叠位置关系的示意图。
例如，如图6K所示，在第二方向Y上，第一过孔h100在衬底基板上的正投影位于所复位信号线Rt在衬底基板上的正投影和第二发光控制信号线EM2在衬底基板上的正投影之间，也就是说，在本公开的实施例中，第一过孔h100的设置位置更加灵活，可以适应于各种像素排布的像素电路，此外，还可以根据发光元件的第一电极的设置位置，灵活地调整第一过孔h100的位置，从而使得第一过孔h100更靠近发光元件的第一电极，减少发光元件的第一电极的走线，发光元件的第一电极和第一发光控制晶体管T6的第二极之间的连接更加灵活。如图6K所示，第一过孔h100位于扫描信号线Ga附近，在第二方向Y上，第一过孔h100在衬底基板上的正投影大致上位于扫描信号线Ga在衬底基板上的正投影和第二发光控制信号线EM2在衬底基板上的正投影之间。
例如，在另一些实施例中，在第二方向Y上，第一过孔h100在衬底基板上的正投影位于扫描信号线Ga在所述衬底基板上的正投影和第一发光控制信号线EM1在衬底基板上的正投影之间。
图6L示出了该像素电路120的阳极层650，阳极层650包括发光元件121的第一电极(即阳极)R/G/B。需要说明的是，在图6L中，仅示出了发光层中的电致发光层，而没有示出其他公共层。
例如，多个子像素对包括多个第一子像素对和多个第二子像素对，每个第一子像素对包括一个第一子像素和一个第二子像素，每个第二子像素对包括一个第一子像素和一个第三子像素，第一子像素可以为绿色子像素，第二子像素可以为红色子像素，第三子像素可以为蓝色子像素。在每一子像素行(平行于第一方向X)，多个第一子像素对和多个第二子像素对交替排列，在每一子像素列(平行于第二方向Y)，多个第一子像素对和多个第二子像素对也交替排列。
例如，如图6L所示，位于两行两列的四个子像素对包括两个第一子像素对PP1和两个第二子像素对PP2，两个第一子像素对PP1分别位于第一行第一列和第二行第二列，两个第二子像素对PP2分别位于第一行第二列和第二行第一列。第一子像素对PP1包括一个红色子像素R和一个绿色子像素G，第二子像素对PP2包括一个蓝色子像素B和一个绿色子像素G。也就是说，如图6L所示，位于奇数行(第一行)的多个子像素对按照RG(第一子像素对PP1)BG(第二子像素对PP2)RG(第一子像素对PP1)BG(第二子像素对PP2)的方式依次排列，位于偶数行(第二行)的多个子像素对按照(第二子像素对PP2)RG(第一子像素对PP1)BG(第二子像素对PP2)RG(第一子像素对PP1)的方式依次排列。
例如，当在第一方向X上，数据线Vda位于第一子电压线VDD1和第二子初始信号线Vinit2之间时，对于多个子像素对中的在第一方向X上相邻的两个子像素对，两个子像素对的在第一方向X彼此相邻的两个子像素的像素电路与同一条第一子电压线电连接。如图6H 和图6L所示，在一个示例中，在第一方向X上相邻的两个子像素对分别为位于第一行的第一子像素对PP1和第二子像素对PP2，第一子像素对PP1和第二子像素对PP2的在第一方向X彼此相邻的两个子像素分别为第一子像素对PP1中的一个绿色子像素G和第二子像素对PP2中的一个蓝色子像素B，该绿色子像素G的像素电路和该蓝色子像素B的像素电路与同一条第一子电压线VDD1'电连接，且第一子电压线VDD1'位于该绿色子像素G的像素电路和该蓝色子像素B的像素电路之间。在本公开的实施例中，通过将相邻的子像素的像素电路与同一条第一子电压线电连接，从而可以节省走线。
例如，第一子像素对PP1中的蓝色子像素B的像素电路和位于该第一子像素对PP1的远离第二子像素对PP2的一侧的第二子像素对中的绿色子像素G的像素电路电连接至同一条第一子电压线VDD1。例如，该第二子像素对PP2中的绿色子像素G的像素电路和位于该第二子像素对PP2的远离第一子像素对PP1的一侧的第一子像素对中的红色子像素R的像素电路电连接至同一条第一子电压线VDD1”。
例如，如图6H和图6L所示，在另一个示例中，在第一方向X上相邻的两个子像素对分别为位于第二行的第一子像素对PP1和第二子像素对PP2，第一子像素对PP1和第二子像素对PP2的在第一方向X彼此相邻的两个子像素分别为第二子像素对PP2中的一个绿色子像素G和第一子像素对PP1中的一个红色子像素R，该绿色子像素G的像素电路和该红色子像素R的像素电路与同一条第一子电压线VDD1'电连接。
例如，如图6H和图6L所示，在第一行中，与该第一子电压线VDD1'电连接的绿色子像素G的像素电路中的第二发光控制晶体管的第二极和该蓝色子像素B的像素电路中的第二发光控制晶体管的第二极为同一个，即图6H所示的电极sc5'。此外，与该第一子电压线VDD1'对应的过孔h28'和h30'也被与该第一子电压线VDD1'电连接的第一子像素对PP1中的绿色子像素G的像素电路和第二子像素对PP2中的蓝色子像素B的像素电路共用。
例如，如图6H和图6L所示，位于第一行的第一子像素对PP1的像素电路和第二子像素对PP2的像素电路相对于第一子电压线VDD1'大致呈镜像对称，位于第二行的第一子像素对PP1的像素电路和第二子像素对PP2的像素电路相对于第一子电压线VDD1'大致呈镜像对称。也就是说，位于第一列的像素电路和位于第二列的像素电路相对于第一子电压线VDD1'大致呈镜像对称。
图6M为有源半导体层510、第一导电层520、第二导电层530、第三绝缘层610、源漏极金属层540、平坦化层620和阳极层550的层叠位置关系的示意图。例如，如图6M所示，发光元件121的第一电极通过第一过孔h100连接至第一连接电极Co1。第一连接电极Co1连接至第一发光控制晶体管T6的第二极sc6，从而发光元件121的第一电极与第一发光控制晶体管T6的第二极sc6电连接。
图7A为图6M中直线A'处的截面结构的示意图，图7B为图6M中直线B'处的截面结构的示意图。
例如，如图7A和图7B所示，衬底基板10包括多层结构(例如图7A示出为两层结 构)，多层结构均为柔性材料制备。
例如，如图7A和图7B所示，在衬底基板10上形成一层缓冲层11以防止外界水汽、氧气和杂质等进入像素电路120中。例如，缓冲层11的材料可以包括氧化硅、氮化硅、氧氮化硅等无机绝缘材料，或其它合适的材料。
例如，如图7A和图7B所示，在缓冲层11的远离衬底基板10的一侧形成有源半导体层510，图7A所示的有源半导体层510包括第一复位有源层部分T11和第一补偿有源层部分T21。图7B所示的有源半导体层510包括有源半导体层510的与第一发光控制晶体管T6的第二极对应的部分。
例如，如图7A和图7B所示，在有源半导体层510的远离缓冲层11的一侧形成第一绝缘层630，在第一绝缘层630的远离有源半导体层510的一侧形成第一导电层520(图5A中未示出)，图7B所示的第一导电层520包括扫描信号线Ga和存储电容Cst的第一电极板CC1的一部分。
例如，如图7A和图7B所示，在第一导电层520的远离第一绝缘层630的一侧形成第二绝缘层640，在第二绝缘层640的远离第一导电层520的一侧形成第二导电层530。图7A所示的第二导电层530包括第一子初始信号线Vinit1，第一复位有源层部分T11在衬底基板10上的正投影和第一补偿有源层部分T21在衬底基板10上的正投影均位于第一子初始信号线Vinit1在衬底基板10上的正投影内，从而在垂直于衬底基板10的方向上，第一子初始信号线Vinit1可以遮挡第一复位有源层部分T11和第一补偿有源层部分T21。图7B所示的第二导电层530包括存储电容Cst的第二电极板CC2的一部分。
例如，如图7A和图7B所示，在第二导电层530的远离第二绝缘层640的一侧形成第三绝缘层610，在第三绝缘层610的远离第二导电层530的一侧形成源漏极金属层540，图7A所示的源漏极金属层540包括数据线Vda和第二子初始信号线Vinit2，第二子初始信号线Vinit2通过贯穿第三绝缘层610的绝缘层过孔h21连接至第一子初始信号线Vinit1，从而第一子初始信号线Vinit1和第二子初始信号线Vinit2彼此电连接。图7B所示的源漏极金属层540包括第一连接电极Co1，第一连接电极Co1通过贯穿第一绝缘层630、第二绝缘层640和第三绝缘层610的第二过孔h200电连接至有源半导体层510的与第一发光控制晶体管T6的第二极对应的部分。
例如，如图7A和图7B所示，在源漏极金属层540的远离第三绝缘层610的一侧形成平坦化层620，在平坦化层620的远离源漏极金属层540的一侧形成阳极层550，在阳极层550的远离平坦化层620的一侧和平坦化层620上形成像素限定层560。像素限定层560包括多个像素开口。在垂直于衬底基板的方向上，每个像素开口暴露对应的发光元件的第一电极R/G/B的至少一部分。
例如，第一连接电极Co1与第一发光控制晶体管T6的第二极电连接，例如一体设置，如图7B所示，第一连接电极Co1通过第一过孔h100电连接至阳极层550中的发光元件120的第一电极。由此，在第四节点N4处进行跳线设计，即有源半导体层510的与第一发光控 制晶体管T6的第二极对应的部分首先通过第二过孔h200连接至第一连接电极Co1，然后，第一连接电极Co1通过第一过孔h100电连接至阳极层550中的发光元件120的第一电极，从而使得第一过孔h100的设置位置可以更加灵活。
在上面的实施例中，第一发光控制信号线EM1的形状大致上为弯曲形状，但本公开不限于此，图8为本公开另一些实施例提供的一种第一导电层的结构示意图，例如，如图8所示，在另一些实施例中，在该第一导电层320”中，第一发光控制信号线EM1的形状大致上为直线形状。如图4C和图6C所示，第一发光控制晶体管T6的有源层的中心和第二复位晶体管T7的有源层的中心之间的连线与第一方向X不平行，与第二方向Y也不平行。如图8所示，矩形实线框示出了第一发光控制晶体管T6的有源层与该第一导电层320”之间的重叠部分和第二复位晶体管T7的有源层与该第一导电层320”之间的重叠部分，基于此可知，在图8所示的示例中，第一发光控制晶体管T6的有源层的中心和第二复位晶体管T7的有源层的中心之间的连线与第一方向X大致平行。
需要说明的是，在本公开中，矩形虚线框和矩形点划线框示出的区域也仅表示像素电路或子像素对的像素电路的大致区域，像素电路的实际区域与像素电路中的具体的晶体管和电容的设置位置相关。
本公开至少一实施例还提供一种显示面板。图9为本公开至少一实施例提供的一种显示面板的示意图。如图9所示，该显示面板800包括本公开任一实施例提供的显示基板100，例如，图1中所示的显示基板100。
例如，显示面板800可以为液晶显示面板或有机发光二极管(OLED)显示面板等。例如，当显示面板800为液晶显示面板时，显示基板100可以为阵列基板，也可以为彩膜基板。当显示面板800为有机发光二极管显示面板时，显示基板100可以为阵列基板。
例如，显示面板800可以为矩形面板、圆形面板、椭圆形面板或多边形面板等。另外，显示面板800不仅可以为平面面板，也可以为曲面面板，甚至球面面板。
例如，显示面板800还可以具备触控功能，即显示面板800可以为触控显示面板。
例如，显示面板800可以应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件中。
例如，该显示面板800可以为柔性显示面板，从而可以满足各种实际应用需求，例如，该显示面板800可以应用于曲面屏等。
需要说明的是，该显示面板800还可以包括其他部件，例如数据驱动电路、时序控制器等，本公开的实施例对此不作限定。为表示清楚、简洁，本公开的实施例并没有给出该显示面板800的全部组成单元。为实现该显示面板800的基本功能，本领域技术人员可以根据具体需要提供、设置其他未示出的结构，本公开的实施例对此不作限制。
关于上述实施例提供的显示面板800的技术效果可以参考本公开的实施例中提供的显示基板100的技术效果，这里不再赘述。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本发明的实施例的附图中，层或结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (26)

  1. 一种显示基板，包括：衬底基板以及设置在所述衬底基板上的多个子像素、第一电压线、数据线、扫描信号线、第一发光控制信号线和第二发光控制信号线，
    其中，每个子像素包括像素电路和发光元件，所述像素电路包括：驱动子电路、第一发光控制子电路、第二发光控制子电路和数据写入子电路，
    所述第一发光控制子电路电连接至所述驱动子电路的第一端、所述发光元件的第一电极和所述第一发光控制信号线，且被配置为在所述第一发光控制信号线上的第一发光控制信号的控制下，控制所述驱动子电路的第一端和所述发光元件的第一电极之间的连接导通或断开；
    所述第二发光控制子电路电连接至所述驱动子电路的第二端、所述第一电压线和所述第二发光控制信号线，且被配置为在所述第二发光控制信号线上的第二发光控制信号的控制下，控制所述驱动子电路的第二端和所述第一电压线之间的连接导通或断开；
    所述数据写入子电路电连接至所述驱动子电路的第二端、所述数据线和所述扫描信号线，且被配置为在所述扫描信号线上的扫描信号的控制下，将所述数据线上的数据电压传输至所述驱动子电路的第二端；
    所述第一发光控制信号线、所述扫描信号线和所述第二发光控制信号线沿第一方向延伸，且沿与所述第一方向不平行的第二方向排布，在所述第二方向上，所述扫描信号线位于所述第一发光控制信号线和所述第二发光控制信号线之间。
  2. 根据权利要求1所述的显示基板，其中，所述像素电路还包括存储电容，所述存储电容的第一电极板电连接至所述驱动子电路的控制端，所述存储电容的第二电极板电连接至所述第一电压线，
    在所述第二方向上，所述第一发光控制信号线在所述衬底基板上的正投影和所述第二发光控制信号线在所述衬底基板上的正投影位于所述存储电容的第二电极板在所述衬底基板上的正投影的两侧。
  3. 根据权利要求2所述的显示基板，其中，在所述第二方向上，所述扫描信号线在所述衬底基板上的正投影和所述第二发光控制信号线在所述衬底基板上的正投影位于所述存储电容的第二电极板在所述衬底基板上的正投影的两侧。
  4. 根据权利要求1-3任一项所述的显示基板，还包括设置在所述衬底基板上的复位信号线和初始信号线，
    其中，所述像素电路还包括复位子电路和阈值补偿子电路，
    所述复位子电路电连接至所述驱动子电路的控制端、所述初始信号线、所述第一发光控制信号线和所述复位信号线，且被配置为在所述第一发光控制信号和所述复位信号线上的复位控制信号的控制下，将所述初始信号线上的初始电压传输至所述驱动子电路的控制端；
    所述阈值补偿子电路电连接至所述驱动子电路的控制端和第一端以及所述复位信号线， 且被配置为在所述复位控制信号的控制下，控制所述驱动子电路的第一端和所述驱动子电路的控制端之间的连接导通或断开；
    所述复位信号线沿所述第一方向延伸，在所述第二方向上，所述复位信号线位于所述第一发光控制信号线的远离所述扫描信号线的一侧。
  5. 根据权利要求4所述的显示基板，其中，所述复位子电路包括第一复位晶体管，所述第一复位晶体管包括复位有源层，所述复位有源层包括第一复位有源层部分，
    所述阈值补偿子电路包括阈值补偿晶体管，所述阈值补偿晶体管包括补偿有源层，所述补偿有源层包括第一补偿有源层部分，
    所述第一复位有源层部分在所述衬底基板上的正投影和所述初始信号线在所述衬底基板上的正投影至少部分重叠，
    所述第一补偿有源层部分在所述衬底基板上的正投影和所述初始信号线在所述衬底基板上的正投影至少部分重叠。
  6. 根据权利要求5所述的显示基板，其中，所述初始信号线包括第一子初始信号线，所述第一子初始信号线沿所述第一方向延伸，所述第一复位有源层部分在所述衬底基板上的正投影和所述第一补偿有源层部分在所述衬底基板上的正投影均位于所述第一子初始信号线在所述衬底基板上的正投影内。
  7. 根据权利要求6所述的显示基板，其中，所述第一复位有源层部分和所述第一补偿有源层部分在所述第一方向上依次排列。
  8. 根据权利要求6或7所述的显示基板，其中，所述初始信号线还包括第二子初始信号线，所述第二子初始信号线沿所述第二方向延伸，所述第一子初始信号线和所述第二子初始信号线电连接。
  9. 根据权利要求8所述的显示基板，其中，所述显示基板包括有源半导体层、第一导电层、第二导电层和源漏极金属层，在垂直于所述衬底基板的方向上，所述有源半导体层位于所述衬底基板与所述第一导电层之间，所述第一导电层位于所述有源半导体层和所述第二导电层之间，所述第二导电层位于所述第一导电层和所述源漏极金属层之间，
    所述第一子初始信号线位于所述第二导电层，所述第二子初始信号线位于所述源漏极金属层。
  10. 根据权利要求5-9任一项所述的显示基板，其中，所述复位有源层还包括第二复位有源层部分，所述补偿有源层包括第二补偿有源层部分，
    所述第二复位有源层部分在所述衬底基板上的正投影和所述复位信号线在所述衬底基板上的正投影至少部分重叠，
    所述第二补偿有源层部分在所述衬底基板上的正投影和所述复位信号线在所述衬底基板上的正投影至少部分重叠，
    所述第二复位有源层部分和所述第二补偿有源层部分在所述第一方向上依次排列。
  11. 根据权利要求5-10任一项所述的显示基板，其中，所述第一复位晶体管和所述阈 值补偿晶体管均为双栅晶体管。
  12. 根据权利要求4-11任一项所述的显示基板，其中，所述显示基板包括有源半导体层和第一导电层，在垂直于所述衬底基板的方向上，所述有源半导体层位于所述衬底基板与所述第一导电层之间，
    所述复位信号线、所述扫描信号线、所述第一发光控制信号线和所述第二发光控制信号线均位于所述第一导电层。
  13. 根据权利要求4-12任一项所述的显示基板，其中，在所述第一发光控制信号和所述复位控制信号的控制下，所述初始电压经由所述复位子电路、所述阈值补偿子电路和所述第一发光控制子电路被传输至所述发光元件的第一电极。
  14. 根据权利要求4-13任一项所述的显示基板，其中，所述驱动子电路包括驱动晶体管，所述驱动子电路的控制端包括所述驱动晶体管的栅极，所述驱动电路的第一端包括所述驱动晶体管的第一极，所述驱动电路的第二端包括所述驱动晶体管的第二极；
    所述第一发光控制子电路包括第一发光控制晶体管，所述第一发光控制晶体管的栅极电连接所述第一发光控制信号线，所述第一发光控制晶体管的第一极电连接至所述驱动晶体管的第一极，所述第一发光控制晶体管的第二极电连接至所述发光元件的第一电极，所述发光元件的第二电极电连接至第二电压线；
    所述第二发光控制子电路包括第二发光控制晶体管，所述第二发光控制晶体管的栅极电连接所述第二发光控制信号线，所述第二发光控制晶体管的第一极电连接至所述驱动晶体管的第二极，所述第二发光控制晶体管的第二极电连接至所述第一电压线；
    所述数据写入子电路包括数据写入晶体管，所述数据写入晶体管的栅极电连接所述扫描信号线，所述数据写入晶体管的第一极电连接至所述数据线，所述数据写入晶体管的第二极电连接至所述驱动晶体管的第二极；
    所述复位子电路包括第一复位晶体管和第二复位晶体管，所述第一复位晶体管的栅极电连接所述复位信号线，所述第一复位晶体管的第一极电连接至所述初始信号线，所述第一复位晶体管的第二极电连接至所述第二复位晶体管的第一极，所述第二复位晶体管的栅极电连接所述第一发光控制信号线，所述第二复位晶体管的第二极电连接至所述驱动晶体管的栅极；
    所述阈值补偿子电路包括阈值补偿晶体管，所述阈值补偿晶体管的栅极电连接所述复位信号线，所述阈值补偿晶体管的第一极电连接至所述驱动晶体管的第一极，所述阈值补偿晶体管的第二极电连接至所述驱动晶体管的栅极。
  15. 根据权利要求14所述的显示基板，其中，所述显示基板包括有源半导体层、第一导电层、第二导电层、源漏极金属层和平坦化层，在垂直于所述衬底基板的方向上，所述有源半导体层位于所述衬底基板与所述第一导电层之间，所述第一导电层位于所述有源半导体层和所述第二导电层之间，所述第二导电层位于所述第一导电层和所述源漏极金属层之间，所述平坦化层位于所述源漏极金属层的远离所述衬底基板的一侧，
    所述第一发光控制晶体管的第二极通过贯穿所述平坦化层的第一过孔电连接至所述发光元件的第一电极，
    在所述第二方向上，所述第一过孔在所述衬底基板上的正投影位于所述复位信号线在所述衬底基板上的正投影和所述第二发光控制信号线在所述衬底基板上的正投影之间。
  16. 根据权利要求15所述的显示基板，其中，所述显示基板还包括第一绝缘层、第二绝缘层和第三绝缘层，所述第一绝缘层位于所述有源半导体层和所述第一导电层之间，所述第二绝缘层位于所述第一导电层和所述第二导电层之间，所述第三绝缘层位于所述第二导电层和所述源漏极金属层之间，
    所述有源半导体层的与所述第一发光控制晶体管的第二极对应的部分通过贯穿所述第一绝缘层、所述第二绝缘层和所述第三绝缘层的第二过孔电连接至所述源漏极金属层中的第一连接电极，所述第一连接电极与所述所述第一发光控制晶体管的第二极电连接，
    所述第一连接电极通过所述第一过孔电连接至所述发光元件的第一电极。
  17. 根据权利要求15或16所述的显示基板，其中，在所述第二方向上，所述第一过孔在所述衬底基板上的正投影位于所述扫描信号线在所述衬底基板上的正投影和所述第一发光控制信号线在所述衬底基板上的正投影之间。
  18. 根据权利要求1-17任一项所述的显示基板，其中，所述第一电压线包括第一子电压线和第二子电压线，所述第一子电压线和所述第二子电压线电连接，所述第一子电压线沿所述第二方向延伸，所述第二子电压线沿所述第一方向延伸。
  19. 根据权利要求18所述的显示基板，其中，所述多个子像素的像素电路沿所述第一方向和所述第二方向阵列排布。
  20. 根据权利要求19所述的显示基板，其中，所述初始信号线包括第一子初始信号线和第二子初始信号线，所述第一子初始信号线沿所述第一方向延伸，所述第二子初始信号线沿所述第二方向延伸，所述第一子初始信号线和所述第二子初始信号线电连接，
    所述数据线沿所述第二方向延伸，
    所述第一子电压线、所述数据线和所述第二子初始信号线位于同一层，所述数据线、所述第一子电压线和所述第二子初始信号线沿所述第一方向排列，且在所述第一方向上，所述第一子电压线位于所述数据线和所述第二子初始信号线之间。
  21. 根据权利要求18所述的显示基板，其中，所述多个子像素包括多个子像素对，所述多个子像素对沿所述第一方向和所述第二方向阵列排布，
    每个子像素对包括在所述第一方向上相邻的两个子像素，所述两个子像素的像素电路沿平行于所述第二方向的对称轴镜像对称。
  22. 根据权利要求21所述的显示基板，其中，所述初始信号线包括第一子初始信号线和第二子初始信号线，所述第一子初始信号线沿所述第一方向延伸，所述第二子初始信号线沿所述第二方向延伸，所述第一子初始信号线和所述第二子初始信号线电连接，
    所述数据线沿所述第二方向延伸，
    所述第一子电压线、所述数据线和所述第二子初始信号线位于同一层，所述数据线、所述第一子电压线和所述第二子初始信号线沿所述第一方向排列，且在所述第一方向上，所述数据线位于所述第一子电压线和所述第二子初始信号线之间。
  23. 根据权利要求22所述的显示基板，其中，对于所述多个子像素对中的在所述第一方向上相邻的两个子像素对，
    所述两个子像素对的在所述第一方向彼此相邻的两个子像素的像素电路与同一条第一子电压线电连接。
  24. 根据权利要求1-23任一项所述的显示基板，其中，所述第一发光控制信号线的形状为弯曲形状或直线形状。
  25. 根据权利要求1-24任一项所述的显示基板，其中，所述第一方向和所述第二方向彼此垂直。
  26. 一种显示面板，包括根据权利要求1-25任一项所述的显示基板。
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