WO2022001419A1 - 像素电路、显示基板、显示面板和显示装置 - Google Patents

像素电路、显示基板、显示面板和显示装置 Download PDF

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Publication number
WO2022001419A1
WO2022001419A1 PCT/CN2021/094026 CN2021094026W WO2022001419A1 WO 2022001419 A1 WO2022001419 A1 WO 2022001419A1 CN 2021094026 W CN2021094026 W CN 2021094026W WO 2022001419 A1 WO2022001419 A1 WO 2022001419A1
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Prior art keywords
circuit
sub
pixel
transistor
light
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PCT/CN2021/094026
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English (en)
French (fr)
Inventor
顾品超
黄炜赟
程羽雕
吴超
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/772,594 priority Critical patent/US20220406257A1/en
Priority to EP21831733.7A priority patent/EP4053831A4/en
Publication of WO2022001419A1 publication Critical patent/WO2022001419A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/10—Intensity circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
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    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
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    • G—PHYSICS
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    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors

Definitions

  • Embodiments of the present disclosure relate to a pixel circuit, a display substrate, a display panel, and a display device.
  • At least one embodiment of the present disclosure provides a pixel circuit, including: a first driving circuit, a second driving circuit, a first lighting control circuit, a second lighting control circuit, a storage circuit and a data writing circuit, the first lighting control circuit A circuit is electrically connected to the first power supply line, the first driver circuit and the light emitting element, and is configured to control the connection between the first driver circuit and the light emitting element to turn on or off and to control the first The connection between the driving circuit and the first power supply line is turned on or off; the second light emission control circuit is electrically connected to the second power supply line, the second driving circuit and the light emitting element, and is configured to Control the connection between the second drive circuit and the light-emitting element to be turned on or off, and control the connection between the second drive circuit and the second power line to turn on or off; the data writing The input circuit is electrically connected to the first drive circuit and is configured to write a data voltage to the first drive circuit; the first drive circuit and the second drive circuit are configured to be based on the same data voltage
  • the pixel circuit provided by at least one embodiment of the present disclosure further includes a power supply connection line, and the first power supply line and the second power supply line are electrically connected to each other through the power supply connection line.
  • the pixel circuit is located on a base substrate, the pixel circuit has a first functional layer and a second functional layer, the first functional layer and the first functional layer
  • the two functional layers are located on the base substrate, and in the direction perpendicular to the base substrate, the first functional layer is located on the side of the second functional layer away from the base substrate, the The first power line and the second power line are located on the first functional layer, the power connecting line is located on the second functional layer, and the power connecting line is electrically connected to the first power line and the first power line through a via hole. the second power cord.
  • control terminal of the first driving circuit and the control terminal of the second driving circuit are electrically connected.
  • the pixel circuit provided by at least one embodiment of the present disclosure further includes a first gate connection line, a second gate connection line and a third gate connection line, a control terminal of the first driving circuit and the second driving circuit
  • the control end of the circuit is electrically connected through the first gate connection line, the second gate connection line and the third gate connection line, and the control end of the first drive circuit is connected to the first gate
  • the pole connecting line is electrically connected
  • the control terminal of the second driving circuit is electrically connected with the second gate connecting line
  • the third gate connecting line is used to electrically connect the first gate connecting line and the
  • a second gate connection line is used to electrically connect the control terminal of the first driving circuit to the control terminal of the second driving circuit.
  • the pixel circuit is located on a base substrate, the pixel circuit has a first functional layer and a second functional layer, the first functional layer and the first functional layer
  • the two functional layers are located on the base substrate, and in the direction perpendicular to the base substrate, the first functional layer is located on the side of the second functional layer away from the base substrate, the The first gate connection line and the second gate connection line are located in the first functional layer, the third gate connection line is located in the second functional layer, and the third gate connection line passes through a via hole connected to the first gate connection line and the second gate connection line.
  • the first driving circuit includes a first driving transistor
  • the second driving circuit includes a second driving transistor
  • the control terminal of the first driving circuit includes all The gate of the first drive transistor
  • the control terminal of the second drive circuit includes the gate of the second drive transistor
  • the threshold voltage of the first drive transistor is the same as the threshold voltage of the second drive transistor.
  • the pixel circuit provided by at least one embodiment of the present disclosure further includes a threshold compensation circuit, the threshold compensation circuit is electrically connected to the control terminal of the first driving circuit and the control terminal of the second driving circuit, and is configured to Threshold compensation is performed on the first drive circuit.
  • the pixel circuit provided by at least one embodiment of the present disclosure further includes a first initialization circuit and a second initialization circuit, and the first initialization circuit is electrically connected to the control terminal of the first driving circuit and the control terminal of the second driving circuit.
  • a control terminal configured to initialize the control terminal of the first driving circuit and the control terminal of the second driving circuit
  • the second initialization circuit is electrically connected to the first pole of the light-emitting element, and is configured to The first pole of the light-emitting element is initialized.
  • the first lighting control circuit includes a first lighting control sub-circuit and a second lighting control sub-circuit, the first lighting control sub-circuit and the first lighting control sub-circuit
  • the first end of the drive circuit is connected to the first power line, and is configured to turn on or off the connection between the first end of the first drive circuit and the first power line
  • the first Two light-emitting control sub-circuits are electrically connected to the second end of the first drive circuit and the first pole of the light-emitting element, and are configured to implement the second end of the first drive circuit and the first pole of the light-emitting element
  • the connection between one pole is made or broken.
  • the second light-emitting control circuit includes a third light-emitting control sub-circuit and a fourth light-emitting control sub-circuit, the third light-emitting control sub-circuit and the second light-emitting control sub-circuit
  • the first end of the drive circuit is connected to the second power line, and is configured to turn on or off the connection between the first end of the second drive circuit and the second power line
  • the first end Four light-emitting control sub-circuits are electrically connected to the second end of the second drive circuit and the first pole of the light-emitting element, and are configured to implement the second end of the second drive circuit and the first electrode of the light-emitting element
  • the connection between one pole is made or broken.
  • the pixel circuit provided by at least one embodiment of the present disclosure further includes a threshold compensation circuit, a first initialization circuit, and a second initialization circuit
  • the first lighting control circuit includes a first lighting control sub-circuit and a second lighting control sub-circuit
  • the second lighting control circuit includes a third lighting control sub-circuit and a fourth lighting control sub-circuit
  • the first driving circuit includes a first driving transistor
  • the second driving circuit includes a second driving transistor
  • the first driving circuit includes a first driving circuit
  • the light-emitting control sub-circuit includes a first light-emitting control transistor
  • the second light-emitting control sub-circuit includes a second light-emitting control transistor
  • the third light-emitting control sub-circuit includes a third light-emitting control transistor
  • the fourth light-emitting control sub-circuit includes a fourth light-emitting control transistor
  • the data writing circuit includes a data writing transistor
  • the storage circuit includes a storage capacitor
  • the threshold compensation circuit includes
  • the gate of the input transistor is electrically connected to the first scan line; the first pole of the first light-emitting control transistor is electrically connected to the first power supply line, and the second pole of the first light-emitting control transistor is electrically connected to the first power line
  • the first pole of the first driving transistor, the gate of the first light-emitting control transistor is electrically connected to the first light-emitting control signal line;
  • the first pole of the second light-emitting control transistor is electrically connected to the first driving transistor the second electrode, the second electrode of the second light-emitting control transistor is electrically connected to the first electrode of the light-emitting element, and the gate of the second light-emitting control transistor is electrically connected to the second light-emitting control signal line;
  • the first electrodes of the three light-emitting control transistors are electrically connected to the second power supply line, the second electrodes of the third light-emitting control transistors are electrically connected to the first electrodes of the second driving transistors, and the third light-e
  • the gate of the second initialization transistor is electrically connected to the second initialization control signal line
  • the first pole of the storage capacitor is electrically connected to the gate of the first driving transistor and the gate of the second driving transistor pole, the second pole of the storage capacitor is electrically connected to the first power line.
  • the pixel circuit is located on a base substrate, the pixel circuit has a first functional layer, a second functional layer and a third functional layer, the first functional layer layer, the second functional layer and the third functional layer are located on the base substrate, and in a direction perpendicular to the base substrate, the second functional layer is located on the first functional layer and Between the third functional layers, the second functional layer is located on the side of the third functional layer away from the base substrate, and the first functional layer is located on the side of the second functional layer away from the One side of the base substrate, the first scan line, the second scan line, the first light emission control signal line, the second light emission control signal line, the third light emission control signal line and the The fourth light-emitting control signal line is located in the third functional layer, the data line, the first power supply line and the second power supply line are located in the first functional layer, the first initialization voltage line and the The second initialization voltage line is located at the second functional layer.
  • the first driving transistor and the second driving transistor transmit the driving current to the light-emitting element in the light-emitting stage to drive the light-emitting element to emit light
  • the drive current is expressed as:
  • I OLED K1*(Vgs1-Vth1)+K2*(Vgs2-Vth2)
  • I OLED represents the driving current
  • K1 is the process constant of the first driving transistor
  • Vgs1 is the voltage difference between the gate and the first electrode of the first driving transistor in the light-emitting stage
  • Vth1 is The threshold voltage of the first driving transistor
  • K2 is the process constant of the second driving transistor
  • Vgs2 is the voltage difference between the gate and the first electrode of the second driving transistor in the light-emitting stage
  • Vth2 is the threshold voltage of the second drive transistor.
  • At least one embodiment of the present disclosure provides a display substrate, the display substrate includes a plurality of sub-pixels, and each of the plurality of sub-pixels includes the pixel circuit and the light-emitting element provided in any embodiment of the present disclosure.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a base substrate, the base substrate includes a first display area, the first display area includes a plurality of pixel areas, each of the plurality of pixel areas Each pixel area includes a first sub-area and a second sub-area that do not overlap with each other, and the first driving circuit, the first light-emitting control circuit, the storage circuit and the data writing circuit in the pixel circuit are located in the first sub-area of the corresponding pixel area. sub-region, the second driving circuit and the second light-emitting control circuit in the pixel circuit are located in the second sub-region of the corresponding pixel region.
  • the base substrate further includes a second display region
  • the plurality of sub-pixels includes a plurality of first sub-pixels and a plurality of second sub-pixels
  • the plurality of sub-pixels include a plurality of first sub-pixels and a plurality of second sub-pixels.
  • the pixel circuits of the first sub-pixels and the pixel circuits of the plurality of second sub-pixels are in one-to-one correspondence with the plurality of pixel regions, the second display region at least partially surrounds the first display region, and the display the substrate has a first side for display and a second side opposite the first side, the first display area allows light from the first side to be at least partially transmitted to the second side; the multiple The light-emitting elements of the first sub-pixels are located in the first display area, and the pixel circuits of the first sub-pixels are located in the second display area; the light-emitting elements and pixel circuits of the second sub-pixels are both located in the second display area. in the second display area.
  • the first sub-region of each pixel region includes a first side and a second side opposite to each other, and the pixel circuits of the plurality of first sub-pixels constitute a plurality of a first repeating unit, each of the first repeating units includes pixel circuits of four first sub-pixels arranged in two rows and two columns, and the pixel circuits of the four first sub-pixels are located in the first row and the first column
  • the second sub-region in the pixel region corresponding to the pixel circuit of the first sub-pixel is located on the first side of the first sub-region, and the pixel circuits of the four first sub-pixels are located in the first column of the second row and the first column.
  • the second sub-region in the pixel region corresponding to the pixel circuit of the sub-pixel is located on the first side of the first sub-region, and the pixel circuits of the four first sub-pixels are located in the first sub-pixel in the first row and the second column.
  • the second sub-area in the pixel area corresponding to the pixel circuit is located on the second side of the first sub-area, and the pixel circuit of the first sub-pixel located in the second row and the second column in the pixel circuits of the four first sub-pixels corresponds to
  • the second sub-region in the pixel region is located on the second side of the first sub-region, and the pixel circuits of the plurality of second sub-pixels constitute a plurality of second repeating units, each of which includes two Pixel circuits of four second sub-pixels in rows and two columns, among the pixel circuits of the four second sub-pixels, the second sub-pixels are located in the pixel area corresponding to the pixel circuits of the second sub-pixels in the first row and the first column.
  • the area is located on the second side of the first sub-area, and the second sub-area in the pixel area corresponding to the pixel circuit of the second sub-pixel located in the second row and the first column of the pixel circuits of the four second sub-pixels is located in the first sub-area.
  • the second sub-region in the pixel region corresponding to the pixel circuit of the second sub-pixel located in the first row and the second column of the pixel circuits of the four second sub-pixels is located in the first sub-region
  • the second sub-region in the pixel region corresponding to the pixel circuit of the second sub-pixel in the second row and the second column in the pixel circuits of the four second sub-pixels is in the first sub-region of the first sub-region. side.
  • the plurality of first repeating units and the plurality of second repeating units constitute a plurality of repeating unit groups, and each of the plurality of repeating unit groups
  • the repeating unit group includes two first repeating units and two second repeating units, the two first repeating units and the two second repeating units are arranged in two rows and two columns, and the two first repeating units are respectively located in the first row, the second column and the second row and the first column, and the two second repeating units are respectively located in the first row, the first column and the second row, the second column; or, the two first repeating units
  • the two second repeating units are respectively located in the first row, the first column and the second row and the second column, and the two second repeating units are respectively located in the first row and the second column and the second row and the first column.
  • the first sub-pixel located in the first row and the first column of the four first sub-pixels and the four second sub-pixels located in the first row is a red sub-pixel
  • the first sub-pixel in the first column in the second row and the four second sub-pixels in the first sub-pixel in the second row is a blue sub-pixel
  • the first sub-pixel, the second sub-pixel located in the first row and the second column of the four second sub-pixels, and the second sub-pixel located in the second row and the second column of the four second sub-pixels are: Green subpixel.
  • At least one embodiment of the present disclosure provides a display panel including the display substrate provided in any embodiment of the present disclosure.
  • At least one embodiment of the present disclosure provides a display device including the display panel provided by any embodiment of the present disclosure.
  • FIG. 1A is a schematic block diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 1B is a schematic block diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure
  • 3A is a schematic plan view of a display substrate according to some embodiments of the present disclosure.
  • 3B is a schematic diagram of the arrangement of sub-pixels on a display substrate according to some embodiments of the present disclosure
  • FIG. 4A is a schematic diagram of the arrangement of a first repeating unit according to some embodiments of the present disclosure.
  • 4B is a schematic diagram of the arrangement of a second repeating unit according to some embodiments of the present disclosure.
  • FIG. 4C is a schematic diagram of arrangement of pixel regions according to some embodiments of the present disclosure.
  • 4D is a schematic diagram of another arrangement of pixel regions provided by some embodiments of the present disclosure.
  • 5A-5E are schematic structural diagrams of each functional layer of a pixel circuit according to some embodiments of the present disclosure.
  • 6A-6D are enlarged schematic diagrams of each functional layer of a pixel circuit according to some embodiments of the present disclosure.
  • FIG. 7 is a schematic block diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG. 8 is a schematic block diagram of a display device according to at least one embodiment of the present disclosure.
  • the display panel in order to allow more light to enter the camera located under the display panel, the display panel can be designed to have a high pixel density area (ie, a high PPI area) and a low pixel density area ( That is, the low PPI area), the camera is placed under the low pixel density area that allows more light to pass through.
  • a high pixel density area ie, a high PPI area
  • a low pixel density area That is, the low PPI area
  • the camera is placed under the low pixel density area that allows more light to pass through.
  • the distribution density per unit area of the light-emitting elements in the low pixel density area is lower than that in the high pixel density area
  • the light emission brightness in the low pixel density area is lower than that in the high pixel density area, which affects the display.
  • the display effect of the panel reduces the display quality of the display panel.
  • At least one embodiment of the present disclosure provides a pixel circuit, a display substrate, a display panel, and a display device.
  • the pixel circuit includes a first driving circuit, a second driving circuit, a first lighting control circuit, a second lighting control circuit, a storage circuit, and data write circuit.
  • the first lighting control circuit is electrically connected to the first power supply line, the first driving circuit and the light-emitting element, and is configured to control the connection between the first driving circuit and the light-emitting element to be turned on or off and to control the first driving circuit and the first driving circuit and the light-emitting element.
  • a connection between the power lines is turned on or off;
  • a second lighting control circuit is electrically connected to the second power line, the second driving circuit and the light-emitting element, and is configured to control the connection between the second driving circuit and the light-emitting element Turning on or off and controlling the connection between the second driving circuit and the second power supply line to be turned on or off;
  • the data writing circuit is electrically connected with the first driving circuit, and is configured to write the data voltage into the first driving circuit
  • the first driving circuit and the second driving circuit are configured to control the driving current for driving the light-emitting element to emit light based on the same data voltage;
  • the storage circuit is electrically connected to the control terminal of the first driving circuit and the control terminal of the second driving circuit, and is It is configured to maintain the voltage of the control terminal of the first driving circuit and the control terminal of the second driving circuit.
  • this pixel circuit by adding a second driving circuit for driving the light-emitting element in the low pixel density area to emit light, two driving circuits can drive one light-emitting element at the same time, thereby improving the driving of the light-emitting element in the low pixel density area.
  • current increase the brightness of the low pixel density area, reduce or eliminate the problem of uneven luminous brightness caused by setting the camera under the display panel, and improve the display effect and display quality.
  • transistors can be divided into N-type transistors and P-type transistors.
  • the embodiments of the present disclosure take transistors as P-type transistors (eg, low temperature polysilicon (LTPS) P-type thin film transistors) as an example.
  • LTPS low temperature polysilicon
  • the transistors in the embodiments of the present disclosure are not limited to P-type transistors.
  • N-type transistors eg, N-type MOS transistors
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors, etc. .
  • the source and drain of the transistor may be symmetrical in structure, so the source and drain of the transistor may be indistinguishable in physical structure.
  • one of the gate electrodes is directly described as the first electrode and the other electrode is the second electrode.
  • the first and second poles are interchangeable as required.
  • FIG. 1A is a schematic block diagram of a pixel circuit according to an embodiment of the disclosure
  • FIG. 1B is a schematic block diagram of another pixel circuit according to an embodiment of the disclosure.
  • the pixel circuit 100 may include a first driving circuit 101 , a second driving circuit 111 , a first lighting control circuit 102 , a second lighting control circuit 112 , a storage circuit 103 and data Write circuit 104 .
  • the data writing circuit 104 is electrically connected to the first driving circuit 101 and is configured to write a data voltage to the first driving circuit 101 .
  • the data writing circuit 104 is electrically connected to the first end of the first driving circuit 101, the data line and the first scan line, so as to apply the data voltage provided by the data line under the control of the first scan signal provided by the first scan line Write to the first end of the first drive circuit 101 .
  • the data writing circuit 104 may also write the data voltage into the second driving circuit 111 .
  • the first driving circuit 101 and the second driving circuit 111 are configured to drive the light-emitting element 200 to emit light based on the same data voltage, so that the light-emitting element 200 emits light corresponding to the same data voltage.
  • the control terminal of the first driving circuit 101 and the control terminal of the second driving circuit 111 are electrically connected, so that the first driving circuit 101 and the second driving circuit 111 can be controlled by the same signal.
  • a driving circuit 101 and a second driving circuit 111 can share the same data writing circuit 104, storage circuit 103, threshold compensation circuit (described below) and first initialization circuit (described below), thereby reducing the number of pixel circuits number of transistors and capacitors, saving costs.
  • the present disclosure is not limited thereto.
  • the control terminal of the first driving circuit 101 and the control terminal of the second driving circuit 111 are not connected. However, at this time, the control terminal of the first driving circuit 101 and the second driving circuit The control terminal of the driving circuit 111 can receive the same signal.
  • the first light emission control circuit 102 is electrically connected to a first power supply line (not shown in FIG. 1A ), the first driving circuit 101 and the light emitting element 200 , and is configured to control the communication between the first driving circuit 101 and the light emitting element 200 The connection is turned on or off and the connection between the first driving circuit 101 and the first power line is controlled to be turned on or off.
  • the first light emission control circuit 102 is electrically connected to the first and second ends of the first driving circuit 101 , the first pole of the light emitting element 200 , the first light emission control signal line and the second light emission control signal line.
  • the first lighting control circuit 102 is configured to control whether the first driving circuit 101 drives the light-emitting element under the control of the first lighting control signal provided by the first lighting control signal line and the second lighting control signal provided by the second lighting control signal line 200 to emit light. For example, when the first lighting control circuit 102 controls the connection between the first driving circuit 101 and the light-emitting element 200 to be turned on and controls the connection between the first driving circuit 101 and the first power line to be turned on, then this When the first driving circuit 101 drives the light-emitting element 200 to emit light; when the first light-emitting control circuit 102 controls the connection between the first driving circuit 101 and the light-emitting element 200 to disconnect and/or controls the first driving circuit 101 and the first power supply When the connection between the lines is disconnected, at this time, the first driving circuit 101 does not drive the light-emitting element 200 to emit light.
  • the second light emission control circuit 112 is electrically connected to a second power supply line (not shown in FIG. 1A ), the second driving circuit 111 and the light emitting element 200 , and is configured to control the communication between the second driving circuit 111 and the light emitting element 200 .
  • the connection is turned on or off and the connection between the second driving circuit 111 and the second power line is controlled to be turned on or off.
  • the second light emitting control circuit 112 is electrically connected to the first and second ends of the second driving circuit 111, the first pole of the light emitting element 200, the third light emitting control signal line and the fourth light emitting control signal line.
  • the second lighting control circuit 112 is configured to control whether the second driving circuit 111 drives the light-emitting element under the control of the third lighting control signal provided by the third lighting control signal line and the fourth lighting control signal provided by the fourth lighting control signal line 200 to emit light. For example, when the second lighting control circuit 112 controls the connection between the second driving circuit 111 and the light-emitting element 200 to be turned on and controls the connection between the second driving circuit 111 and the second power line to be turned on, then this When the second drive circuit 111 drives the light-emitting element 200 to emit light; when the second light-emitting control circuit 112 controls the connection between the second drive circuit 111 and the light-emitting element 200 to disconnect and/or controls the second drive circuit 111 and the second power supply When the connection between the lines is disconnected, at this time, the second driving circuit 111 does not drive the light-emitting element 200 to emit light.
  • the first power cord and the second power cord are electrically connected to each other; in other embodiments, the first power cord and the second power cord are not electrically connected to each other, however, the first power cord provides The power supply voltage is the same as that provided by the second power line.
  • the first power line and the second power line can be connected to the same power terminal to receive the same power voltage, so as to save the number of power terminals and save the production cost.
  • the storage circuit 103 is electrically connected to the control terminal of the first driving circuit 101 and the control terminal of the second driving circuit 111 , and is configured to maintain the voltages of the control terminal of the first driving circuit 101 and the control terminal of the second driving circuit 11 .
  • the second electrode of the light emitting element 200 is electrically connected to a third power supply line (not shown in FIG. 1A ).
  • both the first power line and the second power line may provide a constant high power supply voltage
  • the third power line may provide a constant low power supply voltage, or may be grounded, or the like.
  • the present disclosure is not limited thereto.
  • the first power supply line and the second power supply line both provide a constant low power supply voltage
  • the third power supply line may provide a constant high power supply voltage.
  • the light emitting element 200 may be a light emitting diode or the like.
  • the light emitting diode may be an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), or the like.
  • the light-emitting element 200 is configured to receive a light-emitting signal (eg, may be a current signal) during operation, and emit light with an intensity corresponding to the light-emitting signal.
  • a light-emitting signal eg, may be a current signal
  • the pixel circuit 100 provided by the embodiment of the present disclosure can be applied to a display panel, such as an active matrix organic light emitting diode (AMOLED) display panel or an active matrix quantum dot light emitting diode (AMQLED) display panel.
  • a display panel such as an active matrix organic light emitting diode (AMOLED) display panel or an active matrix quantum dot light emitting diode (AMQLED) display panel.
  • AMOLED active matrix organic light emitting diode
  • AMQLED active matrix quantum dot light emitting diode
  • the pixel circuit 100 further includes a threshold compensation circuit 105 .
  • the threshold compensation circuit 105 is electrically connected to the control terminal of the first driving circuit 101 and the control terminal of the second driving circuit 102 , and is configured to perform threshold compensation on the first driving circuit 101 .
  • the threshold compensation circuit 105 is electrically connected to the control terminal and the second terminal of the first drive circuit 101, the control terminal of the second drive circuit 111 and the second scan line, and is configured to provide a second scan line on the second scan line Under the control of the signal, the compensation voltage based on the data voltage is written into the control terminal of the first driving circuit 101 and the control terminal of the second driving circuit 111 .
  • the first storage circuit 103 can store the compensation voltage and keep the compensation voltage at the control terminal of the first driving circuit 101 and the control terminal of the second driving circuit 111 .
  • the compensation voltage can control the degree of conduction between the first driving circuit 101 and the second driving circuit 111, thereby controlling the driving current for driving the light element 200 to emit light.
  • the threshold compensation circuit 105 may also perform threshold compensation on the second driving circuit 111 .
  • the pixel circuit 100 further includes a first initialization circuit 106 and a second initialization circuit 107 .
  • the first initialization circuit 106 is electrically connected to the control terminal of the first driving circuit 101 and the control terminal of the second driving circuit 111 , and is configured to perform operation on the control terminal of the first driving circuit 101 and the control terminal of the second driving circuit 111 . initialization.
  • the first initialization circuit 106 is electrically connected to the control terminal of the first driving circuit 101, the control terminal of the second driving circuit 111, the first initialization control signal line and the first initialization voltage line, and is configured to be connected to the first initialization control signal line
  • the first initialization voltage provided by the first initialization voltage line is written into the control terminal of the first driving circuit 101 and the control terminal of the second driving circuit 111 under the control of the provided first initialization control signal, so as to realize the control of the first driving circuit 101
  • the control terminal of 111 and the control terminal of the second driving circuit 111 are initialized.
  • the second initialization circuit 107 is electrically connected to the first pole of the light emitting element 200 and is configured to initialize the first pole of the light emitting element 200 .
  • the second initialization circuit 107 is electrically connected to the first pole, the second initialization control signal line and the second initialization voltage line of the light emitting element 200, and is configured to be under the control of the second initialization control signal provided by the second initialization control signal line
  • the second initialization voltage provided by the second initialization voltage line is written into the first electrode of the light-emitting element 200 to initialize the first electrode of the light-emitting element 200 .
  • FIG. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • the circuit structure shown in FIG. 2 is a circuit structure of a specific implementation example of the pixel circuit shown in FIG. 1B .
  • the first driving circuit 101 includes a first driving transistor T11
  • the second driving circuit 111 includes a second driving transistor T12
  • the control end of the first drive circuit 101 includes the gate of the first drive transistor T11
  • the first end of the first drive circuit 101 includes the first pole of the first drive transistor T11
  • the second end of the first drive circuit 101 includes The second pole of the first drive transistor T11
  • the control end of the second drive circuit 111 includes the gate of the second drive transistor T12
  • the control end of the second drive circuit 111 includes the gate of the second drive transistor T12
  • the first terminal of 111 includes the first pole of the second driving transistor T12
  • the second terminal of the second driving circuit 111 includes the second pole of the second driving transistor T12.
  • the gate of the first driving transistor T11 can be used as the first terminal.
  • the control terminal of the driving circuit 101, the first terminal of the first driving transistor T11 is used as the first terminal of the first driving circuit 101, the second terminal of the first driving transistor T11 is used as the second terminal of the first driving circuit 101, the second driving The gate of the transistor T12 is used as the control terminal of the second driving circuit 111 , the first terminal of the second driving transistor T12 is used as the first terminal of the second driving circuit 111 , and the second terminal of the second driving transistor T12 is used as the second driving circuit 111 the second end.
  • the first driving transistor T11 and the second driving transistor T12 are the same, for example, the types and electrical parameters of the first driving transistor T11 and the second driving transistor T12 are the same, that is, the threshold voltage of the first driving transistor T11 and the The threshold voltages of the two driving transistors T12 are the same, so when the threshold compensation circuit 105 performs threshold compensation on the first driving transistor T11 of the first driving circuit 101, in fact, the threshold voltage of the second driving transistor T12 is also compensated.
  • the above compensation voltage may include the data voltage and the threshold voltage of the first driving transistor T11, for example, the above compensation voltage may be the sum of the data voltage and the threshold voltage of the first driving transistor T11.
  • the first driving transistor T11 and the second driving transistor T12 are both P-type transistors.
  • the gate of the first driving transistor T11 and the gate of the second driving transistor T12 are both electrically connected to the node N1
  • the first electrode of the first driving transistor T11 is electrically connected to the node N2
  • the second electrode of the first driving transistor T11 is electrically connected to the node N2. Electrically connected to node N3.
  • the first lighting control circuit 102 includes a first lighting control sub-circuit 1021 and a second lighting control sub-circuit 1022.
  • the first light-emitting control sub-circuit 1021 is connected to the first terminal of the first driving circuit 101 and the first power supply line VDD1, and is configured to realize the connection between the first terminal of the first driving circuit 101 and the first power supply line VDD1 The connection is made or disconnected.
  • the first light-emitting control sub-circuit 1021 is also electrically connected to the first light-emitting control signal line, so as to realize the connection between the first end of the first driving circuit 101 and the first power line VDD1 under the control of the first light-emitting control signal The connection is made or disconnected.
  • the second lighting control sub-circuit 1022 is electrically connected to the second terminal of the first driving circuit 101 and the first pole of the light-emitting element 200 and is configured to implement the second terminal of the first driving circuit 101 and the first pole of the light-emitting element 200 The connection between one pole is made or broken.
  • the second light-emitting control sub-circuit 1022 is also electrically connected to the second light-emitting control signal line, so as to realize the connection between the second end of the first driving circuit 101 and the first pole of the light-emitting element 200 under the control of the second light-emitting control signal The connection between them is turned on or off.
  • the second lighting control circuit 112 includes a third lighting control sub-circuit 1121 and a fourth lighting control sub-circuit 1122 .
  • the third light emission control sub-circuit 1121 is connected to the first end of the second driving circuit 111 and the second power supply line VDD2, and is configured to realize the connection between the first end of the second driving circuit 111 and the second power supply line VDD2 The connection is made or disconnected.
  • the third light-emitting control sub-circuit 1121 is also electrically connected to the third light-emitting control signal line, so as to realize the connection between the first end of the second driving circuit 111 and the second power line VDD2 under the control of the third light-emitting control signal The connection is made or disconnected.
  • the fourth lighting control sub-circuit 1122 is electrically connected to the second terminal of the second driving circuit 111 and the first pole of the light-emitting element 200 and is configured to implement the second terminal of the second driving circuit 111 and the first pole of the light-emitting element 200 The connection between one pole is made or broken.
  • the fourth light-emitting control sub-circuit 1122 is also electrically connected to the fourth light-emitting control signal line, so as to realize the connection between the second end of the second driving circuit 111 and the first pole of the light-emitting element 200 under the control of the fourth light-emitting control signal The connection between them is turned on or off.
  • the first lighting control sub-circuit 1021 includes a first lighting control transistor T21
  • the second lighting control sub-circuit 1022 includes a second lighting control transistor T31
  • the third lighting control sub-circuit 1121 includes a third light-emitting control transistor T22
  • the fourth light-emitting control sub-circuit 1122 includes a fourth light-emitting control transistor T32
  • the data writing circuit 104 includes a data writing transistor T4
  • the storage circuit 103 includes a storage capacitor C
  • the threshold compensation circuit 105 includes a threshold Compensation transistor T5
  • the first initialization circuit 106 includes a first initialization transistor T6
  • the second initialization circuit 107 includes a second initialization transistor T7.
  • the first electrode of the data writing transistor T4 is electrically connected to the data line Vd to receive the data voltage
  • the second electrode of the data writing transistor T4 is electrically connected to the first electrode of the first driving transistor T11, that is, the node N2
  • the data writing The gate of the input transistor T4 is electrically connected to the first scan line G1 to receive the first scan signal.
  • the data writing transistor T4 is used for writing the data voltage to the first electrode of the first driving transistor T11 under the control of the first scan signal.
  • the first pole of the threshold compensation transistor T5 is electrically connected to the second pole of the first driving transistor T11, namely the node N3, and the second pole of the threshold compensation transistor T5 is electrically connected to the gate of the first driving transistor T11 and the second driving
  • the gate of the transistor T12, ie, the node N1, and the gate of the threshold compensation transistor T5 are electrically connected to the second scan line to receive the second scan signal.
  • the data writing transistor T4 and the threshold compensation transistor T5 may be turned on at the same time.
  • the first scan signal and the second scan signal may be the same.
  • the first scan line G1 and the second scan line G2 are the same signal line to transmit the same signal, thereby saving the number of signal lines, Reduce manufacturing costs.
  • the gate of the data writing transistor T4 and the gate of the threshold compensation transistor T5 may be electrically connected to the same signal line, eg, the first scan line G1, to receive the same signal.
  • the present disclosure is not limited thereto, the first scan line G1 and the second scan line G2 may also be different signal lines, so that the data writing transistor T4 and the threshold compensation transistor T5 can be controlled separately and independently, increasing the flexibility of controlling the pixel circuit sex.
  • the first scan signal and the second scan signal may also be different, as long as the first scan signal and the second scan signal can enable the data writing transistor T4 and the threshold compensation transistor T5 to be turned on at the same time.
  • the first electrode of the first light-emitting control transistor T21 is electrically connected to the first power supply line VDD1
  • the second electrode of the first light-emitting control transistor T21 is electrically connected to the first electrode of the first driving transistor T11
  • the first light-emitting control transistor T21 The gate of the is electrically connected to the first light emission control signal line EM1 to receive the first light emission control signal.
  • the first light-emitting control transistor T21 is turned on under the control of the first light-emitting control signal, the first power line VDD1 and the first electrode of the first driving transistor T11 are electrically connected.
  • the first electrode of the second light-emitting control transistor T31 is electrically connected to the second electrode of the first driving transistor T11, namely the node N3, the second electrode of the second light-emitting control transistor T31 is electrically connected to the first electrode of the light-emitting element 200, That is, at the node N4, the gate of the second light emission control transistor T31 is electrically connected to the second light emission control signal line EM2 to receive the second light emission control signal.
  • the second light-emitting control transistor T31 is turned on under the control of the second light-emitting control signal, the second electrode of the first driving transistor T11 and the first electrode of the light-emitting element 200 are electrically connected.
  • the first electrode of the third light-emitting control transistor T22 is electrically connected to the second power supply line VDD2
  • the second electrode of the third light-emitting control transistor T22 is electrically connected to the first electrode of the second driving transistor T12
  • the third light-emitting control transistor T22 The gate of the is electrically connected to the third lighting control signal line EM3 to receive the third lighting control signal.
  • the third light-emitting control transistor T22 is turned on under the control of the third light-emitting control signal, the second power supply line VDD2 and the first electrode of the second driving transistor T12 are electrically connected.
  • the first electrode of the fourth light-emitting control transistor T32 is electrically connected to the second electrode of the second driving transistor T12
  • the second electrode of the fourth light-emitting control transistor T32 is electrically connected to the first electrode of the light-emitting element 200
  • the fourth light-emitting control transistor T32 is electrically connected to the first electrode of the light-emitting element 200.
  • the gate of the transistor T32 is electrically connected to the fourth light emission control signal line EM4 to receive the fourth light emission control signal.
  • the first light emission control transistor T21, the second light emission control transistor T31, the third light emission control transistor T22, and the fourth light emission control transistor T32 may be turned on at the same time, so that the first driving transistor T11 and the second driving transistor T12 are simultaneously driven
  • the light-emitting element 200 emits light.
  • the first lighting control signal, the second lighting control signal, the third lighting control signal and the fourth lighting control signal may be the same, for example, the first lighting control signal line EM1, the second lighting control signal line EM2, the third light-emitting control signal line EM3 and the fourth light-emitting control signal line EM4 are the same signal line, that is, the gate of the first light-emitting control transistor T21, the gate of the second light-emitting control transistor T31, and the third light-emitting control transistor
  • the gate of T22 and the gate of the fourth light emission control transistor T32 may be electrically connected to the same signal line, such as the first light emission control signal line EM1, to receive the same signal (for example, the first light emission control signal), at this time,
  • the second light emission control signal line EM2, the third light emission control signal line EM3, and the fourth light emission control signal line EM4 may not be provided, thereby reducing the number of signal lines.
  • the gate of the first light-emitting control transistor T21, the gate of the second light-emitting control transistor T31, the gate of the third light-emitting control transistor T22, and the gate of the fourth light-emitting control transistor T32 may also be electrically connected to different Signal lines, that is, the gate of the first light emission control transistor T21 is electrically connected to the first light emission control signal line EM1, the gate of the second light emission control transistor T31 is electrically connected to the second light emission control signal line EM2, and the third light emission control transistor T31 is electrically connected to the second light emission control signal line EM2.
  • the gate of T22 is electrically connected to the third light-emitting control signal line EM3, the gate of the fourth light-emitting control transistor T32 is electrically connected to the fourth light-emitting control signal line EM4, and the first light-emitting control signal line EM1, the second light-emitting control signal line
  • the signals transmitted by the EM2, the third lighting control signal line EM3 and the fourth lighting control signal line EM4 are the same.
  • first lighting control signal, the second lighting control signal, the third lighting control signal, and the fourth lighting control signal may also be different, which are not limited in the embodiments of the present disclosure.
  • the first electrode of the first initialization transistor T6 is electrically connected to the first initialization voltage line Vinit1
  • the second electrode of the first initialization transistor T6 is electrically connected to the gate of the first driving transistor T11 and the gate of the second driving transistor T12
  • the gate of the first initialization transistor T6 is electrically connected to the first initialization control signal line Rst1.
  • the first initialization transistor T6 When the first initialization transistor T6 is turned on under the control of the first initialization control signal provided by the first initialization control signal line Rst1, the first initialization transistor T6 transmits the first initialization voltage provided by the first initialization voltage line Vinit1 to the first initialization voltage line Vinit1.
  • the gate of the driving transistor T11 and the gate of the second driving transistor T12 are used to initialize the gate of the first driving transistor T11 and the gate of the second driving transistor T12.
  • the first electrode of the second initialization transistor T7 is electrically connected to the second initialization voltage line Vinit2
  • the second electrode of the second initialization transistor T7 is electrically connected to the first electrode of the light-emitting element 200, that is, the node N4, and the second initialization transistor T7
  • the gate of is electrically connected to the second initialization control signal line Rst2.
  • the first initialization control signal and the second initialization control signal may be the same.
  • the first initialization control signal line Rst1 and the second initialization control signal line Rst2 are the same signal line, that is, The gate of the first initialization transistor T6 and the gate of the second initialization transistor T7 may be electrically connected to the same signal line, eg, the first initialization control signal line Rst1, to receive the same signal (eg, the first initialization control signal), At this time, the second initialization control signal line Rst2 may not be provided, thereby reducing the number of signal lines; in other examples, the gate of the first initialization transistor T6 and the gate of the second initialization transistor T7 may also be electrically connected to Different signal lines, ie the gate of the first initialization transistor T6 is electrically connected to the first initialization control signal line Rst1, the gate of the second initialization transistor T7 is electrically connected to the second initialization control signal line Rst2, and the first initialization control signal The line Rst1 and the second
  • the first initialization control signal and the second initialization control signal may be different.
  • the first initialization control signal line Rst1 and the second initialization control signal line Rst2 are different signal lines, so that the The first initialization transistor T6 and the second initialization transistor T7 are controlled separately and independently, which increases the flexibility of controlling the pixel circuit.
  • the display panel is provided with a plurality of sub-pixels arranged in N rows and M columns, a second initialization circuit in the pixel circuit of the sub-pixel in the n-th row in the N rows, and a second initialization circuit in the N-th row in the N row.
  • the first initialization circuit in the pixel circuit of the sub-pixel in the row (n+1) is controlled by the same initialization control signal line, that is, connected with the second initialization circuit in the pixel circuit of the sub-pixel in the nth row.
  • the second initialization control signal line and the first initialization control signal line connected to the first initialization circuit in the pixel circuit of the sub-pixel in the (n+1)th row are the same signal line, so that the number of signal lines can be saved.
  • N, M, and n are positive integers, and n is less than N.
  • the connected first initialization voltage lines Vinit1 are the same signal line.
  • the first initialization voltage line Vinit1 and the second initialization voltage line Vinit2 may transmit a constant DC voltage.
  • the first initialization voltage line Vinit1 and the second initialization voltage line Vinit2 may be electrically connected to the high voltage terminal, or may be electrically connected to the low voltage terminal, as long as they can provide the first initialization voltage and the second initialization voltage to the gate of the first driving transistor T11
  • the gate electrode, the gate electrode of the second driving transistor T12 and the first electrode of the light emitting element 200 may be initialized, which is not limited in the present disclosure.
  • the first electrode of the storage capacitor C is electrically connected to the gate of the first driving transistor T11 and the gate of the second driving transistor T12, and the second electrode of the storage capacitor C is electrically connected to the first power line VDD1.
  • the second pole of the storage capacitor C may also be electrically connected to the second power line VDD2.
  • the two driving circuits ie the first driving transistor T11 and the second driving transistor T12
  • Both are connected to the light-emitting element 200 , so that the purpose of theoretically increasing the driving current flowing through the light-emitting element 200 is twice that of the original driving circuit.
  • the threshold compensation circuit 105 , the first initialization circuit 106 and the second initialization circuit 107 are only illustrative, the first driving circuit 101 , the second driving circuit 111 , the first lighting control circuit 102 , the second lighting control circuit 112 , the storage circuit 103.
  • the specific structures of the data writing circuit 104, the threshold compensation circuit 105, the first initialization circuit 106, and the second initialization circuit 107 can be set according to actual application requirements, which are not specifically limited in the embodiments of the present disclosure.
  • the pixel circuit 100 may further include more or less circuits according to actual conditions.
  • the pixel circuit 100 further includes a power supply connection line VDDc1 .
  • the first power supply line VDD1 and the second power supply line VDD2 are electrically connected to each other through the power supply connection line VDDc1.
  • the timing diagram of the pixel circuit may be set according to actual requirements, which is not specifically limited in the embodiments of the present disclosure.
  • various working stages of the pixel circuit will be briefly described.
  • the first initialization transistor T6 and the second initialization transistor T7 are turned on, and the first initialization voltage is transmitted to the gate of the first driving transistor T11 and the second driving transistor via the first initialization transistor T6
  • the voltage of the gate of the transistor T12, and thus the gate of the first driving transistor T11 and the gate of the second driving transistor T12, is initialized to the first initialization voltage.
  • the second initialization voltage is transmitted to the first electrode of the light emitting element 200 via the second initialization transistor T7, so that the voltage of the first electrode of the light emitting element 200 is initialized to the second initialization voltage.
  • the first driving transistor T11 and the second driving transistor T12 may be in an on state.
  • the data writing transistor T4 and the threshold compensation transistor T5 are turned on, and the data voltage is sequentially written into the node N1 through the data writing transistor T4 and the threshold compensation transistor T5, that is, The gate of the first driving transistor T11 and the gate of the second driving transistor T12, when the voltage at the node N1 becomes the sum of the data voltage Vdata and the threshold voltage Vth1 of the first driving transistor T11 (ie Vdata+Vth1), the first Once the drive transistor T11 is turned off, the data writing and compensation phase ends.
  • the first driving transistor T11 and the second driving transistor T12 transmit the driving current to the light emitting element 200 to drive the light emitting element 200 to emit light in the light emitting stage.
  • the first light-emitting control transistor T21, the second light-emitting control transistor T31, the third light-emitting control transistor T22 and the fourth light-emitting control transistor T32 are all turned on, and the first power line VDD1 outputs the first light-emitting
  • the power supply voltage can be transmitted to the first pole of the first driving transistor T11 via the first light-emitting control transistor T21, the voltage of the first pole of the first driving transistor T11 becomes the first power supply voltage, and the first power supply output by the first power supply line VDD1
  • the voltage can be transmitted to the first pole of the first driving transistor T11 through the first light-emitting control transistor T21, the voltage of the first pole of the first driving transistor T11 becomes the first power supply voltage, and the second power supply voltage output by the second power
  • the driving current I OLED flowing to the light-emitting element 200 can be expressed as:
  • I OLED represents the driving current
  • K1 is the process constant of the first driving transistor T11
  • Vgs1 is the voltage difference between the gate and the first electrode of the first driving transistor T11 in the light-emitting stage
  • Vth1 is the voltage difference of the first driving transistor T11 Threshold voltage
  • K2 is the process constant of the second driving transistor T12
  • Vgs2 is the voltage difference between the gate and the first electrode of the second driving transistor T12 in the light-emitting stage
  • Vth2 is the threshold voltage of the second driving transistor T12
  • Vth1 and Vth2 is the same
  • Vdd1 represents the first power supply voltage
  • Vdd2 represents the second power supply voltage
  • Vdata represents the data voltage.
  • the driving current I OLED is not affected by the threshold voltages of the first driving transistor T11 and the second driving transistor T12, but is only related to the first/second power supply voltage and the data voltage Vdata.
  • the data voltage Vdata is directly transmitted by the data line Vd, which has nothing to do with the threshold voltages of the first driving transistor T11 and the second driving transistor T12, so that the first driving transistor T11 and the second driving transistor T11 due to the process and long-term operation can be solved.
  • the problem of the threshold voltage drift of the transistor T12 ensures the accuracy of the driving current I OLED , ensures the normal operation of the light-emitting element 200, improves the uniformity of the display image, and improves the display effect.
  • ⁇ n1 is the first drive
  • the electron mobility of the transistor T11, C ox1 is the gate unit capacitance of the first driving transistor T11
  • W1 is the channel width of the first driving transistor T11
  • L1 is the channel length of the first driving transistor T11
  • ⁇ n2 is the first driving transistor T11.
  • Cox2 is the gate unit capacitance of the second driving transistor T12
  • W2 is the channel width of the second driving transistor T12
  • L2 is the channel length of the second driving transistor T12.
  • the pixel circuit 100 is located on a base substrate (to be described below), the pixel circuit 100 has a first functional layer and a second functional layer, the first functional layer and the second functional layer are located on the base substrate, and are perpendicular to the In the direction of the base substrate, the first functional layer is located on the side of the second functional layer away from the base substrate, the first power supply line VDD1 and the second power supply line VDD2 are located in the first functional layer, and the power supply connection line VDDc1 is located in the second functional layer.
  • Floor to be described below
  • the pixel circuit 100 has a first functional layer and a second functional layer
  • the first functional layer and the second functional layer are located on the base substrate, and are perpendicular to the In the direction of the base substrate
  • the first functional layer is located on the side of the second functional layer away from the base substrate
  • the first power supply line VDD1 and the second power supply line VDD2 are located in the first functional layer
  • the power supply connection line VDDc1 is located in the second functional
  • the power supply connection line VDDc1 is located at a layer different from the layers where the first power supply line VDD1 and the second power supply line VDD2 are located, and the power supply connection line VDDc1 is electrically connected to the first power supply line VDD1 and the second power supply line VDD2 through two via holes, respectively. connect.
  • the pixel circuit 100 further includes a first gate connection line, a second gate connection line and a third gate connection line (not shown in FIG. 2 ).
  • the control end of the first drive circuit 101 and the control end of the second drive circuit 111 are electrically connected through the first gate connection line, the second gate connection line and the third gate connection line, and the control end of the first drive circuit 101 It is electrically connected to the first gate connection line, the control terminal of the second driving circuit 111 is electrically connected to the second gate connection line, and the third gate connection line is used to electrically connect the first gate connection line and the second gate connection line. line, so as to realize the electrical connection between the control terminal of the first driving circuit 101 and the control terminal of the second driving circuit 111 .
  • the gate of the first driving transistor T11 is electrically connected to the first gate connection line
  • the second driving transistor T11 is electrically connected to the first gate connection line
  • the gate of the driving transistor T12 is electrically connected to the second gate connection line.
  • the first gate connection line and the second gate connection line are located in the first functional layer, and the third gate connection line is located in the second functional layer, that is, the third gate connection line is located in the first gate connection line On a layer different from the layer where the second gate connection line is located, the third gate connection line is respectively connected to the first gate connection line and the second gate connection line through two via holes.
  • the pixel circuit 100 further has a third functional layer, the first functional layer, the second functional layer and the third functional layer are stacked on each other, and the third functional layer is also located on the base substrate and in a direction perpendicular to the base substrate
  • the second functional layer is located between the first functional layer and the third functional layer, the second functional layer is located on the side of the third functional layer away from the substrate substrate, and the first functional layer is located on the side of the second functional layer away from the substrate. side of the substrate.
  • the signal line EM3 and the fourth light emission control signal line EM4 are located in the third functional layer; the data line Vd is located in the first functional layer, and the first initialization voltage line Vinit1 and the second initialization voltage line Vinit2 are located in the second functional layer.
  • the first functional layer, the second functional layer and the third functional layer will be described in detail below, and will not be repeated here.
  • the first functional layer can be a source-drain metal layer
  • the second functional layer can be a second functional layer
  • the gate metal layer, and the third functional layer can be the first gate metal layer.
  • FIG. 3A is a schematic plan view of a display substrate according to some embodiments of the disclosure
  • FIG. 3B is a schematic diagram of the arrangement of sub-pixels on a display substrate according to some embodiments of the disclosure.
  • the display substrate has a first side for display (ie, the display side) and a second side (ie, the non-display side, also referred to as the back side) opposite the first side.
  • the display substrate further includes a base substrate comprising a first display area 10 and a second display area 20 at least partially surrounding (in the example shown in FIG.
  • the first The display area 10 allows light from the first side to be at least partially transmitted to the second side, that is, the first display area 10 is a transparent display area, and light can pass from the display side of the display substrate through the transparent display area to the non-display side, the non-display side
  • a sensor such as a camera and an infrared sensing device can be provided.
  • the sensor can be provided under the second display area 20. The sensor can collect and use the light transmitted from the first display area 10 to the non-display side to perform sensing work, such as Imaging, image capture, distance perception, light intensity perception and other operations.
  • the display substrate may include a plurality of sub-pixels, each of which includes the pixel circuit and the light-emitting element described in any one of the above.
  • the plurality of sub-pixels includes a plurality of first sub-pixels P1 and a plurality of second sub-pixels P2.
  • each first sub-pixel P1 includes a light-emitting element and a pixel circuit, and the light-emitting elements of the plurality of first sub-pixels P1 (the first display in FIG. 3B )
  • the white squares in the area 10 are located in the first display area 10
  • the pixel circuits of the plurality of first sub-pixels P1 ie, the gray squares in the second display area 20 in FIG. 3B
  • the pixel circuit of the first sub-pixel P1 is used to drive the light-emitting element of the first sub-pixel P1.
  • the pixel circuits of the plurality of first sub-pixels P1 in the first display area 10 are arranged in the second display area 20, thereby avoiding too many structures arranged in the first display area 10 or having an opaque structure, thereby preventing Ensuring the light transmittance of the first display area 10 is beneficial to transmit more light for being sensed by the sensor and improve the sensing quality.
  • each second sub-pixel P2 includes a light-emitting element and a pixel circuit electrically connected to the light-emitting element, and the pixel circuit of the second sub-pixel P2 is configured as The light-emitting element of the second sub-pixel P2 is driven to emit light.
  • the light-emitting elements and pixel circuits of the plurality of second sub-pixels P2 ie, the white box in the second display area 20 in FIG. 3B includes the light-emitting elements and pixel circuits of the second sub-pixels P2 ) are located in the second display area 20 .
  • the light-emitting element of the second sub-pixel P2 and the pixel circuit of the second sub-pixel P2 are stacked and disposed, and the light-emitting element of the second sub-pixel P2 is disposed in the pixel of the second sub-pixel P2 side of the circuit near the display side.
  • the light-emitting elements of the plurality of first sub-pixels P1 and the light-emitting elements of the plurality of second sub-pixels P2 are uniformly arranged in the first display area 10 and the second display area 20, respectively, so that the first display area 10 and The second display area 20 emits light and displays uniformly as a whole.
  • the base substrate further includes a third display area 30 at least partially surrounding the second display area 20 .
  • the first display area 10, the second display area 20 and the third display area 30 do not overlap each other.
  • the base substrate may further include a peripheral area, and the peripheral area at least partially surrounds the third display area 30 .
  • the third display area 30 is provided with a plurality of third sub-pixels P3 arranged in an array, and the light-emitting elements and pixel circuits of the plurality of third sub-pixels P3 are located in the third display area 30 .
  • the pixel circuit of the third sub-pixel P3 may include 7 transistors and a capacitor, such as the circuit formed by transistors T11, T21, T31, T4-T7 and capacitor C shown in FIG. 2, that is, a conventional 7T1C pixel circuit structure.
  • the distribution density per unit area of the light-emitting elements of the plurality of third sub-pixels P3 in the third display area 30 is greater than the distribution density per unit area of the light-emitting elements of the plurality of first sub-pixels P1 in the first display area 10, and is also greater than The distribution density per unit area of the light-emitting elements of the plurality of second sub-pixels P2 in the second display area 20 .
  • the distribution density per unit area of the light emitting elements in the first display area 10 is smaller than the distribution density per unit area of the light emitting elements in the second display area 20 .
  • the first display area 10 and the second display area 20 may be referred to as a low pixel density area of the display substrate, and correspondingly, the third display area 30 may be referred to as a high pixel density area of the display substrate.
  • the distribution density per unit area of the light emitting elements in the first display area 10 may also be equal to the distribution density per unit area of the light emitting elements in the second display area 20, which may be determined according to actual requirements, The embodiments of the present disclosure do not limit this.
  • the arrangement of the plurality of first sub-pixels P1/the plurality of second sub-pixels P2/the plurality of third sub-pixels P3 may refer to the conventional arrangement of sub-pixels, such as GGRB, RGBG, RGB, etc.
  • the embodiment does not limit this.
  • the shape of the first display area 10 may be substantially circular or oval
  • the shape of the second display area 20 may be substantially a circle or oval rectangle with a hollow
  • the shape of the third display area 30 may be substantially It may be a rectangle with a hollowed-out rectangle, but embodiments of the present disclosure are not limited thereto.
  • the shapes of the first display area 10 , the second display area 20 and the third display area 30 may all be rectangles or other suitable shapes. It should be noted that although the shapes of the first display area 10 , the second display area 20 and the third display area 30 shown in FIG. 3A and FIG. 3B are all regular shapes, on the actual layout, the first display area The shapes of the area 10, the second display area 20 and the third display area 30 may be irregular, for example, the shape of the first display area 10 is actually an irregular circle.
  • FIG. 4A is a schematic diagram of the arrangement of a first repeating unit according to some embodiments of the present disclosure
  • FIG. 4B is a schematic diagram of the arrangement of a second repeating unit according to some embodiments of the present disclosure
  • FIG. 4D is a schematic diagram of another arrangement of pixel regions provided by some embodiments of the present disclosure.
  • the first display region 10 includes a plurality of pixel regions PD corresponding to the pixel circuits of a plurality of first sub-pixels and a plurality of second sub-pixels one-to-one, and the plurality of pixel regions PD are arranged in a plurality of rows Multi-column, FIG. 4C shows pixel regions PD with four rows and four columns.
  • the first direction X is the row direction of the plurality of pixel regions PD
  • the second direction Y is the column direction of the plurality of pixel regions PD, for example, the first direction X and the second direction Y are perpendicular to each other.
  • each pixel region PD of the plurality of pixel regions PD includes a first sub-region PD1 and a second sub-region PD2 that do not overlap with each other. It should be noted that the shaded rectangular area in FIG. 4C represents the second sub-area PD2.
  • the first driving circuit, the first light emission control circuit, the storage circuit and the data writing circuit in the pixel circuit 100 are located in the first sub-region PD1 of the corresponding pixel region PD, for example, the first initialization circuit, The second initialization circuit and the threshold compensation circuit are also located in the first sub-region PD1 of the corresponding pixel region PD; the second driving circuit and the second light-emitting control circuit in the pixel circuit 100 are located in the second sub-region PD2 of the corresponding pixel region PD.
  • the first driving transistor T11, the first light emission control transistor T21, the second light emission control transistor T31, the data writing transistor T4, the threshold compensation transistor T5, the first initialization transistor T6 and the second initialization transistor T7 are located in the corresponding pixels
  • the first sub-region PD1 of the region PD, and the second driving transistor T12, the third light-emitting control transistor T22 and the fourth light-emitting control transistor T32 are located in the second sub-region PD2 of the corresponding pixel region PD.
  • the area of the first sub-region PD1 may be equal to the area of the second sub-region PD2, but the present disclosure is not limited thereto, and the area of the first sub-region PD1 and the area of the second sub-region PD2 are based on actual conditions Sure.
  • the first sub-region PD1 of each pixel region PD includes first and second sides opposite to each other in the first direction X, for example, the first sub-region PD1 of the first sub-region PD1
  • the side is the left side in FIGS. 4A to 4C
  • the second side of the first sub-region PD1 is the right side in FIGS. 4A to 4C . It should be noted that “left side” and “right side” are divided from the perspective of the viewer.
  • pixel circuits of a plurality of first sub-pixels P1 constitute a plurality of first repeating units RP1
  • pixel circuits of a plurality of second sub-pixels P2 constitute a plurality of second repeating units RP2.
  • each first repeating unit RP1 includes pixel circuits of four first sub-pixels arranged in two rows and two columns
  • each second repeating unit RP2 includes pixels of four second sub-pixels arranged in two rows and two columns circuit.
  • the pixel circuits in the pixel region PD corresponding to the pixel circuits of the first sub-pixel P1 in the first row and the first column are located in the pixel region PD.
  • the second sub-region PD2 is located on the first side of the first sub-region PD1; among the pixel circuits of the four first sub-pixels P1, the pixel circuits in the pixel region PD corresponding to the pixel circuits of the first sub-pixel P1 in the second row and the first column are located in the pixel region PD.
  • the second sub-region PD2 is located on the first side of the first sub-region PD1; among the pixel circuits of the four first sub-pixels P1, the pixel circuits in the pixel region PD corresponding to the pixel circuits of the first sub-pixel P1 in the first row and the second column are located in the pixel region PD.
  • the second sub-region PD2 is located on the second side of the first sub-region PD1; among the pixel circuits of the four first sub-pixels P1, the pixel circuits in the pixel region PD corresponding to the pixel circuits of the first sub-pixel P1 in the second row and second column are located in the pixel region PD.
  • the second sub-region PD2 is located on the second side of the first sub-region PD1. That is, in the first repeating unit RP1, in the first direction X, the four first sub-regions PD1 are located between the four second sub-regions PD2.
  • the pixel circuits in the pixel region PD corresponding to the pixel circuits of the second sub-pixel P2 in the first row and the first column are located in the pixel region PD.
  • the second sub-region PD2 is located on the second side of the first sub-region PD1; among the pixel circuits of the four second sub-pixels P2, the pixel circuits in the pixel region PD corresponding to the pixel circuits of the second sub-pixel P2 in the second row and the first column are located in the pixel region PD.
  • the second sub-region PD2 is located on the second side of the first sub-region PD1; among the pixel circuits of the four second sub-pixels P2, the pixel circuits in the pixel region PD corresponding to the pixel circuits of the second sub-pixel P2 in the first row and the second column are located in the pixel region PD.
  • the second sub-region PD2 is located on the first side of the first sub-region PD1; among the pixel circuits of the four second sub-pixels P2, the pixel circuits in the pixel region PD corresponding to the pixel circuits of the second sub-pixel P2 in the second row and second column are located in the pixel region PD.
  • the second sub-region PD2 is located on the first side of the first sub-region PD1. That is, in the second repeating unit RP2, in the first direction X, the four second sub-regions PD2 are located between the four first sub-regions PD1.
  • a plurality of first repeating units RP1 are arranged at intervals, and a plurality of second repeating units RP2 are also arranged at intervals; in the second direction On Y, a plurality of first repeating units RP1 are arranged at intervals, and a plurality of second repeating units RP2 are also arranged at intervals; that is, in the first direction X, there is a space between any two adjacent first repeating units RP1.
  • the second repeating unit RP2 there is a first repeating unit RP1 between any two adjacent second repeating units RP2; similarly, in the second direction Y, between any two adjacent first repeating units RP1 There is one second repeating unit RP2, and there is one first repeating unit RP1 between any two adjacent second repeating units RP2.
  • a plurality of first repeating units RP1 and a plurality of second repeating units RP2 constitute a plurality of repeating unit groups
  • each repeating unit group in the plurality of repeating unit groups includes two first repeating units RP1 and two second repeating units Unit RP2, namely two first repeating units RP1 and two second repeating units RP2, constitute a repeating unit group, that is, each repeating unit group includes 16 pixel regions
  • FIG. 4C shows one repeating unit group.
  • a plurality of repeating unit groups are arranged in an array. In each repeating unit group, two first repeating units RP1 and two second repeating units RP2 are arranged in two rows and two columns.
  • the two first repeating units RP1 are located in the first The row and the second column and the second row and the first column
  • the two second repeating units RP2 are respectively located in the first row and the first column and the second row and the second column.
  • the embodiments of the present disclosure are not limited thereto.
  • the two first repeating units RP1 are located in the first row, the first column, and the second row, the second column, respectively
  • the two second repeating units RP2 is located in the first row, second column and the second row, first column, respectively.
  • the first repeating unit RP1 and the second repeating unit RP2 among the four first subpixels P1, the first subpixel P1 and the four second subpixels P2 located in the first row and the first column are located in the first row.
  • the second sub-pixel P2 in the first column is a red sub-pixel; among the four first sub-pixels P1, the first sub-pixel P1 in the second row and the first column and the four second sub-pixels P2 are in the second row and the first sub-pixel P2.
  • the second sub-pixel P2 in the column is a blue sub-pixel; the first sub-pixel P1 in the first row and the second column in the four first sub-pixels P1, and the first sub-pixel P1 in the second row and the second column in the four first sub-pixels P1
  • the first sub-pixel P1, the second sub-pixel P2 located in the first row and the second column of the four second sub-pixels P2, and the second sub-pixel P2 located in the second row and the second column of the four second sub-pixels P2 are green subpixels.
  • the shapes of the pixel region PD, the first sub-region PD1 and the second sub-region PD2 shown in FIGS. 4A to 4D are all regular rectangles, on the actual layout, the pixel region PD, the first sub-region PD1 and the second sub-region PD2 are all regular rectangles.
  • the shapes of the first sub-region PD1 and the second sub-region PD2 are irregular, and the first sub-region PD1 and the second sub-region PD2 may have overlapping portions or may be spaced apart from each other.
  • the third display area 30 includes a plurality of pixel areas corresponding to the pixel circuits of the plurality of third sub-pixels one-to-one, and the area of the pixel area corresponding to the pixel circuits of the third sub-pixel P3 is smaller than that of the first sub-pixel P1/second
  • the area of the pixel region PD corresponding to the pixel circuit of the sub-pixel P2 for example, the area of the pixel region corresponding to the pixel circuit of the third sub-pixel P3 is the pixel region PD corresponding to the pixel circuit of the first sub-pixel P1/second sub-pixel P2 half of the area.
  • a plurality of data lines are further disposed on the display substrate.
  • the plurality of data lines include a first data line Vd1 to an eighth data line Vd8.
  • the data lines overlapping the first sub-region PD1 in the pixel region PD are electrically connected to the pixel circuits in the pixel region PD to provide data voltages. That is, as shown in FIG. 4C, in the second repeating unit RP2, the first data line Vd1 is connected with the pixel circuit of the second sub-pixel located in the first row and the first column and the second sub-pixel located in the second row and the first column.
  • the pixel circuits of the sub-pixels are electrically connected, and the fourth data line Vd4 is electrically connected to the pixel circuits of the second sub-pixels located in the first row and the second column and the pixel circuits of the second sub-pixels located in the second row and the second column;
  • the sixth data line Vd6 is electrically connected to the pixel circuit of the first sub-pixel located in the first row and the third column and the pixel circuit of the first sub-pixel located in the second row and the third column
  • the seventh data line Vd7 is electrically connected to the pixel circuit of the first sub-pixel located in the first row and the fourth column and the pixel circuit of the first sub-pixel located in the second row and the fourth column.
  • the fifth data line Vd5 is electrically connected to the pixel circuit of the second sub-pixel located in the third row and the third column and the pixel circuit of the second sub-pixel located in the fourth row and the third column
  • the eighth data line Vd8 It is electrically connected to the pixel circuit of the second sub-pixel located in the third row and the fourth column and the pixel circuit of the second sub-pixel located in the fourth row and the fourth column
  • the second data line Vd2 is connected to the second sub-pixel located in the third row and the first column.
  • the pixel circuit of a sub-pixel is electrically connected to the pixel circuit of the first sub-pixel located in the fourth row and the first column, and the third data line Vd3 is connected to the pixel circuit of the first sub-pixel located in the third row and the second column and the pixel circuit of the first sub-pixel located in the fourth row and the second column.
  • the pixel circuits of the first sub-pixels in the row and the second column are electrically connected.
  • the first data line Vd1 to the eighth data line Vd8 extend along the second direction Y
  • the first data line Vd1 , the fourth data line Vd4 , the sixth data line Vd6 and the seventh data line Vd7 extend from the Extending from bottom to top
  • the second data line Vd2 , the third data line Vd3 , the fifth data line Vd5 and the eighth data line Vd8 extend from top to bottom.
  • the data line connected to the first subpixel passes through the first display area, then passes through the peripheral area, and finally extends to the pixel area of the pixel circuit of the corresponding first subpixel.
  • the light-emitting element of the first sub-pixel connected to the second data line Vd2 and the third data line Vd3 is located in the first display area 10, for example, located in the third row
  • the pixel circuits in the first column are used to drive the light emitting elements 201 in the first display area 10 to emit light
  • the pixel circuits in the third row and the second column are used to drive the light emitting elements 202 in the first display area 10 to emit light.
  • the pixel circuit located in the third row and the first column is electrically connected to the corresponding light-emitting element 201 through the connecting line CL1, thereby driving the corresponding light-emitting element 201 to emit light; the pixel circuit located in the third row and the second column is connected to the corresponding light-emitting element 201 through the connecting line CL2.
  • the elements 202 are electrically connected to drive the corresponding light-emitting elements 202 to emit light.
  • the second data line Vd2 passes through the first display area 10, then passes through the peripheral area, and finally extends to the pixel area of the pixel circuit located in the third row and the first column;
  • the third data line Vd3 passes through the first display area 10, Then, it passes through the peripheral area, and finally extends to the pixel area of the pixel circuit located in the third row and the second column.
  • the pixel circuit of the first sub-pixel is located in the second display area 20 (that is, the non-camera area), and the light-emitting element of the first sub-pixel is located in the first display area 10 (that is, the non-camera area).
  • camera area since the data lines (Vd1 to Vd8) are arranged in the first display area and the second display area from left to right (ie, the first direction X), they are in the non-camera area (for example, as shown in FIG. 4D ).
  • the left part of the second display area 20) - the camera area eg, the first display area 10 shown in FIG.
  • the data lines belonging to the camera area that is, the data lines corresponding to the first sub-pixel, for example, the data line Vd2, the data line Vd3, the data line Vd6 and the data line Vd7, etc.
  • the lower part corresponding to the camera area extends along the second direction Y and is introduced into the camera area. After passing through the camera area, it is re-introduced from the peripheral area (the upper part shown in FIG.
  • the rest of the data lines belonging to the non-camera area (that is, the data lines corresponding to the second sub-pixel, for example, the data line Vd1, the data line Vd4, the data line Vd5 and the data line Vd8, etc.)
  • the lower portion corresponding to the non-camera area shown in FIG. 4D extends along the second direction Y and is directly introduced into the pixel circuit of the second sub-pixel located in the non-camera area.
  • Table 1 below represents a conventional 7T1C pixel circuit (eg, elements other than the second driving transistor T12, the third emission control transistor T22, and the fourth emission control transistor T32 in the pixel circuit shown in FIG. 2) and the present disclosure The simulated current of the pixel circuit shown in FIG. 2 .
  • the R sub-pixel may represent the first sub-pixel located in the first row and the first column in the first repeating unit or the first sub-pixel located in the first row and the first column in the second repeating unit.
  • the B sub-pixel can represent the first sub-pixel located in the second row and the first column in the first repeating unit or the second sub-pixel located in the second row and the first column in the second repeating unit
  • the G1 sub-pixel can represent The first sub-pixel located in the first row and the second column in the first repeating unit or the second sub-pixel located in the first row and the second column in the second repeating unit
  • the G2 sub-pixel may indicate that the first repeating unit is located in the second row.
  • V N1 represents the voltage of the N1 node
  • V N2 represents the voltage of the N2 node
  • V N3 represents the voltage of the N3 node
  • V N4 represents the voltage of the N4 node.
  • the unit of voltage is volts (V).
  • the driving current of the R sub-pixel is 76.23 mA (mA)
  • the driving current of the G1 sub-pixel is 34.56 mA
  • the driving current of the B sub-pixel is 127 mA
  • the driving current of the G2 subpixel is 34.57mA
  • the driving current of the R subpixel is 174.59mA
  • the driving current of the G1 subpixel is 95.772mA
  • the driving current of the B subpixel is 320.28mA
  • the driving current of the G2 subpixel is 95.787mA; that is, the current difference of the driving current of the R subpixel is 229%, that is, for the R subpixel, the driving current obtained based on the pixel circuit shown in FIG.
  • the driving current obtained by the pixel circuit is 2.29 times; the current difference of the driving current of the G1 sub-pixel is 227.1%, that is, for the G1 sub-pixel, the driving current obtained based on the pixel circuit shown in Figure 2 is based on the conventional 7T1C pixel circuit.
  • the current is 2.271 times; the current difference of the driving current of the B sub-pixel is 252.2%, that is, for the B sub-pixel, the driving current obtained based on the pixel circuit shown in Figure 2 is 2.522 times that based on the conventional 7T1C pixel circuit; G2 The current difference of the driving current of the sub-pixels is 227.1%, that is, for the G2 sub-pixel, the driving current obtained based on the pixel circuit shown in FIG. 2 is 2.271 times the driving current obtained based on the conventional 7T1C pixel circuit.
  • the current difference is more than twice, in fact, in different simulations, the current difference is not the same, the current difference is more than double, more than twice, etc., all meet the expected requirements of.
  • FIGS. 5A to 5E are schematic structural diagrams of functional layers of a pixel circuit according to some embodiments of the present disclosure. The following describes the positional relationship of each element in the pixel circuit on the backplane with reference to FIGS. 5A to 5E .
  • the example shown in FIGS. 5A to 5E takes the pixel circuit 100 shown in FIG. 2 as an example.
  • the pixel circuit 100 has an active semiconductor layer 510 , a first functional layer 540 , a second functional layer 530 and a third functional layer 520
  • FIG. 5E shows the active semiconductor layer 510 , the first functional layer A schematic diagram of the stacked positional relationship of the layer 540 , the second functional layer 530 and the third functional layer 520 .
  • the structures of the active semiconductor layer 510 , the first functional layer 540 , the second functional layer 530 and the third functional layer 520 are described in detail below with reference to FIGS. 5A to 5E .
  • each layer structure shown in FIGS. 5A-5E corresponds to 16 subpixels in one repeating unit group.
  • the pixel circuit 100 includes a first driving transistor T11 , a second driving transistor T12 , a first light-emitting control transistor T21 , a second light-emitting control transistor T31 , a third light-emitting control transistor T22 , a fourth light-emitting control transistor T22 and a fourth light-emitting control transistor T21 shown in FIG. 2 .
  • 5A to 5E also show the first scan line G1 , the second scan line G1 , the first power supply line VDD1 , the second power supply line VDD2 , the power supply connection line VDDc1 , and the first light emission control signal line EM1 connected to the pixel circuit 100 .
  • the first scan line G1 and the second scan line G2 are the same signal line, and the first to fourth light emission control signal lines EM1 to EM4 are the same signal line. a signal line.
  • the first initialization control signal line Rst1 and the second initialization control signal line Rst2 are different signal lines, and the first initialization control signal line Rst1 is connected to the first initialization circuit and the pixel circuit located in the pixel circuit of the sub-pixel located in the nth row.
  • the second initialization circuit in the pixel circuit of the sub-pixel in the (n-1)th row (not shown in the figure), the second initialization control signal line Rst2 is connected to the second initialization circuit in the pixel circuit of the sub-pixel in the n-th row an initialization circuit and a first initialization circuit in the pixel circuit of the sub-pixel in the (n+1)th row.
  • the first initialization voltage line Vinit1 and the second initialization voltage line Vinit2 are different signal lines, and the first initialization voltage line Vinit1 is connected to the first initialization circuit in the pixel circuit of the sub-pixel located in the nth row and the pixel circuit located in the (th)th row.
  • the second initialization circuit in the pixel circuit of the sub-pixel in the n-1) row, the second initialization voltage line Vinit2 is connected to the second initialization circuit in the pixel circuit of the sub-pixel in the n-th row and the (n+1)-th initialization circuit in the pixel circuit of the sub-pixel in the n-th row.
  • each rectangular frame is a pixel area corresponding to one pixel circuit 100 .
  • FIG. 5A shows the active semiconductor layer 510 of the pixel circuit 100
  • FIG. 6A is an enlarged schematic view of the rectangular dotted frame in FIG. 5A
  • the active semiconductor layer 510 may be formed on the base substrate by patterning a semiconductor material.
  • the active semiconductor layer 510 can be used to fabricate the above-mentioned first driving transistor T11, second driving transistor T12, first light-emitting control transistor T21, second light-emitting control transistor T31, third light-emitting control transistor T22, fourth light-emitting control transistor T32, Active layers of the data writing transistor T4, the threshold compensation transistor T5, the first initialization transistor T6 and the second initialization transistor T7, each active layer may include a source region, a drain region, and a region between the source region and the drain region the channel region.
  • the active layers of the first driving transistor T11, the first light emission control transistor T21, the second light emission control transistor T31, the data writing transistor T4, the threshold compensation transistor T5, the first initialization transistor T6 and the second initialization transistor T7 are integrally provided
  • the active layers of the second driving transistor T12, the third light-emitting control transistor T22 and the fourth light-emitting control transistor T32 are integrally arranged, however, the channel regions of the respective transistors may become accessible due to the scan signals on the corresponding gates Conduction or return to non-conductivity, but the portion of the active layer between the transistors does not become conductive because it is not affected by the scan signal, so the integrated arrangement does not cause crosstalk between the transistors.
  • the second initialization transistor T7 shares the initialization voltage line and initialization with the first initialization transistor in the pixel circuit of the next adjacent row. Therefore, on the layout, the second initialization transistor T7 in the pixel circuit of the sub-pixel in the n-th row is located in the pixel area corresponding to the pixel circuit of the sub-pixel in the (n+1)-th row.
  • the shape of the active layer of the first driving transistor T11 and the shape of the active layer of the second driving transistor T12 may be the same.
  • the relative positional relationship between the active layers of the two light emission control transistors T31 and the active layer of the second driving transistor T12, the active layer of the third light emission control transistor T22 and the active layer of the fourth light emission control transistor T32 The relative positional relationship is the same.
  • the active semiconductor layer 510 can be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like.
  • the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the doped source region corresponds to the source of the transistor (eg, the first electrode of the transistor), and the doped drain region corresponds to the drain of the transistor (eg, the second electrode of the transistor).
  • the active layer of the data writing transistor T4 the active layer of the threshold compensation transistor T5, the active layer of the first initialization transistor T6 and the second initialization
  • the active layer of the transistor T7 is located on the first side, eg, the upper side, of the active layer of the first driving transistor T11; the active layer of the first light-emitting control transistor T21 and the active layer of the second light-emitting control transistor T31 are located on the first side
  • the second side eg, the lower side, of the active layer of the driving transistor T11.
  • the first side and the second side of the active layer of the first driving transistor T11 are opposite sides of the active layer of the first driving transistor T11 in the second direction Y that are opposite to each other.
  • the active layer of the third light emission control transistor T22 and the active layer of the fourth light emission control transistor T32 are located, for example, on the lower side of the active layer of the second driving transistor T12.
  • the active semiconductor layer 510 has a part of the region Ad, and the part of the region Ad is not used to form the active layer of the transistor, but to improve the first sub-region Ad in the pixel region
  • the area and the second sub-area are set for uniform etching; the shape of the partial area Ad is not limited to that shown in the figure, for example, it may also include a plurality of parts that are disconnected from each other.
  • a gate insulating layer (not shown) is formed on the above-mentioned active semiconductor layer 510 for protecting the above-mentioned active semiconductor layer 510 .
  • 5B shows a third functional layer 520 (eg, a first gate metal layer) of the pixel circuit 100 , the third functional layer 520 is disposed on the gate insulating layer so as to be insulated from the active semiconductor layer 510 .
  • FIG. 6B is an enlarged schematic view of the rectangular dotted box in FIG. 5B .
  • the third functional layer 520 may include a first electrode CC1 of the storage capacitor C, a first scan line G1, a second scan line G2, a first initialization control signal line Rst1, a second initialization control signal line Rst2, a first light emission control line Signal line EM1 to fourth light emission control signal line EM4, and first drive transistor T11, second drive transistor T12, first light emission control transistor T21, second light emission control transistor T31, third light emission control transistor T22, fourth light emission control
  • the first electrode CC1 of the storage capacitor C is multiplexed as the gate of the first driving transistor T11 , and the gate of the second driving transistor T12 is represented as g12 in FIGS. 5B and 6B . It should be noted that the storage capacitor C is only located in the first sub-region of the pixel region corresponding to the pixel circuit to which the storage capacitor C belongs.
  • the gate of the data writing transistor T4 may be a portion where the first scan line G1 overlaps with the active semiconductor layer 510 .
  • the threshold compensation transistor T5 may be a thin film transistor with a double gate structure, the first gate of the threshold compensation transistor T5 may be the portion where the second scan line G2 and the active semiconductor layer 510 overlap, and the second gate of the threshold compensation transistor T5
  • the pole may be a portion where the protrusion protruding from the second scan line G2 overlaps with the active semiconductor layer 510 .
  • the first scan line G1 and the second scan line G2 are the same signal line, that is, the first scan line G1 (ie, the second scan line G2 ) and the active semiconductor layer 510 have three overlapping portions.
  • the gate of the first emission control transistor T21 may be the first portion of the first emission control signal line EM1 overlapping the active semiconductor layer 310
  • the gate of the second emission control transistor T31 may be the first emission control signal line EM1
  • the gate of the third light-emitting control transistor T22 may be the third portion where the first light-emitting control signal line EM1 overlaps with the active semiconductor layer 310
  • the gate may be the fourth portion where the first light-emitting control signal line EM1 overlaps with the active semiconductor layer 310.
  • the first light-emitting control signal line EM1 overlaps with the active semiconductor layer 310.
  • the first part, the second part, the third part and the fourth part are arranged in sequence along the first direction X.
  • the first initialization transistor T6 can also be a thin film transistor with a double gate structure, and the two gates of the first initialization transistor T6 are respectively the first part and the second part where the first initialization control signal line Rst1 overlaps with the active semiconductor layer 510 .
  • the gate of the second initialization transistor T7 is the third part where the first initialization control signal line Rst1 overlaps with the active semiconductor layer 310 .
  • a first portion, a second portion and a third portion of the first initialization control signal line Rst1 overlapping with the active semiconductor layer 310 are sequentially arranged along the first direction X.
  • each dotted rectangle in FIG. 5A and FIG. 6A shows each part where the third functional layer 520 overlaps with the active semiconductor layer 510 in the direction perpendicular to the base substrate.
  • the control signal lines EM4 generally extend along the first direction X and are arranged along the second direction Y.
  • the first scan line G1/second scan line G2 is located between the first initialization control signal line Rst1 and the first to fourth light emission control signal lines EM1 to EM4, and the first to fourth light emission control signal lines EM1 to EM1
  • the signal line EM4 is located between the first scan line G1/second scan line G2 and the second initialization control signal line Rst2.
  • the first pole CC1 of the storage capacitor C is located between the first scan line G1/second scan line G2 and the first to fourth light emission control signal lines EM1 to EM4.
  • the protrusion protruding from the second scan line G2 is located on the side of the second scan line G2 away from the first to fourth light emission control signal lines EM1 to EM4.
  • the gate of the data writing transistor T4, the gate of the threshold compensation transistor T5, the gate of the first initialization transistor T6 and The gate of the second initialization transistor T7 is located on the first side, eg, the upper side, of the gate of the first driving transistor T11; the gate of the first light emission control transistor T21 and the gate of the second light emission control transistor T31 are located in the first driving transistor The second side, eg, the lower side, of the gate of the transistor T11.
  • the first side and the second side of the gate of the first driving transistor T11 are opposite sides of the gate of the first driving transistor T11 in the second direction Y to each other.
  • the gate of the third light emission control transistor T22 and the gate of the fourth light emission control transistor T32 are located, for example, on the lower side of the gate of the second driving transistor T12.
  • the gate of the threshold compensation transistor T5, the gate of the second light emission control transistor T31 and the gate of the second initialization transistor T7 Both are located on the third side, for example, the left side of the gate of the first driving transistor T11; the gate of the data writing transistor T4 and the gate of the first light-emitting control transistor T21 are both located on the third side of the gate of the first driving transistor T11.
  • Four sides, eg, right sides; the third and fourth sides of the gate of the first driving transistor T11 are opposite sides of the gate of the first driving transistor T11 in the first direction X.
  • the gate of the fourth light emission control transistor T32 is located, for example, to the left of the gate of the second driving transistor T12, and the gate of the third light emission control transistor T22 is located, for example, to the right of the gate of the second driving transistor T12.
  • a first insulating layer (not shown) is formed on the above-mentioned third functional layer 520 for protecting the above-mentioned third functional layer 520 .
  • 5C shows the second functional layer 530 of the pixel circuit 100.
  • the second functional layer 530 includes the second electrode CC2 of the storage capacitor C, the first initialization voltage line Vinit1, the second initialization voltage line Vinit2, and the power supply connection line VDDc1 ( For example, it may be referred to as a first power supply connection line VDDc1), a power supply connection line VDDc2 (eg, may be referred to as a second power supply connection line VDDc2 hereinafter), and a third gate connection line Gc3.
  • FIG. 6C is an enlarged schematic view of the rectangular dotted box in FIG. 5C .
  • the first power supply connection line VDDc1 is used to connect the first power supply line VDD1 and the second power supply line VDD2.
  • the second power supply connection line VDDc2 is used to connect the first power supply line VDD1 electrically connected to the pixel circuits of two adjacent sub-pixels in the same row.
  • the second power supply connection line VDDc2 is integrally formed with the second pole CC2 of the storage capacitor C.
  • the first power supply line VDD1 and the second power supply line VDD2 corresponding to each pixel circuit are connected through the first power supply connection line VDDc1 and the second power supply connection line VDDc2, so that all the first power supply line VDD1 and the second power supply line VDD2 are formed.
  • the network is beneficial to reduce the power supply voltage drop (IR drop), thereby improving the stability of the power supply voltages provided by the first power supply line VDD1 and the second power supply line VDD2.
  • the first pole CC1 of the storage capacitor C and the second pole CC2 of the storage capacitor C at least partially overlap to form the storage capacitor C.
  • the second electrode CC2 of the storage capacitor C includes a via hole, and the second electrode of the threshold compensation transistor T5 is electrically connected to the gate of the first driving transistor T11 through the via hole.
  • the second functional layer 530 further includes a first connection electrode block VDDe1 and a second connection electrode block VDDe2 , the first connection electrode block VDDe1 is electrically connected to the first power supply line VDD1 , and the second connection electrode block VDDe1 is electrically connected to the first power supply line VDD1 .
  • the electrode block VDDe2 is electrically connected to the second power supply line VDD2, and the first power supply connecting line VDDc1 is used to electrically connect the first connecting electrode block VDDe1 to the second connecting electrode block VDDe2, so as to realize the electrical connection of the first power supply line VDD1 to the second connecting electrode block VDDe2.
  • Power line VDD2 Power line VDD2.
  • the first initialization voltage line Vinit1 , the second initialization voltage line Vinit2 , the third gate connection line Gc3 , the first power supply connection line VDDc1 and the second power supply connection line VDDc2 are substantially along the One direction X extends.
  • the first power supply connection line VDDc1 is located between the third gate connection line Gc3 and the second power supply connection line VDDc2
  • the third gate connection line Gc3 is located between the first initialization voltage line Vinit1 and the first power supply connection
  • the second power supply connection line VDDc2 is located between the second initialization voltage line Vinit2 and the first power supply connection line VDDc1.
  • FIG. 5D shows the first functional layer 540 of the pixel circuit 100 , the first functional layer 540 includes the first data line Vd1 to the eighth data line Vd8 (only the first data line Vd1 and the second data line are marked in FIG. 5D ) Vd2), a first power supply line VDD1, a second power supply line VDD2, a first gate connection line Gc1 and a second gate connection line Gc2.
  • FIG. 6D is an enlarged schematic view of the rectangular dotted box in FIG. 5D .
  • the first data line Vd1, the second data line Vd2, the first power supply line VDD1, the second power supply line VDD2, the first gate connection line Gc1 and the second gate connection line Gc2 Extends substantially in the second direction Y.
  • the first power supply line VDD1 is located between the first gate connection line Gc1 and the first data line Vd1
  • the first data line Vd1 is located between the first power supply line VDD1 and the second gate connection line Gc2
  • the second gate connection line Gc2 is located between the first data line Vd1 and the second power supply line VDD2
  • the second power supply line VDD2 is located between the second gate connection line Gc2 and the second data line Vd2.
  • FIG. 5E is a schematic diagram of the stacking positional relationship of the above-mentioned active semiconductor layer 510 , the third functional layer 520 , the second functional layer 530 and the first functional layer 540 .
  • the first data line Vd1 communicates with the active semiconductor layer 510 through at least one via hole (eg, via hole h1 ) among the gate insulating layer, the first insulating layer, and the second insulating layer. is connected to the source region of the data writing transistor T4.
  • the first power supply line VDD1 communicates with the source of the corresponding first light emitting control transistor T21 in the active semiconductor layer 310 through at least one via hole (eg, via hole h2 ) among the gate insulating layer, the first insulating layer, and the second insulating layer.
  • the first power supply line VDD1 is connected to the second pole CC2 of the storage capacitor in the second functional layer 530 through at least one via hole (eg, h4 ) in the second insulating layer.
  • the first power supply line VDD1 is also connected to the first connection electrode block VDDe1 in the second conductive layer 330 through at least one via hole (eg, via hole h5 ) in the second insulating layer.
  • the second power supply line VDD2 communicates with the source of the corresponding third light emitting control transistor T22 in the active semiconductor layer 310 through at least one via hole (eg, via hole h3 ) among the gate insulating layer, the first insulating layer, and the second insulating layer.
  • the second power supply line VDD2 is connected to the second connection electrode block VDDe2 in the second functional layer 530 through at least one via hole (eg, h6) in the second insulating layer.
  • the first functional layer 540 further includes a first connection part 541 , a second connection part 542 , a third connection part 543 and a fourth connection part 544 .
  • One end of the first connection part 541 communicates with the drain of the corresponding threshold compensation transistor T5 in the active semiconductor layer 510 through at least one via hole (eg, via hole h7 ) in the gate insulating layer, the first insulating layer and the second insulating layer.
  • the other end of the first connection part 541 is connected to the gate of the first driving transistor T11 in the third functional layer 520 through at least one via hole (for example, via hole h8 ) in the first insulating layer and the second insulating layer.
  • the poles ie the first pole CC1 of the storage capacitor C) are connected.
  • One end of the second connection portion 542 is connected to the first initialization voltage line Vinit1 through a via hole (eg, via hole h9 ) in the second insulating layer, and the other end of the second connection portion 542 is connected to the first initialization voltage line Vinit1 through the gate insulating layer, the first insulating layer At least one via hole (eg, via hole h10 ) in the layer and the second insulating layer is connected to the drain region of the first initialization transistor T6 in the active semiconductor layer 510 .
  • a via hole eg, via hole h9
  • the first functional layer of the pixel circuit of the sub-pixel in the (n+1)th row includes a connection part 542 ′, and one end of the connection part 542 ′ is passed through one of the second insulating layers.
  • the hole (for example, the via hole h9') is connected to the second initialization voltage line Vinit2, and the other end of the connection part 542' passes through at least one via hole (for example, the via hole) among the gate insulating layer, the first insulating layer and the second insulating layer.
  • the hole h10' is connected to the drain region of the second initialization transistor T7 in the active semiconductor layer 510, so that the first electrode of the second initialization transistor T7 is electrically connected to the second initialization voltage line Vinit2, and the first electrode of the second initialization transistor T7 is electrically connected to the second initialization voltage line Vinit2.
  • the diode is ultimately connected to the first pole (ie, the anode) of the light-emitting element.
  • the second electrode of the fourth light-emitting control transistor T32 is also electrically connected to the first electrode of the light-emitting element
  • the second electrode of the second initialization transistor T7 is also electrically connected to the second electrode of the fourth light-emitting control transistor T32. pole.
  • the third connection part 543 is connected to the drain of the second light emitting control transistor T31 in the active semiconductor layer 510 through at least one via hole (eg, via hole h11 ) among the gate insulating layer, the first insulating layer, and the second insulating layer. Regions are connected.
  • the fourth connection part 544 is connected to the drain of the fourth light emission control transistor T32 in the active semiconductor layer 510 through at least one via hole (eg, via hole h12 ) in the gate insulating layer, the first insulating layer and the second insulating layer Regions are connected.
  • first gate connection line Gc1 and the first connection portion 541 are integrally provided.
  • one end of the first gate connection line Gc1 away from the first connection part 541 is connected to the third gate connection line in the second functional layer 530 through at least one via hole (eg, via hole h13 ) in the second insulating layer Gc3 linked.
  • one end of the second gate connection line Gc2 is connected to the third gate connection line Gc3 in the second functional layer 530 through at least one via hole (eg, via hole h14 ) in the second insulating layer, and the second gate
  • the other end of the connection line Gc2 is connected to the gate of the second driving transistor T12 in the third functional layer 520 through at least one via hole (eg, via hole h15 ) in the first insulating layer and the second insulating layer.
  • a region of the first functional layer 540 corresponding to the region Ad on the active semiconductor layer 510 has a fifth connection part 545 , and one end of the fifth connection part 545 passes through the second One via hole (eg, via hole h16) in the insulating layer is connected to the first initialization voltage line Vinit1, and the other end of the fifth connection part 545 passes through at least one of the gate insulating layer, the first insulating layer, and the second insulating layer A via hole (eg, via hole h17 ) is connected to the region Ad in the active semiconductor layer 510 .
  • the fifth connection portion 545 is also provided to ensure the etching uniformity of the first sub-region and the second sub-region in the pixel region, and is not a part of the pixel circuit 100 .
  • an intermediate layer (not shown) is formed on the above-mentioned first functional layer 540 for protecting the above-mentioned first functional layer 540 .
  • the first pole of the light-emitting element of each sub-pixel may be disposed on a side of the intermediate layer away from the base substrate.
  • the first driving circuit, the second driving circuit, the first lighting control circuit, the second lighting control circuit, the third lighting control circuit, the fourth lighting control circuit, the data writing circuit The positional arrangement relationship of the storage circuit, the threshold compensation circuit, the first initialization circuit and the second initialization circuit is not limited to the examples shown in FIGS. 5A to 5E , and the first driving circuit, the second driving circuit, the second driving circuit, the The positions of the first lighting control circuit, the second lighting control circuit, the third lighting control circuit, the fourth lighting control circuit, the data writing circuit, the storage circuit, the threshold compensation circuit, the first initialization circuit and the second initialization circuit.
  • FIG. 7 is a schematic block diagram of a display panel according to at least one embodiment of the present disclosure.
  • At least one embodiment of the present disclosure provides a display panel.
  • the display panel 600 includes the display substrate 601 provided by any embodiment of the present disclosure.
  • the display panel 600 may be an organic light emitting diode (OLED) display panel or the like.
  • the display substrate 601 may be an array substrate.
  • the display panel 600 may be a rectangular panel, a circular panel, an oval panel, a polygonal panel, or the like.
  • the display panel 600 can be not only a flat panel, but also a curved panel, or even a spherical panel.
  • the display panel 600 may also have a touch function, that is, the display panel 600 may be a touch display panel.
  • the display panel 600 can be applied to any product or component having a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • FIG. 8 is a schematic block diagram of a display device according to at least one embodiment of the present disclosure.
  • the display device 700 includes a display panel 701 and a sensor 702 .
  • the display panel 701 is a display panel provided by any embodiment of the present disclosure, such as the aforementioned display panel 600 .
  • the sensor 702 is disposed on the second side (non-display side) of the display substrate of the display panel, and the sensor 702 is configured to receive light from the first side (display side) of the display substrate.
  • the sensor 702 may be any form of sensor such as a camera, an infrared sensor, or the like.
  • the senor 702 at least partially overlaps the first display area 10 of the display substrate in a direction perpendicular to the surface of the display substrate, so as to adequately receive light from the first side of the display substrate, and Work based on this light.
  • the display device 700 can be any electronic device having a display function, such as a smart phone, a notebook computer, a tablet computer, a TV, and the like.
  • the smartphone or tablet may have a full-screen design, that is, without a peripheral area surrounding the third display area 30 .
  • the smartphone or tablet computer also has an off-screen sensor (such as a camera, an infrared sensor, etc.), which can perform operations such as image capture, distance perception, and light intensity perception.
  • the display device may be any product or component with display function, such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc., which is not limited by the embodiments of the present disclosure.
  • the display panel 701 and other components of the display device 700 are those of ordinary skill in the art It should be understood that there are, and will not be repeated here, nor should it be taken as a limitation of the present invention.

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  • Control Of El Displays (AREA)

Abstract

一种像素电路、显示基板、显示面板和显示装置。像素电路包括：第一驱动电路、第二驱动电路、第一发光控制电路、第二发光控制电路、存储电路和数据写入电路。第一发光控制电路被配置为控制第一驱动电路和发光元件之间的连接导通或断开和控制第一驱动电路和第一电源线之间的连接导通或断开，第二发光控制电路被配置为控制第二驱动电路和发光元件之间的连接导通或断开和控制第二驱动电路和第二电源线之间的连接导通或断开，数据写入电路被配置为将数据电压写入第一驱动电路；第一驱动电路和第二驱动电路被配置为基于同一数据电压控制驱动发光元件发光的驱动电流，存储电路被配置为保持第一驱动电路的控制端和第二驱动电路的控制端的电压。

Description

像素电路、显示基板、显示面板和显示装置
本申请要求于2020年06月29日递交的中国专利申请第202010606662.9号的优先权，在此出于所有目标全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种像素电路、显示基板、显示面板和显示装置。
背景技术
随着全面屏显示的深入发展，从在显示面板的开口区域放置摄像头进一步发展到将摄像头与显示面板进行结合的方案，即“屏下摄像头”的方案。对于“屏下摄像头”的显示设计，显示面板的放置摄像头的区域为低PPI(Pixels Per Inch，每英寸像素数量)区域，以使得低PPI区域的透光度达到摄像头成像的要求。然而，在低PPI区域中，由于像素排列的PPI比正常显示区域的PPI低，会出现低PPI区域的显示亮度低于正常显示区域的显示亮度的问题。
发明内容
本公开至少一实施例提供一种像素电路，包括：第一驱动电路、第二驱动电路、第一发光控制电路、第二发光控制电路、存储电路和数据写入电路，所述第一发光控制电路电连接至第一电源线、所述第一驱动电路和发光元件，且被配置为控制所述第一驱动电路和所述发光元件之间的连接导通或断开和控制所述第一驱动电路和所述第一电源线之间的连接导通或断开；所述第二发光控制电路电连接至第二电源线、所述第二驱动电路和所述发光元件，且被配置为控制所述第二驱动电路和所述发光元件之间的连接导通或断开和控制所述第二驱动电路和所述第二电源线之间的连接导通或断开；所述数据写入电路与所述第一驱动电路电连接，且被配置为将数据电压写入所述第一驱动电路；所述第一驱动电路和所述第二驱动电路被配置为基于同一所述数据电压控制驱动所述发光元件发光的驱动电流；所述存储电路电连接至所述第一驱动电路的控制端和所述第二驱动电路的控制端，且被配置为保持所述第一驱动电路的控制端和所述第二驱动电路的控制端的电压。
例如，本公开至少一实施例提供的像素电路还包括电源连接线，所述第一电源线和所述第二电源线通过所述电源连接线彼此电连接。
例如，在本公开至少一实施例提供的像素电路中，所述像素电路位于衬底基板上，所述像素电路具有第一功能层和第二功能层，所述第一功能层和所述第二功能层位于所述衬底基板上，且在垂直于所述衬底基板的方向上，所述第一功能层位于所述第二功能层的远离所述衬底基板的一侧，所述第一电源线和所述第二电源线位于所述第一功能层，所述电源连接 线位于所述第二功能层，所述电源连接线通过过孔电连接至所述第一电源线和所述第二电源线。
例如，在本公开至少一实施例提供的像素电路中，所述第一驱动电路的控制端和所述第二驱动电路的控制端电连接。
例如，本公开至少一实施例提供的像素电路还包括第一栅极连接线、第二栅极连接线和第三栅极连接线，所述第一驱动电路的控制端和所述第二驱动电路的控制端通过所述第一栅极连接线、所述第二栅极连接线和所述第三栅极连接线进行电连接，所述第一驱动电路的控制端与所述第一栅极连接线电连接，所述第二驱动电路的控制端与所述第二栅极连接线电连接，所述第三栅极连接线用于电连接所述第一栅极连接线和所述第二栅极连接线以将所述第一驱动电路的控制端电连接至所述第二驱动电路的控制端。
例如，在本公开至少一实施例提供的像素电路中，所述像素电路位于衬底基板上，所述像素电路具有第一功能层和第二功能层，所述第一功能层和所述第二功能层位于所述衬底基板上，且在垂直于所述衬底基板的方向上，所述第一功能层位于所述第二功能层的远离所述衬底基板的一侧，所述第一栅极连接线和所述第二栅极连接线位于所述第一功能层，所述第三栅极连接线位于所述第二功能层，所述第三栅极连接线通过过孔连接至所述第一栅极连接线和所述第二栅极连接线。
例如，在本公开至少一实施例提供的像素电路中，所述第一驱动电路包括第一驱动晶体管，所述第二驱动电路包括第二驱动晶体管，所述第一驱动电路的控制端包括所述第一驱动晶体管的栅极，所述第二驱动电路的控制端包括所述第二驱动晶体管的栅极，所述第一驱动晶体管的阈值电压和所述第二驱动晶体管的阈值电压相同。
例如，本公开至少一实施例提供的像素电路还包括阈值补偿电路，所述阈值补偿电路与所述第一驱动电路的控制端和所述第二驱动电路的控制端电连接，且被配置为对所述第一驱动电路进行阈值补偿。
例如，本公开至少一实施例提供的像素电路还包括第一初始化电路和第二初始化电路，所述第一初始化电路电连接至所述第一驱动电路的控制端和所述第二驱动电路的控制端，且配置为对所述第一驱动电路的控制端和所述第二驱动电路的控制端进行初始化，所述第二初始化电路电连接至所述发光元件的第一极，且配置为对所述发光元件的第一极进行初始化。
例如，在本公开至少一实施例提供的像素电路中，所述第一发光控制电路包括第一发光控制子电路和第二发光控制子电路，所述第一发光控制子电路与所述第一驱动电路的第一端和所述第一电源线连接，且被配置为实现所述第一驱动电路的第一端和所述第一电源线之间的连接导通或断开，所述第二发光控制子电路与所述第一驱动电路的第二端和所述发光元件的第一极电连接，且被配置为实现所述第一驱动电路的第二端和所述发光元件的第一极之间的连接导通或断开。
例如，在本公开至少一实施例提供的像素电路中，所述第二发光控制电路包括第三发光控制子电路和第四发光控制子电路，所述第三发光控制子电路与所述第二驱动电路的第一端和所述第二电源线连接，且被配置为实现所述第二驱动电路的第一端和所述第二电源线之间的连接导通或断开，所述第四发光控制子电路与所述第二驱动电路的第二端和所述发光元件的第一极电连接，且被配置为实现所述第二驱动电路的第二端和所述发光元件的第一极之间的连接导通或断开。
例如，本公开至少一实施例提供的像素电路还包括阈值补偿电路、第一初始化电路和第二初始化电路，所述第一发光控制电路包括第一发光控制子电路和第二发光控制子电路，所述第二发光控制电路包括第三发光控制子电路和第四发光控制子电路，所述第一驱动电路包括第一驱动晶体管，所述第二驱动电路包括第二驱动晶体管，所述第一发光控制子电路包括第一发光控制晶体管，所述第二发光控制子电路包括第二发光控制晶体管，所述第三发光控制子电路包括第三发光控制晶体管，所述第四发光控制子电路包括第四发光控制晶体管，所述数据写入电路包括数据写入晶体管，所述存储电路包括存储电容，所述阈值补偿电路包括阈值补偿晶体管，所述第一初始化电路包括第一初始化晶体管，所述第二初始化电路包括第二初始化晶体管，所述第一驱动电路的控制端包括所述第一驱动晶体管的栅极，所述第二驱动电路的控制端包括所述第二驱动晶体管的栅极，所述数据写入晶体管的第一极电连接至数据线以接收所述数据电压，所述数据写入晶体管的第二极电连接至所述第一驱动晶体管的第一极，所述数据写入晶体管的栅极电连接至第一扫描线；所述第一发光控制晶体管的第一极电连接至所述第一电源线，所述第一发光控制晶体管的第二极电连接至所述第一驱动晶体管的第一极，所述第一发光控制晶体管的栅极电连接至第一发光控制信号线；所述第二发光控制晶体管的第一极电连接至所述第一驱动晶体管的第二极，所述第二发光控制晶体管的第二极电连接至所述发光元件的第一极，所述第二发光控制晶体管的栅极电连接至第二发光控制信号线；所述第三发光控制晶体管的第一极电连接至所述第二电源线，所述第三发光控制晶体管的第二极电连接至所述第二驱动晶体管的第一极，所述第三发光控制晶体管的栅极电连接至第三发光控制信号线；所述第四发光控制晶体管的第一极电连接至所述第二驱动晶体管的第二极，所述第四发光控制晶体管的第二极电连接至所述发光元件的第一极，所述第四发光控制晶体管的栅极电连接至第四发光控制信号线，所述阈值补偿晶体管的第一极电连接至所述第一驱动晶体管的第二极，所述阈值补偿晶体管的第二极电连接至所述第一驱动晶体管的栅极和所述第二驱动晶体管的栅极，所述阈值补偿晶体管的栅极电连接至第二扫描线；所述第一初始化晶体管的第一极电连接至第一初始化电压线，所述第一初始化晶体管的第二极电连接至所述第一驱动晶体管的栅极和所述第二驱动晶体管的栅极，所述第一初始化晶体管的栅极电连接至第一初始化控制信号线；所述第二初始化晶体管的第一极电连接至第二初始化电压线，所述第二初始化晶体管的第二极电连接至所述发光元件的第一极，所述第二初始化晶体管的栅极电连接至第二初始化控制信号线，所述存储电 容的第一极电连接至所述第一驱动晶体管的栅极和所述第二驱动晶体管的栅极，所述存储电容的第二极电连接至所述第一电源线。
例如，在本公开至少一实施例提供的像素电路中，所述像素电路位于衬底基板上，所述像素电路具有第一功能层、第二功能层和第三功能层，所述第一功能层、所述第二功能层和所述第三功能层位于所述衬底基板上，且在垂直于所述衬底基板的方向上，所述第二功能层位于所述第一功能层和所述第三功能层之间，所述第二功能层位于所述第三功能层的远离所述衬底基板的一侧，所述第一功能层位于所述第二功能层的远离所述衬底基板的一侧，所述第一扫描线、所述第二扫描线、所述第一发光控制信号线、所述第二发光控制信号线、所述第三发光控制信号线和所述第四发光控制信号线位于所述第三功能层，所述数据线、所述第一电源线和所述第二电源线位于所述第一功能层，所述第一初始化电压线和所述第二初始化电压线位于所述第二功能层。
例如，在本公开至少一实施例提供的像素电路中，所述第一驱动晶体管和所述第二驱动晶体管在发光阶段将所述驱动电流传输至所述发光元件以驱动所述发光元件发光，
所述驱动电流表示为：
I OLED＝K1*(Vgs1-Vth1)+K2*(Vgs2-Vth2)，
其中，I OLED表示所述驱动电流，K1为所述第一驱动晶体管的工艺常数，Vgs1为在所述发光阶段所述第一驱动晶体管的栅极和第一极之间的电压差，Vth1为所述第一驱动晶体管的阈值电压，K2为所述第二驱动晶体管的工艺常数，Vgs2为在所述发光阶段所述第二驱动晶体管的栅极和第一极之间的电压差，Vth2为所述第二驱动晶体管的阈值电压。
本公开至少一实施例提供一种显示基板，显示基板包括多个子像素，所述多个子像素中的每个包括本公开任一实施例提供的像素电路和所述发光元件。
例如，本公开至少一实施例提供的显示基板还包括衬底基板，所述衬底基板包括第一显示区域，所述第一显示区域包括多个像素区域，所述多个像素区域中的每个像素区域包括彼此不重叠的第一子区域和第二子区域，所述像素电路中的第一驱动电路、第一发光控制电路、存储电路和数据写入电路位于对应的像素区域的第一子区域，所述像素电路中的第二驱动电路和第二发光控制电路位于所述对应的像素区域的第二子区域。
例如，在本公开至少一实施例提供的显示基板中，所述衬底基板还包括第二显示区域，所述多个子像素包括多个第一子像素和多个第二子像素，所述多个第一子像素的像素电路和所述多个第二子像素的像素电路与所述多个像素区域一一对应，所述第二显示区域至少部分围绕所述第一显示区域，所述显示基板具有用于显示的第一侧和与所述第一侧相对的第二侧，所述第一显示区域允许来自所述第一侧的光至少部分透射至所述第二侧；所述多个第一子像素的发光元件位于所述第一显示区域，所述多个第一子像素的像素电路位于所述第二显示区域；所述多个第二子像素的发光元件和像素电路均位于所述第二显示区域。
例如，在本公开至少一实施例提供的显示基板中，每个像素区域的第一子区域包括彼此 相对的第一侧和第二侧，所述多个第一子像素的像素电路构成多个第一重复单元，每个所述第一重复单元包括排列为两行两列的四个第一子像素的像素电路，所述四个第一子像素的像素电路中位于第一行第一列的第一子像素的像素电路对应的像素区域中的第二子区域位于第一子区域的第一侧，所述四个第一子像素的像素电路中位于第二行第一列的第一子像素的像素电路对应的像素区域中的第二子区域位于第一子区域的第一侧，所述四个第一子像素的像素电路中位于第一行第二列的第一子像素的像素电路对应的像素区域中的第二子区域位于第一子区域的第二侧，所述四个第一子像素的像素电路中位于第二行第二列的第一子像素的像素电路对应的像素区域中的第二子区域位于第一子区域的第二侧，所述多个第二子像素的像素电路构成多个第二重复单元，每个所述第二重复单元包括排列为两行两列的四个第二子像素的像素电路，所述四个第二子像素的像素电路中位于第一行第一列的第二子像素的像素电路对应的像素区域中的第二子区域位于第一子区域的第二侧，所述四个第二子像素的像素电路中位于第二行第一列的第二子像素的像素电路对应的像素区域中的第二子区域位于第一子区域的第二侧，所述四个第二子像素的像素电路中位于第一行第二列的第二子像素的像素电路对应的像素区域中的第二子区域位于第一子区域的第一侧，所述四个第二子像素的像素电路中位于第二行第二列的第二子像素的像素电路对应的像素区域中的第二子区域位于第一子区域的第一侧。
例如，在本公开至少一实施例提供的显示基板中，所述多个第一重复单元和所述多个第二重复单元构成多个重复单元组，所述多个重复单元组中的每个重复单元组包括两个第一重复单元和两个第二重复单元，所述两个第一重复单元和所述两个第二重复单元排列为两行两列，所述两个第一重复单元分别位于第一行第二列和第二行第一列，所述两个第二重复单元分别位于第一行第一列和第二行第二列；或者，所述两个第一重复单元分别位于第一行第一列和第二行第二列，所述两个第二重复单元分别位于第一行第二列和第二行第一列。
例如，在本公开至少一实施例提供的显示基板中，所述四个第一子像素中位于第一行第一列的第一子像素和所述四个第二子像素中位于第一行第一列的第二子像素为红色子像素，所述四个第一子像素中位于第二行第一列的第一子像素和所述四个第二子像素中位于第二行第一列的第二子像素为蓝色子像素，所述四个第一子像素中位于第一行第二列的第一子像素、所述四个第一子像素中位于第二行第二列的第一子像素、所述四个第二子像素中位于第一行第二列的第二子像素和所述四个第二子像素中位于第二行第二列的第二子像素为绿色子像素。
本公开至少一实施例提供一种显示面板，包括本公开任一实施例提供的所述的显示基板。
本公开至少一实施例提供一种显示装置，包括本公开任一实施例提供的显示面板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为本公开一实施例提供的一种像素电路的示意性框图；
图1B为本公开一实施例提供的另一种像素电路的示意性框图；
图2为本公开一实施例提供的一种像素电路的结构示意图；
图3A为本公开一些实施例提供的一种显示基板的平面示意图；
图3B为本公开一些实施例提供的一种显示基板上的子像素的排布示意图；
图4A为本公开一些实施例提供的一种第一重复单元的排列示意图；
图4B为本公开一些实施例提供的一种第二重复单元的排列示意图；
图4C为本公开一些实施例提供的一种像素区域的排列示意图；
图4D为本公开一些实施例提供的另一种像素区域的排列示意图；
图5A～5E为本公开一些实施例提供的一种像素电路的各功能层的结构示意图；
图6A～6D为本公开一些实施例提供的一种像素电路的各功能层的放大示意图；
图7为本公开至少一实施例提供的一种显示面板的示意框图；
图8为本公开至少一个实施例提供的一种显示装置的示意框图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。
在“屏下摄像头”的设计方案中，为了使得更多的光能够进入位于显示面板下方的摄像头中，可以将显示面板设计为具有高像素密度区域(即高PPI区域)和低像素密度区域(即低PPI区域)，摄像头则设置在能够允许更多的光透过的低像素密度区域下方。然而，由于 低像素密度区域的发光元件的单位面积分布密度低于高像素密度区域的发光元件的单位面积分布密度，导致低像素密度区域的发光亮度低于高像素密度区域的发光亮度，影响显示面板的显示效果，降低显示面板的显示质量。
本公开至少一个实施例提供一种像素电路、显示基板、显示面板和显示装置，该像素电路包括第一驱动电路、第二驱动电路、第一发光控制电路、第二发光控制电路、存储电路和数据写入电路。第一发光控制电路电连接至第一电源线、第一驱动电路和发光元件，且被配置为控制第一驱动电路和发光元件之间的连接导通或断开和控制第一驱动电路和第一电源线之间的连接导通或断开；第二发光控制电路电连接至第二电源线、第二驱动电路和发光元件，且被配置为控制第二驱动电路和发光元件之间的连接导通或断开和控制第二驱动电路和第二电源线之间的连接导通或断开；数据写入电路与第一驱动电路电连接，且被配置为将数据电压写入第一驱动电路；第一驱动电路和第二驱动电路被配置为基于同一数据电压控制驱动发光元件发光的驱动电流；存储电路电连接至第一驱动电路的控制端和第二驱动电路的控制端，且被配置为保持第一驱动电路的控制端和第二驱动电路的控制端的电压。
在该像素电路中，通过增加驱动低像素密度区域内的发光元件发光第二驱动电路，从而使得两个驱动电路同时对一个发光元件进行驱动，从而提高驱动低像素密度区域内的发光元件的驱动电流，增加低像素密度区域的亮度，降低或消除由于在显示面板下方设置摄像头而导致的发光亮度不均匀的问题，提高显示效果和显示质量。
例如，按照晶体管的特性，晶体管可以分为N型晶体管和P型晶体管，为了清楚起见，本公开的实施例以晶体管为P型晶体管(例如，低温多晶硅(LTPS)P型薄膜晶体管)为例详细阐述了本公开的技术方案，然而本公开的实施例的晶体管不限于P型晶体管，本领域技术人员还可以根据实际需要利用N型晶体管(例如，N型MOS晶体管)实现本公开的实施例中的一个或多个晶体管的功能。
需要说明的是，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本公开的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。
下面对本公开的一些实施例进行详细说明，但是本公开并不限于这些具体的实施例。
图1A为本公开一实施例提供的一种像素电路的示意性框图，图1B为本公开一实施例提供的另一种像素电路的示意性框图。
例如，如图1A所示，本公开实施例提供的像素电路100可以包括第一驱动电路101、第二驱动电路111、第一发光控制电路102、第二发光控制电路112、存储电路103和数据写入电路104。
例如，数据写入电路104与第一驱动电路101电连接，且被配置为将数据电压写入第一驱动电路101。例如，数据写入电路104电连接至第一驱动电路101的第一端、数据线和第一扫描线，以在第一扫描线提供的第一扫描信号的控制下将数据线提供的数据电压写入第一驱动电路101的第一端。例如，数据写入电路104还可以将数据电压写入第二驱动电路111。
例如，第一驱动电路101和第二驱动电路111被配置为基于同一数据电压驱动发光元件200发光，以使得发光元件200发出与该同一数据电压相对应的光。
例如，在一些实施例中，第一驱动电路101的控制端和第二驱动电路111的控制端电连接，从而第一驱动电路101和第二驱动电路111可以被相同的信号控制，此时第一驱动电路101和第二驱动电路111可以共享同一个数据写入电路104、存储电路103、阈值补偿电路(下面将会描述)和第一初始化电路(下面将会描述)，从而可以减少像素电路中的晶体管和电容数量，节省成本。但本公开不限于此，在另一些实施例中，第一驱动电路101的控制端和第二驱动电路111的控制端不连接，但是，此时，第一驱动电路101的控制端和第二驱动电路111的控制端可以接受相同的信号。
例如，第一发光控制电路102电连接至第一电源线(图1A没有示出)、第一驱动电路101和发光元件200，且被配置为控制第一驱动电路101和发光元件200之间的连接导通或断开和控制第一驱动电路101和第一电源线之间的连接导通或断开。例如，第一发光控制电路102电连接至第一驱动电路101的第一端和第二端、发光元件200的第一极、第一发光控制信号线和第二发光控制信号线。第一发光控制电路102被配置为在第一发光控制信号线提供的第一发光控制信号和第二发光控制信号线提供的第二发光控制信号的控制下控制第一驱动电路101是否驱动发光元件200进行发光，例如，当第一发光控制电路102控制第一驱动电路101和发光元件200之间的连接导通且控制第一驱动电路101和第一电源线之间的连接导通，则此时，第一驱动电路101驱动发光元件200进行发光；当第一发光控制电路102控制第一驱动电路101和发光元件200之间的连接断开和/或控制第一驱动电路101和第一电源线之间的连接断开，则此时，第一驱动电路101不驱动发光元件200进行发光。
例如，第二发光控制电路112电连接至第二电源线(图1A没有示出)、第二驱动电路111和发光元件200，且被配置为控制第二驱动电路111和发光元件200之间的连接导通或断开和控制第二驱动电路111和第二电源线之间的连接导通或断开。例如，第二发光控制电路112电连接至第二驱动电路111的第一端和第二端、发光元件200的第一极、第三发光控制信号线和第四发光控制信号线。第二发光控制电路112被配置为在第三发光控制信号线提供的第三发光控制信号和第四发光控制信号线提供的第四发光控制信号的控制下控制第二驱动电路111是否驱动发光元件200进行发光，例如，当第二发光控制电路112控制第二驱动电路111和发光元件200之间的连接导通且控制第二驱动电路111和第二电源 线之间的连接导通，则此时，第二驱动电路111驱动发光元件200进行发光；当第二发光控制电路112控制第二驱动电路111和发光元件200之间的连接断开和/或控制第二驱动电路111和第二电源线之间的连接断开，则此时，第二驱动电路111不驱动发光元件200进行发光。
例如，在一些实施例中，第一电源线和第二电源线彼此电连接；在另一些实施例中，第一电源线和第二电源线彼此不电连接，然而，第一电源线提供的电源电压和第二电源线提供的电源电压相同。例如，例如，第一电源线和第二电源线可以连接至同一个电源端以接收相同的电源电压，以节省电源端数量，节约生产成本。
例如，存储电路103电连接至第一驱动电路101的控制端和第二驱动电路111的控制端，且被配置为保持第一驱动电路101的控制端和第二驱动电路11的控制端的电压。
例如，发光元件200的第二极电连接至第三电源线(图1A中没有示出)。
例如，第一电源线和第二电源线均提供恒定的高电源电压，第三电源线可以提供恒定的低电源电压，或可以接地等。但本公开不限于此，在另一些实施例中，第一电源线和第二电源线均提供恒定的低电源电压，第三电源线可以提供恒定的高电源电压。
例如，发光元件200可以为发光二极管等。发光二极管可以为有机发光二极管(OLED)或量子点发光二极管(QLED)等。发光元件200被配置为在工作时接收发光信号(例如，可以为电流信号)，并发出与该发光信号相对应强度的光。
例如，本公开实施例提供的像素电路100可应用于显示面板，例如有源矩阵有机发光二极管(AMOLED)显示面板或有源矩阵量子点发光二极管(AMQLED)显示面板等。
例如，如图1B所示，在一些实施例中，像素电路100还包括阈值补偿电路105。阈值补偿电路105与第一驱动电路101的控制端和第二驱动电路102的控制端电连接，且被配置为对第一驱动电路101进行阈值补偿。例如，阈值补偿电路105电连接至第一驱动电路101的控制端和第二端、第二驱动电路111的控制端和第二扫描线，且被配置为在第二扫描线提供的第二扫描信号的控制下，将基于数据电压的补偿电压写入第一驱动电路101的控制端和第二驱动电路111的控制端。第一存储电路103可以存储该补偿电压，并将该补偿电压保持在第一驱动电路101的控制端和第二驱动电路111的控制端。该补偿电压可以控制第一驱动电路101和第二驱动电路111的导通程度，从而控制驱动光元件200发光的驱动电流。需要说明的是，阈值补偿电路105还可以为对第二驱动电路111进行阈值补偿。
例如，如图1B所示，在一些实施例中，像素电路100还包括第一初始化电路106和第二初始化电路107。
例如，第一初始化电路106电连接至第一驱动电路101的控制端和第二驱动电路111的控制端，且配置为对第一驱动电路101的控制端和第二驱动电路111的控制端进行初始化。第一初始化电路106电连接至第一驱动电路101的控制端、第二驱动电路111的控制端、第一初始化控制信号线和第一初始化电压线，且被配置为在第一初始化控制信号线提供 的第一初始化控制信号的控制下将第一初始化电压线提供的第一初始化电压写入第一驱动电路101的控制端和第二驱动电路111的控制端，以实现对第一驱动电路101的控制端和第二驱动电路111的控制端进行初始化。
例如，第二初始化电路107电连接至发光元件200的第一极，且配置为对发光元件200的第一极进行初始化。第二初始化电路107电连接至发光元件200的第一极、第二初始化控制信号线和第二初始化电压线，且被配置为在第二初始化控制信号线提供的第二初始化控制信号的控制下将第二初始化电压线提供的第二初始化电压写入发光元件200的第一极，以实现对发光元件200的第一极进行初始化。
图2为本公开一实施例提供的一种像素电路的结构示意图。图2所示的电路结构为图1B所示的像素电路的一种具体实现示例的电路结构。
例如，如图2所示，在一些实施例中，第一驱动电路101包括第一驱动晶体管T11，第二驱动电路111包括第二驱动晶体管T12。例如，第一驱动电路101的控制端包括第一驱动晶体管T11的栅极，第一驱动电路101的第一端包括第一驱动晶体管T11的第一极，第一驱动电路101的第二端包括第一驱动晶体管T11的第二极，第二驱动电路111的控制端包括第二驱动晶体管T12的栅极，第二驱动电路111的控制端包括第二驱动晶体管T12的栅极，第二驱动电路111的第一端包括第二驱动晶体管T12的第一极，第二驱动电路111的第二端包括第二驱动晶体管T12的第二极，例如，第一驱动晶体管T11的栅极可以作为第一驱动电路101的控制端，第一驱动晶体管T11的第一极作为第一驱动电路101的第一端，第一驱动晶体管T11的第二极作为第一驱动电路101的第二端，第二驱动晶体管T12的栅极作为第二驱动电路111的控制端，第二驱动晶体管T12的第一极作为第二驱动电路111的第一端，第二驱动晶体管T12的第二极作为第二驱动电路111的第二端。
例如，在第一驱动电路101的控制端和第二驱动电路111的控制端彼此电连接的情况下，第一驱动晶体管T11的栅极和第二驱动晶体管T12的栅极彼此电连接，此时，第一驱动晶体管T11和第二驱动晶体管T12相同，例如，第一驱动晶体管T11和第二驱动晶体管T12的类型和电学参数等均相同，也就是说，第一驱动晶体管T11的阈值电压和第二驱动晶体管T12的阈值电压相同，从而当阈值补偿电路105对第一驱动电路101的第一驱动晶体管T11进行阈值补偿时，实际上，第二驱动晶体管T12的阈值电压也被补偿。例如，上述补偿电压可以包括数据电压和第一驱动晶体管T11的阈值电压，例如，上述补偿电压可以为数据电压和第一驱动晶体管T11的阈值电压之和。
例如，第一驱动晶体管T11和第二驱动晶体管T12均为P型晶体管。
例如，第一驱动晶体管T11的栅极和第二驱动晶体管T12的栅极均电连接至节点N1，第一驱动晶体管T11的第一极电连接至节点N2，第一驱动晶体管T11的第二极电连接至节点N3。
例如，如图2所示，第一发光控制电路102包括第一发光控制子电路1021和第二发光 控制子电路1022。
例如，第一发光控制子电路1021与第一驱动电路101的第一端和第一电源线VDD1连接，且被配置为实现第一驱动电路101的第一端和第一电源线VDD1之间的连接导通或断开。例如，第一发光控制子电路1021还与第一发光控制信号线电连接，以在第一发光控制信号的控制下，实现第一驱动电路101的第一端和第一电源线VDD1之间的连接导通或断开。
例如，第二发光控制子电路1022与第一驱动电路101的第二端和发光元件200的第一极电连接，且被配置为实现第一驱动电路101的第二端和发光元件200的第一极之间的连接导通或断开。例如，第二发光控制子电路1022还与第二发光控制信号线电连接，以在第二发光控制信号的控制下，实现第一驱动电路101的第二端和发光元件200的第一极之间的连接导通或断开。
例如，如图2所示，第二发光控制电路112包括第三发光控制子电路1121和第四发光控制子电路1122。
例如，第三发光控制子电路1121与第二驱动电路111的第一端和第二电源线VDD2连接，且被配置为实现第二驱动电路111的第一端和第二电源线VDD2之间的连接导通或断开。例如，第三发光控制子电路1121还与第三发光控制信号线电连接，以在第三发光控制信号的控制下，实现第二驱动电路111的第一端和第二电源线VDD2之间的连接导通或断开。
例如，第四发光控制子电路1122与第二驱动电路111的第二端和发光元件200的第一极电连接，且被配置为实现第二驱动电路111的第二端和发光元件200的第一极之间的连接导通或断开。例如，第四发光控制子电路1122还与第四发光控制信号线电连接，以在第四发光控制信号的控制下，实现第二驱动电路111的第二端和发光元件200的第一极之间的连接导通或断开。
例如，如图2所示，在一些实施例中，第一发光控制子电路1021包括第一发光控制晶体管T21，第二发光控制子电路1022包括第二发光控制晶体管T31，第三发光控制子电路1121包括第三发光控制晶体管T22，第四发光控制子电路1122包括第四发光控制晶体管T32，数据写入电路104包括数据写入晶体管T4，存储电路103包括存储电容C，阈值补偿电路105包括阈值补偿晶体管T5，第一初始化电路106包括第一初始化晶体管T6，第二初始化电路107包括第二初始化晶体管T7。
例如，数据写入晶体管T4的第一极电连接至数据线Vd以接收数据电压，数据写入晶体管T4的第二极电连接至第一驱动晶体管T11的第一极，即节点N2，数据写入晶体管T4的栅极电连接至第一扫描线G1以接收第一扫描信号。数据写入晶体管T4用于在第一扫描信号的控制下将数据电压写入第一驱动晶体管T11的第一极。
例如，阈值补偿晶体管T5的第一极电连接至第一驱动晶体管T11的第二极，即节点 N3，阈值补偿晶体管T5的第二极电连接至第一驱动晶体管T11的栅极和第二驱动晶体管T12的栅极，即节点N1，阈值补偿晶体管T5的栅极电连接至第二扫描线以接收第二扫描信号。当阈值补偿晶体管T5在第二扫描信号的控制下导通时，第一驱动晶体管T11连接成为二极管连接方式。
例如，数据写入晶体管T4和阈值补偿晶体管T5可以同时导通。
例如，第一扫描信号和第二扫描信号可以相同，在一些实施例中，第一扫描线G1和第二扫描线G2为同一条信号线，以传输相同的信号，从而节省信号线的数量，降低制造成本。此时，数据写入晶体管T4的栅极和阈值补偿晶体管T5的栅极可以电连接到同一条信号线，例如第一扫描线G1，以接收相同的信号。但本公开不限于此，第一扫描线G1和第二扫描线G2也可以为不同的信号线，从而可以使得数据写入晶体管T4和阈值补偿晶体管T5被分开单独控制，增加控制像素电路的灵活性。又例如，第一扫描信号和第二扫描信号也可以不相同，只要第一扫描信号和第二扫描信号能够使得数据写入晶体管T4和阈值补偿晶体管T5被同时导通即可。
例如，第一发光控制晶体管T21的第一极电连接至第一电源线VDD1，第一发光控制晶体管T21的第二极电连接至第一驱动晶体管T11的第一极，第一发光控制晶体管T21的栅极电连接至第一发光控制信号线EM1以接收第一发光控制信号。当第一发光控制晶体管T21在第一发光控制信号的控制下导通时，第一电源线VDD1和第一驱动晶体管T11的第一极电连接。
例如，第二发光控制晶体管T31的第一极电连接至第一驱动晶体管T11的第二极，即节点N3，第二发光控制晶体管T31的第二极电连接至发光元件200的第一极，即节点N4，第二发光控制晶体管T31的栅极电连接至第二发光控制信号线EM2以接收第二发光控制信号。当第二发光控制晶体管T31在第二发光控制信号的控制下导通时，第一驱动晶体管T11的第二极和发光元件200的第一极电连接。
例如，第三发光控制晶体管T22的第一极电连接至第二电源线VDD2，第三发光控制晶体管T22的第二极电连接至第二驱动晶体管T12的第一极，第三发光控制晶体管T22的栅极电连接至第三发光控制信号线EM3以接收第三发光控制信号。当第三发光控制晶体管T22在第三发光控制信号的控制下导通时，第二电源线VDD2和第二驱动晶体管T12的第一极电连接。
例如，第四发光控制晶体管T32的第一极电连接至第二驱动晶体管T12的第二极，第四发光控制晶体管T32的第二极电连接至发光元件200的第一极，第四发光控制晶体管T32的栅极电连接至第四发光控制信号线EM4以接收第四发光控制信号。当第四发光控制晶体管T32在第四发光控制信号的控制下导通时，第二驱动晶体管T12的第二极和发光元件200的第一极电连接。
例如，第一发光控制晶体管T21、第二发光控制晶体管T31、第三发光控制晶体管T22 和第四发光控制晶体管T32可以同时被导通，从而使得第一驱动晶体管T11和第二驱动晶体管T12同时驱动发光元件200发光。
例如，在一些实施例中，第一发光控制信号、第二发光控制信号、第三发光控制信号和第四发光控制信号可以相同，例如，第一发光控制信号线EM1、第二发光控制信号线EM2、第三发光控制信号线EM3和第四发光控制信号线EM4为同一条信号线，即，第一发光控制晶体管T21的栅极、第二发光控制晶体管T31的栅极、第三发光控制晶体管T22的栅极和第四发光控制晶体管T32的栅极可以电连接到同一条信号线，例如第一发光控制信号线EM1，以接收相同的信号(例如，第一发光控制信号)，此时，可以不设置第二发光控制信号线EM2、第三发光控制信号线EM3和第四发光控制信号线EM4，从而减少信号线的数量。又例如，第一发光控制晶体管T21的栅极、第二发光控制晶体管T31的栅极、第三发光控制晶体管T22的栅极和第四发光控制晶体管T32的栅极也可以分别电连接至不同的信号线，即，第一发光控制晶体管T21的栅极电连接到第一发光控制信号线EM1，第二发光控制晶体管T31的栅极电连接到第二发光控制信号线EM2，第三发光控制晶体管T22的栅极电连接到第三发光控制信号线EM3，第四发光控制晶体管T32的栅极电连接到第四发光控制信号线EM4，而第一发光控制信号线EM1、第二发光控制信号线EM2、第三发光控制信号线EM3和第四发光控制信号线EM4传输的信号相同。
需要说明的是，第一发光控制信号、第二发光控制信号、第三发光控制信号和第四发光控制信号也可以不相同，本公开的实施例对此不作限制。
例如，第一初始化晶体管T6的第一极电连接至第一初始化电压线Vinit1，第一初始化晶体管T6的第二极电连接至第一驱动晶体管T11的栅极和第二驱动晶体管T12的栅极，第一初始化晶体管T6的栅极电连接至第一初始化控制信号线Rst1。当第一初始化晶体管T6在第一初始化控制信号线Rst1提供的第一初始化控制信号的控制下导通时，第一初始化晶体管T6将第一初始化电压线Vinit1提供的第一初始化电压传输至第一驱动晶体管T11的栅极和第二驱动晶体管T12的栅极，以实现对第一驱动晶体管T11的栅极和第二驱动晶体管T12的栅极进行初始化。
例如，第二初始化晶体管T7的第一极电连接至第二初始化电压线Vinit2，第二初始化晶体管T7的第二极电连接至发光元件200的第一极，即节点N4，第二初始化晶体管T7的栅极电连接至第二初始化控制信号线Rst2。当第二初始化晶体管T7在第二初始化控制信号线Rst2提供的第二初始化控制信号的控制下导通时，第二初始化晶体管T7将第二初始化电压线Vinit2提供的第二初始化电压传输至发光元件200的第一极，以实现对发光元件200的第一极进行初始化。
例如，在一些实施例中，第一初始化控制信号和第二初始化控制信号可以相同，在一些示例中，第一初始化控制信号线Rst1和第二初始化控制信号线Rst2为同一条信号线，即，第一初始化晶体管T6的栅极和第二初始化晶体管T7的栅极可以电连接到同一条信号线， 例如第一初始化控制信号线Rst1，以接收相同的信号(例如，第一初始化控制信号)，此时，可以不设置第二初始化控制信号线Rst2，从而减少信号线的数量；在另一些示例中，第一初始化晶体管T6的栅极和第二初始化晶体管T7的栅极也可以分别电连接至不同的信号线，即第一初始化晶体管T6的栅极电连接到第一初始化控制信号线Rst1，第二初始化晶体管T7的栅极电连接到第二初始化控制信号线Rst2，而第一初始化控制信号线Rst1和第二初始化控制信号线Rst2传输的信号相同。又例如，在另一些实施例中，第一初始化控制信号和第二初始化控制信号可以不相同，例如，第一初始化控制信号线Rst1和第二初始化控制信号线Rst2为不同的信号线，从而可以使得第一初始化晶体管T6和第二初始化晶体管T7被分开单独控制，增加控制像素电路的灵活性。
例如，在一些示例中，显示面板上设置有排布为N行M列多个子像素，位于N行中的第n行的子像素的像素电路中的第二初始化电路和位于N行中的第(n+1)行的子像素的像素电路中的第一初始化电路由同一条初始化控制信号线控制，也就是说，与位于第n行的子像素的像素电路中的第二初始化电路连接的第二初始化控制信号线和与位于第(n+1)行的子像素的像素电路中的第一初始化电路连接的第一初始化控制信号线为同一条信号线，从而可以节省信号线的数量。例如，N、M和n为正整数，且n小于N。类似地，与位于第n行的子像素的像素电路中的第二初始化电路连接的第二初始化电压线Vinit2和与位于第(n+1)行的子像素的像素电路中的第一初始化电路连接的第一初始化电压线Vinit1为同一条信号线。
例如，第一初始化电压线Vinit1和第二初始化电压线Vinit2可以传输恒定的直流电压。第一初始化电压线Vinit1和第二初始化电压线Vinit2可以电连接至高压端，也可以电连接至低压端，只要其能够提供第一初始化电压和第二初始化电压以对第一驱动晶体管T11的栅极、第二驱动晶体管T12的栅极和发光元件200的第一极进行初始化即可，本公开对此不作限制。
例如，存储电容C的第一极电连接至第一驱动晶体管T11的栅极和第二驱动晶体管T12的栅极，存储电容C的第二极电连接至第一电源线VDD1。例如，在另一些示例中，存储电容C的第二极也可以电连接至第二电源线VDD2。
例如，如图2所示，在本公开的实施例中，通过额外增加一个驱动电路(即第二驱动晶体管T12)，将两个驱动电路(即第一驱动晶体管T11和第二驱动晶体管T12)均连接至发光元件200，从而可以达到理论上使得流过发光元件200的驱动电流增加为原始驱动电路的两倍的目的。
需要说明的是，图2所示的像素电路中的第一驱动电路101、第二驱动电路111、第一发光控制电路102、第二发光控制电路112、存储电路103、数据写入电路104、阈值补偿电路105、第一初始化电路106和第二初始化电路107仅为示意性的，第一驱动电路101、第二驱动电路111、第一发光控制电路102、第二发光控制电路112、存储电路103、数据写入 电路104、阈值补偿电路105、第一初始化电路106和第二初始化电路107等电路的具体结构可以根据实际应用需求进行设定，本公开的实施例对此不作具体限定。此外，根据实际情况，像素电路100还可以包括更多或更少的电路。
例如，如图2所示，像素电路100还包括电源连接线VDDc1。第一电源线VDD1和第二电源线VDD2通过电源连接线VDDc1彼此电连接。
例如，像素电路的时序图可以根据实际需求进行设定，本公开的实施例对此不作具体限定。下面结合图2所示的像素电路，简单描述该像素电路的各个工作阶段。
例如，如图2所示，在初始化阶段，第一初始化晶体管T6和第二初始化晶体管T7导通，第一初始化电压经由第一初始化晶体管T6传输至第一驱动晶体管T11的栅极和第二驱动晶体管T12的栅极，从而第一驱动晶体管T11的栅极和第二驱动晶体管T12的栅极的电压被初始化为第一初始化电压。第二初始化电压经由第二初始化晶体管T7传输至发光元件200的第一极，从而发光元件200的第一极的电压被初始化为第二初始化电压。此时，第一驱动晶体管T11和第二驱动晶体管T12可以处于导通状态。
例如，如图2所示，在数据写入和补偿阶段，数据写入晶体管T4和阈值补偿晶体管T5导通，数据电压依次经过数据写入晶体管T4和阈值补偿晶体管T5被写入节点N1，即第一驱动晶体管T11的栅极和第二驱动晶体管T12的栅极，当节点N1处的电压变为数据电压Vdata和第一驱动晶体管T11的阈值电压Vth1之和(即Vdata+Vth1)时，第一驱动晶体管T11截止，数据写入和补偿阶段结束。
例如，第一驱动晶体管T11和第二驱动晶体管T12在发光阶段将驱动电流传输至发光元件200以驱动发光元件200发光。如图2所示，在发光阶段，第一发光控制晶体管T21、第二发光控制晶体管T31、第三发光控制晶体管T22和第四发光控制晶体管T32均导通，第一电源线VDD1输出的第一电源电压可以经由第一发光控制晶体管T21传输至第一驱动晶体管T11的第一极，第一驱动晶体管T11的第一极的电压变为第一电源电压，第一电源线VDD1输出的第一电源电压可以经由第一发光控制晶体管T21传输至第一驱动晶体管T11的第一极，第一驱动晶体管T11的第一极的电压变为第一电源电压，第二电源线VDD2输出的第二电源电压可以经由第二发光控制晶体管T22传输至第二驱动晶体管T12的第一极，第二驱动晶体管T12的第一极的电压变为第二电源电压，第一电源电压和第二电源电压相同。
由此，基于第一驱动晶体管T11和第二驱动晶体管T12的饱和电流公式，可以得到流至发光元件200的驱动电流I OLED可以表示为：
Figure PCTCN2021094026-appb-000001
其中，I OLED表示驱动电流，K1为第一驱动晶体管T11的工艺常数，Vgs1为在发光阶 段第一驱动晶体管T11的栅极和第一极之间的电压差，Vth1为第一驱动晶体管T11的阈值电压，K2为第二驱动晶体管T12的工艺常数，Vgs2为在发光阶段第二驱动晶体管T12的栅极和第一极之间的电压差，Vth2为第二驱动晶体管T12的阈值电压，Vth1和Vth2相同，Vdd1表示第一电源电压，Vdd2表示第二电源电压，Vdata表示数据电压。
由上式中可以看到，驱动电流I OLED已经不受第一驱动晶体管T11和第二驱动晶体管T12的阈值电压的影响，而只与第一电源电压/第二电源电压和数据电压Vdata有关。数据电压Vdata由数据线Vd直接传输，其与第一驱动晶体管T11和第二驱动晶体管T12的阈值电压无关，这样就可以解决由于工艺制程及长时间的操作造成第一驱动晶体管T11和第二驱动晶体管T12的阈值电压漂移的问题，保证驱动电流I OLED的准确性，保证发光元件200正常工作，提高显示画面的均匀性，提升显示效果。
例如，在上面的公式中，K1表示为：K1＝0.5μ n1C ox1(W1/L1)，K2表示为：K2＝0.5μ n2C ox2(W2/L2)，其中，μ n1为第一驱动晶体管T11的电子迁移率，C ox1为第一驱动晶体管T11的栅极单位电容量，W1为第一驱动晶体管T11的沟道宽，L1为第一驱动晶体管T11的沟道长，μ n2为第二驱动晶体管T12的电子迁移率，C ox2为第二驱动晶体管T12的栅极单位电容量，W2为第二驱动晶体管T12的沟道宽，L2为第二驱动晶体管T12的沟道长。
例如，像素电路100位于衬底基板(下面将会描述)上，像素电路100具有第一功能层和第二功能层，第一功能层和第二功能层位于衬底基板上，且在垂直于衬底基板的方向上，第一功能层位于第二功能层的远离衬底基板的一侧，第一电源线VDD1和第二电源线VDD2位于第一功能层，电源连接线VDDc1位于第二功能层。也就是说，电源连接线VDDc1位于第一电源线VDD1和第二电源线VDD2所在的层不同的层，电源连接线VDDc1通过两个过孔分别与第一电源线VDD1和第二电源线VDD2电连接。
例如，像素电路100还包括第一栅极连接线、第二栅极连接线和第三栅极连接线(图2中未示出)。第一驱动电路101的控制端和第二驱动电路111的控制端通过第一栅极连接线、第二栅极连接线和第三栅极连接线进行电连接，第一驱动电路101的控制端与第一栅极连接线电连接，第二驱动电路111的控制端与第二栅极连接线电连接，第三栅极连接线用于电连接第一栅极连接线和第二栅极连接线，从而实现将第一驱动电路101的控制端和第二驱动电路111的控制端电连接。例如，在第一驱动电路101包括第一驱动晶体管T11，第二驱动电路111包括第二驱动晶体管T12的情况下，第一驱动晶体管T11的栅极与第一栅极连接线电连接，第二驱动晶体管T12的栅极与第二栅极连接线电连接。
例如，第一栅极连接线和第二栅极连接线位于第一功能层，第三栅极连接线位于第二功能层，也就是说，第三栅极连接线位于第一栅极连接线和第二栅极连接线所在的层不同的层，第三栅极连接线通过两个过孔分别连接至第一栅极连接线和第二栅极连接线。
例如，像素电路100还具有第三功能层，第一功能层、第二功能层和第三功能层彼此层叠设置，第三功能层也位于衬底基板上，且在垂直于衬底基板的方向上，第二功能层位于第 一功能层和第三功能层之间，第二功能层位于第三功能层的远离衬底基板的一侧，第一功能层位于第二功能层的远离衬底基板的一侧。
例如，第一扫描线G1、第二扫描线G2、第一初始化控制信号线Rst1、第二初始化控制信号线Rst2、第一发光控制信号线EM1、第二发光控制信号线EM2、第三发光控制信号线EM3和第四发光控制信号线EM4位于第三功能层；数据线Vd位于第一功能层，第一初始化电压线Vinit1和第二初始化电压线Vinit2位于第二功能层。
例如，第一功能层、第二功能层和第三功能层将在下面进行详细描述，此处不赘述，例如，第一功能层可以为源漏极金属层，第二功能层可以为第二栅极金属层，第三功能层可以为第一栅极金属层。
图3A为本公开一些实施例提供的一种显示基板的平面示意图，图3B为本公开一些实施例提供的一种显示基板上的子像素的排布示意图。
本公开至少一实施例提供一种显示基板。例如，如图3A所示，该显示基板具有用于显示的第一侧(即显示侧)和与第一侧相对的第二侧(即非显示侧，又可称为背侧)。例如，显示基板还包括衬底基板，衬底基板包括第一显示区域10以及至少部分围绕(在图3A所示的示例中，完全围绕)第一显示区域10的第二显示区域20，第一显示区域10允许来自第一侧的光至少部分透射至第二侧，也即第一显示区域10为透明显示区域，光线可从显示基板的显示侧通过透明显示区域到达非显示侧，非显示侧例如可以设置摄像头、红外感应装置等传感器，例如，该传感器可以设置在第二显示区域20下方，该传感器可采集并利用从第一显示区域10透射至非显示侧的光进行感测工作，例如成像、图像拍摄、距离感知、光强感知等操作。
例如，显示基板可以包括多个子像素，多个子像素中的每个包括上述任一项所述的像素电路和发光元件。例如，如图3B所示，多个子像素包括多个第一子像素P1和多个第二子像素P2。
例如，多个第一子像素P1阵列排布在第一显示区域10，每个第一子像素P1包括发光元件和像素电路，多个第一子像素P1的发光元件(图3B中第一显示区域10内的白色方框)位于第一显示区域10，多个第一子像素P1的像素电路(即图3B中第二显示区域20内的灰色方框)位于第二显示区域20。第一子像素P1的像素电路用于驱动第一子像素P1的发光元件。即，第一显示区域10中的多个第一子像素P1的像素电路设置在第二显示区域20，由此可避免第一显示区域10中设置的结构过多或者具有不透光结构，从而保证第一显示区域10的透光性，有利于透射更多的用于被传感器感测的光，改善感测质量。
例如，多个第二子像素P2阵列排布在第二显示区域20，每个第二子像素P2包括发光元件以及与该发光元件电连接的像素电路，第二子像素P2的像素电路配置为驱动第二子像素P2的发光元件发光。多个第二子像素P2的发光元件和像素电路(即图3B中第二显示区域20内的白色方框包括第二子像素P2的发光元件和像素电路)均位于第二显示区域20。 例如，在垂直于衬底基板的方向上，第二子像素P2的发光元件和第二子像素P2的像素电路层叠设置，且第二子像素P2的发光元件设置在第二子像素P2的像素电路的靠近显示侧的一侧。
例如，多个第一子像素P1的发光元件和多个第二子像素P2的发光元件分别在第一显示区域10和第二显示区域20中排列均匀，由此可以实现第一显示区域10和第二显示区域20整体上均匀发光与显示。
例如，如图3A所示，衬底基板还包括至少部分围绕第二显示区域20的第三显示区域30。例如，第一显示区域10、第二显示区域20和第三显示区域30互不重叠。需要说明是，在一些示例中，衬底基板还可以包括周边区域，该周边区域至少部分围绕第三显示区域30。
例如，如图3B所示，第三显示区域30中设置有阵列排布的多个第三子像素P3，多个第三子像素P3的发光元件和像素电路均位于第三显示区域30。例如，第三子像素P3的像素电路可以包括7个晶体管和一个电容，例如图2所示的晶体管T11、T21、T31、T4～T7以及电容C所构成的电路，即具有常规的7T1C像素电路结构。
例如，多个第三子像素P3的发光元件在第三显示区域30内的单位面积分布密度大于多个第一子像素P1的发光元件在第一显示区域10内的单位面积分布密度，也大于多个第二子像素P2的发光元件在第二显示区域20内的单位面积分布密度。例如，第一显示区域10中的发光元件的单位面积分布密度小于第二显示区域20中的发光元件的单位面积分布密度。例如，第一显示区域10和第二显示区域20可以被称为显示基板的低像素密度区域，相应地，第三显示区域30可以被称为显示基板的高像素密度区域。需要说明的是，在一些示例中，第一显示区域10中的发光元件的单位面积分布密度也可以等于第二显示区域20中的发光元件的单位面积分布密度，这可以根据实际需求而定，本公开的实施例对此不作限制。
例如，多个第一子像素P1/多个第二子像素P2/多个第三子像素P3的排布方式可以参考常规的子像素排布方式，例如GGRB、RGBG、RGB等，本公开的实施例对此不作限制。
例如，第一显示区域10的形状大体上可以为圆形或椭圆形，第二显示区域20的形状大体上可以为具有镂空的圆形或椭圆形的矩形，第三显示区域30的形状大体上可以为具有镂空矩形的矩形，但本公开的实施例不限于此。又例如，第一显示区域10、第二显示区域20和第三显示区域30的形状可以均为矩形或者其它适用的形状。需要说明的是，虽然图3A和图3B中示出的第一显示区域10、第二显示区域20和第三显示区域30的形状均为规则的形状，然而，在实际版图上，第一显示区域10、第二显示区域20和第三显示区域30的形状可以是不规则的，例如，第一显示区域10的形状实际上是不规则的圆形。
图4A为本公开一些实施例提供的一种第一重复单元的排列示意图，图4B为本公开一些实施例提供的一种第二重复单元的排列示意图，图4C为本公开一些实施例提供的一种像素区域的排列示意图，图4D为本公开一些实施例提供的另一种像素区域的排列示意图。
例如，如图4C所示，第一显示区域10包括与多个第一子像素和多个第二子像素的像素电路一一对应的多个像素区域PD，多个像素区域PD排列为多行多列，图4C示出了四行四列的像素区域PD。如图4C所示，第一方向X为多个像素区域PD的行方向，第二方向Y为多个像素区域PD的列方向，例如，第一方向X和第二方向Y彼此垂直。
例如，如图4C所示，多个像素区域PD中的每个像素区域PD包括彼此不重叠的第一子区域PD1和第二子区域PD2。需要说明的是，图4C中有阴影的矩形区域表示第二子区域PD2。
例如，像素电路100中的第一驱动电路、第一发光控制电路、存储电路和数据写入电路位于对应的像素区域PD的第一子区域PD1，例如，像素电路100中的第一初始化电路、第二初始化电路和阈值补偿电路也位于对应的像素区域PD的第一子区域PD1；像素电路100中的第二驱动电路和第二发光控制电路位于对应的像素区域PD的第二子区域PD2。也就是说，第一驱动晶体管T11、第一发光控制晶体管T21、第二发光控制晶体管T31、数据写入晶体管T4、阈值补偿晶体管T5、第一初始化晶体管T6和第二初始化晶体管T7位于对应的像素区域PD的第一子区域PD1，而第二驱动晶体管T12、第三发光控制晶体管T22和第四发光控制晶体管T32位于对应的像素区域PD的第二子区域PD2。
例如，在一些实施例中，第一子区域PD1的面积可以等于第二子区域PD2的面积，但本公开不限于此，第一子区域PD1的面积和第二子区域PD2的面积根据实际情况确定。
例如，如图4A～4C所示，每个像素区域PD的第一子区域PD1包括在第一方向X上的彼此相对的第一侧和第二侧，例如，第一子区域PD1的第一侧为图4A～4C中的左侧，第一子区域PD1的第二侧为图4A～4C中的右侧。需要说明的是，“左侧”和“右侧”是从观看者的角度进行划分的。
例如，多个第一子像素P1的像素电路构成多个第一重复单元RP1，多个第二子像素P2的像素电路构成多个第二重复单元RP2。例如，每个第一重复单元RP1包括排列为两行两列的四个第一子像素的像素电路，每个第二重复单元RP2包括排列为两行两列的四个第二子像素的像素电路。
例如，如图4A所示，在第一重复单元RP1中，四个第一子像素P1的像素电路中位于第一行第一列的第一子像素P1的像素电路对应的像素区域PD中的第二子区域PD2位于第一子区域PD1的第一侧；四个第一子像素P1的像素电路中位于第二行第一列的第一子像素P1的像素电路对应的像素区域PD中的第二子区域PD2位于第一子区域PD1的第一侧；四个第一子像素P1的像素电路中位于第一行第二列的第一子像素P1的像素电路对应的像素区域PD中的第二子区域PD2位于第一子区域PD1的第二侧；四个第一子像素P1的像素电路中位于第二行第二列的第一子像素P1的像素电路对应的像素区域PD中的第二子区域PD2位于第一子区域PD1的第二侧。也就是说，在第一重复单元RP1中，在第一方向X上，四个第一子区域PD1位于四个第二子区域PD2的之间。
例如，如图4B所示，在第二重复单元RP2中，四个第二子像素P2的像素电路中位于第一行第一列的第二子像素P2的像素电路对应的像素区域PD中的第二子区域PD2位于第一子区域PD1的第二侧；四个第二子像素P2的像素电路中位于第二行第一列的第二子像素P2的像素电路对应的像素区域PD中的第二子区域PD2位于第一子区域PD1的第二侧；四个第二子像素P2的像素电路中位于第一行第二列的第二子像素P2的像素电路对应的像素区域PD中的第二子区域PD2位于第一子区域PD1的第一侧；四个第二子像素P2的像素电路中位于第二行第二列的第二子像素P2的像素电路对应的像素区域PD中的第二子区域PD2位于第一子区域PD1的第一侧。也就是说，在第二重复单元RP2中，在第一方向X上，四个第二子区域PD2位于四个第一子区域PD1的之间。
例如，如图4C和图4D所示，在衬底基板300上，在第一方向X上，多个第一重复单元RP1间隔设置，多个第二重复单元RP2也间隔设置；在第二方向Y上，多个第一重复单元RP1间隔设置，多个第二重复单元RP2也间隔设置；也就是说，在第一方向X上，任意相邻的两个第一重复单元RP1之间具有一个第二重复单元RP2，任意相邻的两个第二重复单元RP2之间具有一个第一重复单元RP1；类似地，在第二方向Y上，任意相邻的两个第一重复单元RP1之间具有一个第二重复单元RP2，任意相邻的两个第二重复单元RP2之间具有一个第一重复单元RP1。
例如，多个第一重复单元RP1和多个第二重复单元RP2构成多个重复单元组，多个重复单元组中的每个重复单元组包括两个第一重复单元RP1和两个第二重复单元RP2，即两个第一重复单元RP1和两个第二重复单元RP2构成一个重复单元组，也就是说，每个重复单元组包括16个像素区域，图4C示出了一个重复单元组。如图4D所示，在衬底基板上，多个重复单元组阵列排布。在每个重复单元组中，两个第一重复单元RP1和两个第二重复单元RP2排列为两行两列，在图4C所示的示例中，两个第一重复单元RP1分别位于第一行和第二列和第二行第一列，两个第二重复单元RP2分别位于第一行第一列和第二行第二列。需要说明的是，本公开的实施例不限于此，在另一些实施例中，两个第一重复单元RP1分别位于第一行第一列和第二行第二列，两个第二重复单元RP2分别位于第一行第二列和第二行第一列。
例如，在第一重复单元RP1和第二重复单元RP2中，四个第一子像素P1中位于第一行第一列的第一子像素P1和四个第二子像素P2中位于第一行第一列的第二子像素P2为红色子像素；四个第一子像素P1中位于第二行第一列的第一子像素P1和四个第二子像素P2中位于第二行第一列的第二子像素P2为蓝色子像素；四个第一子像素P1中位于第一行第二列的第一子像素P1、四个第一子像素P1中位于第二行第二列的第一子像素P1、四个第二子像素P2中位于第一行第二列的第二子像素P2和四个第二子像素P2中位于第二行第二列的第二子像素P2为绿色子像素。
需要说明的是，虽然图4A～图4D中示出的像素区域PD、第一子区域PD1和第二子区 域PD2的形状均为规则的矩形，然而，在实际版图上，像素区域PD、第一子区域PD1和第二子区域PD2的形状是不规则的，第一子区域PD1和第二子区域PD2可能具有重叠的部分，也可能彼此间隔。
例如，第三显示区域30包括与多个第三子像素的像素电路一一对应的多个像素区域，第三子像素P3的像素电路对应的像素区域的面积小于第一子像素P1/第二子像素P2的像素电路对应的像素区域PD的面积，例如，第三子像素P3的像素电路对应的像素区域的面积为第一子像素P1/第二子像素P2的像素电路对应的像素区域PD的面积的一半。
例如，如图4C和图4D所示，显示基板上还设置有多条数据线，例如，多条数据线包括第一数据线Vd1～第八数据线Vd8。与像素区域PD中的第一子区域PD1有交叠的数据线与该像素区域PD中的像素电路电连接，以提供数据电压。也就是说，如图4C所示，在第二重复单元RP2中，第一数据线Vd1与位于第一行第一列的第二子像素的像素电路和位于第二行第一列的第二子像素的像素电路电连接，第四数据线Vd4与位于第一行第二列的第二子像素的像素电路和位于第二行第二列的第二子像素的像素电路电连接；在第一重复单元RP1中，第六数据线Vd6与位于第一行第三列的第一子像素的像素电路和位于第二行第三列的第一子像素的像素电路电连接，第七数据线Vd7与位于第一行第四列的第一子像素的像素电路和位于第二行第四列的第一子像素的像素电路电连接。此外，类似地，第五数据线Vd5与位于第三行第三列的第二子像素的像素电路和位于第四行第三列的第二子像素的像素电路电连接，第八数据线Vd8与位于第三行第四列的第二子像素的像素电路和位于第四行第四列的第二子像素的像素电路电连接；第二数据线Vd2与位于第三行第一列的第一子像素的像素电路和位于第四行第一列的第一子像素的像素电路电连接，第三数据线Vd3与位于第三行第二列的第一子像素的像素电路和位于第四行第二列的第一子像素的像素电路电连接。
例如，如图4C所示，第一数据线Vd1～第八数据线Vd8沿第二方向Y延伸，第一数据线Vd1、第四数据线Vd4、第六数据线Vd6和第七数据线Vd7从下向上延伸，第二数据线Vd2、第三数据线Vd3、第五数据线Vd5和第八数据线Vd8从上向下延伸。
例如，如图4D所示，与第一子像素连接的数据线穿过第一显示区域，然后经过周边区域，最终延伸到对应的第一子像素的像素电路的像素区域。以第二数据线Vd2和第三数据线Vd3为例，与第二数据线Vd2和第三数据线Vd3连接的第一子像素的发光元件位于第一显示区域10内，例如，位于第三行第一列的像素电路用于驱动位于第一显示区域10内的发光元件201发光，位于第三行第二列的像素电路用于驱动位于第一显示区域10内的发光元件202发光。位于第三行第一列的像素电路通过连接线CL1与对应的发光元件201电连接，从而驱动对应的发光元件201发光；位于第三行第二列的像素电路通过连接线CL2与对应的发光元件202电连接，从而驱动对应的发光元件202发光。例如，第二数据线Vd2穿过第一显示区域10，然后经过周边区域，最终延伸到位于第三行第一列的像素电路的像 素区域；第三数据线Vd3穿过第一显示区域10，然后经过周边区域，最终延伸到位于第三行第二列的像素电路的像素区域。
需要说明的是，在本公开的实施例中，第一子像素的像素电路位于第二显示区域20(即非摄像头区域)，而第一子像素的发光元件则位于第一显示区域10(即摄像头区域)，由于数据线(Vd1～Vd8)在第一显示区域和第二显示区域从左到右(即第一方向X)的排布顺序依次为非摄像头区域(例如，图4D所示的第二显示区域20的左侧部分)-摄像头区域(例如，图4D所示的第一显示区域10，即中间部分)-非摄像头区域(例如，图4D所示的第二显示区域20的右侧部分)，因此，属于摄像头区域的数据线(即与第一子像素对应的数据线，例如，数据线Vd2、数据线Vd3、数据线Vd6和数据线Vd7等)只能从图4D所示的下方的与摄像头区域对应的部分沿着第二方向Y延伸并引入摄像头区域内，穿过摄像头区域之后，从周边区域(图4D所示的上方)绕线再引入位于非摄像头区域的第一子像素的像素电路中，而其余属于非摄像头区域的数据线(即与第二子像素对应的数据线，例如，数据线Vd1、数据线Vd4、数据线Vd5和数据线Vd8等)则可以从图4D所示的下方的与非摄像头区域对应的部分沿着第二方向Y延伸并直接引入位于非摄像头区域的第二子像素的像素电路中。
下面的表格1表示常规的7T1C像素电路(例如，图2所示的像素电路中除了第二驱动晶体管T12、第三发光控制晶体管T22和第四发光控制晶体管T32之外的元件)和本公开的图2所示的像素电路的仿真电流。
表格1
Figure PCTCN2021094026-appb-000002
如表格1所示，参考图4A和图4B，R子像素可以表示第一重复单元中位于第一行第一列的第一子像素或第二重复单元中位于第一行第一列的第二子像素，B子像素可以表示第一重复单元中位于第二行第一列的第一子像素或第二重复单元中位于第二行第一列的第二子像素，G1子像素可以表示第一重复单元中位于第一行第二列的第一子像素或第二重复单元中位于第一行第二列的第二子像素，G2子像素可以表示第一重复单元中位于第二行第 二列的第一子像素或第二重复单元中位于第二行第二列的第二子像素。
例如，Ioled表示流过发光元件200的驱动电流。V N1表示N1节点的电压，V N2表示N2节点的电压，V N3表示N3节点的电压，V N4表示N4节点的电压。在表格1中，电压的单位为伏特(V)。
如表格1所示，在实际仿真中，基于常规的7T1C像素电路，R子像素的驱动电流为76.23mA(毫安)，G1子像素的驱动电流为34.56mA，B子像素的驱动电流为127mA，G2子像素的驱动电流为34.57mA；基于图2所示的像素电路，R子像素的驱动电流为174.59mA，G1子像素的驱动电流为95.772mA，B子像素的驱动电流为320.28mA，G2子像素的驱动电流为95.787mA；也就是说，R子像素的驱动电流的电流差异为229％，即对于R子像素，基于图2所示的像素电路得到的驱动电流为基于常规的7T1C像素电路得到的驱动电流2.29倍；G1子像素的驱动电流的电流差异为227.1％，即对于G1子像素，基于图2所示的像素电路得到的驱动电流为基于常规的7T1C像素电路得到的驱动电流2.271倍；B子像素的驱动电流的电流差异为252.2％，即对于B子像素，基于图2所示的像素电路得到的驱动电流为基于常规的7T1C像素电路得到的驱动电流2.522倍；G2子像素的驱动电流的电流差异为227.1％，即对于G2子像素，基于图2所示的像素电路得到的驱动电流为基于常规的7T1C像素电路得到的驱动电流2.271倍。
需要说明的是，在本次仿真中，电流差异均大于两倍，实际上，在不同的仿真中，电流差异并不相同，电流差异为一倍以上、两倍以上等，都是符合预期要求的。
图5A～5E为本公开一些实施例提供的一种像素电路的各功能层的结构示意图。下面结合附图5A～5E描述像素电路中的各个元件在背板上的位置关系，图5A-5E所示的示例以图2所示的像素电路100为例。
例如，如图5A～5E所示，像素电路100具有有源半导体层510、第一功能层540、第二功能层530和第三功能层520，图5E为有源半导体层510、第一功能层540、第二功能层530和第三功能层520的层叠位置关系的示意图。下面结合图5A～5E详细描述有源半导体层510、第一功能层540、第二功能层530和第三功能层520的结构。例如，图5A-5E所示的各个层结构对应于一个重复单元组中的16个子像素。
如图2所示，像素电路100包括图2所示的第一驱动晶体管T11、第二驱动晶体管T12、第一发光控制晶体管T21、第二发光控制晶体管T31、第三发光控制晶体管T22、第四发光控制晶体管T32、数据写入晶体管T4、存储电容C、阈值补偿晶体管T5、第一初始化晶体管T6和第二初始化晶体管T7。图5A～5E还示出了连接到像素电路100的第一扫描线G1、第二扫描线G1、第一电源线VDD1、第二电源线VDD2、电源连接线VDDc1、第一发光控制信号线EM1至第四发光控制信号线EM4、第一初始化电压线Vinit1、第二初始化电压线Vinit2、第一初始化控制信号线Rst1、第二初始化控制信号线Rst2、数据线Vd等。
需要说明的是，在图5A至5E所示的示例中，第一扫描线G1和第二扫描线G2为同一 条信号线，第一发光控制信号线EM1至第四发光控制信号线EM4为同一条信号线。例如，第一初始化控制信号线Rst1和第二初始化控制信号线Rst2为不同的信号线，第一初始化控制信号线Rst1连接至位于第n行的子像素的像素电路中的第一初始化电路和位于第(n-1)行(图中未示出)的子像素的像素电路中的第二初始化电路，第二初始化控制信号线Rst2连接至位于第n行的子像素的像素电路中的第二初始化电路和位于第(n+1)行的子像素的像素电路中的第一初始化电路。类似地，第一初始化电压线Vinit1和第二初始化电压线Vinit2为不同的信号线，第一初始化电压线Vinit1连接至位于第n行的子像素的像素电路中的第一初始化电路和位于第(n-1)行的子像素的像素电路中的第二初始化电路，第二初始化电压线Vinit2连接至位于第n行的子像素的像素电路中的第二初始化电路和位于第(n+1)行的子像素的像素电路中的第一初始化电路。
例如，图5A～5D中，每个矩形框表示的部分为一个像素电路100对应的像素区域。
例如，图5A示出了该像素电路100的有源半导体层510，图6A为图5A中矩形虚线框的放大示意图。有源半导体层510可采用半导体材料图案化形成在衬底基板上。有源半导体层510可用于制作上述的第一驱动晶体管T11、第二驱动晶体管T12、第一发光控制晶体管T21、第二发光控制晶体管T31、第三发光控制晶体管T22、第四发光控制晶体管T32、数据写入晶体管T4、阈值补偿晶体管T5、第一初始化晶体管T6和第二初始化晶体管T7的有源层，各有源层可包括源极区域、漏极区域和源极区域和漏极区域之间的沟道区。例如，第一驱动晶体管T11、第一发光控制晶体管T21、第二发光控制晶体管T31、数据写入晶体管T4、阈值补偿晶体管T5、第一初始化晶体管T6和第二初始化晶体管T7的有源层一体设置，第二驱动晶体管T12、第三发光控制晶体管T22和第四发光控制晶体管T32的有源层一体设置，虽然如此，各个晶体管的沟道区可以由于对应的栅极上的扫描信号而变得可导电或恢复为不导电，但是各个晶体管之间的有源层的部分由于不受扫描信号的影响而不会变得导电，因此该一体设置不会导致各个晶体管之间的串扰。
需要说明的是，对于第二初始化晶体管T7，在图5A和图6A所示的示例中，第二初始化晶体管T7与相邻的下一行的像素电路中的第一初始化晶体管共用初始化电压线和初始化控制信号线，因此，在版图上，位于第n行的子像素的像素电路中的第二初始化晶体管T7位于第(n+1)行的子像素的像素电路对于的像素区域内。
例如，第一驱动晶体管T11的有源层的形状和第二驱动晶体管T12的有源层的形状可以相同，第一驱动晶体管T11的有源层、第一发光控制晶体管T21的有源层和第二发光控制晶体管T31的有源层之间的相对位置关系和第二驱动晶体管T12的有源层、第三发光控制晶体管T22的有源层和第四发光控制晶体管T32的有源层之间的相对位置关系相同。
例如，有源半导体层510可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。在本公开实施例中，掺杂的源极区域对应晶体管的源极(例如晶体管的第一极)，掺杂的漏极区域对应晶 体管的漏极(例如晶体管的第二极)。
例如，如图5A和图6A所示，在第二方向Y上，数据写入晶体管T4的有源层、阈值补偿晶体管T5的有源层、第一初始化晶体管T6的有源层和第二初始化晶体管T7的有源层位于第一驱动晶体管T11的有源层的第一侧，例如，上侧；第一发光控制晶体管T21的有源层和第二发光控制晶体管T31的有源层位于第一驱动晶体管T11的有源层的第二侧，例如，下侧。第一驱动晶体管T11的有源层的第一侧和第二侧为在第二方向Y上第一驱动晶体管T11的有源层的彼此相对的两侧。第三发光控制晶体管T22的有源层和第四发光控制晶体管T32的有源层位于第二驱动晶体管T12的有源层的例如下侧。
需要说明的是，如图5A和图6A所示，有源半导体层510上具有一部分区域Ad，该部分区域Ad并不用于形成晶体管的有源层，而是为了改善像素区域中的第一子区域和第二子区域的刻蚀均一性而设置的；该部分区域Ad的形状不限于图中示出的，例如，也可以包括多个彼此断开的部分。
例如，在上述的有源半导体层510上形成有栅极绝缘层(未示出)，用于保护上述的有源半导体层510。图5B示出了该像素电路100的第三功能层520(例如，第一栅极金属层)，第三功能层520设置在栅极绝缘层上，从而与有源半导体层510绝缘。图6B为图5B中矩形虚线框的放大示意图。
例如，第三功能层520可以包括存储电容C的第一极CC1、第一扫描线G1、第二扫描线G2、第一初始化控制信号线Rst1、第二初始化控制信号线Rst2、第一发光控制信号线EM1至第四发光控制信号线EM4、以及第一驱动晶体管T11、第二驱动晶体管T12、第一发光控制晶体管T21、第二发光控制晶体管T31、第三发光控制晶体管T22、第四发光控制晶体管T32、数据写入晶体管T4、阈值补偿晶体管T5、第一初始化晶体管T6和第二初始化晶体管T7的栅极。例如，存储电容C的第一极CC1复用为第一驱动晶体管T11的栅极，第二驱动晶体管T12的栅极表示为图5B和图6B中的g12。需要说明的是，存储电容C仅仅位于该存储电容C所属的像素电路对应的像素区域的第一子区域中。
例如，如图5B和图6B所示，数据写入晶体管T4的栅极可以为第一扫描线G1与有源半导体层510交叠的部分。阈值补偿晶体管T5可为双栅结构的薄膜晶体管，阈值补偿晶体管T5的第一个栅极可为第二扫描线G2与有源半导体层510交叠的部分，阈值补偿晶体管T5的第二个栅极可为从第二扫描线G2突出的突出部与有源半导体层510交叠的部分。例如，第一扫描线G1和第二扫描线G2为同一条信号线，也就是说，第一扫描线G1(即第二扫描线G2)与有源半导体层510具有三个交叠的部分。
例如，第一发光控制晶体管T21的栅极可以为第一发光控制信号线EM1与有源半导体层310交叠的第一部分，第二发光控制晶体管T31的栅极可以为第一发光控制信号线EM1与有源半导体层310交叠的第二部分，第三发光控制晶体管T22的栅极可以为第一发光控制信号线EM1与有源半导体层310交叠的第三部分，第四发光控制晶体管T32的栅极可以 为第一发光控制信号线EM1与有源半导体层310交叠的第四部分，如图5A和图6A所示，第一发光控制信号线EM1与有源半导体层310交叠的第一部分、第二部分、第三部分和第四部分沿第一方向X依次排列。
例如，第一初始化晶体管T6也可为双栅结构的薄膜晶体管，第一初始化晶体管T6的两个栅极分别为第一初始化控制信号线Rst1与有源半导体层510交叠的第一部分和第二部分，第二初始化晶体管T7的栅极为第一初始化控制信号线Rst1与有源半导体层310交叠的第三部分。如图5A和图6A所示，第一初始化控制信号线Rst1与有源半导体层310交叠的第一部分、第二部分和第三部分沿第一方向X依次排列。
需要说明的是，图5A和图6A中的各虚线矩形框示出了在垂直于衬底基板的方向上第三功能层520与有源半导体层510交叠的各个部分。
例如，如图5B和图6B所示，第一扫描线G1/第二扫描线G2、第一初始化控制信号线Rst1、第二初始化控制信号线Rst2和第一发光控制信号线EM1至第四发光控制信号线EM4大致上沿第一方向X延伸，且沿第二方向Y排布。第一扫描线G1/第二扫描线G2位于第一初始化控制信号线Rst1和第一发光控制信号线EM1至第四发光控制信号线EM4之间，第一发光控制信号线EM1至第四发光控制信号线EM4位于第一扫描线G1/第二扫描线G2和第二初始化控制信号线Rst2之间。
例如，在第一方向X上，存储电容C的第一极CC1位于第一扫描线G1/第二扫描线G2和第一发光控制信号线EM1至第四发光控制信号线EM4之间。从第二扫描线G2突出的突出部位于第二扫描线G2的远离第一发光控制信号线EM1至第四发光控制信号线EM4的一侧。
例如，如图5A、图6A、图5B和图6B所示，在第二方向Y上，数据写入晶体管T4的栅极、阈值补偿晶体管T5的栅极、第一初始化晶体管T6的栅极和第二初始化晶体管T7的栅极位于第一驱动晶体管T11的栅极的第一侧，例如，上侧；第一发光控制晶体管T21的栅极和第二发光控制晶体管T31的栅极位于第一驱动晶体管T11的栅极的第二侧，例如，下侧。第一驱动晶体管T11的栅极的第一侧和第二侧为在第二方向Y上第一驱动晶体管T11的栅极的彼此相对的两侧。例如，第三发光控制晶体管T22的栅极和第四发光控制晶体管T32的栅极位于第二驱动晶体管T12的栅极的例如下侧。
例如，在一些实施例中，如图5A和图6A所示，在第一方向X上，阈值补偿晶体管T5的栅极、第二发光控制晶体管T31的栅极和第二初始化晶体管T7的栅极均位于第一驱动晶体管T11的栅极的第三侧，例如，左侧；数据写入晶体管T4的栅极和第一发光控制晶体管T21的栅极均位于第一驱动晶体管T11的栅极的第四侧，例如，右侧；第一驱动晶体管T11的栅极的第三侧和第四侧为在第一方向X上第一驱动晶体管T11的栅极的彼此相对的两侧。第四发光控制晶体管T32的栅极位于第二驱动晶体管T12的栅极的例如左侧，第三发光控制晶体管T22的栅极位于第二驱动晶体管T12的栅极的例如右侧。
例如，在上述的第三功能层520上形成有第一绝缘层(未示出)，用于保护上述的第三功能层520。图5C示出了该像素电路100的第二功能层530，第二功能层530包括存储电容C的第二极CC2、第一初始化电压线Vinit1、第二初始化电压线Vinit2、电源连接线VDDc1(例如，以下可以称为第一电源连接线VDDc1)、电源连接线VDDc2(例如，以下可以称为第二电源连接线VDDc2)和第三栅极连接线Gc3。图6C为图5C中矩形虚线框的放大示意图。
例如，第一电源连接线VDDc1用于连接第一电源线VDD1和第二电源线VDD2。第二电源连接线VDDc2用于连接与位于同一行的相邻两个子像素的像素电路电连接的第一电源线VDD1，第二电源连接线VDDc2与存储电容C的第二极CC2一体形成。通过第一电源连接线VDDc1和第二电源连接线VDDc2将各个像素电路对应的第一电源线VDD1和第二电源线VDD2连接起来，从而使得所有的第一电源线VDD1和第二电源线VDD2形成网络，有利于降低电源电压降(IR drop)，进而可以提高第一电源线VDD1和第二电源线VDD2提供的电源电压的稳定性。
例如，在垂直于衬底基板的方向上，存储电容C的第一极CC1与存储电容C的第二极CC2至少部分重叠以形成存储电容C。
例如，存储电容C的第二极CC2中包括过孔，阈值补偿晶体管T5的第二极通过该过孔与第一驱动晶体管T11的栅极电连接。
例如，如图5C和图6C所示，第二功能层530还包括第一连接电极块VDDe1和第二连接电极块VDDe2，第一连接电极块VDDe1与第一电源线VDD1电连接，第二连接电极块VDDe2与第二电源线VDD2电连接，第一电源连接线VDDc1用于将第一连接电极块VDDe1电连接至第二连接电极块VDDe2，从而实现将第一电源线VDD1电连接至第二电源线VDD2。
例如，如图5C和图6C所示，第一初始化电压线Vinit1、第二初始化电压线Vinit2、第三栅极连接线Gc3、第一电源连接线VDDc1和第二电源连接线VDDc2大致上沿第一方向X延伸。在第二方向Y上，第一电源连接线VDDc1位于第三栅极连接线Gc3和第二电源连接线VDDc2之间，第三栅极连接线Gc3位于第一初始化电压线Vinit1和第一电源连接线VDDc1之间，第二电源连接线VDDc2位于第二初始化电压线Vinit2和第一电源连接线VDDc1之间。
例如，在上述的第二功能层530上形成有第二绝缘层(未示出)，用于保护上述的第二功能层530。图5D示出了该像素电路100的第一功能层540，第一功能层540包括第一数据线Vd1至第八数据线Vd8(图5D中仅标记了第一数据线Vd1和第二数据线Vd2)、第一电源线VDD1、第二电源线VDD2、第一栅极连接线Gc1和第二栅极连接线Gc2。图6D为图5D中矩形虚线框的放大示意图。
例如，如图5D和图6D所示，第一数据线Vd1、第二数据线Vd2、第一电源线VDD1、 第二电源线VDD2、第一栅极连接线Gc1和第二栅极连接线Gc2大致上沿第二方向Y延伸。在第一方向X上，第一电源线VDD1位于第一栅极连接线Gc1和第一数据线Vd1之间，第一数据线Vd1位于第一电源线VDD1和第二栅极连接线Gc2之间，第二栅极连接线Gc2位于第一数据线Vd1和第二电源线VDD2之间，第二电源线VDD2位于第二栅极连接线Gc2和第二数据线Vd2之间。
图5E为上述的有源半导体层510、第三功能层520、第二功能层530和第一功能层540的层叠位置关系的示意图。如图5D、图6D和5E所示，第一数据线Vd1通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔h1)与有源半导体层510中的数据写入晶体管T4的源极区域相连。
第一电源线VDD1通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔h2)与有源半导体层310中对应的第一发光控制晶体管T21的源极区域相连；第一电源线VDD1通过第二绝缘层中的至少一个过孔(例如，h4)与第二功能层530中的存储电容的第二极CC2相连。第一电源线VDD1还通过第二绝缘层中的至少一个过孔(例如，过孔h5)与第二导电层330中的第一连接电极块VDDe1相连。
第二电源线VDD2通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔h3)与有源半导体层310中对应的第三发光控制晶体管T22的源极区域相连；第二电源线VDD2通过第二绝缘层中的至少一个过孔(例如，h6)与第二功能层530中的第二连接电极块VDDe2相连。
例如，如图5D、图6D和5E所示，第一功能层540还包括第一连接部541、第二连接部542、第三连接部543和第四连接部544。
第一连接部541的一端通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔h7)与有源半导体层510中对应的阈值补偿晶体管T5的漏极区域相连，第一连接部541的另一端通过第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔h8)与第三功能层520中的第一驱动晶体管T11的栅极(即存储电容C的第一极CC1)相连。
第二连接部542的一端通过第二绝缘层中的一个过孔(例如，过孔h9)与第一初始化电压线Vinit1相连，第二连接部542的另一端通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔h10)与有源半导体层510中的第一初始化晶体管T6的漏极区域相连。
例如，如图5D和图6D所示，第(n+1)行的子像素的像素电路的第一功能层包括连接部542’，连接部542’的一端通过第二绝缘层中的一个过孔(例如，过孔h9’)与第二初始化电压线Vinit2相连，连接部542’的另一端通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔h10’)与有源半导体层510中的第二初始化晶体管T7的漏极区域相连，从而第二初始化晶体管T7的第一极电连接至第二初始化电压线Vinit2，第二初始化晶体管T7的第二极最终连接至发光元件的第一极(即阳极)。
需要说明的是，由于第四发光控制晶体管T32的第二极也电连接至发光元件的第一极，从而第二初始化晶体管T7的第二极也电连接至第四发光控制晶体管T32的第二极。
第三连接部543通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔h11)与有源半导体层510中的第二发光控制晶体管T31的漏极区域相连。
第四连接部544通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔h12)与有源半导体层510中的第四发光控制晶体管T32的漏极区域相连。
例如，第一栅极连接线Gc1和第一连接部541一体设置。例如，第一栅极连接线Gc1的远离第一连接部541的一端通过第二绝缘层中的至少一个过孔(例如，过孔h13)与第二功能层530中的第三栅极连接线Gc3相连。
例如，第二栅极连接线Gc2的一端通过第二绝缘层中的至少一个过孔(例如，过孔h14)与第二功能层530中的第三栅极连接线Gc3相连，第二栅极连接线Gc2的另一端通过第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔h15)与第三功能层520中的第二驱动晶体管T12的栅极相连。
需要说明的是，如图5D和图6D所示，第一功能层540的与有源半导体层510上的区域Ad对应的区域具有第五连接部545，第五连接部545的一端通过第二绝缘层中的一个过孔(例如，过孔h16)与第一初始化电压线Vinit1相连，第五连接部545的另一端通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔h17)与有源半导体层510中的区域Ad相连。类似地，第五连接部545也是为了保证像素区域中的第一子区域和第二子区域的刻蚀均一性而设置的，并不作为像素电路100的一部分。
例如，在上述的第一功能层540上形成有中间层(未示出)，用于保护上述的第一功能层540。各个子像素的发光元件的第一极可设置在中间层远离衬底基板的一侧。
需要说明的是，每个像素电路中的第一驱动电路、第二驱动电路、第一发光控制电路、第二发光控制电路、第三发光控制电路、第四发光控制电路、数据写入电路、存储电路、阈值补偿电路、第一初始化电路和第二初始化电路等的位置排布关系不限于图5A～5E所示的示例，可以根据实际应用需求具体设置第一驱动电路、第二驱动电路、第一发光控制电路、第二发光控制电路、第三发光控制电路、第四发光控制电路、数据写入电路、存储电路、阈值补偿电路、第一初始化电路和第二初始化电路的位置。
图7为本公开至少一实施例提供的一种显示面板的示意框图。
本公开至少一实施例提供一种显示面板。例如，如图7所示，显示面板600包括本公开任一实施例提供的显示基板601。
例如，例如，显示面板600可以为有机发光二极管(OLED)显示面板等。例如，当显示面板700为有机发光二极管显示面板时，显示基板601可以为阵列基板。
例如，显示面板600可以为矩形面板、圆形面板、椭圆形面板或多边形面板等。另外，显示面板600不仅可以为平面面板，也可以为曲面面板，甚至球面面板。
例如，显示面板600还可以具备触控功能，即显示面板600可以为触控显示面板。
例如，显示面板600可以应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件中。
图8为本公开至少一个实施例提供的一种显示装置的示意框图。
本公开至少一实施例提供一种显示装置。如图8所示，该显示装置700包括显示面板701以及传感器702，显示面板701为本公开任一实施例提供的显示面板，例如前述的显示面板600。传感器702设置于显示面板的显示基板的第二侧(非显示侧)，且传感器702配置为接收来自显示基板的第一侧(显示侧)的光。例如，传感器702可以为摄像头、红外传感器等任意形式的传感器。
例如，在一些实施例中，在垂直于显示基板的板面的方向上，传感器702与显示基板的第一显示区域10至少部分重叠，从而可充分接受来自显示基板的第一侧的光，并基于该光进行工作。
例如，该显示装置700可以为任何具有显示功能的电子装置，例如智能手机、笔记本电脑、平板电脑、电视等。例如，当显示装置700为智能手机或平板电脑时，该智能手机或平板电脑可以具有全面屏设计，也即是，没有围绕第三显示区域30的周边区域。并且，该智能手机或平板电脑还具有屏下传感器(例如摄像头、红外传感器等)，可以进行图像拍摄、距离感知、光强感知等操作。
例如，显示装置可以为电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开的实施例对此不作限制。
需要说明的是，对于该显示面板701和显示装置700的其它组成部分(例如控制装置、图像数据编码/解码装置、栅极驱动器、定时控制器、时钟电路等)均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本发明的实施例的附图中，层或结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种像素电路，包括：第一驱动电路、第二驱动电路、第一发光控制电路、第二发光控制电路、存储电路和数据写入电路，
    其中，所述第一发光控制电路电连接至第一电源线、所述第一驱动电路和发光元件，且被配置为控制所述第一驱动电路和所述发光元件之间的连接导通或断开和控制所述第一驱动电路和所述第一电源线之间的连接导通或断开；
    所述第二发光控制电路电连接至第二电源线、所述第二驱动电路和所述发光元件，且被配置为控制所述第二驱动电路和所述发光元件之间的连接导通或断开和控制所述第二驱动电路和所述第二电源线之间的连接导通或断开；
    所述数据写入电路与所述第一驱动电路电连接，且被配置为将数据电压写入所述第一驱动电路；
    所述第一驱动电路和所述第二驱动电路被配置为基于同一所述数据电压控制驱动所述发光元件发光的驱动电流；
    所述存储电路电连接至所述第一驱动电路的控制端和所述第二驱动电路的控制端，且被配置为保持所述第一驱动电路的控制端和所述第二驱动电路的控制端的电压。
  2. 根据权利要求1所述的像素电路，还包括电源连接线，
    其中，所述第一电源线和所述第二电源线通过所述电源连接线彼此电连接。
  3. 根据权利要求2所述的像素电路，其中，所述像素电路位于衬底基板上，所述像素电路具有第一功能层和第二功能层，所述第一功能层和所述第二功能层位于所述衬底基板上，且在垂直于所述衬底基板的方向上，所述第一功能层位于所述第二功能层的远离所述衬底基板的一侧，
    所述第一电源线和所述第二电源线位于所述第一功能层，
    所述电源连接线位于所述第二功能层，
    所述电源连接线通过过孔电连接至所述第一电源线和所述第二电源线。
  4. 根据权利要求1所述的像素电路，其中，所述第一驱动电路的控制端和所述第二驱动电路的控制端电连接。
  5. 根据权利要求4所述的像素电路，还包括第一栅极连接线、第二栅极连接线和第三栅极连接线，
    其中，所述第一驱动电路的控制端和所述第二驱动电路的控制端通过所述第一栅极连接线、所述第二栅极连接线和所述第三栅极连接线进行电连接，
    所述第一驱动电路的控制端与所述第一栅极连接线电连接，所述第二驱动电路的控制端与所述第二栅极连接线电连接，
    所述第三栅极连接线用于电连接所述第一栅极连接线和所述第二栅极连接线以将所述 第一驱动电路的控制端电连接至所述第二驱动电路的控制端。
  6. 根据权利要求5所述的像素电路，其中，所述像素电路位于衬底基板上，所述像素电路具有第一功能层和第二功能层，所述第一功能层和所述第二功能层位于所述衬底基板上，且在垂直于所述衬底基板的方向上，所述第一功能层位于所述第二功能层的远离所述衬底基板的一侧，
    所述第一栅极连接线和所述第二栅极连接线位于所述第一功能层，
    所述第三栅极连接线位于所述第二功能层，
    所述第三栅极连接线通过过孔连接至所述第一栅极连接线和所述第二栅极连接线。
  7. 根据权利要求4或5所述的像素电路，其中，所述第一驱动电路包括第一驱动晶体管，所述第二驱动电路包括第二驱动晶体管，
    所述第一驱动电路的控制端包括所述第一驱动晶体管的栅极，所述第二驱动电路的控制端包括所述第二驱动晶体管的栅极，
    所述第一驱动晶体管的阈值电压和所述第二驱动晶体管的阈值电压相同。
  8. 根据权利要求1～7任一项所述的像素电路，还包括阈值补偿电路，
    其中，所述阈值补偿电路与所述第一驱动电路的控制端和所述第二驱动电路的控制端电连接，且被配置为对所述第一驱动电路进行阈值补偿。
  9. 根据权利要求1～8任一项所述的像素电路，还包括第一初始化电路和第二初始化电路，
    其中，所述第一初始化电路电连接至所述第一驱动电路的控制端和所述第二驱动电路的控制端，且配置为对所述第一驱动电路的控制端和所述第二驱动电路的控制端进行初始化，
    所述第二初始化电路电连接至所述发光元件的第一极，且配置为对所述发光元件的第一极进行初始化。
  10. 根据权利要求1～9任一项所述的像素电路，其中，所述第一发光控制电路包括第一发光控制子电路和第二发光控制子电路，
    所述第一发光控制子电路与所述第一驱动电路的第一端和所述第一电源线连接，且被配置为实现所述第一驱动电路的第一端和所述第一电源线之间的连接导通或断开，
    所述第二发光控制子电路与所述第一驱动电路的第二端和所述发光元件的第一极电连接，且被配置为实现所述第一驱动电路的第二端和所述发光元件的第一极之间的连接导通或断开。
  11. 根据权利要求1～10任一项所述的像素电路，其中，所述第二发光控制电路包括第三发光控制子电路和第四发光控制子电路，
    所述第三发光控制子电路与所述第二驱动电路的第一端和所述第二电源线连接，且被配置为实现所述第二驱动电路的第一端和所述第二电源线之间的连接导通或断开，
    所述第四发光控制子电路与所述第二驱动电路的第二端和所述发光元件的第一极电连接，且被配置为实现所述第二驱动电路的第二端和所述发光元件的第一极之间的连接导通或断开。
  12. 根据权利要求1、2、4和5中任一项所述的像素电路，还包括阈值补偿电路、第一初始化电路和第二初始化电路，
    其中，所述第一发光控制电路包括第一发光控制子电路和第二发光控制子电路，所述第二发光控制电路包括第三发光控制子电路和第四发光控制子电路，
    所述第一驱动电路包括第一驱动晶体管，所述第二驱动电路包括第二驱动晶体管，所述第一发光控制子电路包括第一发光控制晶体管，所述第二发光控制子电路包括第二发光控制晶体管，所述第三发光控制子电路包括第三发光控制晶体管，所述第四发光控制子电路包括第四发光控制晶体管，所述数据写入电路包括数据写入晶体管，所述存储电路包括存储电容，所述阈值补偿电路包括阈值补偿晶体管，所述第一初始化电路包括第一初始化晶体管，所述第二初始化电路包括第二初始化晶体管，
    所述第一驱动电路的控制端包括所述第一驱动晶体管的栅极，所述第二驱动电路的控制端包括所述第二驱动晶体管的栅极，
    所述数据写入晶体管的第一极电连接至数据线以接收所述数据电压，所述数据写入晶体管的第二极电连接至所述第一驱动晶体管的第一极，所述数据写入晶体管的栅极电连接至第一扫描线；
    所述第一发光控制晶体管的第一极电连接至所述第一电源线，所述第一发光控制晶体管的第二极电连接至所述第一驱动晶体管的第一极，所述第一发光控制晶体管的栅极电连接至第一发光控制信号线；
    所述第二发光控制晶体管的第一极电连接至所述第一驱动晶体管的第二极，所述第二发光控制晶体管的第二极电连接至所述发光元件的第一极，所述第二发光控制晶体管的栅极电连接至第二发光控制信号线；
    所述第三发光控制晶体管的第一极电连接至所述第二电源线，所述第三发光控制晶体管的第二极电连接至所述第二驱动晶体管的第一极，所述第三发光控制晶体管的栅极电连接至第三发光控制信号线；
    所述第四发光控制晶体管的第一极电连接至所述第二驱动晶体管的第二极，所述第四发光控制晶体管的第二极电连接至所述发光元件的第一极，所述第四发光控制晶体管的栅极电连接至第四发光控制信号线，
    所述阈值补偿晶体管的第一极电连接至所述第一驱动晶体管的第二极，所述阈值补偿晶体管的第二极电连接至所述第一驱动晶体管的栅极和所述第二驱动晶体管的栅极，所述阈值补偿晶体管的栅极电连接至第二扫描线；
    所述第一初始化晶体管的第一极电连接至第一初始化电压线，所述第一初始化晶体管 的第二极电连接至所述第一驱动晶体管的栅极和所述第二驱动晶体管的栅极，所述第一初始化晶体管的栅极电连接至第一初始化控制信号线；
    所述第二初始化晶体管的第一极电连接至第二初始化电压线，所述第二初始化晶体管的第二极电连接至所述发光元件的第一极，所述第二初始化晶体管的栅极电连接至第二初始化控制信号线，
    所述存储电容的第一极电连接至所述第一驱动晶体管的栅极和所述第二驱动晶体管的栅极，所述存储电容的第二极电连接至所述第一电源线。
  13. 根据权利要求12所述的像素电路，其中，所述像素电路位于衬底基板上，所述像素电路具有第一功能层、第二功能层和第三功能层，所述第一功能层、所述第二功能层和所述第三功能层位于所述衬底基板上，且在垂直于所述衬底基板的方向上，所述第二功能层位于所述第一功能层和所述第三功能层之间，所述第二功能层位于所述第三功能层的远离所述衬底基板的一侧，所述第一功能层位于所述第二功能层的远离所述衬底基板的一侧，
    所述第一扫描线、所述第二扫描线、所述第一发光控制信号线、所述第二发光控制信号线、所述第三发光控制信号线和所述第四发光控制信号线位于所述第三功能层，
    所述数据线、所述第一电源线和所述第二电源线位于所述第一功能层，
    所述第一初始化电压线和所述第二初始化电压线位于所述第二功能层。
  14. 根据权利要求12或13所述的像素电路，其中，所述第一驱动晶体管和所述第二驱动晶体管在发光阶段将所述驱动电流传输至所述发光元件以驱动所述发光元件发光，
    所述驱动电流表示为：
    I OLED＝K1*(Vgs1-Vth1)+K2*(Vgs2-Vth2)，
    其中，I OLED表示所述驱动电流，K1为所述第一驱动晶体管的工艺常数，Vgs1为在所述发光阶段所述第一驱动晶体管的栅极和第一极之间的电压差，Vth1为所述第一驱动晶体管的阈值电压，K2为所述第二驱动晶体管的工艺常数，Vgs2为在所述发光阶段所述第二驱动晶体管的栅极和第一极之间的电压差，Vth2为所述第二驱动晶体管的阈值电压。
  15. 一种显示基板，包括多个子像素，
    其中，所述多个子像素中的每个包括根据权利要求1～14任一项所述的像素电路和所述发光元件。
  16. 根据权利要求15所述的显示基板，还包括衬底基板，
    其中，所述衬底基板包括第一显示区域，
    所述第一显示区域包括多个像素区域，
    所述多个像素区域中的每个像素区域包括彼此不重叠的第一子区域和第二子区域，
    所述像素电路中的第一驱动电路、第一发光控制电路、存储电路和数据写入电路位于对应的像素区域的第一子区域，
    所述像素电路中的第二驱动电路和第二发光控制电路位于所述对应的像素区域的第二 子区域。
  17. 根据权利要求16所述的显示基板，其中，所述衬底基板还包括第二显示区域，
    所述多个子像素包括多个第一子像素和多个第二子像素，所述多个第一子像素的像素电路和所述多个第二子像素的像素电路与所述多个像素区域一一对应，
    所述第二显示区域至少部分围绕所述第一显示区域，所述显示基板具有用于显示的第一侧和与所述第一侧相对的第二侧，所述第一显示区域允许来自所述第一侧的光至少部分透射至所述第二侧；
    所述多个第一子像素的发光元件位于所述第一显示区域，所述多个第一子像素的像素电路位于所述第二显示区域；
    所述多个第二子像素的发光元件和像素电路均位于所述第二显示区域。
  18. 根据权利要求17所述的显示基板，其中，每个像素区域的第一子区域包括彼此相对的第一侧和第二侧，
    所述多个第一子像素的像素电路构成多个第一重复单元，
    每个所述第一重复单元包括排列为两行两列的四个第一子像素的像素电路，
    所述四个第一子像素的像素电路中位于第一行第一列的第一子像素的像素电路对应的像素区域中的第二子区域位于第一子区域的第一侧，
    所述四个第一子像素的像素电路中位于第二行第一列的第一子像素的像素电路对应的像素区域中的第二子区域位于第一子区域的第一侧，
    所述四个第一子像素的像素电路中位于第一行第二列的第一子像素的像素电路对应的像素区域中的第二子区域位于第一子区域的第二侧，
    所述四个第一子像素的像素电路中位于第二行第二列的第一子像素的像素电路对应的像素区域中的第二子区域位于第一子区域的第二侧，
    所述多个第二子像素的像素电路构成多个第二重复单元，
    每个所述第二重复单元包括排列为两行两列的四个第二子像素的像素电路，
    所述四个第二子像素的像素电路中位于第一行第一列的第二子像素的像素电路对应的像素区域中的第二子区域位于第一子区域的第二侧，
    所述四个第二子像素的像素电路中位于第二行第一列的第二子像素的像素电路对应的像素区域中的第二子区域位于第一子区域的第二侧，
    所述四个第二子像素的像素电路中位于第一行第二列的第二子像素的像素电路对应的像素区域中的第二子区域位于第一子区域的第一侧，
    所述四个第二子像素的像素电路中位于第二行第二列的第二子像素的像素电路对应的像素区域中的第二子区域位于第一子区域的第一侧。
  19. 根据权利要求18所述的显示基板，其中，所述多个第一重复单元和所述多个第二重复单元构成多个重复单元组，所述多个重复单元组中的每个重复单元组包括两个第一重 复单元和两个第二重复单元，
    所述两个第一重复单元和所述两个第二重复单元排列为两行两列，
    所述两个第一重复单元分别位于第一行第二列和第二行第一列，所述两个第二重复单元分别位于第一行第一列和第二行第二列；或者，所述两个第一重复单元分别位于第一行第一列和第二行第二列，所述两个第二重复单元分别位于第一行第二列和第二行第一列。
  20. 根据权利要求18或19所述的显示基板，其中，所述四个第一子像素中位于第一行第一列的第一子像素和所述四个第二子像素中位于第一行第一列的第二子像素为红色子像素，
    所述四个第一子像素中位于第二行第一列的第一子像素和所述四个第二子像素中位于第二行第一列的第二子像素为蓝色子像素，
    所述四个第一子像素中位于第一行第二列的第一子像素、所述四个第一子像素中位于第二行第二列的第一子像素、所述四个第二子像素中位于第一行第二列的第二子像素和所述四个第二子像素中位于第二行第二列的第二子像素为绿色子像素。
  21. 一种显示面板，包括根据权利要求15～20任一项所述的显示基板。
  22. 一种显示装置，包括：根据权利要求21所述的显示面板。
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