WO2023245490A9 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2023245490A9
WO2023245490A9 PCT/CN2022/100394 CN2022100394W WO2023245490A9 WO 2023245490 A9 WO2023245490 A9 WO 2023245490A9 CN 2022100394 W CN2022100394 W CN 2022100394W WO 2023245490 A9 WO2023245490 A9 WO 2023245490A9
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WO
WIPO (PCT)
Prior art keywords
light
display area
compensation
conductive layer
display panel
Prior art date
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PCT/CN2022/100394
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English (en)
French (fr)
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WO2023245490A1 (zh
Inventor
王彬艳
刘聪
程羽雕
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/100394 priority Critical patent/WO2023245490A1/zh
Priority to CN202280001844.0A priority patent/CN117616904A/zh
Publication of WO2023245490A1 publication Critical patent/WO2023245490A1/zh
Publication of WO2023245490A9 publication Critical patent/WO2023245490A9/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • part of the display panel is set to have a higher light transmittance.
  • the camera is placed on the back of the sub-display area.
  • the brightness of the light-emitting devices in the current light-transmitting display area is uneven.
  • the purpose of the present disclosure is to overcome the above-mentioned shortcomings of the prior art and provide a display panel and a display device.
  • a display panel having adjacent main display areas and secondary display areas, the display panel including:
  • a plurality of light-emitting devices arranged in an array in the secondary display area, including a first light-emitting device and a second light-emitting device;
  • a plurality of pixel circuits arranged in an array in the main display area including a first pixel circuit and a second pixel circuit;
  • a plurality of first connection wires connected between the first light-emitting device and the second pixel circuit
  • a plurality of second connection wires are connected between the second light-emitting device and the second pixel circuit, and the capacitance per unit area of the second connection wires is smaller than the capacitance per unit area of the first connection wires;
  • a plurality of compensation parts are connected correspondingly to a plurality of second connection wires.
  • the first light-emitting device and the second light-emitting device are located in the same row and have the same color, and the first light-emitting device is closer to the second light-emitting device than the second light-emitting device.
  • the first pixel circuit is closer to the secondary display area than the second pixel circuit, and the second connection wire is provided on the side of the first connection wire away from the pixel circuit, along The secondary display area points in the direction of the main display area, and the capacitances of the plurality of first connection wires and the plurality of the plurality of said second light-emitting devices are connected to the same row.
  • the capacitance of the second connecting wire increases or decreases linearly.
  • the first light-emitting device and the second light-emitting device are red light-emitting devices and/or blue light-emitting devices.
  • the display panel further includes:
  • a first conductive layer is provided on one side of the base substrate
  • a first insulating layer is provided on the side of the first conductive layer facing away from the base substrate;
  • the second conductive layer is provided on the side of the first insulating layer facing away from the base substrate.
  • the first conductive layer includes the first connection wire
  • the second conductive layer includes the second connection wire
  • the compensation portion is provided on the first conductive layer and/or the second conductive layer.
  • the compensation part includes one or both of a first compensation part and a second compensation part; the first compensation part is provided on the first conductive layer, so The second compensation part is provided on the second conductive layer.
  • the second compensation part is arranged graphically, and part of the edge of the second compensation part is connected to the second connection wire.
  • the display panel further includes:
  • a second insulating layer is provided on the side of the second conductive layer facing away from the base substrate;
  • a third conductive layer is provided on the side of the second insulating layer facing away from the base substrate;
  • the third conductive layer includes the second connection wire
  • the second conductive layer includes the first connection wire
  • the compensation part is provided on the first conductive layer and/or the second conductive layer. layer and/or the third conductive layer.
  • the compensation part includes a first compensation part provided on the first conductive layer, a second compensation part provided on the second conductive layer, or a first compensation part provided on the second conductive layer. At least one of the third compensation parts of the three conductive layers.
  • the first compensation part includes:
  • the first part is connected to the second connecting wire, and the orthographic projection of the first part on the base substrate does not overlap with the orthographic projection of the second connecting wire on the base substrate;
  • the second part is connected to the first part, and the orthographic projection of the second part on the base substrate is located within the orthographic projection of the second connecting wire on the base substrate.
  • the second compensation part includes:
  • the third part is connected to the second connecting wire, and the orthographic projection of the third part on the base substrate does not overlap with the orthographic projection of the second connecting wire on the base substrate;
  • the fourth part is connected to the third part, and the orthographic projection of the fourth part on the base substrate is located within the orthographic projection of the second connecting wire on the base substrate.
  • the third compensation part is arranged in a pattern, and part of an edge of the third compensation part is connected to the second connection wire.
  • the compensation part is provided in the main display area.
  • the main display area includes:
  • a transition area is provided between the auxiliary display area and the normal display area, the pixel circuit is provided in the transition area, and the compensation part is provided in the transition area.
  • multiple pixel circuits in the same row include:
  • the first group of pixel circuits is arranged close to the secondary display area
  • a second group of pixel circuits is provided on the side of the first group of pixel circuits away from the secondary display area;
  • a third group of pixel circuits is provided on the side of the second group of pixel circuits away from the secondary display area;
  • the first group of pixel circuits are connected to the light-emitting device through the first conductive layer
  • the second group of pixel circuits are connected to the light-emitting device through the second conductive layer
  • the third group of pixels The circuit is connected to the light emitting device through the third conductive layer.
  • the display panel further includes:
  • a plurality of third connection wires are provided on the first conductive layer.
  • the plurality of third connection wires are correspondingly connected between the first group of pixel circuits and a plurality of the light-emitting devices.
  • the plurality of first connection wires are The connection wires are correspondingly connected between the second group of pixel circuits and the plurality of light-emitting devices, and the plurality of second connection wires are correspondingly connected between the third group of pixel circuits and the plurality of light-emitting devices.
  • the first compensation part is spaced apart from the third connection wire and is located on a side of the third connection wire away from the secondary display area; the second compensation part The compensation portion is spaced apart from the first connection wire and located on a side of the first connection wire away from the secondary display area.
  • one end of the plurality of first compensation portions close to the secondary display area is flush, and one end of the plurality of second compensation portions close to the secondary display area is flush.
  • the first compensation part includes:
  • the first compensation section is connected to the second connecting wire
  • a first dummy segment is spaced apart from the first compensation segment and located on the side of the first compensation segment close to the secondary display area;
  • the second compensation part includes:
  • a second dummy segment is spaced apart from the second compensation segment and located on the side of the second compensation segment close to the secondary display area;
  • the orthographic projection areas of the plurality of first compensation segments on the base substrate are the same, the orthographic projection areas of the plurality of second compensation segments on the base substrate are the same, and the orthographic projection areas of the plurality of second compensation segments on the base substrate are the same.
  • One end of the first dummy segment close to the auxiliary display area is flush, and one end of the plurality of second dummy segments close to the auxiliary display area is flush.
  • the plurality of light-emitting devices in the same row include:
  • a plurality of green light-emitting devices correspondingly connected to a plurality of the pixel circuits in the same row close to the secondary display area;
  • a plurality of red light-emitting devices and a plurality of blue light-emitting devices are alternately connected to a plurality of pixel circuits in the same row away from the sub-display area.
  • the pixel density of the transition area is equal to the pixel density of the secondary display area, and the pixel density of the normal display area is greater than the pixel density of the secondary display area.
  • the area of the orthographic projection of the light-emitting device in the secondary display area on the base substrate is smaller than the area of the light-emitting device in the transition area on the base substrate. The area of the orthographic projection on.
  • the display panel further includes:
  • a fourth connection wire is connected between the light-emitting device closest to the main display area and the pixel circuit closest to the secondary display area.
  • the fourth connection wire is provided at the source of the pixel circuit. drain layer.
  • a display device includes:
  • the display panel is the display panel mentioned in any of the above items.
  • a photosensitive sensor is provided on the non-display surface of the display panel, and an orthographic projection of the photosensitive sensor on the display surface at least partially overlaps with the auxiliary display area.
  • Figure 1 is a schematic structural diagram of the area division of the display panel.
  • Figure 2 is a schematic structural diagram of the arrangement of sub-pixels, pixel circuits and light-emitting devices in various areas of the display panel.
  • FIG. 3 is a schematic structural diagram of the connection relationship between half of a row of light-emitting devices in the secondary display area and the pixel circuit.
  • FIG. 4 is a schematic diagram of capacitance curves of multiple connection wires connecting multiple light-emitting devices and multiple pixel circuits in the same row.
  • FIG. 5 is a schematic diagram of the luminance brightness curve of multiple light-emitting devices connected to the connecting wires in FIG. 4 .
  • Figure 6 is a schematic structural diagram of a pixel circuit.
  • FIG. 7 is a schematic structural diagram of the display panel according to the first exemplary embodiment of the present disclosure, cut along the first connecting wire.
  • FIG. 8 is a schematic structural diagram of the display panel according to the first exemplary embodiment of the present disclosure, cut along the second connecting wire.
  • FIG. 9 is a schematic top view of the second connection wire of the display panel according to the first exemplary embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a display panel according to a second exemplary embodiment of the present disclosure, cut along a second connecting wire.
  • FIG. 11 is a schematic top view of the second connection wire of the display panel according to the second exemplary embodiment of the present disclosure.
  • Figure 12 is a schematic diagram of the relationship between the third connecting wire or the first connecting wire and the first compensation part or the second compensation part.
  • FIG. 13 is a schematic structural diagram of a third exemplary embodiment of a display panel of the present disclosure.
  • FIG. 14 is a schematic structural diagram of a fourth exemplary embodiment of a display panel of the present disclosure.
  • FIG. 15 is a schematic structural diagram of a fifth exemplary embodiment of a display panel of the present disclosure.
  • Pixel circuit 101. The first group of pixel circuit; 102. The second group of pixel circuit; 103. The third group of pixel circuit; 1001. The first pixel circuit; 1002. The second pixel circuit;
  • Base substrate 12. Light shielding layer; 13. Buffer layer; 14. Active layer; 15. Gate insulating layer; 16. Gate electrode; 17. Interlayer dielectric layer; 181. Source electrode; 182. Drain electrode ;19. Passivation layer;
  • R red light-emitting device
  • G green light-emitting device
  • B blue light-emitting device
  • AA1 main display area; AA11, transition area; AA12, normal display area; AA2, secondary display area; PX, sub-pixel;
  • X first direction
  • Y second direction
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • connection should be understood in a broad sense.
  • connection can be a fixed connection, a detachable connection, or an integral body; it can be a direct connection or a detachable connection. Can be connected indirectly through intermediaries.
  • “And/or” is just an association relationship that describes related objects. It means that there can be three relationships. For example, A and/or B can mean: A alone exists, A and B exist simultaneously, and B alone exists. situation.
  • the character "/" in this article generally indicates that the related objects are an "or” relationship.
  • the circuit 10 drives the luminescence and luminous intensity of the light-emitting device 20 through the pixel circuit 10 .
  • the connecting wires need to be arranged on different conductive layers.
  • the conductive layer closer to the pixel circuit 10 can form a capacitance with the conductor layer in the pixel circuit 10, so that the conductive layer is closer to the pixel.
  • the capacitance per unit area of the conductive layer of the circuit 10 is greater than the capacitance per unit area of the conductive layer far away from the pixel circuit 10. Therefore, the capacitance gap of the connecting wires connecting the light-emitting devices 20 in the same row is large and cannot form a linear shape.
  • L2 represents the capacitance of the connecting wires disposed close to the conductive layer of the pixel circuit 10, and the capacitance of these connecting wires is relatively large
  • L1 represents the capacitance of the connecting wires disposed far away from the conductive layer of the pixel circuit 10, and the capacitance of these connecting wires is relatively large.
  • Small especially when two adjacent connecting wires are located on different conductive layers, the capacitance of the two adjacent connecting wires will suddenly change, resulting in a difference in the brightness of the light-emitting devices 20 in the same row.
  • the vertical direction in Figure 5 The coordinates represent the brightness, and the numbers at each point represent the light-emitting devices connected to the connecting wires in Figure 4.
  • the maximum brightness difference is approximately 11.69.
  • Example embodiments of the present disclosure provide a display panel. As shown in FIGS. 1 to 13 , the display panel has adjacent main display area AA1 and auxiliary display area AA2 .
  • the display panel may include multiple light-emitting devices 20 , multiple a pixel circuit 10, a plurality of first connection wires 31, a plurality of second connection wires 32 and a plurality of compensation parts 33; a plurality of light-emitting devices 20 are arranged in an array in the sub-display area AA2, including the first light-emitting device 201 and the second light-emitting device 20.
  • the light-emitting device 202; a plurality of pixel circuits 10 are arranged in an array in the main display area AA1, including a first pixel circuit 1001 and a second pixel circuit 1002; a plurality of first connection wires 31 are connected to the first light-emitting device 201 and the first pixel circuit 1001; multiple second connection wires 32 are connected between the second light-emitting device 202 and the second pixel circuit 1002, and the unit area capacitance of the second connection wires 32 is smaller than the unit area capacitance of the first connection wire 31; multiple compensation The portion 33 is connected correspondingly to a plurality of second connection wires 32 .
  • the unit area capacitance of the second connection wire 32 is smaller than the unit area capacitance of the first connection wire 31 , and the plurality of compensation parts 33 are connected to the plurality of second connection wires 32 in one-to-one correspondence.
  • the capacitance of the second connection wire 32 is compensated by the compensation part 33 to increase the capacitance of the second connection wire 32 and reduce the difference between the capacitance of the second connection wire 32 and the capacitance of the first connection wire 31, thereby reducing the capacitance of the second connection wire 32 and the capacitance of the first connection wire 31.
  • the brightness difference of the small light emitting device 20 is small.
  • the display panel can be an OLED (Organic Electroluminescence Display, organic light-emitting semiconductor) display panel, a QLED (Quantum Dot Light Emitting Diodes, quantum dot light-emitting diode) display panel, etc.; the display panel has a light emitting side and a non-light emitting side, and a light emitting side and a non-light emitting side. The two sides are arranged oppositely, and the picture can be displayed on the light-emitting side, and the side showing the picture is the display surface.
  • OLED display panels have the characteristics of self-illumination, high brightness, wide viewing angle, fast response time, and the ability to produce R, G, and B full-color components. Therefore, they are regarded as the star products of next-generation displays.
  • the display panel may be divided into a secondary display area AA2 and a main display area AA1.
  • the main display area AA1 may include a transition area AA11 and a normal display area AA12.
  • the transition area AA11 surrounds the main display area AA1
  • the normal display area AA12 surrounds the transition area AA11.
  • the display panel is suitable for a display panel with a camera installed under the screen.
  • the auxiliary display area AA2 corresponds to the installation of camera components, and the normal display area AA12 is used for screen display. Since the transition area AA11 and the sub-display area AA2 also need to display images, the sub-display area AA2 also needs to allow light to pass through to the camera on the non-display side. The camera can work using the light transmitted to the non-display side.
  • the pixel elements eg, thin film transistors, light-emitting devices 20 and other elements
  • the sub-display area AA2 block the camera, so only the transparent light-emitting device 20 is provided in the sub-display area AA2 without the pixel circuit 10 . It should be understood that in the following description, the light-emitting devices 20 in the sub-display area AA2 refer to the transparent light-emitting devices 20 .
  • the area of the orthogonal projection of the light-emitting device 20 of the sub-display area AA2 on the base substrate 11 can be set to be smaller than the area of the light-emitting device 20 of the transition area AA11 on the base substrate 11
  • the area of the orthographic projection of the light-emitting device 20 in the sub-display area AA2 on the base substrate 11 may be the area of the orthographic projection of the light-emitting device 20 of the transition area AA11 on the base substrate 11 .
  • the light-emitting device 20 provided in the sub-display area AA2 needs to be driven by the pixel circuit 10 to emit light. Therefore, multiple pixel circuits 10 are provided in the transition area AA11.
  • the pixel circuits 10 in the transition area AA11 and the light-emitting devices in the sub-display area AA2 20 Connect via connecting wires.
  • a small box in the figure represents a pixel area.
  • the display panel includes a plurality of pixel areas arranged in an array, including the pixel area of the normal display area AA12, the pixel area of the transition area AA11 and the pixels of the sub-display area AA2.
  • the layout of the zones is consistent.
  • a plurality of sub-pixels PX capable of normal display are arranged in an array, and one sub-pixel PX is provided in one pixel area.
  • One sub-pixel PX or pixel circuit 10 is provided in one pixel area; two sub-pixels PX and one pixel circuit 10 can be Arranged as a group, the pixel circuit 10 is disposed between two sub-pixels PX.
  • a plurality of light-emitting devices 20 are arranged in an array in the sub-display area AA2, and one light-emitting device 20 is provided in one pixel area.
  • the subpixel PX includes a pixel circuit 10 and a light emitting device 20 .
  • first direction X is a row
  • second direction Y is a column
  • the pixel circuit 10 in the transition area AA11 is connected to the light-emitting device 20 in the sub-display area AA2 of the same row, which avoids more intersections in the connection wires between the pixel circuit 10 and the light-emitting device 20 and affects the layout of the connection wires, and is easy to produce signal interference.
  • the transition area AA11 is provided with a plurality of pixel circuits 10, the pixel density of the transition area AA11 is smaller than the pixel density of the normal display area AA12; and the pixel density of the transition area AA11 can be the same as the pixel density of the secondary display area AA2; of course, it is also It may be that the pixel density of the transition area AA11 is greater than the pixel density of the sub-display area AA2.
  • cameras can be installed in the secondary display area AA2, but also other photosensitive sensors such as infrared sensing devices and fingerprint sensors can be installed.
  • the pixel circuit 10 at least includes a switching transistor and a driving transistor, and of course may also include a threshold compensation transistor, a storage capacitor, and other structures. Referring to FIG. 6 , an exemplary pixel circuit 10 is shown.
  • the pixel circuit 10 may specifically include: a storage capacitor C1, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7.
  • the first terminal of the first transistor T1 is connected to the data line DATA, the second terminal of the first transistor T1 is connected to the N1 node, the control terminal of the first transistor T1 is connected to the scan line Gate; the first terminal of the second transistor T2 is connected to N1 node, the second terminal of the second transistor T2 is connected to the N3 node, the control terminal of the second transistor T2 is connected to the N2 node; the first terminal of the third transistor T3 is connected to the N3 node, and the second terminal of the third transistor T3 is connected to N2 node, the control terminal of the third transistor T3 is connected to the scan line Gate; the first terminal of the fourth transistor T4 is connected to the N2 node, the second terminal of the fourth transistor T4 is connected to (initialization voltage line) Vint1, the fourth transistor T4 The control terminal of is connected to the first reset line Reset1; the first terminal of the fifth transistor T5 is connected to the power line VDD, the second terminal of the fifth transistor T5 is connected to the N1 no
  • the first pole of the storage capacitor C1 is connected to the power line VDD, and the second pole of the storage capacitor C1 is connected to the N2 node.
  • the first electrode 21 of the light-emitting device 20 is connected to the N4 node, and the second electrode 24 of the light-emitting device 20 is connected to the second power line VSS.
  • the transistor used above can be a thin film transistor, a field effect transistor, or other devices with the same characteristics. Since the source electrode 181 and the drain electrode 182 of the transistor used are symmetrical, the source electrode 181 and the drain electrode 182 are not difference. In the embodiment of the present disclosure, to distinguish the transistor, the source 181 is called the first terminal, the drain 182 is called the second terminal, and the gate 16 is called the control terminal. In addition, transistors can be divided into N-type and P-type according to their characteristics.
  • the first terminal is the source 181 of the P-type transistor
  • the second terminal is the drain 182 of the P-type transistor
  • the gate When 16 inputs a low level, the source and drain 182 are turned on;
  • the first terminal is the source 181 of the N-type transistor
  • the second terminal is the drain 182 of the N-type transistor
  • the gate 16 inputs a high voltage.
  • the source and drain 182 are conductive.
  • the display panel may include a driving backplane 100 and a light emitting substrate 200.
  • the driving backplane 100 The light-emitting substrate 200 may include multiple pixel circuits 10 arranged in an array.
  • the light-emitting substrate 200 may include multiple light-emitting devices 20 arranged in an array.
  • the pixel circuit 10 may drive the light-emitting devices 20 to emit light.
  • the driving backplane 100 may include a base substrate 11, and the material of the base substrate 11 may include an inorganic material.
  • the inorganic material may be glass, quartz or metal.
  • the material of the base substrate 11 may also include organic materials.
  • the organic materials may be polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, or polyethylene terephthalate. Resin materials such as ester and polyethylene naphthalate.
  • the base substrate 11 may be formed of multiple material layers.
  • the base substrate 11 may include multiple base layers, and the material of the base layer may be any of the above-mentioned materials.
  • the base substrate 11 can also be provided as a single layer, and can be made of any of the above materials.
  • a light-shielding layer 12 may also be provided on one side of the base substrate 11.
  • the light incident from the base substrate 11 into the active layer 14 will generate photogenerated carriers in the active layer 14, thereby having a huge impact on the characteristics of the thin film transistor. , ultimately affecting the display quality of the display device; the light rays incident from the base substrate 11 can be blocked by the light-shielding layer 12 , thereby avoiding any impact on the characteristics of the thin film transistor and the display quality of the display device.
  • a buffer layer 13 can also be formed on the side of the light-shielding layer 12 away from the base substrate 11.
  • the buffer layer 13 serves to block water vapor and impurity ions in the base substrate 11 (especially organic materials), and serves as a buffer for subsequent formation.
  • the active layer 14 increases the effect of hydrogen ions, and the buffer layer 13 is made of an insulating material, which can insulate and isolate the light-shielding layer 12 from the active layer 14 .
  • An active layer 14 is provided on a side of the buffer layer 13 away from the base substrate 11 .
  • the active layer 14 may include a channel part and conductor parts provided at both ends of the channel part.
  • the active layer 14 is on a side far away from the base substrate 11
  • a gate insulating layer 15 is provided on one side of the gate insulating layer 15, a gate electrode 16 is provided on one side of the gate electrode 16, and an interlayer dielectric layer 17 is provided on the side of the gate electrode 16 away from the base substrate 11.
  • a first via hole is provided on the electrical layer 17, and the first via hole is connected to the conductor part; a source electrode 181 and a drain electrode 182 are provided on the side of the interlayer dielectric layer 17 away from the base substrate 11, and the source electrode 181 and the drain electrode 182 are provided on the side of the interlayer dielectric layer 17 away from the base substrate 11.
  • the drain electrode 182 is connected to the two conductor parts through two first via holes respectively.
  • a passivation layer 19 is provided on the side of the source electrode 181 and the drain electrode 182 away from the base substrate 11 .
  • a second via hole is provided on the passivation layer 19 , and the second via hole is connected to the source electrode 181 .
  • the active layer 14, the gate electrode 16, the source electrode 181 and the drain electrode 182 form a thin film transistor.
  • the thin film transistor described in this specification is a top-gate thin film transistor.
  • the thin film transistor may also be a bottom-gate type or a double-gate type, and the specific structure thereof will not be discussed here. Repeat.
  • the functions of the "source electrode 181" and the “drain electrode 182" may be interchanged with each other. Therefore, in this specification, “source electrode 181” and “drain electrode 182" may be interchanged with each other.
  • the driving backplane 100 in the sub-display area AA2 may include the base substrate 11, the buffer layer 13, the gate insulating layer 15, the interlayer dielectric layer 17 and the Passivation layer 19 and so on.
  • the structure of the driving backplane 100 in the normal display area AA12 and in the transition area AA11 may be the same.
  • a first conductive layer 41 is provided on the side of the passivation layer 19 facing away from the base substrate 11 , and a first conductive layer 41 is provided on the side of the first conductive layer 41 facing away from the base substrate 11 .
  • the first insulating layer 42 has a second conductive layer 43 disposed on a side of the first insulating layer 42 facing away from the base substrate 11 .
  • the first conductive layer 41 may include a first connection wire 31 , and the first connection wire 31 may extend from the transition area AA11 to the secondary display area AA2 ; specifically, one end of the first connection wire 31 passes through the passivation layer
  • the second via hole provided on 19 is connected to the source electrode 181; the other end of the first connection wire 31 is connected to the first electrode 21 of the light emitting device 20.
  • the first conductive layer 41 may be a transparent conductive layer, that is, the material of the first conductive layer 41 may be ITO (Indium Tin Txide), IZO (Indium Zinc Oxide), or the like.
  • most of the first connection wires 31 may be disposed in the secondary display area AA2, with only a small part extending to the transition area AA11; and the source electrode 181 of the thin film transistor in the transition area AA11 extends to the secondary display area AA11.
  • a first supplementary connection wire is extended from one side of the display area AA2, and the first supplementary connection wire extends to the edge of the transition area AA11. Then, the first connection wire 31 is connected to the first supplementary connection wire through a second via hole provided on the passivation layer 19.
  • connection wires are arranged so that the connection wires connecting the light-emitting device 20 and the thin film transistor located in a part of the sub-display area AA2 (the first connection wires 31) are made of transparent conductive material, and the part of the connection wires located in the transition area AA11 (the first supplementary connection wires) It is made of metal material, which can reduce the resistance of the connecting wire and improve the display brightness.
  • the second conductive layer 43 may include a second connection wire 32 , and the second connection wire 32 may extend from the transition area AA11 to the secondary display area AA2 ; specifically, one end of the second connection wire 32 passes through the passivation layer
  • the second via hole provided on 19 and the third via hole provided on the first insulating layer 42 are connected to the source electrode 181 ; the other end of the second connection wire 32 is connected to the first electrode 21 of the light emitting device 20 .
  • the second conductive layer 43 may be a transparent conductive layer, that is, the material of the second conductive layer 43 may be ITO (Indium Tin Txide), IZO (Indium Zinc Oxide), or the like.
  • connection wire may extend from the transition area AA11 to the secondary display area AA2 to connect the pixel circuit 10 and the light emitting device 20 .
  • the source and drain layers are arranged in two layers, that is, the above-mentioned source and drain layers are the first source and drain layers
  • a portion of the passivation layer 19 facing away from the base substrate 11 A second source-drain layer is also provided on the side of The hole is connected to the source 181 and the second supplementary connection wire extends to the edge of the transition area AA11.
  • An insulating layer is provided on the side of the second source and drain layer 182 facing away from the base substrate 11 , and the first conductive layer 41 , the first insulating layer 42 , and the second conductive layer are sequentially provided on the side of the insulating layer facing away from the base substrate 11 43.
  • the second connection wire 32 may be provided in the secondary display area AA2, and only a small part extends to the transition area AA11; the second connection wire 32 is connected to the second supplementary connection wire through the fourth via hole provided on the insulating layer, so It is arranged so that a part of the connection wire connecting the light-emitting device 20 and the thin film transistor located in the sub-display area AA2 (the second connection wire 32) is made of a transparent conductive material, and a part (the second supplementary connection wire) located in the transition area AA11 is made of a metal material, This can reduce the resistance of the connecting wire and improve the display brightness.
  • the first connection wire 31 is closer to the conductive layer of the pixel circuit 10 than the second connection wire 32 , the first connection wire 31 and the conductor layer in the pixel circuit 10 form a capacitance, so that the unit area capacitance of the first connection wire 31 is greater than the unit area capacitance of the second connection wire 32. Therefore, the capacitance gap between the first connection wire 31 and the second connection wire 32 connected to the same row of light-emitting devices 20 is large and cannot form a linear shape. This will occur even if algorithm compensation is performed subsequently. Brightness difference.
  • a second compensation part 332 may be provided on the second conductive layer 43 , and the second compensation part 332 may be provided in a patterned manner.
  • the second compensation part 332 may be provided in the transition area AA11. Since the second connecting wire 32 is led out from the pixel circuit 10 and then bent into the gap between two adjacent rows of pixel circuits 10 and extends along the gap, the second compensation part 332 is set in a rectangular structure, so that the second Both sides of the compensation portion 332 are connected to the second connection wire 32 , that is, one end of the second connection wire 32 close to the pixel circuit 10 is patterned.
  • the second compensation part 332 can increase the capacitance of the second connection wire 32 so that the difference between the capacitance of the second connection wire 32 and the first connection wire 31 is reduced, thereby reducing the brightness difference of the light emitting device 20 .
  • the second compensation part 332 can also be configured as various polygons or graphics with arcuate sides.
  • a red light-emitting device is taken as an example to indicate the first light-emitting device 201, the second light-emitting device 202, the first pixel circuit 1001 and the second pixel circuit 1002; a plurality of first connecting wires 31 are marked one by one.
  • the first direction X is the direction from the secondary display area AA2 to the main display area AA1. It should be noted that the direction from the main display area AA1 to the secondary display area AA2 is also the first direction X. Specifically, the first direction X is a row. It can also be said that the first direction X is a row direction.
  • the capacitances of the plurality of first connection wires 31 and the plurality of second connection wires 32 connecting the plurality of first light-emitting devices 201 and the plurality of second light-emitting devices 202 in the same row are The capacitance increases or decreases linearly.
  • L3 in the figure is a curve formed by compensating the capacitances of the plurality of second connection wires 32 .
  • L3 and L2 in the figure basically form a straight line.
  • the capacitance of the second connection wires 32 is calculated through the compensation part 33 .
  • the requirements that need to be met for compensation are: the capacitance and the capacitance of the plurality of first connection wires 31 connecting the plurality of first light-emitting devices 201 and the plurality of second light-emitting devices 202 in the same row in the direction from the secondary display area AA2 to the main display area AA1.
  • the capacitance of the second connecting wires 32 increases or decreases linearly, and the difference in capacitance between two adjacent first connecting wires 31 is basically the same.
  • the difference in capacitance is basically the same, and the difference in capacitance between the adjacent first connecting wire 31 and the second connecting wire 32 is basically the same.
  • the area size of the second compensation portion 332 connected to each second connecting wire 32 can be set according to the above requirements.
  • a first compensation part 331 may also be provided on the first conductive layer 41 , and the first compensation part 331 may include a first part 3311 and a second part 3312 .
  • the second part 3312 is connected to the first part 3311, the first part 3311 extends along the second direction Y, the second part 3312 extends along the first direction X, and the connection between the second part 3312 and the first part 3311 forms a corner.
  • the first part 3311 is connected to the second connection wire 32 .
  • the first part 3311 can be connected to the source 181 through the fifth via hole on the passivation layer 19 , so that the second connection wire 32 and the first part 3311 are connected through the source 181 Connection; the first part 3311 and the second connection wire 32 are connected to the source 181 through different via holes. Therefore, the orthographic projection of the first part 3311 on the substrate 11 is the same as the orthogonal projection of the second connection wire 32 on the substrate 11 . Projections have no overlap.
  • the first part 3311 may be connected to the source 181 first, and the second connection wire 32 is then connected to the first part 3311. In this case, the first part 3311 is on the substrate 11
  • the orthographic projection and the orthographic projection of the second connection conductor 32 on the base substrate 11 may overlap.
  • the plurality of second connection wires 32 between two adjacent rows of pixel circuits 10 all need compensation, and since the length of the second part 3312 in the first direction X is shorter than the length of the second connection wires 32 in the first direction X,
  • the orthographic projection of the second part 3312 on the base substrate 11 is located within the orthographic projection of the second connecting wire 32 on the base substrate 11. That is, the second part 3312 and the second connecting wire 32 are overlapped to facilitate accommodating multiple third connection wires.
  • a capacitance can also be formed between the first compensation part 331 and the second connection wire 32 to further increase the capacitance of the second connection wire 32.
  • first compensation part 331 and the second compensation part 332 may be provided at the same time, or only the first compensation part 331 may be provided, or only the second compensation part 332 may be provided.
  • a fourth compensation part may also be provided on the first conductive layer 41 , and the fourth compensation part may be patterned.
  • the fourth compensation part may be provided in the transition area AA11. Since the first compensation part 331 is led out from the pixel circuit 10 and then bent into the gap between two adjacent rows of pixel circuits 10 and extends along the gap, the fourth compensation part 331 is set in a rectangular structure, so that the fourth compensation part Both sides of the edge of the first compensation part 331 are connected to the first compensation part 331 , that is, one end of the first compensation part 331 close to the pixel circuit 10 is patterned.
  • the fourth compensation part 33 can increase the capacitance of the second connection wire 32 so that the difference between the capacitance of the second connection wire 32 and the first connection wire 31 is reduced, thereby reducing the brightness difference of the light emitting device 20 .
  • the display panel may further include a second insulating layer 44 and a third conductive layer 45 ; specifically, the second insulating layer 44 is provided on a side of the second conductive layer 43 away from the base substrate 11 ;
  • the layer 45 is provided on a side of the second insulating layer 44 facing away from the base substrate 11 .
  • the third conductive layer 45 may include a second connection wire 32
  • the second conductive layer 43 may include a first connection wire 31
  • the compensation part 33 is provided on the first conductive layer 41 and/or the second conductive layer 43 and/or the third conductive layer 43 .
  • the third conductive layer 45 may be a transparent conductive layer, that is, the material of the third conductive layer 45 may be ITO (Indium Tin Txide), IZO (Indium Zinc Oxide), etc.
  • the first conductive layer 41 , the second conductive layer 43 and the third conductive layer 45 may be provided. Connection wires connecting the pixel circuit 10 and the light-emitting device 20 can be provided on the first conductive layer 41, the second conductive layer 43 and the third conductive layer 45, so that when two adjacent rows of the light-emitting devices 20 have the same gap, A larger number of connecting wires are accommodated to meet the purpose of having a larger area of the sub-display area AA2 and a larger number of light-emitting devices 20 installed therein.
  • the first conductive layer 41 is closer to the conductive layer of the pixel circuit 10 than the second conductive layer 43, the first conductive layer 41 and the conductor layer in the pixel circuit 10 form a capacitance, so that the capacitance per unit area of the first conductive layer 41 is larger.
  • the second conductive layer 43 can form a capacitor with the first conductive layer 41 and the third conductive layer 45, so that the capacitance per unit area of the second conductive layer 43 is relatively large; but the third conductive layer 45 can only be connected with the second conductive layer 45.
  • the layer 43 forms a capacitor such that the capacitance per unit area of the third conductive layer 45 is smaller than the capacitance per unit area of the first conductive layer 41 and the second conductive layer 43 .
  • the unit area capacitance of the first connection wire 31 is is greater than the unit area capacitance of the second connection wire 32. Therefore, the capacitance gap between the first connection wire 31 and the second connection wire 32 connected to the same row of light-emitting devices 20 is large and cannot form a linear shape. This will occur even if algorithm compensation is performed subsequently. Brightness difference.
  • the first compensation part 331 can be provided on the first conductive layer 41 , and the first compensation part 331 can include a first part 3311 and a second part 3312 .
  • the second part 3312 is connected to the first part 3311, the first part 3311 extends along the second direction Y, the second part 3312 extends along the first direction X, and the connection between the second part 3312 and the first part 3311 forms a corner.
  • the first part 3311 is connected to the second connection wire 32 .
  • the first part 3311 can be connected to the source 181 through the fifth via hole on the passivation layer 19 , so that the second connection wire 32 and the first part 3311 are connected through the source 181 Connection; the first part 3311 and the second connection wire 32 are connected to the source 181 through different via holes. Therefore, the orthographic projection of the first part 3311 on the substrate 11 is the same as the orthogonal projection of the second connection wire 32 on the substrate 11 . Projections have no overlap.
  • the first part 3311 may be connected to the source 181 first, and the second connection wire 32 is then connected to the first part 3311. In this case, the first part 3311 is on the substrate 11
  • the orthographic projection and the orthographic projection of the second connection conductor 32 on the base substrate 11 may overlap.
  • the plurality of second connection wires 32 between two adjacent rows of pixel circuits 10 all need compensation, and since the length of the second part 3312 in the first direction X is shorter than the length of the second connection wires 32 in the first direction X,
  • the orthographic projection of the second part 3312 on the base substrate 11 is located within the orthographic projection of the second connecting wire 32 on the base substrate 11. That is, the second part 3312 and the second connecting wire 32 are overlapped to facilitate accommodating multiple third connection wires.
  • a capacitance can also be formed between the first compensation part 331 and the second connection wire 32 to further increase the capacitance of the second connection wire 32.
  • a second compensation part 332 may be provided on the second conductive layer 43 , and the second compensation part 332 may include a third part 3321 and a fourth part. 3322.
  • the fourth part 3322 is connected to the third part 3321, the third part 3321 extends along the second direction Y, the fourth part 3322 extends along the first direction X, and the connection between the fourth part 3322 and the third part 3321 forms a corner.
  • the third part 3321 is connected to the second connection wire 32.
  • the third part 3321 can be connected to the source electrode 181 through the passivation layer 19 and the via hole on the first insulating layer 42, thereby connecting the second connection wire 332 through the source electrode 181.
  • the wire 32 is connected to the third part 3321; the third part 3321 and the second connection wire 32 are connected to the source 181 through different via holes. Therefore, the orthographic projection of the third part 3321 on the base substrate 11 is different from that of the second connection wire 32.
  • the orthographic projection of 32 on the base substrate 11 has no overlap.
  • the third part 3321 may be connected to the source 181 first, and the second connecting wire 32 is then connected to the third part 3321. In this case, the third part 3321 is connected to the base substrate.
  • the orthographic projection on 11 and the orthographic projection of the second connecting wire 32 on the base substrate 11 may overlap.
  • the plurality of second connection wires 32 between two adjacent rows of pixel circuits 10 all need compensation, and since the length of the fourth part 3322 in the first direction X is shorter than the length of the second connection wires 32 in the first direction X,
  • the orthographic projection of the fourth part 3322 on the base substrate 11 is located within the orthographic projection of the second connecting wire 32 on the base substrate 11 , that is, the fourth part 3322 and the second connecting wire 32 are overlapped to facilitate accommodating multiple third connection wires 32 .
  • the second compensation part 332 also facilitates calculation during design.
  • a capacitance can also be formed between the second compensation part 332 and the second connection wire 32 to further increase the capacitance of the second connection wire 32 .
  • the third compensation part 333 may be provided on the third conductive layer 45 , and the third compensation part 333 may be provided graphically.
  • the third compensation part 333 may be provided in the transition area AA11. Since the second connecting wire 32 is led out from the pixel circuit 10 and then bent into the gap between two adjacent rows of pixel circuits 10 and extends along the gap, the third compensation part 333 is set in a rectangular structure, so that the third compensation part 333 is arranged in a rectangular structure. Both sides of the compensation portion 333 are connected to the second connection wire 32 , that is, one end of the second connection wire 32 close to the pixel circuit 10 is patterned.
  • the third compensation part 333 can increase the capacitance of the second connection wire 32 so that the difference between the capacitance of the second connection wire 32 and the first connection wire 31 is reduced, thereby reducing the brightness difference of the light emitting device 20 .
  • the third compensation part 333 can also be configured as various polygons or graphics with arcuate sides.
  • the plurality of first connection wires 31 and the plurality of second connection wires 32 are connected to the plurality of light-emitting devices 20 arranged along the first direction X in a one-to-one correspondence.
  • the plurality of light-emitting devices 20 are arranged serially along the first direction
  • the arrangement numbers of one connection wire 31 and the plurality of second connection wires 32 are the same as the arrangement numbers of the plurality of light-emitting devices 20 connected thereto.
  • L3 in the figure is the capacitance curve after compensation for the plurality of second connection wires 32 .
  • L3 and L1 in the figure basically form a straight line.
  • the compensation part 33 needs to compensate the capacitance of the second connection wires 32 to achieve The requirement is: the capacitance of the plurality of first connection wires 31 and the capacitance of the plurality of second connection wires 32 are linear according to the arrangement sequence.
  • the capacitance of the plurality of first connection wires 31 and the capacitance of the plurality of second connection wires 32 It increases or decreases sequentially according to the arrangement number, and the difference in capacitance between two adjacent first connecting wires 31 is the same, and the difference in capacitance between two adjacent second connecting wires 32 is the same. , the difference in capacitance between the adjacent first connecting wires 31 and the second connecting wires 32 is the same.
  • the area size of the third compensation part 333 connected to each second connection wire 32, the area size of the first compensation part 331, and the area size of the second compensation part 332 can be set according to the above needs.
  • first compensation part 331, the second compensation part 332 and the third compensation part 333 can be provided at the same time. Only the first compensation part 331 may be provided, only the second compensation part 332 may be provided, or only the third compensation part 333 may be provided. Two of the first compensation part 331, the second compensation part 332 and the third compensation part 333 may also be provided, and may be determined according to the capacitance that actually needs to be compensated.
  • a fourth compensation part may also be provided on the first conductive layer 41 , and the fourth compensation part may be patterned.
  • the fourth compensation part may be provided in the transition area AA11. Since the first compensation part 331 is led out from the pixel circuit 10 and then bent into the gap between two adjacent rows of pixel circuits 10 and extends along the gap, the fourth compensation part 331 is set in a rectangular structure, so that the fourth compensation part Both sides of the edge of the first compensation part 331 are connected to the first compensation part 331 , that is, one end of the first compensation part 331 close to the pixel circuit 10 is patterned.
  • the fourth compensation part can increase the capacitance of the second connection wire 32 so that the difference between the capacitance of the second connection wire 32 and the capacitance of the first connection wire 31 is reduced, thereby reducing the brightness difference of the light emitting device 20 .
  • a fifth compensation part may be provided on the second conductive layer 43 , and the fifth compensation part may be provided in a pattern.
  • the fifth compensation part may be provided in the transition area AA11. Since the first compensation part 331 is led out from the pixel circuit 10 and then bent into the gap between two adjacent rows of pixel circuits 10 and extends along the gap, the fifth compensation part 331 is set in a rectangular structure, so that the fifth compensation part Both sides of the edge of the first compensation part 331 are connected to the first compensation part 331 , that is, one end of the first compensation part 331 close to the pixel circuit 10 is patterned.
  • the fifth compensation part can increase the capacitance of the second connection wire 32 so that the difference between the capacitance of the second connection wire 32 and the first connection wire 31 is reduced, thereby reducing the brightness difference of the light emitting device 20 .
  • the fourth compensation part and the fifth compensation part may also be configured as various polygons or graphics with arcuate sides.
  • FIG. 3 different line types are used to indicate that the connecting wires are arranged on different conductive layers, and the figure shows the connection relationship between half of the row of light-emitting devices 20 in the sub-display area AA2 and the pixel circuit 10 because,
  • the sub-display area AA2 is generally arranged symmetrically, and the transition area AA11 is also arranged symmetrically.
  • the light-emitting device 20 on the left half of the sub-display area AA2 is connected to the pixel circuit 10 on the corresponding side
  • the light-emitting device 20 on the right half of the sub-display area AA2 is connected to the pixel circuit 10 on the corresponding side.
  • 20 is connected to the pixel circuit 10 on the corresponding side.
  • the pixel circuit connected to the green light-emitting device G is marked G'
  • the pixel circuit connected to the red light-emitting device R is marked R'
  • the pixel circuit connected to the blue light-emitting device B is marked B'.
  • multiple pixel circuits 10 in the same row may include a first group of pixel circuits 101, a second group of pixel circuits 102, and a third group of pixel circuits 103.
  • the first group of pixel circuits 101, the second group of pixel circuits 102 and the third group of pixel circuits 103 are arranged in sequence away from the sub-display area AA2.
  • the first group of pixel circuits 101 are arranged close to the sub-display area AA2, and fourteen pixel circuits 10 of the first group of pixel circuits 101 can be arranged;
  • Two groups of pixel circuits 102 are provided on the side of the first group of pixel circuits 101 away from the sub-display area AA2.
  • pixel circuits 10 of the second group of pixel circuits 102 can be provided; and a third group of pixel circuits 103 are provided on the second group. On the side of the pixel circuit 102 away from the secondary display area AA2, thirteen pixel circuits 10 of the third group of pixel circuits 103 may be provided. The number of pixel circuits 10 included in each of the first group of pixel circuits 101, the second group of pixel circuits 102, and the third group of pixel circuits 103 can be set as needed.
  • the first group of pixel circuits 101 is connected to the light-emitting device 20 through the first conductive layer 41
  • the second group of pixel circuits 102 is connected to the light-emitting device 20 through the second conductive layer 43
  • the third group of pixel circuits 103 is connected through the third conductive layer 45 Connected to the light emitting device 20 .
  • the first conductive layer 41 may include fourteen third connection wires 34, and the fourteen third connection wires 34 are correspondingly connected to the fourteen pixel circuits 10 and the fourteen light-emitting devices 20 of the first group of pixel circuits 101.
  • the fourteen light-emitting devices 20 may all be green light-emitting devices G; the thirteen first connection wires 31 are correspondingly connected to one of the thirteen pixel circuits 10 and the thirteen light-emitting devices 20 of the second group of pixel circuits 102 During the period, six of the thirteen light-emitting devices 20 can be green light-emitting devices G, three of them can be blue light-emitting devices B, and four of them can be red light-emitting devices R; a plurality of second connection wires 32 are connected correspondingly.
  • seven of the thirteen light-emitting devices 20 may be blue light-emitting devices B, and six of them may be red light-emitting devices R. .
  • the third connecting wire 34 only occupies a part of the transition area AA11 close to the auxiliary display area AA2 , and a part of the transition area AA11 close to the normal display area AA12 is not occupied. Therefore,
  • the first compensation part 331 can be provided in a part of the transition area AA11 close to the normal display area AA12, so that the first compensation part 331 is spaced apart from the third connection wire 34, and the first compensation part 331 is located away from the third connection wire 34 in the secondary display area.
  • the third connecting wire 34 and the first compensation part 331 belong to the first conductive layer 41, thereby preventing the first compensation part 331 from affecting the arrangement and electrical performance of the third connecting wire 34. Moreover, one end of the plurality of first compensation parts 331 close to the secondary display area AA2 may be flush.
  • the second part 3312 of the first compensation part 331 may include a first compensation segment 3312a and a first dummy segment 3312b; the first compensation The section 3312a is connected to the second connecting wire 32, that is, the first compensation section 3312a is connected to the first part 3311, and is connected to the second connecting wire 32 through the first part 3311; the first dummy section 3312b is spaced apart from the first compensation section 3312a, and is located at The first compensation section 3312a is close to the side of the secondary display area AA2; the first compensation section 3312a has a capacitance compensation effect on the second connection wire 32, and the first dummy section 3312b has no capacitance compensation effect on the second connection wire 32, just for Maintain etching uniformity.
  • the orthogonal projection areas of the plurality of first compensation segments 3312a on the base substrate 11 are the same, that is, the plurality of first compensation segments 3312a have the same length in the first direction X and the same width in the second direction Y. Therefore, the capacitances compensated by the plurality of first compensation sections 3312a for the plurality of second connection wires 32 are the same.
  • the plurality of first compensation portions 331 can also be set to the same length, so that the plurality of first compensation portions 331 have the same capacitance corresponding to the compensation of the plurality of second connection wires 32, so that the plurality of first compensation portions 331 are close to each other.
  • One end of the secondary display area AA2 may not be flush.
  • the first connecting wire 31 only occupies a part of the transition area AA11 close to the auxiliary display area AA2 , and a part of the transition area AA11 close to the normal display area AA12 is not occupied. Therefore,
  • the second compensation part 332 can be provided in a part of the transition area AA11 close to the normal display area AA12, so that the second compensation part 332 is spaced apart from the first connection wire 31, and the second compensation part 332 is located away from the first connection wire 31 in the secondary display area.
  • the first connection wire 31 and the second compensation part 332 belong to the second conductive layer 42, thereby preventing the second compensation part 332 from affecting the arrangement and electrical performance of the first connection wire 31.
  • the fourth part 3322 of the second compensation part 332 may include a second compensation segment 3322a and a second dummy segment 3322b; the second compensation The section 3322a is connected to the second connecting wire 32, that is, the second compensation section 3322a is connected to the third part 3321, and is connected to the second connecting wire 32 through the third part 3321; the second dummy section 3322b is spaced apart from the second compensation section 3322a, And is located on the side of the second compensation section 3322a close to the secondary display area; the second compensation section 3322a has a capacitance compensation effect on the second connection wire 32, and the second dummy section 3322b has no capacitance compensation effect on the second connection wire 32.
  • the orthogonal projection areas of the plurality of second compensation segments 3322a on the base substrate 11 are the same, that is, the plurality of second compensation segments 3322a have the same length in the first direction X and the same width in the second direction Y. Therefore, the capacitances compensated by the plurality of second compensation sections 3322a for the plurality of second connection wires 32 are the same.
  • the plurality of second compensation portions 332 can also be set to the same length, so that the plurality of second compensation portions 332 have the same capacitance corresponding to the compensation of the plurality of second connection wires 32, so that the plurality of second compensation portions 332 are close to each other.
  • One end of the secondary display area AA2 may not be flush.
  • the compensation part 33 may be provided in the sub-display area AA2.
  • the plurality of light-emitting devices 20 in the same row of the sub-display area AA2 may be arranged according to the distance from the transition area AA11.
  • each group is connected to the pixel circuit 10 in the transition area AA11 through a connecting wire in a conductive layer, so that the connecting wire does not occupy the secondary display area AA2, and compensation can be set on a part of the conductive layer where the connecting wire is not provided That is to say, the connection method of the light-emitting device 20 in the sub-display area AA2 is the same as the connection method of the pixel circuit 10 in the above-mentioned transition area AA11.
  • multiple light-emitting devices 20 in the same row may include multiple green light-emitting devices G, multiple red light-emitting devices R, and multiple blue light-emitting devices B, and their arrangement may be is BGRG; a plurality of green light-emitting devices G corresponds to a plurality of pixel circuits 10 connected to the same row close to the sub-display area AA2 in sequence; that is, a plurality of green light-emitting devices G corresponds to a plurality of pixel circuits connected to the first group of pixel circuits 101 in sequence 10 and the second group of pixel circuits 102 are close to the plurality of pixel circuits 10 in the sub-display area AA2.
  • a plurality of red light-emitting devices R and a plurality of blue light-emitting devices B alternately correspond to a plurality of pixel circuits 10 connected to the same row away from the sub-display area AA2, that is, a plurality of red light-emitting devices R and a plurality of blue light-emitting devices B, Alternately corresponding to the plurality of pixel circuits 10 connected to the third group of pixel circuits 103 and the plurality of pixel circuits 10 of the second group of pixel circuits 102 away from the sub-display area AA2.
  • Such an arrangement makes the length of the connecting wire connecting the green light-emitting device G and the pixel circuit 10 shorter, which can be called a green-first connection method; since the luminescent material of the green light-emitting device G is driven slowly by induction, if the green light-emitting device G G is driven simultaneously with the red light-emitting device R and the blue light-emitting device B.
  • the green light-emitting device G will lag behind the light-emitting speed of the red light-emitting device R and the blue light-emitting device B, causing the entire display panel to glow purple; connect the green light-emitting device G
  • the length of the connecting wire with the pixel circuit 10 is designed to be short, so that the green light-emitting device G can be driven in advance, so that the green light-emitting device G, the red light-emitting device R and the blue light-emitting device B emit light almost simultaneously, thereby making the display panel normal.
  • the display will not turn purple overall.
  • the display panel may further include a fourth connection wire 5 connected between the light-emitting device 20 closest to the main display area AA1 and the pixel circuit 10 closest to the secondary display area AA2.
  • the connection wires 5 are provided on the source and drain layers of the pixel circuit 10 . That is to say, when the pixel density of the sub-display area AA2 is relatively high and there are many connection wires, the source electrode 181 of the pixel circuit 10 closest to the sub-display area AA2 can be extended to the sub-display area AA2 to form a fourth connection wire. 5.
  • the first electrode 21 of the light-emitting device 20 closest to the main display area AA1 can be connected to the fourth connection wire 5 through the via hole on each insulating layer.
  • the fourth connection wire 5 connects the light-emitting device 20 closest to the main display area AA1 and the pixel circuit 10 closest to the sub-display area AA2, the length of the fourth connection wire 5 extending into the sub-display area AA2 is very short. Therefore, the light transmission effect of the secondary display area AA2 will not be affected, and the shaping effect of the camera will not be affected.
  • the light emitting device 20 may include a first electrode 21 , a pixel definition layer 22 , a light emitting layer group 23 and a second electrode 24 .
  • the first electrode 21 may be an anode (pixel electrode).
  • the first electrode 21 and the second connection wire 32 can be provided on the same conductive layer, that is, the second conductive layer 43 can include the first electrode 21 and the second connection wire 32 .
  • the first electrode 21 and the second connection wire 32 may be formed as an integrated structure.
  • the connection can be achieved through a via hole on the first insulating layer 42 .
  • the first electrode 21 and the second connection wire 32 may be provided on the same conductive layer, that is, the third conductive layer 45 may include the first electrode 21 and the second connection wire 32 .
  • the first electrode 21 and the second connection wire 32 may be formed as an integrated structure.
  • the connection can be achieved through a via hole on the second insulating layer 44 .
  • the connection can be achieved through a via hole on the first insulating layer 42 and a via hole on the second insulating layer 44.
  • the first electrode 21 and the second connection wire 32 can be provided on different conductive layers.
  • the second insulating layer 44 can be provided on the side of the second conductive layer 43 facing away from the base substrate, and the first electrode 21 can be provided on the side of the second insulating layer 44 facing away from the base substrate;
  • the electrode 21 is connected to the first connection wire 31 and the second connection wire 32 through the via holes on each insulation layer, and the specific connection method will not be described again here.
  • FIG. 14 the second insulating layer 44 can be provided on the side of the second conductive layer 43 facing away from the base substrate, and the first electrode 21 can be provided on the side of the second insulating layer 44 facing away from the base substrate;
  • the electrode 21 is connected to the first connection wire 31 and the second connection wire 32 through the via holes on each insulation layer, and the specific connection method will not be described again here.
  • FIG. 14 the specific connection method will not be described again here.
  • the third insulating layer 46 can be provided on the side of the third conductive layer 45 facing away from the base substrate, and the first electrode 21 can be provided on the side of the third insulating layer 46 facing away from the base substrate;
  • the electrode 21 is connected to the first connection wire 31 , the second connection wire 32 and the third connection wire 34 through the via holes on each insulation layer. The specific connection method will not be described again here.
  • the compensation part 33 may also be provided in the sub-display area AA2.
  • a pixel definition layer 22 is provided on a side of the first electrode 21 away from the base substrate 11 .
  • An opening is provided on the pixel definition layer 22 , and a light-emitting layer group 23 is provided in the opening.
  • a second electrode 24 is provided on a side of the light-emitting layer group 23 away from the base substrate 11 .
  • the second electrode 24 may be a cathode (common electrode), and the second electrode 24 is connected to the ground line VSS.
  • the light-emitting layer group 23 may include a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer and an electron injection layer that are stacked in sequence.
  • the hole injection layer is in contact with the first electrode 21 and the electron injection layer is in contact with the second electrode 24 touch.
  • the light-emitting layer group 23 may only include a hole transport layer, a light-emitting layer and an electron transport layer.
  • the light-emitting layer group 23 may also have other structures, and its specific structure may be set as needed.
  • An encapsulation layer group 25 is provided on the side of the second electrode 24 away from the base substrate 11 .
  • the encapsulation layer group 25 may be provided with multiple layers, and the encapsulation layer group 25 may include an organic layer and an inorganic layer.
  • the encapsulation layer group 25 may include a first inorganic layer, which is disposed on a side of the first inorganic layer away from the base substrate 11
  • the organic layer is disposed on the side of the organic layer away from the base substrate 11 and the second inorganic layer.
  • the materials of the first inorganic layer, the organic layer and the second inorganic layer will not be described again here.
  • the encapsulation layer group 25 may also include more layers or fewer layers.
  • a touch layer group may be provided on a side of the packaging layer group 25 facing away from the base substrate 11 , and the touch function is implemented through the touch layer group.
  • a polarizer is provided on the side of the touch layer group facing away from the base substrate 11
  • a cover plate is provided on the side of the polarizer facing away from the base substrate 11 .
  • the display device may include any of the above-mentioned display panels and photosensitive sensors.
  • the specific structure of the display panel has been described in detail above. Therefore, this No further details will be given.
  • the light-sensitive sensor is disposed on the non-display surface of the display panel, and the orthographic projection of the light-sensitive sensor on the display surface at least partially overlaps with the auxiliary display area.
  • the orthographic projection of the light-sensitive sensor on the display surface can overlap with the auxiliary display area.
  • the light-sensitive sensor The orthographic projection on the display surface can be located within the secondary display area and so on.
  • the specific type of the display device is not particularly limited. Any type of display device commonly used in the field can be used, such as mobile devices such as mobile phones, wearable devices such as watches, VR devices, etc. Those skilled in the art can use the display device according to the The specific use should be selected accordingly and will not be described again here.
  • the display device also includes other necessary components and components, taking a display as an example, such as a casing, a circuit board, a power cord, etc.
  • a display such as a casing, a circuit board, a power cord, etc.
  • Those skilled in the art can determine the configuration of the display device based on the details of the display device. The specific usage requirements will be supplemented accordingly and will not be repeated here.
  • the beneficial effects of the display device provided by the exemplary embodiments of the present invention are the same as the beneficial effects of the display panel provided by the above exemplary embodiments, and will not be described again here.

Abstract

一种显示面板和显示装置，该显示面板具有相邻的主显示区域(AA1)和副显示区域(AA2)，包括多个发光器件(20)、多个像素电路(10)、多根第一连接导线(31)、多根第二连接导线(32)以及多个补偿部(33)；多个发光器件(20)阵列排布于副显示区域(AA2)；多个像素电路(10)阵列排布于主显示区域(AA1)；多根第一连接导线(31)连接于一部分发光器件(20)与一部分像素电路(10)之间；多根第二连接导线(32)连接于另一部分发光器件(20)与另一部分像素电路(10)之间，第二连接导线(32)的单位面积电容小于第一连接导线(31)的单位面积电容；多个补偿部(33)与多根第二连接导线(32)对应连接。该显示面板显示亮度均匀。

Description

显示面板和显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示面板和显示装置。
背景技术
随着消费者对显示屏幕感官追求的不断提高，以及显示面板行业技术的不断进步，为了实现高的屏占比，达到极致的观感体验，将显示面板的一部分设置为具有较高透光率的显示区(副显示区域)，将摄像头设置在副显示区域背面。
但是，目前的透光显示区的发光器件的亮度不均匀。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服上述现有技术的不足，提供一种显示面板和显示装置。
根据本公开的一个方面，提供了一种显示面板，具有相邻的主显示区域和副显示区域，所述显示面板包括：
多个发光器件，阵列排布于所述副显示区域，包括第一发光器件和第二发光器件；
多个像素电路，阵列排布于所述主显示区域，包括第一像素电路和第二像素电路；
多根第一连接导线，连接于所述第一发光器件与所述第二像素电路之间；
多根第二连接导线，连接于所述第二发光器件与所述第二像素电路之间，所述第二连接导线的单位面积电容小于所述第一连接导线的单位面积电容；
多个补偿部，与多根所述第二连接导线对应连接。
在本公开的一种示例性实施例中，所述第一发光器件和所述第二发光器件位于同一行且颜色相同，所述第一发光器件相对于所述第二发光器件更靠近所述主显示区域，所述第一像素电路相对于所述第二像素电路更靠近所述副显示区域，所述第二连接导线设于所述第一连接导线背离所述像素电路的一侧，沿所述副显示区域指向所述主显示区域的方向，连接同一行多个所述第一发光器件和多个所述第二发光器件的多根所述第一连接导线的电容和多根所述第二连接导线的电容呈线性依次增加或减小。
在本公开的一种示例性实施例中，所述第一发光器件和第二发光器件为红色发光器件和/或蓝色发光器件。
在本公开的一种示例性实施例中，所述显示面板还包括：
衬底基板；
第一导电层，设于所述衬底基板的一侧；
第一绝缘层，设于所述第一导电层背离所述衬底基板的一侧；
第二导电层，设于所述第一绝缘层背离所述衬底基板的一侧。
在本公开的一种示例性实施例中，所述第一导电层包括所述第一连接导线，所述第二导电层包括所述第二连接导线，所述补偿部设于所述第一导电层和/或所述第二导电层。
在本公开的一种示例性实施例中，所述补偿部包括第一补偿部、第二补偿部中的一种或两种；所述第一补偿部设于所述第一导电层，所述第二补偿部设于所述第二导电层。
在本公开的一种示例性实施例中，所述第二补偿部图形化设置，所述第二补偿部的部分边沿与所述第二连接导线连接。
在本公开的一种示例性实施例中，所述显示面板还包括：
第二绝缘层，设于所述第二导电层背离所述衬底基板的一侧；
第三导电层，设于所述第二绝缘层背离所述衬底基板的一侧；
其中，所述第三导电层包括所述第二连接导线，所述第二导电层包括所述第一连接导线，所述补偿部设于所述第一导电层和/或所述第二导电层和/或所述第三导电层。
在本公开的一种示例性实施例中，所述补偿部包括设于所述第一导电层的第一补偿部、设于所述第二导电层的第二补偿部或设于所述第三导电层的第三补偿部中的至少一种。
在本公开的一种示例性实施例中，所述第一补偿部包括：
第一部分，连接于所述第二连接导线，所述第一部分在所述衬底基板上的正投影与所述第二连接导线在所述衬底基板上的正投影无交叠；
第二部分，连接于所述第一部分，所述第二部分在所述衬底基板上的正投影位于所述第二连接导线在所述衬底基板上的正投影内。
在本公开的一种示例性实施例中，所述第二补偿部包括：
第三部分，连接于所述第二连接导线，所述第三部分在所述衬底基板上的正投影与所述第二连接导线在所述衬底基板上的正投影无交叠；
第四部分，连接于所述第三部分，所述第四部分在所述衬底基板上的正投影位于所述第二连接导线在所述衬底基板上的正投影内。
在本公开的一种示例性实施例中，所述第三补偿部设置为图形化设置，所述第三补偿部的部分边沿与所述第二连接导线连接。
在本公开的一种示例性实施例中，所述补偿部设于所述主显示区域。
在本公开的一种示例性实施例中，所述主显示区域包括：
正常显示区域；
过渡区域，设于所述副显示区域与所述正常显示区域之间，所述像素电路设于所述过渡区域，所述补偿部设于所述过渡区域。
在本公开的一种示例性实施例中，同一行的多个所述像素电路包括：
第一组像素电路，靠近所述副显示区域设置；
第二组像素电路，设于所述第一组像素电路背离所述副显示区域的一侧；
第三组像素电路，设于所述第二组像素电路背离所述副显示区域的一侧；
其中，所述第一组像素电路通过所述第一导电层与所述发光器件连接，所述第二组像素电路通过所述第二导电层与所述发光器件连接，所述第三组像素电路通过所述第三导电层与所述发光器件连接。
在本公开的一种示例性实施例中，所述显示面板还包括：
多根第三连接导线，设于所述第一导电层，多根所述第三连接导线对应连接于所述第一组像素电路与多个所述发光器件之间，多根所述第一连接导线对应连接于所述第二组像素电路与多个所述发光器件之间，多根所述第二连接导线对应连接于所述第三组像素电路与多个所述发光器件之间。
在本公开的一种示例性实施例中，所述第一补偿部与所述第三连接导线间隔设置，且位于所述第三连接导线远离所述副显示区域的一侧；所述第二补偿部与所述第一连接导线间隔设置，且位于所述第一连接导线远离所述副显示区域的一侧。
在本公开的一种示例性实施例中，多个所述第一补偿部靠近所述副显示区域的一端平齐，多个所述第二补偿部靠近所述副显示区域的一端平齐。
在本公开的一种示例性实施例中，
所述第一补偿部包括：
第一补偿段，连接于所述第二连接导线；
第一虚设段，与所述第一补偿段间隔设置，且位于所述第一补偿段靠近所述副显示区域的一侧；
所述第二补偿部包括：
第二补偿段，连接于所述第二连接导线；
第二虚设段，与所述第二补偿段间隔设置，且位于所述第二补偿段靠近所述副显示区域的一侧；
其中，多个所述第一补偿段在所述衬底基板上的正投影的面积相同，多个所述第二补偿段在所述衬底基板上的正投影的面积相同，多个所述第一虚设段靠近所述副显示区域的一端平齐，多个所述第二虚设段靠近所述副显示区域的一端平齐。
在本公开的一种示例性实施例中，同一行的多个所述发光器件包括：
多个绿色发光器件，依次对应连接于靠近所述副显示区域的同一行的多个所述像素电路；
多个红色发光器件和多个蓝色发光器件，交替对应连接于远离所述副显示区域的同一行的多个所述像素电路。
在本公开的一种示例性实施例中，所述过渡区域的像素密度等于所述副显示区域的像素密度，所述正常显示区域的像素密度大于所述副显示区域的像素密度。
在本公开的一种示例性实施例中，所述副显示区域的所述发光器件在所述衬底基板上的正投影的面积小于所述过渡区域的所述发光器件在所述衬底基板上的正投影的面积。
在本公开的一种示例性实施例中，所述显示面板还包括：
第四连接导线，连接于最靠近所述主显示区域的所述发光器件与最靠近所述副显示区域的所述像素电路之间，所述第四连接导线被设于所述像素电路的源漏极层。
根据本公开的另一个方面，一种显示装置，包括：
显示面板，是上述任意一项所述的显示面板；
感光传感器，设于所述显示面板的非显示面，并且所述感光传感器在所述显示面上的正投影与所述副显示区域至少部分交叠。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为显示面板区域划分的结构示意图。
图2为显示面板各个区域子像素、像素电路以及发光器件排布的结构示意图。
图3为副显示区域中的一行发光器件中的一半与像素电路的连接关系结构示意图。
图4为连接同一行多个发光器件与多个像素电路的多个连接导线的电容曲线示意图。
图5为与图4中的连接导线连接的多个发光器件的发光亮度曲线示意图。
图6为像素电路的结构示意图。
图7为本公开显示面板第一示例实施方式沿第一连接导线剖切后的结构示意图。
图8为本公开显示面板第一示例实施方式沿第二连接导线剖切后的结构示意图。
图9为本公开显示面板第一示例实施方式第二连接导线处的俯视示意图。
图10为本公开显示面板第二示例实施方式沿第二连接导线剖切后的结构示意图。
图11为本公开显示面板第二示例实施方式第二连接导线处的俯视示意图。
图12为第三连接导线或第一连接导线与第一补偿部或第二补偿部关系结构示意图。
图13为本公开显示面板第三示例实施方式的结构示意图。
图14为本公开显示面板第四示例实施方式的结构示意图。
图15为本公开显示面板第五示例实施方式的结构示意图。
附图标记说明：
10、像素电路；101、第一组像素电路；102、第二组像素电路；103、第三组像素电路；1001、第一像素电路；1002、第二像素电路；
11、衬底基板；12、遮光层；13、缓冲层；14、有源层；15、栅绝缘层；16、栅极；17、层间介电层；181、源极；182、漏极；19、钝化层；
20、发光器件；201、第一发光器件；202、第二发光器件；21、第一电极；22、像素定义层；23、发光层组；24、第二电极；25、封装层组；
31、第一连接导线；32、第二连接导线；33、补偿部；331、第一补偿部；3311、第一部分；3312、第二部分；3312a、第一补偿段；3312b、第一虚设段；332、第二补偿部；3321、第三部分；3322、第四部分；3322a、 第二补偿段；3322b、第二虚设段；333、第三补偿部；34、第三连接导线；
41、第一导电层；42、第一绝缘层；43、第二导电层；44、第二绝缘层；45、第三导电层；46、第三绝缘层；
5、第四连接导线；
100、驱动背板；200、发光基板；
R、红色发光器件；G、绿色发光器件；B、蓝色发光器件；
AA1、主显示区域；AA11、过渡区域；AA12、正常显示区域；AA2、副显示区域；PX、子像素；
X、第一方向；Y、第二方向。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
在本申请中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
发明人发现：导致副显示区域AA2的发光器件20的亮度不均匀的主要原因在于，参照图1和图2所示，为了增加副显示区域AA2的透光率，在副显示区域AA2仅设置有发光器件20，而没有设置像素电路10；在主显示区域AA1设置有像素电路10和能够正常显示的子像素PX；副显示区域AA2的发光器件20需要通过连接导线连接至主显示区域AA1的像素电路10，通过像素电路10驱动发光器件20的发光和发光强度。
但是，由于相邻两行发光器件20之间的空间有限，连接导线需要设置在不同的导电层，越靠近像素电路10的导电层由于能够与像素电路10中的导体层形成电容，使得靠近像素电路10的导电层的单位面积电容大于远离像素电路10的导电层的单位面积电容，因此，使得连接同一行发光器件20的连接导线的电容差距较大，不能形成线形，参照图4所示，例如，L2表示设置在靠近像素电路10的导电层的连接导线的电容，这些连接导线的电容较大，L1表示设置在远离像素电路10的导电层的连接导线的电容，这些连接导线的电容较小，特别是相邻两根连接导线位于不同的导电层时，相邻两根连接导线的电容产生突变，从而导致同一行发光器件20的亮度产生差异，参照图5所示，图5中纵坐标表示亮度，各个点处的数字表示与图4中连接导线对应连接的发光器件，最大亮度差异大约为11.69。
本公开示例实施方式提供了一种显示面板，参照图1-图13所示，该显示面板具有相邻的主显示区域AA1和副显示区域AA2，该显示面板可以包括多个发光器件20、多个像素电路10、多根第一连接导线31、多根第二连接导线32以及多个补偿部33；多个发光器件20阵列排布于副显示区域AA2，包括第一发光器件201和第二发光器件202；多个像素电路10阵列排布于主显示区域AA1，包括第一像素电路1001和第二像 素电路1002；多根第一连接导线31连接于第一发光器件201与第一像素电路1001之间；多根第二连接导线32连接于第二发光器件202与第二像素电路1002之间，第二连接导线32的单位面积电容小于第一连接导线31的单位面积电容；多个补偿部33与多根第二连接导线32对应连接。
本公开的显示面板，第二连接导线32的单位面积电容小于第一连接导线31的单位面积电容，多个补偿部33一一对应连接于多根第二连接导线32。通过补偿部33对第二连接导线32的电容进行补偿，以增大第二连接导线32的电容，减小第二连接导线32的电容与第一连接导线31的电容之间的差距，从而减小发光器件20的亮度差异。
显示面板可以是OLED(Organic Electroluminescence Display，有机发光半导体)显示面板、QLED(Quantum Dot Light Emitting Diodes，量子点发光二极管)显示面板等等；显示面板具有出光侧和非出光侧，出光侧与非出光侧相对设置，在出光侧能够显示画面，显示画面的一面为显示面。OLED显示面板具有自发光、高亮度、广视角、快速反应时间以及R、G、B全彩组件皆可制作等特质，因此被视为次世代显示器的明星产品。
下面以OLED为例进行说明。
在本示例实施方式中，参照图1所示，显示面板可以划分为副显示区域AA2和主显示区域AA1，主显示区域AA1可以包括过渡区域AA11以及正常显示区域AA12。过渡区域AA11环绕主显示区域AA1，正常显示区域AA12环绕过渡区域AA11。
显示面板适用于屏下安装摄像头的显示面板中。副显示区域AA2则对应安装摄像头元件，正常显示区域AA12用于画面的显示。由于过渡区域AA11和副显示区域AA2也需显示画面，但是，副显示区域AA2还需要使得光线能够透过射至非显示侧的摄像头，摄像头可利用透射至非显示侧的光线进行工作，为避免副显示区域AA2的像素元件(例如：薄膜晶体管、发光器件20等元件)遮挡摄像头，故仅在副显示区域AA2设置透明发光器件20，而不设置像素电路10。应当理解的是，在下述描述中副显示区域AA2中的发光器件20均是指透明发光器件20。
而且，为了增加副显示区域AA2的透光率，可以将副显示区域AA2的发光器件20在衬底基板11上的正投影的面积，设置为小于过渡区域AA11的发光器件20在衬底基板11上的正投影的面积，例如，副显示区域AA2的发光器件20在衬底基板11上的正投影的面积，可以是过渡区域AA11的发光器件20在衬底基板11上的正投影的面积的三分之一至三分之二之间，具体可以是二分之一。
而设置在副显示区域AA2的发光器件20需要像素电路10的驱动才能进行发光，因此，在过渡区域AA11设置有多个像素电路10，过渡区域AA11的像素电路10与副显示区域AA2的发光器件20通过连接导线连接。
参照图2所示，图中一个小方框表示一个像素区，显示面板包括多个阵列排布的像素区，正常显示区域AA12的像素区、过渡区域AA11的像素区与副显示区域AA2的像素区的排布是一致的。
在正常显示区域AA12阵列排布有多个能够正常显示的子像素PX，一个像素区内设置有一个子像素PX。在过渡区域AA11阵列排布有多个能够正常显示的子像素PX以及多个像素电路10，一个像素区内设置有一个子像素PX或像素电路10；可以将两个子像素PX与一个像素电路10设置为一组，像素电路10设置在两个子像素PX之间。在副显示区域AA2阵列排布有多个发光器件20，一个像素区内设置有一个发光器件20。子像素PX包括像素电路10和发光器件20。
需要说明的是，沿第一方向X为行，沿第二方向Y为列。过渡区域AA11内的像素电路10与同一行的副显示区域AA2内的发光器件20连接，避免像素电路10与发光器件20之间的连接导线产生更多的交点，影响连接导线的布局，而且容易产生信号干扰。
由于过渡区域AA11设置有多个像素电路10，因此，过渡区域AA11的像素密度小于正常显示区域AA12的像素密度；而过渡区域AA11的像素密度可以与副显示区域AA2的像素密度相同；当然，也可以是过渡区域AA11的像素密度大于副显示区域AA2的像素密度。
需要说明的是，在副显示区域AA2不仅可以安装摄像头，还可以安装红外感应装置、指纹传感器等其他感光传感器。
像素电路10至少包括开关晶体管和驱动晶体管，当然还可以包括阈值补偿晶体管、存储电容等结构，参照图6所示，给出一种示例性的像素电路10。该像素电路10具体可以包括：存储电容C1、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7。
第一晶体管T1的第一端连接至数据线DATA，第一晶体管T1的第二端连接至N1节点，第一晶体管T1的控制端连接扫描线Gate；第二晶体管T2的第一端连接至N1节点，第二晶体管T2的第二端连接至N3节点，第二晶体管T2的控制端连接至N2节点；第三晶体管T3的第一端连接至N3节点，第三晶体管T3的第二端连接至N2节点，第三晶体管T3的控制端连接至扫描线Gate；第四晶体管T4的第一端连接至N2节点，第四晶体管T4的第二端连接至(初始化电压线)Vint1，第四晶体管T4的的控制端连接至第一复位线Reset1；第五晶体管T5的第一端连接至电源线VDD，第五晶体管T5的第二端连接至N1节点，第五晶体管T5的控制端连接至(控制信号线)EM线；第六晶体管T6的第一端连接至N3节点，第六晶体管T6的第二端连接至N4节点，第六晶体管T6的控制端连接至(控制信号线)EM线；第七晶体管T7的第一端连接至(初始化电压线)Vint2，第七晶体管T7的第二端连接至N4节点，第七晶体管T7的控制端连接至第二复位线Reset2。存储电容C1的第一极连接至电源线VDD，存储电容C1的第二极连接至N2节点。发光器件20的第一电极21连接至N4节点，发光器件20的第二电极24连接第二电源线VSS。
其中，上述的所采用的晶体管可以为薄膜晶体管或场效应管或其他特性的相同器件，由于采用的晶体管的源极181和漏极182是对称的，所以其源极181、漏极182是没有区别的。在本公开的实施例中，为区分晶体管的源极181称之为第一端，漏极182称之为第二端，栅极16称为控制端。此外按照晶体管的特性区分可以将晶体管分为N型和P型，当采用P型晶体管时，第一端为P型晶体管的源极181，第二端为P型晶体管的漏极182，栅极16输入低电平时，源漏极182导通；当采用N型晶体管时，第一端为N型晶体管的源极181，第二端为N型晶体管的 漏极182，栅极16输入高电平时，源漏极182导通。其中，上述的像素电路10中的晶体管均是以N型晶体管为例进行说明的，可以想到的是采用P型晶体管实现是本领域技术人员可以在没有付出创造性劳动前提下轻易想到的，因此也是在本公开实施例的保护范围内的。
参照图7-图11所示，图中只画出一个薄膜晶体管，下面以一个薄膜晶体管为例对像素电路10进行详细说明，显示面板可以包括驱动背板100和发光基板200，驱动背板100可以包括多个阵列排布的像素电路10，发光基板200可以包括多个阵列排布的发光器件20，像素电路10可以驱动发光器件20发光。
具体来讲，驱动背板100可以包括衬底基板11，衬底基板11的材料可以包括无机材料，例如，该无机材料可以为玻璃、石英或金属等。衬底基板11的材料还可以包括有机材料，例如，该有机材料可以为聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料。该衬底基板11可以由多层材料层形成，例如衬底基板11可以包括多层基底层，基底层的材料可以是上述的任意一种材料。当然，衬底基板11还可以设置为单层，可以是上述任一一种材料。
在衬底基板11的一侧还可以设置有遮光层12，从衬底基板11射入有源层14的光线会在有源层14产生光生载流子，进而对薄膜晶体管的特性产生巨大影响，最终影响显示装置的显示画质；通过遮光层12可以遮挡从衬底基板11射入的光线，从而避免对薄膜晶体管的特性产生影响，避免影响显示装置的显示画质。
在遮光层12远离衬底基板11的一侧还可以形成缓冲层13，缓冲层13起到阻隔衬底基板11(特别是有机材料)中的水汽以及杂质离子的作用，并且起到为后续形成的有源层14增加氢离子的作用，缓冲层13的材质为绝缘材料，可以将遮光层12与有源层14绝缘隔离。
在缓冲层13的远离衬底基板11的一侧设置有源层14，有源层14可以包括沟道部以及设置在沟道部两端的导体部，在有源层14的远离衬底基板11的一侧设置有栅绝缘层15，在栅绝缘层15的一侧设置有栅极16，在栅极16的远离衬底基板11的一侧设置有层间介电层17，在层 间介电层17上设置有第一过孔，第一过孔连通至导体部；在层间介电层17的远离衬底基板11的一侧设置有源极181和漏极182，源极181和漏极182分别对应通过两个第一过孔连接至两个导体部。在源极181和漏极182远离衬底基板11的一侧设置有钝化层19，在钝化层19上设置有第二过孔，第二过孔连接至源极181。有源层14、栅极16、源极181和漏极182形成薄膜晶体管。
需要说明的是，本说明书中说明的薄膜晶体管为顶栅型薄膜晶体管，在本公开的其他示例实施方式中，薄膜晶体管还可以是底栅型或双栅型，对其具体结构在此不再赘述。而且，在使用极性相反的薄膜晶体管的情况或电路工作中的电流方向变化的情况等下，“源极181”及“漏极182”的功能有时互相调换。因此，在本说明书中，“源极181”和“漏极182”可以互相调换。
由于在副显示区域AA2没有设置像素电路10，因此，驱动背板100在副显示区域AA2可以包括依次层叠设置的衬底基板11、缓冲层13、栅绝缘层15、层间介电层17以及钝化层19等等。驱动背板100在正常显示区域AA12和在过渡区域AA11的结构可以相同。
请继续参照图7和图8所示，在钝化层19背离衬底基板11的一侧设置有第一导电层41，在第一导电层41背离所述衬底基板11的一侧设置有第一绝缘层42，在第一绝缘层42背离所述衬底基板11的一侧设置有第二导电层43。
在副显示区域AA2的面积较小，设置的发光器件20较少的情况下，可以仅设置第一导电层41和第二导电层43。参照图7所示，第一导电层41可以包括第一连接导线31，第一连接导线31可以从过渡区域AA11延伸至副显示区域AA2；具体地，第一连接导线31的一端通过钝化层19上设置的第二过孔连接至源极181；第一连接导线31的另一端连接至发光器件20的第一电极21。
第一导电层41可以是透明导电层，即第一导电层41的材质可以是ITO(Indium Tin Txide，氧化铟锡)、IZO(铟锌氧化物)等等。
在本公开的另一些示例实施方式中，第一连接导线31可以是大部分设置在副显示区域AA2，仅有一小部分延伸至过渡区域AA11；而过渡 区域AA11的薄膜晶体管的源极181向副显示区域AA2一侧延伸形成第一补充连接导线，第一补充连接导线延伸至过渡区域AA11的边沿，然后，第一连接导线31通过钝化层19上设置的第二过孔连接至第一补充连接导线，如此设置，使得连接发光器件20和薄膜晶体管的连接导线位于副显示区域AA2的一部分(第一连接导线31)为透明导电材料，而位于过渡区域AA11的一部分(第一补充连接导线)为金属材料，这样可以降低连接导线的电阻，提高显示亮度。
参照图8所示，第二导电层43可以包括第二连接导线32，第二连接导线32可以从过渡区域AA11延伸至副显示区域AA2；具体地，第二连接导线32的一端通过钝化层19上设置的第二过孔以及第一绝缘层42上设置的第三过孔连接至源极181；第二连接导线32的另一端连接至发光器件20的第一电极21。
第二导电层43可以是透明导电层，即第二导电层43的材质可以是ITO(Indium Tin Txide，氧化铟锡)、IZO(铟锌氧化物)等等。
在源漏极层设置为一层的情况下，由于相邻两行发光器件20之间的空间有限，不能够在一层内容纳所有的连接导线，上述源漏极层已经设置有第一补充连接导线，因此，第二连接导线32可以从过渡区域AA11延伸至副显示区域AA2，以连接像素电路10和发光器件20。
在本公开的另一些示例实施方式中，在源漏极层设置为两层的情况下，即上述源漏极层为第一源漏极层，在钝化层19背离衬底基板11的一侧还设置有第二源漏极层，第二源漏极可以包括连接电极和第二补充连接导线，连接电极与第二补充连接导线连接，连接电极通过钝化层19上设置的第二过孔连接至源极181，第二补充连接导线延伸至过渡区域AA11的边沿。在第二源漏极182层背离衬底基板11的一侧设置绝缘层，在绝缘层背离衬底基板11的一侧依次设置上述第一导电层41、第一绝缘层42、第二导电层43。
第二连接导线32可以是大部分设置在副显示区域AA2，仅有一小部分延伸至过渡区域AA11；第二连接导线32通过绝缘层上设置的第四过孔连接至第二补充连接导线，如此设置，使得连接发光器件20和薄膜晶体管的连接导线位于副显示区域AA2的一部分(第二连接导线32) 为透明导电材料，而位于过渡区域AA11的一部分(第二补充连接导线)为金属材料，这样可以降低连接导线的电阻，提高显示亮度。
另外，由于第一连接导线31相对于第二连接导线32更靠近像素电路10的导电层，第一连接导线31与像素电路10中的导体层形成电容，使得第一连接导线31的单位面积电容大于第二连接导线32的单位面积电容，因此，使得连接同一行发光器件20的第一连接导线31和第二连接导线32的电容差距较大，不能形成线形，即使后续进行算法补偿也会出现亮度差异。
参照图9所示，可以在第二导电层43设置第二补偿部332，第二补偿部332设置为图形化设置。第二补偿部332可以设置在过渡区域AA11。由于第二连接导线32从像素电路10引出后折弯至相邻两行像素电路10之间的间隙内，且沿该间隙延伸，因此，将第二补偿部332设置为矩形结构，使得第二补偿部332的两侧边沿与第二连接导线32连接，即使得第二连接导线32的靠近像素电路10的一端图形化设置。通过第二补偿部332可以增加第二连接导线32的电容，使得第二连接导线32的电容与第一连接导线31的电容之间的差距减小，从而减小发光器件20的亮度差异。当然，第二补偿部332还可以设置为各种多边形或具有弧形边的图形。
参照图3所示，图中以红色发光器件为例标出了第一发光器件201、第二发光器件202、第一像素电路1001和第二像素电路1002；多根第一连接导线31一一对应地连接于沿第一方向X排列的多个第一发光器件201和多个第一像素电路1001之间，多根第二连接导线32一一对应地连接于沿第一方向X排列的多个第二发光器件202和多个第二像素电路1002之间；多个第一发光器件201和多个第二发光器件202位于同一行且颜色相同，第一发光器件201相对于第二发光器件202更靠近主显示区域AA1，第一像素电路1001相对于第二像素电路1002更靠近副显示区域AA2。第一方向X为从副显示区域AA2指向主显示区域AA1的方向，需要说明的是，从主显示区域AA1指向副显示区域AA2的方向也是第一方向X。具体地，第一方向X为行，也可以说第一方向X为行方向。
沿副显示区域AA2指向主显示区域AA1的方向，连接同一行多个第一发光器件201和多个第二发光器件202的多根第一连接导线31的电容和多根第二连接导线32的电容呈线性依次增加或减小。
具体参照图4所示，图中L3为对多根第二连接导线32补偿后的电容形成的曲线，图中L3与L2基本形成一条直线，通过补偿部33对第二连接导线32的电容进行补偿需要达到的要求是：沿副显示区域AA2指向主显示区域AA1的方向，连接同一行多个第一发光器件201和多个第二发光器件202的多根第一连接导线31的电容和多根第二连接导线32的电容呈线性依次增加或减小，而且，相邻两个第一连接导线31之间的电容的差值是基本相同的，相邻两个第二连接导线32之间的电容的差值是基本相同的，相邻的第一连接导线31与第二连接导线32之间的电容的差值均是基本相同的。
参照表一所示的对连接红色发光器件R的第二连接导线32补偿前后的电容对比表。
表一
Figure PCTCN2022100394-appb-000001
因此，与各个第二连接导线32连接的第二补偿部332的面积大小，可以根据上述需要设置。
另外，参照图8和图9所示，还可以在第一导电层41设置第一补偿部331，第一补偿部331可以包括第一部分3311和第二部分3312。第二部分3312连接于第一部分3311，第一部分3311沿第二方向Y延伸，第二部分3312沿第一方向X延伸，第二部分3312与第一部分3311的连 接处形成拐角。
第一部分3311连接于第二连接导线32，具体地，第一部分3311可以通过钝化层19上的第五过孔连接至源极181，从而通过源极181将第二连接导线32与第一部分3311连接；第一部分3311和第二连接导线32通过不同的过孔连接至源极181，因此，第一部分3311在衬底基板11上的正投影与第二连接导线32在衬底基板11上的正投影无交叠。当然，在本公开的其他一些示例实施方式中，可以是第一部分3311先连接至源极181，第二连接导线32再连接至第一部分3311，这样的话，第一部分3311在衬底基板11上的正投影与第二连接导线32在衬底基板11上的正投影可以重叠。
在相邻两行像素电路10之间的多根第二连接导线32均需要补偿，而且由于第二部分3312在第一方向X的长度比第二连接导线32在第一方向X的长度短，使得第二部分3312在衬底基板11上的正投影位于第二连接导线32在衬底基板11上的正投影内，即将第二部分3312与第二连接导线32重叠设置，方便容纳多根第一补偿部331；而且方便设计时的计算，另外，第一补偿部331与第二连接导线32之间也可以形成电容，进一步增加第二连接导线32的电容。
需要说明的是，第一补偿部331和第二补偿部332可以同时设置，也可以仅设置第一补偿部331，还可以仅设置第二补偿部332。
在本公开的一些示例实施方式中，在第一导电层41还可以设置第四补偿部，第四补偿部可以图形化设置。第四补偿部可以设置在过渡区域AA11。由于第一补偿部331从像素电路10引出后折弯至相邻两行像素电路10之间的间隙内，且沿该间隙延伸，因此，将第四补偿部设置为矩形结构，使得第四补偿部的两侧边沿与第一补偿部331连接，即使得第一补偿部331的靠近像素电路10的一端图形化设置。通过第四补偿部33可以增加第二连接导线32的电容，使得第二连接导线32的电容与第一连接导线31的电容之间的差距减小，从而减小发光器件20的亮度差异。
参照图10所示，显示面板还可以包括第二绝缘层44和第三导电层45；具体地，第二绝缘层44设于第二导电层43背离衬底基板11的一侧； 第三导电层45设于第二绝缘层44背离衬底基板11的一侧。第三导电层45可以包括第二连接导线32，第二导电层43可以包括第一连接导线31，补偿部33设于第一导电层41和/或第二导电层43和/或第三导电层45。
第三导电层45可以是透明导电层，即第三导电层45的材质可以是ITO(Indium Tin Txide，氧化铟锡)、IZO(铟锌氧化物)等等。
具体来讲，在副显示区域AA2的面积较大，设置的发光器件20较多的情况下，可以设置第一导电层41、第二导电层43和第三导电层45。在第一导电层41、第二导电层43和第三导电层45上均可以设置连接像素电路10和发光器件20的连接导线，使得在相邻两行发光器件20具有相同间隙的情况下可以容纳较多的连接导线，以满足副显示区域AA2的面积较大，设置的发光器件20较多的目的。
由于第一导电层41相对于第二导电层43更靠近像素电路10的导电层，第一导电层41与像素电路10中的导体层形成电容，使得第一导电层41的单位面积电容较大；而第二导电层43与第一导电层41和第三导电层45均能够形成电容，使得第二导电层43的单位面积电容也比较大；但是第三导电层45只能与第二导电层43形成电容，使得第三导电层45的单位面积电容比第一导电层41和第二导电层43的单位面积电容均小。
因此，在将连接同一行发光器件20的第二连接导线32设置在第三导电层45，且将第一连接导线31设置在第二导电层43时，使得第一连接导线31的单位面积电容大于第二连接导线32的单位面积电容，因此，使得连接同一行发光器件20的第一连接导线31和第二连接导线32的电容差距较大，不能形成线形，即使后续进行算法补偿也会出现亮度差异。
在本公开的一些示例实施方式中，参照图10和图11所示，图11中为了区分第二连接导线32、第二部分3312和第四部分3322，因此，把他们的宽度画的不同，实际产品中可以根据需要设置他们的宽度；可以在第一导电层41设置第一补偿部331，第一补偿部331可以包括第一部分3311和第二部分3312。第二部分3312连接于第一部分3311，第一部分3311沿第二方向Y延伸，第二部分3312沿第一方向X延伸，第二部分3312与第一部分3311的连接处形成拐角。
第一部分3311连接于第二连接导线32，具体地，第一部分3311可 以通过钝化层19上的第五过孔连接至源极181，从而通过源极181将第二连接导线32与第一部分3311连接；第一部分3311和第二连接导线32通过不同的过孔连接至源极181，因此，第一部分3311在衬底基板11上的正投影与第二连接导线32在衬底基板11上的正投影无交叠。当然，在本公开的其他一些示例实施方式中，可以是第一部分3311先连接至源极181，第二连接导线32再连接至第一部分3311，这样的话，第一部分3311在衬底基板11上的正投影与第二连接导线32在衬底基板11上的正投影可以重叠。
在相邻两行像素电路10之间的多根第二连接导线32均需要补偿，而且由于第二部分3312在第一方向X的长度比第二连接导线32在第一方向X的长度短，使得第二部分3312在衬底基板11上的正投影位于第二连接导线32在衬底基板11上的正投影内，即将第二部分3312与第二连接导线32重叠设置，方便容纳多根第一补偿部331；而且方便设计时的计算，另外，第一补偿部331与第二连接导线32之间也可以形成电容，进一步增加第二连接导线32的电容。
在本公开的一些示例实施方式中，请继续参照图10和图11所示，可以在第二导电层43设置第二补偿部332，第二补偿部332可以包括第三部分3321和第四部分3322。第四部分3322连接于第三部分3321，第三部分3321沿第二方向Y延伸，第四部分3322沿第一方向X延伸，第四部分3322与第三部分3321的连接处形成拐角。
第三部分3321连接于第二连接导线32，具体地，第三部分3321可以通过钝化层19和第一绝缘层42上的过孔连接至源极181，从而通过源极181将第二连接导线32与第三部分3321连接；第三部分3321和第二连接导线32通过不同的过孔连接至源极181，因此，第三部分3321在衬底基板11上的正投影与第二连接导线32在衬底基板11上的正投影无交叠。当然，在本公开的其他一些示例实施方式中，可以是第三部分3321先连接至源极181，第二连接导线32再连接至第三部分3321，这样的话，第三部分3321在衬底基板11上的正投影与第二连接导线32在衬底基板11上的正投影可以重叠。
在相邻两行像素电路10之间的多根第二连接导线32均需要补偿， 而且由于第四部分3322在第一方向X的长度比第二连接导线32在第一方向X的长度短，使得第四部分3322在衬底基板11上的正投影位于第二连接导线32在衬底基板11上的正投影内，即将第四部分3322与第二连接导线32重叠设置，方便容纳多根第二补偿部332；而且方便设计时的计算，另外，第二补偿部332与第二连接导线32之间也可以形成电容，进一步增加第二连接导线32的电容。
在本公开的一些示例实施方式中，请继续参照图11所示，可以在第三导电层45设置第三补偿部333，第三补偿部333图形化设置。第三补偿部333可以设置在过渡区域AA11。由于第二连接导线32从像素电路10引出后折弯至相邻两行像素电路10之间的间隙内，且沿该间隙延伸，因此，将第三补偿部333设置为矩形结构，使得第三补偿部333的两侧边沿与第二连接导线32连接，即使得第二连接导线32的靠近像素电路10的一端图形化设置。通过第三补偿部333可以增加第二连接导线32的电容，使得第二连接导线32的电容与第一连接导线31的电容之间的差距减小，从而减小发光器件20的亮度差异。当然，第三补偿部333还可以设置为各种多边形或具有弧形边的图形。
多根第一连接导线31和多根第二连接导线32一一对应地连接于沿第一方向X排列的多个发光器件20，多个发光器件20沿第一方向X排列序号，多根第一连接导线31和多根第二连接导线32的排列序号与与其连接的多个发光器件20的排列序号相同。参照图4所示，图中L3为对多根第二连接导线32补偿后的电容曲线，图中L3与L1基本形成一条直线，通过补偿部33对第二连接导线32的电容进行补偿需要达到的要求是：多根第一连接导线31的电容和多根第二连接导线32的电容按照排列序号呈线性，例如，多根第一连接导线31的电容和多根第二连接导线32的电容按照排列序号依次增大或减小，而且，相邻两个第一连接导线31之间的电容的差值是相同的，相邻两个第二连接导线32之间的电容的差值是相同的，相邻的第一连接导线31与第二连接导线32之间的电容的差值均是相同的。
因此，与各个第二连接导线32连接的第三补偿部333的面积大小、第一补偿部331的面积大小以及第二补偿部332的面积大小，可以根据 上述需要进行设置。
需要说明的是，第一补偿部331、第二补偿部332和第三补偿部333可以同时设置。可以仅设置第一补偿部331，也可以仅设置第二补偿部332，还可以仅设置第三补偿部333。还可以设置第一补偿部331、第二补偿部332和第三补偿部333中的其中两种，可以根据实际需要补偿的电容进行确定。
在本公开的一些示例实施方式中，在第一导电层41还可以设置第四补偿部，第四补偿部可以图形化设置。第四补偿部可以设置在过渡区域AA11。由于第一补偿部331从像素电路10引出后折弯至相邻两行像素电路10之间的间隙内，且沿该间隙延伸，因此，将第四补偿部设置为矩形结构，使得第四补偿部的两侧边沿与第一补偿部331连接，即使得第一补偿部331的靠近像素电路10的一端图形化设置。通过第四补偿部可以增加第二连接导线32的电容，使得第二连接导线32的电容与第一连接导线31的电容之间的差距减小，从而减小发光器件20的亮度差异。
另外，在第二导电层43还可以设置第五补偿部，第五补偿部可以图形化设置。第五补偿部可以设置在过渡区域AA11。由于第一补偿部331从像素电路10引出后折弯至相邻两行像素电路10之间的间隙内，且沿该间隙延伸，因此，将第五补偿部设置为矩形结构，使得第五补偿部的两侧边沿与第一补偿部331连接，即使得第一补偿部331的靠近像素电路10的一端图形化设置。通过第五补偿部可以增加第二连接导线32的电容，使得第二连接导线32的电容与第一连接导线31的电容之间的差距减小，从而减小发光器件20的亮度差异。
当然，第四补偿部和第五补偿部还可以设置为各种多边形或具有弧形边的图形。
参照图3所示，图中用不同的线型表示连接导线设置在不同的导电层，而且图中表示副显示区域AA2中的一行发光器件20中的一半与像素电路10的连接关系，因为，副显示区域AA2一般是对称设置的，过渡区域AA11也是对称设置的，副显示区域AA2中左半侧的发光器件20连接于对应侧的像素电路10，副显示区域AA2中右半侧的发光器件20连接于对应侧的像素电路10。图中与绿色发光器件G连接的像素电路标 记为G’，与红色发光器件R连接的像素电路标记为R’，与蓝色发光器件B连接的像素电路标记为B’。
在本示例实施方式中，同一行的多个像素电路10可以包括第一组像素电路101、第二组像素电路102和第三组像素电路103，第一组像素电路101、第二组像素电路102和第三组像素电路103依次远离副显示区域AA2设置，具体地，第一组像素电路101靠近副显示区域AA2设置，第一组像素电路101的像素电路10可以设置有十四个；第二组像素电路102设于第一组像素电路101背离副显示区域AA2的一侧，第二组像素电路102的像素电路10可以设置有十三个；第三组像素电路103设于第二组像素电路102背离副显示区域AA2的一侧，第三组像素电路103的像素电路10可以设置有十三个。第一组像素电路101、第二组像素电路102和第三组像素电路103各自所包括的像素电路10的数量可以根据需要设置。
其中，第一组像素电路101通过第一导电层41与发光器件20连接，第二组像素电路102通过第二导电层43与发光器件20连接，第三组像素电路103通过第三导电层45与发光器件20连接。具体地，第一导电层41可以包括十四根第三连接导线34，十四根第三连接导线34对应连接于第一组像素电路101的十四个像素电路10与十四个发光器件20之间，该十四个发光器件20可以都是绿色发光器件G；十三根第一连接导线31对应连接于第二组像素电路102的十三个像素电路10与十三个发光器件20之间，该十三个发光器件20中其中六个可以是绿色发光器件G，其中三个可以是蓝色发光器件B，其中四个可以是红色发光器件R；多根第二连接导线32对应连接于第三组像素电路103的多个像素电路10与多个发光器件20之间，该十三个发光器件20中其中七个可以是蓝色发光器件B，其中六个可以是红色发光器件R。
如此设置，参照图3和图12所示，使得第三连接导线34只占据了过渡区域AA11靠近副显示区域AA2的一部分，而过渡区域AA11靠近正常显示区域AA12的一部分并没有被占据，因此，在过渡区域AA11靠近正常显示区域AA12的一部分可以设置第一补偿部331，且使得第一补偿部331与第三连接导线34间隔设置，第一补偿部331位于第三连 接导线34远离副显示区域的一侧，第三连接导线34与第一补偿部331同属于第一导电层41，从而避免第一补偿部331对第三连接导线34的排布和电性能产生影响。而且，多个第一补偿部331靠近副显示区域AA2的一端可以平齐，具体地，第一补偿部331的第二部分3312可以包括第一补偿段3312a和第一虚设段3312b；第一补偿段3312a连接于第二连接导线32，即第一补偿段3312a连接于第一部分3311，通过第一部分3311连接于第二连接导线32；第一虚设段3312b与第一补偿段3312a间隔设置，且位于第一补偿段3312a靠近副显示区域AA2的一侧；第一补偿段3312a对第二连接导线32有电容补偿的作用，第一虚设段3312b对第二连接导线32没有电容补偿的作用，只是为了保持刻蚀的均一性。多个第一补偿段3312a在衬底基板11上的正投影的面积相同，即多个第一补偿段3312a在第一方向X的长度相同，在第二方向Y的宽度相同。使得多个第一补偿段3312a对多个第二连接导线32所补偿的电容是相同的。
当然，也可以将多个第一补偿部331设置为相同的长度，使得多个第一补偿部331对应对多个第二连接导线32的补偿的电容相同，那么多个第一补偿部331靠近副显示区域AA2的一端可以不平齐。
同理，参照图3和图12所示，使得第一连接导线31只占据了过渡区域AA11靠近副显示区域AA2的一部分，而过渡区域AA11靠近正常显示区域AA12的一部分并没有被占据，因此，在过渡区域AA11靠近正常显示区域AA12的一部分可以设置第二补偿部332，且使得第二补偿部332与第一连接导线31间隔设置，第二补偿部332位于第一连接导线31远离副显示区域的一侧，第一连接导线31与第二补偿部332同属于第二导电层42，从而避免第二补偿部332对第一连接导线31的排布和电性能产生影响。而且，多个第二补偿部332靠近副显示区域AA2的一端可以平齐，具体地，第二补偿部332的第四部分3322可以包括第二补偿段3322a和第二虚设段3322b；第二补偿段3322a连接于第二连接导线32，即第二补偿段3322a连接于第三部分3321，通过第三部分3321连接于第二连接导线32；第二虚设段3322b与第二补偿段3322a间隔设置，且位于第二补偿段3322a靠近副显示区域的一侧；第二补偿段3322a对第二连接导线32有电容补偿的作用，第二虚设段3322b对第二连接导 线32没有电容补偿的作用，只是为了保持刻蚀的均一性。多个第二补偿段3322a在衬底基板11上的正投影的面积相同，即多个第二补偿段3322a在第一方向X的长度相同，在第二方向Y的宽度相同。使得多个第二补偿段3322a对多个第二连接导线32所补偿的电容是相同的。
当然，也可以将多个第二补偿部332设置为相同的长度，使得多个第二补偿部332对应对多个第二连接导线32的补偿的电容相同，那么多个第二补偿部332靠近副显示区域AA2的一端可以不平齐。
当然，在本公开的其他示例实施方式中，可以将补偿部33设置在副显示区域AA2，例如，可以将副显示区域AA2的同一行的多个发光器件20按照与过渡区域AA11的距离的远近分成多组，每一组通过一层导电层中的连接导线与过渡区域AA11的像素电路10连接，使得连接导线没有占满副显示区域AA2，可以在没有设置连接导线的一部分导电层上设置补偿部；也就是说，副显示区域AA2的发光器件20连接方式与上述过渡区域AA11的像素电路10的连接方式一样。
参照图3所示，在本示例实施方式中，同一行的多个发光器件20可以包括多个绿色发光器件G、多个红色发光器件R和多个蓝色发光器件B，它们的排列方式可以是BGRG；多个绿色发光器件G依次对应连接于靠近副显示区域AA2的同一行的多个像素电路10；即多个绿色发光器件G依次对应连接于第一组像素电路101的多个像素电路10和第二组像素电路102靠近副显示区域AA2的多个像素电路10。多个红色发光器件R和多个蓝色发光器件B，交替对应连接于远离副显示区域AA2的同一行的多个像素电路10，即多个红色发光器件R和多个蓝色发光器件B，交替对应连接于第三组像素电路103的多个像素电路10和第二组像素电路102远离副显示区域AA2的多个像素电路10。
如此设置，使得连接绿色发光器件G与像素电路10的连接导线的长度较短，可以称之为绿色优先的连接方式；由于绿色发光器件G的发光材料感应驱动的速度较慢，如果绿色发光器件G与红色发光器件R和蓝色发光器件B同时进行驱动，绿色发光器件G会落后于红色发光器件R和蓝色发光器件B的发光速度，导致显示面板整体发紫；将连接绿色发光器件G与像素电路10的连接导线的长度设计的较短，可以使得绿 色发光器件G提前进行驱动，从而使得绿色发光器件G与红色发光器件R和蓝色发光器件B几乎同时发光，进而使得显示面板正常显示，不会整体发紫。
参照图13所示，显示面板还可以包括第四连接导线5，第四连接导线5连接于最靠近主显示区域AA1的发光器件20与最靠近副显示区域AA2的像素电路10之间，第四连接导线5被设于像素电路10的源漏极层。也就是说，在副显示区域AA2的像素密度较大，连接导线较多的情况下，可以将最靠近副显示区域AA2的像素电路10的源极181延伸至副显示区域AA2形成第四连接导线5，最靠近主显示区域AA1的发光器件20的第一电极21可以通过各层绝缘层上的过孔与第四连接导线5连接。由于第四连接导线5连接的是最靠近主显示区域AA1的发光器件20与最靠近副显示区域AA2的像素电路10，因此，第四连接导线5延伸至副显示区域AA2内的长度很短，因此，不会对副显示区域AA2的透光效果产生影响，不会影响摄像头的成型效果。
参照图7、图8和图10所示，发光器件20可以包括第一电极21、像素定义层22、发光层组23以及第二电极24。第一电极21可以是阳极(像素电极)。
参照图7和图8所示，可以将第一电极21和第二连接导线32设置在同一导电层，即第二导电层43可以包括第一电极21和第二连接导线32。第一电极21与第二连接导线32连接时，可以将第一电极21与第二连接导线32只作为一体结构。第一电极21与第一连接导线31连接时，可以通过第一绝缘层42上的过孔实现连接。
参照图10所示，可以将第一电极21和第二连接导线32设置在同一导电层，即第三导电层45可以包括第一电极21和第二连接导线32。第一电极21与第二连接导线32连接时，可以将第一电极21与第二连接导线32只作为一体结构。第一电极21与第一连接导线31连接时，可以通过第二绝缘层44上的过孔实现连接。第一电极21与第三连接导线34连接时，可以通过第一绝缘层42上的过孔和第二绝缘层44上的过孔实现连接。
当然，可以将第一电极21和第二连接导线32设置在不同的导电层。 例如，参照图14所示，可以在第二导电层43背离衬底基板的一侧设置第二绝缘层44，在第二绝缘层44背离衬底基板的一侧设置第一电极21；第一电极21通过各层绝缘层上的过孔实现与第一连接导线31以及第二连接导线32的连接，具体的连接方式在此不再赘述。例如，参照图15所示，可以在第三导电层45背离衬底基板的一侧设置第三绝缘层46，在第三绝缘层46背离衬底基板的一侧设置第一电极21；第一电极21通过各层绝缘层上的过孔实现与第一连接导线31、第二连接导线32以及第三连接导线34的连接，具体的连接方式在此不再赘述。
而且，参照图14和图15所示，由于补偿部33的材质是透明材质，因此，补偿部33也可以设置在副显示区域AA2。
在第一电极21远离衬底基板11的一侧设置有像素定义层22，像素定义层22上设置有开口部，在开口部内设置有发光层组23。在发光层组23远离衬底基板11的一侧设置有第二电极24，第二电极24可以是阴极(公共电极)，第二电极24连接至地线VSS。
发光层组23可以包括依次层叠设置的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层，空穴注入层与第一电极21接触，电子注入层与第二电极24接触。当然，在本公开的其他示例实施方式中，发光层组23可以仅包括空穴传输层、发光层和电子传输层，发光层组23还可以是其他结构，其具体结构可以根据需要设置。
在第二电极24远离衬底基板11的一侧设置有封装层组25。封装层组25可以设置为多层，封装层组25可以包括有机层和无机层，具体地，封装层组25可以包括第一无机层，设置在第一无机层远离衬底基板11的一侧的有机层，设置在有机层远离衬底基板11的一侧的第二无机层。第一无机层、有机层和第二无机层的材料在此不再赘述。当然，封装层组25还可以包括更多层或更少的层数。
在本公开的其他一些示例实施方式中，可以在封装层组25背离衬底基板11的一侧设置触控层组，通过触控层组实现触控功能。在触控层组背离衬底基板11的一侧设置偏光片，在偏光片背离衬底基板11的一侧设置盖板。
基于同一发明构思，本公开示例实施方式提供了一种显示装置，该 显示装置可以包括上述任意一项所述的显示面板和感光传感器，显示面板的具体结构上述已经进行了详细说明，因此，此处不再赘述。
感光传感器设于显示面板的非显示面，并且感光传感器在显示面上的正投影与副显示区域至少部分交叠，例如，感光传感器在显示面上的正投影可以与副显示区域重叠，感光传感器在显示面上的正投影可以位于副显示区域之内等等。
而该显示装置的具体类型不受特别的限制，本领域常用的显示装置类型均可，具体例如手机等移动装置、手表等可穿戴设备、VR装置等等，本领域技术人员可根据该显示设备的具体用途进行相应地选择，在此不再赘述。
需要说明的是，该显示装置除了显示面板以外，还包括其他必要的部件和组成，以显示器为例，具体例如外壳、电路板、电源线，等等，本领域技术人员可根据该显示装置的具体使用要求进行相应地补充，在此不再赘述。
与现有技术相比，本发明示例实施方式提供的显示装置的有益效果与上述示例实施方式提供的显示面板的有益效果相同，在此不做赘述。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (24)

  1. 一种显示面板，具有相邻的主显示区域和副显示区域，其中，所述显示面板包括：
    多个发光器件，阵列排布于所述副显示区域，包括第一发光器件和第二发光器件；
    多个像素电路，阵列排布于所述主显示区域，包括第一像素电路和第二像素电路；
    多根第一连接导线，连接于所述第一发光器件与所述第一像素电路之间；
    多根第二连接导线，连接于所述第二发光器件与所述第二像素电路之间，所述第二连接导线的单位面积电容小于所述第一连接导线的单位面积电容；
    多个补偿部，与多根所述第二连接导线对应连接。
  2. 根据权利要求1所述的显示面板，其中，所述第一发光器件和所述第二发光器件位于同一行且颜色相同，所述第一发光器件相对于所述第二发光器件更靠近所述主显示区域，所述第一像素电路相对于所述第二像素电路更靠近所述副显示区域，所述第二连接导线设于所述第一连接导线背离所述像素电路的一侧，沿所述副显示区域指向所述主显示区域的方向，连接同一行多个所述第一发光器件和多个所述第二发光器件的多根所述第一连接导线的电容和多根所述第二连接导线的电容呈线性依次增加或减小。
  3. 根据权利要求2所述的显示面板，其中，所述第一发光器件和第二发光器件为红色发光器件和/或蓝色发光器件。
  4. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    衬底基板；
    第一导电层，设于所述衬底基板的一侧；
    第一绝缘层，设于所述第一导电层背离所述衬底基板的一侧；
    第二导电层，设于所述第一绝缘层背离所述衬底基板的一侧。
  5. 根据权利要求4所述的显示面板，其中，所述第一导电层包括所述第一连接导线，所述第二导电层包括所述第二连接导线，所述补偿部 设于所述第一导电层和/或所述第二导电层。
  6. 根据权利要求5所述的显示面板，其中，所述补偿部包括第一补偿部、第二补偿部中的一种或两种；所述第一补偿部设于所述第一导电层，所述第二补偿部设于所述第二导电层。
  7. 根据权利要求6所述的显示面板，其中，所述第二补偿部图形化设置，所述第二补偿部的部分边沿与所述第二连接导线连接。
  8. 根据权利要求4所述的显示面板，其中，所述显示面板还包括：
    第二绝缘层，设于所述第二导电层背离所述衬底基板的一侧；
    第三导电层，设于所述第二绝缘层背离所述衬底基板的一侧；
    其中，所述第三导电层包括所述第二连接导线，所述第二导电层包括所述第一连接导线，所述补偿部设于所述第一导电层和/或所述第二导电层和/或所述第三导电层。
  9. 根据权利要求8所述的显示面板，其中，所述补偿部包括设于所述第一导电层的第一补偿部、设于所述第二导电层的第二补偿部或设于所述第三导电层的第三补偿部中的至少一种。
  10. 根据权利要求6或9所述的显示面板，其中，所述第一补偿部包括：
    第一部分，连接于所述第二连接导线，所述第一部分在所述衬底基板上的正投影与所述第二连接导线在所述衬底基板上的正投影无交叠；
    第二部分，连接于所述第一部分，所述第二部分在所述衬底基板上的正投影位于所述第二连接导线在所述衬底基板上的正投影内。
  11. 根据权利要求9所述的显示面板，其中，所述第二补偿部包括：
    第三部分，连接于所述第二连接导线，所述第三部分在所述衬底基板上的正投影与所述第二连接导线在所述衬底基板上的正投影无交叠；
    第四部分，连接于所述第三部分，所述第四部分在所述衬底基板上的正投影位于所述第二连接导线在所述衬底基板上的正投影内。
  12. 根据权利要求9所述的显示面板，其中，所述第三补偿部设置为图形化设置，所述第三补偿部的部分边沿与所述第二连接导线连接。
  13. 根据权利要求9所述的显示面板，其中，所述补偿部设于所述主显示区域。
  14. 根据权利要求13所述的显示面板，其中，所述主显示区域包括：
    正常显示区域；
    过渡区域，设于所述副显示区域与所述正常显示区域之间，所述像素电路设于所述过渡区域，所述补偿部设于所述过渡区域。
  15. 根据权利要求14所述的显示面板，其中，同一行的多个所述像素电路包括：
    第一组像素电路，靠近所述副显示区域设置；
    第二组像素电路，设于所述第一组像素电路背离所述副显示区域的一侧；
    第三组像素电路，设于所述第二组像素电路背离所述副显示区域的一侧；
    其中，所述第一组像素电路通过所述第一导电层与所述发光器件连接，所述第二组像素电路通过所述第二导电层与所述发光器件连接，所述第三组像素电路通过所述第三导电层与所述发光器件连接。
  16. 根据权利要求15所述的显示面板，其中，所述显示面板还包括：
    多根第三连接导线，设于所述第一导电层，多根所述第三连接导线对应连接于所述第一组像素电路与多个所述发光器件之间，多根所述第一连接导线对应连接于所述第二组像素电路与多个所述发光器件之间，多根所述第二连接导线对应连接于所述第三组像素电路与多个所述发光器件之间。
  17. 根据权利要求16所述的显示面板，其中，所述第一补偿部与所述第三连接导线间隔设置，且位于所述第三连接导线远离所述副显示区域的一侧；所述第二补偿部与所述第一连接导线间隔设置，且位于所述第一连接导线远离所述副显示区域的一侧。
  18. 根据权利要求17所述的显示面板，其中，多个所述第一补偿部靠近所述副显示区域的一端平齐，多个所述第二补偿部靠近所述副显示区域的一端平齐。
  19. 根据权利要求18所述的显示面板，其中，
    所述第一补偿部包括：
    第一补偿段，连接于所述第二连接导线；
    第一虚设段，与所述第一补偿段间隔设置，且位于所述第一补偿段靠近所述副显示区域的一侧；
    所述第二补偿部包括：
    第二补偿段，连接于所述第二连接导线；
    第二虚设段，与所述第二补偿段间隔设置，且位于所述第二补偿段靠近所述副显示区域的一侧；
    其中，多个所述第一补偿段在所述衬底基板上的正投影的面积相同，多个所述第二补偿段在所述衬底基板上的正投影的面积相同，多个所述第一虚设段靠近所述副显示区域的一端平齐，多个所述第二虚设段靠近所述副显示区域的一端平齐。
  20. 根据权利要求15所述的显示面板，其中，同一行的多个所述发光器件包括：
    多个绿色发光器件，依次对应连接于靠近所述副显示区域的同一行的多个所述像素电路；
    多个红色发光器件和多个蓝色发光器件，交替对应连接于远离所述副显示区域的同一行的多个所述像素电路。
  21. 根据权利要求14所述的显示面板，其中，所述过渡区域的像素密度等于所述副显示区域的像素密度，所述正常显示区域的像素密度大于所述副显示区域的像素密度。
  22. 根据权利要求14所述的显示面板，其中，所述副显示区域的所述发光器件在所述衬底基板上的正投影的面积小于所述过渡区域的所述发光器件在所述衬底基板上的正投影的面积。
  23. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    第四连接导线，连接于最靠近所述主显示区域的所述发光器件与最靠近所述副显示区域的所述像素电路之间，所述第四连接导线被设于所述像素电路的源漏极层。
  24. 一种显示装置，其中，包括：
    显示面板，是权利要求1～23任意一项所述的显示面板；
    感光传感器，设于所述显示面板的非显示面，并且所述感光传感器在所述显示面上的正投影与所述副显示区域至少部分交叠。
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