WO2021227040A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2021227040A1
WO2021227040A1 PCT/CN2020/090586 CN2020090586W WO2021227040A1 WO 2021227040 A1 WO2021227040 A1 WO 2021227040A1 CN 2020090586 W CN2020090586 W CN 2020090586W WO 2021227040 A1 WO2021227040 A1 WO 2021227040A1
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WIPO (PCT)
Prior art keywords
layer
area
substrate
light
driving structure
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PCT/CN2020/090586
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English (en)
French (fr)
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WO2021227040A9 (zh
Inventor
李蒙
李永谦
许晨
张大成
王景泉
袁志东
徐海侠
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/090586 priority Critical patent/WO2021227040A1/zh
Priority to CN202080000752.1A priority patent/CN113950747A/zh
Priority to EP20900761.6A priority patent/EP3993055B1/en
Priority to US17/270,414 priority patent/US20220123073A1/en
Publication of WO2021227040A1 publication Critical patent/WO2021227040A1/zh
Publication of WO2021227040A9 publication Critical patent/WO2021227040A9/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate, a preparation method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • PM Passive Matrix
  • AM Active Matrix
  • AMOLED is a current drive device that uses independent thin film transistors. (Thin Film Transistor, TFT for short) controls each sub-pixel, and each sub-pixel can continuously and independently drive to emit light.
  • Transparent display is an important personalized display field of display technology. It refers to the display of images in a transparent state. The viewer can not only see the image in the display device, but also see the scene behind the display device, which can realize virtual reality ( Virtual Reality, VR for short) and Augmented Reality (AR for short) and 3D display functions.
  • a transparent display device using AMOLED technology usually divides each pixel into a display area and a transparent area. The display area is provided with a pixel drive circuit and a light-emitting element to realize image display, and the transparent area realizes light transmission.
  • the present disclosure provides a display substrate including a substrate and a plurality of display units arranged on the substrate; the display unit includes: a display area and a transparent area; the display unit includes: Display area, and a driving structure layer, a light emitting structure layer, and a color filter layer arranged on the substrate in sequence; the light emitting structure layer includes: a plurality of light emitting structures; each light emitting structure includes: a pixel definition layer, a first electrode , An organic light-emitting layer and a second electrode; the organic light-emitting layer is located in the opening area of the pixel definition layer and on the pixel definition layer; the color filter layer includes: a plurality of filters;
  • the display substrate includes: an interval area located in the display area, the interval area is located between the opening areas of the pixel definition layers of adjacent light-emitting structures, and the orthographic projection of the interval area on the substrate and the pixel There is an overlap area in the orthographic projection of the definition layer on the substrate;
  • the orthographic projections of adjacent filters on the substrate have overlapping regions; the orthographic projections of the overlapping regions of adjacent filters on the substrate and the spacer regions on the substrate have overlapping regions.
  • the multiple light-emitting structures include: a first light-emitting structure, a second light-emitting structure, a third light-emitting structure, and a fourth light-emitting structure; Arranged in a direction, the third light-emitting structure and the fourth light-emitting structure are arranged in a first direction; the first light-emitting structure and the third light-emitting structure are arranged in a second direction, and the second light-emitting structure And the fourth light emitting structure is arranged along the second direction;
  • the multiple filters include: a first color filter, a second color filter, and a third color filter; the three color filters are respectively arranged on three of the four light emitting structures;
  • the first direction is an arrangement direction of the transparent area and the display area in a display unit; the second direction is perpendicular to the first direction, and the first color and the second color And the third color is one of red, blue, and green, and the three colors are different from each other.
  • the drive structure layer includes: a plurality of first scan lines and second scan lines extending in a first direction, a plurality of first power lines and second power lines extending in a second direction , The data line and the compensation line and the first driving structure, the second driving structure, the third driving structure and the fourth driving structure arranged along the first direction;
  • the first driving structure is located on a side of the second driving structure close to the transparent area, and the fourth driving structure is located on a side of the third driving structure away from the transparent area;
  • the first power line is located on the side of the fourth drive structure away from the third drive structure;
  • the second power line is located on the side of the first drive structure away from the second drive structure;
  • the The compensation line is located between the second driving structure and the third driving structure;
  • the data line includes: a first data line, a second data line, a third data line, and a fourth data line;
  • the first data line is connected to the first driving structure and is located on a side of the first driving structure close to the second driving structure;
  • the second data line is connected to the second driving structure, and Located on the side of the second driving structure close to the first driving structure;
  • the third data line is connected to the third driving structure and is located on a side of the third driving structure close to the fourth driving structure Side;
  • the fourth data line is connected to the fourth drive structure, and is located on the side of the fourth drive structure close to the third drive structure;
  • the first scan line and the second scan line are respectively located on both sides of the driving structure layer;
  • the length of the first power line along the first direction is greater than the length of the compensation line or the data line along the first direction
  • the length of the second power line along the first direction is greater than the length of the compensation line or the data line The length of the line along the first direction.
  • the first drive structure and the fourth drive structure are mirror-symmetrical with respect to the compensation line, and the second drive structure and the third drive structure are mirrored with respect to the compensation line. symmetry.
  • each drive structure includes: a pixel drive circuit, the pixel drive circuit includes: a first transistor, a second transistor, a third transistor, and a storage capacitor; the second transistor is a drive transistor;
  • the storage capacitor includes: a first electrode plate, a second electrode plate and a third electrode plate;
  • the gate electrode of the first transistor is connected to the first scan line, the first electrode of the first transistor is connected to the data line, and the second electrode of the first transistor is connected to the gate of the second transistor.
  • the first electrode of the second transistor is connected to the first power line, the second electrode of the second transistor is connected to the first electrode of the light-emitting structure, and the gate electrode of the third transistor is connected to the
  • the second scan line is connected, the first electrode of the third transistor is connected to the compensation line through a compensation connection line, the second electrode of the third transistor is connected to the second electrode of the second transistor, and the light emitting
  • the second electrode of the structure is connected to the second power line; the first electrode plate and the third electrode plate are connected to the second electrode of the second transistor, and the second electrode plate is connected to the second electrode of the second transistor.
  • the driving structure layer further includes: a power connection line, an auxiliary power line, and a compensation connection line;
  • the first pole of the second transistor is connected to the first power line through the power connection line;
  • the power connection line is arranged in the same layer as the first scan line and the second scan line, and the first power source
  • the wire is connected to the power connection wire through a via hole, and a double-layer wiring is formed between the gate electrode of the first transistor and the gate electrode of the third transistor;
  • the auxiliary power line is provided in the same layer as the first scan line and the second scan line, the second power line is connected to the auxiliary power line through a via hole, and the gate electrode of the first transistor is connected to the A double-layer wiring is formed between the gate electrodes of the third transistor;
  • the compensation connection line is provided on the same layer as the first electrode plate, and the compensation connection line is connected to the compensation line through a via hole.
  • the drive structure layer includes: a first metal layer, a first insulating layer, a metal oxide layer, a second insulating layer, a second metal layer, a third insulating layer, The third metal layer, the fourth insulating layer and the flat layer;
  • the first metal layer includes a first electrode plate and a compensation connection line
  • the metal oxide layer includes a second electrode plate and active layers of all transistors
  • the second metal layer includes a first scan line and a second scan line. Wires, power connection wires, auxiliary power wires, and gate electrodes of all transistors.
  • the third metal layer includes: the first power wire, the second power wire, the compensation wire, the data wire, the third plate and the source and drain of all transistors Pole; the flat layer is provided with a via hole exposing the second pole of the second transistor;
  • the orthographic projection of the first electrode plate on the substrate covers the active layers of the first transistor and the second transistor, and the second electrode plate is on the substrate. Orthographic projection on the bottom;
  • the length of the first electrode plate in the second direction is greater than the distance between the gate electrode of the first transistor and the gate electrode of the third transistor.
  • the second plate in the second drive structure and the third drive structure are provided with openings; the opening of the second plate in the second drive structure is provided in the second drive structure.
  • the driving structure is close to the side of the third driving structure, and the opening of the second plate of the third driving structure is arranged on the side of the third driving structure close to the second driving structure;
  • the flat layer vias in the first driving structure and the fourth driving structure are located between the third transistor and the second plate; the flat layer vias in the first driving structure are connected to the The vias of the flat layer in the fourth driving structure are mirror-symmetrical with respect to the compensation line;
  • the flat layer via of the second drive structure is located in the opening of the second plate of the second drive structure, and the flat layer via of the third drive structure is located on the second plate of the third drive structure In the opening; the flat layer via in the second driving structure and the flat layer via in the third driving structure are mirror-symmetrical with respect to the compensation line;
  • the angle between the arrangement direction of the flat layer vias in the first driving structure and the flat layer vias in the second driving structure and the first direction is greater than 0 degrees and less than 90 degrees.
  • the first electrode of the first light-emitting structure is connected to the first driving structure through a planar layer via hole in the first driving structure, and the first electrode of the second light-emitting structure is connected to the first driving structure through a fourth driving structure.
  • the flat layer via in the structure is connected to the fourth driving structure, the first electrode of the third light emitting structure is connected to the second driving structure through the flat layer via in the second driving structure, and the fourth light emitting structure is connected to the second driving structure.
  • An electrode is connected to the third driving structure through a flat layer via in the third driving structure;
  • the opening area of the pixel definition layer of the first light-emitting structure and the opening area of the pixel definition layer of the third light-emitting structure are located between the first power line and the compensation line, and are on the substrate There is an overlap area between the orthographic projection and the orthographic projection of the first driving structure and the second driving structure on the substrate;
  • the opening area of the pixel defining layer of the second light-emitting structure and the opening area of the pixel defining layer of the fourth light-emitting structure are located between the compensation line and the second power line, and are projected onto the substrate There is an overlap area with the orthographic projection of the third driving structure and the fourth driving structure on the substrate.
  • the orthographic projection of the flat layer via hole of the first driving structure on the substrate and the orthographic projection of the opening area of the pixel definition layer in the first light-emitting structure on the substrate There is no overlapping area;
  • the interval area includes a first interval area, a second interval area, and a third interval area
  • the first interval area is located between the opening area of the pixel definition layer of the first light-emitting structure and the opening area of the pixel definition layer of the third light-emitting structure; the second interval area is located in the second light-emitting structure Between the opening area of the pixel definition layer of the fourth light-emitting structure and the opening area of the pixel definition layer of the fourth light-emitting structure; the first interval area and the second interval area are arranged along a first direction;
  • the first spacing area and the second spacing area are respectively located on both sides of the third spacing area, and the orthographic projection of the third spacing area on the substrate is different from the orthographic projection of the third spacing area on the substrate.
  • the orthographic projections of the compensation lines between the second scan lines on the substrate coincide;
  • the third interval area includes: a first sub-interval area, a second sub-interval area, and a third sub-interval area that are sequentially arranged along the second direction and are connected end to end; the second sub-interval area is located in the first sub-interval area. Between a sub-interval area and a third sub-interval area;
  • the first sub-interval area is located between the opening area of the pixel defining layer of the first light-emitting structure and the opening area of the pixel defining layer of the second light-emitting structure; the third sub-interval area is located in the third light-emitting structure Between the opening area of the pixel definition layer of the fourth light-emitting structure and the opening area of the pixel definition layer of the fourth light-emitting structure;
  • the second sub-interval area is located between the first space area and the second space area, and is arranged along the first direction with the first space area and the second space area.
  • the orthographic projection of the filter on the substrate covers the opening area and the second pixel definition layer of the first light-emitting structure.
  • the orthographic projection of the filter on the substrate covers the opening area of the pixel definition layer of the second light-emitting structure, the second spacer area, and the The orthographic projection of the first sub-interval area and the second sub-interval area on the substrate, and there is an overlap area with the orthographic projection of part of the second scan line and part of the first power line in the display area on the substrate;
  • the orthographic projection of the filter on the substrate covers the orthographic projection of the opening area of the pixel definition layer of the third light-emitting structure on the substrate, and is consistent with There is an overlap area in the orthographic projections of part of the first interval area, part of the third sub-interval area, part of the first scan line in the display area, and part of the second power line on the substrate;
  • the orthographic projection of the filter on the substrate covers the orthographic projection of the opening area of the pixel definition layer of the fourth light-emitting structure on the substrate, and is consistent with There is an overlap area in the orthographic projections of part of the second interval area, part of the third sub-interval area, part of the first scan line in the display area, and part of the first power line on the substrate.
  • the display substrate further includes: a shielding layer
  • the shielding layer includes: a first shielding layer and a second shielding layer; the second shielding layer is located on a side of the first shielding layer close to the substrate;
  • the first shielding layer is arranged in the same layer as one of the color filters in the plurality of filters, and the second shielding layer is in the same layer as the other color filter in the plurality of filters set up.
  • the present disclosure also provides a method for manufacturing a display substrate for manufacturing the above-mentioned display substrate, and the method includes:
  • a display unit including a display area and a transparent area is formed on a substrate to form a display substrate;
  • the display unit includes: a driving structure layer, a light emitting structure layer, and a light emitting structure layer located in the display area and sequentially disposed on the substrate
  • the light-emitting structure layer includes: a plurality of light-emitting structures; each light-emitting structure includes: a pixel definition layer, a first electrode, an organic light-emitting layer and a second electrode; the organic light-emitting layer is located in the opening area of the pixel definition layer and On the pixel defining layer;
  • the display substrate includes: an interval area located in the display area, the interval area being located between the opening areas of the pixel defining layer of adjacent light-emitting structures, and on the substrate with the pixel defining layer
  • the color film layer includes: a plurality of filters; the orthographic projection of adjacent filters on
  • the forming a display unit including a display area and a transparent area on the substrate includes:
  • a metal oxide layer including a second electrode plate in the display area is formed on the first insulating layer, and the orthographic projection of the second electrode plate on the substrate is the same as that of the first electrode plate on the substrate There is an overlap area in the orthographic projection of, to form the first storage capacitor;
  • the second metal layer includes: a first scan line and a second scan line;
  • a third metal layer located in the display area is formed on the third insulating layer.
  • the third metal layer includes a first power line, a second power line, a compensation line, a data line, and a third electrode plate. There is an overlap area between the orthographic projection of the electrode plate on the substrate and the orthographic projection of the second electrode plate on the substrate to form a second storage capacitor, and the third electrode plate is connected to the first electrode plate through a via;
  • a color film layer is formed on the packaging layer.
  • the forming a color filter layer on the encapsulation layer includes:
  • a color film layer and a shielding layer are formed on the packaging layer;
  • the present disclosure also provides a display device including the above-mentioned display substrate.
  • FIG. 1A is a first top view of a display substrate provided by an embodiment of the disclosure.
  • FIG. 1B is a second top view of a display substrate provided by an embodiment of the disclosure.
  • Figure 2 is a cross-sectional view of Figure 1B along the B-B direction;
  • FIG. 3 is a third top view of a display substrate provided by an embodiment of the disclosure.
  • FIG. 4 is an equivalent circuit diagram of a pixel driving circuit provided by an exemplary embodiment
  • 5A is a schematic diagram after forming the first metal layer
  • Fig. 5B is a cross-sectional view taken along the line A-A in Fig. 5A;
  • Figure 5C is a cross-sectional view taken along the line B-B in Figure 5A;
  • 6A is a schematic diagram after forming a metal oxide layer
  • Fig. 6B is a cross-sectional view taken along the line A-A in Fig. 6A;
  • Figure 6C is a cross-sectional view taken along the line B-B in Figure 6A;
  • FIG. 7A is a schematic diagram after forming a second metal layer
  • Fig. 7B is a sectional view taken along the line A-A in Fig. 7A;
  • Figure 7C is a cross-sectional view taken along the line B-B in Figure 7A;
  • FIG. 8A is a schematic diagram of forming a third insulating layer
  • Fig. 8B is a sectional view taken along the line A-A in Fig. 8A;
  • Figure 8C is a cross-sectional view taken along the line B-B in Figure 8A;
  • FIG. 9A is a schematic diagram of forming a third metal layer
  • Fig. 9B is a sectional view taken along the line A-A in Fig. 9A;
  • Figure 9C is a cross-sectional view taken along the line B-B in Figure 9A;
  • 10A is a schematic diagram after forming a fourth insulating layer and a flat layer
  • Fig. 10B is a sectional view taken along the line A-A in Fig. 10A;
  • Figure 10C is a cross-sectional view taken along the line B-B in Figure 10A;
  • FIG. 11A is a schematic diagram after forming a transparent conductive layer in the present disclosure.
  • Fig. 11B is a sectional view taken along the line A-A in Fig. 11A;
  • FIG. 12A is a schematic diagram after forming a pixel definition layer
  • Figure 12B is a cross-sectional view taken along the line A-A in Figure 12A;
  • Figure 12C is a cross-sectional view taken along the line B-B in Figure 12A;
  • FIG. 13 is a schematic diagram after forming an organic light-emitting layer
  • Figure 14A is a schematic diagram after forming a cathode
  • Fig. 14B is a sectional view taken along the line A-A in Fig. 14A;
  • Figure 14C is a cross-sectional view taken along the line B-B in Figure 14A;
  • Fig. 15 is a schematic diagram after forming an encapsulation layer.
  • connection should be interpreted broadly. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate piece, or internal communication between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged.
  • electrical connection includes the case where constituent elements are connected together by elements having a certain electrical function.
  • An element having a certain electrical function is not particularly limited as long as it can transmit and receive electrical signals between connected constituent elements.
  • elements having a certain electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore, it also includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore, also includes a state where an angle of 85° or more and 95° or less is included.
  • film and “layer” can be interchanged.
  • the “conductive layer” can be replaced by the “conductive film.”
  • the “insulating film” can sometimes be replaced with an “insulating layer.”
  • the metal covered by the pixel definition layer located between adjacent light-emitting structures because the pixel definition layer is a transparent material, the metal reflection phenomenon occurs, which reduces the display effect of the transparent display substrate.
  • FIG. 1A is a first top view of a display substrate provided by an embodiment of the present disclosure
  • FIG. 1B is a second top view of a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a cross-sectional view of FIG. 1B along the direction B-B.
  • the display substrate provided by the embodiment of the present disclosure includes: a substrate 10 and a plurality of display units arranged on the substrate 10.
  • the display unit includes: a display area 100 and a transparent area 200; the display unit includes: a driving structure layer, a light emitting structure layer, and a color film layer located in the display area 100 and sequentially disposed on a substrate; the light emitting structure layer includes: a plurality of light emitting structures Each light-emitting structure includes: a pixel defining layer 71, a first electrode, an organic light-emitting layer and a second electrode; the organic light-emitting layer is located on the opening area of the pixel defining layer and the pixel defining layer 71, the color film layer 20 includes: a plurality of filters Light film.
  • the display substrate 1 includes a spacer area A (the dotted area in FIG. 1) located in the display area, the spacer area A is located between the opening areas of the pixel definition layers of adjacent light-emitting structures, and the spacer area A is in the liner. There is an overlap area between the orthographic projection on the bottom and the orthographic projection of the pixel definition layer 71 on the substrate.
  • the orthographic projections of adjacent filters on the substrate have overlapping areas; the orthographic projections of the overlapping areas of adjacent filters on the substrate and the spacing areas on the substrate have overlapping areas.
  • the multiple filters include: the first color, the second color, and the third color are one of red, blue, and green, and the three colors are different from each other.
  • the first color can be red, the second color can be blue, the third color can be green, or the first color can be red, the second color can be green, the third color can be blue, or the first color It can be blue, the second color can be red, the third color can be green, or the first color can be blue, the second color can be green, the third color can be red, or the first color can be green ,
  • the second color can be red, the third color can be blue, or the first color can be green, the second color can be blue, and the third color can be red.
  • the display area is configured to achieve image display, and the transparent area is configured to achieve light transmission, thereby achieving image display in a transparent state, that is, transparent display.
  • the substrate 10 may be a rigid substrate or a flexible substrate, where the rigid substrate may be, but is not limited to, one or more of glass and metal sheet; the flexible substrate may be But not limited to polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, One or more of polyvinyl chloride, polyethylene, and textile fibers.
  • the plurality of light emitting structures includes: a first light emitting structure, a second light emitting structure, a third light emitting structure, and a fourth light emitting structure; the first light emitting structure and the second light emitting structure Arranged along the first direction, the third light emitting structure and the fourth light emitting structure are arranged along the first direction; the first light emitting structure and the third light emitting structure are arranged along the second direction, and the second light emitting structure and the fourth light emitting structure are arranged along the first direction. Arranged in two directions.
  • the first direction is the arrangement direction of the transparent area 200 and the display area 100 in a display unit, and the second direction is perpendicular to the first direction.
  • FIG. 1B illustrates an example in which the first color filter is located on the first light-emitting structure, the second color filter is located on the third light-emitting structure, and the third color filter is located on the fourth light-emitting structure.
  • the overlapping and adjacent optical filters can play a role in shielding the light reflected by the metal located in the spaced area, can reduce the metal reflection phenomenon, and improve the display effect of the display substrate.
  • the area B located in the display area may be used to form an auxiliary electrode connected to the second electrode of the light emitting structure layer to provide a low-level signal to the second electrode.
  • the display substrate provided by the embodiment of the present disclosure includes a display substrate and a second substrate disposed oppositely, the display substrate includes: a substrate and a plurality of display units disposed on the substrate; the display unit includes: a display area and a transparent area; the display unit includes : A driving structure layer, a light emitting structure layer and a color filter layer located in the display area and sequentially arranged on the substrate; the light emitting structure layer includes: a plurality of light emitting structures; each light emitting structure includes: a pixel definition layer, a first electrode, and an organic The light-emitting layer and the second electrode; the organic light-emitting layer is located in the opening area of the pixel definition layer and on the pixel definition layer; the color film layer includes: a plurality of filters; Between the opening areas of the pixel definition layer adjacent to the light-emitting structure, and there is an overlap area between the orthographic projection of the spacer area on the substrate and the orthographic projection of the pixel definition layer on the substrate; the orthographic projection of adjacent
  • FIG. 3 is a third top view of the display substrate provided by an embodiment of the disclosure.
  • the driving structure layer in each display unit includes: a plurality of first scan lines Gn and second scan lines Sn extending in a first direction, and a plurality of first power supply lines VDD extending in a second direction.
  • the first power line VDD, the second power line VSS, Dn, and the compensation line Se, and the first driving structure P1, the second driving structure P2, the third driving structure P3, and the fourth driving structure P4 Located in the display area.
  • the first driving structure P1 is located on the side of the second driving structure P2 close to the transparent area 200, and the fourth driving structure P4 is located on the side of the third driving structure P3 away from the transparent area 200.
  • Each driving structure includes a pixel driving circuit.
  • the pixel driving circuit is electrically connected to the light emitting structure.
  • the first scan line and the second scan line are used to define a display row, and the first power line and the second power line are used to define a display column.
  • the first power line VDD is located on the side of the fourth driving structure P4 away from the third driving structure P3; the second power line VSS is located on the side of the first driving structure P1 away from the second driving structure P2; the compensation line Se is located in the second driving structure Between P2 and the third driving structure P3.
  • the data line includes: a first data line, a second data line, a third data line, and a fourth data line.
  • the first data line is connected to the first driving structure and is located on the side of the first driving structure P1 close to the second driving structure P2.
  • the second data line is connected to the second driving structure P2 and is located on the side of the second driving structure P2 close to the first driving structure P1;
  • the third data line is connected to the third driving structure P3 and is located near the third driving structure P3.
  • One side of the four driving structure P4; the fourth data line is connected to the fourth driving structure P4, and is located on the side of the fourth driving structure P4 close to the third driving structure P3.
  • the first power line VDD, the second power line VSS, the compensation line Se, and the four data lines Dn are parallel to each other, and along the direction away from the transparent region 200, the second power line VSS, the two data lines
  • the line Dn, the compensation line Se, the two data lines Dn, and the first power line VDD are arranged in sequence, a driving structure is formed between the first power line VDD and the adjacent data line Dn, and the second power line VSS is connected to the adjacent data line.
  • a driving structure is formed between Dn, and two driving structures are respectively formed between the compensation line Se and the adjacent data line Dn.
  • four drive structures are formed between the first power line VDD and the second power line VSS by providing one compensation line Se and four data lines Dn, and two of the four data lines Dn are located between the compensation lines Se and Between the second power line VSS, the other two data lines Dn are located between the compensation line Se and the first power line VDD.
  • the length of the first power line VDD in the first direction is greater than the length of the compensation line Se or the data line Dn in the first direction
  • the length of the second power line VSS in the first direction is greater than the length of the compensation line Se or the data line Dn in the first direction.
  • the length can reduce the resistance of the first power supply line VDD and the second power supply line VSS.
  • the first scan line Gn and the second scan line Sn are respectively located on both sides of the driving structure layer.
  • the voltage of the first power line VDD may be set to be greater than the voltage of the second power line VSS, and the maximum voltage of the data signal transmitted by the data line Dn is less than the maximum voltage of the first scan line, and is also less than the first scan line.
  • the voltage of the power supply line VDD may be set to be greater than the voltage of the second power line VSS, and the maximum voltage of the data signal transmitted by the data line Dn is less than the maximum voltage of the first scan line, and is also less than the first scan line.
  • the first driving structure P1 and the fourth driving structure P4 are mirror-symmetrical with respect to the compensation line Se, and the second driving structure P2 and the third driving structure P3 are relative to the compensation line Se. Mirror symmetry.
  • FIG. 4 is an equivalent circuit diagram of a pixel driving circuit provided by an exemplary embodiment.
  • the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor C ST , and the light-emitting structure is an OLED.
  • the first transistor T1 is a switching transistor
  • the second transistor T2 is a driving transistor
  • the third transistor T3 is a compensation transistor.
  • the storage capacitor includes a first plate 41, a second plate 42 and a third plate 43.
  • the gate electrode of the first transistor T1 is connected to the first scan line Gn, the first electrode of the first transistor T1 is connected to the data line Dn, the second electrode of the first transistor T1 is connected to the gate electrode of the second transistor T2, and the first transistor T1 is used for Under the control of the first scan line Gn, the data signal transmitted by the data line Dn is received, so that the gate electrode of the second transistor T2 receives the data signal.
  • the gate electrode of the second transistor T2 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2 is connected to the first power line VDD, the second electrode of the second transistor T2 is connected to the first electrode of the OLED, and the second transistor T2 is used to generate a corresponding current in the second pole under the control of the data signal received by its gate electrode.
  • the gate electrode of the third transistor T3 is connected to the second scan line Sn, the first electrode of the third transistor T3 is connected to the compensation line Se, the second electrode of the third transistor T3 is connected to the second electrode of the second transistor T2, and the third transistor T3 is used for
  • the threshold voltage Vth and mobility of the second transistor T2 are extracted in response to the compensation timing to compensate the threshold voltage Vth.
  • the first electrode of the OLED is connected to the second electrode of the second transistor T2, and the second electrode of the OLED is connected to the second power line VSS.
  • the OLED is used for emitting light of corresponding brightness in response to the current of the second electrode of the second transistor T2.
  • the first storage capacitor C ST electrode of the second transistor T2 is connected to the gate electrode of the second storage capacitor C ST electrode of the second transistor T2 is connected to the second electrode, the storage capacitor C ST for storing the second gate transistor T2 The potential of the electrode.
  • the first electrode plate 41 and the third electrode plate 43 are connected through a via hole, so that the potential of the first electrode plate 41 and the third electrode plate 43 are the same, forming a first storage capacitor and a second storage capacitor in a parallel structure.
  • the driving structure layer further includes a plurality of connecting lines.
  • the multiple connection lines include at least a compensation connection line 51, a power connection line 52, and an auxiliary power supply line.
  • the compensation connection line 51 and the first electrode plate 41 are provided in the same layer, and the compensation connection line 51 is connected to the compensation line Se through a via hole.
  • the first pole of the second transistor is connected to the first power line VDD through the power connection line 52; the power connection line 52 is arranged in the same layer as the first scan line Gn and the second scan line Sn, A power line VDD is connected to the power connection line 52 through a via hole, and a double-layer wiring is formed between the gate electrode of the first transistor and the gate electrode of the third transistor. A double-layer wiring is formed between the gate electrode of the first transistor and the gate electrode of the third transistor to ensure the reliability of power signal transmission and reduce the resistance of the first power line VDD.
  • the auxiliary power line is provided in the same layer as the first scan line and the second scan line, the second power line is connected to the auxiliary power line through a via hole, and the gate electrode of the first transistor is connected to the third transistor.
  • a double-layer wiring is formed between the gate electrodes of the first transistor; a double-layer wiring is formed between the gate electrode of the first transistor and the gate electrode of the third transistor, which ensures the reliability of power signal transmission and reduces the second power line VSS The resistance.
  • the compensation connection line 51 is connected to the compensation line Se through the via hole, so that the compensation line Se provides compensation signals to the four driving structures through the compensation connection line 51, and the power connection line 52 is connected to the first power supply line VDD through the via hole, so that the first power supply
  • the line VDD provides power signals to the four sub-pixels through the power connection line 52 to form a one-to-four structure of the first power line VDD and the compensation line Se.
  • the first power line and the compensation line are designed as a one-to-four structure, which saves the number of signal lines, reduces the occupied space, has a simple structure, reasonable layout, makes full use of layout space, improves space utilization, and helps improve resolution and transparency.
  • the first electrode plate 41 is an elongated rectangle. Except for the position of the compensation connecting line 51, the first electrode plate 41 completely covers the pixel driving circuit in each driving structure.
  • the length of the first electrode plate 41 in the second direction is greater than the distance between the gate electrode of the first transistor and the gate electrode of the third transistor to be formed later, and the length of the first electrode plate 41 along the second direction
  • the length in the two directions is greater than the distance between the first electrode of the first transistor and the first electrode of the third transistor to be formed subsequently, which can realize effective shielding and prevent light from entering the active layer in all transistors.
  • the pixel driving circuit in each driving structure includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor.
  • the first transistor T1 includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode
  • the second transistor T2 includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode
  • the third transistor T3 includes a third active layer, a third gate electrode, a third source electrode, and a third drain electrode.
  • the storage capacitor includes a first plate 41, a second plate 42 and a third plate 43.
  • the first plate 41 and the second plate 42 form a first storage capacitor
  • the second plate 42 and the third plate 43 form a first storage capacitor
  • the potentials of the first plate 41 and the third plate 43 are the same, so the first storage capacitor and the second storage capacitor form a parallel structure, which effectively increases the storage capacity.
  • the first scan line Gn is connected to the first gate electrode of the first transistor T1 in each sub-pixel
  • the second scan line Sn is connected to the third gate electrode of the third transistor T3 in each sub-pixel.
  • the data line Dn is connected to the first source electrode of the first transistor T1 in each sub-pixel
  • the compensation connection line 51 is configured to connect the compensation line Se to the third source electrode of the third transistor T3 in each sub-pixel.
  • the power supply connection line 52 is configured to connect the first power supply line VDD with the second source electrode of the second transistor T2 in each sub-pixel.
  • the first gate electrode of the first transistor T1 is connected to the first scan line Gn
  • the first source electrode of the first transistor T1 is connected to the data line Dn
  • the first transistor T1 The first drain electrode is connected to the second gate electrode of the second transistor T2.
  • the second gate electrode of the second transistor T2 is connected to the first drain electrode of the first transistor T1, the second source electrode of the second transistor T2 is connected to the first power supply line VDD through the power connection line 52, and the second transistor T2 is connected to the first power supply line VDD.
  • the drain electrode is connected to the third drain electrode of the third transistor T3 and the anode of the light-emitting element.
  • the third gate electrode of the third transistor T3 is connected to the second scan line Sn, the third source electrode of the third transistor T3 is connected to the compensation line Se through the compensation connection line 51, and the third drain electrode of the third transistor T3 is connected to the second transistor
  • the second drain electrode of T2 is connected to the anode of the light-emitting element.
  • the first plate 41 is connected to the second drain electrode of the second transistor T2 and the third drain electrode of the third transistor T3, and the second plate 42 is connected to the first drain electrode of the first transistor T1 and the second drain electrode of the second transistor T2.
  • the gate electrode is connected, and the third electrode plate 43 is connected to the second drain electrode of the second transistor T2 and the third drain electrode of the third transistor T3.
  • the driving structure layer in a direction perpendicular to the display substrate, includes a first metal layer, a first insulating layer, a metal oxide layer, a second insulating layer, a second metal layer, The third insulating layer, the third metal layer, the fourth insulating layer and the flat layer.
  • the first metal layer includes a first electrode plate 41 as a shielding layer and a compensation connection line 51.
  • the first electrode plate 41 as a shielding layer and the compensation connection line 51 are arranged in the same layer and formed by the same patterning process.
  • the metal oxide layer includes the second electrode plate 42 and the active layer of each transistor.
  • the second electrode plate 42 and the active layer of each transistor are arranged in the same layer and formed by the same patterning process.
  • the second metal layer includes the first scan line Gn, the second scan line Sn, the power connection line 52 and the gate electrode of each transistor, the first scan line Gn, the second scan line Sn, the power connection line 52 and the gate electrode of each transistor It is arranged in the same layer and formed by the same patterning process.
  • the third metal layer includes a data line Dn, a compensation line Se, a first power line VDD, a second power line VSS, a third plate 43, and the source and drain electrodes of each transistor.
  • the data line Dn, the first power line VDD, The second power line VSS, the compensation line Se, the third plate 43, and the source electrode and the drain electrode of each transistor are arranged in the same layer, and are formed by the same patterning process.
  • the flat layer is provided with a via hole, the flat layer via hole V exposes the second electrode of the second transistor, and the first electrode in the light emitting structure layer is connected to the driving structure layer through the flat layer via hole.
  • the first transistor T1 and the second transistor T2 are located on the side of the second plate 42 close to the first scan line Gn, and the third transistor T3 is located on the second plate 42 close to the second scan line Sn. On the side.
  • An exemplary embodiment adopts a second electrode plate of metal oxide material as the electrode plate of the storage capacitor, and the second electrode plate is respectively connected to the first electrode plate in the first metal layer and the third electrode plate in the third metal layer.
  • the plate forms a storage capacitor.
  • the first electrode plate and the third electrode plate have the same potential, and the second electrode plate has a different potential than the first electrode plate and the third electrode plate. Therefore, the first electrode plate, the second electrode plate and the second electrode plate Two storage capacitors connected in parallel are formed between the tripolar plates, which effectively increases the capacity of the storage capacitor and is beneficial to realize high-resolution display.
  • the preparation process of the present disclosure can be realized by using existing mature preparation equipment, has little improvement to the existing process, can be well compatible with the existing preparation process, is simple to implement, easy to implement, high production efficiency, and low production cost. High yield rate.
  • the second electrode plate in the second driving structure and the third driving structure is provided with an opening; the opening of the second electrode plate of the second driving structure is arranged in the second driving structure close to the third driving structure On the side of the third driving structure, the opening of the second plate of the third driving structure is arranged on the side of the third driving structure close to the second driving structure.
  • the flat layer vias in the first driving structure and the fourth driving structure are located between the third transistor and the second plate; the flat layer vias in the first driving structure and the fourth driving structure are The flat layer vias in the structure are mirror-symmetrical with respect to the compensation line; the flat layer vias of the second driving structure are located in the openings of the second plate of the second driving structure, and the flat layer vias of the third driving structure are located in the third In the opening of the second plate of the driving structure; the flat layer via in the second driving structure and the flat layer via in the third driving structure are mirror-symmetrical with respect to the compensation line.
  • the angle between the arrangement direction of the flat layer vias in the first driving structure and the flat layer vias in the second driving structure and the first direction is greater than 0 degrees and less than 90 degrees .
  • the first electrode of the first light emitting structure is connected to the first driving structure through the planar layer via hole in the first driving structure, and the first electrode of the second light emitting structure is connected to the first driving structure through the fourth driving structure.
  • the flat layer via is connected to the fourth driving structure, the first electrode of the third light emitting structure is connected to the second driving structure through the flat layer via in the second driving structure, and the first electrode of the fourth light emitting structure is connected through the third driving structure
  • the flat layer vias in are connected to the third driving structure.
  • the opening area 711 of the pixel definition layer of the first light-emitting structure and the opening area 713 of the pixel definition layer of the third light-emitting structure are located between the second power line VSS and the compensation line Se, and the orthographic projection on the substrate and the first driving
  • the orthographic projection of the structure and the second driving structure on the substrate has an overlapping area.
  • the opening area 712 of the pixel defining layer of the second light-emitting structure and the opening area 714 of the pixel defining layer of the fourth light-emitting structure are located between the compensation line Se and the first power line VDD, and the orthographic projection on the substrate and the third driving
  • the orthographic projection of the structure and the fourth driving structure on the substrate has an overlapping area.
  • the transparent region includes a first insulating layer, a third insulating layer, a fourth insulating layer, and a flat layer stacked on a substrate.
  • the interval area includes a first interval area A1, a second interval area A2, and a third interval area.
  • the first spacer area A1 is located between the opening area of the pixel definition layer of the first light emitting structure and the opening area of the pixel definition layer of the third light emitting structure;
  • the second spacer area A2 is located between the opening area of the pixel definition layer of the second light emitting structure and Between the opening regions of the pixel definition layer of the fourth light-emitting structure; the first spacer region and the second spacer region are arranged along the first direction.
  • the first interval area and the second interval area are respectively located on both sides of the third interval area, the orthographic projection of the third interval area on the substrate and the compensation line between the first scan line and the second scan line are on the substrate The orthographic projections coincide.
  • the third interval area includes: a first sub-interval area A31, a second sub-interval area A32, and a third sub-interval area A31, a second sub-interval area A32, and a third sub-interval area that are sequentially arranged along the second direction and are connected end to end.
  • Sub-interval area A33; the second sub-interval area A32 is located between the first sub-interval area A31 and the third sub-interval area A33.
  • the first sub-interval area A31 is located between the opening area of the pixel defining layer of the first light-emitting structure and the opening area of the pixel defining layer of the second light-emitting structure; the third sub-interval area A33 is located at the opening of the pixel defining layer of the third light-emitting structure Between the area and the opening area of the pixel definition layer of the fourth light-emitting structure.
  • the second sub-interval area A32 is located between the first space area A1 and the second space area A2, and is arranged along the first direction with the first space area A1 and the second space area A2.
  • the orthographic projection of the filter on the substrate covers the opening area of the pixel definition layer of the first light-emitting structure,
  • the orthographic projections of the first sub-interval area and the second sub-interval area on the substrate are overlapped with the orthographic projections of part of the second scan line and part of the second power line in the display area on the substrate.
  • the orthographic projection of the filter on the substrate covers the opening area of the pixel definition layer of the second light-emitting structure,
  • the orthographic projections of the second interval area, the first sub-interval area, and the second sub-interval area on the substrate overlap with the orthographic projections of part of the second scan line and part of the first power line in the display area on the substrate area;
  • the orthographic projection of the filter on the substrate covers the opening area of the pixel definition layer of the third light-emitting structure.
  • the orthographic projection of the filter on the substrate covers the opening area of the pixel definition layer of the fourth light-emitting structure.
  • the orthographic projection on the substrate has an overlapping area with the orthographic projection of part of the second spacing area, part of the third sub-interval area, part of the first scan line in the display area, and part of the first power line on the substrate.
  • the display substrate further includes: a shielding layer 30.
  • a shielding layer 30 There is an overlap area between the orthographic projection of the shielding layer 30 on the substrate and the orthographic projection of the first scan line Gn located in the transparent area and the second scan line Sn located in the transparent area and part of the display area on the substrate.
  • the shielding layer 30 includes: a first shielding layer and a second shielding layer; the first shielding layer is located on a side of the second shielding layer close to the substrate, the first shielding layer and a plurality of filters One of the color filters is arranged in the same layer, and the second shielding layer is arranged in the same layer as the other color filters of the plurality of filters, which can simplify the manufacturing process of the display substrate.
  • the structure of the display substrate provided by an exemplary embodiment will be described below through the preparation process of the display substrate.
  • the "patterning process” includes the process of depositing a film, coating photoresist, mask exposure, developing, etching and stripping photoresist.
  • the deposition can be any one or more of sputtering, evaporation and chemical vapor deposition
  • the coating can be any one or more of spraying and spin coating
  • the etching can be any of dry etching and wet etching.
  • Thin film refers to a layer of thin film made by depositing or coating a certain material on a substrate.
  • the "film” does not require a patterning process during the entire production process, the “film” can also be referred to as a "layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process.
  • “A and B are arranged in the same layer” means that A and B are formed at the same time through the same patterning process.
  • FIGS. 5 to 15 are schematic diagrams of a display substrate preparation process provided by an exemplary embodiment, illustrating the layout structure of a display unit of a top-emitting OLED display substrate.
  • Each display unit includes a display area 100 and a transparent area 200.
  • the driving structure layer of 100 includes four driving structures P1 to P4.
  • the pixel driving circuit of each driving structure includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor.
  • Forming the first metal layer includes: depositing a first metal film on a substrate, patterning the first metal film through a patterning process, and forming a first metal layer in the display area 100 on the substrate 10.
  • the first metal layer includes a first electrode plate 41 and a compensation connection line 51.
  • Each driving structure forms a first electrode plate 41, as shown in FIG. Sectional view of direction BB in 5A.
  • the first plate 41 is used as a plate of the first storage capacitor to form a first storage capacitor with the second plate formed subsequently, and as a shielding layer, it is configured to
  • the active layer is subjected to light-shielding treatment to reduce the intensity of light irradiated on the transistor and reduce leakage current, thereby reducing the influence of light on the characteristics of the transistor.
  • the compensation connection line 51 is a strip structure that spans 4 sub-pixels.
  • the compensation connection line 51 is configured to be connected to a compensation line formed subsequently, so that the compensation line provides a compensation signal to the driving structure.
  • the first metal layer in the first driving structure P1 and the first metal layer in the fourth driving structure P4 are mirror-symmetrical with respect to the vertical axis
  • the first metal layer in the third driving structure P3 is mirror-symmetrical with respect to the vertical axis.
  • the vertical axis is the center line of the second drive structure and the third drive structure.
  • Forming a metal oxide layer includes: depositing a first insulating film on a substrate on which a first metal layer is formed, and patterning the first insulating film through a patterning process to form a layer covering the first metal layer and located In the first insulating layer 61 in the display area and the transparent area, a metal oxide film is deposited on the first insulating layer 61, and the metal oxide film is patterned through a patterning process to form a metal oxide layer in the display area.
  • the metal oxide layer includes a first active layer 11, a second active layer 21, a third active layer 31, and a second electrode plate 42 provided in each driving structure.
  • FIG. 6B is a cross-sectional view in the direction of A-A in FIG. 6A
  • FIG. 6C is a cross-sectional view in the direction of B-B in FIG. 6A.
  • the first active layer 11 serves as the active layer of the first transistor
  • the second active layer 21 serves as the active layer of the second transistor
  • the third active layer 31 serves as the active layer of the third transistor
  • the second plate 42 There is an overlap area between the orthographic projection on the substrate 10 and the orthographic projection of the first electrode plate 41 on the substrate 10, and the first electrode plate 41 and the second electrode plate 42 form a first storage capacitor.
  • the second plate 42 serves as a plate of the first storage capacitor and a plate of the second storage capacitor.
  • the second plate 42 is configured to form a second storage capacitor with a third plate formed subsequently.
  • the orthographic projection of the first active layer 11, the second active layer 21, and the third active layer 31 on the substrate 10 and the orthographic projection of the first plate 41 on the substrate 10 exist. Overlap area, so that the first electrode plate 41 as a shielding layer can shield the channel area of the first transistor, the second transistor and the third transistor to avoid the influence of light on the channel and avoid the influence of the channel due to the generation of photo-generated leakage display effect.
  • the orthographic projection of the first active layer 11, the second active layer 21, and the third active layer 31 on the substrate 10 is spaced apart from the orthographic projection of the second electrode plate 42 on the substrate 10, that is, the first active layer There is no overlapping area between the layer 11 and the second electrode plate 42, between the second active layer 21 and the second electrode plate 42, and between the third active layer 31 and the second electrode plate 42, which is beneficial to meet relevant requirements. Design the channel width to length ratio of the first transistor, the second transistor, and the third transistor.
  • the third active layer 31 is located on the side of the second electrode plate 42 close to the compensation connection line 51, and the first active layer 11 and the second active layer 21 are located on the side of the second electrode plate 42 away from the compensation connection line 51.
  • the two active layers 21 are located on the side of the first active layer 11 close to the compensation connection line 51.
  • the metal oxide layer in the first driving structure P1 and the metal oxide layer in the fourth driving structure P4 are mirror-symmetrical with respect to the vertical axis, and the metal oxide layer in the second driving structure P2 With the metal oxide layer in the third driving structure P3 in mirror symmetry with respect to the vertical axis, there is a gap between the second electrode plate 42 and the third active layer 31 in the first driving structure P1 and the fourth driving structure P4, and the first An opening is provided in the middle of the second plate 42 of the second driving structure P2 and the third driving structure P3.
  • Forming the second metal layer includes: depositing a second insulating film on a substrate formed with a metal oxide, and patterning the second insulating film through a patterning process to form a second insulating layer 62 in the display area.
  • a second metal film is deposited on the second insulating layer 62, and the second metal film is patterned through a patterning process to form a second metal layer.
  • the second metal layer includes the first scan line Gn, the second scan line Sn, the power connection line 52 and the auxiliary power line 53 formed in each display unit, and the first gate electrode 12 and the second gate electrode 12 formed in each driving structure.
  • the second gate electrode 22 and the third gate electrode 32 are as shown in FIG. 7A.
  • FIG. 7B is a cross-sectional view in the AA direction in FIG. 7A
  • FIG. 7C is a cross-sectional view in the BB direction in FIG. 7A.
  • the first scan line Gn and the second scan line Sn are arranged in parallel, and both extend along the first direction.
  • the first scan line Gn and the second scan line Sn are located on both sides of the driving structure layer.
  • the first scan line Gn is located on the side of the driving structure layer close to the first transistor, and the second scan line Sn is located on the side of the driving structure layer close to the third transistor.
  • the first gate electrode 12 is an integral structure connected to the first scan line Gn, and is arranged across the first active layer 11.
  • the second gate electrode 22 straddles the second active layer 21 and the second electrode plate 42.
  • the third gate electrode 32 is an integral structure connected to the second scan line Sn, and straddles the third active layer 31.
  • the power connection line 52 includes a first connection bar perpendicular to the first scan line Gn and a second connection bar parallel to the first scan line Gn. Connect one end to each other.
  • the first connecting bar is formed in the area where the first power line VDD is located in the display unit, and is configured to connect to the first power line VDD formed subsequently, and the second connecting bar is arranged across 4 driving structures and is configured to provide each driving structure with High level signal.
  • the auxiliary power line 53 is formed in the area where the second power line VSS is located in the display unit, is perpendicular to the first scan line Gn, and is configured to be connected to the second power line VSS formed subsequently.
  • the second insulating layer 62 is the same as the second metal layer, that is, the second insulating layer 62 is located under the second metal layer, and there is no second insulating layer 62 in the area outside the second metal layer.
  • the second metal layer in the first driving structure P1 and the second metal layer in the fourth driving structure P4 are mirror-symmetrical with respect to the vertical axis, and the second metal layer in the second driving structure P2 is mirror-symmetrical with respect to the vertical axis.
  • the second metal layer in the third driving structure P3 is mirror-symmetrical with respect to the vertical axis.
  • this process further includes conductive treatment.
  • Conduction treatment is to use the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 as a shield to perform plasma treatment on the metal oxide layer after the second metal layer is formed.
  • the metal oxide layer in the shielding area of the second gate electrode 22 and the third gate electrode 32 serves as the channel region of the transistor
  • the metal oxide layer in the area not covered by the second metal layer is processed into a conductive layer to form a conductive second electrode plate 42 and a conductive source and drain region.
  • a third insulating layer is formed.
  • Forming the third insulating layer includes depositing a third insulating film on the substrate on which the second metal layer is formed, and patterning the third insulating film through a patterning process to form the third insulating layer 63 in the display area and the transparent area.
  • a plurality of via holes are opened on the third insulating layer 63, and the plurality of via holes include: a first via hole V1 and a second via hole V2 located on both sides of the first gate electrode 12, and a first via hole V2 located on both sides of the second gate electrode 22; Three vias V3 and fourth vias V4, fifth vias V5 and sixth vias V6 located on both sides of the third gate electrode 32, seventh vias V7 and eighth vias located at the position of the compensation connecting line 51 V8, the ninth via hole V9 located in the overlapping area of the second gate electrode 22 and the second plate 42, the tenth via hole V10 located at the position of the first plate 41, located at the position of the first connection bar of the power connection line 52
  • the multiple eleventh vias V11, the multiple twelfth vias V12 at the location of the auxiliary power line 53, as shown in FIG. 8A, FIG. 8B is a cross-sectional view along the AA direction in FIG. Section BB in the middle.
  • the first via hole V1 and the second via hole V2 expose the surfaces at both ends of the first active layer 11.
  • the third via hole V3 is a via via.
  • the via via is composed of two half holes, one half hole is formed on the second active layer 21, and the other half hole is formed on the second connection bar of the power connection line 52 Above, the via via composed of two half holes simultaneously exposes the surface of the second active layer 21 and the surface of the second connecting bar of the power connection line 52.
  • the fourth via hole V4 exposes the surface of the second active layer 21.
  • the fifth via hole V5 and the sixth via hole V6 expose the surfaces at both ends of the third active layer 31.
  • the seventh via V7 is located at the position where the compensation connection line 51 overlaps with the compensation line formed subsequently.
  • Each driving structure forms an eighth via V8.
  • the seventh via V7 and the eighth via V8 expose the compensation connection line 51. surface.
  • the ninth via V9 is a transfer via.
  • the transfer via is composed of two half holes, one half hole is formed on the second gate electrode 22, the other half hole is formed on the second plate 42, and the two half holes are formed on the second gate electrode 22.
  • the via hole composed of holes simultaneously exposes the surface of the second gate electrode 22 and the surface of the second electrode plate 42.
  • the tenth via V10 exposes the surface of the first electrode plate 41.
  • the eleventh via V11 is located at the position of the first connection bar of the power connection line 52, a plurality of eleventh vias V11 are arranged at intervals, and the eleventh via V11 exposes the surface of the first connection bar of the power connection line 52.
  • the twelfth via hole V12 is located at the position of the auxiliary power line 53, a plurality of twelfth via holes V12 are arranged at intervals, and the third insulating layer 63 in the twelfth via hole V12 exposes the surface of the auxiliary power line 53.
  • the tenth via V10 in the first driving structure P1 and the fourth driving structure P4 is located in the interval between the second plate 42 and the third active layer 31.
  • the tenth via V10 in the second driving structure P2 and the third driving structure P3 is located in the opening in the middle of the second plate 42,
  • Forming the third metal layer includes: depositing a third metal film on the substrate on which the third insulating layer is formed, patterning the third metal film through a patterning process, and forming a display located on the third insulating layer 63
  • the third metal layer includes: one first power line VDD, one second power line VSS, one compensation line Se and four data lines Dn formed in each display unit, and a first source formed in each driving structure
  • FIG. 9B is a cross-sectional view in the direction of A-A in FIG. 9A
  • FIG. 9C is a cross-sectional view in the direction of B-B in FIG. 9A.
  • the first power line VDD, the second power line VSS, the compensation line Se, and the data line Dn are arranged in parallel and extend in the second direction.
  • the second power line VSS is disposed on the side of the first driving structure P1 close to the transparent area 200
  • the first power line VDD is disposed on the side of the fourth driving structure away from the transparent area 200.
  • the compensation line Se is arranged between the first power line VDD and the second power line VSS, and between the second driving structure P2 and the third driving structure P3.
  • the two data lines Dn are arranged between the second power line VSS and the compensation line Se, and between the first driving structure P1 and the second driving structure P2.
  • the other two data lines Dn are arranged between the first power line VDD and the compensation line Se, and between the third driving structure P3 and the fourth driving structure P4.
  • the first power line VDD is connected to the power connection line 52 through a plurality of eleventh vias V11, so that the first power line VDD is connected to the second power supply line 52 of each driving structure through the power connection line 52, respectively.
  • the source electrode 23 is connected.
  • the second power line VSS is connected to the auxiliary power line 53 through a plurality of twelfth vias V12, so that the second power line VSS outputs a low-level signal to the cathode of the light emitting element of each sub-pixel through the auxiliary power line 53.
  • the compensation line Se is connected to the compensation connection line 51 through the seventh via V7, so that the compensation line Se is respectively connected to the third source electrode 33 of each driving structure through the compensation connection line 51.
  • the compensation line Se is arranged in the middle of the display area 100, it is connected to the third transistors of the driving structure on both sides through the compensation connecting line 51, and the third transistors of the driving structure on the left and right sides are arranged symmetrically with respect to the compensation line Se.
  • This symmetrical design As a result, each display unit only needs to use one compensation line Se, which can ensure that the RC delay of the compensation signal before being written into the transistor is basically the same, and the display uniformity is ensured.
  • the first source electrode 13 is an integral structure connected to the data line Dn, so that each data line Dn is respectively connected to the first source electrode 13 of the driving structure where the first source electrode 13 passes through the first source electrode 13
  • a via hole V1 is connected to one end of the first active layer 11
  • the first drain electrode 14 is connected to the other end of the first active layer 11 through the second via hole V2
  • the first drain electrode 14 is also connected to the second end of the transition structure.
  • the nine via holes V9 are simultaneously connected to the second gate electrode 22 and the second electrode plate 42 to realize that the first drain electrode 14, the second gate electrode 22 and the second electrode plate 42 have the same potential.
  • the second source electrode 23 is simultaneously connected to the power connection line 52 and one end of the second active layer 21 through the third via hole V3 of the transition structure, so that the second source electrode 23 and the second active layer 21 are connected.
  • a power line VDD is connected, and the second drain electrode 24 is connected to the other end of the second active layer 21 through the fourth via V4.
  • the third source electrode 33 is connected to one end of the third active layer 31 through the fifth via hole V5, and at the same time is connected to the compensation connection line 51 through the eighth via hole V8, so as to realize the third source
  • the electrode 33 is connected to the compensation line Se
  • the third drain electrode 34 is connected to the other end of the third active layer 31 through the sixth via hole V6.
  • the second drain electrode 24, the third drain electrode 34, and the third electrode plate 43 are an integral structure connected to each other.
  • the third electrode plate 43 is connected to the first electrode plate 41 through the tenth via V10. Therefore, the second drain electrode 24 is connected to the first electrode plate 41 and the third electrode plate 43 at the same time, and the third drain electrode 34 is connected to the first electrode plate 41 at the same time.
  • the electrode plate 41 and the third electrode plate 43 are connected to realize that the second drain electrode 24, the third drain electrode 34, the first electrode plate 41 and the third electrode plate 43 have the same potential.
  • the plate 42 forms a second storage capacitor.
  • the third metal layer in the first driving structure P1 and the third metal layer in the fourth driving structure P4 are mirror-symmetrical with respect to the vertical axis
  • the third metal layer in the second driving structure P2 is mirror-symmetrical to the third metal layer in the second driving structure P2.
  • the third metal layer in the driving structure P3 is mirror-symmetrical with respect to the vertical axis.
  • a third metal layer is formed in the display area 100, and the transparent area 200 includes a first insulating layer 61 and a third insulating layer 63 stacked on the substrate 10.
  • Forming a fourth insulating layer and a flat layer includes: depositing a fourth insulating film on the substrate on which the third metal layer is formed, and then coating the flat film, through the mask, exposure and development of the flat film, The fourth insulating film is etched to form a fourth insulating layer 64 located in the display area and the transparent area, and a flat layer 65 located on the fourth insulating layer 64 in the display area and the transparent area, the fourth insulating layer 64 and A plurality of via holes are opened on the flat layer 65, and the plurality of via holes includes: a thirteenth via hole V13 at the position of the drain electrode of the second transistor T2 in each driving structure, as shown in FIG. 10, and FIG. 10B is FIG.
  • FIG. 10A A cross-sectional view in the AA direction
  • FIG. 10C is a cross-sectional view in the BB direction in FIG. 10A.
  • the fourth insulating layer 64 and the flat layer 65 in the thirteenth via V13 expose the surface of the drain electrode of the second transistor T2.
  • the third via hole V13 is the same via hole as the flat layer via hole V in FIG. 1.
  • Forming a transparent conductive layer includes: depositing a transparent conductive film on a substrate with a flat layer, patterning the transparent conductive film through a patterning process, and forming a transparent conductive layer on the flat layer 65, the transparent conductive layer including an anode 70.
  • An anode 70 is formed in each light-emitting structure of the display area 100, and the anode 70 is connected to the second electrode of the second transistor T2 through a thirteenth via V13, as shown in FIG. 15. Since the second electrode of the second transistor T2, the first electrode of the third transistor T3, and the third electrode plate 43 are integrally connected to each other, the thirteenth via V13 can be arranged at any position of the third electrode plate 43, such as As shown in FIG. 11, FIG. 11B is a cross-sectional view in the AA direction in FIG. 11A, and the cross-sectional view in the BB direction in FIG. 11A is the same as that in FIG. 10C.
  • a pixel definition layer includes: coating a pixel definition film on a substrate forming a transparent conductive layer, and forming a pixel definition layer (Pixel Define Layer) through masking, exposure and development processes.
  • the pixel definition layer is formed on the display In each light-emitting structure of the region 100, the pixel defining layer in each light-emitting structure is formed with an opening area 710 exposing the anode 70, as shown in FIG. 12, FIG. 12B is a cross-sectional view in the AA direction in FIG. A cross-sectional view in the BB direction in FIG. 12A.
  • Forming an organic light-emitting layer includes: forming an organic light-emitting layer 71 in the opening area of the formed pixel defining layer and on the pixel defining layer, and the organic light-emitting layer 71 is connected to the anode 70, as shown in FIG. 13.
  • Forming a cathode includes: coating a cathode film on a substrate forming an organic light-emitting layer, and patterning the cathode film through a patterning process to form a cathode 73.
  • the cathode is formed in the display area 100 and covers the organic light emitting layer in each light emitting structure. In the display area 100, the cathode 73 is connected to the organic light-emitting layer 72, as shown in FIG. 14.
  • FIG. 14B is a cross-sectional view along the A-A direction in FIG. 14A
  • FIG. 14C is a cross-sectional view along the B-B direction in FIG. 14A.
  • An encapsulation layer is formed, and an encapsulation layer is formed on the substrate forming the cathode.
  • the encapsulation layer is formed on the encapsulation layer of the display area 100 and the transparent area 200.
  • the encapsulation layer of the display area 100 includes the first encapsulation layer 74 made of inorganic material and the organic
  • the second encapsulation layer 75 of material and the third encapsulation layer 76 of inorganic material includes the first encapsulation layer 74 made of inorganic material and the organic
  • the second encapsulation layer 75 of material and the third encapsulation layer 76 of inorganic material The first encapsulation layer 74 is arranged on the cathode 73, the second encapsulation layer 75 is arranged on the first encapsulation layer 74, and the third encapsulation layer 76 is arranged on the first encapsulation layer.
  • the encapsulation layer of the transparent region 200 includes a first encapsulation layer 74 made of inorganic material and a third encapsulation layer 76 made of inorganic material.
  • the first encapsulation layer 74 is disposed on the cathode 73, and the third encapsulation layer 76 is disposed on the first encapsulation layer 74.
  • a laminated structure of inorganic material/inorganic material is formed, as shown in FIG. 15.
  • a color film layer and a shielding layer are formed on the packaging layer, as shown in Fig. 1B.
  • the first metal layer, the second metal layer, and the third metal layer may use metal materials, such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo).
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo).
  • Any one or more, or alloy materials of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), may have a single-layer structure or a multilayer composite structure, such as Mo/Cu/Mo.
  • the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON) , It can be single layer, multilayer or composite layer.
  • the first insulating layer is called the buffer layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer is called the gate insulating (GI) layer
  • the third insulating layer is called the interlayer insulation (ILD).
  • the fourth insulating layer is called a passivation (PVX) layer.
  • the thickness of the second insulating layer is smaller than the thickness of the third insulating layer, and the thickness of the first insulating layer is smaller than the sum of the thickness of the second insulating layer and the third insulating layer.
  • the flat layer can be made of organic materials
  • the transparent conductive film can be made of indium tin oxide ITO or indium zinc oxide IZO
  • the pixel definition layer can be made of polyimide, acrylic or polyethylene terephthalate.
  • the second electrode may use any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or may use any one or more of the foregoing metals.
  • the thickness of the first insulating layer is 3000 angstroms to 5000 angstroms
  • the thickness of the second insulating layer is 1000 angstroms to 2000 angstroms
  • the thickness of the third insulating layer is 4500 angstroms to 7000 angstroms.
  • the thickness of the insulating layer is 3000 angstroms to 5000 angstroms.
  • the thickness of the first metal layer is 80 angstroms to 1200 angstroms
  • the thickness of the second metal layer is 3000 angstroms to 5000 angstroms
  • the thickness of the third metal layer is 3000 angstroms to 9000 angstroms.
  • the metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten and indium and zinc, an oxide containing titanium and indium, an oxide containing Titanium and oxides of indium and tin, oxides containing indium and zinc, oxides containing silicon and indium and tin, oxides containing indium and gallium and zinc, and the like.
  • the metal oxide layer may be a single layer, or may be a double layer, or may be a multilayer.
  • the structure shown in the present disclosure and the preparation process thereof are only an exemplary description.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • the pixel driving circuit can be 5T1C or 7T1C.
  • other electrodes or leads may be provided in the film structure.
  • the embodiments of the present disclosure also provide a method for preparing a display substrate, and the method for preparing the display substrate includes:
  • Step S1 Provide a substrate.
  • Step S2 forming a display unit including a display area and a transparent area on the substrate to form a display substrate.
  • the display unit includes: a driving structure layer, a light emitting structure layer, and a color filter layer located in the display area and sequentially arranged on the substrate;
  • the light emitting structure layer includes: a plurality of light emitting structures; each light emitting structure includes: a pixel definition layer, a first The electrode, the organic light-emitting layer and the second electrode; the organic light-emitting layer is located in the opening area of the pixel defining layer and on the pixel defining layer;
  • the display substrate includes: a spacing area located in the display area, the spacing area located in the adjacent pixel defining layer of the light-emitting structure Between the opening areas, there is an overlap area with the orthographic projection of the pixel defining layer on the substrate;
  • the color film layer includes: a plurality of filters; the orthographic projection of adjacent filters on the substrate has an overlapped area; adjacent There is an overlap area between the orthographic projection of the overlapping area of the filter on the substrate and the orthographic projection of the spacer area on the substrate.
  • the display substrate is the display substrate provided in the foregoing embodiment, and the implementation principle and the implementation effect are similar, and will not be repeated here.
  • step S1 includes: forming a first metal layer including a first electrode plate in the display area on the substrate; forming a first insulating layer covering the first metal layer in the display area and the transparent area. Layer; On the first insulating layer is formed a metal oxide layer located in the display area including the second electrode plate, the orthographic projection of the second electrode plate on the substrate overlaps with the orthographic projection of the first electrode plate on the substrate Area to form a first storage capacitor; sequentially form a second insulating layer and a second metal layer located in the display area; the second metal layer includes: a first scan line and a second scan line; The third insulating layer in the area and the transparent area; a third metal layer located in the display area is formed on the third insulating layer, the third metal layer includes the first power line, the second power line, the compensation line, the data line and the third pole There is an overlap area between the orthographic projection of the third electrode plate on the substrate and the orthographic projection of the second electrode plate on the substrate to form a second storage
  • forming a color filter layer on the packaging layer includes: forming a color filter layer and a shielding layer on the packaging layer.
  • An embodiment of the present disclosure also provides a display device, including the display substrate provided in any of the foregoing embodiments.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种显示基板及其制备方法、显示装置，显示基板包括：多个显示单元；显示单元包括：位于显示区域，且依次设置在衬底上的驱动结构层、发光结构层和彩膜层；发光结构层包括：多个发光结构；每个发光结构包括：像素定义层和有机发光层；有机发光层位于像素定义层的开口区域内和像素定义层上；彩膜层包括：多个滤光片；显示基板包括：位于显示区域的间隔区域，间隔区域位于相邻发光结构的像素定义层的开口区域之间，且间隔区域在衬底上的正投影与像素定义层在衬底上的正投影存在重叠区域；相邻滤光片在衬底上的正投影存在重叠区域；相邻滤光片的重叠区域在衬底上的正投影与间隔区域在衬底上的正投影存在重叠区域。

Description

显示基板及其制备方法、显示装置 技术领域
本公开涉及但不限于显示技术领域，尤其涉及一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)为主动发光显示器件，具有发光、超薄、广视角、高亮度、高对比度、较低耗电、极高反应速度等优点。随着显示技术的不断发展，OLED技术越来越多的应用于柔性显示装置中，已逐渐成为极具发展前景的下一代显示技术。依据驱动方式的不同，OLED可分为无源矩阵驱动(Passive Matrix，简称PM)型和有源矩阵驱动(Active Matrix，简称AM)型两种，其中AMOLED是电流驱动器件，采用独立的薄膜晶体管(Thin Film Transistor，简称TFT)控制每个子像素，每个子像素皆可以连续且独立的驱动发光。
随着显示技术的不断发展，OLED技术越来越多的应用于透明显示中。透明显示是显示技术一个重要的个性化显示领域，是指在透明状态下进行图像显示，观看者不仅可以看到显示装置中的影像，而且可以看到显示装置背后的景象，可实现虚拟现实(Virtual Reality，简称VR)和增强现实(Augmented Reality，简称AR)和3D显示功能。采用AMOLED技术的透明显示装置通常是将每个像素划分为显示区域和透明区域，显示区域设置像素驱动电路和发光元件实现图像显示，透明区域实现光线透过。
发明概述
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供一种显示基板，包括衬底和设置在所述衬底上的多个显示单元；所述显示单元包括：显示区域和透明区域；所述显示单元包 括：位于所述显示区域，且依次设置在所述衬底上的驱动结构层、发光结构层和彩膜层；所述发光结构层包括：多个发光结构；每个发光结构包括：像素定义层、第一电极、有机发光层和第二电极；所述有机发光层位于所述像素定义层的开口区域内和所述像素定义层上；所述彩膜层包括：多个滤光片；
所述显示基板包括：位于所述显示区域的间隔区域，所述间隔区域位于相邻发光结构的像素定义层的开口区域之间，且所述间隔区域在衬底上的正投影与所述像素定义层在衬底上的正投影存在重叠区域；
相邻滤光片在所述衬底上的正投影存在重叠区域；相邻滤光片的重叠区域在衬底上的正投影与所述间隔区域在衬底上的正投影存在重叠区域。
在一些可能的实现方式中，多个发光结构包括：第一发光结构、第二发光结构、第三发光结构和第四发光结构；所述第一发光结构和所述第二发光结构沿第一方向排布，所述第三发光结构和所述第四发光结构沿第一方向排布；所述第一发光结构和所述第三发光结构沿第二方向排布，所述第二发光结构和所述第四发光结构沿第二方向排布；
多个滤光片包括：第一颜色滤光片、第二颜色滤光片和第三颜色滤光片；三种颜色的滤光片分别设置在四个发光结构的其中三个发光结构上；
其中，所述第一方向为一个显示单元内所述透明区域和所述显示区域的排布方向；所述第二方向垂直于所述第一方向，所述第一颜色、所述第二颜色和所述第三颜色为红色、蓝色和绿色中的一种，且三种颜色互不相同。
在一些可能的实现方式中，所述驱动结构层包括：多个沿第一方向延伸的第一扫描线和第二扫描线、多个沿第二方向延伸的第一电源线、第二电源线、数据线和补偿线以及沿第一方向排布的第一驱动结构、第二驱动结构、第三驱动结构和第四驱动结构；
所述第一驱动结构位于所述第二驱动结构靠近所述透明区域的一侧，所述第四驱动结构位于所述第三驱动结构远离所述透明区域的一侧；
所述第一电源线位于所述第四驱动结构远离所述第三驱动结构的一侧；所述第二电源线位于所述第一驱动结构远离所述第二驱动结构的一侧；所述补偿线位于所述第二驱动结构和所述第三驱动结构之间；
所述数据线包括：第一数据线、第二数据线、第三数据线和第四数据线；
所述第一数据线与所述第一驱动结构连接，且位于所述第一驱动结构靠近所述第二驱动结构的一侧；所述第二数据线与所述第二驱动结构连接，且位于所述第二驱动结构靠近所述第一驱动结构的一侧；所述第三数据线与所述第三驱动结构连接，且位于所述第三驱动结构靠近所述第四驱动结构的一侧；所述第四数据线与所述第四驱动结构连接，且位于所述第四驱动结构靠近所述第三驱动结构的一侧；
所述第一扫描线和所述第二扫描线分别位于所述驱动结构层的两侧；
所述第一电源线沿第一方向的长度大于所述补偿线或所述数据线沿第一方向的长度，所述第二电源线沿第一方向的长度大于所述补偿线或所述数据线沿第一方向的长度。
在一些可能的实现方式中，所述第一驱动结构和所述第四驱动结构相对于所述补偿线镜像对称，所述第二驱动结构和所述第三驱动结构相对于所述补偿线镜像对称。
在一些可能的实现方式中，每个驱动结构包括：像素驱动电路，所述像素驱动电路包括：第一晶体管、第二晶体管、第三晶体管和存储电容；所述第二晶体管为驱动晶体管；所述存储电容包括：第一极板、第二极板和第三极板；
所述第一晶体管的栅电极与所述第一扫描线连接，所述第一晶体管的第一极与所述数据线连接，所述第一晶体管的第二极与所述第二晶体管的栅电极连接，所述第二晶体管的第一极与所述第一电源线连接，所述第二晶体管的第二极与发光结构的第一电极连接，所述第三晶体管的栅电极与所述第二扫描线连接，所述第三晶体管的第一极通过补偿连接线与所述补偿线连接，所述第三晶体管的第二极与所述第二晶体管的第二极连接，所述发光结构的第二电极与所述第二电源线连接；所述第一极板和第三极板与所述第二晶体管的第二极连接，所述第二极板与所述第二晶体管的栅电极连接；
所述驱动结构层还包括：电源连接线、辅助电源线和补偿连接线；
所述第二晶体管的第一极通过所述电源连接线与所述第一电源线连接； 所述电源连接线与所述第一扫描线和第二扫描线同层设置，所述第一电源线通过过孔与所述电源连接线连接，在所述第一晶体管的栅电极与所述第三晶体管的栅电极之间形成双层走线；
所述辅助电源线与所述第一扫描线和第二扫描线同层设置，所述第二电源线通过过孔与所述辅助电源线连接，在所述第一晶体管的栅电极与所述第三晶体管的栅电极之间形成双层走线；
所述补偿连接线与所述第一极板同层设置，所述补偿连接线通过过孔与补偿线连接。
在一些可能的实现方式中，所述驱动结构层包括：依次叠层设置的第一金属层、第一绝缘层、金属氧化物层、第二绝缘层、第二金属层、第三绝缘层、第三金属层、第四绝缘层和平坦层；
所述第一金属层包括第一极板和补偿连接线，所述金属氧化物层包括第二极板和所有晶体管的有源层，所述第二金属层包括第一扫描线、第二扫描线、电源连接线、辅助电源线和所有晶体管的栅电极，所述第三金属层包括：第一电源线、第二电源线、补偿线、数据线、第三极板和所有晶体管的源漏电极；所述平坦层设置有暴露出所述第二晶体管的第二极的过孔；
所述第一极板在衬底上的正投影与所述第二极板在衬底上的正投影存在交叠区域，以形成第一存储电容，所述第三极板在衬底上的正投影与所述第二极板在衬底上的正投影存在交叠区域，以形成第二存储电容，所述第三极板与第一极板通过过孔连接。
在一些可能的实现方式中，所述第一极板在所述衬底上的正投影覆盖所述第一晶体管和所述第二晶体管的有源层以及所述第二极板在所述衬底上的正投影；
所述第一极板沿第二方向的长度大于所述第一晶体管的栅电极与所述第三晶体管的栅电极之间的距离。
在一些可能的实现方式中，所述第二驱动结构和所述第三驱动结构中的第二极板设置有开口；所述第二驱动结构的第二极板的开口设置在所述第二驱动结构靠近所述第三驱动结构的一侧，所述第三驱动结构的第二极板的开 口设置在所述第三驱动结构靠近所述第二驱动结构的一侧；
所述第一驱动结构和所述第四驱动结构中的平坦层过孔位于所述第三晶体管和所述第二极板之间；所述第一驱动结构中的平坦层过孔与所述第四驱动结构中的平坦层的过孔相对于补偿线镜像对称；
所述第二驱动结构的平坦层过孔位于所述第二驱动结构的第二极板的开口内，所述第三驱动结构的平坦层过孔位于所述第三驱动结构的第二极板的开口内；所述第二驱动结构中的平坦层过孔与所述第三驱动结构中的平坦层过孔相对于补偿线镜像对称；
所述第一驱动结构中的平坦层过孔与所述第二驱动结构中的平坦层过孔的排布方向与所述第一方向之间的夹角大于0度，小于90度。
在一些可能的实现方式中，所述第一发光结构的第一电极通过第一驱动结构中的平坦层过孔与第一驱动结构连接，所述第二发光结构的第一电极通过第四驱动结构中的平坦层过孔与第四驱动结构连接，所述第三发光结构的第一电极通过第二驱动结构中的平坦层过孔与第二驱动结构连接，所述第四发光结构的第一电极通过第三驱动结构中的平坦层过孔与第三驱动结构连接；
所述第一发光结构的像素定义层的开口区域和所述第三发光结构的像素定义层的开口区域位于所述第一电源线和所述补偿线之间，且在所述衬底上的正投影与所述第一驱动结构和第二驱动结构在所述衬底上的正投影存在重叠区域；
所述第二发光结构的像素定义层的开口区域和所述第四发光结构的像素定义层的开口区域位于所述补偿线和所述第二电源线之间，且在衬底上的正投影与所述第三驱动结构和第四驱动结构在所述衬底上的正投影存在重叠区域。
在一些可能的实现方式中，所述第一驱动结构的平坦层过孔在所述衬底上的正投影与所述第一发光结构中的像素定义层的开口区域在衬底上的正投影不存在重叠区域；
所述第二驱动结构的平坦层过孔在所述衬底上的正投影与所述第三发光 结构中的像素定义层的开口区域在衬底上的正投影不存在重叠区域；
所述第三驱动结构的平坦层过孔在所述衬底上的正投影与所述第四发光结构中的像素定义层的开口区域在衬底上的正投影不存在重叠区域；
所述第四驱动结构的平坦层过孔在所述衬底上的正投影与所述第二发光结构中的像素定义层的开口区域在衬底上的正投影不存在重叠区域。
在一些可能的实现方式中，所述间隔区域包括第一间隔区域、第二间隔区域和第三间隔区域；
所述第一间隔区域位于所述第一发光结构的像素定义层的开口区域与所述第三发光结构的像素定义层的开口区域之间；所述第二间隔区域位于所述第二发光结构的像素定义层的开口区域与所述第四发光结构的像素定义层的开口区域之间；所述第一间隔区域和所述第二间隔区域沿第一方向排布；
所述第一间隔区域和所述第二间隔区域分别位于所述第三间隔区域的两侧，所述第三间隔区域在所述衬底上的正投影与位于所述第一扫描线和所述第二扫描线之间的所述补偿线在衬底上的正投影重合；
所述第三间隔区域包括：沿第二方向依次设置的，且首尾相接的第一子间隔区域、第二子间隔区域和第三子间隔区域；所述第二子间隔区域位于所述第一子间隔区域和第三子间隔区域之间；
所述第一子间隔区域位于所述第一发光结构的像素定义层的开口区域与所述第二发光结构的像素定义层的开口区域之间；所述第三子间隔区域位于第三发光结构的像素定义层的开口区域与所述第四发光结构的像素定义层的开口区域之间；
所述第二子间隔区域位于所述第一间隔区域和所述第二间隔区域之间，且与所述第一间隔区域和所述第二间隔区域沿第一方向排布。
在一些可能的实现方式中，当滤光片位于所述第一发光结构上时，所述滤光片在衬底上的正投影覆盖所述第一发光结构的像素定义层的开口区域、第一子间隔区域、所述第二子间隔区域在衬底上的正投影，且与位于显示区域的部分第二扫描线和部分第二电源线在衬底上的正投影存在重叠区域；
当滤光片位于所述第二发光结构上时，所述滤光片在衬底上的正投影覆 盖所述第二发光结构的像素定义层的开口区域、所述第二间隔区域、所述第一子间隔区域、所述第二子间隔区域在衬底上的正投影，且与位于显示区域的部分第二扫描线和部分第一电源线在衬底上的正投影存在重叠区域；
当滤光片位于所述第三发光结构上时，所述滤光片在衬底上的正投影覆盖所述第三发光结构的像素定义层的开口区域在衬底上的正投影，且与部分第一间隔区域、部分第三子间隔区域、位于显示区域的部分第一扫描线和部分第二电源线在衬底上的正投影存在重叠区域；
当滤光片位于所述第四发光结构上时，所述滤光片在衬底上的正投影覆盖所述第四发光结构的像素定义层的开口区域在衬底上的正投影，且与部分第二间隔区域、部分第三子间隔区域、位于显示区域的部分第一扫描线和部分第一电源线在衬底上的正投影存在重叠区域。
所述彩膜层在衬底上的正投影与驱动结构层中的平坦层过孔在衬底上的正投影不存在重叠区域。
在一些可能的实现方式中，所述显示基板还包括：遮挡层；
所述遮挡层在衬底上的正投影与位于透明区域的第一扫描线和位于透明区域和部分显示区域的第二扫描线在衬底上的正投影存在重叠区域。
在一些可能的实现方式中，所述遮挡层包括：第一遮挡层和第二遮挡层；所述第二遮挡层位于所述第一遮挡层靠近所述衬底的一侧；
所述第一遮挡层与多个滤光片中的其中一种颜色滤光片同层设置，所述第二遮挡层与所述多个滤光片中的另一种颜色滤光片同层设置。
第二方面，本公开还提供一种显示基板的制备方法，用于制作上述显示基板，所述方法包括：
提供衬底；
在衬底上形成包括显示区域和透明区域的显示单元，以形成显示基板；所述显示单元包括：位于所述显示区域，且依次设置在所述衬底上的驱动结构层、发光结构层和彩膜层；所述发光结构层包括：多个发光结构；每个发光结构包括：像素定义层、第一电极、有机发光层和第二电极；有机发光层位于像素定义层的开口区域内和所述像素定义层上；所述显示基板包括：位 于显示区域的间隔区域，所述间隔区域位于相邻发光结构的像素定义层的开口区域之间，且与所述像素界定层在衬底上的正投影存在重叠区域；所述彩膜层包括：多个滤光片；相邻滤光片在所述衬底上的正投影存在重叠区域；相邻滤光片的重叠区域在衬底上的正投影与所述间隔区域在衬底上的正投影存在重叠区域。
在一些可能的实现方式中，所述在衬底上形成包括显示区域和透明区域的显示单元包括：
在衬底上形成位于显示区域的包括第一极板的第一金属层；
形成覆盖所述第一金属层的位于显示区域和透明区域的第一绝缘层；
在所述第一绝缘层上形成位于显示区域的包括第二极板的金属氧化物层，所述第二极板在所述衬底上的正投影与所述第一极板在衬底上的正投影存在交叠区域，以形成第一存储电容；
依次形成位于显示区域的第二绝缘层和第二金属层；所述第二金属层包括：第一扫描线和第二扫描线；
形成覆盖第二金属层的位于显示区域和透明区域的第三绝缘层；
在所述第三绝缘层上形成位于显示区域的第三金属层，所述第三金属层包括第一电源线、第二电源线、补偿线、数据线和第三极板，所述第三极板在衬底上的正投影与所述第二极板在衬底上的正投影存在交叠区域，以形成第二存储电容，所述第三极板通过过孔连接第一极板；
形成覆盖所述第三金属层的位于显示区域和透明区域的第四绝缘层和平坦层；
在所述平坦层上形成第一电极；
依次形成像素定义层、有机发光层和阴极；
形成封装层；
在封装层上形成彩膜层。
在一些可能的实现方式中，所述在封装层上形成彩膜层包括：
在封装层上形成彩膜层和遮挡层；
所述遮挡层在衬底上的正投影与位于透明区域的第一扫描线和位于透明区域和部分显示区域的第二扫描线在衬底上的正投影存在重叠区域。
第三方面，本公开还提供一种显示装置，包括上述显示基板。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1A为本公开实施例提供的显示基板的第一俯视图；
图1B为本公开实施例提供的显示基板的第二俯视图；
图2为图1B沿B-B方向的剖面图；
图3为本公开实施例提供的显示基板的第三俯视图；
图4为一种示例性实施例提供的像素驱动电路的等效电路图；
图5A为形成第一金属层后的示意图；
图5B为图5A中A-A向的剖面图；
图5C为图5A中B-B向的剖面图；
图6A为形成金属氧化物层后的示意图；
图6B为图6A中A-A向的剖面图；
图6C为图6A中B-B向的剖面图；
图7A为形成第二金属层后的示意图；
图7B为图7A中A-A向的剖面图；
图7C为图7A中B-B向的剖面图；
图8A为形成第三绝缘层的示意图；
图8B为图8A中A-A向的剖面图；
图8C为图8A中B-B向的剖面图；
图9A为形成第三金属层的示意图；
图9B为图9A中A-A向的剖面图；
图9C为图9A中B-B向的剖面图；
图10A为形成第四绝缘层和平坦层后的示意图；
图10B为图10A中A-A向的剖面图；
图10C为图10A中B-B向的剖面图；
图11A为本公开形成透明导电层后的示意图；
图11B为图11A中A-A向的剖面图；
图12A为形成像素定义层后的示意图；
图12B为图12A中A-A向的剖面图；
图12C为图12A中B-B向的剖面图；
图13为形成有机发光层后的示意图；
图14A为形成阴极后的示意图；
图14B为图14A中A-A向的剖面图；
图14C为图14A中B-B向的剖面图；
图15为形成封装层后的示意图。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不 冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的实施方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的实施方式不局限于附图所示的形状或数值。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。
晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本说明书中，沟道区域是指电流主要流过的区域。
第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的 电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
在一种透明显示基板中，位于相邻发光结构之间的被像素定义层所覆盖金属，由于像素定义层为透明材料，会出现金属反光现象，降低了透明显示基板的显示效果。
图1A为本公开实施例提供的显示基板的第一俯视图，图1B为本公开实施例提供的显示基板的第二俯视图，图2为图1B沿B-B方向的剖面图。如图1和2所示，本公开实施例提供的显示基板包括：衬底10和设置在衬底10上的多个显示单元。显示单元包括：显示区域100和透明区域200；显示单元包括：位于显示区域100，且依次设置在衬底上的驱动结构层、发光结构层和彩膜层；发光结构层包括：多个发光结构；每个发光结构包括：像素定义层71、第一电极、有机发光层和第二电极；有机发光层位于像素定义层的开口区域和像素定义层71上，彩膜层20包括：多个滤光片。
如图1所示，显示基板1包括：位于显示区域的间隔区域A(图1中的虚线区域)，间隔区域A位于相邻发光结构的像素定义层的开口区域之间，间隔区域A在衬底上的正投影与像素定义层71在衬底上的正投影存在重叠区域。
相邻滤光片在衬底上的正投影存在重叠区域；相邻滤光片的重叠区域在衬底上的正投影与间隔区域在衬底上的正投影存在重叠区域。
多个滤光片包括：第一颜色、第二颜色和第三颜色为红色、蓝色和绿色中的一种，且三种颜色互不相同。第一颜色可以为红色、第二颜色可以为蓝 色，第三颜色可以为绿色，或者，第一颜色可以为红色、第二颜色可以为绿色、第三颜色可以为蓝色，或者第一颜色可以为蓝色、第二颜色可以为红色，第三颜色可以为绿色，或者，第一颜色可以为蓝色、第二颜色可以为绿色、第三颜色可以为红色，或者第一颜色可以为绿色、第二颜色可以为红色，第三颜色可以为蓝色，或者，第一颜色可以为绿色、第二颜色可以为蓝色、第三颜色可以为红色。
显示区域被配置为实现图像显示，透明区域被配置为实现光线透过，从而实现透明状态下的图像显示，即透明显示。
在一种示例性实施例中，衬底10可以为刚性衬底或柔性衬底，其中，刚性衬底可以为但不限于玻璃、金属萡片中的一种或多种；柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在一种示例性实施例中，如图1A所示，多个发光结构包括：第一发光结构、第二发光结构、第三发光结构和第四发光结构；第一发光结构和第二发光结构沿第一方向排布，第三发光结构和第四发光结构沿第一方向排布；第一发光结构和第三发光结构沿第二方向排布，第二发光结构和第四发光结构沿第二方向排布。
第一方向为一个显示单元内透明区域200和显示区域100的排布方向，第二方向垂直于第一方向。
第一发光结构的像素定义层的开口区域711分别与第二发光结构的像素定义层的开口区域712和第三发光结构的像素定义层的开口区域713之间存在间隔，第四发光结构的像素定义层的开口区域714分别与第二发光结构的像素定义层的开口区域712和第三发光结构的像素定义层的开口区域713之间存在间隔。
在一种示例性实施例中，三种颜色的滤光片分别设置在四个发光结构的其中三个发光结构上。图1B是以第一颜色滤光片位于第一发光结构上、第二颜色滤光片位于第三发光结构上和第三颜色滤光片位于第四发光结构上为 例进行说明的。
本公开实施例中，相互重叠的相邻的滤光片可以起到遮挡位于间隔区域的金属的所反射的光线的作用，可以减弱金属反光现象，提升了显示基板的显示效果。
在一种示例性实施例中，位于显示区域中的区域B可以用来形成与发光结构层的第二电极连接的辅助电极，以向第二电极提供低电平信号。
本公开实施例提供的显示基板包括相对设置的显示基板和第二基板，显示基板包括：衬底和设置在衬底上的多个显示单元；显示单元包括：显示区域和透明区域；显示单元包括：位于显示区域，且依次设置在衬底上的驱动结构层、发光结构层和彩膜层；发光结构层包括：多个发光结构；每个发光结构包括：像素定义层、第一电极、有机发光层和第二电极；有机发光层位于像素定义层的开口区域内和像素定义层上；彩膜层包括：多个滤光片；显示基板包括：位于显示区域的间隔区域，间隔区域位于相邻发光结构的像素定义层的开口区域之间，且间隔区域在衬底上的正投影与像素定义层在衬底上的正投影存在重叠区域；相邻滤光片在衬底上的正投影存在重叠区域；相邻滤光片的重叠区域在衬底上的正投影与间隔区域在衬底上的正投影存在重叠区域。本公开实施例提供的技术方案通过设置彩膜层中的滤光片相互重叠可以遮挡将从间隔区域的金属所反射的光线，减弱显示基板出现金属反光现象，提高了显示基板的显示效果。
在一种示例性实施例中，图3为本公开实施例提供的显示基板的第三俯视图。如图3所示，每个显示单元中的驱动结构层包括：多个沿第一方向延伸的第一扫描线Gn和第二扫描线Sn、多个沿第二方向延伸的第一电源线VDD、第二电源线VSS、Dn和补偿线Se以及沿第一方向排布的第一驱动结构P1、第二驱动结构P2、第三驱动结构P3和第四驱动结构P4。
在一种示例性实施例中，第一电源线VDD、第二电源线VSS、Dn和补偿线Se以及第一驱动结构P1、第二驱动结构P2、第三驱动结构P3和第四驱动结构P4位于显示区域。
第一驱动结构P1位于第二驱动结构P2靠近透明区域200的一侧，第四 驱动结构P4位于第三驱动结构P3远离透明区域200的一侧。每个驱动结构包括像素驱动电路。像素驱动电路与发光结构电连接。
在一种示例性实施例中，第一扫描线和第二扫描线用于限定出一显示行，第一电源线和第二电源线用于限定出一显示列。
第一电源线VDD位于第四驱动结构P4远离第三驱动结构P3的一侧；第二电源线VSS位于第一驱动结构P1远离第二驱动结构P2的一侧；补偿线Se位于第二驱动结构P2和第三驱动结构P3之间。
在一种示例性实施例中，数据线包括：第一数据线、第二数据线、第三数据线和第四数据线。第一数据线与第一驱动结构连接，且位于第一驱动结构P1靠近第二驱动结构P2的一侧。第二数据线与第二驱动结构P2连接，且位于第二驱动结构P2靠近第一驱动结构P1的一侧；第三数据线与第三驱动结构P3连接，且位于第三驱动结构P3靠近第四驱动结构P4的一侧；第四数据线与第四驱动结构P4连接，且位于第四驱动结构P4靠近第三驱动结构P3的一侧。
在一种示例性实施例中，第一电源线VDD、第二电源线VSS、补偿线Se和四条数据线Dn相互平行，沿着远离透明区域200的方向，第二电源线VSS、两条数据线Dn、补偿线Se、两条数据线Dn和第一电源线VDD依次设置，第一电源线VDD与邻近的数据线Dn之间形成有一个驱动结构，第二电源线VSS与邻近的数据线Dn之间形成有一个驱动结构，补偿线Se与邻近的数据线Dn之间分别形成两个驱动结构。这样，第一电源线VDD与第二电源线VSS之间通过设置1条补偿线Se和4条数据线Dn形成四个驱动结构，4条数据线Dn中两条数据线Dn位于补偿线Se与第二电源线VSS之间，另外两条数据线Dn位于补偿线Se与第一电源线VDD之间。
第一电源线VDD沿第一方向的长度大于补偿线Se或数据线Dn沿第一方向的长度，第二电源线VSS沿第一方向的长度大于补偿线Se或数据线Dn沿第一方向的长度，可以降低第一电源线VDD和第二电源线VSS的电阻。
在一种示例性实施例中，第一扫描线Gn和第二扫描线Sn分别位于驱动结构层的两侧。
在一种示例性实施例中，可以设置第一电源线VDD的电压大于第二电源线VSS的电压，数据线Dn传输的数据信号的最大电压小于第一扫描线的最大电压，也小于第一电源线VDD的电压。
在一种示例性实施例中，如图3所示，第一驱动结构P1和第四驱动结构P4相对于补偿线Se镜像对称，第二驱动结构P2和第三驱动结构P3相对于补偿线Se镜像对称。
图4为一种示例性实施例提供的像素驱动电路的等效电路图。如图4所示，像素驱动电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容C ST，发光结构为OLED。第一晶体管T1为开关晶体管，第二晶体管T2为驱动晶体管，第三晶体管T3为补偿晶体管，存储电容包括：第一极板41、第二极板42和第三极板43。
第一晶体管T1的栅电极连接第一扫描线Gn，第一晶体管T1的第一极连接数据线Dn，第一晶体管T1的第二极连接第二晶体管T2的栅电极，第一晶体管T1用于在第一扫描线Gn控制下，接收数据线Dn传输的数据信号，使第二晶体管T2的栅电极接收数据信号。第二晶体管T2的栅电极连接第一晶体管T1的第二极，第二晶体管T2的第一极连接第一电源线VDD，第二晶体管T2的第二极连接OLED的第一极，第二晶体管T2用于在其栅电极所接收的数据信号控制下，在第二极产生相应的电流。第三晶体管T3的栅电极连接第二扫描线Sn，第三晶体管T3的第一极连接补偿线Se，第三晶体管T3的第二极连接第二晶体管T2的第二极，第三晶体管T3用于响应补偿时序提取第二晶体管T2的阈值电压Vth以及迁移率，以对阈值电压Vth进行补偿。OLED的第一极连接第二晶体管T2的第二极，OLED的第二极连接第二电源线VSS，OLED用于响应第二晶体管T2的第二极的电流而发出相应亮度的光。存储电容C ST的第一极与第二晶体管T2的栅电极连接，存储电容C ST的第二极与第二晶体管T2的第二极连接，存储电容C ST用于存储第二晶体管T2的栅电极的电位。
在一种示例性实施例中，第一极板41在衬底上的正投影与第二极板42在衬底上的正投影至少存在交叠区域，形成第一存储电容，第三极板43在衬底上的正投影与第二极板42在衬底上的正投影至少存在交叠区域，形成 第二存储电容。第一极板41和第三极板43通过过孔连接，使第一极板41和第三极板43的电位相同，形成并联结构的第一存储电容和第二存储电容。
在一种示例性实施例中，驱动结构层还包括多条连接线。多条连接线至少包括补偿连接线51、电源连接线52和辅助电源线。
在一种示例性实施例中，补偿连接线51与第一极板41同层设置，补偿连接线51通过过孔与补偿线Se连接。
在一种示例性实施例中，第二晶体管的第一极通过电源连接线52与第一电源线VDD连接；电源连接线52与第一扫描线Gn和第二扫描线Sn同层设置，第一电源线VDD通过过孔与电源连接线52连接，在第一晶体管的栅电极与第三晶体管的栅电极之间形成双层走线。在第一晶体管的栅电极与第三晶体管的栅电极之间形成双层走线，保证了电源信号传输的可靠性，并降低了第一电源线VDD的电阻。
在一种示例性实施例中，辅助电源线与第一扫描线和第二扫描线同层设置，第二电源线通过过孔与辅助电源线连接，在第一晶体管的栅电极与第三晶体管的栅电极之间形成双层走线；在第一晶体管的栅电极与第三晶体管的栅电极之间形成双层走线，保证了电源信号传输的可靠性，并降低了第二电源线VSS的电阻。
补偿连接线51通过过孔与补偿线Se连接，使得补偿线Se通过补偿连接线51向四个驱动结构提供补偿信号，电源连接线52通过过孔与第一电源线VDD连接，使得第一电源线VDD通过电源连接线52向四个子像素提供电源信号，形成第一电源线VDD和补偿线Se的一拖四结构。第一电源线和补偿线设计为一拖四结构，节省了信号线数量，减小了占用空间，结构简洁，布局合理，充分利用布图空间，提高了空间利用率，有利于提高分辨率和透明度。
在一种示例性实施例中，第一极板41为长条状的矩形，除了补偿连接线51位置，第一极板41完全覆盖每个驱动结构中的像素驱动电路。
在一种示例性实施例中，第一极板41沿第二方向的长度大于后续形成的第一晶体管的栅电极与第三晶体管的栅电极之间的距离，第一极板41的沿第二方向的长度大于后续形成的第一晶体管的第一电极与第三晶体管的第一极之间的距离可以实现有效的遮挡，避免光线进入所有晶体管中的有源层。
如图1和3所示，显示区域的4个驱动结构中，每个驱动结构中的像素驱动电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容。第一晶体管T1包括第一有源层、第一栅电极、第一源电极和第一漏电极，第二晶体管T2包括第二有源层、第二栅电极、第二源电极和第二漏电极，第三晶体管T3包括第三有源层、第三栅电极、第三源电极和第三漏电极。存储电容包括第一极板41、第二极板42和第三极板43，第一极板41和第二极板42形成第一存储电容，第二极板42和第三极板43形成第二存储电容，第一极板41和第三极板43的电位相同，因而第一存储电容和第二存储电容形成并联结构，有效提高了存储容量。
在一种示例性实施例中，第一扫描线Gn与每个子像素中第一晶体管T1的第一栅电极连接，第二扫描线Sn与每个子像素中第三晶体管T3的第三栅电极连接，数据线Dn与每个子像素中第一晶体管T1的第一源电极连接，补偿连接线51被配置为使补偿线Se与每个子像素中第三晶体管T3的第三源电极连接，电源连接线52被配置为使第一电源线VDD与每个子像素中第二晶体管T2的第二源电极连接。以第一子像素P1的像素驱动电路为例，第一晶体管T1的第一栅电极与第一扫描线Gn连接，第一晶体管T1的第一源电极与数据线Dn连接，第一晶体管T1的第一漏电极与第二晶体管T2的第二栅电极连接。第二晶体管T2的第二栅电极与第一晶体管T1的第一漏电极连接，第二晶体管T2的第二源电极通过电源连接线52与第一电源线VDD连接，第二晶体管T2的第二漏电极与第三晶体管T3的第三漏电极和发光元件的阳极连接。第三晶体管T3的第三栅电极与第二扫描线Sn连接，第三晶体管T3的第三源电极通过补偿连接线51与补偿线Se连接，第三晶体管T3的第三漏电极与第二晶体管T2的第二漏电极和发光元件的阳极连接。第一极板41与第二晶体管T2的第二漏电极和第三晶体管T3的第三漏电极连接，第二极板42与第一晶体管T1的第一漏电极和第二晶体管T2的第二栅电极 连接，第三极板43与第二晶体管T2的第二漏电极和第三晶体管T3的第三漏电极连接。
在一种示例性实施例中，在垂直于显示基板的方向上，驱动结构层包括叠设的第一金属层、第一绝缘层、金属氧化物层、第二绝缘层、第二金属层、第三绝缘层、第三金属层、第四绝缘层和平坦层。
第一金属层包括作为遮挡层的第一极板41和补偿连接线51，作为遮挡层的第一极板41和补偿连接线51同层设置且通过同一次构图工艺形成。金属氧化物层包括第二极板42以及各个晶体管的有源层，第二极板42以及各个晶体管的有源层同层设置且通过同一次构图工艺形成。第二金属层包括第一扫描线Gn、第二扫描线Sn、电源连接线52以及各个晶体管的栅电极，第一扫描线Gn、第二扫描线Sn、电源连接线52以及各个晶体管的栅电极同层设置，且通过同一次构图工艺形成。第三金属层包括数据线Dn、补偿线Se、第一电源线VDD、第二电源线VSS、第三极板43以及各个晶体管的源电极和漏电极，数据线Dn、第一电源线VDD、第二电源线VSS、补偿线Se、第三极板43以及各个晶体管的源电极和漏电极同层设置，且通过同一次构图工艺形成。平坦层上设置有过孔，平坦层过孔V暴露第二晶体管的第二极，发光结构层中的第一电极通过平坦层过孔与驱动结构层连接。
在一种示例性实施例中，第一晶体管T1和第二晶体管T2位于第二极板42靠近第一扫描线Gn的一侧，第三晶体管T3位于第二极板42靠近第二扫描线Sn的一侧。
一种示例性实施例通过采用金属氧化物材料的第二极板作为存储电容的极板，第二极板分别与第一金属层中的第一极板和第三金属层中的第三极板形成存储电容，第一极板和第三极板具有相同的电位，第二极板具有不同于第一极板和第三极板的电位，因此第一极板、第二极板和第三极板之间形成二个并联的存储电容，有效增大了存储电容的容量，有利于实现高分辨率显示。本公开的制备工艺利用现有成熟的制备设备即可实现，对现有工艺改进较小，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
在一种示例性实施例中，第二驱动结构和第三驱动结构中的第二极板设 置有开口；第二驱动结构的第二极板的开口设置在第二驱动结构靠近第三驱动结构的一侧，第三驱动结构的第二极板的开口设置在第三驱动结构靠近第二驱动结构的一侧。
在一种示例性实施例中，第一驱动结构和第四驱动结构中的平坦层过孔位于第三晶体管和第二极板之间；第一驱动结构中的平坦层过孔与第四驱动结构中的平坦层的过孔相对于补偿线镜像对称；第二驱动结构的平坦层过孔位于第二驱动结构的第二极板的开口内，第三驱动结构的平坦层过孔位于第三驱动结构的第二极板的开口内；第二驱动结构中的平坦层过孔与第三驱动结构中的平坦层过孔相对于补偿线镜像对称。
在一种示例性实施例中，第一驱动结构中的平坦层过孔与第二驱动结构中的平坦层过孔的排布方向与第一方向之间的夹角大于0度，小于90度。
在一种示例性实施例中，第一发光结构的第一电极通过第一驱动结构中的平坦层过孔与第一驱动结构连接，第二发光结构的第一电极通过第四驱动结构中的平坦层过孔与第四驱动结构连接，第三发光结构的第一电极通过第二驱动结构中的平坦层过孔与第二驱动结构连接，第四发光结构的第一电极通过第三驱动结构中的平坦层过孔与第三驱动结构连接。
第一发光结构的像素定义层的开口区域711和第三发光结构的像素定义层的开口区域713位于第二电源线VSS和补偿线Se之间，且在衬底上的正投影与第一驱动结构和第二驱动结构在衬底上的正投影存在重叠区域。
第二发光结构的像素定义层的开口区域712和第四发光结构的像素定义层的开口区域714位于补偿线Se和第一电源线VDD之间，且在衬底上的正投影与第三驱动结构和第四驱动结构在衬底上的正投影存在重叠区域。
如图1所示，第一驱动结构的平坦层过孔V在衬底上的正投影与第一发光结构中的像素定义层的开口区域在衬底上的正投影不存在重叠区域；第二驱动结构的平坦层过孔V在衬底上的正投影与第三发光结构中的像素定义层的开口区域在衬底上的正投影不存在重叠区域；第三驱动结构的平坦层过孔V在衬底上的正投影与第四发光结构中的像素定义层的开口区域在衬底上的正投影不存在重叠区域。第四驱动结构的平坦层过孔V在衬底上的正投影与第二发光结构中的像素定义层的开口区域在衬底上的正投影不存在重叠区 域。
在一种示例性实施例中，透明区域包括在衬底上叠设的第一绝缘层、第三绝缘层、第四绝缘层和平坦层。
在一种示例性实施例中，如图1所示，间隔区域包括第一间隔区域A1、第二间隔区域A2和第三间隔区域。第一间隔区域A1位于第一发光结构的像素定义层的开口区域与第三发光结构的像素定义层的开口区域之间；第二间隔区域A2位于第二发光结构的像素定义层的开口区域与第四发光结构的像素定义层的开口区域之间；第一间隔区域和第二间隔区域沿第一方向排布。第一间隔区域和第二间隔区域分别位于第三间隔区域的两侧，第三间隔区域在衬底上的正投影与位于第一扫描线和第二扫描线之间的补偿线在衬底上的正投影重合。
在一种示例性实施例中，如图1所示，第三间隔区域包括：沿第二方向依次设置的，且首尾相接的第一子间隔区域A31、第二子间隔区域A32和第三子间隔区域A33；第二子间隔区域A32位于所述第一子间隔区域A31和第三子间隔区域A33之间。
第一子间隔区域A31位于第一发光结构的像素定义层的开口区域与第二发光结构的像素定义层的开口区域之间；第三子间隔区域A33位于第三发光结构的像素定义层的开口区域与第四发光结构的像素定义层的开口区域之间。第二子间隔区域A32位于第一间隔区域A1和第二间隔区域A2之间，且与第一间隔区域A1和第二间隔区域A2沿第一方向排布。
在一种示例性实施例中，如图1所示，当滤光片位于第一发光结构上时，滤光片在衬底上的正投影覆盖第一发光结构的像素定义层的开口区域、第一子间隔区域、第二子间隔区域在衬底上的正投影，且与位于显示区域的部分第二扫描线和部分第二电源线在衬底上的正投影存在重叠区域。
在一种示例性实施例中，如图1所示，当滤光片位于第二发光结构上时，滤光片在衬底上的正投影覆盖第二发光结构的像素定义层的开口区域、第二间隔区域、第一子间隔区域、第二子间隔区域在衬底上的正投影，且与位于显示区域的部分第二扫描线和部分第一电源线在衬底上的正投影存在重叠区 域；
在一种示例性实施例中，如图1所示，当滤光片位于第三发光结构上时，滤光片在衬底上的正投影覆盖第三发光结构的像素定义层的开口区域在衬底上的正投影，且与部分第一间隔区域、部分第三子间隔区域、位于显示区域的部分第一扫描线和部分第二电源线在衬底上的正投影存在重叠区域；
在一种示例性实施例中，如图1所示，当滤光片位于第四发光结构上时，滤光片在衬底上的正投影覆盖第四发光结构的像素定义层的开口区域在衬底上的正投影，且与部分第二间隔区域、部分第三子间隔区域、位于显示区域的部分第一扫描线和部分第一电源线在衬底上的正投影存在重叠区域。
在一种示例性实施例中，如图1B所示，彩膜层在衬底上的正投影与驱动结构层中的平坦层过孔在衬底上的正投影不存在重叠区域，可以保证相邻滤光片之间的重叠区域减少，以减少串色。
在一种示例性实施例中，如图1A和1B所示，显示基板还包括：遮挡层30。遮挡层30在衬底上的正投影与位于透明区域的第一扫描线Gn和位于透明区域和部分显示区域的第二扫描线Sn在衬底上的正投影存在重叠区域。
在一种示例性实施例中，遮挡层30包括：第一遮挡层和第二遮挡层；第一遮挡层位于第二遮挡层靠近衬底的一侧，第一遮挡层与多个滤光片中的其中一种颜色滤光片同层设置，第二遮挡层与多个滤光片中的另一种颜色滤光片同层设置，可以简化显示基板的制作工艺。
下面通过显示基板的制备过程说明一种示例性实施例提供的显示基板的结构。“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶处理。沉积可以采用溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用喷涂和旋涂中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在衬底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。若在整个制作过程中该“薄膜”需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。本公开中所说的“A和B同层设置”是指，A和B通过同一次构图工艺同时形成。
图5～图15为一种示例性实施例提供的显示基板制备过程的示意图，示意了顶发射OLED显示基板一个显示单元的版图结构，每个显示单元包括显示区域100和透明区域200，显示区域100的驱动结构层包括：四个驱动结构P1至P4。每个驱动结构的像素驱动电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容。
(1)形成第一金属层，包括：在衬底上沉积第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，在衬底10上形成位于显示区域100的第一金属层。第一金属层包括第一极板41和补偿连接线51，每个驱动结构形成一个第一极板41，如图5所示，图5B为图5A中A-A向的剖面图，图5C为图5A中B-B向的剖面图。
在一种示例性实施例中，第一极板41既作为第一存储电容的一个极板，为与后续形成的第二极板形成第一存储电容，又作为遮挡层，配置为对晶体管的有源层进行遮光处理，以降低照射到晶体管上的光强度，降低漏电流，从而减少光照对晶体管特性的影响。
在一种示例性实施例中，补偿连接线51为跨设4个子像素的条状结构。补偿连接线51配置为与后续形成的补偿线连接，使补偿线向驱动结构提供补偿信号。
在一种示例性实施例中，第一驱动结构P1中的第一金属层与第四驱动结构P4中的第一金属层相对于垂直轴镜像对称，第二驱动结构P2中的第一金属层与第三驱动结构P3中的第一金属层相对于垂直轴镜像对称。垂直轴为第二驱动结构和第三驱动结构的中线。
(2)形成金属氧化物层，包括：在形成有第一金属层的衬底上，沉积第一绝缘薄膜，通过构图工艺对第一绝缘薄膜进行构图，形成覆盖第一金属层的，且位于显示区域和透明区域的第一绝缘层61，在第一绝缘层61上沉积金属氧化物薄膜，通过构图工艺对金属氧化物薄膜进行构图，形成位于显示区域的金属氧化物层。金属氧化物层包括设置在每个驱动结构中的第一有源层11、第二有源层21、第三有源层31和一个第二极板42。如图6所示，图6B为图6A中A-A向的剖面图，图6C为图6A中B-B向的剖面图。
第一有源层11作为第一晶体管的有源层，第二有源层21作为第二晶体管的有源层，第三有源层31作为第三晶体管的有源层，第二极板42在衬底10上的正投影与第一极板41在衬底10上的正投影存在交叠区域，第一极板41和第二极板42形成第一存储电容。第二极板42既作为第一存储电容的一个极板，又作为第二存储电容的一个极板，第二极板42配置为与后续形成的第三极板形成第二存储电容。
在示例性实施方式中，第一有源层11、第二有源层21和第三有源层31在衬底10上的正投影与第一极板41在衬底10上的正投影存在交叠区域，使得作为遮挡层的第一极板41可以遮挡第一晶体管、第二晶体管和第三晶体管的沟道区域，避免光线对沟道产生影响，以避免沟道因生成光生漏电而影响显示效果。第一有源层11、第二有源层21和第三有源层31在衬底10上的正投影与第二极板42在衬底10上的正投影间隔设置，即第一有源层11与第二极板42之间、第二有源层21与第二极板42之间以及第三有源层31与第二极板42之间没有交叠区域，有利于根据相关需求设计第一晶体管、第二晶体管和第三晶体管的沟道宽长比。
第三有源层31位于第二极板42靠近补偿连接线51的一侧，第一有源层11和第二有源层21位于第二极板42远离补偿连接线51的一侧，第二有源层21位于第一有源层11靠近补偿连接线51的一侧。
在一种示例性实施例中，第一驱动结构P1中的金属氧化物层与第四驱动结构P4中的金属氧化物层相对于垂直轴镜像对称，第二驱动结构P2中的金属氧化物层与第三驱动结构P3中的金属氧化物层相对于垂直轴镜像对称，第一驱动结构P1和第四驱动结构P4中的第二极板42与第三有源层31之间存在间隔，第二驱动结构P2和第三驱动结构P3的第二极板42中部设置有开口。
(3)形成第二金属层，包括：在形成有金属氧化物的衬底上，沉积第二绝缘薄膜，通过构图工艺对第二绝缘薄膜进行构图，形成位于显示区域的第二绝缘层62。在第二绝缘层62上沉积第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，形成第二金属层。第二金属层包括形成在每个显示单元中的第一扫描线Gn、第二扫描线Sn、电源连接线52和辅助电源线53以及 形成在每个驱动结构中的第一栅电极12、第二栅电极22和第三栅电极32，如图7A所示，图7B为图7A中A-A向的剖面图，图7C为图7A中B-B向的剖面图。
在一种示例性实施例中，第一扫描线Gn和第二扫描线Sn平行设置，且均沿第一方向延伸。第一扫描线Gn和第二扫描线Sn位于驱动结构层的两侧。第一扫描线Gn设置在驱动结构层靠近第一晶体管的一侧，第二扫描线Sn位于驱动结构层靠近第三晶体管的一侧。
在一种示例性实施例中，第一栅电极12是与第一扫描线Gn连接的一体结构，且跨设在第一有源层11上。第二栅电极22跨设在第二有源层21和第二极板42上。第三栅电极32是与第二扫描线Sn连接的一体结构，且跨设在第三有源层31上。
在一种示例性实施例中，电源连接线52包括垂直于第一扫描线Gn的第一连接条和平行于第一扫描线Gn的第二连接条，第一连接条和第二连接条的一端相互连接。第一连接条形成在显示单元中第一电源线VDD所在区域，配置为连接后续形成的第一电源线VDD，第二连接条跨设在4个驱动结构内，配置为向每个驱动结构提供高电平信号。
在一种示例性实施例中，辅助电源线53形成在显示单元中第二电源线VSS所在区域，垂直于第一扫描线Gn，配置为连接后续形成的第二电源线VSS。
在一种示例性实施例中，第二绝缘层62与第二金属层相同，即第二绝缘层62位于第二金属层的下方，第二金属层以外区域没有第二绝缘层62。
在一种示例性实施例中，第一驱动结构P1中第二金属层与第四驱动结构P4中的第二金属层相对于垂直轴镜像对称，第二驱动结构P2中的第二金属层与第三驱动结构P3中的第二金属层相对于垂直轴镜像对称。
在一种示例性实施例中，本次工艺还包括导体化处理。导体化处理是在形成第二金属层后，利用第一栅电极12、第二栅电极22和第三栅电极32作为遮挡对金属氧化物层进行等离子体处理，被第一栅电极12、第二栅电极22和第三栅电极32遮挡区域的金属氧化物层(即金属氧化物层与第一栅电 极12、第二栅电极22和第三栅电极重叠的区域)作为晶体管的沟道区域，未被第二金属层遮挡区域的金属氧化物层被处理成导体化层，形成导体化的第二极板42和导体化的源漏区域。
(4)形成第三绝缘层。形成第三绝缘层包括：在形成有第二金属层的衬底上，沉积第三绝缘薄膜，通过构图工艺对第三绝缘薄膜进行构图，形成位于显示区域和透明区域的第三绝缘层63。第三绝缘层63上开设有多个过孔，多个过孔包括：位于第一栅电极12两侧的第一过孔V1和第二过孔V2，位于第二栅电极22两侧的第三过孔V3和第四过孔V4，位于第三栅电极32两侧的第五过孔V5和第六过孔V6，位于补偿连接线51所在位置的第七过孔V7和第八过孔V8，位于第二栅电极22与第二极板42重叠区域的第九过孔V9，位于第一极板41所在位置的第十过孔V10，位于电源连接线52的第一连接条所在位置的多个第十一过孔V11，位于辅助电源线53所在位置的多个第十二过孔V12，如图8A所示，图8B为图8A中A-A向的剖面图，图8C为图8A中B-B向的剖面图。
在一种示例性实施例中，第一过孔V1和第二过孔V2暴露出第一有源层11两端的表面。第三过孔V3为转接过孔，转接过孔由两个半孔组成，一个半孔形成在第二有源层21上，另一个半孔形成在电源连接线52的第二连接条上，两个半孔组成的转接过孔同时暴露出第二有源层21的表面和电源连接线52的第二连接条的表面。第四过孔V4暴露出第二有源层21的表面。第五过孔V5和第六过孔V6暴露出第三有源层31两端的表面。第七过孔V7位于补偿连接线51与后续形成的补偿线重叠的位置，每个驱动结构形成一个第八过孔V8，第七过孔V7和第八过孔V8暴露出补偿连接线51的表面。第九过孔V9为转接过孔，转接过孔由两个半孔组成，一个半孔形成在第二栅电极22上，另一个半孔形成在第二极板42上，两个半孔组成的转接过孔同时暴露出第二栅电极22的表面和第二极板42的表面。第十过孔V10暴露出第一极板41的表面。第十一过孔V11位于电源连接线52的第一连接条所在位置，多个第十一过孔V11间隔设置，第十一过孔V11暴露出电源连接线52的第一连接条的表面。第十二过孔V12位于辅助电源线53所在位置，多个第十二过孔V12间隔设置，第十二过孔V12内的第三绝缘层63暴露出辅 助电源线53的表面。
在一种示例性实施例中，第一驱动结构P1和第四驱动结构P4中的第十过孔V10位于第二极板42与第三有源层31之间的间隔内。第二驱动结构P2和第三驱动结构P3中的第十过孔V10位于第二极板42中部的开口内，
(5)形成第三金属层，包括：在形成有第三绝缘层的衬底上，沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，在第三绝缘层63上形成位于显示区域100的第三金属层。第三金属层包括：形成在每个显示单元中的一条第一电源线VDD、一条第二电源线VSS、一条补偿线Se和四条数据线Dn，以及形成在每个驱动结构中的第一源电极13、第一漏电极14、第二源电极23、第二漏电极24、第三源电极33、第三漏电极34和第三极板43。如图9A所示，图9B为图9A中A-A向的剖面图，图9C为图9A中B-B向的剖面图。
在一种示例性实施例中，第一电源线VDD、第二电源线VSS、补偿线Se和数据线Dn平行设置，且沿第二方向延伸。第二电源线VSS设置在第一驱动结构P1靠近透明区域200的一侧，第一电源线VDD设置在第四驱动结构远离透明区域200的一侧。补偿线Se设置在第一电源线VDD和第二电源线VSS中间，且设置在第二驱动结构P2和第三驱动结构P3之间。两条数据线Dn设置在第二电源线VSS和补偿线Se之间，且设置在第一驱动结构P1和第二驱动结构P2之间。另外两条数据线Dn设置在第一电源线VDD和补偿线Se之间，且设置在第三驱动结构P3和第四驱动结构P4之间。
在一种示例性实施例中，第一电源线VDD通过多个第十一过孔V11与电源连接线52连接，使得第一电源线VDD通过电源连接线52分别与每个驱动结构的第二源电极23连接。第二电源线VSS通过多个第十二过孔V12与辅助电源线53连接，使得第二电源线VSS通过辅助电源线53向每个子像素的发光元件的阴极输出低电平信号。补偿线Se通过第七过孔V7与补偿连接线51连接，使得补偿线Se通过补偿连接线51分别与每个驱动结构的第三源电极33连接。由于补偿线Se设置在显示区域100的中部，通过补偿连接线51与两侧的驱动结构的第三晶体管连接，左右两侧驱动结构的第三晶体管相对于补偿线Se对称设置，这种对称设计使得每个显示单元只需要采用 一条补偿线Se，可以保证补偿信号在写入晶体管前RC延迟基本上相同，保证了显示均一性。
在一种示例性实施例中，第一源电极13是与数据线Dn连接的一体结构，使得每条数据线Dn分别与所在驱动结构的第一源电极13连接，第一源电极13通过第一过孔V1与第一有源层11的一端连接，第一漏电极14通过第二过孔V2与第一有源层11的另一端连接，第一漏电极14还通过转接结构的第九过孔V9同时与第二栅电极22和第二极板42连接，实现了第一漏电极14、第二栅电极22和第二极板42具有相同的电位。
在一种示例性实施例中，第二源电极23通过转接结构的第三过孔V3同时与电源连接线52和第二有源层21的一端连接，实现了第二源电极23与第一电源线VDD的连接，第二漏电极24通过第四过孔V4与第二有源层21的另一端连接。
在一种示例性实施例中，第三源电极33通过第五过孔V5与第三有源层31的一端连接，同时通过第八过孔V8与补偿连接线51连接，实现了第三源电极33与补偿线Se的连接，第三漏电极34通过第六过孔V6与第三有源层31的另一端连接。
在一种示例性实施例中，第二漏电极24、第三漏电极34和第三极板43为相互连接的一体结构。第三极板43通过第十过孔V10与第一极板41连接，因而，第二漏电极24同时与第一极板41和第三极板43连接，第三漏电极34同时与第一极板41和第三极板43连接，实现了第二漏电极24、第三漏电极34、第一极板41和第三极板43具有相同的电位。
在一种示例性实施例中，第三极板43在衬底10上的正投影与第二极板42在衬底10上的正投影存在交叠区域，第三极板43与第二极板42形成第二存储电容。
在示例性实施方式中，第一驱动结构P1中第三金属层与第四驱动结构P4中的第三金属层相对于垂直轴镜像对称，第二驱动结构P2中的第三金属层与第三驱动结构P3中的第三金属层相对于垂直轴镜像对称。
本次构图工艺后，第三金属层形成在显示区域100，透明区域200包括 在衬底10上叠设的第一绝缘层61和第三绝缘层63。
(6)形成第四绝缘层和平坦层，包括：在形成有第三金属层的衬底上，先沉积第四绝缘薄膜，后涂覆平坦薄膜，通过平坦薄膜的掩膜、曝光和显影，对第四绝缘薄膜进行刻蚀形成位于显示区域和透明区域的第四绝缘层64，以及设置在第四绝缘层64上的，位于显示区域和透明区域的平坦层65，第四绝缘层64和平坦层65上开设有多个过孔，多个过孔包括：每个驱动结构中第二晶体管T2的漏电极所在位置的第十三过孔V13，如图10所示，图10B为图10A中A-A向的剖面图，图10C为图10A中B-B向的剖面图。第十三过孔V13中的第四绝缘层64和平坦层65暴露出第二晶体管T2的漏电极的表面。
第三过孔V13与图1中的平坦层过孔V为同一过孔。
(7)形成透明导电层，包括：在形成有平坦层的衬底上，沉积透明导电薄膜，通过构图工艺对透明导电薄膜进行构图，在平坦层65上形成透明导电层，透明导电层包括阳极70，阳极70形成在显示区域100的每个发光结构中，阳极70通过第十三过孔V13与第二晶体管T2的第二极连接，如图15所示。由于第二晶体管T2的第二极、第三晶体管T3的第一极和第三极板43是相互连接的一体结构，第十三过孔V13可以设置在第三极板43的任意位置，如图11所示，图11B为图11A中A-A向的剖面图，图11A中B-B向的剖面图与图10C相同。
(8)形成像素定义层，包括：在形成透明导电层的衬底上涂覆像素定义薄膜，通过掩膜、曝光和显影工艺形成像素定义层(Pixel Define Layer)，像素定义层形成在在显示区域100的每个发光结构中，每个发光结构中的像素定义层形成有暴露出阳极70的开口区域710，如图12所示，图12B为图12A中A-A向的剖面图，图12C为图12A中B-B向的剖面图。
(9)形成有机发光层，包括：在形成的像素定义层的开口区域内和像素定义层上形成有机发光层71，有机发光层71与阳极70连接，如图13所示。
(10)形成阴极，包括：在形成有机发光层的衬底上涂覆阴极薄膜，通过构图工艺对阴极薄膜进行构图，形成阴极73。阴极形成在显示区域100中， 并覆盖每个发光结构中的有机发光层。在显示区域100，阴极73与有机发光层72连接，如图14所示，图14B为图14A中A-A向的剖面图，图14C为图14A中B-B向的剖面图。
(11)形成封装层，在形成阴极的衬底上形成封装层，封装层形成在显示区域100和透明区域200的封装层，显示区域100的封装层包括无机材料的第一封装层74、有机材料的第二封装层75和无机材料的第三封装层76，第一封装层74设置在阴极73上，第二封装层75设置在第一封装层74上，第三封装层76设置在第二封装层75上，形成无机材料/有机材料/无机材料的叠层结构。透明区域200的封装层包括无机材料的第一封装层74和无机材料的第三封装层76，第一封装层74设置在阴极73上，第三封装层76设置在第一封装层74上，形成无机材料/无机材料的叠层结构，如图15所示。
(12)在封装层上形成彩膜层和遮挡层，如图1B所示。
在一种示例性实施例中，第一金属层、第二金属层和第三金属层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层称之为缓冲(Buffer)层，用于提高衬底的抗水氧能力，第二绝缘层称之为栅绝缘(GI)层，第三绝缘层称之为层间绝缘(ILD)层，第四绝缘层称之为钝化(PVX)层。第二绝缘层的厚度小于第三绝缘层的厚度，第一绝缘层的厚度小于第二绝缘层和第三绝缘层的厚度之和，在保证绝缘效果的前提下，提高存储电容的容量。平坦层可以采用有机材料，透明导电薄膜可以采用氧化铟锡ITO或氧化铟锌IZO，像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯。第二电极可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或更多种，或可以采用上述金属中任意一种或多种制成的合金。
在一种示例性实施例中，第一绝缘层的厚度为3000埃到5000埃，第二绝缘层的厚度为1000埃到2000埃，第三绝缘层的厚度为4500埃到7000埃， 第四绝缘层的厚度为3000埃到5000埃。
在一种示例性实施例中，第一金属层的厚度为80埃到1200埃，第二金属层的厚度为3000埃到5000埃，第三金属层的厚度为3000埃到9000埃。
在一种示例性实施例中，金属氧化物层可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物、包含铟和镓和锌的氧化物等。金属氧化物层可以单层，或者可以是双层，或者可以是多层。
本公开所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，像素驱动电路可以是5T1C或7T1C。再如，膜层结构中还可以设置其它电极或引线。
本公开实施例还提供了一种显示基板的制备方法，显示基板的制备方法包括：
步骤S1、提供衬底。
步骤S2、在衬底上形成包括显示区域和透明区域的显示单元，以形成显示基板。
显示单元包括：位于显示区域，且依次设置在衬底上的驱动结构层、发光结构层和彩膜层；发光结构层包括：多个发光结构；每个发光结构包括：像素定义层、第一电极、有机发光层和第二电极；有机发光层位于像素定义层的开口区域内和像素定义层上；显示基板包括：位于显示区域的间隔区域，间隔区域位于相邻发光结构的像素定义层的开口区域之间，且与像素界定层在衬底上的正投影存在重叠区域；彩膜层包括：多个滤光片；相邻滤光片在衬底上的正投影存在重叠区域；相邻滤光片的重叠区域在衬底上的正投影与间隔区域在衬底上的正投影存在重叠区域。
显示基板为前述实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
在一种示例性实施例中，步骤S1包括：在衬底上形成位于显示区域的 包括第一极板的第一金属层；形成覆盖第一金属层的位于显示区域和透明区域的第一绝缘层；在第一绝缘层上形成位于显示区域的包括第二极板的金属氧化物层，第二极板在衬底上的正投影与第一极板在衬底上的正投影存在交叠区域，以形成第一存储电容；依次形成位于显示区域的第二绝缘层和第二金属层；第二金属层包括：第一扫描线和第二扫描线；形成覆盖第二金属层的位于显示区域和透明区域的第三绝缘层；在第三绝缘层上形成位于显示区域的第三金属层，第三金属层包括第一电源线、第二电源线、补偿线、数据线和第三极板，第三极板在衬底上的正投影与第二极板在衬底上的正投影存在交叠区域，以形成第二存储电容，第三极板通过过孔连接第一极板；形成覆盖第三金属层的位于显示区域和透明区域的第四绝缘层和平坦层；在平坦层上形成第一电极；依次形成像素定义层、有机发光层和阴极；形成封装层；在封装层上形成彩膜层。
在一种示例性实施例中，在封装层上形成彩膜层包括：在封装层上形成彩膜层和遮挡层。
本公开实施例还提供了一种显示装置，包括前述任一实施例提供的显示基板。
在一种示例性实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (20)

  1. 一种显示基板，包括：衬底和设置在所述衬底上的多个显示单元；所述显示单元包括：显示区域和透明区域；所述显示单元包括：位于所述显示区域，且依次设置在所述衬底上的驱动结构层、发光结构层和彩膜层；所述发光结构层包括：多个发光结构；每个发光结构包括：像素定义层、第一电极、有机发光层和第二电极；所述有机发光层位于所述像素定义层的开口区域内和所述像素定义层上；所述彩膜层包括：多个滤光片；
    所述显示基板包括：位于所述显示区域的间隔区域，所述间隔区域位于相邻发光结构的像素定义层的开口区域之间，且所述间隔区域在衬底上的正投影与所述像素定义层在衬底上的正投影存在重叠区域；
    相邻滤光片在所述衬底上的正投影存在重叠区域；相邻滤光片的重叠区域在衬底上的正投影与所述间隔区域在衬底上的正投影存在重叠区域。
  2. 根据权利要求1所述的显示基板，其中，多个发光结构包括：第一发光结构、第二发光结构、第三发光结构和第四发光结构；所述第一发光结构和所述第二发光结构沿第一方向排布，所述第三发光结构和所述第四发光结构沿第一方向排布；所述第一发光结构和所述第三发光结构沿第二方向排布，所述第二发光结构和所述第四发光结构沿第二方向排布；
    多个滤光片包括：第一颜色滤光片、第二颜色滤光片和第三颜色滤光片；三种颜色的滤光片分别设置在四个发光结构的其中三个发光结构上；
    其中，所述第一方向为一个显示单元内透明区域和显示区域的排布方向,所述第二方向垂直于所述第一方向，所述第一颜色、所述第二颜色和所述第三颜色为红色、蓝色和绿色中的一种，且三种颜色互不相同。
  3. 根据权利要求2所述的显示基板，其中，所述驱动结构层包括：多个沿第一方向延伸的第一扫描线和第二扫描线、多个沿第二方向延伸的第一电源线、第二电源线、数据线和补偿线以及沿第一方向排布的第一驱动结构、第二驱动结构、第三驱动结构和第四驱动结构；
    所述第一驱动结构位于所述第二驱动结构靠近所述透明区域的一侧，所述第四驱动结构位于所述第三驱动结构远离所述透明区域的一侧；
    所述第一电源线位于所述第四驱动结构远离所述第三驱动结构的一侧；所述第二电源线位于所述第一驱动结构远离所述第二驱动结构的一侧；所述补偿线位于所述第二驱动结构和所述第三驱动结构之间；
    所述数据线包括：第一数据线、第二数据线、第三数据线和第四数据线；
    所述第一数据线与所述第一驱动结构连接，且位于所述第一驱动结构靠近所述第二驱动结构的一侧；所述第二数据线与所述第二驱动结构连接，且位于所述第二驱动结构靠近所述第一驱动结构的一侧；所述第三数据线与所述第三驱动结构连接，且位于所述第三驱动结构靠近所述第四驱动结构的一侧；所述第四数据线与所述第四驱动结构连接，且位于所述第四驱动结构靠近所述第三驱动结构的一侧；
    所述第一扫描线和所述第二扫描线分别位于所述驱动结构层的两侧；
    所述第一电源线沿第一方向的长度大于所述补偿线或所述数据线沿第一方向的长度，所述第二电源线沿第一方向的长度大于所述补偿线或所述数据线沿第一方向的长度。
  4. 根据权利要求3所述的显示基板，其中，所述第一驱动结构和所述第四驱动结构相对于所述补偿线镜像对称，所述第二驱动结构和所述第三驱动结构相对于所述补偿线镜像对称。
  5. 根据权利要求4所述的显示基板，其中，每个驱动结构包括：像素驱动电路，所述像素驱动电路包括：第一晶体管、第二晶体管、第三晶体管和存储电容；所述第二晶体管为驱动晶体管；所述存储电容包括：第一极板、第二极板和第三极板；
    所述第一晶体管的栅电极与所述第一扫描线连接，所述第一晶体管的第一极与所述数据线连接，所述第一晶体管的第二极与所述第二晶体管的栅电极连接，所述第二晶体管的第一极与所述第一电源线连接，所述第二晶体管的第二极与发光结构的第一电极连接，所述第三晶体管的栅电极与所述第二扫描线连接，所述第三晶体管的第一极通过补偿连接线与所述补偿线连接，所述第三晶体管的第二极与所述第二晶体管的第二极连接，所述发光结构的第二电极与所述第二电源线连接；所述第一极板和第三极板与所述第二晶体 管的第二极连接，所述第二极板与所述第二晶体管的栅电极连接；
    所述驱动结构层还包括：电源连接线、辅助电源线和补偿连接线；
    所述第二晶体管的第一极通过所述电源连接线与所述第一电源线连接；所述电源连接线与所述第一扫描线和第二扫描线同层设置，所述第一电源线通过过孔与所述电源连接线连接，在所述第一晶体管的栅电极与所述第三晶体管的栅电极之间形成双层走线；
    所述辅助电源线与所述第一扫描线和第二扫描线同层设置，所述第二电源线通过过孔与所述辅助电源线连接，在所述第一晶体管的栅电极与所述第三晶体管的栅电极之间形成双层走线；
    所述补偿连接线与所述第一极板同层设置，所述补偿连接线通过过孔与补偿线连接。
  6. 根据权利要求5所述的显示基板，其中，所述驱动结构层包括：依次叠层设置的第一金属层、第一绝缘层、金属氧化物层、第二绝缘层、第二金属层、第三绝缘层、第三金属层、第四绝缘层和平坦层；
    所述第一金属层包括第一极板和补偿连接线，所述金属氧化物层包括第二极板和所有晶体管的有源层，所述第二金属层包括第一扫描线、第二扫描线、电源连接线、辅助电源线和所有晶体管的栅电极，所述第三金属层包括：第一电源线、第二电源线、补偿线、数据线、第三极板和所有晶体管的源漏电极；所述平坦层设置有暴露出所述第二晶体管的第二极的过孔；
    所述第一极板在衬底上的正投影与所述第二极板在衬底上的正投影存在交叠区域，以形成第一存储电容，所述第三极板在衬底上的正投影与所述第二极板在衬底上的正投影存在交叠区域，以形成第二存储电容，所述第三极板与第一极板通过过孔连接。
  7. 根据权利要求6所述的显示基板，其中，所述第一极板在所述衬底上的正投影覆盖所述所有晶体管的有源层以及所述第二极板在所述衬底上的正投影；
    所述第一极板沿第二方向的长度大于所述第一晶体管的栅电极与所述第三晶体管的栅电极之间的距离。
  8. 根据权利要求7所述的显示基板，其中，所述第一晶体管和所述第二晶体管位于所述第二极板靠近所述第一扫描线的一侧，所述第三晶体管位于所述第二极板靠近所述第二扫描线的一侧。
  9. 根据权利要求8所述的显示基板，其中，所述第二驱动结构和所述第三驱动结构中的第二极板设置有开口；所述第二驱动结构的第二极板的开口设置在所述第二驱动结构靠近所述第三驱动结构的一侧，所述第三驱动结构的第二极板的开口设置在所述第三驱动结构靠近所述第二驱动结构的一侧；
    所述第一驱动结构和所述第四驱动结构中的平坦层过孔位于所述第三晶体管和所述第二极板之间；所述第一驱动结构中的平坦层过孔与所述第四驱动结构中的平坦层的过孔相对于补偿线镜像对称；
    所述第二驱动结构的平坦层过孔位于所述第二驱动结构的第二极板的开口内，所述第三驱动结构的平坦层过孔位于所述第三驱动结构的第二极板的开口内；所述第二驱动结构中的平坦层过孔与所述第三驱动结构中的平坦层过孔相对于补偿线镜像对称；
    所述第一驱动结构中的平坦层过孔与所述第二驱动结构中的平坦层过孔的排布方向与所述第一方向之间的夹角大于0度，小于90度。
  10. 根据权利要求9所述的显示基板，其中，所述第一发光结构的第一电极通过第一驱动结构中的平坦层过孔与第一驱动结构连接，所述第二发光结构的第一电极通过第四驱动结构中的平坦层过孔与第四驱动结构连接，所述第三发光结构的第一电极通过第二驱动结构中的平坦层过孔与第二驱动结构连接，所述第四发光结构的第一电极通过第三驱动结构中的平坦层过孔与第三驱动结构连接；
    所述第一发光结构的像素定义层的开口区域和所述第三发光结构的像素定义层的开口区域位于所述第一电源线和所述补偿线之间，且在所述衬底上的正投影与所述第一驱动结构和第二驱动结构在所述衬底上的正投影存在重叠区域；
    所述第二发光结构的像素定义层的开口区域和所述第四发光结构的像素定义层的开口区域位于所述补偿线和所述第二电源线之间，且在衬底上的正 投影与所述第三驱动结构和第四驱动结构在所述衬底上的正投影存在重叠区域。
  11. 根据权利要求10所述的显示基板，其中，所述第一驱动结构的平坦层过孔在所述衬底上的正投影与所述第一发光结构中的像素定义层的开口区域在衬底上的正投影不存在重叠区域；
    所述第二驱动结构的平坦层过孔在所述衬底上的正投影与所述第三发光结构中的像素定义层的开口区域在衬底上的正投影不存在重叠区域；
    所述第三驱动结构的平坦层过孔在所述衬底上的正投影与所述第四发光结构中的像素定义层的开口区域在衬底上的正投影不存在重叠区域；
    所述第四驱动结构的平坦层过孔在所述衬底上的正投影与所述第二发光结构中的像素定义层的开口区域在衬底上的正投影不存在重叠区域。
  12. 根据权利要求11所述的显示基板，其中，所述间隔区域包括第一间隔区域、第二间隔区域和第三间隔区域；
    所述第一间隔区域位于所述第一发光结构的像素定义层的开口区域与所述第三发光结构的像素定义层的开口区域之间；所述第二间隔区域位于所述第二发光结构的像素定义层的开口区域与所述第四发光结构的像素定义层的开口区域之间；所述第一间隔区域和所述第二间隔区域沿第一方向排布；
    所述第一间隔区域和所述第二间隔区域分别位于所述第三间隔区域的两侧，所述第三间隔区域在所述衬底上的正投影与位于所述第一扫描线和所述第二扫描线之间的所述补偿线在衬底上的正投影重合；
    所述第三间隔区域包括：沿第二方向依次设置的，且首尾相接的第一子间隔区域、第二子间隔区域和第三子间隔区域；所述第二子间隔区域位于所述第一子间隔区域和第三子间隔区域之间；
    所述第一子间隔区域位于所述第一发光结构的像素定义层的开口区域与所述第二发光结构的像素定义层的开口区域之间；所述第三子间隔区域位于第三发光结构的像素定义层的开口区域与所述第四发光结构的像素定义层的开口区域之间；
    所述第二子间隔区域位于所述第一间隔区域和所述第二间隔区域之间， 且与所述第一间隔区域和所述第二间隔区域沿第一方向排布。
  13. 根据权利要求12所述的显示基板，其中，当滤光片位于所述第一发光结构上时，所述滤光片在衬底上的正投影覆盖所述第一发光结构的像素定义层的开口区域、第一子间隔区域、所述第二子间隔区域在衬底上的正投影，且与位于显示区域的部分第二扫描线和部分第二电源线在衬底上的正投影存在重叠区域；
    当滤光片位于所述第二发光结构上时，所述滤光片在衬底上的正投影覆盖所述第二发光结构的像素定义层的开口区域、所述第二间隔区域、所述第一子间隔区域、所述第二子间隔区域在衬底上的正投影，且与位于显示区域的部分第二扫描线和部分第一电源线在衬底上的正投影存在重叠区域；
    当滤光片位于所述第三发光结构上时，所述滤光片在衬底上的正投影覆盖所述第三发光结构的像素定义层的开口区域在衬底上的正投影，且与部分第一间隔区域、部分第三子间隔区域、位于显示区域的部分第一扫描线和部分第二电源线在衬底上的正投影存在重叠区域；
    当滤光片位于所述第四发光结构上时，所述滤光片在衬底上的正投影覆盖所述第四发光结构的像素定义层的开口区域在衬底上的正投影，且与部分第二间隔区域、部分第三子间隔区域、位于显示区域的部分第一扫描线和部分第一电源线在衬底上的正投影存在重叠区域。
  14. 根据权利要求13所述的显示基板，其中，所述彩膜层在衬底上的正投影与驱动结构层中的平坦层过孔在衬底上的正投影不存在重叠区域。
  15. 根据权利要求14所述的显示基板，其中，所述显示基板还包括：遮挡层；
    所述遮挡层在衬底上的正投影与位于透明区域的第一扫描线和位于透明区域和部分显示区域的第二扫描线在衬底上的正投影存在重叠区域。
  16. 根据权利要求15所述的显示基板，其中，所述遮挡层包括：第一遮挡层和第二遮挡层；所述第二遮挡层位于所述第一遮挡层靠近所述衬底的一侧；
    所述第一遮挡层与多个滤光片中的其中一种颜色滤光片同层设置，所述 第二遮挡层与所述多个滤光片中的另一种颜色滤光片同层设置。
  17. 一种显示基板的制备方法，用于制作如权利要求1至16任一项所述的显示基板，所述方法包括：
    提供衬底；
    在衬底上形成包括显示区域和透明区域的显示单元，以形成显示基板；所述显示单元包括：位于所述显示区域，且依次设置在所述衬底上的驱动结构层、发光结构层和彩膜层；所述发光结构层包括：多个发光结构；每个发光结构包括：像素定义层、第一电极、有机发光层和第二电极；有机发光层位于像素定义层的开口区域内和所述像素定义层上；所述显示基板包括：位于显示区域的间隔区域，所述间隔区域位于相邻发光结构的像素定义层的开口区域之间，且与所述像素界定层在衬底上的正投影存在重叠区域；所述彩膜层包括：多个滤光片；相邻滤光片在所述衬底上的正投影存在重叠区域；相邻滤光片的重叠区域在衬底上的正投影与所述间隔区域在衬底上的正投影存在重叠区域。
  18. 根据权利要求17所述的制备方法，其中，所述在衬底上形成包括显示区域和透明区域的显示单元包括：
    在衬底上形成位于显示区域的包括第一极板的第一金属层；
    形成覆盖所述第一金属层的位于显示区域和透明区域的第一绝缘层；
    在所述第一绝缘层上形成位于显示区域的包括第二极板的金属氧化物层，所述第二极板在所述衬底上的正投影与所述第一极板在衬底上的正投影存在交叠区域，以形成第一存储电容；
    依次形成位于显示区域的第二绝缘层和第二金属层；所述第二金属层包括：第一扫描线和第二扫描线；
    形成覆盖第二金属层的位于显示区域和透明区域的第三绝缘层；
    在所述第三绝缘层上形成位于显示区域的第三金属层，所述第三金属层包括第一电源线、第二电源线、补偿线、数据线和第三极板，所述第三极板在衬底上的正投影与所述第二极板在衬底上的正投影存在交叠区域，以形成 第二存储电容，所述第三极板通过过孔连接第一极板；
    形成覆盖所述第三金属层的位于显示区域和透明区域的第四绝缘层和平坦层；
    在所述平坦层上形成第一电极；
    依次形成像素定义层、有机发光层和阴极；
    形成封装层；
    在封装层上形成彩膜层。
  19. 根据权利要求18所述的方法，其中，所述在封装层上形成彩膜层包括：
    在封装层上形成彩膜层和遮挡层；
    所述遮挡层在衬底上的正投影与位于透明区域的第一扫描线和位于透明区域和部分显示区域的第二扫描线在衬底上的正投影存在重叠区域。
  20. 一种显示装置，包括如权利要求1至16任一项所述的显示基板。
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