WO2021227029A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2021227029A1
WO2021227029A1 PCT/CN2020/090558 CN2020090558W WO2021227029A1 WO 2021227029 A1 WO2021227029 A1 WO 2021227029A1 CN 2020090558 W CN2020090558 W CN 2020090558W WO 2021227029 A1 WO2021227029 A1 WO 2021227029A1
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Prior art keywords
line
electrode
layer
transistor
electrode plate
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PCT/CN2020/090558
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English (en)
French (fr)
Inventor
李蒙
李永谦
王迎
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/090558 priority Critical patent/WO2021227029A1/zh
Priority to US17/266,085 priority patent/US11895879B2/en
Priority to EP20900749.1A priority patent/EP3993054B1/en
Priority to CN202080000746.6A priority patent/CN113950745A/zh
Publication of WO2021227029A1 publication Critical patent/WO2021227029A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/824—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80522—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, in particular to a display substrate, a preparation method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • PM Passive Matrix
  • AM Active Matrix
  • AMOLED is a current drive device that uses independent thin film transistors. (Thin Film Transistor, TFT for short) controls each sub-pixel, and each sub-pixel can continuously and independently drive to emit light.
  • Transparent display is an important personalized display field of display technology. It refers to the display of images in a transparent state. The viewer can not only see the image in the display device, but also see the scene behind the display device, which can realize virtual reality ( Virtual Reality, VR for short) and Augmented Reality (AR for short) and 3D display functions.
  • a transparent display device using AMOLED technology usually divides each pixel into a display area and a transparent area. The display area is provided with a pixel drive circuit and a light-emitting element to realize image display, and the transparent area realizes light transmission.
  • the present disclosure provides a display substrate including a plurality of display units, the display unit includes a display area and a transparent area, the display area includes a plurality of sub-pixels; in a direction perpendicular to the display substrate, the sub-pixels
  • the pixel includes a first metal layer, a semiconductor layer, a second metal layer, and a third metal layer disposed on a substrate.
  • the first metal layer includes a first electrode plate
  • the semiconductor layer includes a second electrode plate
  • the first metal layer includes a second electrode plate.
  • the two metal layers include a first scan line and a second scan line that define a sub-pixel row, the third metal layer includes a third plate, and a first power line and a second power line that define the plurality of sub-pixels , Compensation line and data line;
  • the orthographic projection of the second electrode plate on the substrate and the orthographic projection of the first electrode plate on the substrate have an overlapping area to form a first storage capacitor, the third electrode plate There is an overlap area between the orthographic projection on the substrate and the orthographic projection of the second electrode plate on the substrate to form a second storage capacitor, and the third electrode plate is connected to the first electrode plate through a via;
  • the third metal layer further includes at least one auxiliary cathode, the at least one auxiliary cathode is disposed in the transparent area, and the at least one auxiliary cathode is connected to the second power line.
  • the display area includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel provided with a pixel driving circuit, and the four sub-pixels are arranged in a parallel manner.
  • At least one of the first metal layer and the semiconductor layer of the first sub-pixel and the fourth sub-pixel is arranged in mirror symmetry with respect to the compensation line, and the second sub-pixel And at least one of the first metal layer and the semiconductor layer of the third sub-pixel is arranged in mirror symmetry with respect to the compensation line.
  • the pixel driving circuit includes a first transistor, a second transistor, a third transistor, and a storage capacitor, a gate electrode of the first transistor is connected to the first scan line, and the first The first electrode of the transistor is connected to the data line, the second electrode of the first transistor is connected to the gate electrode of the second transistor, and the first electrode of the second transistor is connected to the first power line, The second electrode of the second transistor is connected to the first electrode of the organic electroluminescent diode, the gate electrode of the third transistor is connected to the second scan line, and the first electrode of the third transistor is connected through compensation The line is connected to the compensation line, the second electrode of the third transistor is connected to the second electrode of the second transistor, and the second electrode of the organic electroluminescent diode is connected to the second power line; The first electrode plate and the third electrode plate are connected to the second electrode of the second transistor, and the second electrode plate is connected to the gate electrode of the second transistor.
  • the pixel driving circuit further includes a power connection line, and the first pole of the second transistor is connected to the first power line through the power connection line; the power connection line is connected to the power supply line.
  • the first scan line and the second scan line are arranged in the same layer, the first power line is connected to the power connection line through a via hole, and is between the gate electrode of the first transistor and the gate electrode of the third transistor. A double-layer routing is formed between.
  • the pixel driving circuit further includes an auxiliary power line, the auxiliary power line is provided in the same layer as the first scan line and the second scan line, and the second power line is connected to the second scan line through a via hole.
  • the auxiliary power line is connected to form a double-layer wiring between the gate electrode of the first transistor and the gate electrode of the third transistor.
  • the semiconductor layer further includes an active layer of a first transistor, an active layer of a second transistor, and an active layer of a third transistor, and the compensation connection line is connected to the first electrode plate.
  • the second electrode plate is arranged in the same layer as the active layer of the first transistor, the active layer of the second transistor and the active layer of the third transistor.
  • the first electrode plate serves as a shielding layer, and the shape of the first electrode plate includes a long rectangle. In a direction parallel to the compensation line, the length of the first electrode plate is Greater than the distance between the gate electrode of the first transistor and the gate electrode of the third transistor.
  • the auxiliary cathode includes an electrode block and a connecting bar, the electrode block is connected to the second power line through the connecting bar, and the area of the electrode block is the area of the transparent region 5% to 20%.
  • the shape of the electrode block in a plane parallel to the display substrate, includes any one of a circle, an ellipse, a rectangle, a trapezoid, a pentagon, a hexagon, and a dumbbell.
  • the connecting bars include any one or more of straight bars, folded lines and arc lines.
  • the display substrate further includes a shielding bar
  • the orthographic projection of the shielding bar on the base includes the first scan line, the second scan line, the first power line, and the second power line. Orthographic projection on the substrate.
  • the display substrate further includes a raised structure, the raised structure is arranged on the inner side of the edge of the transparent area, and the raised structure includes a wave-shaped shielding strip or a plurality of spaced apart
  • the protrusion forms a transparent area with a concave-convex inner edge or a transparent area with a wavy inner edge.
  • the shape of the protrusion includes any one of a circle, an ellipse, a rectangle, a trapezoid, a pentagon, a hexagon, and a dumbbell. Many kinds.
  • the protruding structure and the shielding strip are arranged in the same layer.
  • the present disclosure also provides a method for preparing a display substrate, the display substrate includes a plurality of display units, the display unit includes a display area and a transparent area, the display area includes a plurality of sub-pixels; the preparation method includes :
  • a first metal layer, a semiconductor layer, and a second metal layer are formed on the substrate;
  • the first metal layer includes a first electrode plate;
  • the semiconductor layer includes a second electrode plate, and the second electrode plate is on the positive side of the substrate.
  • the second metal layer includes a first scan line and a second scan line that define a sub-pixel row;
  • a third metal layer is formed; the third metal layer includes a third plate and a first power line, a second power line, a compensation line, and a data line that define the plurality of sub-pixels; the third plate is on the substrate There is an overlap area between the orthographic projection on the upper and the orthographic projection of the second electrode plate on the substrate to form a second storage capacitor, and the third electrode plate is connected to the first electrode plate through a via;
  • the three-metal layer also includes at least one auxiliary cathode, the at least one auxiliary cathode is disposed in the transparent area, and the at least one auxiliary cathode is connected to the second power line.
  • forming the first metal layer, the semiconductor layer, and the second metal layer in sequence on the substrate includes:
  • first metal layer including a first electrode plate and a compensation connection line on the substrate
  • a first insulating layer covering the first metal layer is formed, a semiconductor layer including a second electrode plate is formed on the first insulating layer, and the orthographic projection of the second electrode plate on the substrate and the first insulating layer There is an overlap area in the orthographic projection of a plate on the substrate to form a first storage capacitor;
  • a second insulating layer and a second metal layer disposed on the second insulating layer are formed.
  • the second insulating layer has the same pattern as the second metal layer.
  • the second metal layer includes a first scan line and a second scan line. Cable and power connection cable.
  • forming the third metal layer includes:
  • a third insulating layer covering the second metal layer is formed, a plurality of via holes are formed on the third insulating layer, and the plurality of via holes includes: a seventh via hole exposing the compensation connection line, exposing The tenth via hole of the first plate is exposed, and the eleventh via hole of the power connection line is exposed;
  • a third metal layer is formed on the third insulating layer, and the third metal layer includes a third plate, a first power line, a second power line, a compensation line, a data line, and at least one auxiliary cathode;
  • the third electrode plate passes through the tenth via hole with the The first plate is connected;
  • the compensation line is connected to the compensation line through the seventh via, and the first power line is connected to the power connection line through the eleventh via;
  • the at least one The auxiliary cathode is arranged in the transparent area, and the at least one auxiliary cathode is connected to the second power line.
  • the preparation method further includes:
  • anode Forming an anode and a connecting electrode on the flat layer, the anode is connected to the third electrode plate, and the connecting electrode is connected to the auxiliary cathode;
  • a shielding strip is formed on the packaging layer, and the orthographic projection of the shielding strip on the substrate includes the orthographic projection of the first scan line, the second scan line, the first power line, and the second power line on the substrate.
  • forming a shielding bar on the encapsulation layer includes:
  • a shielding strip and a raised structure are formed on the encapsulation layer, the raised structure is arranged on the inner side of the edge of the transparent area, and the raised structure includes a wave-shaped shielding strip or a plurality of raised protrusions arranged at intervals to form A transparent area with a concave-convex inner edge or a transparent area with a wavy inner edge.
  • the present disclosure also provides a display device including the aforementioned display substrate.
  • FIG. 1 is an equivalent circuit diagram of the pixel driving circuit of the present disclosure
  • FIG. 2 is a schematic diagram showing a structure of a substrate according to the present disclosure
  • FIG. 3 is a schematic diagram after the first metal layer pattern is formed in the present disclosure
  • Figure 4 is a cross-sectional view taken along the line A-A in Figure 3;
  • FIG. 5 is a schematic diagram after the semiconductor layer pattern is formed in the present disclosure.
  • Fig. 6 is a cross-sectional view taken along the line A-A in Fig. 5;
  • FIG. 7 is a schematic diagram after the second metal layer pattern is formed in the present disclosure.
  • Fig. 8 is a sectional view taken along the line A-A in Fig. 7;
  • FIG. 9 is a schematic diagram after the third insulating layer pattern is formed in the present disclosure.
  • Figure 10 is a cross-sectional view taken along the line A-A in Figure 9;
  • FIG. 11 is a schematic diagram after the third metal layer pattern is formed in the present disclosure.
  • Figure 12 is a cross-sectional view along the A-A direction in Figure 11;
  • FIG. 13 is a schematic diagram after the fourth insulating layer and the flat layer pattern are formed in the present disclosure.
  • Figure 14 is a cross-sectional view taken along the line A-A in Figure 13;
  • FIG. 15 is a schematic diagram after the transparent conductive layer pattern is formed in the present disclosure.
  • Figure 16 is a cross-sectional view taken along the line A-A in Figure 15;
  • FIG. 17 is a schematic diagram after forming a pixel definition layer, an organic light-emitting layer, and a cathode pattern according to the present disclosure
  • FIG. 18 is a schematic diagram of the present disclosure after forming an encapsulation layer pattern
  • 19 is a schematic plan view of the display substrate of the present disclosure.
  • FIG. 20 is a schematic diagram showing another structure of the substrate according to the present disclosure.
  • FIG. 21 is a schematic diagram showing another structure of the substrate in the present disclosure.
  • 1 display unit
  • 10 base
  • 11 first active layer
  • 21 Second active layer
  • 22 Second gate electrode
  • 23 Third source electrode
  • 65 flat layer
  • 70 anode
  • 71 pixel definition layer
  • 80 auxiliary cathode
  • 90 shielding strip
  • 91 protruding structure
  • 100 display area
  • 200 transparent area
  • connection should be interpreted broadly. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate piece, or internal communication between two components.
  • connection should be interpreted broadly. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate piece, or internal communication between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • it may be the drain electrode of the first electrode and the source electrode of the second electrode, or it may be the source electrode of the first electrode and the drain electrode of the second electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged.
  • electrical connection includes the case where constituent elements are connected together by elements having a certain electrical function.
  • An element having a certain electrical function is not particularly limited as long as it can transmit and receive electrical signals between connected constituent elements.
  • elements having a certain electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore, it also includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore also includes a state where an angle of 85° or more and 95° or less is included.
  • film and “layer” can be interchanged.
  • the “conductive layer” can be replaced by the “conductive film.”
  • the “insulating film” can sometimes be replaced with an “insulating layer.”
  • the display substrate of the present disclosure includes a plurality of display units arranged regularly, the display unit includes a display area and a transparent area, the display area is configured to realize image display, the transparent area is configured to realize light transmission, and the display area includes multiple Sub-pixels; in a direction perpendicular to the display substrate, the sub-pixels include a first metal layer, a semiconductor layer, a second metal layer, and a third metal layer disposed on a substrate, and the first metal layer includes a first electrode
  • the semiconductor layer includes a second electrode plate, the second metal layer includes a first scan line and a second scan line defining a sub-pixel row, and the third metal layer includes a third electrode plate and defines The first power line, the second power line, the compensation line and the data line of the plurality of sub-pixels; the orthographic projection of the second electrode plate on the substrate overlaps the orthographic projection of the first electrode plate on the substrate Area to form a first storage capacitor, the orthographic projection of the third electrode plate on the substrate and the orthographic projection of the
  • the display area includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel where a pixel driving circuit is provided, and the four sub-pixels are arranged in a parallel manner.
  • At least one of the first metal layer and the semiconductor layer of the first sub-pixel and the fourth sub-pixel is arranged in mirror symmetry with respect to the compensation line, and the second sub-pixel and At least one of the first metal layer and the semiconductor layer of the third sub-pixel is arranged in mirror symmetry with respect to the compensation line.
  • the pixel driving circuit includes a first transistor, a second transistor, a third transistor, and a storage capacitor, a gate electrode of the first transistor is connected to the first scan line, and the first transistor
  • the first electrode of the first transistor is connected to the data line
  • the second electrode of the first transistor is connected to the gate electrode of the second transistor
  • the first electrode of the second transistor is connected to the first power line
  • the second electrode of the second transistor is connected to the first electrode of the organic electroluminescent diode
  • the gate electrode of the third transistor is connected to the second scan line
  • the first electrode of the third transistor is connected to the compensation connecting line.
  • the second electrode of the third transistor is connected to the second electrode of the second transistor, and the second electrode of the organic electroluminescent diode is connected to the second power line;
  • the first electrode plate and the third electrode plate are connected to the second electrode of the second transistor, and the second electrode plate is connected to the gate electrode of the second transistor.
  • the pixel driving circuit further includes a power connection line, the first pole of the second transistor is connected to the first power line through the power connection line; the power connection line is connected to the The first scan line and the second scan line are arranged in the same layer, and the first power line is connected to the power connection line through a via hole between the gate electrode of the first transistor and the gate electrode of the third transistor Form a double-layer wiring.
  • the pixel driving circuit further includes an auxiliary power supply line, the auxiliary power supply line is provided in the same layer as the first scan line and the second scan line, and the second power supply line is connected to the second scan line through the via hole.
  • the auxiliary power line is connected to form a double-layer wiring between the gate electrode of the first transistor and the gate electrode of the third transistor.
  • the compensation connection line is arranged in the same layer as the first electrode plate, and the second electrode plate is connected to the active layer of the first transistor, the active layer of the second transistor, and the third electrode.
  • the active layer of the transistor is arranged in the same layer.
  • the first electrode plate serves as a shielding layer, and the shape of the first electrode plate includes an elongated rectangle. In a direction parallel to the compensation line, the length of the first electrode plate is greater than The distance between the gate electrode of the first transistor and the gate electrode of the third transistor.
  • the auxiliary cathode includes an electrode block and a connection bar, the electrode block is connected to the second power line through the connection bar, and the area of the electrode block is equal to that of the transparent region. 5% to 20%.
  • the shape of the electrode block in a plane parallel to the display substrate, includes any one or more of a circle, an ellipse, a rectangle, a trapezoid, a pentagon, a hexagon, and a dumbbell.
  • the connecting strips include any one or more of straight strips, folded lines, and arced lines.
  • the display substrate further includes a shielding bar which is arranged at the edge of the display area, or at the edge of the transparent area, or at the edge of the display area and the transparent area.
  • the orthographic projection of the shielding bar on the substrate includes orthographic projections of the first scan line, the second scan line, the first power line, and the second power line on the substrate.
  • the display substrate further includes a raised structure disposed on the inner side of the edge of the transparent area, and the raised structure includes a wave-shaped shielding strip or a plurality of spaced convex structures.
  • the shape of the protrusion includes any one or more of a circle, an ellipse, a rectangle, a trapezoid, a pentagon, a hexagon, and a dumbbell.
  • the protruding structure and the shielding strip are arranged in the same layer.
  • the display area includes three or four sub-pixels provided with pixel driving circuits, and the pixel driving circuit of each sub-pixel is configured to be connected to an organic electroluminescent diode.
  • FIG. 1 is an equivalent circuit diagram of the pixel driving circuit of the present disclosure. As shown in FIG. 1, the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor C ST , and the light-emitting element is an OLED.
  • the first transistor T1 is a switching transistor
  • the second transistor T2 is a driving transistor
  • the third transistor T3 is a compensation transistor.
  • the gate electrode of the first transistor T1 is connected to the first scan line Gn, the first electrode of the first transistor T1 is connected to the data line Dn, the second electrode of the first transistor T1 is connected to the gate electrode of the second transistor T2, and the first transistor T1 is used for Under the control of the first scan line Gn, the data signal transmitted by the data line Dn is received, so that the gate electrode of the second transistor T2 receives the data signal.
  • the gate electrode of the second transistor T2 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2 is connected to the first power line VDD, the second electrode of the second transistor T2 is connected to the first electrode of the OLED, and the second transistor T2 is used to generate a corresponding current in the second pole under the control of the data signal received by its gate electrode.
  • the gate electrode of the third transistor T3 is connected to the second scan line Sn, the first electrode of the third transistor T3 is connected to the compensation line Se, the second electrode of the third transistor T3 is connected to the second electrode of the second transistor T2, and the third transistor T3 is used for
  • the threshold voltage Vth and mobility of the second transistor T2 are extracted in response to the compensation timing to compensate the threshold voltage Vth.
  • the first electrode of the OLED is connected to the second electrode of the second transistor T2, and the second electrode of the OLED is connected to the second power line VSS.
  • the OLED is used for emitting light of corresponding brightness in response to the current of the second electrode of the second transistor T2.
  • the first storage capacitor C ST electrode of the second transistor T2 is connected to the gate electrode of the second storage capacitor C ST electrode of the second transistor T2 is connected to the second electrode, the storage capacitor C ST for storing the second gate transistor T2 The potential of the electrode.
  • the voltage of the first power line VDD can be set to be greater than the voltage of the second power line VSS, and the maximum voltage of the data signal transmitted by the data line Dn is less than the maximum voltage of the first scan line, and is also less than the first power source.
  • the voltage of line VDD can be set to be greater than the voltage of the second power line VSS, and the maximum voltage of the data signal transmitted by the data line Dn is less than the maximum voltage of the first scan line, and is also less than the first power source.
  • FIG. 2 is a schematic diagram of a structure of the display substrate of the present disclosure, and illustrates the structure of a display unit.
  • the display substrate includes a plurality of display units regularly arranged, each display unit includes a display area 100 and a transparent area 200, the display area 100 is configured to realize image display, and the transparent area 200 is configured to Realize the light transmission, so as to realize the image display in the transparent state, that is, the transparent display.
  • the display substrate includes a plurality of first signal lines and second signal lines, and the first signal line and the second signal line perpendicularly intersect to define a plurality of display units.
  • the first signal line includes a first scan line Gn and a second scan line Sn arranged horizontally
  • the second signal line includes a first power supply line VDD, a second power supply line VSS, a compensation line Se and four arranged vertically.
  • Data line Dn In an exemplary embodiment, the first scan line Gn and the second scan line Sn define one display row, one display row includes one sub-pixel row, the second scan line Sn is located on the upper side of the defined sub-pixel row, and the first The scan line Gn is located on the lower side of the defined sub-pixel row.
  • the second power supply line VSS of the present display unit is connected to the present display
  • the first power line VDD of the cell defines the display area 100 of the display unit
  • the second power line VSS of the display unit and the first power line VDD of the adjacent display unit define the transparent area 200 of the display unit.
  • the display area 100 is located on the right side of the display unit.
  • the display area 100 defined by the first power supply line VDD and the second power supply line VSS includes four sub-pixels where the pixel drive circuit is provided, so that the first signal line and the second signal line define four sub-pixels where the pixel drive circuit is provided.
  • the four sub-pixels of the driving circuit are arranged in parallel.
  • the four sub-pixels arranged in parallel are: a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4.
  • sub-pixels all refer to sub-pixels provided with a pixel driving circuit.
  • the first sub-pixel P1 is located on the left side of the display area, and is adjacent to the transparent area 200 of the present display unit
  • the fourth sub-pixel P4 is located on the right side of the display area, and is connected to the transparent area of another display unit.
  • the area 200 is adjacent
  • the second sub-pixel P2 and the third sub-pixel P3 are located between the first sub-pixel P1 and the fourth sub-pixel P4, the second sub-pixel P2 is adjacent to the first sub-pixel P1, and the third sub-pixel P3 is adjacent to the first sub-pixel P1.
  • the four sub-pixels P4 are adjacent.
  • the second power line VSS, the two data lines Dn, the compensation line Se, the two data lines Dn, and the first power line VDD are sequentially arranged, and the first power line A first sub-pixel is formed between VDD and the adjacent data line Dn, a fourth sub-pixel is formed between the second power line VSS and the adjacent data line Dn, and a second sub-pixel is formed between the compensation line Se and the adjacent data line Dn. Pixels and third sub-pixels. In this way, four sub-pixels are formed between the first power line VDD and the second power line VSS by providing one compensation line Se and four data lines Dn. Among the four data lines Dn, two data lines Dn are located between the compensation line Se and the second power supply line. Between the lines VSS, the other two data lines Dn are located between the compensation line Se and the first power line VDD.
  • the display area 100 further includes a plurality of connection lines, and the plurality of connection lines include at least a compensation connection line 51 and a power connection line 52.
  • the compensation connection line 51 is connected to the compensation line Se through the via hole, so that the compensation line Se provides compensation signals to the four sub-pixels through the compensation connection line 51
  • the power connection line 52 is connected to the first power line VDD through the via hole, so that the first power line VDD provides power signals to the four sub-pixels through the power connection line 52, forming a one-to-four structure of the first power line VDD and the compensation line Se.
  • the present disclosure shows that by designing the first power line and the compensation line as a one-to-four structure, the substrate of the present disclosure saves the number of signal lines, reduces the occupied space, has a simple structure, a reasonable layout, makes full use of layout space, and improves space utilization. Conducive to improving resolution and transparency.
  • the pixel driving circuit in each sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor.
  • the first transistor T1 includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode
  • the second transistor T2 includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode
  • the third transistor T3 includes a third active layer, a third gate electrode, a third source electrode, and a third drain electrode.
  • the storage capacitor includes a first plate 41, a second plate 42 and a third plate 43.
  • the first plate 41 and the second plate 42 form a first storage capacitor
  • the second plate 42 and the third plate 43 form a first storage capacitor
  • the potentials of the first plate 41 and the third plate 43 are the same, so the first storage capacitor and the second storage capacitor form a parallel structure, which effectively increases the storage capacity.
  • the pixel drive circuit structure of the first sub-pixel P1 and the pixel drive circuit structure of the fourth sub-pixel P4 are mirror-symmetrical with respect to the vertical axis (compensation line Se).
  • the pixel drive circuit structure of the second sub-pixel P2 is mirror-symmetrical to that of the third sub-pixel P3.
  • the pixel drive circuit structure is mirror-symmetrical with respect to the vertical axis (compensation line Se).
  • the first scan line Gn is connected to the first gate electrode of the first transistor T1 in each sub-pixel
  • the second scan line Sn is connected to the third gate electrode of the third transistor T3 in each sub-pixel.
  • the line Dn is connected to the first source electrode of the first transistor T1 in each sub-pixel
  • the compensation line Se is connected to the third source electrode of the third transistor T3 in each sub-pixel through a compensation connection line 51
  • the first power line VDD is connected through a power source
  • the line 52 is connected to the second source electrode of the second transistor T2 in each sub-pixel.
  • the first gate electrode of the first transistor T1 is connected to the first scan line Gn
  • the first source electrode of the first transistor T1 is connected to the data line Dn
  • the first transistor T1 The first drain electrode is connected to the second gate electrode of the second transistor T2.
  • the second gate electrode of the second transistor T2 is connected to the first drain electrode of the first transistor T1, the second source electrode of the second transistor T2 is connected to the first power supply line VDD through the power connection line 52, and the second transistor T2 is connected to the first power supply line VDD.
  • the drain electrode is connected to the third drain electrode of the third transistor T3 and the anode of the light-emitting element.
  • the third gate electrode of the third transistor T3 is connected to the second scan line Sn, the third source electrode of the third transistor T3 is connected to the compensation line Se through the compensation connection line 51, and the third drain electrode of the third transistor T3 is connected to the second transistor
  • the second drain electrode of T2 is connected to the anode of the light-emitting element.
  • the first electrode plate 41 is respectively connected to the second drain electrode of the second transistor T2 and the third drain electrode of the third transistor T3, and the second electrode plate 42 is respectively connected to the first drain electrode of the first transistor T1 and the second transistor T2.
  • the second gate electrode is connected, and the third electrode plate 43 is respectively connected to the second drain electrode of the second transistor T2 and the third drain electrode of the third transistor T3, so the first electrode plate 41 and the third electrode plate 43 have the same potential ,
  • the second electrode plate 42 has a different potential than the first electrode plate 41 and the third electrode plate 43, the first electrode plate 41 and the second electrode plate 42 form a first storage capacitor, the third electrode plate 43 and the second electrode plate 42 forms a second storage capacitor, and the first storage capacitor and the second storage capacitor are in a parallel structure.
  • each sub-pixel in a direction perpendicular to the display substrate, includes a first metal layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second metal layer, and a first metal layer stacked on a substrate. Three insulating layers, a third metal layer, a fourth insulating layer and a flat layer.
  • the first metal layer includes at least a first electrode plate 41 and a compensation connection line 51.
  • the first electrode plate 41 also serves as a shielding layer of the display substrate.
  • the first electrode plate 41 and the compensation connection line 51 are arranged in the same layer and formed by the same patterning process. .
  • the semiconductor layer includes at least the second electrode plate 42 and the active layers of the three transistors.
  • the second electrode plate 42 and the active layers of the three transistors are arranged in the same layer and formed by the same patterning process.
  • the second metal layer includes at least a first scan line Gn, a second scan line Sn, a power connection line 52, an auxiliary power line, and gate electrodes of three transistors.
  • the first scan line Gn, a second scan line Sn, and a power connection line 52 The auxiliary power line and the gate electrodes of the three transistors are arranged in the same layer, and are formed by the same patterning process.
  • the third metal layer includes at least a data line Dn, a first power line VDD, a second power line VSS, a third plate 43, and the source and drain electrodes of three transistors.
  • the data line Dn, the first power line VDD, and the second The power line VSS, the third plate 43, and the source and drain electrodes of the three transistors are arranged in the same layer, and are formed by the same patterning process.
  • the orthographic projection of the first electrode plate 41 on the substrate and the orthographic projection of the second electrode plate 42 on the substrate at least have an overlap area to form a first storage capacitor
  • the orthographic projection of the plate 42 on the substrate has at least an overlap area to form a second storage capacitor.
  • the first electrode plate 41 and the third electrode plate 43 are connected through a via hole, so that the potential of the first electrode plate 41 and the third electrode plate 43 are the same, forming a first storage capacitor and a second storage capacitor in a parallel structure.
  • the transparent area 200 is defined by the first scan line Gn, the second scan line Sn, the first power line VDD, and the second power line VSS.
  • the transparent area 200 includes an auxiliary cathode 80, an auxiliary cathode 80 and a second power source.
  • the line VSS is connected, and the auxiliary cathode 80 and the second power line VSS are arranged in the same layer and formed by the same patterning process.
  • the auxiliary cathode 80 is configured to reduce the diffraction effect of the transparent area, and on the other hand, the auxiliary cathode 80 is configured to provide a low-level signal to the cathode of the light emitting element in the display area 100.
  • Diffraction effect means that when light passes through obstacles such as slits, it will spread to different degrees, causing the light to deviate from the original straight line.
  • the width of the slit affects the distribution of the diffraction fringes.
  • the positions of the diffraction fringes are the same, which results in a significant diffraction effect.
  • the transparent area is a regular rectangular shape, so the diffraction effect is obvious, which causes the object behind the screen to be blurred, which seriously affects the transparent display effect.
  • the present disclosure changes the transparent area into an irregular shape by arranging an auxiliary cathode 80 in the transparent area 200.
  • the diffraction fringes When light passes through the irregularly shaped transparent area, the diffraction fringes are generated at different positions and the directions of the diffraction fringes are different, so the light is generated.
  • the diffraction fringes will not diffuse in one direction, but in multiple directions, thus greatly weakening the diffraction effect, avoiding the phenomenon of blurring of objects behind the screen, and improving the transparent display effect.
  • a structure in which the second power line VSS directly provides a low-level signal to the cathode of the light-emitting element is usually adopted.
  • an auxiliary cathode 80 is provided in the transparent area 200, and the auxiliary cathode 80 is connected to the cathode of the light-emitting element, which can effectively alleviate the voltage drop (IR Drop) of the large-scale transparent display and ensure the uniformity of the display.
  • the auxiliary cathode 80 is arranged in the transparent area 200, which is beneficial to simplify the structural layout of the display area, reduce the occupied space of each sub-pixel, increase the area ratio of the transparent area, and improve the resolution and transparency.
  • the "patterning process” referred to in the present disclosure includes film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping treatments.
  • the deposition can be any one or more of sputtering, evaporation and chemical vapor deposition
  • the coating can be any one or more of spraying and spin coating
  • the etching can be any of dry etching and wet etching.
  • “Thin film” refers to a layer of film made by depositing or coating a certain material on a substrate.
  • the "film” does not require a patterning process during the entire production process, the “film” can also be referred to as a "layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are formed at the same time through the same patterning process.
  • Each display unit includes a display area 100 and a transparent area 200, and the display area 100 includes a first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4.
  • the pixel driving circuit of each sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor.
  • Forming a first metal layer pattern includes: depositing a first metal film on a substrate, patterning the first metal film through a patterning process, and forming a first metal layer pattern on the substrate 10.
  • the first metal layer pattern includes a first metal layer pattern.
  • the compensation connecting line 51 is a strip structure with 4 sub-pixels, as shown in FIG. 3 and FIG. 4, and FIG. 4 is FIG. 3 Sectional view in the AA direction.
  • the first plate 41 serves as a plate of the first storage capacitor, and is configured to form a first storage capacitor with a second plate formed subsequently, and the first plate 41 also serves as a shielding layer.
  • the compensation connection line 51 is configured to connect to a compensation line formed subsequently, so that the compensation line provides a compensation signal to each sub-pixel.
  • the first electrode plate 41 is an elongated rectangle. Except for the position of the compensation connection line 51, the first electrode plate 41 completely covers the pixel driving circuit area of each sub-pixel. In order to achieve effective shielding, in the elongated direction, the length of the first electrode plate 41 is greater than the distance between the gate electrode of the first transistor and the gate electrode of the third transistor to be formed later.
  • the length of the first electrode plate 41 is greater than the distance between the first electrode of the first transistor and the first electrode of the third transistor to be formed later.
  • the first metal layer pattern in the first sub-pixel P1 and the first metal layer pattern in the fourth sub-pixel P4 are mirror-symmetrical with respect to the vertical axis
  • the first metal layer in the second sub-pixel P2 The pattern and the first metal layer pattern in the third sub-pixel P3 are mirror-symmetrical with respect to the vertical axis.
  • the first metal layer pattern is formed in the display area 100, and the transparent area 200 has no corresponding film layer.
  • Forming a semiconductor layer pattern includes: sequentially depositing a first insulating film and a semiconductor film on the substrate with the aforementioned pattern, and patterning the semiconductor film through a patterning process to form a first insulating layer covering the pattern of the first metal layer 61, and a semiconductor layer pattern formed on the first insulating layer 61.
  • the semiconductor layer includes a first active layer 11, a second active layer 21, a third active layer 31, and a second electrode provided in each sub-pixel.
  • the pattern of the plate 42 is shown in FIG. 5 and FIG. 6, and FIG. 6 is a cross-sectional view in the AA direction in FIG. 5.
  • the first active layer 11 serves as the active layer of the first transistor
  • the second active layer 21 serves as the active layer of the second transistor
  • the third active layer 31 serves as the active layer of the third transistor
  • the second plate 42 There is an overlap area between the orthographic projection on the substrate 10 and the orthographic projection of the first electrode plate 41 on the substrate 10, and the first electrode plate 41 and the second electrode plate 42 form a first storage capacitor.
  • the second plate 42 serves as a plate of the first storage capacitor and a plate of the second storage capacitor.
  • the second plate 42 is configured to form a second storage capacitor with a third plate formed subsequently.
  • the orthographic projection of the first active layer 11, the second active layer 21, and the third active layer 31 on the substrate 10 overlaps with the orthographic projection of the first electrode plate 41 on the substrate 10. Area, so that the first plate 41 as a shielding layer can shield the channel area of the first transistor, the second transistor and the third transistor to prevent light from affecting the channel and avoid the channel from generating light-generated leakage and affecting the display effect .
  • the orthographic projection of the first active layer 11, the second active layer 21, and the third active layer 31 on the substrate 10 are spaced apart from the orthographic projection of the second electrode plate 42 on the substrate 10, that is, the first active layer 11 There is no overlapping area between the second electrode plate 42, the second active layer 21 and the second electrode plate 42, and the third active layer 31 and the second electrode plate 42, which is beneficial to design the second electrode plate according to relevant requirements.
  • the channel width-to-length ratio of a transistor, a second transistor, and a third transistor are provided.
  • a gap 44 is provided between the second electrode plate 42 and the third active layer 31 in the first sub-pixel P1 and the fourth sub-pixel P4, and the second sub-pixel P2 and the third sub-pixel P3 are An opening 45 is provided in the middle of the second electrode plate 42 of the.
  • the semiconductor layer pattern in the first sub-pixel P1 and the semiconductor layer pattern in the fourth sub-pixel P4 are mirror-symmetrical with respect to the vertical axis
  • the semiconductor layer pattern in the second sub-pixel P2 is mirror-symmetrical with respect to the third sub-pixel.
  • the semiconductor layer pattern in P3 is mirror-symmetrical with respect to the vertical axis.
  • a metal oxide may be used for the semiconductor layer.
  • the semiconductor layer pattern is formed in the display area 100, and the transparent area 200 includes the substrate 10 and the first insulating layer 61 disposed on the substrate 10.
  • Forming a second metal layer pattern includes: sequentially depositing a second insulating film and a second metal film on the substrate on which the aforementioned pattern is formed, and patterning the second insulating film and the second metal film through a patterning process to form The second insulating layer 62 pattern and the second metal layer pattern disposed on the second insulating layer 62.
  • the second metal layer pattern includes a first scan line Gn, a second scan line Sn, and a power connection formed in each display unit.
  • the line 52 and the auxiliary power line 53, as well as the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 formed in each sub-pixel, are shown in FIGS. 7 and 8.
  • FIG. 8 is AA in FIG. Cross-sectional view.
  • the first scan line Gn and the second scan line Sn are arranged in parallel and extend straight along the horizontal direction.
  • the first scan line Gn is located on the upper side of the sub-pixel
  • the second scan line Sn is located on the lower side of the sub-pixel
  • the first gate electrode 12 It is an integrated structure connected to the first scan line Gn, and is arranged across the first active layer 11, and the second gate electrode 22 is arranged across the second active layer 21, and has an overlapping area with the second electrode plate 42
  • the third gate electrode 32 is an integral structure connected with the second scan line Sn, and straddles the third active layer 31.
  • the power connection line 52 includes a first connection bar perpendicular to the first scan line Gn and a second connection bar parallel to the first scan line Gn, and one end of the first connection bar and the second connection bar are connected to each other.
  • the first connecting bar is formed in the area where the first power supply line VDD is located in the display unit, and is configured to connect to the subsequently formed first power supply line VDD
  • the second connecting bar is arranged across 4 sub-pixels and is configured to provide high power to each sub-pixel.
  • Flat signal is formed in the area where the second power line VSS is located in the display unit, is perpendicular to the first scan line Gn, and is configured to be connected to the second power line VSS formed subsequently.
  • the first connection bar of the power connection line 52 and the auxiliary power supply line 53 are located between the first gate electrode 12 and the third gate electrode 32.
  • the second insulating layer 62 pattern is the same as the second metal layer pattern, that is, the second insulating layer 62 is located under the second metal layer, and there is no second insulating layer 62 in regions other than the second metal layer.
  • the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 in the first sub-pixel P1 and the fourth sub-pixel P4 are mirror-symmetrical with respect to the vertical axis, and the second sub-pixel P2 is mirror-symmetrical with respect to the vertical axis.
  • the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 in the third sub-pixel P3 are mirror-symmetrical with respect to the vertical axis.
  • this process further includes conductive treatment.
  • Conduction treatment is to use the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 as a shield for plasma treatment after the second metal layer pattern is formed.
  • the semiconductor layer in the area shielded by the third gate electrode 32 (that is, the area where the semiconductor layer overlaps the first gate electrode 12, the second gate electrode 22, and the third gate electrode) serves as the channel region of the transistor, and is not shielded by the second metal layer
  • the semiconductor layer of the region is processed into a conductive layer to form a conductive second electrode plate 42 and a conductive source/drain region.
  • the second metal layer pattern is formed in the display area 100, and the transparent area 200 includes the substrate 10 and the first insulating layer 61 disposed on the substrate 10.
  • Forming the third insulating layer pattern includes: depositing a third insulating film on the substrate formed with the aforementioned pattern, and patterning the third insulating film through a patterning process to form a pattern of the third insulating layer 63 covering the aforementioned structure, and the third insulating layer 63 is provided with a plurality of via patterns, the plurality of via patterns include: a first via V1 and a second via V2 located on both sides of the first gate electrode 12, and a third via located on both sides of the second gate electrode 22
  • the ninth via V9 located in the overlapping area of the second gate electrode 22 and the second electrode plate 42, the tenth via V10 located at the position of the first electrode plate 41, and the more An eleventh via V11
  • the third insulating layer 63 in the first via hole V1 and the second via hole V2 is etched away, exposing the surfaces at both ends of the first active layer 11.
  • the third via hole V3 is a via via.
  • the via via is composed of two half holes, one half hole is formed on the second active layer 21, and the other half hole is formed on the second connection bar of the power connection line 52
  • the third insulating layer 63 in the two half holes is etched away, so that the via hole composed of the two half holes simultaneously exposes the surface of the second active layer 21 and the second connection bar of the power connection line 52
  • the third insulating layer 63 in the fourth via hole V4 is etched away, exposing the surface of the second active layer 21.
  • the third insulating layer 63 in the fifth via hole V5 and the sixth via hole V6 is etched away, exposing the surfaces at both ends of the third active layer 31.
  • the seventh via hole V7 is located at the position where the compensation connection line 51 overlaps with the compensation line formed subsequently, each sub-pixel forms an eighth via hole V8, and the first insulating layer 61 and the first insulating layer 61 and The third insulating layer 63 is etched away, exposing the surface of the compensation connection line 51.
  • the ninth via V9 is a transfer via.
  • the transfer via is composed of two half holes, one half hole is formed on the second gate electrode 22, the other half hole is formed on the second plate 42, and the two half holes are formed on the second gate electrode 22.
  • the third insulating layer 63 in the hole is etched away, so that the via hole composed of two half holes exposes the surface of the second gate electrode 22 and the surface of the second electrode plate 42 at the same time.
  • the tenth via V10 in the first sub-pixel P1 and the fourth sub-pixel P4 is located at the gap 44 between the second plate 42 and the third active layer 31, and the second sub-pixel P2 and the third sub-pixel P3
  • the tenth via hole V10 in V10 is located at the position of the opening 45 in the middle of the second electrode plate 42, and the first insulating layer 61 and the third insulating layer 63 in the tenth via hole V10 are etched away, exposing the first electrode plate 41 s surface.
  • the eleventh via V11 is located at the position of the first connection bar of the power connection line 52, a plurality of eleventh vias V11 are arranged at intervals, and the third insulating layer 63 in the eleventh via V11 is etched away, exposing The surface of the first connection bar of the power connection line 52.
  • the twelfth via V12 is located at the position of the auxiliary power line 53, and a plurality of twelfth vias V12 are arranged at intervals.
  • the third insulating layer 63 in the twelfth via V12 is etched away, exposing the auxiliary power line 53 surface.
  • the transparent area 200 includes a first insulating layer 61 and a third insulating layer 63 stacked on the substrate 10.
  • Forming the third metal layer pattern includes: depositing a third metal film on the substrate with the aforementioned pattern, patterning the third metal film through a patterning process, and forming a third metal layer on the third insulating layer 63
  • the pattern and the pattern of the auxiliary cathode 80, the third metal layer is formed in the display area 100, and the auxiliary cathode 80 is formed in the transparent area 200.
  • the third metal layer of the display area 100 includes: one first power line VDD, one second power line VSS, one compensation line Se, and four data lines Dn formed in each display unit, and
  • the first source electrode 13, the first drain electrode 14, the second source electrode 23, the second drain electrode 24, the third source electrode 33, the third drain electrode 34 and the third electrode plate 43 are patterned.
  • the auxiliary cathode 80 of the transparent area 200 and the second power line VSS are an integral structure connected to each other, as shown in FIG. 11 and FIG.
  • the first power supply line VDD, the second power supply line VSS, the compensation line Se, and the data line Dn are arranged in parallel and extend along the vertical direction, and the second power supply line VSS is arranged on a side adjacent to the transparent region 200 ,
  • the first power line VDD is arranged on the side away from the transparent region 200
  • the compensation line Se is arranged between the first power line VDD and the second power line VSS
  • the two data lines Dn are arranged on the second power line VSS and the compensation line Se In between, the other two data lines Dn are arranged between the first power supply line VDD and the compensation line Se.
  • the first power line VDD is connected to the power connection line 52 through a plurality of eleventh vias V11, so that the first power line VDD is connected to the second source electrode 23 of each sub-pixel through the power connection line 52, respectively.
  • a double-layer wiring is formed between the first gate electrode 12 and the third gate electrode 32, which ensures the reliability of power signal transmission and reduces the resistance of the first power line VDD.
  • the double-layered wiring includes the power connection line 52 of the second metal layer and the first power line VDD of the third metal layer.
  • the second power line VSS is connected to the auxiliary power line 53 through a plurality of twelfth vias V12, and a double-layer wiring is formed between the first gate electrode 12 and the third gate electrode 32 to ensure the reliability of power signal transmission. And the resistance of the second power supply line VSS is reduced.
  • the double-layered wiring includes the auxiliary power line 53 of the second metal layer and the second power line VSS of the third metal layer.
  • the widths of the first power line VDD and the second power line VSS are both greater than the width of the compensation line Se, and the first power line VDD
  • the widths of the second power supply line VSS and the second power supply line VSS are both larger than the width of the data line Dn, which can further reduce the resistance of the first power supply line VDD and the second power supply line VSS.
  • the compensation line Se is connected to the compensation connection line 51 through the seventh via hole V7, so that the compensation line Se is respectively connected to the third source electrode 33 of each sub-pixel through the compensation connection line 51.
  • the compensation line Se is arranged in the middle of the display area 100, it is connected to the third transistors of the sub-pixels on both sides through the compensation connection line 51, and the third transistors of the sub-pixels on the left and right sides are arranged symmetrically with respect to the compensation line Se.
  • This symmetrical design As a result, each display unit only needs to use one compensation line Se, which can ensure that the RC delay of the compensation signal before being written into the transistor is basically the same, and the display uniformity is ensured.
  • the first source electrode 13 is an integrated structure connected to the data line Dn, so that each data line Dn is respectively connected to the first source electrode 13 of the sub-pixel where it is located, and the first source electrode 13 passes through the first pass.
  • the hole V1 is connected to one end of the first active layer 11, the first drain electrode 14 is connected to the other end of the first active layer 11 through the second via hole V2, and the first drain electrode 14 also passes through the ninth pass of the transfer structure.
  • the hole V9 is connected to the second gate electrode 22 and the second electrode plate 42 at the same time, so that the first drain electrode 14, the second gate electrode 22 and the second electrode plate 42 have the same potential.
  • the second source electrode 23 is connected to the power connection line 52 and one end of the second active layer 21 at the same time through the third via hole V3 of the switching structure, so as to realize the connection of the second source electrode 23 and the first power line VDD.
  • the drain electrode 24 is connected to the other end of the second active layer 21 through the fourth via V4.
  • the third source electrode 33 is connected to one end of the third active layer 31 through the fifth via hole V5, and at the same time is connected to the compensation connection line 51 through the eighth via hole V8, thereby realizing the connection between the third source electrode 33 and the compensation line Se.
  • the third drain electrode 34 is connected to the other end of the third active layer 31 through the sixth via hole V6.
  • the second drain electrode 24, the third drain electrode 34, and the third electrode plate 43 are an integral structure connected to each other.
  • the third electrode plate 43 is connected to the first electrode plate 41 through the tenth via V10, so the second drain electrode 24 is at the same time Connected to the first electrode plate 41 and the third electrode plate 43, and the third drain electrode 34 is connected to the first electrode plate 41 and the third electrode plate 43 at the same time, realizing the second drain electrode 24, the third drain electrode 34, and the first
  • the electrode plate 41 and the third electrode plate 43 have the same potential.
  • the first source electrode 13, the first drain electrode 14, the second source electrode 23, the second drain electrode 24, and the third source electrode 33 in the first sub-pixel P1 and the fourth sub-pixel P4 The third drain electrode 34 and the third electrode plate 43 are mirror-symmetrical with respect to the vertical axis.
  • the first source electrode 13, the first drain electrode 14, the second source electrode 23, and the second sub-pixel P2 and the third sub-pixel P3 are The second drain electrode 24, the third source electrode 33, the third drain electrode 34, and the third electrode plate 43 are mirror-symmetrical with respect to the vertical axis.
  • the auxiliary cathode 80 is configured to reduce the diffraction effect of the transparent area.
  • the transparent area 200 is changed from a regular rectangle to an irregular shape, and different positions of the transparent area 200 have different slit widths.
  • the diffraction fringes are generated in different positions and the directions of the diffraction fringes are different. Therefore, the diffraction fringes generated by the light will not diffuse in one direction, but in multiple directions. The diffraction effect is weakened, the blur phenomenon of objects behind the screen is avoided, and the transparent display effect is improved.
  • the auxiliary cathode 80 of the transparent area 200 includes an electrode block 801 and a connecting bar 802.
  • the electrode block 801 is connected to the second power line VSS through the connecting bar 802.
  • the electrode block 801 may include a circle, an oval, Any one or more of rectangles, trapezoids, pentagons, hexagons, and dumbbell shapes.
  • the connecting strips 802 can be any one or more of straight lines, fold lines, and arc lines. The present disclosure is here. Do not make specific restrictions.
  • the width of the electrode block 801 is greater than the width of the connection bar 802, and in the direction perpendicular to the second power line VSS, the length of the connection bar 802 is greater than that of the electrode block. The length of 801.
  • the position of the auxiliary cathode 80 may be set to be adjacent to the first scan line Gn, or to be adjacent to the second scan line Sn, or to be located between the first scan line Gn and the second scan line Gn.
  • the transparent area 200 may be provided with one auxiliary cathode 80, or two or more auxiliary cathodes 80 may be provided, and the area of the electrode block 801 may be 5% to 20% of the area of the transparent area 200, which is not specifically limited in this disclosure. .
  • the transparent area 200 includes the first insulating layer 61 and the third insulating layer 63 stacked on the substrate 10, and the third insulating layer 63. Auxiliary cathode 80.
  • Forming the fourth insulating layer and the flat layer pattern includes: first depositing the fourth insulating film on the substrate with the aforementioned pattern, and then coating the flat film, and performing the masking, exposure and development of the flat film, The four insulating films are etched to form a pattern of the fourth insulating layer 64 covering the aforementioned structure, and a pattern of a flat (PLN) layer 65 disposed on the fourth insulating layer 64. A plurality of patterns are provided on the fourth insulating layer 64 and the flat layer 65.
  • the multiple via patterns at least include: a thirteenth via V13 located at the position of the third electrode plate 43 in each sub-pixel of the display area 100, and a fourteenth via V13 located at the position of the auxiliary cathode 80 in the transparent area 200
  • the via hole V14 is shown in FIG. 13 and FIG. 14, and FIG. 14 is a cross-sectional view in the AA direction in FIG. 13.
  • the thirteenth via V13 is located at the gap 44 between the second electrode plate 42 and the third active layer 31, and in the second For the sub-pixel P2 and the third sub-pixel P3, the thirteenth via hole V13 is located at the position of the opening 45 of the second plate 42, and the fourth insulating layer 64 and the flat layer 65 in the thirteenth via hole V13 are etched away, The surface of the third electrode plate 43 is exposed, the fourth insulating layer 64 and the flat layer 65 in the fourteenth via V14 are etched away, and the surface of the auxiliary cathode 80 is exposed.
  • the transparent area 200 includes a first insulating layer 61 and a third insulating layer 63 stacked on the substrate 10, an auxiliary cathode 80 disposed on the third insulating layer 63, and a fourth insulating layer covering the auxiliary cathode 80.
  • the layer 64 and the flat layer 65, the fourth insulating layer 64 and the flat layer 65 are provided with a fourteenth via V14 exposing the auxiliary cathode 80.
  • Forming a transparent conductive layer pattern including: depositing a transparent conductive film on the substrate with the aforementioned pattern, patterning the transparent conductive film through a patterning process, and forming a transparent conductive layer pattern on the flat layer 65, the transparent conductive layer including
  • the anode 70 and the connecting electrode 81 are formed in each sub-pixel of the display area 100.
  • the anode 70 in each sub-pixel is connected to the drain electrode of the second transistor T2 through the thirteenth via V13 in the corresponding sub-pixel, and is connected to
  • the electrode 81 is formed at the position where the auxiliary cathode 80 is located in the transparent area 100, and the connecting electrode 81 is connected to the auxiliary cathode 80 through the fourteenth via V14, as shown in FIGS.
  • the drain electrode of the second transistor T2 in each sub-pixel, the drain electrode of the third transistor T3, and the third electrode plate 43 are connected to each other in an integrated structure, the anode 70 and the second transistor T2 in each sub-pixel are connected to each other. Drain electrode connection.
  • the four anodes 70 may form a red light emitting unit, a green light emitting unit, a blue light emitting unit, and a white light emitting unit.
  • the four anodes 70 in the display area 100 may be rectangular, the four anodes 70 are arranged in a square shape, and the anode 70 on the upper left passes through the thirteenth via hole V13 of the first sub-pixel P1 and The third plate 43 of the first sub-pixel P1 is connected, the anode 70 on the upper right is connected to the third plate 43 of the fourth sub-pixel P4 through the thirteenth via hole V13 of the fourth sub-pixel P4, and the anode 70 on the lower left passes through the
  • the thirteenth via hole V13 of the second sub-pixel P2 is connected to the third electrode plate 43 of the second sub-pixel P2, and the anode 70 at the lower right passes through the thirteenth via hole V13 of the third sub-pixel P3 and the third sub-pixel P3.
  • the third electrode plate 43 is connected.
  • the four anodes 70 in the display area 100 may be in a strip shape, the four anodes 70 are arranged in a parallel manner, and each anode 70 corresponds to the position of the sub-pixel.
  • the arrangement of the anodes 70 in the display area 100 can be adjusted according to actual needs, which is not specifically limited in the present disclosure.
  • the transparent area 200 includes a first insulating layer 61 and a third insulating layer 63 stacked on the substrate 10, an auxiliary cathode 80 disposed on the third insulating layer 63, and a fourth insulating layer covering the auxiliary cathode 80.
  • the layer 64 and the flat layer 65, the connecting electrode 81 provided on the flat layer 65, and the connecting electrode 81 are connected to the auxiliary cathode 80 through the fourteenth via V14.
  • Forming a pixel definition layer, an organic light-emitting layer and a cathode pattern includes: coating a pixel definition film on the substrate forming the aforementioned pattern, and forming a pixel definition layer (Pixel Define Layer) 71 pattern through masking, exposure and development processes, The pixel defining layer 71 is formed in each sub-pixel in the display area 100, and the pixel defining layer 71 in each sub-pixel is formed with a pixel opening exposing the anode 70. Subsequently, an organic light-emitting layer 72 is formed in the aforementioned pixel opening, and the organic light-emitting layer 72 is connected to the anode 70.
  • a pixel definition layer Panel Define Layer
  • a cathode film is deposited, and the cathode film is patterned through a patterning process to form a cathode 73 pattern in the display area 100 and the transparent area 200.
  • the cathode 73 is connected to the organic light-emitting layer 72, and in the transparent area 200, the cathode 73 It is connected to the connection electrode 81. Since the connection electrode 81 is connected to the auxiliary cathode 80 and the auxiliary cathode 80 is connected to the second power supply line VSS, the cathode 73 is connected to the second power supply line VSS, as shown in FIG.
  • the encapsulation layer of the display area 100 includes a first encapsulation layer 74 made of an inorganic material, a second encapsulation layer 75 made of an organic material, and a third encapsulation layer 76 made of an inorganic material.
  • the first encapsulation layer 74 is disposed on the cathode 73, and the second encapsulation layer 75 It is disposed on the first encapsulation layer 74, and the third encapsulation layer 76 is disposed on the second encapsulation layer 75, forming a laminated structure of inorganic material/organic material/inorganic material.
  • the encapsulation layer of the transparent region 200 includes a first encapsulation layer 74 made of inorganic material and a third encapsulation layer 76 made of inorganic material.
  • the first encapsulation layer 74 is disposed on the cathode 73, and the third encapsulation layer 76 is disposed on the first encapsulation layer 74.
  • a laminated structure of inorganic material/inorganic material is formed, as shown in FIG. 18.
  • the first active layer 11, the first gate electrode 12, the first source electrode 13, and the first drain electrode 14 constitute the first transistor T1
  • the second active layer 21 the first The second gate electrode 22, the second source electrode 23 and the second drain electrode 24 constitute the second transistor T2
  • the third active layer 31 constitute the third gate electrode 32, the third source electrode 33 and the third drain electrode 34 constitute the third transistor T2.
  • the first electrode plate 41 and the second electrode plate 42 constitute a first storage capacitor
  • the second electrode plate 42 and the third electrode plate 43 constitute a second storage capacitor
  • the first storage capacitor and the second storage capacitor are connected in parallel to achieve The potential of the second gate electrode 22 of the sub-pixel is stored.
  • the first transistor T1, the second transistor T2, the third transistor T3, the first storage capacitor and the second storage capacitor in the first sub-pixel P1 and the fourth sub-pixel P4 are mirror-symmetrical with respect to the compensation line Se, and the second sub-pixel P2
  • the first transistor T1, the second transistor T2, the third transistor T3, the first storage capacitor and the second storage capacitor in the third sub-pixel P3 are mirror-symmetrical with respect to the compensation line Se.
  • the first gate electrode 12 is connected to the first scan line Gn
  • the first source electrode 13 is connected to the data line Dn
  • the first drain electrode 14 is connected to the second gate electrode 22 of the sub-pixel.
  • the second gate electrode 22 is connected to the first drain electrode 14 of the sub-pixel where it is located
  • the second source electrode 23 is connected to the first power line VDD through the power connection line 52
  • the second drain electrode 24 is connected to the anode of the sub-pixel where it is located.
  • the third gate electrode 32 is connected to the second scan line Sn
  • the third source electrode 33 is connected to the compensation line Se through the compensation connection line 51
  • the third drain electrode 34 is connected to the second drain electrode 24 of the sub-pixel where it is located.
  • the first substrate 41 is connected to the second drain electrode 24 and the third drain electrode 34 of the sub-pixel where it is located
  • the second substrate 42 is connected to the second gate electrode 22 and the first drain electrode 14 of the sub-pixel where it is located
  • the third substrate 43 is connected to the The second drain electrode 24 and the third drain electrode 34 of the sub-pixel are connected.
  • the anode 70 is connected to the second drain electrode 24 of the sub-pixel where it is located, and the cathode 73 covering all the sub-pixels is connected to the second power line VSS through the auxiliary cathode 80 of the transparent area 200, so that the organic light-emitting layer 72 between the anode 70 and the cathode 73 In response to the current of the second drain electrode 24 of the sub-pixel, light of corresponding brightness is emitted.
  • the first metal layer, the second metal layer, and the third metal layer may use a metal material, such as any one of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo).
  • a metal material such as any one of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo).
  • One or more, or alloy materials of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure or a multilayer composite structure, such as Mo/Cu/Mo.
  • the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), It can be a single layer, multiple layers or composite layers.
  • the first insulating layer is called the buffer layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer is called the gate insulating (GI) layer
  • the third insulating layer is called the interlayer insulation (ILD)
  • the fourth insulating layer is called a passivation (PVX) layer.
  • the thickness of the second insulating layer is smaller than the thickness of the third insulating layer, and the thickness of the first insulating layer is smaller than the sum of the thickness of the second insulating layer and the third insulating layer.
  • the flat layer can be made of organic materials
  • the transparent conductive film can be made of indium tin oxide ITO or indium zinc oxide IZO
  • the pixel definition layer can be made of polyimide, acrylic or polyethylene terephthalate.
  • the cathode can be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or made of any one or more of the above metals alloy.
  • the thickness of the first insulating layer is 3000 angstroms to 5000 angstroms
  • the thickness of the second insulating layer is 1000 angstroms to 2000 angstroms
  • the thickness of the third insulating layer is 4500 angstroms to 7000 angstroms
  • the fourth insulating layer has a thickness of 4500 angstroms to 7000 angstroms.
  • the thickness of the layer is 3000 angstroms to 5000 angstroms.
  • the thickness of the first metal layer is 80 angstroms to 1200 angstroms
  • the thickness of the second metal layer is 3000 angstroms to 5000 angstroms
  • the thickness of the third metal layer is 3000 angstroms to 9000 angstroms.
  • the semiconductor layer may employ an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten and indium and zinc, an oxide containing titanium and indium, and an oxide containing titanium and indium.
  • the semiconductor layer may be a single layer, or may be a double layer, or may be a multilayer.
  • the display substrate provided by the present disclosure includes:
  • a first metal layer disposed on the substrate 10 includes a first electrode plate 41 and a compensation connection line 51.
  • the first insulating layer 61 covers the first metal layer.
  • the semiconductor layer is arranged on the first insulating layer 61, the semiconductor layer includes the first active layer 11, the second active layer 21, the third active layer 31 and the second electrode plate 42.
  • the second electrode plate 42 is on the substrate 10 There is an overlap area between the orthographic projection of the first electrode plate 41 and the orthographic projection of the first electrode plate 41 on the substrate 10, and the second electrode plate 42 and the first electrode plate 41 form a first storage capacitor.
  • the second metal layer includes: a first scan line Gn, a second scan line Sn, a power connection line 52, an auxiliary power line 53, a first
  • the gate electrode 12, the second gate electrode 22 and the third gate electrode 32, the first gate electrode 12 and the first scan line Gn are an integral structure
  • the third gate electrode 32 and the second scan line Sn are an integral structure
  • the second insulating layer 62 has the same pattern as the second metal layer.
  • the third insulating layer 63 covering the second metal layer has a plurality of via holes respectively opened thereon, and the plurality of via holes includes: a first via hole V1 and a second via hole V2 exposing both ends of the first active layer 11, exposing The third via hole V3 and the fourth via hole V4 at both ends of the second active layer 21 are exposed, the fifth via hole V5 and the sixth via hole V6 at both ends of the third active layer 31 are exposed, and the compensation connection line 51 is exposed.
  • the seventh via V7 and the eighth via V8 simultaneously expose the second gate electrode 22 and the ninth via V9 of the second plate 42, and expose the tenth via V10 of the first plate 41, exposing the power supply
  • the plurality of eleventh via holes V11 of the connecting line 52 and the plurality of twelfth via holes V12 of the auxiliary power line 53 are exposed.
  • the third metal layer includes a first power line VDD, a second power line VSS, a compensation line Se, a data line Dn, a first source electrode 13, and a first drain electrode 14.
  • the second power line VSS is connected to the auxiliary power line 53 through the twelfth via hole V12
  • the compensation line Se is connected to the compensation connection line 51 through the seventh via hole V7, the first source electrode 13 and the data line Dn are in an integrated structure
  • the second The source electrode 23 is connected to the power connection line 52 through the third via hole V3, the third source electrode 33 is connected to the compensation connection line 51 through the eighth via hole V8, and the first drain electrode 14 is simultaneously connected to the second gate through the ninth via hole V9.
  • the electrode 22 is connected to the second electrode plate 42, the second drain electrode 24, the third drain electrode 34, and the third electrode plate 43 are an integral structure connected to each other.
  • the third electrode plate 43 is connected to the first electrode plate through the tenth via V10. 41 is connected, the orthographic projection of the third electrode plate 43 on the substrate 10 and the orthographic projection of the second electrode plate 42 on the substrate 10 have an overlapping area, and the second electrode plate 42 and the third electrode plate 43 form a second storage capacitor.
  • the fourth insulating layer 64 and the flat layer 65 covering the third metal layer are respectively provided with a plurality of via holes.
  • the plurality of via holes includes: a thirteenth via hole V13 exposing the drain electrode of the second transistor and an auxiliary The fourteenth via V14 of the cathode 80.
  • the transparent conductive layer is provided on the flat layer 65.
  • the transparent conductive layer includes an anode 70 and a connection electrode 81 pattern.
  • the anode 70 is connected to the drain electrode of the second transistor through a thirteenth via V13, and the connection electrode 81 passes through a fourteenth via V14. Connect with the auxiliary cathode 80.
  • the pixel definition layer 71 is disposed on the flat layer 65, and the pixel definition layer 71 defines a pixel opening exposing the anode 70 in each sub-pixel.
  • the organic light-emitting layer 72 provided in the opening area is connected to the anode 70.
  • Cathode 73, the cathode 73 of the display area 100 is connected to the organic light-emitting layer 72, and the cathode 73 of the transparent area 200 is connected to the auxiliary cathode 80 through the connecting electrode 81;
  • the encapsulation layer 74 of the above structure is covered.
  • the structure shown in the present disclosure and the preparation process thereof are only an exemplary description.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • the display area may include 3 sub-pixels.
  • the pixel driving circuit can be 5T1C or 7T1C.
  • other electrodes or leads may be provided in the film structure, and the present disclosure does not make specific limitations herein.
  • the display substrate provided by the present disclosure changes the transparent area into an irregular shape by arranging an auxiliary cathode in the transparent area.
  • the diffraction fringes produced by the light will not diffuse in one direction, but in multiple directions, which greatly weakens the diffraction effect and avoids objects behind the screen.
  • the blur phenomenon improves the transparent display effect.
  • the simulation shows that when the auxiliary cathode is not set, the diffraction value of the display substrate is 50%, and 4 serious diffraction spots are generated around the center point.
  • the diffraction value of the display substrate is 30%, and 4 slight diffraction spots are generated around the center point.
  • the display substrate provided by the present disclosure can also effectively alleviate the voltage drop of large-scale transparent display by providing auxiliary cathodes connected to the cathodes of the light-emitting elements in the transparent area, ensuring display uniformity, and simplifying the structural layout of the display area. Reduce the occupied space of each sub-pixel, increase the area ratio of the transparent area, and improve the resolution and transparency.
  • a second electrode plate made of metal oxide material is used as an electrode plate of a storage capacitor. The three-electrode plate forms a storage capacitor.
  • the first electrode plate and the third electrode plate have the same potential, and the second electrode plate has a different potential than the first electrode plate and the third electrode plate. Therefore, the first electrode plate and the second electrode plate Two parallel storage capacitors are formed between the third electrode plate and the third electrode plate, which effectively increases the capacity of the storage capacitor and is beneficial to realize high-resolution display.
  • the preparation process of the present disclosure can be realized by using existing mature preparation equipment, has little improvement to the existing process, can be well compatible with the existing preparation process, is simple to implement, easy to implement, high production efficiency, and low production cost. High yield rate.
  • FIG. 19 is a schematic plan view of the display substrate of the present disclosure.
  • the display substrate of the present disclosure includes a plurality of display units 1 arranged regularly.
  • Each display unit 1 includes a display area 100 and a transparent area 200.
  • the transparent area 200 is arranged on one side of the display area 100.
  • the transparent area 200 An auxiliary cathode 80 is provided therein, the display area 100 is configured to realize image display, and the transparent area 200 is configured to realize light transmission, thereby realizing transparent display.
  • the display substrate includes a plurality of first scan lines Gn and second scan lines Sn arranged horizontally, and a plurality of first power lines VDD and second power lines VSS arranged vertically, between the first scan lines Gn and the second scan lines Sn
  • One sub-pixel row is defined, and four sub-pixel columns are defined between the first power supply line VDD and the second power supply line VSS.
  • One sub-pixel row and four sub-pixel columns constitute four sub-pixels with pixel drive circuits, and four sub-pixels. Arranged side by side.
  • the display substrate also includes a plurality of compensation lines Se and data lines Dn vertically arranged.
  • the compensation lines Se are arranged between the first power line VDD and the second power line VSS, and the two data lines Dn are arranged on the second power line VSS and the compensation line. Between the lines Se, another two data lines Dn are arranged between the first power line VDD and the compensation line Se.
  • the four sub-pixels in one display area include: a first sub-pixel defined by a second power line VSS and a data line Dn, a second sub-pixel defined by a data line Dn and a compensation line Se, and a compensation line Se and a data line Dn defined
  • the third sub-pixel is the fourth sub-pixel defined by the data line Dn and the first power line VDD.
  • the transparent area 200 is defined by the first scan line Gn, the second scan line Sn, the first power line VDD, and the second power line VSS.
  • the transparent area 200 includes an auxiliary cathode 80 configured to reduce the diffraction effect of the transparent area. It is also configured to provide a low-level signal to the cathode of the light-emitting element in the display area 100.
  • the present disclosure changes the transparent area into an irregular shape by arranging an auxiliary cathode 80 in the transparent area 200. When light passes through the irregularly shaped transparent area, the diffraction fringes are generated at different positions and the directions of the diffraction fringes are different, so the light is generated.
  • an auxiliary cathode 80 is provided in the transparent area 200, and the auxiliary cathode 80 is connected to the cathode of the light-emitting element, which can effectively alleviate the voltage drop (IR Drop) of the large-scale transparent display and ensure the uniformity of the display.
  • the auxiliary cathode 80 is arranged in the transparent area 200, which is beneficial to simplify the structural layout of the display area, reduce the occupied space of each sub-pixel, increase the area ratio of the transparent area, and improve the resolution and transparency.
  • FIG. 20 is a schematic diagram showing another structure of the substrate according to the present disclosure.
  • the display substrate further includes a shielding bar 90.
  • the shielding bar 90 is arranged at the edge of the display area 100, or at the edge of the transparent area 200, or at the edges of the display area 100 and the transparent area 200, and the shielding bar 90 is configured to reduce the reflection phenomenon and diffraction effect of the display area.
  • the display area 100 and the transparent area 200 are provided with multiple signal lines. Since these signal lines are made of metal materials, when external light enters the display area 100 and the transparent area 200, not only the light incident on the metal signal lines appears metallic reflection , And make the light passing through these metal signal lines appear more complicated diffraction fringes, which leads to serious reflection phenomenon and diffraction effect, and reduces the transparent display effect. In addition, the reflection phenomenon and diffraction effect will also reduce the imaging quality of the camera in the transparent display device, causing the image captured by the camera to appear blurry, ghosting, and color fringing.
  • a shielding bar 90 is provided on the edges of the display area 100 and the transparent area 200, so that the shielding bar 90 is located on the light path where light enters the signal line, and the shielding bar 90 is used to shield the edges and the edges of the display area 100.
  • the metal signal line at the edge of the transparent area 200 reduces the light incident on or through the metal signal line, which not only effectively reduces the reflection of the signal line, but also effectively reduces the diffraction effect of the signal line, improves the transparent display effect, and improves the camera The imaging quality.
  • FIG. 21 is a schematic diagram showing another structure of the substrate in the present disclosure.
  • the display substrate further includes a shielding bar 90 and a raised structure 91, the shielding bar 90 is arranged on the edges of the display area 100 and the transparent area 200, and the raised structure 91 is arranged on at least one edge of the transparent area 200,
  • the shielding bar 90 is configured to reduce the light reflection phenomenon and diffraction effect of the display area, and the convex structure 91 is configured to reduce the diffraction effect of the transparent area.
  • the protrusion structure 91 may include a plurality of protrusions arranged at intervals, one end of the plurality of protrusions is located on the inner edge of the transparent area 200, and the other end extends toward the middle of the transparent area 200 to form a concave-convex shape.
  • the raised structure 91 may include a wave-shaped shielding strip to form a transparent area 200 having a wave-shaped inner edge. The present disclosure forms a concave-convex or wavy inner edge on the transparent area 200.
  • the concave-convex or wavy inner edge can produce diffraction stripes with different positions and different diffusion directions, which greatly weakens the diffraction effect and avoids the phenomenon of blurring objects behind the screen. , Improve the transparent display effect.
  • other structures of the display substrate are similar to the corresponding structures described in the foregoing embodiments.
  • the position of the shielding bar 90 may correspond to the positions of the first scan line Gn, the second scan line Sn, the first power line VDD, and the second power line VSS, and the position of the shielding bar 90 on the substrate
  • the orthographic projection may include the orthographic projection of the first scan line Gn, the second scan line Sn, the first power line VDD, and the second power line VSS on the substrate, and the shielding bar 90 may adopt a black matrix (BM for short), or At least two stacked color film layers, for example, a red color film layer and a blue color film layer.
  • the raised structure 91 may be arranged on one edge of the transparent area 200, or may be arranged on two opposite edges of the transparent area 200, or may be arranged on two adjacent edges of the transparent area 200. It may be arranged on each edge, or may be arranged on all the edges in the transparent area 200, so that the distance between the two edges at different positions is different, which is not specifically limited in the present disclosure.
  • the shape of the protrusion may include any one or more of a circle, an ellipse, a rectangle, a trapezoid, a pentagon, a hexagon, and a dumbbell.
  • the shape of the plurality of protrusions or waves may be the same or may be different.
  • the size of the multiple protrusions or waves may be the same or may be different, and the present disclosure does not make specific limitations herein.
  • the protruding structure 91 and the shielding strip 90 are arranged in the same layer, and are formed by the same process. In some possible implementations, the protruding structure 91 and the shielding strip 90 are an integral structure.
  • the present disclosure also provides a method for preparing a display substrate.
  • the display substrate includes a plurality of regularly arranged display units, the display unit includes a display area and a transparent area, the display area includes a plurality of sub-pixels; the preparation method includes :
  • first metal layer forms a first metal layer, a semiconductor layer, and a second metal layer on a substrate;
  • the first metal layer includes a first electrode plate;
  • the semiconductor layer includes a second electrode plate, and the second electrode plate is on the substrate There is an overlap area between the orthographic projection of the first plate and the orthographic projection of the first plate on the substrate to form a first storage capacitor;
  • the second metal layer includes a first scan line and a second scan that define a sub-pixel row String;
  • a third metal layer is formed; the third metal layer includes a third plate and a first power line, a second power line, a compensation line, and a data line that define the plurality of sub-pixels; the third plate There is an overlap area between the orthographic projection on the substrate and the orthographic projection of the second electrode plate on the substrate to form a second storage capacitor, and the third electrode plate is connected to the first electrode plate through a via;
  • the third metal layer further includes at least one auxiliary cathode, the at least one auxiliary cathode is disposed in the transparent area, and the at least one auxiliary cathode is connected to the second power line.
  • step S1 includes:
  • first metal layer including a first electrode plate and a compensation connection line on the substrate
  • a first insulating layer covering the first metal layer is formed, a semiconductor layer including a second electrode plate is formed on the first insulating layer, and the orthographic projection of the second electrode plate on the substrate and the first insulating layer There is an overlap area in the orthographic projection of a plate on the substrate to form a first storage capacitor;
  • a second insulating layer and a second metal layer disposed on the second insulating layer are formed.
  • the second insulating layer has the same pattern as the second metal layer.
  • the second metal layer includes a first scan line and a second scan line. Cable and power connection cable.
  • step S2 includes:
  • a third insulating layer covering the second metal layer is formed, a plurality of via holes are formed on the third insulating layer, and the plurality of via holes includes: a seventh via hole exposing the compensation connection line, exposing The tenth via hole of the first plate is exposed, and the eleventh via hole of the power connection line is exposed;
  • a third metal layer is formed on the third insulating layer, and the third metal layer includes a third plate, a first power line, a second power line, a compensation line, a data line, and at least one auxiliary cathode;
  • the third electrode plate passes through the tenth via hole with the The first plate is connected;
  • the compensation line is connected to the compensation line through the seventh via, and the first power line is connected to the power connection line through the eleventh via;
  • the at least one The auxiliary cathode is arranged in the transparent area, and the at least one auxiliary cathode is connected to the second power line.
  • the preparation method further includes:
  • anode Forming an anode and a connecting electrode on the flat layer, the anode is connected to the third electrode plate, and the connecting electrode is connected to the auxiliary cathode;
  • a shielding strip is formed on the packaging layer, and the orthographic projection of the shielding strip on the substrate includes the orthographic projection of the first scan line, the second scan line, the first power line, and the second power line on the substrate.
  • forming a shielding strip on the encapsulation layer includes:
  • a shielding strip and a raised structure are formed on the encapsulation layer, the raised structure is arranged on the inner side of the edge of the transparent area, and the raised structure includes a wave-shaped shielding strip or a plurality of raised protrusions arranged at intervals to form A transparent area with a concave-convex inner edge or a transparent area with a wavy inner edge.
  • the present disclosure also provides a display device including the display substrate of the foregoing embodiment.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and so on.

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Abstract

一种显示基板及其制备方法、显示装置。显示基板包括多个显示单元，显示单元包括显示区域和透明区域，显示区域包括多个子像素；在垂直于显示基板的方向上，子像素包括在基底上设置的第一金属层、半导体层、第二金属层和第三金属层，第一金属层包括第一极板，半导体层包括第二极板，第二金属层包括第一扫描线和第二扫描线，第三金属层包括第三极板、第一电源线、第二电源线、补偿线和数据线；第二极板与第一极板形成第一存储电容，第三极板与第二极板形成第二存储电容，第三极板通过过孔与第一极板连接；第三金属层还包括至少一个辅助阴极，至少一个辅助阴极设置在透明区域，至少一个辅助阴极与第二电源线连接。

Description

显示基板及其制备方法、显示装置 技术领域
本公开涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)为主动发光显示器件，具有发光、超薄、广视角、高亮度、高对比度、较低耗电、极高反应速度等优点。随着显示技术的不断发展，OLED技术越来越多的应用于柔性显示装置中，已逐渐成为极具发展前景的下一代显示技术。依据驱动方式的不同，OLED可分为无源矩阵驱动(Passive Matrix，简称PM)型和有源矩阵驱动(Active Matrix，简称AM)型两种，其中AMOLED是电流驱动器件，采用独立的薄膜晶体管(Thin Film Transistor，简称TFT)控制每个子像素，每个子像素皆可以连续且独立的驱动发光。
随着显示技术的不断发展，OLED技术越来越多的应用于透明显示中。透明显示是显示技术一个重要的个性化显示领域，是指在透明状态下进行图像显示，观看者不仅可以看到显示装置中的影像，而且可以看到显示装置背后的景象，可实现虚拟现实(Virtual Reality，简称VR)和增强现实(Augmented Reality，简称AR)和3D显示功能。采用AMOLED技术的透明显示装置通常是将每个像素划分为显示区域和透明区域，显示区域设置像素驱动电路和发光元件实现图像显示，透明区域实现光线透过。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，包括多个显示单元，所述显示单元包括显示区域和透明区域，所述显示区域包括多个子像素；在垂直于显示 基板的方向上，所述子像素包括在基底上设置的第一金属层、半导体层、第二金属层和第三金属层，所述第一金属层包括第一极板，所述半导体层包括第二极板，所述第二金属层包括限定出一子像素行的第一扫描线和第二扫描线，所述第三金属层包括第三极板以及限定出所述多个子像素的第一电源线、第二电源线、补偿线和数据线；所述第二极板在基底上的正投影与所述第一极板在基底上的正投影存在交叠区域，以形成第一存储电容，所述第三极板在基底上的正投影与所述第二极板在基底上的正投影存在交叠区域，以形成第二存储电容，所述第三极板通过过孔与所述第一极板连接；所述第三金属层还包括至少一个辅助阴极，所述至少一个辅助阴极设置在所述透明区域，所述至少一个辅助阴极与所述第二电源线连接。
在一些可能的实现方式中，所述显示区域包括设置像素驱动电路的第一子像素、第二子像素、第三子像素和第四子像素，所述四个子像素以并列方式排列。
在一些可能的实现方式中，所述第一子像素与所述第四子像素的第一金属层和半导体层中的至少一层相对于所述补偿线镜像对称设置，所述第二子像素与所述第三子像素的第一金属层和半导体层中的至少一层相对于所述补偿线镜像对称设置。
在一些可能的实现方式中，所述像素驱动电路包括第一晶体管、第二晶体管、第三晶体管和存储电容，所述第一晶体管的栅电极与所述第一扫描线连接，所述第一晶体管的第一极与所述数据线连接，所述第一晶体管的第二极与所述第二晶体管的栅电极连接，所述第二晶体管的第一极与所述第一电源线连接，所述第二晶体管的第二极与有机电致发光二极管的第一极连接，所述第三晶体管的栅电极与所述第二扫描线连接，所述第三晶体管的第一极通过补偿连接线与所述补偿线连接，所述第三晶体管的第二极与所述第二晶体管的第二极连接，所述有机电致发光二极管的第二极与所述第二电源线连接；所述第一极板和第三极板与所述第二晶体管的第二极连接，所述第二极板与所述第二晶体管的栅电极连接。
在一些可能的实现方式中，所述像素驱动电路还包括电源连接线，所述第二晶体管的第一极通过所述电源连接线与所述第一电源线连接；所述电源 连接线与所述第一扫描线和第二扫描线同层设置，所述第一电源线通过过孔与所述电源连接线连接，在所述第一晶体管的栅电极与所述第三晶体管的栅电极之间形成双层走线。
在一些可能的实现方式中，所述像素驱动电路还包括辅助电源线，所述辅助电源线与所述第一扫描线和第二扫描线同层设置，所述第二电源线通过过孔与所述辅助电源线连接，在所述第一晶体管的栅电极与所述第三晶体管的栅电极之间形成双层走线。
在一些可能的实现方式中，所述半导体层还包括第一晶体管的有源层、第二晶体管的有源层和第三晶体管的有源层，所述补偿连接线与所述第一极板同层设置，所述第二极板与所述第一晶体管的有源层、第二晶体管的有源层和第三晶体管的有源层同层设置。
在一些可能的实现方式中，所述第一极板作为遮挡层，所述第一极板的形状包括长条状的矩形，在平行于所述补偿线方向，所述第一极板的长度大于所述第一晶体管的栅电极与所述第三晶体管的栅电极之间的距离。
在一些可能的实现方式中，所述辅助阴极包括电极块和连接条，所述电极块通过所述连接条与所述第二电源线连接，所述电极块的面积为所述透明区域的面积的5％到20％。
在一些可能的实现方式中，在平行于显示基板的平面内，所述电极块的形状包括圆形、椭圆形、矩形、梯形、五边形、六边形和哑铃形中的任意一种或多种，所述连接条包括直线条、折线条和弧线条中的任意一种或多种。
在一些可能的实现方式中，所述显示基板还包括遮挡条，所述遮挡条在基底上的正投影包含所述第一扫描线、第二扫描线、第一电源线和第二电源线在基底上的正投影。
在一些可能的实现方式中，所述显示基板还包括凸起结构，所述凸起结构设置在所述透明区域的边缘的内侧，所述凸起结构包括波浪状遮挡条或者多个间隔设置的凸起，形成具有凹凸状内侧边缘的透明区域或者具有波浪状内侧边缘的透明区域。
在一些可能的实现方式中，在平行于显示基板的平面内，所述凸起的形 状包括圆形、椭圆形、矩形、梯形、五边形、六边形和哑铃形中的任意一种或多种。
在一些可能的实现方式中，所述凸起结构与所述遮挡条同层设置。
另一方面，本公开还提供了一种显示基板的制备方法，显示基板包括多个显示单元，所述显示单元包括显示区域和透明区域，所述显示区域包括多个子像素；所述制备方法包括：
在基底上形成第一金属层、半导体层和第二金属层；所述第一金属层包括第一极板；所述半导体层包括第二极板，所述第二极板在基底上的正投影与所述第一极板在基底上的正投影存在交叠区域，以形成第一存储电容；所述第二金属层包括限定出一子像素行的第一扫描线和第二扫描线；
形成第三金属层；所述第三金属层包括第三极板以及限定出所述多个子像素的第一电源线、第二电源线、补偿线和数据线；所述第三极板在基底上的正投影与所述第二极板在基底上的正投影存在交叠区域，以形成第二存储电容，所述第三极板通过过孔与所述第一极板连接；所述第三金属层还包括至少一个辅助阴极，所述至少一个辅助阴极设置在所述透明区域，所述至少一个辅助阴极与所述第二电源线连接。
在一些可能的实现方式中，在基底上依次形成第一金属层、半导体层和第二金属层，包括：
在基底形成包括第一极板和补偿连接线的第一金属层；
形成覆盖所述第一金属层的第一绝缘层，在所述第一绝缘层上形成包括第二极板的半导体层，所述第二极板在所述基底上的正投影与所述第一极板在基底上的正投影存在交叠区域，以形成第一存储电容；
形成第二绝缘层以及设置在所述第二绝缘层上的第二金属层，所述第二绝缘层与第二金属层图案相同，所述第二金属层包括第一扫描线、第二扫描线和电源连接线。
在一些可能的实现方式中，形成第三金属层，包括：
形成覆盖所述第二金属层的第三绝缘层，所述第三绝缘层上形成有多个 过孔，所述多个过孔包括：暴露出所述补偿连接线的第七过孔，暴露出所述第一极板的第十过孔，暴露出所述电源连接线的第十一过孔；
在所述第三绝缘层上形成第三金属层，所述第三金属层包括第三极板、第一电源线、第二电源线、补偿线、数据线和至少一个辅助阴极；所述第三极板在基底上的正投影与所述第二极板在基底上的正投影存在交叠区域，以形成第二存储电容，所述第三极板通过所述第十过孔与所述第一极板连接；所述补偿线通过所述第七过孔与所述补偿线连接，所述第一电源线通过所述第十一过孔与所述电源连接线连接；所述至少一个辅助阴极设置在所述透明区域，所述至少一个辅助阴极与所述第二电源线连接。
在一些可能的实现方式中，所述制备方法还包括：
形成覆盖所述第三金属层的第四绝缘层和平坦层；
在所述平坦层上形成阳极和连接电极，所述阳极与所述第三极板连接，所述连接电极与所述辅助阴极连接；
依次形成像素定义层、有机发光层、阴极和封装层，所述阴极与所述连接电极连接；
在所述封装层上形成遮挡条，所述遮挡条在基底上的正投影包含所述第一扫描线、第二扫描线、第一电源线和第二电源线在基底上的正投影。
在一些可能的实现方式中，在所述封装层上形成遮挡条包括：
在所述封装层上形成遮挡条和凸起结构，所述凸起结构设置在所述透明区域的边缘的内侧，所述凸起结构包括波浪状遮挡条或者多个间隔设置的凸起，形成具有凹凸状内侧边缘的透明区域或者具有波浪状内侧边缘的透明区域。
又一方面，本公开还提供了一种显示装置，包括前述的显示基板。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部 分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开像素驱动电路的等效电路图；
图2为本公开显示基板一种结构的示意图；
图3为本公开形成第一金属层图案后的示意图；
图4为图3中A-A向的剖面图；
图5为本公开形成半导体层图案后的示意图；
图6为图5中A-A向的剖面图；
图7为本公开形成第二金属层图案后的示意图；
图8为图7中A-A向的剖面图；
图9为本公开形成第三绝缘层图案后的示意图；
图10为图9中A-A向的剖面图；
图11为本公开形成第三金属层图案后的示意图；
图12为图11中A-A向的剖面图；
图13为本公开形成第四绝缘层和平坦层图案后的示意图；
图14为图13中A-A向的剖面图；
图15为本公开形成透明导电层图案后的示意图；
图16为图15中A-A向的剖面图；
图17为本公开形成像素定义层、有机发光层和阴极图案后的示意图；
图18为本公开形成封装层图案后的示意图；
图19为本公开显示基板的平面示意图；
图20为本公开显示基板另一种结构的示意图。
图21为本公开显示基板又一种结构的示意图。
附图标记说明:
1—显示单元；           10—基底；              11—第一有源层；
12—第一栅电极；        13—第一源电极；        14—第一漏电极；
21—第二有源层；        22—第二栅电极；        23—第三源电极；
24—第二漏电极；        31—第三有源层；        32—第三栅电极；
33—第三源电极；        34—第三漏电极；        41—第一极板；
42—第二极板；          43—第三极板；          51—补偿连接线；
52—电源连接线；        53—辅助电源线；        61—第一绝缘层；
62—第二绝缘层；        63—第三绝缘层；        64—第四绝缘层；
65—平坦层；            70—阳极；              71—像素定义层；
72—有机发光层；        73—阴极；              74—第一封装层；
75—第二封装层；        76—第三封装层；        74—第一封装层；
80—辅助阴极；          90—遮挡条；            91—凸起结构；
100—显示区域；         200—透明区域。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的实施方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的实施方式不局限于附图所示的形状或数值。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，可以是第一极为漏电极、第二极为源电极，或者可以是第一极为源电极、第二极为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以 上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开显示基板包括规则排布的多个显示单元，所述显示单元包括显示区域和透明区域，显示区域被配置为实现图像显示，透明区域被配置为实现光线透过，所述显示区域包括多个子像素；在垂直于显示基板的方向上，所述子像素包括在基底上设置的第一金属层、半导体层、第二金属层和第三金属层，所述第一金属层包括第一极板，所述半导体层包括第二极板，所述第二金属层包括限定出一子像素行的第一扫描线和第二扫描线，所述第三金属层包括第三极板以及限定出所述多个子像素的第一电源线、第二电源线、补偿线和数据线；所述第二极板在基底上的正投影与所述第一极板在基底上的正投影存在交叠区域，以形成第一存储电容，所述第三极板在基底上的正投影与所述第二极板在基底上的正投影存在交叠区域，以形成第二存储电容，所述第三极板通过过孔与所述第一极板连接；所述第三金属层还包括至少一个辅助阴极，所述至少一个辅助阴极设置在所述透明区域，被配置为降低透明区域的衍射效应，所述至少一个辅助阴极与所述第二电源线连接。
在示例性实施方式中，所述显示区域包括设置像素驱动电路的第一子像素、第二子像素、第三子像素和第四子像素，所述四个子像素以并列方式排列。
在示例性实施方式中，所述第一子像素与所述第四子像素的第一金属层和半导体层中的至少一层相对于所述补偿线镜像对称设置，所述第二子像素与所述第三子像素的第一金属层和半导体层中的至少一层相对于所述补偿线镜像对称设置。
在示例性实施方式中，所述像素驱动电路包括第一晶体管、第二晶体管、第三晶体管和存储电容，所述第一晶体管的栅电极与所述第一扫描线连接，所述第一晶体管的第一极与所述数据线连接，所述第一晶体管的第二极与所述第二晶体管的栅电极连接，所述第二晶体管的第一极与所述第一电源线连接，所述第二晶体管的第二极与有机电致发光二极管的第一极连接，所述第三晶体管的栅电极与所述第二扫描线连接，所述第三晶体管的第一极通过补 偿连接线与所述补偿线连接，所述第三晶体管的第二极与所述第二晶体管的第二极连接，所述有机电致发光二极管的第二极与所述第二电源线连接；所述第一极板和第三极板与所述第二晶体管的第二极连接，所述第二极板与所述第二晶体管的栅电极连接。
在示例性实施方式中，所述像素驱动电路还包括电源连接线，所述第二晶体管的第一极通过所述电源连接线与所述第一电源线连接；所述电源连接线与所述第一扫描线和第二扫描线同层设置，所述第一电源线通过过孔与所述电源连接线连接，在所述第一晶体管的栅电极与所述第三晶体管的栅电极之间形成双层走线。
在示例性实施方式中，所述像素驱动电路还包括辅助电源线，所述辅助电源线与所述第一扫描线和第二扫描线同层设置，所述第二电源线通过过孔与所述辅助电源线连接，在所述第一晶体管的栅电极与所述第三晶体管的栅电极之间形成双层走线。
在示例性实施方式中，所述补偿连接线与所述第一极板同层设置，所述第二极板与所述第一晶体管的有源层、第二晶体管的有源层和第三晶体管的有源层同层设置。
在示例性实施方式中，所述第一极板作为遮挡层，所述第一极板的形状包括长条状的矩形，在平行于所述补偿线方向，所述第一极板的长度大于所述第一晶体管的栅电极与所述第三晶体管的栅电极之间的距离。
在示例性实施方式中，所述辅助阴极包括电极块和连接条，所述电极块通过所述连接条与所述第二电源线连接，所述电极块的面积为所述透明区域的面积的5％到20％。
在示例性实施方式中，在平行于显示基板的平面内，所述电极块的形状包括圆形、椭圆形、矩形、梯形、五边形、六边形和哑铃形中的任意一种或多种，所述连接条包括直线条、折线条和弧线条中的任意一种或多种。
在示例性实施方式中，所述显示基板还包括遮挡条，所述遮挡条设置在所述显示区域的边缘，或者设置在所述透明区域的边缘，或者设置在所述显 示区域和透明区域的边缘，所述遮挡条在基底上的正投影包含所述第一扫描线、第二扫描线、第一电源线和第二电源线在基底上的正投影。
在示例性实施方式中，所述显示基板还包括凸起结构，所述凸起结构设置在所述透明区域的边缘的内侧，所述凸起结构包括波浪状遮挡条或者多个间隔设置的凸起，形成具有凹凸状内侧边缘的透明区域或者具有波浪状内侧边缘的透明区域。
在示例性实施方式中，所述凸起的形状包括圆形、椭圆形、矩形、梯形、五边形、六边形和哑铃形中的任意一种或多种。
在示例性实施方式中，所述凸起结构与所述遮挡条同层设置。
在示例性实施方式中，显示区域包括三个或四个设置像素驱动电路的子像素，每个子像素的像素驱动电路配置为连接有机电致发光二极管。图1为本公开像素驱动电路的等效电路图。如图1所示，像素驱动电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容C ST，发光元件为OLED。第一晶体管T1为开关晶体管，第二晶体管T2为驱动晶体管，第三晶体管T3为补偿晶体管。第一晶体管T1的栅电极连接第一扫描线Gn，第一晶体管T1的第一极连接数据线Dn，第一晶体管T1的第二极连接第二晶体管T2的栅电极，第一晶体管T1用于在第一扫描线Gn控制下，接收数据线Dn传输的数据信号，使第二晶体管T2的栅电极接收所述数据信号。第二晶体管T2的栅电极连接第一晶体管T1的第二极，第二晶体管T2的第一极连接第一电源线VDD，第二晶体管T2的第二极连接OLED的第一极，第二晶体管T2用于在其栅电极所接收的数据信号控制下，在第二极产生相应的电流。第三晶体管T3的栅电极连接第二扫描线Sn，第三晶体管T3的第一极连接补偿线Se，第三晶体管T3的第二极连接第二晶体管T2的第二极，第三晶体管T3用于响应补偿时序提取第二晶体管T2的阈值电压Vth以及迁移率，以对阈值电压Vth进行补偿。OLED的第一极连接第二晶体管T2的第二极，OLED的第二极连接第二电源线VSS，OLED用于响应第二晶体管T2的第二极的电流而发出相应亮度的光。存储电容C ST的第一极与第二晶体管T2的栅电极连接，存储电容C ST的第二极与第二晶体管T2的第二极连接，存储电容C ST用于存储第二晶体管T2的栅电极的电位。在一些可能的实现方式中，可以 设置第一电源线VDD的电压大于第二电源线VSS的电压，数据线Dn传输的数据信号的最大电压小于第一扫描线的最大电压，也小于第一电源线VDD的电压。
图2为本公开显示基板一种结构的示意图，示意了一个显示单元的结构。在平行于显示基板的方向上，显示基板包括规则排布的多个显示单元，每个显示单元包括显示区域100和透明区域200，显示区域100被配置为实现图像显示，透明区域200被配置为实现光线透过，从而实现透明状态下的图像显示，即透明显示。如图2所示，显示基板包括多条第一信号线和第二信号线，第一信号线和第二信号线垂直交叉限定出多个显示单元。对于一个显示单元，第一信号线包括水平设置的第一扫描线Gn和第二扫描线Sn，第二信号线包括垂直设置的第一电源线VDD、第二电源线VSS、补偿线Se和四条数据线Dn。在示例性实施方式中，第一扫描线Gn和第二扫描线Sn限定出一个显示行，一个显示行包括一个子像素行，第二扫描线Sn位于所限定子像素行的上侧，第一扫描线Gn位于所限定子像素行的下侧。在第一扫描线Gn和第二扫描线Sn所限定的子像素行内(即在第一扫描线Gn和第二扫描线Sn之间的区域)，本显示单元的第二电源线VSS与本显示单元的第一电源线VDD限定出本显示单元的显示区域100，本显示单元的第二电源线VSS与相邻显示单元的第一电源线VDD限定出本显示单元的透明区域200，透明区域200位于显示单元的左侧，显示区域100位于显示单元的右侧。第一电源线VDD和第二电源线VSS限定的显示区域100包括四个设置像素驱动电路的子像素，从而第一信号线和第二信号线限定出设置像素驱动电路的四个子像素，设置像素驱动电路的四个子像素采用并列方式排列。并列方式排列四个子像素分别是：第一子像素P1、第二子像素P2、第三子像素P3和第四子像素P4。后面描述中，子像素均是指设置像素驱动电路的子像素。
在示例性实施方式中，第一子像素P1位于显示区域的左侧位置，与本显示单元的透明区域200邻近，第四子像素P4位于显示区域的右侧位置，与另外一个显示单元的透明区域200邻近，第二子像素P2和第三子像素P3位于第一子像素P1和第四子像素P4之间，第二子像素P2与第一子像素P1邻近，第三子像素P3与第四子像素P4邻近。
在示例性实施方式中，沿着远离透明区域200的方向，第二电源线VSS、两条数据线Dn、补偿线Se、两条数据线Dn和第一电源线VDD依次设置，第一电源线VDD与邻近的数据线Dn之间形成第一子像素，第二电源线VSS与邻近的数据线Dn之间形成第四子像素，补偿线Se与邻近的数据线Dn之间分别形成第二子像素和第三子像素。这样，第一电源线VDD与第二电源线VSS之间通过设置1条补偿线Se和四条数据线Dn形成四个子像素，四条数据线Dn中两条数据线Dn位于补偿线Se与第二电源线VSS之间，另外两条数据线Dn位于补偿线Se与第一电源线VDD之间。
在示例性实施方式中，显示区域100还包括多条连接线，多条连接线至少包括补偿连接线51和电源连接线52。补偿连接线51通过过孔与补偿线Se连接，使得补偿线Se通过补偿连接线51向四个子像素提供补偿信号，电源连接线52通过过孔与第一电源线VDD连接，使得第一电源线VDD通过电源连接线52向四个子像素提供电源信号，形成第一电源线VDD和补偿线Se的一拖四结构。本公开显示基板通过将第一电源线和补偿线设计为一拖四结构，节省了信号线数量，减小了占用空间，结构简洁，布局合理，充分利用布图空间，提高了空间利用率，有利于提高分辨率和透明度。
如图2所示，显示区域的4个子像素中，每个子像素中的像素驱动电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容。第一晶体管T1包括第一有源层、第一栅电极、第一源电极和第一漏电极，第二晶体管T2包括第二有源层、第二栅电极、第二源电极和第二漏电极，第三晶体管T3包括第三有源层、第三栅电极、第三源电极和第三漏电极。存储电容包括第一极板41、第二极板42和第三极板43，第一极板41和第二极板42形成第一存储电容，第二极板42和第三极板43形成第二存储电容，第一极板41和第三极板43的电位相同，因而第一存储电容和第二存储电容形成并联结构，有效提高了存储容量。第一子像素P1的像素驱动电路结构与第四子像素P4的像素驱动电路结构相对于垂直轴(补偿线Se)镜像对称，第二子像素P2的像素驱动电路结构与第三子像素P3的像素驱动电路结构相对于垂直轴(补偿线Se)镜像对称。
在示例性实施方式中，第一扫描线Gn与每个子像素中第一晶体管T1的第一栅电极连接，第二扫描线Sn与每个子像素中第三晶体管T3的第三栅电极连接，数据线Dn与每个子像素中第一晶体管T1的第一源电极连接，补偿线Se通过补偿连接线51与每个子像素中第三晶体管T3的第三源电极连接，第一电源线VDD通过电源连接线52与每个子像素中第二晶体管T2的第二源电极连接。以第一子像素P1的像素驱动电路为例，第一晶体管T1的第一栅电极与第一扫描线Gn连接，第一晶体管T1的第一源电极与数据线Dn连接，第一晶体管T1的第一漏电极与第二晶体管T2的第二栅电极连接。第二晶体管T2的第二栅电极与第一晶体管T1的第一漏电极连接，第二晶体管T2的第二源电极通过电源连接线52与第一电源线VDD连接，第二晶体管T2的第二漏电极与第三晶体管T3的第三漏电极和发光元件的阳极连接。第三晶体管T3的第三栅电极与第二扫描线Sn连接，第三晶体管T3的第三源电极通过补偿连接线51与补偿线Se连接，第三晶体管T3的第三漏电极与第二晶体管T2的第二漏电极和发光元件的阳极连接。第一极板41分别与第二晶体管T2的第二漏电极和第三晶体管T3的第三漏电极连接，第二极板42分别与第一晶体管T1的第一漏电极和第二晶体管T2的第二栅电极连接，第三极板43分别与第二晶体管T2的第二漏电极和第三晶体管T3的第三漏电极连接，因此第一极板41和第三极板43具有相同的电位，第二极板42具有不同于第一极板41和第三极板43的电位，第一极板41和第二极板42形成第一存储电容，第三极板43和第二极板42形成第二存储电容，第一存储电容和第二存储电容为并联结构。
在示例性实施方式中，在垂直于显示基板的方向上，每个子像素包括在基底上叠设的第一金属层、第一绝缘层、半导体层、第二绝缘层、第二金属层、第三绝缘层、第三金属层、第四绝缘层和平坦层。第一金属层至少包括第一极板41和补偿连接线51，第一极板41还作为显示基板的遮挡层，第一极板41和补偿连接线51同层设置且通过同一次构图工艺形成。半导体层至少包括第二极板42以及三个晶体管的有源层，第二极板42以及三个晶体管的有源层同层设置且通过同一次构图工艺形成。第二金属层至少包括第一扫描线Gn、第二扫描线Sn、电源连接线52、辅助电源线以及三个晶体管的栅电极，第一扫描线Gn、第二扫描线Sn、电源连接线52、辅助电源线以及三 个晶体管的栅电极同层设置，且通过同一次构图工艺形成。第三金属层至少包括数据线Dn、第一电源线VDD、第二电源线VSS、第三极板43以及三个晶体管的源电极和漏电极，数据线Dn、第一电源线VDD、第二电源线VSS、第三极板43以及三个晶体管的源电极和漏电极同层设置，且通过同一次构图工艺形成。第一极板41在基底上的正投影与第二极板42在基底上的正投影至少存在交叠区域，形成第一存储电容，第三极板43在基底上的正投影与第二极板42在基底上的正投影至少存在交叠区域，形成第二存储电容。第一极板41和第三极板43通过过孔连接，使第一极板41和第三极板43的电位相同，形成并联结构的第一存储电容和第二存储电容。
如图2所示，透明区域200由第一扫描线Gn、第二扫描线Sn、第一电源线VDD和第二电源线VSS限定，透明区域200包括辅助阴极80，辅助阴极80和第二电源线VSS连接，辅助阴极80和第二电源线VSS同层设置且通过同一次构图工艺形成。一方面，辅助阴极80被配置为降低透明区域的衍射效应，另一方面，辅助阴极80被配置为向显示区域100中发光元件的阴极提供低电平信号。
衍射效应是指光线在穿过狭缝等障碍物时会发生不同程度的弯散传播，使得光线偏离原来的直线传播。衍射效应中，狭缝宽度影响衍射条纹的分布，具有相同狭缝宽度的位置处，产生衍射条纹的位置一致，从而会出现明显的衍射效应。一种显示透明基板中，透明区域为规则的矩形状，因而衍射效应明显，导致屏后物体虚化，严重影响了透明显示效果。本公开通过在透明区域200设置辅助阴极80，将透明区域改变成不规则形状，当光线经过不规则形状的透明区域时，由于产生衍射条纹的位置不同，产生衍射条纹的方向不同，因而光线产生衍射条纹不会朝着一个方向扩散，而是朝着多个方向扩散，因而大大弱化了衍射效应，避免了屏后物体虚化现象，提高了透明显示效果。一种大尺寸显示透明基板中，由于显示区域布局空间较小，通常采用第二电源线VSS直接向发光元件的阴极提供低电平信号的结构。本公开通过在透明区域200设置辅助阴极80，辅助阴极80与发光元件的阴极连接，可以有效缓解大尺寸透明显示的电压降(IR Drop)，保证了显示均一性。辅助阴极80设置在透明区域200，有利于简化显示区域的结构布局，减 小每个子像素的占用空间，提高透明区域的面积比，提高分辨率和透明度。
下面通过显示基板的制备过程的示例说明显示基板的结构。本公开所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶处理。沉积可以采用溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用喷涂和旋涂中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。若在整个制作过程中该“薄膜”需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。本公开中所说的“A和B同层设置”是指，A和B通过同一次构图工艺同时形成。
图3～图17为本公开显示基板制备过程的示意图，示意了顶发射OLED显示基板一个显示单元的版图结构，每个显示单元包括显示区域100和透明区域200，显示区域100包括第一子像素P1、第二子像素P2、第三子像素P3和第四子像素P4，每个子像素的像素驱动电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容。
(1)形成第一金属层图案，包括：在基底上沉积第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，在基底10上形成第一金属层图案，第一金属层图案包括第一极板41和补偿连接线51，每个子像素形成一个第一极板41，补偿连接线51为跨设4个子像素的条形结构，如图3和图4所示，图4为图3中A-A向的剖面图。在示例性实施方式中，第一极板41既作为第一存储电容的一个极板，配置为与后续形成的第二极板形成第一存储电容，第一极板41又作为遮挡层，配置为对晶体管进行遮光处理，降低照射到晶体管上的光强度，降低漏电流，从而减少光照对晶体管特性的影响。补偿连接线51配置为连接后续形成的补偿线，使补偿线向每个子像素提供补偿信号。在示例性实施方式中，第一极板41为长条状的矩形，除了补偿连接线51位置，第一极板41完全覆盖每个子像素的像素驱动电路区域。为了实现有效的遮挡，在长条状方向，第一极板41的长度大于后续形成的第一晶体管的栅电极与第三晶体管的栅电极之间的距离。在一些可能的实现方式中， 第一极板41的长度大于后续形成的第一晶体管的第一电极与第三晶体管的第一极之间的距离。在示例性实施方式中，第一子像素P1中的第一金属层图案与第四子像素P4中的第一金属层图案相对于垂直轴镜像对称，第二子像素P2中的第一金属层图案与第三子像素P3中的第一金属层图案相对于垂直轴镜像对称。
本次构图工艺后，第一金属层图案形成在显示区域100，透明区域200没有相应膜层。
(2)形成半导体层图案，包括：在形成有前述图案的基底上，依次沉积第一绝缘薄膜和半导体薄膜，通过构图工艺对半导体薄膜进行构图，形成覆盖第一金属层图案的第一绝缘层61，以及形成在第一绝缘层61上的半导体层图案，半导体层包括设置在每个子像素中的第一有源层11、第二有源层21、第三有源层31和第二极板42图案，如图5和图6所示，图6为图5中A-A向的剖面图。第一有源层11作为第一晶体管的有源层，第二有源层21作为第二晶体管的有源层，第三有源层31作为第三晶体管的有源层，第二极板42在基底10上的正投影与第一极板41在基底10上的正投影存在交叠区域，第一极板41和第二极板42形成第一存储电容。第二极板42既作为第一存储电容的一个极板，又作为第二存储电容的一个极板，第二极板42配置为与后续形成的第三极板形成第二存储电容。
在示例性实施方式中，第一有源层11、第二有源层21和第三有源层31在基底10上的正投影与第一极板41在基底10上的正投影存在交叠区域，使得作为遮挡层的第一极板41可以遮挡第一晶体管、第二晶体管和第三晶体管的沟道区域，避免光线对沟道产生影响，以避免沟道因生成光生漏电而影响显示效果。第一有源层11、第二有源层21和第三有源层31在基底10上的正投影与第二极板42在基底10上的正投影间隔设置，即第一有源层11与第二极板42之间、第二有源层21与第二极板42之间以及第三有源层31与第二极板42之间没有交叠区域，有利于根据相关需求设计第一晶体管、第二晶体管和第三晶体管的沟道宽长比。在示例性实施方式中，第一子像素P1和第四子像素P4中的第二极板42与第三有源层31之间设置有间隔44，第二子像素P2和第三子像素P3的第二极板42中部设置有开口45。在示例 性实施方式中，第一子像素P1中的半导体层图案与第四子像素P4中的半导体层图案相对于垂直轴镜像对称，第二子像素P2中的半导体层图案与第三子像素P3中的半导体层图案相对于垂直轴镜像对称。在示例性实施方式中，半导体层可以采用金属氧化物。
本次构图工艺后，半导体层图案形成在显示区域100，透明区域200包括基底10以及设置在基底10上的第一绝缘层61。
(3)形成第二金属层图案，包括：在形成有前述图案的基底上，依次沉积第二绝缘薄膜和第二金属薄膜，通过构图工艺对第二绝缘薄膜和第二金属薄膜进行构图，形成第二绝缘层62图案以及设置在第二绝缘层62上的第二金属层图案，第二金属层图案包括形成在每个显示单元中的第一扫描线Gn、第二扫描线Sn、电源连接线52和辅助电源线53，以及形成在每个子像素中的第一栅电极12、第二栅电极22和第三栅电极32，如图7和图8所示，图8为图7中A-A向的剖面图。第一扫描线Gn和第二扫描线Sn平行设置，沿着水平方向直线延伸，第一扫描线Gn位于子像素的上侧，第二扫描线Sn位于子像素的下侧，第一栅电极12是与第一扫描线Gn连接的一体结构，跨设在第一有源层11上，第二栅电极22跨设在第二有源层21上，且与第二极板42存在交叠区域，第三栅电极32是与第二扫描线Sn连接的一体结构，跨设在第三有源层31上。电源连接线52包括垂直于第一扫描线Gn的第一连接条和平行于第一扫描线Gn的第二连接条，第一连接条和第二连接条的一端相互连接。第一连接条形成在显示单元中第一电源线VDD所在区域，配置为连接后续形成的第一电源线VDD，第二连接条跨设在4个子像素内，配置为向每个子像素提供高电平信号。辅助电源线53形成在显示单元中第二电源线VSS所在区域，垂直于第一扫描线Gn，配置为连接后续形成的第二电源线VSS。在示例性实施方式中，电源连接线52的第一连接条和辅助电源线53位于第一栅电极12与第三栅电极32之间。在示例性实施方式中，第二绝缘层62图案与第二金属层图案相同，即第二绝缘层62位于第二金属层的下方，第二金属层以外区域没有第二绝缘层62。在示例性实施方式中，第一子像素P1与第四子像素P4中的第一栅电极12、第二栅电极22和第三栅电极32相对于垂直轴镜像对称，第二子像素P2与第三子像素P3 中的第一栅电极12、第二栅电极22和第三栅电极32相对于垂直轴镜像对称。
在示例性实施方式中，本次工艺还包括导体化处理。导体化处理是在形成第二金属层图案后，利用第一栅电极12、第二栅电极22和第三栅电极32作为遮挡进行等离子体处理，被第一栅电极12、第二栅电极22和第三栅电极32遮挡区域的半导体层(即半导体层与第一栅电极12、第二栅电极22和第三栅电极重叠的区域)作为晶体管的沟道区域，未被第二金属层遮挡区域的半导体层被处理成导体化层，形成导体化的第二极板42和导体化的源漏区域。
本次构图工艺后，第二金属层图案形成在显示区域100，透明区域200包括基底10以及设置在基底10上的第一绝缘层61。
(4)形成第三绝缘层图案。形成第三绝缘层图案包括：在形成有前述图案的基底上，沉积第三绝缘薄膜，通过构图工艺对第三绝缘薄膜进行构图，形成覆盖前述结构的第三绝缘层63图案，第三绝缘层63上开设有多个过孔图案，多个过孔图案包括：位于第一栅电极12两侧的第一过孔V1和第二过孔V2，位于第二栅电极22两侧的第三过孔V3和第四过孔V4，位于第三栅电极32两侧的第五过孔V5和第六过孔V6，位于补偿连接线51所在位置的第七过孔V7和第八过孔V8，位于第二栅电极22与第二极板42重叠区域的第九过孔V9，位于第一极板41所在位置的第十过孔V10，位于电源连接线52的第一连接条所在位置的多个第十一过孔V11，位于辅助电源线53所在位置的多个第十二过孔V12，如图9和图10所示，图10为图9中A-A向的剖面图。
第一过孔V1和第二过孔V2内的第三绝缘层63被刻蚀掉，暴露出第一有源层11两端的表面。第三过孔V3为转接过孔，转接过孔由两个半孔组成，一个半孔形成在第二有源层21上，另一个半孔形成在电源连接线52的第二连接条上，两个半孔内的第三绝缘层63被刻蚀掉，使得两个半孔组成的转接过孔同时暴露出第二有源层21的表面和电源连接线52的第二连接条的表面，第四过孔V4内的第三绝缘层63被刻蚀掉，暴露出第二有源层21的表面。第五过孔V5和第六过孔V6内的第三绝缘层63被刻蚀掉，暴露出 第三有源层31两端的表面。第七过孔V7位于补偿连接线51与后续形成的补偿线重叠的位置，每个子像素形成一个第八过孔V8，第七过孔V7和第八过孔V8内的第一绝缘层61和第三绝缘层63被刻蚀掉，暴露出补偿连接线51的表面。第九过孔V9为转接过孔，转接过孔由两个半孔组成，一个半孔形成在第二栅电极22上，另一个半孔形成在第二极板42上，两个半孔内的第三绝缘层63被刻蚀掉，使得两个半孔组成的转接过孔同时暴露出第二栅电极22的表面和第二极板42的表面。第一子像素P1和第四子像素P4中的第十过孔V10位于第二极板42与第三有源层31之间的间隔44所在位置，第二子像素P2和第三子像素P3中的第十过孔V10位于第二极板42中部的开口45所在位置，第十过孔V10内的第一绝缘层61和第三绝缘层63被刻蚀掉，暴露出第一极板41的表面。第十一过孔V11位于电源连接线52的第一连接条所在位置，多个第十一过孔V11间隔设置，第十一过孔V11内的第三绝缘层63被刻蚀掉，暴露出电源连接线52的第一连接条的表面。第十二过孔V12位于辅助电源线53所在位置，多个第十二过孔V12间隔设置，第十二过孔V12内的第三绝缘层63被刻蚀掉，暴露出辅助电源线53的表面。
本次构图工艺后，多个过孔图案形成在显示区域100，透明区域200包括在基底10上叠设的第一绝缘层61和第三绝缘层63。
(5)形成第三金属层图案，包括：在形成有前述图案的基底上，沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，在第三绝缘层63上形成第三金属层图案和辅助阴极80图案，第三金属层形成在显示区域100，辅助阴极80形成在透明区域200。显示区域100的第三金属层包括：形成在每个显示单元中的一条第一电源线VDD、一条第二电源线VSS、一条补偿线Se和四条数据线Dn，以及形成在每个子像素中的第一源电极13、第一漏电极14、第二源电极23、第二漏电极24、第三源电极33、第三漏电极34和第三极板43图案。透明区域200的辅助阴极80与第二电源线VSS为相互连接的一体结构，如图11和图12所示，图12为图11中A-A向的剖面图。
在示例性实施方式中，第一电源线VDD、第二电源线VSS、补偿线Se和数据线Dn平行设置，沿着竖直方向延伸，第二电源线VSS设置在邻近透明区域200的一侧，第一电源线VDD设置在远离透明区域200的一侧，补 偿线Se设置在第一电源线VDD和第二电源线VSS中间，两条数据线Dn设置在第二电源线VSS和补偿线Se之间，另外两条数据线Dn设置在第一电源线VDD和补偿线Se之间。
在示例性实施方式中，第一电源线VDD通过多个第十一过孔V11与电源连接线52连接，使得第一电源线VDD通过电源连接线52分别与每个子像素的第二源电极23连接，在第一栅电极12与第三栅电极32之间形成双层走线，保证了电源信号传输的可靠性，并降低了第一电源线VDD的电阻。双层走线包括第二金属层的电源连接线52和第三金属层的第一电源线VDD。第二电源线VSS通过多个第十二过孔V12与辅助电源线53连接，在第一栅电极12与第三栅电极32之间形成双层走线，保证了电源信号传输的可靠性，并降低了第二电源线VSS的电阻。双层走线包括第二金属层的辅助电源线53和第三金属层的第二电源线VSS。在一些可能的实现方式中，在平行于第一扫描线Gn和第二扫描线Sn方向，第一电源线VDD和第二电源线VSS的宽度均大于补偿线Se的宽度，第一电源线VDD和第二电源线VSS的宽度均大于数据线Dn的宽度，可以进一步降低第一电源线VDD和第二电源线VSS的电阻。补偿线Se通过第七过孔V7与补偿连接线51连接，使得补偿线Se通过补偿连接线51分别与每个子像素的第三源电极33连接。由于补偿线Se设置在显示区域100的中部，通过补偿连接线51与两侧的子像素的第三晶体管连接，左右两侧子像素的第三晶体管相对于补偿线Se对称设置，这种对称设计使得每个显示单元只需要采用一条补偿线Se，可以保证补偿信号在写入晶体管前RC延迟基本上相同，保证了显示均一性。
在示例性实施方式中，第一源电极13是与数据线Dn连接的一体结构，使得每条数据线Dn分别与所在子像素的第一源电极13连接，第一源电极13通过第一过孔V1与第一有源层11的一端连接，第一漏电极14通过第二过孔V2与第一有源层11的另一端连接，第一漏电极14还通过转接结构的第九过孔V9同时与第二栅电极22和第二极板42连接，实现了第一漏电极14、第二栅电极22和第二极板42具有相同的电位。第二源电极23通过转接结构的第三过孔V3同时与电源连接线52和第二有源层21的一端连接，实现了第二源电极23与第一电源线VDD的连接，第二漏电极24通过第四过 孔V4与第二有源层21的另一端连接。第三源电极33通过第五过孔V5与第三有源层31的一端连接，同时通过第八过孔V8与补偿连接线51连接，实现了第三源电极33与补偿线Se的连接，第三漏电极34通过第六过孔V6与第三有源层31的另一端连接。第二漏电极24、第三漏电极34和第三极板43为相互连接的一体结构，第三极板43通过第十过孔V10与第一极板41连接，因而第二漏电极24同时与第一极板41和第三极板43连接，第三漏电极34同时与第一极板41和第三极板43连接，实现了第二漏电极24、第三漏电极34、第一极板41和第三极板43具有相同的电位。第三极板43在基底10上的正投影与第二极板42在基底10上的正投影存在交叠区域，第三极板43与第二极板42形成第二存储电容。在示例性实施方式中，第一子像素P1与第四子像素P4中的第一源电极13、第一漏电极14、第二源电极23、第二漏电极24、第三源电极33、第三漏电极34和第三极板43相对于垂直轴镜像对称，第二子像素P2与第三子像素P3中的第一源电极13、第一漏电极14、第二源电极23、第二漏电极24、第三源电极33、第三漏电极34和第三极板43相对于垂直轴镜像对称。
在示例性实施方式中，辅助阴极80被配置为降低透明区域的衍射效应。通过在透明区域200设置辅助阴极80，将透明区域200由规则的矩形改变成不规则形状，透明区域200的不同位置具有不同的狭缝宽度。当光线经过不规则形状的透明区域200时，由于产生衍射条纹的位置不同，产生衍射条纹的方向不同，因而光线产生衍射条纹不会朝着一个方向扩散，而是朝着多个方向扩散，大大弱化了衍射效应，避免了屏后物体虚化现象，提高了透明显示效果。在一些可能的实现方式中，透明区域200的辅助阴极80包括电极块801和连接条802，电极块801通过连接条802与第二电源线VSS连接，电极块801可以包括圆形、椭圆形、矩形、梯形、五边形、六边形和哑铃形中的任意一种或多种，连接条802可以是直线条、折线条和弧线条中的任意一种或多种，本公开在此不做具体的限定。在一些可能的实现方式中，在平行于第二电源线VSS的方向，电极块801的宽度大于连接条802的宽度，在垂直于第二电源线VSS的方向，连接条802的长度大于电极块801的长度。
在一些可能的实现方式中，辅助阴极80的位置可以设置成邻近第一扫 描线Gn，或者设置成邻近第二扫描线Sn，或者设置成位于第一扫描线Gn和第二扫描线Gn之间，透明区域200可以设置一个辅助阴极80，或者可以设置二个或多个辅助阴极80，电极块801的面积可以是透明区域200的面积的5％到20％，本公开在此不做具体限定。
本次构图工艺后，第三金属层图案形成在显示区域100，透明区域200包括在基底10上叠设的第一绝缘层61和第三绝缘层63，以及设置在第三绝缘层63上的辅助阴极80。
(6)形成第四绝缘层和平坦层图案，包括：在形成有前述图案的基底上，先沉积第四绝缘薄膜，后涂覆平坦薄膜，通过平坦薄膜的掩膜、曝光和显影，对第四绝缘薄膜进行刻蚀形成覆盖前述结构的第四绝缘层64图案，以及设置在第四绝缘层64上的平坦(PLN)层65图案，第四绝缘层64和平坦层65上开设有多个过孔图案，多个过孔图案至少包括：位于显示区域100每个子像素中第三极板43所在位置的第十三过孔V13，以及位于透明区域200中辅助阴极80所在位置的第十四过孔V14，如图13和图14所示，图14为图13中A-A向的剖面图。在示例性实施方式中，在第一子像素P1和第四子像素P4，第十三过孔V13位于第二极板42与第三有源层31之间的间隔44所在位置，在第二子像素P2和第三子像素P3，第十三过孔V13位于第二极板42的开口45所在位置，第十三过孔V13中的第四绝缘层64和平坦层65被刻蚀掉，暴露出第三极板43的表面，第十四过孔V14中的第四绝缘层64和平坦层65被刻蚀掉，暴露出辅助阴极80的表面。
本次构图工艺后，透明区域200包括在基底10上叠设的第一绝缘层61和第三绝缘层63，设置在第三绝缘层63上的辅助阴极80，覆盖辅助阴极80的第四绝缘层64和平坦层65，第四绝缘层64和平坦层65上开设有暴露出辅助阴极80的第十四过孔V14。
(7)形成透明导电层图案，包括：在形成有前述图案的基底上，沉积透明导电薄膜，通过构图工艺对透明导电薄膜进行构图，在平坦层65上形成透明导电层图案，透明导电层包括阳极70和连接电极81，阳极70形成在显示区域100的每个子像素中，每个子像素中的阳极70通过相应子像素中的第十三过孔V13与第二晶体管T2的漏电极连接，连接电极81形成在透明区域 100中辅助阴极80所在位置，连接电极81通过第十四过孔V14与辅助阴极80连接，如图15和图16所示，图16为图15中A-A向的剖面图。由于每个子像素中的第二晶体管T2的漏电极、第三晶体管T3的漏电极和第三极板43是相互连接的一体结构，因此实现了阳极70与每个子像素中的第二晶体管T2的漏电极的连接。在示例性实施方式中，四个阳极70可以形成红色发光单元、绿色发光单元、蓝色发光单元和白色发光单元。在示例性实施方式中，显示区域100内的四个阳极70可以是矩形状，四个阳极70呈正方形(Square)排列，左上的阳极70通过第一子像素P1的第十三过孔V13与第一子像素P1的第三极板43连接，右上的阳极70通过第四子像素P4的第十三过孔V13与第四子像素P4的第三极板43连接，左下的阳极70通过第二子像素P2的第十三过孔V13与第二子像素P2的第三极板43连接，右下的阳极70通过第三子像素P3的第十三过孔V13与第三子像素P3的第三极板43连接。在一些可能的实现方式中，显示区域100内的四个阳极70可以是长条形状，四个阳极70呈并列方式排列，每个阳极70与所在子像素的位置相对应。在一些可能的实现方式中，显示区域100内阳极70的排列方式可以根据实际需要进行调整，本公开在此不做具体限定。
本次构图工艺后，透明区域200包括在基底10上叠设的第一绝缘层61和第三绝缘层63，设置在第三绝缘层63上的辅助阴极80，覆盖辅助阴极80的第四绝缘层64和平坦层65，设置在平坦层65上的连接电极81，连接电极81通过第十四过孔V14与辅助阴极80连接。
(8)形成像素定义层、有机发光层和阴极图案，包括：在形成前述图案的基底上涂覆像素定义薄膜，通过掩膜、曝光和显影工艺形成像素定义层(Pixel Define Layer)71图案，像素定义层71形成在在显示区域100的每个子像素中，每个子像素中的像素定义层71形成有暴露出阳极70的像素开口。随后，在前述形成的像素开口内形成有机发光层72，有机发光层72与阳极70连接。随后，沉积阴极薄膜，通过构图工艺对阴极薄膜进行构图，在显示区域100和透明区域200内形成阴极73图案，在显示区域100，阴极73与有机发光层72连接，在透明区域200，阴极73与连接电极81连接，由于连接电极81与辅助阴极80连接，辅助阴极80与第二电源线VSS连接， 因而实现了阴极73与第二电源线VSS连接，如图17所示。
(9)在形成前述图案的基础上形成封装层，封装层形成在显示区域100和透明区域200。显示区域100的封装层包括无机材料的第一封装层74、有机材料的第二封装层75和无机材料的第三封装层76，第一封装层74设置在阴极73上，第二封装层75设置在第一封装层74上，第三封装层76设置在第二封装层75上，形成无机材料/有机材料/无机材料的叠层结构。透明区域200的封装层包括无机材料的第一封装层74和无机材料的第三封装层76，第一封装层74设置在阴极73上，第三封装层76设置在第一封装层74上，形成无机材料/无机材料的叠层结构，如图18所示。
结合图3～图18，每个子像素中，第一有源层11、第一栅电极12、第一源电极13和第一漏电极14组成第一晶体管T1，第二有源层21、第二栅电极22、第二源电极23和第二漏电极24组成第二晶体管T2，第三有源层31、第三栅电极32、第三源电极33和第三漏电极34组成第三晶体管T3，第一极板41和第二极板42组成第一存储电容，第二极板42和第三极板43组成第二存储电容，第一存储电容和第二存储电容为并联结构，实现存储所在子像素的第二栅电极22的电位。第一子像素P1和第四子像素P4中的第一晶体管T1、第二晶体管T2、第三晶体管T3、第一存储电容和第二存储电容相对于补偿线Se镜像对称，第二子像素P2和第三子像素P3中的第一晶体管T1、第二晶体管T2、第三晶体管T3、第一存储电容和第二存储电容相对于补偿线Se镜像对称。
在每个子像素中，第一栅电极12与第一扫描线Gn连接，第一源电极13与数据线Dn连接，第一漏电极14与所在子像素的第二栅电极22连接。第二栅电极22与所在子像素的第一漏电极14连接，第二源电极23通过电源连接线52与第一电源线VDD连接，第二漏电极24与所在子像素的阳极连接。第三栅电极32与第二扫描线Sn连接，第三源电极33通过补偿连接线51与补偿线Se连接，第三漏电极34与所在子像素的第二漏电极24连接。第一基板41与所在子像素的第二漏电极24和第三漏电极34连接，第二基板42与所在子像素的第二栅电极22和第一漏电极14连接，第三基板43与所在子像素的第二漏电极24和第三漏电极34连接。阳极70与所在子像素的第二漏电 极24连接，覆盖所有子像素的阴极73通过透明区域200的辅助阴极80与第二电源线VSS连接，使得阳极70与阴极73之间的有机发光层72响应所在子像素的第二漏电极24的电流而发出相应亮度的光。
在示例性实施方式中，第一金属层、第二金属层和第三金属层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层称之为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层称之为栅绝缘(GI)层，第三绝缘层称之为层间绝缘(ILD)层，第四绝缘层称之为钝化(PVX)层。第二绝缘层的厚度小于第三绝缘层的厚度，第一绝缘层的厚度小于第二绝缘层和第三绝缘层的厚度之和，在保证绝缘效果的前提下，提高存储电容的容量。平坦层可以采用有机材料，透明导电薄膜可以采用氧化铟锡ITO或氧化铟锌IZO，像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯。阴极可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或多种，或采用上述金属中任意一种或多种制成的合金。
在一些可能的实现方式中，第一绝缘层的厚度为3000埃到5000埃，第二绝缘层的厚度为1000埃到2000埃，第三绝缘层的厚度为4500埃到7000埃，第四绝缘层的厚度为3000埃到5000埃。第一金属层的厚度为80埃到1200埃，第二金属层的厚度为3000埃到5000埃，第三金属层的厚度为3000埃到9000埃。
在示例性实施方式中，半导体层可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物、包含铟和镓和锌的氧化物等。半导体层可以单层，或者可以是双层，或者可以是多层。
如图3～图18所示，本公开所提供的显示基板包括：
基底10。
设置在基底10上的第一金属层，第一金属层包括第一极板41和补偿连接线51。
第一绝缘层61，覆盖第一金属层。
设置在第一绝缘层61上半导体层，半导体层包括第一有源层11、第二有源层21、第三有源层31和第二极板42，第二极板42在基底10上的正投影与第一极板41在基底10上的正投影存在交叠区域，第二极板42与第一极板41形成第一存储电容。
第二绝缘层62以及设置在第二绝缘层62上的第二金属层，第二金属层包括：第一扫描线Gn、第二扫描线Sn、电源连接线52、辅助电源线53、第一栅电极12、第二栅电极22和第三栅电极32，第一栅电极12与第一扫描线Gn为一体结构，第三栅电极32与第二扫描线Sn为一体结构，第二绝缘层62与第二金属层图案相同。
覆盖第二金属层的第三绝缘层63，其上分别开设多个过孔，多个过孔包括：暴露出第一有源层11两端的第一过孔V1和第二过孔V2，暴露出第二有源层21两端的第三过孔V3和第四过孔V4，暴露出第三有源层31两端的第五过孔V5和第六过孔V6，暴露出补偿连接线51的第七过孔V7和第八过孔V8，同时暴露出第二栅电极22和第二极板42的第九过孔V9，暴露出第一极板41的第十过孔V10，暴露出电源连接线52的多个第十一过孔V11，以及暴露出辅助电源线53的多个第十二过孔V12。
设置在第三绝缘层63上的第三金属层，第三金属层包括第一电源线VDD、第二电源线VSS、补偿线Se、数据线Dn、第一源电极13、第一漏电极14、第二源电极23、第二漏电极24、第三源电极33、第三漏电极34和第三极板43，第一电源线VDD通过第十一过孔V11与电源连接线52连接，第二电源线VSS通过第十二过孔V12与辅助电源线53连接，补偿线Se通过第七过孔V7与补偿连接线51连接，第一源电极13与数据线Dn为一体结构，第二源电极23通过第三过孔V3与电源连接线52连接，第三源电极33通过第八过孔V8与补偿连接线51连接，第一漏电极14通过第九过孔V9 同时与第二栅电极22和第二极板42连接，第二漏电极24、第三漏电极34和第三极板43为相互连接的一体结构，第三极板43通过第十过孔V10与第一极板41连接，第三极板43在基底10上的正投影与第二极板42在基底10上的正投影存在交叠区域，第二极板42与第三极板43形成第二存储电容。
覆盖第三金属层的第四绝缘层64和平坦层65，其上分别开设多个过孔，多个过孔包括：暴露出第二晶体管的漏电极的第十三过孔V13和暴露出辅助阴极80的第十四过孔V14。
设置在平坦层65的透明导电层，透明导电层包括阳极70和连接电极81图案，阳极70通过第十三过孔V13与第二晶体管的漏电极连接，连接电极81通过第十四过孔V14与辅助阴极80连接。
设置在平坦层65上的像素定义层71，像素定义层71在每个子像素限定出暴露阳极70的像素开口。
设置在开口区域内的有机发光层72，有机发光层72与阳极70连接。
阴极73，显示区域100的阴极73与有机发光层72连接，透明区域200的阴极73通过连接电极81与辅助阴极80连接；
覆盖上述结构的封装层74。
本公开所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，显示区域可以包括3个子像素。又如，像素驱动电路可以是5T1C或7T1C。再如，膜层结构中还可以设置其它电极或引线，本公开在此不做具体的限定。
通过以上描述的显示基板的结构和制备流程可以看出，本公开所提供的显示基板，通过在透明区域设置辅助阴极，将透明区域改变成不规则形状，当光线经过不规则形状的透明区域时，由于产生衍射条纹的位置不同，产生衍射条纹的方向不同，因而光线产生衍射条纹不会朝着一个方向扩散，而是朝着多个方向扩散，因而大大弱化了衍射效应，避免了屏后物体虚化现象，提高了透明显示效果。仿真模拟显示，没有设置辅助阴极时，显示基板的衍射值为50％，中心点四周产生4个较严重衍射斑点。设置辅助阴极后，显示基板的衍射值为30％，中心点周围产生4个轻微衍射斑点。本公开所提供的 显示基板，通过在透明区域设置与发光元件的阴极连接的辅助阴极，还可以有效缓解大尺寸透明显示的电压降，保证了显示均一性，有利于简化显示区域的结构布局，减小每个子像素的占用空间，提高透明区域的面积比，提高分辨率和透明度。本公开所提供的显示基板，通过采用金属氧化物材料的第二极板作为存储电容的极板，第二极板分别与第一金属层中的第一极板和第三金属层中的第三极板形成存储电容，第一极板和第三极板具有相同的电位，第二极板具有不同于第一极板和第三极板的电位，因此第一极板、第二极板和第三极板之间形成二个并联的存储电容，有效增大了存储电容的容量，有利于实现高分辨率显示。本公开的制备工艺利用现有成熟的制备设备即可实现，对现有工艺改进较小，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
图19为本公开显示基板的平面示意图。如图19所示，本公开显示基板包括规则排布的多个显示单元1，每个显示单元1包括显示区域100和透明区域200，透明区域200设置在显示区域100的一侧，透明区域200中设置有辅助阴极80，显示区域100被配置为实现图像显示，透明区域200被配置为实现光线透过，从而实现透明显示。显示基板包括水平设置的多条第一扫描线Gn和第二扫描线Sn以及垂直设置的多条第一电源线VDD和第二电源线VSS，第一扫描线Gn和第二扫描线Sn之间限定出一个子像素行，第一电源线VDD和第二电源线VSS之间限定出四个子像素列，一个子像素行和四个子像素列构成四个设置像素驱动电路的子像素，四个子像素采用并列方式排列。显示基板还包括垂直设置的多条补偿线Se和数据线Dn，补偿线Se设置在第一电源线VDD和第二电源线VSS之间，两条数据线Dn设置在第二电源线VSS和补偿线Se之间，另外两条数据线Dn设置在第一电源线VDD和补偿线Se之间。一个显示区域中的四个子像素包括：第二电源线VSS和数据线Dn限定出的第一子像素，数据线Dn和补偿线Se限定出的第二子像素，补偿线Se和数据线Dn限定出的第三子像素，数据线Dn和第一电源线VDD限定出的第四子像素。透明区域200由第一扫描线Gn、第二扫描线Sn、第一电源线VDD和第二电源线VSS限定，透明区域200包括辅助阴极80，辅助阴极80被配置为降低透明区域的衍射效应，还被配置为向显示区域100中发光元件的阴极提供低电平信号。本公开通过在透明区域200设置辅助阴 极80，将透明区域改变成不规则形状，当光线经过不规则形状的透明区域时，由于产生衍射条纹的位置不同，产生衍射条纹的方向不同，因而光线产生衍射条纹不会朝着一个方向扩散，而是朝着多个方向扩散，因而大大弱化了衍射效应，避免了屏后物体虚化现象，提高了透明显示效果。本公开通过在透明区域200设置辅助阴极80，辅助阴极80与发光元件的阴极连接，可以有效缓解大尺寸透明显示的电压降(IR Drop)，保证了显示均一性。辅助阴极80设置在透明区域200，有利于简化显示区域的结构布局，减小每个子像素的占用空间，提高透明区域的面积比，提高分辨率和透明度。
图20为本公开显示基板另一种结构的示意图。在示例性实施方式中，显示基板还包括遮挡条90，遮挡条90设置在显示区域100的边缘，或者设置在透明区域200的边缘，或者设置在显示区域100和透明区域200的边缘，遮挡条90被配置为降低显示区域的反光现象和衍射效应。
显示区域100和透明区域200设置有多条信号线，由于这些信号线由金属材料制备，当外部光线入射到显示区域100和透明区域200时，不仅使入射到这些金属信号线的光线出现金属反光，而且使经过这些金属信号线的光线出现较为复杂的衍射条纹，从而导致严重的反光现象和衍射效应，降低了透明显示效果。此外，反光现象和衍射效应还会降低透明显示装置中摄像头的成像质量，使得摄像头拍摄到的画面出现模糊、重影和彩边等失真问题。本公开所提供的显示基板，通过在显示区域100和透明区域200的边缘设置遮挡条90，使遮挡条90位于光线入射到信号线的光线路径上，利用遮挡条90遮挡位于显示区域100边缘和透明区域200边缘的金属信号线，减少了入射到或经过金属信号线的光线，不仅有效减少了信号线的反光现象，而且有效降低了信号线的衍射效应，提高了透明显示效果，提高了摄像头的成像质量。
图21为本公开显示基板又一种结构的示意图。在示例性实施方式中，显示基板还包括遮挡条90和凸起结构91，遮挡条90设置在显示区域100和透明区域200的边缘，凸起结构91设置在透明区域200的至少一个边缘上，遮挡条90被配置为降低显示区域的反光现象和衍射效应，凸起结构91被配置为降低透明区域的衍射效应。
在示例性实施方式中，凸起结构91可以包括多个间隔设置的凸起，多个凸起的一端位于透明区域200的内侧边缘上，另一端向透明区域200的中部延伸，形成具有凹凸状内侧边缘的透明区域200。在示例性实施方式中，凸起结构91可以包括波浪状遮挡条，形成具有波浪状内侧边缘的透明区域200。本公开通过在透明区域200形成凹凸状或波浪状内侧边缘，凹凸状或波浪状内侧边缘可以产生具有不同位置和不同扩散方向的衍射条纹，大大弱化了衍射效应，避免了屏后物体虚化现象，提高了透明显示效果。在示例性实施方式中，显示基板的其它结构与前述实施例中描述的相应结构类似。
在一些可能的实现方式中，遮挡条90的位置可以与第一扫描线Gn、第二扫描线Sn、第一电源线VDD和第二电源线VSS的位置相对应，遮挡条90在基底上的正投影可以包含第一扫描线Gn、第二扫描线Sn、第一电源线VDD和第二电源线VSS在基底上的正投影，遮挡条90可以采用黑矩阵(Black Matrix，简称BM)，或者叠设的至少两个彩膜层，例如，红色彩膜层和蓝色彩膜层。
在一些可能的实现方式中，凸起结构91可以设置在透明区域200中的一个边缘上，或者可以设置在透明区域200中相对的两个边缘上，或者可以设置在透明区域200中邻近的两个边缘上，或者可以设置在透明区域200中所有的边缘上，以使不同位置处两个边缘之间的间距不同，本公开在此不做具体的限定。
在一些可能的实现方式中，凸起的形状可以包括圆形、椭圆形、矩形、梯形、五边形、六边形和哑铃形中的任意一种或多种。多个凸起或波浪的形状可以相同，或者可以不同。多个凸起或波浪的尺寸可以相同，或者可以不同，本公开在此不做具体的限定。
在一些可能的实现方式中，凸起结构91与遮挡条90同层设置，且通过同一次工艺形成。在一些可能的实现方式中，凸起结构91与遮挡条90为一体结构。
本公开还提供了一种显示基板的制备方法，显示基板包括规则排布的多个显示单元，所述显示单元包括显示区域和透明区域，所述显示区域包括多个子像素；所述制备方法包括：
S1、在基底上形成第一金属层、半导体层和第二金属层；所述第一金属层包括第一极板；所述半导体层包括第二极板，所述第二极板在基底上的正投影与所述第一极板在基底上的正投影存在交叠区域，以形成第一存储电容；所述第二金属层包括限定出一子像素行的第一扫描线和第二扫描线；
S2、形成第三金属层；所述第三金属层包括第三极板以及限定出所述多个子像素的第一电源线、第二电源线、补偿线和数据线；所述第三极板在基底上的正投影与所述第二极板在基底上的正投影存在交叠区域，以形成第二存储电容，所述第三极板通过过孔与所述第一极板连接；所述第三金属层还包括至少一个辅助阴极，所述至少一个辅助阴极设置在所述透明区域，所述至少一个辅助阴极与所述第二电源线连接。
在示例性实施方式中，步骤S1包括：
在基底形成包括第一极板和补偿连接线的第一金属层；
形成覆盖所述第一金属层的第一绝缘层，在所述第一绝缘层上形成包括第二极板的半导体层，所述第二极板在所述基底上的正投影与所述第一极板在基底上的正投影存在交叠区域，以形成第一存储电容；
形成第二绝缘层以及设置在所述第二绝缘层上的第二金属层，所述第二绝缘层与第二金属层图案相同，所述第二金属层包括第一扫描线、第二扫描线和电源连接线。
在示例性实施方式中，步骤S2包括：
形成覆盖所述第二金属层的第三绝缘层，所述第三绝缘层上形成有多个过孔，所述多个过孔包括：暴露出所述补偿连接线的第七过孔，暴露出所述第一极板的第十过孔，暴露出所述电源连接线的第十一过孔；
在所述第三绝缘层上形成第三金属层，所述第三金属层包括第三极板、第一电源线、第二电源线、补偿线、数据线和至少一个辅助阴极；所述第三极板在基底上的正投影与所述第二极板在基底上的正投影存在交叠区域，以形成第二存储电容，所述第三极板通过所述第十过孔与所述第一极板连接；所述补偿线通过所述第七过孔与所述补偿线连接，所述第一电源线通过所述第十一过孔与所述电源连接线连接；所述至少一个辅助阴极设置在所述透明 区域，所述至少一个辅助阴极与所述第二电源线连接。
在示例性实施方式中，所述制备方法还包括：
形成覆盖所述第三金属层的第四绝缘层和平坦层；
在所述平坦层上形成阳极和连接电极，所述阳极与所述第三极板连接，所述连接电极与所述辅助阴极连接；
依次形成像素定义层、有机发光层、阴极和封装层，所述阴极与所述连接电极连接；
在所述封装层上形成遮挡条，所述遮挡条在基底上的正投影包含所述第一扫描线、第二扫描线、第一电源线和第二电源线在基底上的正投影。
在示例性实施方式中，在所述封装层上形成遮挡条包括：
在所述封装层上形成遮挡条和凸起结构，所述凸起结构设置在所述透明区域的边缘的内侧，所述凸起结构包括波浪状遮挡条或者多个间隔设置的凸起，形成具有凹凸状内侧边缘的透明区域或者具有波浪状内侧边缘的透明区域。
本公开还提供了一种显示装置，包括前述实施例的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本申请中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本申请的权利要求的范围当中。

Claims (20)

  1. 一种显示基板，包括多个显示单元，所述显示单元包括显示区域和透明区域，所述显示区域包括多个子像素；在垂直于显示基板的方向上，所述子像素包括在基底上设置的第一金属层、半导体层、第二金属层和第三金属层，所述第一金属层包括第一极板，所述半导体层包括第二极板，所述第二金属层包括限定出一子像素行的第一扫描线和第二扫描线，所述第三金属层包括第三极板以及限定出所述多个子像素的第一电源线、第二电源线、补偿线和数据线；所述第二极板在基底上的正投影与所述第一极板在基底上的正投影存在交叠区域，以形成第一存储电容，所述第三极板在基底上的正投影与所述第二极板在基底上的正投影存在交叠区域，以形成第二存储电容，所述第三极板通过过孔与所述第一极板连接；所述第三金属层还包括至少一个辅助阴极，所述至少一个辅助阴极设置在所述透明区域，所述至少一个辅助阴极与所述第二电源线连接。
  2. 根据权利要求1所述的显示基板，其中，所述显示区域包括设置像素驱动电路的第一子像素、第二子像素、第三子像素和第四子像素，所述四个子像素以并列方式排列。
  3. 根据权利要求2所述的显示基板，其中，所述第一子像素与所述第四子像素的第一金属层和半导体层中的至少一层相对于所述补偿线镜像对称设置，所述第二子像素与所述第三子像素的第一金属层和半导体层中的至少一层相对于所述补偿线镜像对称设置。
  4. 根据权利要求2所述的显示基板，其中，所述像素驱动电路包括第一晶体管、第二晶体管、第三晶体管和存储电容，所述第一晶体管的栅电极与所述第一扫描线连接，所述第一晶体管的第一极与所述数据线连接，所述第一晶体管的第二极与所述第二晶体管的栅电极连接，所述第二晶体管的第一极与所述第一电源线连接，所述第二晶体管的第二极与有机电致发光二极管的第一极连接，所述第三晶体管的栅电极与所述第二扫描线连接，所述第三晶体管的第一极通过补偿连接线与所述补偿线连接，所述第三晶体管的第二极与所述第二晶体管的第二极连接，所述有机电致发光二极管的第二极与所述第二电源线连接；所述第一极板和第三极板与所述第二晶体管的第二极 连接，所述第二极板与所述第二晶体管的栅电极连接。
  5. 根据权利要求4所述的显示基板，其中，所述像素驱动电路还包括电源连接线，所述第二晶体管的第一极通过所述电源连接线与所述第一电源线连接；所述电源连接线与所述第一扫描线和第二扫描线同层设置，所述第一电源线通过过孔与所述电源连接线连接，在所述第一晶体管的栅电极与所述第三晶体管的栅电极之间形成双层走线。
  6. 根据权利要求4所述的显示基板，其中，所述像素驱动电路还包括辅助电源线，所述辅助电源线与所述第一扫描线和第二扫描线同层设置，所述第二电源线通过过孔与所述辅助电源线连接，在所述第一晶体管的栅电极与所述第三晶体管的栅电极之间形成双层走线。
  7. 根据权利要求4所述的显示基板，其中，所述半导体层还包括第一晶体管的有源层、第二晶体管的有源层和第三晶体管的有源层，所述补偿连接线与所述第一极板同层设置，所述第二极板与所述第一晶体管的有源层、第二晶体管的有源层和第三晶体管的有源层同层设置。
  8. 根据权利要求4所述的显示基板，其中，所述第一极板作为遮挡层，所述第一极板的形状包括长条状的矩形，在平行于所述补偿线方向，所述第一极板的长度大于所述第一晶体管的栅电极与所述第三晶体管的栅电极之间的距离。
  9. 根据权利要求1到8任一项所述的显示基板，其中，所述辅助阴极包括电极块和连接条，所述电极块通过所述连接条与所述第二电源线连接，所述电极块的面积为所述透明区域的面积的5％到20％。
  10. 根据权利要求9所述的显示基板，其中，在平行于显示基板的平面内，所述电极块的形状包括圆形、椭圆形、矩形、梯形、五边形、六边形和哑铃形中的任意一种或多种，所述连接条包括直线条、折线条和弧线条中的任意一种或多种。
  11. 根据权利要求1到8任一项所述的显示基板，所述显示基板还包括遮挡条，所述遮挡条在基底上的正投影包含所述第一扫描线、第二扫描线、第一电源线和第二电源线在基底上的正投影。
  12. 根据权利要求11所述的显示基板，其中，所述显示基板还包括凸起结构，所述凸起结构设置在所述透明区域的边缘的内侧，所述凸起结构包括波浪状遮挡条或者多个间隔设置的凸起，形成具有凹凸状内侧边缘的透明区域或者具有波浪状内侧边缘的透明区域。
  13. 根据权利要求12所述的显示基板，其中，在平行于显示基板的平面内，所述凸起的形状包括圆形、椭圆形、矩形、梯形、五边形、六边形和哑铃形中的任意一种或多种。
  14. 根据权利要求12所述的显示基板，其中，所述凸起结构与所述遮挡条同层设置。
  15. 一种显示基板的制备方法，所述显示基板包括多个显示单元，所述显示单元包括显示区域和透明区域，所述显示区域包括多个子像素；所述制备方法包括：
    在基底上形成第一金属层、半导体层和第二金属层；所述第一金属层包括第一极板；所述半导体层包括第二极板，所述第二极板在基底上的正投影与所述第一极板在基底上的正投影存在交叠区域，以形成第一存储电容；所述第二金属层包括限定出一子像素行的第一扫描线和第二扫描线；
    形成第三金属层；所述第三金属层包括第三极板以及限定出所述多个子像素的第一电源线、第二电源线、补偿线和数据线；所述第三极板在基底上的正投影与所述第二极板在基底上的正投影存在交叠区域，以形成第二存储电容，所述第三极板通过过孔与所述第一极板连接；所述第三金属层还包括至少一个辅助阴极，所述至少一个辅助阴极设置在所述透明区域，所述至少一个辅助阴极与所述第二电源线连接。
  16. 根据权利要求15所述的制备方法，其中，在基底上依次形成第一金属层、半导体层和第二金属层，包括：
    在基底形成包括第一极板和补偿连接线的第一金属层；
    形成覆盖所述第一金属层的第一绝缘层，在所述第一绝缘层上形成包括第二极板的半导体层，所述第二极板在所述基底上的正投影与所述第一极板在基底上的正投影存在交叠区域，以形成第一存储电容；
    形成第二绝缘层以及设置在所述第二绝缘层上的第二金属层，所述第二绝缘层与第二金属层图案相同，所述第二金属层包括第一扫描线、第二扫描线和电源连接线。
  17. 根据权利要求16所述的制备方法，其中，形成第三金属层，包括：
    形成覆盖所述第二金属层的第三绝缘层，所述第三绝缘层上形成有多个过孔，所述多个过孔包括：暴露出所述补偿连接线的第七过孔，暴露出所述第一极板的第十过孔，暴露出所述电源连接线的第十一过孔；
    在所述第三绝缘层上形成第三金属层，所述第三金属层包括第三极板、第一电源线、第二电源线、补偿线、数据线和至少一个辅助阴极；所述第三极板在基底上的正投影与所述第二极板在基底上的正投影存在交叠区域，以形成第二存储电容，所述第三极板通过所述第十过孔与所述第一极板连接；所述补偿线通过所述第七过孔与所述补偿线连接，所述第一电源线通过所述第十一过孔与所述电源连接线连接；所述至少一个辅助阴极设置在所述透明区域，所述至少一个辅助阴极与所述第二电源线连接。
  18. 根据权利要求15到17任一项所述的制备方法，所述制备方法还包括：
    形成覆盖所述第三金属层的第四绝缘层和平坦层；
    在所述平坦层上形成阳极和连接电极，所述阳极与所述第三极板连接，所述连接电极与所述辅助阴极连接；
    依次形成像素定义层、有机发光层、阴极和封装层，所述阴极与所述连接电极连接；
    在所述封装层上形成遮挡条，所述遮挡条在基底上的正投影包含所述第一扫描线、第二扫描线、第一电源线和第二电源线在基底上的正投影。
  19. 根据权利要求18所述的制备方法，其中，在所述封装层上形成遮挡条包括：
    在所述封装层上形成遮挡条和凸起结构，所述凸起结构设置在所述透明 区域的边缘的内侧，所述凸起结构包括波浪状遮挡条或者多个间隔设置的凸起，形成具有凹凸状内侧边缘的透明区域或者具有波浪状内侧边缘的透明区域。
  20. 一种显示装置，其中，包括如权利要求1到14任一项所述的显示基板。
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