WO2023122895A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2023122895A1
WO2023122895A1 PCT/CN2021/141729 CN2021141729W WO2023122895A1 WO 2023122895 A1 WO2023122895 A1 WO 2023122895A1 CN 2021141729 W CN2021141729 W CN 2021141729W WO 2023122895 A1 WO2023122895 A1 WO 2023122895A1
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Prior art keywords
pixel
sub
display substrate
transistor
layer
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PCT/CN2021/141729
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English (en)
French (fr)
Inventor
吴刘
李永谦
袁粲
袁志东
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Priority to EP21969281.1A priority Critical patent/EP4333594A1/en
Priority to PCT/CN2021/141729 priority patent/WO2023122895A1/zh
Priority to CN202180004219.7A priority patent/CN116686409A/zh
Publication of WO2023122895A1 publication Critical patent/WO2023122895A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/813—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/822—Cathodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/828—Transparent cathodes, e.g. comprising thin metal layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/302—Details of OLEDs of OLED structures
    • H10K2102/3023—Direction of light emission
    • H10K2102/3031—Two-side emission, e.g. transparent OLEDs [TOLED]

Definitions

  • Embodiments of the present disclosure relate to but are not limited to the field of display technology, and in particular, relate to a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • TFT Thin Film Transistor
  • Transparent display is an important personalized display field of display technology. It refers to image display in a transparent state, and the viewer can not only see the image in the display device, but also see the scene behind the display device.
  • the transparent display device usually divides each pixel unit into a pixel area and a transparent area, the pixel area is provided with a pixel driving circuit and a light-emitting device to realize image display, and the transparent area realizes light transmission.
  • an embodiment of the present disclosure provides a display substrate, including: a transparent area and a pixel area, and the pixel area includes: a plurality of light-emitting devices, and the plurality of light-emitting devices include: a first light-emitting device, the first light-emitting device
  • the orthographic projection of the first anode layer of the device on the plane of the display substrate overlaps with the orthographic projection of the transparent region on the plane of the display substrate, and the orthographic projection of the second anode layer of the first light-emitting device on the plane of the display substrate is located at the The pixel area is within the orthographic projection of the display substrate plane.
  • the embodiments of the present disclosure further provide a display device, including the display substrate described in the above embodiments.
  • FIG. 1 is a schematic structural view of a transparent OLED display substrate
  • FIG. 2 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG. 3 is a first structural schematic diagram of a display substrate in an exemplary embodiment of the present disclosure
  • FIG. 4 is a second structural schematic diagram of a display substrate in an exemplary embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a third structure of a display substrate in an exemplary embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a fourth structure of a display substrate in an exemplary embodiment of the present disclosure.
  • FIG. 7A is a schematic diagram after forming the first conductive layer in the display substrate shown in FIG. 3;
  • FIG. 7B is a schematic diagram after forming the semiconductor layer in the display substrate shown in FIG. 3;
  • FIG. 7C is a schematic diagram after forming the second conductive layer in the display substrate shown in FIG. 3;
  • FIG. 7D is a schematic diagram after forming a third insulating layer in the display substrate shown in FIG. 3;
  • FIG. 7E is a schematic diagram after forming the third conductive layer in the display substrate shown in FIG. 3;
  • FIG. 7F is a schematic diagram after forming the fifth insulating layer in the display substrate shown in FIG. 3;
  • FIG. 7G is a schematic diagram after forming the fourth conductive layer in the display substrate shown in FIG. 3;
  • FIG. 7H is a schematic diagram after forming the fifth conductive layer in the display substrate shown in FIG. 3;
  • FIG. 7I is a schematic diagram after forming a pixel definition layer in the display substrate shown in FIG. 3;
  • Figure 7J is a cross-sectional view of the display substrate shown in Figure 7I along the direction A-A';
  • FIG. 8A is a schematic diagram after forming the first conductive layer in the display substrate shown in FIG. 4;
  • FIG. 8B is a schematic diagram after forming the semiconductor layer in the display substrate shown in FIG. 4;
  • FIG. 8C is a schematic diagram after forming the second conductive layer in the display substrate shown in FIG. 4;
  • FIG. 8D is a schematic diagram after forming the third insulating layer in the display substrate shown in FIG. 4;
  • FIG. 8E is a schematic diagram after forming the third conductive layer in the display substrate shown in FIG. 4;
  • FIG. 8F is a schematic diagram after forming the fifth insulating layer in the display substrate shown in FIG. 4;
  • FIG. 8G is a schematic diagram after forming the fourth conductive layer in the display substrate shown in FIG. 4;
  • FIG. 8H is a schematic diagram after forming the fifth conductive layer in the display substrate shown in FIG. 4;
  • FIG. 8I is a schematic diagram after forming a pixel definition layer in the display substrate shown in FIG. 4;
  • Figure 8J is a cross-sectional view of the display substrate shown in Figure 8I along the direction A-A';
  • FIG. 9A is a schematic diagram after forming the first conductive layer in the display substrate shown in FIG. 5;
  • FIG. 9B is a schematic diagram after forming the semiconductor layer in the display substrate shown in FIG. 5;
  • FIG. 9C is a schematic diagram after forming the second conductive layer in the display substrate shown in FIG. 5;
  • FIG. 9D is a schematic diagram after forming the third insulating layer in the display substrate shown in FIG. 5;
  • FIG. 9E is a schematic diagram after forming the third conductive layer in the display substrate shown in FIG. 5;
  • FIG. 9F is a schematic diagram after forming the fifth insulating layer in the display substrate shown in FIG. 5;
  • FIG. 9G is a schematic diagram after forming the fourth conductive layer in the display substrate shown in FIG. 5;
  • FIG. 9H is a schematic diagram after forming the fifth conductive layer in the display substrate shown in FIG. 5;
  • FIG. 9I is a schematic diagram after forming a pixel definition layer in the display substrate shown in FIG. 5;
  • Figure 9J is a cross-sectional view of the display substrate shown in Figure 9I along the direction A-A';
  • FIG. 10A is a schematic diagram after forming the first conductive layer in the display substrate shown in FIG. 6;
  • FIG. 10B is a schematic diagram after forming the semiconductor layer in the display substrate shown in FIG. 6;
  • FIG. 10C is a schematic diagram after forming the second conductive layer in the display substrate shown in FIG. 6;
  • FIG. 10D is a schematic diagram after forming the third insulating layer in the display substrate shown in FIG. 6;
  • FIG. 10E is a schematic diagram after forming the third conductive layer in the display substrate shown in FIG. 6;
  • FIG. 10F is a schematic diagram after forming the fifth insulating layer in the display substrate shown in FIG. 6;
  • FIG. 10G is a schematic diagram after forming the fourth conductive layer in the display substrate shown in FIG. 6;
  • FIG. 10H is a schematic diagram after forming the fifth conductive layer in the display substrate shown in FIG. 6;
  • FIG. 10I is a schematic diagram after forming a pixel definition layer in the display substrate shown in FIG. 6;
  • Fig. 10J is a cross-sectional view of the display substrate shown in Fig. 10I along the direction A-A'.
  • connection should be interpreted in a broad sense unless otherwise specified and limited.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • connection should be interpreted in a broad sense unless otherwise specified and limited.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • electrically connected includes a case where constituent elements are connected together through an element having some kind of electrical function.
  • the "element having some kind of electrical action” is not particularly limited as long as it can transmit and receive electrical signals between connected components.
  • the "element having some kind of electrical function” may be, for example, an electrode or a wiring, or a switching element such as a transistor, or other functional elements such as a resistor, an inductor, or a capacitor.
  • a transistor refers to at least including a gate electrode (also referred to as a gate or a control electrode), a drain electrode (also referred to as a drain electrode terminal, a drain region, or a drain electrode), and a source electrode (also referred to as a A three-terminal element that may be called a source electrode terminal, a source region, or a source).
  • a transistor has a channel region between a drain electrode and a source electrode, and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the second electrode.
  • the first electrode may be the drain electrode and the second electrode may be the second electrode.
  • It may be a source electrode, or, the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged with each other.
  • the transistors in the exemplary embodiments of the present disclosure may be thin film transistors (Thin Film Transistor, TFT) or field effect transistors (Field Effect Transistor, FET) or other devices with the same characteristics.
  • the thin film transistors used in the embodiments of the present disclosure may include but not limited to oxide transistors (Oxide TFT) or low temperature polysilicon thin film transistors (Low Temperature Poly-silicon TFT, LTPS TFT) and the like.
  • the thin film transistor may be a thin film transistor with a bottom gate structure or a thin film transistor with a top gate structure, as long as the switching function can be realized.
  • the embodiments of the present disclosure do not limit this.
  • film and “layer” may be interchanged with each other.
  • conductive layer may sometimes be replaced with “conductive film”.
  • insulating film may sometimes be replaced with “insulating layer”.
  • the triangle, rectangle, trapezoid, pentagon, or hexagon are not strictly defined, and may be approximately triangular, approximately rectangular, approximately trapezoidal, approximately pentagonal, or approximately hexagonal, etc. , there may be some small deformations caused by tolerances, and there may be chamfers, arc edges, and deformations.
  • an "integrated structure" may refer to two (or more than two) structures formed through the same deposition process and patterned through the same patterning process to form interconnected structures. Materials can be the same or different.
  • the first direction DR1 may refer to the horizontal direction or the extending direction of the scanning signal lines, etc.
  • the second direction DR2 may refer to the vertical direction or the extending direction of the data signal lines, etc.
  • the third direction DR3 It may refer to the thickness direction of the display substrate or the direction perpendicular to the plane of the display substrate.
  • the first direction DR1 intersects with the second direction DR2, and the first direction DR1 intersects with the third direction DR3.
  • the first direction DR1 and the second direction DR2 may be perpendicular to each other
  • the first direction DR1 and the third direction DR3 may be perpendicular to each other.
  • Transparent display is an important personalized display field in display technology. It refers to image display in a transparent state. The viewer can not only see the image in the display device, but also see the scene behind the display device, which can give the viewer It brings a different visual experience and makes the visual impact felt by the viewer more intense.
  • FIG. 1 is a schematic structural view of a transparent OLED display substrate.
  • the display area (Area AA) of the transparent OLED display substrate may include: a plurality of pixel (Pixel) units P arranged in an array, and each pixel unit P may include: a pixel area 100 and a transparent area 200 , each pixel unit P may include: a plurality of sub-pixels located in the pixel area 100 .
  • the pixel region 100 which may be referred to as a pixel aperture ratio (Aperture Ratio, AR) region, is provided with a pixel driving circuit and a light emitting device (such as an OLED), and is configured to realize image display by controlling the OLED to emit light.
  • each pixel unit P includes: a red (Red, R) sub-pixel, a green (Green, G) sub-pixel, a blue (Blue, B) sub-pixel and a white (White , W) sub-pixel as an example to illustrate.
  • the display substrate may include: a transparent area and a pixel area, the pixel area includes: a plurality of light emitting devices, and the plurality of light emitting devices include: a first light emitting device, a first anode layer of the first light emitting device
  • the orthographic projection on the plane of the display substrate overlaps with the orthographic projection of the transparent area on the plane of the display substrate, and the orthographic projection of the second anode layer of the first light-emitting device on the plane of the display substrate is located within the range of the orthographic projection of the pixel area on the plane of the display substrate Inside.
  • the display substrate provided by the exemplary embodiment of the present disclosure, by extending the first anode layer of the first light-emitting device to the transparent area, the pixel area can be increased without reducing the area of the transparent area, so that The pixel aperture ratio has been improved to a certain extent, thus, the display effect can be improved.
  • the first anode layer is usually formed of a transparent conductive material, the display effect can be improved without affecting the transparency effect.
  • the pixel area may refer to the area where the light-emitting device and the pixel driving circuit for driving the light-emitting device are arranged
  • the transparent area may refer to the area where the pixel driving circuit is not provided, and has a higher light transmittance for the transmission of natural light.
  • the transmittance of the transparent area is greater than the transmittance of the pixel area.
  • the transmittance of multiple film layers in the transparent region may be greater than 80%.
  • the orthographic projection of the light-emitting (Emitted-Light, EL) layer of the first light-emitting device on the plane of the display substrate overlaps with the orthographic projection of the transparent area on the plane of the display substrate, and overlaps with the pixel area on the plane of the display substrate.
  • the orthographic projections showing the substrate planes partially overlap.
  • the light transmittance of the first anode layer is greater than the light transmittance of the second anode layer.
  • the first anode layer is made of a transparent conductive material.
  • the transparent conductive material may include: indium tin oxide or indium zinc oxide.
  • the embodiments of the present disclosure do not limit this.
  • the second anode layer is formed of a metal material, or formed of a metal material and a transparent conductive material.
  • the embodiments of the present disclosure do not limit this.
  • the plurality of light emitting devices may further include: a second light emitting device, the orthographic projection of the first anode layer of the second light emitting device on the plane of the display substrate, the second anode layer of the second light emitting device
  • the orthographic projection of the substrate plane and the orthographic projection of the light-emitting (EL) layer of the second light emitting device on the display substrate plane are all within the range of the orthographic projection of the pixel area on the display substrate plane.
  • the first light-emitting device can be a white (W) light-emitting device
  • the second light-emitting device can include but not limited to: red (R) light-emitting device, green (G) light-emitting device or blue (B) light-emitting device, etc. device.
  • red (R) light-emitting device green (G) light-emitting device or blue (B) light-emitting device, etc. device.
  • the plurality of light emitting devices may include: a first light emitting device and three second light emitting devices, the first light emitting device includes: a white light emitting device, and the three second light emitting devices may include: a red light emitting device A light-emitting device, a green light-emitting device and a blue light-emitting device, the area of the second anode layer of the blue light-emitting device is larger than the area of the second anode layer of the red light-emitting device and the area of the second anode layer of the green light-emitting device, white light emitting The area of the second anode layer of the device is smaller than the area of the second anode layer of the red light emitting device and the area of the second anode layer of the green light emitting device.
  • the area occupied by the white light emitting device in the pixel area can be reduced, so as to at least increase the area occupied by the blue light emitting device in the pixel area. Since the first anode layer in the white light-emitting device extends to the transparent area, the pixel area can be increased without reducing the area of the transparent area, so that the pixel aperture ratio can be improved to a certain extent, thereby improving the display effect.
  • the transparent area includes: a first transparent sub-area and a second transparent sub-area arranged in sequence along a first direction
  • the pixel area includes: a first area and a second area arranged in sequence along a second direction
  • the first area includes: a first sub-area and a second sub-area arranged in sequence along the first direction
  • the second area includes: a third sub-area and a fourth sub-area arranged in sequence along the first direction
  • a first light-emitting device The orthographic projection of the first anode layer on the display substrate plane at least partially overlaps with the orthographic projection of one of the first to fourth subregions on the display substrate plane, and overlaps with the first transparent subregion and the second transparent subregion.
  • the orthographic projection of one of the transparent sub-regions on the display substrate plane is at least partially overlapped; the orthographic projections of the first anode layers of the three second light-emitting devices on the display substrate plane are respectively with the Orthographic projections of the other three sub-regions on the plane of the display substrate at least partially overlap and are different from each other; the second direction intersects the first direction.
  • the length of the orthographic projection of the second anode layer of the blue light-emitting device on the plane of the display substrate is greater than the length of the orthographic projection of the second anode layer of the red light-emitting device on the plane of the display substrate.
  • the length of the orthographic projection of the second anode layer of the white light-emitting device on the plane of the display substrate and the length of the orthographic projection of the second anode layer of the white light emitting device on the plane of the display substrate, the length refers to a dimensional feature along the first direction. In this way, the area occupied by the blue light-emitting device in the pixel region can be increased.
  • the transparent area includes: a first transparent sub-area and a second transparent sub-area arranged in sequence along a first direction
  • the pixel area includes: a first area and a second area arranged in sequence along a second direction
  • the first area includes: the fifth sub-area and the sixth sub-area arranged in sequence along the second direction
  • the second area includes: the seventh sub-area and the eighth sub-area arranged in sequence along the second direction
  • a first light-emitting device The orthographic projection of the first anode layer on the display substrate plane at least partially overlaps with the orthographic projection of one of the fifth to eighth subregions on the display substrate plane, and overlaps with the first transparent subregion and the second transparent subregion.
  • the orthographic projection of one of the transparent sub-regions on the display substrate plane at least partially overlaps; the orthographic projections of the first anode layers of the three second light-emitting devices on the display substrate plane respectively overlap with the Orthographic projections of the other three sub-regions on the plane of the display substrate at least partially overlap and are different from each other; the second direction intersects the first direction.
  • the width of the orthographic projection of the second anode layer of the blue light-emitting device on the plane of the display substrate is greater than the width of the orthographic projection of the second anode layer of the red light-emitting device on the plane of the display substrate, and the width of the orthographic projection of the second anode layer of the red light-emitting device on the plane of the display substrate.
  • the width of the orthographic projection of the second anode layer of the white light-emitting device on the plane of the display substrate, and the width of the orthographic projection of the second anode layer of the white light emitting device on the plane of the display substrate, the width refers to the dimension characteristic along the second direction. In this way, the area occupied by the blue light-emitting device in the pixel region can be increased.
  • the pixel area may further include: a plurality of pixel driving circuits configured to drive light-emitting devices, and the orthographic projections of the plurality of pixel driving circuits on the display substrate plane are located in the pixel area on the display substrate plane within the range of the orthographic projection. In this way, it is possible to arrange the pixel driving circuit with relatively low light transmittance in the pixel area.
  • the pixel driving circuit may include: a first transistor, a second transistor, and a third transistor, the first transistor and the third transistor are located on both sides of the second transistor in the second direction, and the first transistor The extending directions of the channel regions of the second transistor and the third transistor are all the second direction.
  • the area occupied by the pixel driving circuit can be reduced, the layout space can be saved, the pixel size can be reduced, and a higher resolution (Pixel Per Inch, PPI) can be achieved. display effect.
  • the "extending direction of the channel region of the transistor" used in the embodiments of the present disclosure may refer to the extending direction of the connection line between the first region and the second region of the active layer of the transistor, that is, the first region of the transistor The extension direction of the connection line between the pole and the second pole of the transistor.
  • the pixel driving circuit may further include: a storage capacitor located between the second transistor and the third transistor, and the extension direction of the storage capacitor is the second direction. In this way, by optimizing the arrangement of transistors and storage capacitors, the area occupied by the pixel driving circuit can be reduced, and the layout space can be saved. display effect.
  • a plurality of pixel driving circuits may be arranged side by side along the first direction.
  • “side by side” used in the embodiments of the present disclosure means to be arranged in a straight line.
  • the pixel driving circuit includes: a first transistor, a second transistor, a third transistor, and a storage capacitor; in a direction perpendicular to the plane of the display substrate, the display substrate may include: The first conductive layer, the semiconductor layer, the second conductive layer and the third conductive layer; the first conductive layer includes: the first plate, and the semiconductor layer includes: the active layer of the first transistor, the active layer of the second transistor, the second transistor The active layer and the second plate of the three transistors, the second conductive layer includes: the gate electrode of the first transistor, the gate electrode of the second transistor and the gate electrode of the third transistor, and the third conductive layer may include: the gate electrode of the first transistor The first pole, the second pole of the first transistor, the first pole of the second transistor, the second pole of the second transistor, the first pole of the third transistor, the second pole of the third transistor and the third plate, the first The first pole plate and the second pole plate form a first storage capacitor, the second pole plate and the third pole plate form a second storage capacitor
  • the first conductive layer further includes: a compensation connection line
  • the third conductive layer further includes: a compensation signal line
  • the first electrode of the third transistor is connected to the compensation signal line through the compensation connection line.
  • the second conductive layer includes: a power connection line
  • the third conductive layer further includes: a first power line, and the first electrode of the second transistor is connected to the first power line through the power connection line;
  • a power line is connected to the power connection line through the via hole, and a double-layer wiring is formed between the gate electrode of the first transistor and the gate electrode of the third transistor.
  • the second conductive layer further includes: a first scanning signal line and a second scanning signal line, the gate electrode of the first transistor is connected to the first scanning signal line, and the gate electrode of the third transistor is connected to the first scanning signal line. Two scanning signal lines are connected.
  • the third conductive layer further includes: a data signal line, and the first electrode of the first transistor is connected to the data signal line.
  • the pixel driving circuit may include, but is not limited to adopt: 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C and other circuit structures.
  • 3T in “3T1C” refers to 3 transistors
  • 1C refers to a storage capacitor or a whole after multiple capacitors are connected in parallel; 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C, etc., and so on.
  • the embodiments of the present disclosure do not limit this.
  • FIG. 2 is a schematic diagram of an equivalent circuit of a pixel driving circuit.
  • the pixel driving circuit may include: 3 transistors (the first transistor T1, the second transistor T2 and the third transistor T3) and 1 storage capacitor C; the display substrate also includes: 6 signal lines (data signal line Data, the first scanning signal line G1, the second scanning signal line G2, the compensation signal line Sense, the first power line VDD and the second power line VSS).
  • the first transistor T1 is a switching transistor
  • the second transistor T2 is a driving transistor
  • the third transistor T3 is a compensation transistor.
  • the gate electrode of the first transistor T1 is coupled to the first scanning signal line G1, the first pole of the first transistor T1 is coupled to the data signal line Data, and the second pole of the first transistor T1 is coupled to the gate of the second transistor T2. electrode, the first transistor T1 is configured to receive the data signal transmitted by the data signal line Data under the control of the first scanning signal line G1, so that the gate electrode of the second transistor T2 receives the data signal.
  • the gate electrode of the second transistor T2 is coupled to the second pole of the first transistor T1, the first pole of the second transistor T2 is coupled to the first power line VDD, and the second pole of the second transistor T2 is coupled to the light emitting device L
  • the second transistor T2 is configured to generate a corresponding current at the second electrode under the control of the data signal received by its gate electrode.
  • the gate electrode of the third transistor T3 is coupled to the second scanning signal line G2, the first pole of the third transistor T3 is coupled to the compensation signal line Sense, and the second pole of the third transistor T3 is coupled to the first pole of the second transistor T2.
  • the third transistor T3 is configured to extract the threshold voltage Vth and the mobility of the second transistor T2 in response to the compensation timing, so as to compensate the threshold voltage Vth.
  • the first pole of the light emitting device L is coupled to the second pole of the second transistor T2, the second pole of the light emitting device L is coupled to the second power line VSS, and the light emitting device L is configured to respond to the second pole of the second transistor T2 The current emits light of corresponding brightness.
  • the first electrode of the storage capacitor C is coupled to the gate electrode of the second transistor T2, the second electrode of the storage capacitor C is coupled to the second electrode of the second transistor T2, and the storage capacitor C is configured to store the gate electrode of the second transistor T2. electrode potential.
  • the signal of the first power line VDD is a continuously high level signal
  • the signal of the second power line VSS is a low level signal
  • the first transistor T1 to the third transistor T3 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield rate of the product.
  • the first to third transistors T1 to T3 may include P-type transistors and N-type transistors.
  • the first scanning signal line S1 and the second scanning signal line S2 may extend along the first direction DR1
  • the second power line VSS, the first power line VDD and the data signal line Data may extend along the second direction DR1.
  • the direction DR2 extends.
  • the light emitting device L may be an electronic device with light emitting performance.
  • the light emitting device may include: an organic electroluminescence diode (OLED) or a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED) and the like.
  • OLED organic electroluminescence diode
  • QLED quantum dot light emitting diode
  • the embodiments of the present disclosure do not limit this.
  • the light-emitting device L may include: a stacked first electrode (for example, as an anode), an organic light-emitting layer, and a second electrode (for example, as a cathode) .
  • At least one of the plurality of pixel units P may include: four sub-pixels, wherein one of the four sub-pixels may be a white (W) sub-pixel, and all but the four sub-pixels may be The other three sub-pixels other than one sub-pixel may be any one of red (R) sub-pixel, green (G) sub-pixel and blue (B) sub-pixel and are different from each other.
  • the four sub-pixels may include: a first sub-pixel P1 emitting light of the first color, a second sub-pixel P2 emitting light of the second color, a third sub-pixel P3 emitting light of the third color, and a second sub-pixel P3 emitting light of the fourth color.
  • the first sub-pixel P1 may be a red (R) sub-pixel
  • the second sub-pixel P2 may be a green (G) sub-pixel
  • the third sub-pixel P3 may be a blue (B) sub-pixel.
  • the four sub-pixels P4 may be white (W) sub-pixels.
  • the embodiments of the present disclosure do not limit this.
  • the four sub-pixels may be arranged in a rectangular manner, vertically or horizontally.
  • the embodiments of the present disclosure do not limit this.
  • one light emitting device and one corresponding pixel driving circuit can be divided into one sub-pixel.
  • the white (W) sub-pixel may include a white light-emitting device and a pixel driving circuit connected to the white light-emitting device
  • the red (R) sub-pixel may include a red light-emitting device and a pixel driving circuit connected to the white light-emitting device
  • the green (G) sub-pixel may include a green light-emitting device and a pixel drive circuit connected to the white light-emitting device
  • the blue (B) sub-pixel may include a blue light-emitting device and a pixel drive circuit connected to the white light-emitting device.
  • the first sub-pixel P1 is a red (R) sub-pixel
  • the second sub-pixel P2 is a green (G) sub-pixel
  • the third sub-pixel P3 is a blue (B) sub-pixel
  • the fourth sub-pixel P4 is a white ( W) sub-pixel as an example
  • a white light-emitting device is used as the first light-emitting device
  • a red light-emitting device, a blue light-emitting device, and a green light-emitting device are used as the second light-emitting device for illustration.
  • FIG. 3 is a schematic diagram of a first structure of a display substrate in an exemplary embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a second structure of a display substrate in an exemplary embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a third structure of a display substrate in an exemplary embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a fourth structure of a display substrate in an exemplary embodiment of the present disclosure.
  • two pixel units on the display substrate are taken as an example for illustration.
  • four sub-pixels can be arranged in a rectangular manner as an example for illustration.
  • four sub-pixels can be vertically juxtaposed as an example for illustration.
  • the display substrate may include: a plurality of pixel regions 100 and a plurality of transparent regions 200 arranged alternately.
  • the display substrate may further include: a plurality of pixel (Pixel) units arranged in an array, and each pixel unit may include: a transparent region 200 and a pixel region 100 sequentially arranged along the first direction DR1.
  • the second light emitting devices of the first sub-pixel P1 , the second sub-pixel P2 and the third sub-pixel P3 are formed in the pixel region 100 of the pixel unit.
  • the first light-emitting device of the fourth subpixel P4 is formed in the pixel area 100 and the transparent area 200 in this pixel unit, or, as shown in FIG. 3 and FIG. 6, the fourth subpixel P4
  • the first light-emitting device is formed in the pixel region 100 in the current pixel unit and the transparent region 200 in the adjacent pixel unit.
  • the pixel driving circuits of the first sub-pixel P1 to the fourth sub-pixel P4 are all formed in the pixel region 100 of the pixel unit.
  • the first electrode layer in the first light-emitting device of the fourth sub-pixel P4 includes: a pixel area located in the pixel unit 100 and the extension of the transparent region 200 located in this pixel unit, or, as shown in FIG. 3 and FIG. 6 , the first electrode layer in the first light-emitting device of the fourth sub-pixel P4 includes: The main body of the pixel region 100 in a unit and the extension of the transparent region 200 in an adjacent pixel unit. In this way, the first light emitting device can be extended to the transparent area.
  • the transparent region 200 may include: a first transparent subregion 201 and a second transparent subregion 202 sequentially arranged along the first direction DR1
  • the pixel region 100 may include: a first region 101 and a second region 102 sequentially arranged along the second direction DR2
  • the first region 101 may include: a first subregion 101-1 and a second subregion 101-1 arranged sequentially along the first direction DR1
  • the area 101-2, the second area 102 may include: a third sub-area 102-1 and a fourth sub-area 102-2 arranged in sequence along the first direction DR1.
  • the second light-emitting device of each first sub-pixel P1 is formed in the first sub-region 101-1 of the pixel unit, and the second light-emitting device of each second sub-pixel P2 is formed in the current sub-region 101-1.
  • the second light-emitting device of the third sub-pixel P3 is formed in the third sub-region 102-1 of the pixel unit, and the first light-emitting device of the fourth sub-pixel P4 is formed in the current sub-region 102-1.
  • the fourth sub-region 102-2 in the pixel unit and the first transparent sub-region 201 in the adjacent pixel unit.
  • the first anode layer of each fourth sub-pixel P4 may include: a main body part located in the pixel area 100 and an extension part located in the transparent area 200, the main part and the extension part The section may be located in adjacent two pixel units.
  • the fourth sub-region 102-2 in the first pixel unit is located at the lower right side of the pixel region 100, adjacent to the first transparent sub-region 201 in the transparent region 200 of the second pixel unit, therefore, the first pixel unit
  • the main part of the fourth sub-pixel P4 in the first pixel unit can be set in the fourth sub-region 102-2, and the extension part of the fourth sub-pixel P4 in the first pixel unit can be set in the second pixel unit The first transparent sub-region 201 .
  • the fourth sub-pixel P4 (ie, the white sub-pixel) in the first pixel unit can be extended to the transparent area in the second pixel unit, which can increase the aperture ratio.
  • the first light emitting device of the fourth sub-pixel P4 can also be formed in other sub-regions (for example, the second sub-region) in the pixel area of the pixel unit. 101-2) and the first transparent sub-region 201 in adjacent pixel units.
  • the embodiments of the present disclosure do not limit this.
  • the transparent region 200 may include: a first transparent subregion 201 and a second transparent subregion 202 sequentially arranged along the first direction DR1
  • the pixel region 100 may include: a first region 101 and a second region 102 sequentially arranged along the second direction DR2
  • the first region 101 may include: a first subregion 101-1 and a second subregion 101-1 arranged sequentially along the first direction DR1
  • the area 101-2, the second area 102 may include: a third sub-area 102-1 and a fourth sub-area 102-2 arranged in sequence along the first direction DR1.
  • the second light-emitting device of each first sub-pixel P1 is formed in the first sub-region 101-1 of the pixel unit, and the second light-emitting device of each second sub-pixel P2 is formed in the current sub-region 101-1.
  • the second light-emitting device of the third sub-pixel P3 is formed in the fourth sub-region 102-2 of the pixel unit, and the first light-emitting device of the fourth sub-pixel P4 is formed in the current The third sub-region 102-1 and the second transparent sub-region 202 in the pixel unit.
  • the first anode layer of the first light emitting device of each fourth sub-pixel P4 may include: a main body part located in the pixel area 100 and an extension part located in the transparent area 200 , the main body part and the extension part may be located in the same pixel unit.
  • the first pixel unit can be set in the third sub-region 102-1, and the extension part of the fourth sub-pixel P4 in the first pixel unit can be set in the third sub-region 102-1 in the first pixel unit.
  • the second transparent sub-region 202 In this way, the fourth sub-pixel P4 (ie, the white sub-pixel) in the first pixel unit can be extended to the transparent area in the first pixel unit, which can increase the aperture ratio.
  • the first light-emitting device of the fourth sub-pixel can also be formed in other sub-regions (for example, the first sub-region 101 -1) and in the second transparent sub-region 202.
  • the embodiments of the present disclosure do not limit this.
  • the transparent region 200 may include: a first transparent subregion 201 and a second transparent subregion 202 sequentially arranged along the first direction DR1
  • the pixel region 100 may include: a first region 101 and a second region 102 sequentially arranged along the second direction DR2
  • the first region 101 may include: a fifth subregion 101-3 and a sixth subregion 101-3 arranged sequentially along the second direction DR2
  • the area 101-4, the second area 102 may include: a seventh sub-area 102-3 and an eighth sub-area 102-4 arranged in sequence along the second direction DR2.
  • the second light-emitting device of each first sub-pixel P1 is formed in the fifth sub-region 101-3 in this pixel unit, and the second light-emitting device of each second sub-pixel P2 is formed in this pixel unit.
  • the second light-emitting device of the third sub-pixel P3 is formed in the seventh sub-region 102-3 of the pixel unit, and the first light-emitting device of the fourth sub-pixel P4 is formed in this pixel unit.
  • the first anode layer of the first light emitting device of each fourth sub-pixel P4 may include: a main body part located in the pixel area 100 and an extension part located in the transparent area 200 , the main body part and the extension part may be located in the same pixel unit.
  • the eighth sub-region 102-4 in the first pixel unit is adjacent to the second transparent sub-region 202 in the first pixel unit, the main body portion of the fourth sub-pixel P4 in the first pixel unit can be disposed on The eighth sub-region 102-4 in the first pixel unit, the extension of the fourth sub-pixel P4 in the first pixel unit may be disposed in the second transparent sub-region 202 in the first pixel unit.
  • the fourth sub-pixel P4 ie, the white sub-pixel
  • the first pixel unit can be extended to the transparent area in the first pixel unit, which can increase the aperture ratio.
  • the fourth sub-pixel P4 can also be formed in other sub-regions (for example, the fifth sub-region 101-3, the any one of the sixth sub-region 101-4 and the seventh sub-region 102-3) and the second transparent sub-region 202.
  • the embodiments of the present disclosure do not limit this.
  • the transparent region 200 may include: a first transparent subregion 201 and a second transparent subregion 202 sequentially arranged along the first direction DR1
  • the pixel region 100 may include: a first region 101 and a second region 102 sequentially arranged along the second direction DR2
  • the first region 101 may include: a fifth subregion 101-3 and a sixth subregion 101-3 arranged sequentially along the second direction DR2
  • the area 101-4, the second area 102 may include: a seventh sub-area 102-3 and an eighth sub-area 102-4 arranged in sequence along the second direction DR2.
  • the second light-emitting device of each first sub-pixel P1 is formed in the fifth sub-region 101-3 in this pixel unit, and the second light-emitting device of each second sub-pixel P2 is formed in this pixel unit.
  • the second light-emitting device of the third sub-pixel P3 is formed in the seventh sub-region 102-3 of the pixel unit, and the first light-emitting device of the fourth sub-pixel P4 is formed in this pixel unit.
  • the first anode layer of the first light emitting device of each fourth sub-pixel P4 may include: a main body part located in the pixel area 100 and an extension part located in the transparent area 200 , the main body portion and the extension portion may be located in two adjacent pixel units.
  • the eighth sub-region 102-4 in the first pixel unit is adjacent to the first transparent sub-region 201 in the second pixel unit, the main part of the fourth sub-pixel P4 in the first pixel unit can be disposed on The eighth sub-region 102-4 in the first pixel unit, the extension of the fourth sub-pixel P4 in the first pixel unit may be disposed in the first transparent sub-region 201 in the second pixel unit.
  • the fourth sub-pixel P4 ie, the white sub-pixel
  • the first pixel unit can be extended to the transparent area in the first pixel unit, which can increase the aperture ratio.
  • the first light emitting device of the fourth subpixel P4 can also be formed in other subregions (for example, the fifth subregion) in the pixel region of the pixel unit. 101-3, any one of the sixth sub-region 101-4 and the seventh sub-region 102-3) and the first transparent sub-region 201 in the adjacent sub-pixel.
  • the embodiments of the present disclosure do not limit this.
  • the area of the pixel region 100 may be about 30% to 35% of the area of the pixel unit.
  • the area of the transparent region 200 may be about 42% to 47% of the area of the pixel unit.
  • the area of the transparent region 200 may be about 45% of the area of the pixel unit.
  • the embodiments of the present disclosure do not limit this.
  • the area occupied by the light-emitting device of the red (R) sub-pixel may be about 30% to 36.37% of the area of the pixel region 100, and the area occupied by the green (G) sub-pixel
  • the area where the light emitting device is located may be about 25% to 29.1% of the area of the pixel area 100, or the area where the light emitting device of the blue (B) sub-pixel is located may be about 35% to 40% of the area of the pixel area 100. %.
  • the area where the light-emitting device of the white (W) sub-pixel is located may be about 40% to 46.5% of the area of the pixel unit.
  • the embodiments of the present disclosure do not limit this.
  • the structure of the display substrate will be described below by way of an example of the manufacturing process of the display substrate.
  • the “patterning process” mentioned in this disclosure includes deposition of film layer, coating of photoresist, mask exposure, development, etching and stripping of photoresist. Any one or more of sputtering, evaporation and chemical vapor deposition can be used for deposition, any one or more of spray coating and spin coating can be used for coating, and any of dry etching and wet etching can be used for etching. one or more.
  • “Film” refers to a layer of film produced by depositing or coating a certain material on a substrate.
  • the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "film” requires a patterning process during the entire production process, it is called a “film” before the patterning process, and it is called a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”. "A and B are arranged in the same layer” in this disclosure means that A and B are formed simultaneously through the same patterning process.
  • the display substrate in a direction perpendicular to the plane of the display substrate (that is, the third direction DR3), may include: a base, a first conductive layer, a first insulating layer stacked on the base in sequence , a semiconductor layer, a second insulating layer, a second conducting layer, a third insulating layer, a third conducting layer, a fourth insulating layer, a fifth insulating layer, a fourth conducting layer and a fifth conducting layer.
  • FIG. 7A to 7I are schematic diagrams of the preparation process of the display substrate shown in FIG. 3 , which illustrate the layout structure of two pixel units of the display substrate.
  • FIG. 7J is a cross-sectional view of the display substrate shown in FIG. 7I along the AA' direction . Referring to the structure of the display substrate shown in FIG. 3 , and referring to FIG. 7A to FIG. 7J , the preparation process of the display substrate provided in the exemplary embodiment of the present disclosure will be described.
  • each pixel unit includes a pixel area 100 and a transparent area 200, each pixel unit includes a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3 and a fourth sub-pixel P4 , the pixel driving circuit of each sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor C.
  • the pixel driving circuits of the third sub-pixel P3 , the first sub-pixel P1 , the second sub-pixel P2 and the fourth sub-pixel P4 are sequentially arranged along the first direction DR1 .
  • the preparation process of the display substrate may include the following steps:
  • forming the first conductive layer may include: depositing a first conductive film on the substrate, patterning the first conductive film through a patterning process, and forming the first conductive layer on the substrate.
  • the first conductive layer may be formed using a metal material.
  • metal materials may include, but are not limited to: any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the metals listed above, such as aluminum Neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), etc.
  • the first conductive layer may be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo and the like.
  • the first conductive layer may be called a shield (Shield, SHL) layer.
  • the first conductive layer may include: a compensation connection line 51 and a first plate 41 .
  • the compensation connection line 51 may be a strip structure extending along the first direction DR1 .
  • the compensation connection line 51 may be arranged across four sub-pixels and configured to be connected to the subsequently formed compensation signal line Sense, so that the compensation signal line Sense provides a compensation signal to the third transistor T3 of each sub-pixel.
  • the first plate 41 can be arranged in each sub-pixel, and the first plate 41 can be used as a plate of the first storage capacitor Cst1, configured as The first storage capacitor Cst1 is formed with the subsequently formed second plate, and the first plate 41 can also be used as a shielding layer, configured to perform light-shielding treatment on the transistor in the sub-pixel, reduce the light intensity irradiated on the transistor, and reduce the Leakage current, thereby reducing the impact of light on transistor characteristics.
  • four first pole plates 41 may be arranged in sequence along the first direction DR1.
  • the shape of the first pole plate 41 may be a strip-shaped rectangular structure extending along the second direction DR2, and the corners of the rectangular structure may be chamfered.
  • the first electrode plate 41 can completely cover the pixel driving circuit area of each sub-pixel.
  • the length of the first plate 41 may be greater than the distance between the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 formed subsequently, or the first plate 41 The length of 41 may be greater than the distance between the first electrode of the subsequently formed first transistor and the first electrode of the third transistor.
  • the first conductive layer pattern in the third sub-pixel P3 and the first conductive layer pattern in the fourth sub-pixel P4 are mirror-symmetrical with respect to the vertical axis, and the first conductive layer pattern in the first sub-pixel P1 The conductive layer pattern is mirror-symmetrical to the first conductive layer pattern in the second sub-pixel P2 with respect to the vertical axis.
  • the first conductive layer pattern is formed in the pixel region 100 , and the transparent region 200 has no corresponding film layer.
  • forming the semiconductor layer may include: sequentially depositing a first insulating film and a semiconductor film on the substrate forming the aforementioned structure, patterning the semiconductor film through a patterning process, and forming a second layer covering the first conductive layer.
  • the first insulating layer may be called a buffer (Buffer) layer
  • the semiconductor layer may be called an Active (ACT) layer.
  • the semiconductor layer may include: a first active layer 11, a second active layer 21, a third active layer 31 and a second plate of each sub-pixel 42.
  • the first active layer 11 is used as the active layer of the first transistor T1
  • the second active layer 21 is used as the active layer of the second transistor T2
  • the third active layer 11 is used as the active layer of the second transistor T2.
  • the source layer 31 serves as an active layer of the third transistor T3.
  • Each of the first active layer 31 , the second active layer 32 and the third active layer 33 includes a channel region and first and second regions located on both sides of the channel region.
  • the shape of the first active layer 11 may be a "Z" shape extending along the second direction DR2.
  • the shape of the second active layer 21 may be an "I" shape extending along the second direction DR2.
  • the orthographic projections of the first active layer 11, the second active layer 21, and the third active layer 31 on the substrate 10 are the same as the first polar plate 41 on the substrate.
  • the first plate 41 as a shielding layer can shield the channel regions of the first transistor, the second transistor and the third transistor, so as to avoid the impact of light on the channel, so as to avoid the channel
  • the display effect is affected due to the generation of photo-generated leakage.
  • the orthographic projection of the first active layer 11, the second active layer 21 and the third active layer 31 on the substrate 10 is the same as that of the second electrode plate 42 on the substrate.
  • the orthographic projection on 10 is arranged at intervals, that is, between the first active layer 11 and the second pole plate 42, between the second active layer 21 and the second pole plate 42, and between the third active layer 31 and the second pole plate There is no overlapping area between 42, which is beneficial to design the channel width-to-length ratios of the first transistor T1, the second transistor T2 and the third transistor T3 according to relevant requirements.
  • the shape of the second pole plate 34 may be a rectangle extending along the second direction DR2.
  • rectangular corners may be chamfered.
  • the edges of a rectangular shape may be polylines.
  • the embodiments of the present disclosure do not limit this.
  • the second plate 42 serves as both a plate of the first storage capacitor Cst1 and a plate of the second storage capacitor Cst2 .
  • the orthographic projection of the second pole plate 42 on the substrate 10 overlaps with the orthographic projection of the first pole plate 41 on the substrate 10, and the second pole plate 42 is configured to form a first storage space with the first pole plate 41.
  • the orthographic projection of the second pole plate 42 on the substrate 10 overlaps with the orthographic projection of the subsequently formed third pole plate 43 on the substrate 10, and the second pole plate 42 is also configured to overlap with the subsequently formed third pole plate 43 forms the second storage capacitor Cst2.
  • the overall capacitance value of the storage capacitor C can be increased.
  • a space 44 is provided between the second plate 42 in the first sub-pixel P1 and the second sub-pixel P2 and the third active layer 31, and the third sub-pixel An opening 45 is disposed in the second plate 42 of the pixel P3 and the fourth sub-pixel P4.
  • the semiconductor layer pattern in the third sub-pixel P3 is mirror-symmetrical to the semiconductor layer pattern in the fourth sub-pixel P4 with respect to the vertical axis.
  • the semiconductor layer pattern in the first sub-pixel P1 is mirror-symmetrical to the semiconductor layer pattern in the second sub-pixel P2 with respect to the vertical axis.
  • the semiconductor layer may be made of metal oxide material.
  • metal oxide materials may include, but are not limited to: oxides containing indium and tin, oxides containing tungsten and indium, oxides containing tungsten and indium and zinc, oxides containing titanium and indium, oxides containing titanium and indium and tin oxides, oxides containing indium and zinc, oxides containing silicon and indium and tin, oxides containing indium, gallium and zinc, and the like.
  • the semiconductor layer may be a single layer, a double layer, or a multilayer, and the like. Here, the embodiments of the present disclosure do not limit this.
  • the first insulating layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be single layer, multilayer layers or composite layers.
  • a semiconductor layer pattern is formed in the pixel region 100 , and the transparent region 200 includes the substrate 10 and the first insulating layer 61 disposed on the substrate 10 .
  • forming the second conductive layer may include: sequentially depositing a second insulating film and a second conductive film on the substrate forming the aforementioned structure, and patterning the second insulating film and the second conductive film through a patterning process. Patterning is performed to form a second insulating layer 62 and a second conductive layer disposed on the second insulating layer 62 .
  • the second insulating layer 62 has the same pattern as the second conductive layer.
  • the second insulating layer may be called a gate insulating (GI) layer.
  • the second conductive layer may be called a gate metal (Gate, GT) layer.
  • the second insulating layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be single-layer, multilayer layers or composite layers.
  • the second conductive layer may be formed using a metal material.
  • metal materials may include, but are not limited to: any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the metals listed above, such as aluminum Neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), etc.
  • the third conductive layer may be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo and the like.
  • the second conductive layer may include: the first scanning signal line G1, the second scanning signal line G2, the power connection line 52 and the auxiliary power supply line 53, and each The first gate electrode 12, the second gate electrode 22 and the third gate electrode 32 of the pixel.
  • the first scanning signal line G1 and the second scanning signal line G2 may have a strip structure extending along the first direction DR1 .
  • the first scanning signal line G1 and the second scanning signal line G2 may be arranged across the first sub-pixel P1 to the fourth sub-pixel P4.
  • the first scanning signal line G1 and the second scanning signal line G2 may be arranged in parallel.
  • the first scanning signal line Gn is located on the upper side of the sub-pixel
  • the second scanning signal line Sn is located on the lower side of the sub-pixel
  • the first scanning signal line G1 and the second scanning signal line G2 may be arranged with equal widths.
  • the first scanning signal line G1 and the second scanning signal line G2 may be arranged mirror-symmetrically with respect to the vertical axis (for example, the subsequently formed compensation signal line Sense).
  • the first gate electrode 12 may be disposed in each sub-pixel as the gate electrode of the first transistor T1. In each sub-pixel, there is an overlapping area between the orthographic projection of the first gate electrode 12 on the substrate and the orthographic projection of the first active layer 11 on the substrate.
  • the first gate electrode 12 and the first scanning signal line G1 may be an integral structure connected to each other.
  • the second gate electrode 22 may be disposed in each sub-pixel as the gate electrode of the second transistor T2.
  • the orthographic projection of the second gate electrode 22 on the substrate overlaps with the orthographic projection of the second active layer 21 on the substrate, and overlaps with the orthographic projection of the second electrode plate 42 on the substrate.
  • a third gate electrode 32 may be provided in each sub-pixel as the gate electrode of the third transistor T3. There is an overlapping area between the orthographic projection of the third gate electrode 32 on the substrate and the orthographic projection of the third active layer 31 on the substrate.
  • the third gate electrode 32 and the second scanning signal line G2 may be an integral structure connected to each other.
  • the power connection line 52 may be a bar-shaped structure whose main part extends along the second direction DR2, and the power connection line 52 may include: A first connection bar and a second connection bar extending along the first direction DR1.
  • the first connection bar of the power connection line 52 is configured to be connected to the subsequently formed first power line VDD through the subsequently formed via hole
  • the second connection bar of the power supply connection line 52 is configured to be connected to the subsequently formed via hole.
  • the third connecting electrode 23 formed subsequently is connected. In this way, on the one hand, double-layer wiring can be formed to ensure the reliability of power signal transmission and reduce the resistance of the first power line VDD.
  • the third connecting electrode 23 can be with the third connection electrode 23.
  • the auxiliary power line 53 may be a strip structure extending along the second direction DR2.
  • the auxiliary power line 53 is configured to be connected to the subsequently formed second power line VSS to form a double-layer wiring to ensure the reliability of power signal transmission and reduce the resistance of the second power line VSS.
  • the main body portion of the auxiliary power line 53 and the main body portion of the power connection line 52 ie, the first connecting bar
  • the main body portion of the auxiliary power line 53 and the main body portion of the power connection line 52 may be arranged mirror-symmetrically with respect to the vertical axis (eg, the subsequently formed compensation signal line Sense).
  • the main part of the power connection line 52 and the main part of the auxiliary power line 53 may be arranged in parallel.
  • the pattern of the second insulating layer 62 is the same as that of the second conductive layer, that is, the second insulating layer 62 is located below the second conductive layer, and there is no second insulating layer 62 in areas other than the second conductive layer.
  • the first gate electrode 12, the second gate electrode 22 and the third gate electrode 32 in the third sub-pixel P3 and the fourth sub-pixel P4 are mirror-symmetrical with respect to the vertical axis
  • the first sub-pixel P1 is mirror-symmetrical to the first gate electrode 12 , the second gate electrode 22 and the third gate electrode 32 in the second sub-pixel P2 with respect to the vertical axis.
  • this process may further include conductorization treatment.
  • the conductive treatment is to use the first gate electrode 12, the second gate electrode 22 and the third gate electrode 32 as shields to perform plasma treatment after forming the second conductive layer pattern, and the first gate electrode 12, the second gate electrode
  • the semiconductor layer of the electrode 22 and the third gate electrode 32 shielding area (that is, the area where the semiconductor layer overlaps with the first gate electrode 12, the second gate electrode 22 and the third gate electrode 32) is used as the channel area of the transistor, and is not covered by the second gate electrode.
  • the semiconductor layer in the metal layer shielding area is processed into a conductorized layer to form a conductorized second plate 42 and a conductorized source-drain region (that is, the first region of the transistor and the second region of the transistor located on both sides of the channel region of the transistor). Second District).
  • the first transistor T1 and the third transistor T2 are located on both sides of the second transistor T2 in the second direction, and the first transistor T2
  • the extension directions of the channel regions of the transistor T1, the second transistor T2 and the third transistor T3 are all in the second direction.
  • the extending direction of the channel region of the transistor is indicated by a dotted line.
  • the extending direction of the channel region of the first transistor T1 may refer to the extending direction of the connection line between the first pole of the first transistor T1 and the second pole of the first transistor T2.
  • the storage capacitor C is located between the second transistor T1 and the third transistor T3, and the extension direction of the storage capacitor C is the second direction.
  • pixel driving circuits of four sub-pixels are arranged side by side along the first direction DR1 .
  • the second conductive layer pattern is formed in the pixel region 100 , and the transparent region 200 includes the substrate 10 and the first insulating layer 61 disposed on the substrate 10 .
  • forming the third insulating layer may include: depositing a third insulating film on the substrate forming the aforementioned structure, and patterning the third insulating film through a patterning process to form a third insulating layer covering the aforementioned structure.
  • Layer 63 pattern For example, the third insulating layer may be called an interlayer dielectric (ILD) layer.
  • ILD interlayer dielectric
  • a plurality of via holes are provided on the third insulating layer 63, and the plurality of via holes may include: a first via hole V1, a second via hole V2, a third via hole Hole V3, fourth via V4, fifth via V5, sixth via V6, seventh via V7, eighth via V8, ninth via V9, tenth via V10, eleventh via V11 and the twelfth via V12.
  • the first via hole V1 and the second via hole V2 may be provided in each sub-pixel, for example, the first via hole V1 and the second via hole V2 may be provided in The two sides of the first gate electrode 12 of each sub-pixel.
  • the orthographic projection of the first via hole V1 on the substrate is within the range of the orthographic projection of the first region of the first active layer 11 in the sub-pixel on the substrate
  • the second via hole V2 is within the range of the orthographic projection of the first region of the first active layer 11 on the substrate.
  • the orthographic projection on is located within the range of the orthographic projection of the second region of the first active layer 11 in the sub-pixel on the substrate.
  • the third insulating layer 63 inside the first via hole V1 and the second via hole V2 is etched away, exposing the surfaces at both ends of the first active layer 11 .
  • the first via hole V1 is configured so that the first electrode of the subsequently formed first transistor T1 is connected to the first region of the first active layer 11 and the subsequently formed data signal line Data through the via hole
  • the second via hole V2 is configured to connect the second electrode of the subsequently formed first transistor T1 to the second region of the first active layer 11 through the via hole.
  • the third via hole V3 and the fourth via hole V4 may be provided in each sub-pixel, for example, the third via hole V3 and the fourth via hole V4 may be provided in The two sides of the second gate electrode 22 of each sub-pixel.
  • the third via hole V3 and the fourth via hole V4 may be provided in The two sides of the second gate electrode 22 of each sub-pixel.
  • the third via hole V3 is a transfer via hole, and the transfer via hole is composed of two half holes, one half hole is formed on the second active layer 21, and the other half hole is formed on the On the second connection bar of the power connection line 52, the third insulating layer 63 in the two half holes is etched away, so that the transfer via hole composed of the two half holes exposes the surface of the second active layer 21 and the surface of the second active layer 21 at the same time.
  • the surface of the second connection bar of the power connection line 52 is etched away, so that the transfer via hole composed of the two half holes exposes the surface of the second active layer 21 and the surface of the second active layer 21 at the same time.
  • the third insulating layer 63 in the fourth via hole V4 is etched away, exposing the surface of the second active layer 21 .
  • the third via hole V3 is configured so that the first electrode of the subsequently formed second transistor T2 is connected to the first region of the second active layer 21 and the second connection bar of the power connection line 52 through the via hole at the same time, so as to realize The first pole of the second transistor T2 is connected to the subsequently formed first power line VDD.
  • the fourth via hole V4 is configured to connect the second electrode of the subsequently formed second transistor T2 to the second region of the second active layer 21 through the via hole.
  • the fifth via hole V5 and the sixth via hole V6 may be provided in each sub-pixel, for example, the fifth via hole V5 and the sixth via hole V6 may be provided in The two sides of the third gate electrode 32 of each sub-pixel.
  • the orthographic projection of the fifth via hole V5 on the substrate is within the range of the orthographic projection of the first region of the third active layer 31 in the sub-pixel on the substrate, and the sixth via hole V6 is in the The orthographic projection on is located within the range of the orthographic projection of the second region of the third active layer 31 in the sub-pixel on the substrate.
  • the third insulating layer 63 in the fifth via hole V5 and the sixth via hole V6 is etched away, exposing surfaces at both ends of the third active layer 31 .
  • the fifth via hole V5 is configured to connect the first electrode of the subsequently formed third transistor T3 to the first region of the third active layer 31 through the via hole.
  • the sixth via hole V6 is configured to connect the second electrode of the subsequently formed third transistor T3 to the second region of the third active layer 31 through the via hole.
  • a seventh via hole V7 may be provided in each sub-pixel.
  • the orthographic projection of the seventh via hole V7 on the substrate is within the range of the orthographic projection of the compensation connection line 51 on the substrate.
  • the first insulating layer 61 and the third insulating layer 63 in the seventh via hole V7 are etched away, exposing the surface of the compensation connection line 51 .
  • the seventh via hole V7 is configured to connect the first pole of the subsequently formed third transistor T3 to the compensation connection line 51 through the via hole, so as to be connected to the compensation signal line Sense.
  • any one of the eighth via hole V8 and the ninth via hole V9 may be provided in each sub-pixel.
  • the eighth via hole V8 is located at the space 44 between the second pole plate 42 and the third active layer 31
  • the ninth via hole V9 is located at the position of the opening 45 in the second pole plate 42 .
  • the orthographic projection of the eighth via hole V8 on the base is within the range of the orthographic projection of the first plate 41 on the base, and does not overlap with the orthographic projection of the second plate 42 on the base.
  • the orthographic projection of the ninth via hole V9 on the base is within the range of the orthographic projection of the first plate 41 on the base, and does not overlap with the orthographic projection of the second plate 42 on the base.
  • the first insulating layer 61 and the third insulating layer 63 in the eighth via hole V8 and the ninth via hole V9 are etched away, exposing the surface of the first electrode plate 41 .
  • the eighth via hole V8 is configured to allow the subsequently formed third pole plate 43 to pass through the via hole to connect to the first pole plate 41
  • the ninth via hole V9 is configured to allow the subsequently formed third pole plate 43 to pass through the via hole. It is connected with the first pole plate 41.
  • the eighth via hole V8 may be located in the first sub-pixel P1 and the second sub-pixel P2
  • the ninth via hole V9 may be located in the third sub-pixel P3 and the fourth sub-pixel P4.
  • a plurality of ninth vias V9 are arranged at intervals.
  • the tenth via hole V10 is a transfer via hole, and the transfer via hole may be composed of two half holes, one half hole is formed on the second gate electrode 22, The other half hole is formed on the second electrode plate 42, and the third insulating layer 63 in the two half holes is etched away, so that the transition via formed by the two half holes simultaneously exposes the surface of the second gate electrode 22 and the surface of the second pole plate 42 .
  • the tenth via hole V10 is configured so that the second electrode of the first transistor T1 formed subsequently is connected to the second gate electrode 22 and the second electrode plate 42 through the via hole.
  • the orthographic projection of the eleventh via hole V11 on the substrate is within the range of the orthographic projection of the first connecting strip of the power connection line 52 on the substrate.
  • the third insulating layer 63 in the eleventh via hole V11 is etched away, exposing the surface of the first connection bar of the power connection line 52 .
  • the eleventh via hole V11 is configured to connect the subsequently formed first power line VDD to the power connection line 52 through the via hole.
  • a plurality of eleventh vias V11 are arranged at intervals along the second direction DR2 to increase connection reliability between the first power line VDD and the power connection line 52 .
  • the orthographic projection of the twelfth via hole V12 on the substrate is within the range of the orthographic projection of the auxiliary power line 53 on the substrate.
  • the third insulating layer 63 in the twelfth via hole V12 is etched away, exposing the surface of the auxiliary power line 53 .
  • the twelfth via hole V12 is configured to connect the subsequently formed second power supply line VSS to the auxiliary power supply line 53 through the via hole.
  • a plurality of twelfth vias V12 are arranged at intervals along the second direction DR2 to increase connection reliability between the second power line VSS and the auxiliary power line 53 .
  • the third insulating layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be single layer, multilayer layers or composite layers.
  • the transparent area 200 includes the first insulating layer 61 and the third insulating layer 63 stacked on the substrate 10 .
  • forming the third conductive layer may include: depositing a third conductive film on the substrate forming the aforementioned structure, patterning the third conductive film through a patterning process, and forming a third conductive film on the third insulating layer 63.
  • the third conductive layer pattern For example, the third conductive layer may be called a source-drain metal (SD) layer.
  • SD source-drain metal
  • the third conductive layer may be formed using a metal material.
  • metal materials may include, but are not limited to: any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the metals listed above, such as aluminum Neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), etc.
  • the third conductive layer can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo and the like.
  • the third conductive layer may include: a first power supply line VDD, a second power supply line VSS, a compensation signal line Sense and a compensation signal line formed in each pixel unit.
  • the four data signal lines Data may also include: a first connection electrode 13, a second connection electrode 14, a third connection electrode 23, a fourth connection electrode 24, a fifth connection electrode 33, a sixth connection electrode formed in each sub-pixel
  • the electrode 34 is connected to the third electrode plate 43 .
  • the first power line VDD extends along the second direction DR2 .
  • the first power line VDD is disposed on a side away from the transparent region 200 .
  • the first power line VDD is configured to be connected to the power connection line 52 through a plurality of eleventh vias V11, so that the first power line VDD is respectively connected to the third terminal of each sub-pixel in the pixel unit through the power connection line 52.
  • the electrodes 23 are connected to form a double-layer wiring between the first gate electrode 12 and the third gate electrode 32, which ensures the reliability of power signal transmission and reduces the resistance of the first power line VDD.
  • the double-layer wiring includes a power connection line 52 of the second metal layer and a first power line VDD of the third metal layer.
  • the exemplary embodiment of the present disclosure realizes respectively writing power signals into the second transistors T2 of the four sub-pixels by providing a first power supply line VDD and a power supply connection line 52 .
  • the first power line VDD extends along the second direction DR2
  • the power connection line 52 includes a first connecting bar extending along the second direction DR2 and a second connecting bar extending along the first direction DR1
  • the first power line VDD is connected to the second transistor T2 through the second connection bar.
  • the second power line VSS extends along the second direction DR2 .
  • the second power line VSS is disposed on a side adjacent to the transparent region 200 .
  • the second power supply line VSS is configured to be connected to the auxiliary power supply line 53 through a plurality of twelfth vias V12, forming a double-layer wiring between the first gate electrode 12 and the third gate electrode 32, and the double-layer wiring includes the first The auxiliary power line 53 of the second metal layer and the second power line VSS of the third metal layer. In this way, the reliability of power signal transmission can be ensured, and the resistance of the second power line VSS can be reduced.
  • the width of the first power supply line VDD and the second The width of the power supply line VSS is greater than the width of the compensation signal line Sense, the width of the first power supply line VDD and the width of the second power supply line VSS are both greater than the width of the data signal line Data. In this way, the resistances of the first power supply line VDD and the second power supply line VSS can be reduced.
  • the compensation signal line Sense is arranged between the first power supply line VDD and the second power supply line VSS, for example, the compensation signal line Sense can be arranged at Between the first sub-pixel P1 and the second sub-pixel P2.
  • the main body portion of the compensation signal line Sense extends along the second direction DR2 .
  • a first protrusion for example, the fifth connection electrode 33 located in the second sub-pixel P2
  • the seventh via hole V7 is connected to the compensation connection line 51, so that the compensation signal line Sense is connected to the compensation connection line 51, and the second end of the first protrusion is connected to the second end of the sub-pixel through the fifth via hole V5 in the sub-pixel.
  • the first regions of the three active layers 31 are connected, and the third end of the first protrusion is connected to the compensation signal line Sense.
  • the first protruding portion can serve as the first electrode of the third transistor T3 in the second sub-pixel P2, so as to write the compensation signal provided by the compensation signal line Sense into the third transistor T3 in the second sub-pixel P2.
  • the first protrusion can transmit the compensation signal provided by the compensation signal line Sense to the compensation connection line 51 connected across the four sub-pixels, and since the compensation connection line 51 passes through the other sub-pixels
  • the seventh via hole V7 is connected to the fifth connection electrode 33 in other sub-pixels, so that the compensation connection line 51 can transmit the compensation signal to the third transistor T3 in other sub-pixels, that is, the compensation signal line Sense can pass through the compensation connection line 51
  • the compensation signal is written into the third transistor T3 in other sub-pixels.
  • the compensation signals can be respectively written into the pixel units.
  • the compensation signal line Sense is directly connected to the third transistor T3 in the second sub-pixel P2
  • the compensation signal line Sense is respectively connected to the third transistors T3 in other sub-pixels through compensation connection lines 51 .
  • a compensation signal line is provided in the middle of the pixel region 100 of each pixel unit to provide compensation signals to four sub-pixels, which can ensure that the RC delay of the compensation signal is basically the same before being written into the transistor, thereby ensuring a uniform display sex.
  • a data signal line Data may be provided in each sub-pixel.
  • the body portion of the data signal line D extends along the second direction DR2.
  • a second protruding portion (that is, the first connection electrode 13) may be provided on the data signal line Data, one end of the second protruding portion is connected to the data signal line Data, and the other end of the second protruding portion
  • the first via hole V1 in this sub-pixel is connected to the first region of the first active layer 11, so that the second protruding part can be used as the first pole of the first transistor T1 to realize writing the data signal into the first transistor T1.
  • two data signal lines Data can be arranged between the second power supply line VSS and the compensation signal line Sense, and the other two data signal lines Data It may be arranged between the first power supply line VDD and the compensation signal line Sense.
  • the exemplary embodiment of the present disclosure may implement writing data signals into the first transistors T1 of the four sub-pixels respectively by providing four data signal lines Data whose main parts extend along the second direction DR2.
  • main parts of the first power line VDD, the second power line VSS, the compensation signal line Sense and the data signal line Data may be arranged in parallel.
  • the first connection electrode 13 may be respectively provided in each sub-pixel, and may serve as the first electrode of the first transistor T1 .
  • the first connection electrode 13 and the data signal line Data are connected to each other as an integrated structure, so that each data signal line Data is connected to the first connection electrode 13 of the sub-pixel, wherein the first connection electrode 13 One end is directly connected to the data signal line Data, and the other end of the first connection electrode 13 is connected to the first region of the first active layer 11 through the first via hole V1 in the sub-pixel.
  • the first connection electrodes 13 may be strip structures extending along the first direction DR1.
  • the second connection electrode 14 can be respectively arranged on each sub-pixel, and can be used as the second electrode of the first transistor T1.
  • the second connection One end of the electrode 14 is connected to the second region of the first active layer 11 through the second via hole V2, and the other end of the second connection electrode 14 is connected to the second gate electrode 22 and the second electrode plate 42 through the tenth via hole V10 at the same time.
  • the second connection electrode 14 , the second gate electrode 22 and the second electrode plate 42 can have the same potential.
  • the second connection electrode 14 may be a strip structure extending along the second direction DR2.
  • the third connection electrode 23 may be respectively provided in each sub-pixel, and may serve as the first electrode of the second transistor T2.
  • the third connection electrode 23 is simultaneously connected to the second connection bar of the power supply connection line 52 and the first region of the second active layer 21 through the third via hole V3.
  • a power line VDD is connected, therefore, the third connection electrode 23 can be connected to the first power line VDD, and the third connection electrode 23 can write a power signal into the second transistor T2.
  • the third connection electrode 23 may be in a bar shape extending along the second direction DR2.
  • the fourth connection electrode 24 may be respectively provided in each sub-pixel, and may serve as the second electrode of the second transistor T2 .
  • the fourth connection electrode 24 is connected to the second region of the second active layer 21 through the fourth via hole V4.
  • the fifth connection electrode 33 may be respectively provided in each sub-pixel, and may serve as the first electrode of the third transistor T3.
  • the first end of the fifth connection electrode 33 in the second sub-pixel P2 is connected to the compensation connection line 51 through the seventh via hole V7 in this sub-pixel, so that the compensation signal line Sense is connected to the compensation connection line 51, and the second sub-pixel
  • the second end of the fifth connection electrode 33 in the pixel P2 is connected to the first region of the third active layer 31 in the sub-pixel through the fifth via hole V5 in the sub-pixel, and the fifth connection in the second sub-pixel P2
  • the third end of the electrode 33 is connected to the compensation signal line Sense.
  • the fifth connection electrode 33 in the second sub-pixel P2 can be used as the first electrode of the third transistor T3 in the second sub-pixel P2, realizing the connection of the compensation signal line
  • the compensation signal provided by Sense is written into the third transistor T3 located in the second sub-pixel P2 and transmitted to the compensation connection line 51 across the four sub-pixels.
  • the fifth connection electrode 33 in other sub-pixels (such as the first sub-pixel P1, the third sub-pixel P3 and the fourth sub-pixel P4) connects with the third active electrode 33 in this sub-pixel through the fifth via hole V5 in this sub-pixel.
  • the first region of the layer 31 is connected, and at the same time, it is connected to the compensation connection line 51 through the seventh via hole V7 in this sub-pixel.
  • the compensation connection line 51 is connected to the compensation signal line Sense, it can realize the second in other sub-pixels.
  • the connection between the five-connection electrode 33 and the compensation signal line Sense can realize that the compensation connection line 51 transmits the compensation signal to the third transistor T3 in other sub-pixels.
  • the sixth connection electrode 34 may be respectively provided in each sub-pixel, and may serve as the second electrode of the third transistor T3 .
  • the sixth connection electrode 34 is connected to the second region of the third active layer 31 through the sixth via hole V6.
  • the orthographic projection of the third pole plate 43 on the base 10 overlaps with the orthographic projection of the second pole plate 42 on the base 10 , and the third pole plate 43
  • the second storage capacitor Cst2 is formed with the second plate 42 .
  • the fourth connection electrode 24 , the sixth connection electrode 34 and the third electrode plate 43 may be an integral structure connected to each other.
  • the third electrode plate 43 passes through the first One of the eight via holes V8 and the ninth via hole V9 is connected to the first pole plate 41, therefore, the fourth connection electrode 24 is connected to the first pole plate 41 and the third pole plate 43 at the same time, and the sixth connection electrode 34 is simultaneously connected to the first pole plate 41 and the third pole plate 43. Connecting with the first pole plate 41 and the third pole plate 43 can realize that the fourth connection electrode 24 , the sixth connection electrode 34 , the first pole plate 41 and the third pole plate 43 have the same potential.
  • the fifth connection electrode 33, the sixth connection electrode 34, and the third electrode plate 43 are mirror-symmetrical with respect to the vertical axis (for example, the compensation signal line Sense), and the third sub-pixel P3 is connected to the first connection in the fourth sub-pixel P4.
  • the electrode 13, the second connection electrode 14, the third connection electrode 23, the fourth connection electrode 24, the fifth connection electrode 33, the sixth connection electrode 34 and the third electrode plate 43 are relative to the vertical axis (for example, the compensation signal line Sense) Mirror symmetry.
  • the third conductive layer pattern is formed in the pixel region 100 , and the transparent region 200 includes the first insulating layer 61 and the third insulating layer 63 stacked on the substrate 10 .
  • a fourth insulating film and a fifth insulating film are deposited on the substrate forming the foregoing structure, and the fourth insulating film and the fifth insulating film are patterned by a patterning process to form a first insulating film covering the foregoing structure.
  • a passivation (PVX) layer disposed on the fourth insulating layer 64 .
  • the fifth insulating layer may be called a planar (PLN) layer or a resin (Resin) layer.
  • multiple via holes are opened on the fourth insulating layer 64 and the fifth insulating layer 65 , and the multiple via holes may include: a thirteenth via hole located in the pixel region 100 The via hole V13 and the fourteenth via hole V14.
  • any one of the thirteenth via hole V13 and the fourteenth via hole V14 may be provided in each sub-pixel.
  • the thirteenth via hole V13 is located at the position of the gap 44 between the second plate 42 and the third active layer 31 .
  • the fourteenth via hole V14 is located at the position of the opening 45 in the second electrode plate 42 .
  • the orthographic projection of the thirteenth via hole V13 on the substrate is within the range of the orthographic projection of the third plate 43 on the substrate, and is in line with the second plate 43
  • the orthographic projections of 42 on the base do not overlap.
  • the orthographic projection of the fourteenth via hole V14 on the base is within the range of the orthographic projection of the third plate 43 on the base, and does not overlap with the orthographic projection of the second plate 42 on the base.
  • the fourth insulating layer 64 and the fifth insulating layer 65 in the thirteenth via hole V13 and the fourteenth via hole V14 are etched away, exposing the surface of the third plate 43 .
  • the thirteenth via hole V13 and the fourteenth via hole V14 are configured to connect the subsequently formed first anode layer 701 to the third electrode plate 43 through the via holes.
  • the connection between the plate 41, the fourth connection electrode 24 and the sixth connection electrode 34 can realize the connection between the first anode layer 701 and the first electrode plate 41, the second transistor T2 and the third transistor T3.
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may use silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON) Any one or more of them can be single layer, multilayer or composite layer.
  • the fifth insulating layer may be made of organic materials, such as resin (Resin) and the like.
  • the transparent region 200 includes a first insulating layer 61 , a third insulating layer 63 and a fourth insulating layer 64 stacked on the substrate 10 .
  • a fourth conductive film is deposited on the substrate on which the aforementioned structure is formed, and the fourth conductive film is patterned by a patterning process to form a pattern of the fourth conductive layer.
  • the fourth conductive layer may be formed using a transparent conductive material.
  • the fourth conductive layer may be formed using indium tin oxide (ITO) or indium zinc oxide (IZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the fourth conductive layer may be called an ITO1 layer.
  • the fourth conductive layer may include: a first anode layer 701 located in each pixel unit.
  • the first anode layer 701 in each pixel unit may include: a first anode 701R, a second anode 701G, a third anode 701B and a fourth anode 701W.
  • the first anode 701R, the second anode 701G and the third anode 701B are formed in the pixel region 100 .
  • the fourth anode 701W is formed in the pixel area 100 in the current pixel unit and the transparent area 200 in the adjacent pixel unit.
  • the first anode 701R may serve as the first anode layer of the first subpixel P1 and be disposed in the first subregion 101 - 1 in the pixel region 100 .
  • the first anode 701R is configured to be connected to the third plate 43 through the thirteenth via hole V13 in the first sub-pixel P1, thus, since the third plate 43 in the first sub-pixel P1, the second transistor
  • the second pole of T2 and the second pole of the third transistor T3 are an integral structure connected to each other, therefore, the first anode 701R and the storage capacitor C, the second pole of the second transistor T2, and the second pole of the third transistor T3 can be realized. pole connection.
  • the second anode 701G may serve as the first anode layer of the second subpixel P2 and be disposed in the second subregion 101 - 2 in the pixel region 100 .
  • the second anode 701G is configured to be connected to the third plate 43 through the thirteenth via V13 in the second sub-pixel P2, thus, since the third plate 43 in the second sub-pixel P2, the second transistor
  • the second pole of T2 and the second pole of the third transistor T3 are an integral structure connected to each other, therefore, the second anode 701G and the storage capacitor C, the second pole of the second transistor T2, and the second pole of the third transistor T3 can be realized. pole connection.
  • the third anode 701B may serve as the first anode layer of the third subpixel P3 and be disposed in the third subregion 102 - 1 in the pixel region 100 .
  • the third anode 701B is configured to be connected to the third plate 43 through the fourteenth via hole V14 in the third sub-pixel P3, thus, since the third plate 43 in the third sub-pixel P3, the second transistor
  • the second pole of T2 and the second pole of the third transistor T3 are an integrated structure connected to each other. Therefore, the third anode 701B and the storage capacitor C, the second pole of the second transistor T2, and the second pole of the third transistor T3 can be realized. pole connection.
  • the fourth anode 701W may include: a main body portion located in the pixel area 100 and an extension portion located in the transparent area 200, which may serve as the fourth sub-pixel P4 (ie The first anode layer of the white sub-pixel).
  • the fourth anode 701W is configured to be connected to the third plate 43 through the fourteenth via hole V14 in the fourth sub-pixel P4, thus, since the third plate 43 in the fourth sub-pixel P4, the second transistor
  • the second pole of T2 and the second pole of the third transistor T3 are an integral structure connected to each other, therefore, the fourth anode 701W and the storage capacitor C, the second pole of the second transistor T2, and the second pole of the third transistor T3 can be realized. pole connection.
  • the main body portion and the extension portion may be located in two adjacent pixel units.
  • the main body part is located in the fourth sub-region 102-2 in the first pixel unit
  • the extension part is located in the first transparent sub-region in the second pixel unit 201.
  • the white sub-pixel area in the first pixel unit can be extended to the transparent area in the second pixel unit, which can increase the aperture ratio.
  • the first anode 701R, the second anode 701G and the third anode 701B may be rectangular.
  • the shape of the fourth anode 701W may be "L”.
  • the transparent region 200 includes: the first insulating layer 61, the third insulating layer 63 and the fourth insulating layer 64 stacked on the substrate 10, and the fourth sub-pixel P4 (that is, the white sub-pixel).
  • An extension in the anode layer is: the first insulating layer 61, the third insulating layer 63 and the fourth insulating layer 64 stacked on the substrate 10, and the fourth sub-pixel P4 (that is, the white sub-pixel).
  • a fifth conductive film is deposited on the substrate forming the foregoing structure, and the fifth conductive film is patterned by a patterning process to form a pattern of the fifth conductive layer.
  • the fifth conductive layer may be formed using a metal material, or may be formed using a metal material and a transparent conductive material.
  • the metal material may include, but is not limited to: any one or more of silver (Ag), aluminum (Al) and molybdenum (Mo).
  • the transparent conductive material may include, but is not limited to, indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the fifth conductive layer may be a single-layer structure, or a multi-layer composite structure.
  • the fifth conductive layer may be a laminated structure (eg, Al/ITO) formed of aluminum (Al) and indium tin oxide (ITO), or may be formed of molybdenum (Mo) and indium tin oxide (ITO) A set stacked structure (such as Mo/ITO) etc. is formed, so that the formed second anode layer has good electrical conductivity.
  • the fifth conductive layer may be called an ITO2 layer.
  • the embodiments of the present disclosure do not limit this.
  • the fifth conductive layer may include: a second anode layer 702 located in each pixel unit.
  • the second anode layer 702 in each pixel unit may include: a fifth anode 702R, a sixth anode 702G, a seventh anode 702B, and an eighth anode 702W located in the pixel region 100 .
  • the orthographic projection of the fifth anode 702R on the substrate overlaps with the orthographic projection of the first anode 701R on the substrate, and the fifth anode 702R is connected to the first anode 701R.
  • the orthographic projection of the sixth anode 702G on the substrate overlaps with the orthographic projection of the second anode 701G on the substrate, and the sixth anode 702G is connected to the second anode 701G.
  • the orthographic projection of the seventh anode 702B on the substrate overlaps with the orthographic projection of the third anode 701B on the substrate, and the seventh anode 702B is connected to the third anode 701B.
  • the orthographic projection of the eighth anode 702W on the substrate overlaps the orthographic projection of the main body of the fourth anode 701W on the substrate, and the eighth anode 702W is connected to the main body of the fourth anode 701W.
  • the shapes of the fifth anode 702R, the sixth anode 702G, the seventh anode 702B, and the eighth anode 702W may be rectangular.
  • An opening is provided on the fifth anode 702R.
  • the transparent region 200 includes: the first insulating layer 61, the third insulating layer 63 and the fourth insulating layer 64 stacked on the substrate 10, and the fourth sub-pixel P4 (that is, the white sub-pixel).
  • An extension in the anode layer is: the first insulating layer 61, the third insulating layer 63 and the fourth insulating layer 64 stacked on the substrate 10, and the fourth sub-pixel P4 (that is, the white sub-pixel).
  • forming the pixel definition layer may include: as shown in FIG. 17A and FIG. 17B , coating a pixel definition film on the substrate forming the aforementioned structure, patterning the pixel definition film by a patterning process, A pixel definition layer 71 is formed.
  • the pixel definition layer 71 may at least include: a pixel opening located in each sub-pixel.
  • the pixel definition layer 71 may include: a first pixel opening 71R in the first sub-pixel P1 exposing the fifth anode 702R; a first pixel opening 71R in the second sub-pixel P2 exposing the The second pixel opening 71G that exposes the sixth anode 702G, the third pixel opening 71B that exposes the seventh anode 702B in the third subpixel P3, and the eighth anode 702W and the fourth anode that are exposed in the fourth subpixel P4 The fourth pixel opening 71W of 701W.
  • the shapes and areas of the pixel openings of different sub-pixels may be different.
  • Exemplary embodiments of the present disclosure can adapt to the transmittance of different sub-pixels by designing the four sub-pixels with different aperture ratios, so that the light-emitting devices of the four sub-pixels can emit the same brightness at different currents, and maximize the optimization of the four sub-pixels.
  • the lifespan of the pixel light-emitting device ensures the lifespan of the product.
  • the pixel definition layer may be made of materials such as polyimide (PI), acrylic or polyethylene terephthalate (PET).
  • PI polyimide
  • PET polyethylene terephthalate
  • the embodiments of the present disclosure do not limit this.
  • the preparation process of the display substrate may further include: forming an organic light-emitting layer, the organic light-emitting layer is connected to the second anode layer through the pixel opening; forming a cathode on the organic light-emitting layer , the cathode is connected to the organic light-emitting layer.
  • the organic light-emitting layer can be formed by evaporation or inkjet printing.
  • the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (Fine Metal Mask, FMM), or by vapor deposition using an open mask (Open Mask).
  • FMM fine metal mask
  • Open Mask open mask
  • the cathode may be a common electrode, that is, multiple light emitting devices may share an entire cathode.
  • the cathode can use any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or use one of the above metals Any one or more alloys made.
  • the manufacturing process of the display substrate may further include: forming an encapsulation layer on the basis of forming the aforementioned pattern, and the encapsulation layer is formed in the pixel area 100 and the transparent area 200 .
  • the encapsulation layer of the pixel area 100 includes a first encapsulation layer of inorganic material, a second encapsulation layer of organic material and a third encapsulation layer of inorganic material, the first encapsulation layer is disposed on the cathode, and the second encapsulation layer is disposed on the first encapsulation layer Above, the third encapsulation layer is disposed on the second encapsulation layer to form a laminated structure of inorganic material/organic material/inorganic material.
  • the encapsulation layer of the transparent area 200 includes a first encapsulation layer of inorganic material and a third encapsulation layer of inorganic material, the first encapsulation layer is disposed on the cathode, and the third encapsulation layer is disposed on the first encapsulation layer, forming an inorganic material/inorganic material layered structure.
  • the display substrate provided by the embodiment of the present disclosure may include:
  • a first conductive layer disposed on the substrate 10 may include a first plate 41 and a compensation connection line 51;
  • the semiconductor layer arranged on the first insulating layer 61, the semiconductor layer can include the first active layer 11, the second active layer 21, the third active layer 31 and the second pole plate 42, the second pole plate 42 is on the base
  • the orthographic projection on 10 and the orthographic projection of the first pole plate 41 on the substrate 10 have overlapping regions, and the second pole plate 42 and the first pole plate 41 form the first storage capacitor Cst1;
  • the second conductive layer disposed on the second insulating layer 62, the second conductive layer may include: the first scanning signal line G1, the second scanning signal line G2, the power connection line 52 and the auxiliary power line 53, the first gate electrode 12 , the second gate electrode 22 and the third gate electrode 32, the first gate electrode 12 and the first scanning signal line G1 are an integral structure connected to each other, and the third gate electrode 32 and the second scanning signal line G2 are an integral structure connected to each other ;
  • the third conductive layer disposed on the third insulating layer 63, the third conductive layer may include: a first power line VDD, a second power line VSS, a compensation signal line Sense, a data signal line Data, a first connection electrode 13, a second power line
  • the second connection electrode 14, the third connection electrode 23, the fourth connection electrode 24, the fifth connection electrode 33, the sixth connection electrode 34 and the third electrode plate 43, the first connection electrode 13 and the data signal line Data are connected as a whole structure
  • the fourth connection electrode 24, the sixth connection electrode 34 and the third pole plate 43 are an integral structure connected to each other, and the orthographic projection of the third pole plate 43 on the substrate 10 is the same as the orthographic projection of the second pole plate 42 on the substrate 10.
  • the second pole plate 42 and the third pole plate 43 form a second storage capacitor Cst2;
  • the fourth insulating layer 64 and the fifth insulating layer 65 covering the third conductive layer, the fourth insulating layer 64 and the fifth insulating layer 65 have a plurality of via holes;
  • the fourth conductive layer disposed on the fourth insulating layer 64 and the fifth insulating layer 65, the fourth conductive layer may include a first anode layer 701, and the first anode layer 701 may include: a first anode 701R located in the pixel region 100 , the second anode 701G, the third anode 701B, and the fourth anode 701W located in the pixel area 100 and the transparent area 200 (ie, the first anode layer of the white sub-pixel);
  • the fifth conductive layer disposed on the fourth conductive layer, the fifth conductive layer may include: the second anode layer 702, the second anode layer 702 may include: the fifth anode 702R, the sixth anode 702G and the The seventh anode 702B and the eighth anode 702W;
  • a pixel definition layer 71 disposed on the fifth insulating layer 65, the pixel definition layer 71 has a pixel opening exposing the second anode layer 702;
  • an organic light-emitting layer disposed in the pixel opening, and the organic light-emitting layer is connected to the second anode layer 702;
  • the first transparent sub-region 201 in the transparent region 200 of the pixel unit may include: The substrate 10 and the first insulating layer 61 , the third insulating layer 63 , the fourth insulating layer 64 and the first anode layer 701 stacked on the substrate 10 in sequence.
  • the second transparent sub-region 202 in the transparent region 200 of the pixel unit may include: the substrate 10 and the first insulating layer 61 , the third insulating layer 63 and the fourth insulating layer 64 sequentially stacked on the substrate 10 .
  • the display substrate provided by the exemplary embodiments of the present disclosure can increase the aperture ratio by setting the design that the first anode layer of the white sub-pixel in this pixel unit expands to the transparent area in the adjacent pixel unit. .
  • FIG. 8A to 8I are schematic diagrams of the preparation process of the display substrate shown in FIG. 4, illustrating the layout structure of a pixel unit of the display substrate, and FIG. 8J is a cross-sectional view of the display substrate shown in FIG. 8I along the direction A-A'.
  • FIG. 8A to FIG. 8J the preparation process of the display substrate provided in the exemplary embodiment of the present disclosure will be described.
  • each pixel unit includes a pixel area 100 and a transparent area 200, each pixel unit includes a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3 and a fourth sub-pixel P4 , the pixel driving circuit of each sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor C.
  • the pixel driving circuits of the fourth sub-pixel P4 , the first sub-pixel P1 , the second sub-pixel P2 and the third sub-pixel P3 are sequentially arranged along the first direction DR1 .
  • the preparation process of the display substrate may include the following steps:
  • the first conductive layer may include: a first electrode plate 41 and compensation connection lines 51 spanning four sub-pixels.
  • the first plate 41 of the fourth sub-pixel P4 the first plate 41 of the first sub-pixel P1, the first plate 41 of the second sub-pixel P2, the first plate 41 of the third sub-pixel P3
  • the first pole plates 41 are arranged in sequence along the first direction DR1.
  • the semiconductor layer may include: a first active layer 11 , a second active layer 21 , a third active layer 31 and a second plate 42 for each sub-pixel.
  • the semiconductor layer pattern in the fourth sub-pixel P4 is symmetrical to the semiconductor layer pattern in the third sub-pixel P3 with respect to the vertical axis
  • the semiconductor layer pattern in the first sub-pixel P1 is symmetrical to the semiconductor layer pattern in the second sub-pixel P2.
  • a space 44 is provided between the second plate 42 of the first sub-pixel P1 and the second sub-pixel P2 and the third active layer 31, and the second plate of the third sub-pixel P3 and the fourth sub-pixel P4 Opening 45 is provided in 42 .
  • the second conductive layer may include: the first scanning signal line G1, the second scanning signal line G2, the power supply connection line 52 and the auxiliary power supply line 53, and the first gate electrode 12 of each sub-pixel , the second gate electrode 22 and the third gate electrode 32 .
  • the first gate electrode 12, the second gate electrode 22 and the third gate electrode 32 in the third sub-pixel P3 and the fourth sub-pixel P4 are mirror-symmetrical with respect to the vertical axis
  • the first gate electrode 12, the second gate electrode 22 and the third gate electrode 32 are mirror-symmetrical with respect to the vertical axis.
  • a plurality of via holes are provided on the third insulating layer 63, and the plurality of via holes may include: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, the fifth via V5, the sixth via V6, the seventh via V7, the eighth via V8, the ninth via V9, the tenth via V10, the eleventh via V11 and the twelfth via V12.
  • the eighth via hole V8 may be located in the first sub-pixel P1 and the second sub-pixel P2, and the ninth via hole V9 may be located in the third sub-pixel P3 and the fourth sub-pixel P4.
  • the third conductive layer may include: a first power supply line VDD, a second power supply line VSS, a compensation signal line Sense and four data signal lines Data formed in each pixel unit, and may also include : the first connection electrode 13, the second connection electrode 14, the third connection electrode 23, the fourth connection electrode 24, the fifth connection electrode 33, the sixth connection electrode 34 and the third electrode plate 43 formed in each sub-pixel .
  • the compensation signal line Sense may be disposed between the first sub-pixel P1 and the second sub-pixel P2.
  • the first end of the fifth connection electrode 33 in the second sub-pixel P2 is connected to the compensation connection line 51 through the seventh via hole V7 in this sub-pixel, so that the compensation signal line Sense is connected to the compensation connection line 51, and the second sub-pixel
  • the second end of the fifth connection electrode 33 in the pixel P2 is connected to the first region of the third active layer 31 in the sub-pixel through the fifth via hole V5 in the sub-pixel, and the fifth connection in the second sub-pixel P2
  • the third end of the electrode 33 is connected to the compensation signal line Sense.
  • the three-electrode plate 43 is mirror-symmetrical with respect to the vertical axis (for example, the compensation signal line Sense), and the first connection electrode 13, the second connection electrode 14, the third connection electrode 23,
  • the fourth connection electrode 24 , the fifth connection electrode 33 , the sixth connection electrode 34 and the third electrode plate 43 are mirror-symmetrical with respect to the vertical axis (for example, the compensation signal line Sense).
  • the third conductive layer may include: a plurality of via holes opened on the fourth insulating layer 64 and the fifth insulating layer 65 , and the plurality of via holes may include: a thirteenth via hole located in the pixel region 100 The via hole V13 and the fourteenth via hole V14.
  • the thirteenth via hole V13 is located at the position of the gap 44 between the second plate 42 and the third active layer 31 .
  • the fourteenth via hole V14 is located at the position of the opening 45 in the second plate 42 .
  • the fourth conductive layer may include: a first anode layer 701 located in each pixel unit.
  • the first anode layer 701 in each pixel unit may include: a first anode 701R, a second anode 701G, a third anode 701B and a fourth anode 701W.
  • each of the first anode 701R, the second anode 701G and the third anode 701B is formed in the pixel region 100 .
  • the fourth anode 701W includes: a main body formed in the pixel region 100 and an extension part formed in the transparent region 200 of the pixel unit.
  • the first anode 701R and the second anode 701G are sequentially arranged along the first direction DR1
  • the main body of the fourth anode 701W and the third anode 701B are arranged sequentially along the first direction DR1
  • the fourth anode 701W The main body part is located on the second direction DR2 side of the first anode 701R
  • the third anode 701B is located on the second direction DR2 side of the second anode 701G.
  • the fifth conductive layer may include: a second anode layer 702 located in each pixel unit.
  • the second anode layer 702 in each pixel unit may include: a fifth anode 702R, a sixth anode 702G, a seventh anode 702B, and an eighth anode 702W located in the pixel region 100 .
  • the fifth anode 702R and the sixth anode 702G are arranged in sequence along the first direction DR1
  • the eighth anode 702W and the seventh anode 702B are arranged in sequence along the first direction DR1
  • the eighth anode 702W is located at the fifth anode
  • the seventh anode 702B is located on the second direction DR2 side of the sixth anode 702G.
  • the pixel definition layer 71 may include: a first pixel opening 71R in the first sub-pixel P1 exposing the fifth anode 702R, a second pixel in the second sub-pixel P2 exposing the sixth anode 702G The opening 71G, the third pixel opening 71B in the third sub-pixel P3 exposing the seventh anode 702B, and the fourth pixel opening 71W in the fourth sub-pixel P4 exposing the eighth anode 702W and the fourth anode 701W.
  • the first transparent sub-region 201 in the transparent region 200 of the pixel unit may include: The base 10 and the first insulating layer 61 , the third insulating layer 63 and the fourth insulating layer 64 stacked on the base 10 in sequence.
  • the second transparent sub-region 202 in the transparent region 200 of the pixel unit may include: the substrate 10 and the first insulating layer 61 , the third insulating layer 63 , the fourth insulating layer 64 and the first anode layer sequentially stacked on the substrate 10 701. In this way, the first anode layer of the white sub-pixel in the pixel unit is extended to the second transparent sub-region 202 in the pixel unit.
  • the display substrate provided by the exemplary embodiments of the present disclosure can be designed without reducing On the premise of the area of the transparent area, the pixel area can be increased to increase the pixel aperture ratio to a certain extent, thereby improving the display effect. Moreover, since the first anode layer is formed of a transparent conductive material, the display effect can be improved without affecting the transparency effect.
  • FIGS. 9A to 9I are schematic diagrams of the preparation process of the display substrate shown in FIG. 5 , illustrating the layout structure of a pixel unit of the display substrate.
  • FIG. 9J is a cross-sectional view of the display substrate shown in FIG. 9I along the direction A-A'. Referring to the structure of the display substrate shown in FIG. 5 , and referring to FIGS. 9A to 9J , the preparation process of the display substrate provided in the exemplary embodiment of the present disclosure will be described. Wherein, in FIGS.
  • each pixel unit may include: a transparent region 200 and a pixel region 100 sequentially arranged along the first direction DR1, and each pixel unit includes: a first sub-pixel P1, a second sub-pixel P2,
  • the pixel driving circuit of each sub-pixel includes: a first transistor T1 , a second transistor T2 , a third transistor T3 and a storage capacitor C.
  • the pixel driving circuits of the first sub-pixel P1 , the second sub-pixel P2 , the third sub-pixel P3 and the fourth sub-pixel P4 are sequentially arranged along the first direction DR1 .
  • the preparation process of the display substrate may include the following steps:
  • the first conductive layer may include: a first plate 41 located in the pixel region 100 and a compensation connection line 51 spanning four sub-pixels.
  • the first electrode plate 41 of the first sub-pixel P1 the first electrode plate 41 of the second sub-pixel P2, the first electrode plate 41 of the third sub-pixel P3, and the first electrode plate 41 of the fourth sub-pixel P4
  • the first pole plates 41 are arranged in sequence along the first direction DR1.
  • the semiconductor layer may include: the first active layer 11, the second active layer 21, the third active layer 31 and the second plate 42 of each sub-pixel located in the pixel region 100 .
  • the first active layer 11 , the second active layer 21 and the third active layer 31 in the second sub-pixel P2 and the third sub-pixel P3 are symmetrical with respect to the vertical axis.
  • the first active layer 11 and the second active layer 21 in the first sub-pixel P1 and the fourth sub-pixel P4 are symmetrical with respect to the vertical axis.
  • a gap 44 is provided between the second plate 42 in the first sub-pixel P1 and the third active layer 31, the second plates of the second sub-pixel P2, the third sub-pixel P3 and the fourth sub-pixel P4 Opening 45 is provided in 42 .
  • the second conductive layer may include: the first scanning signal line G1, the second scanning signal line G2, the power supply connection line 52 and the auxiliary power supply line 53, and the first gate electrode 12 of each sub-pixel. , the second gate electrode 22 and the third gate electrode 32 .
  • the first gate electrode 12, the second gate electrode 22 and the third gate electrode 32 in the first sub-pixel P1 and the fourth sub-pixel P4 are mirror-symmetrical with respect to the vertical axis
  • the second sub-pixel P2 and the third sub-pixel P3 The first gate electrode 12, the second gate electrode 22 and the third gate electrode 32 are mirror-symmetrical with respect to the vertical axis.
  • multiple via holes are provided on the third insulating layer 63 , and the multiple via holes may include: a first via hole V1 located in the pixel region 100 , a second via hole V2 , and a third via hole.
  • the eighth via hole V8 may be located in the first sub-pixel P1
  • the ninth via hole V9 may be located in the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4.
  • the third conductive layer may include: a first power supply line VDD, a second power supply line VSS, a compensation signal line Sense and four data signal lines Data formed in each pixel unit, and may also include : the first connection electrode 13, the second connection electrode 14, the third connection electrode 23, the fourth connection electrode 24, the fifth connection electrode 33, the sixth connection electrode 34 and the first connection electrode 34 located in each sub-pixel in the pixel area 100 Triode 43.
  • the compensation signal line Sense may be disposed between the second sub-pixel P2 and the third sub-pixel P3.
  • the first end of the fifth connection electrode 33 in the third sub-pixel P3 is connected to the compensation connection line 51 through the seventh via hole V7 in this sub-pixel, so that the compensation signal line Sense is connected to the compensation connection line 51, and the third sub-pixel
  • the second end of the fifth connection electrode 33 in the pixel P3 is connected to the first region of the third active layer 31 in the sub-pixel through the fifth via hole V5 in the sub-pixel, and the fifth connection in the third sub-pixel P3
  • the third end of the electrode 33 is connected to the compensation signal line Sense.
  • the three-electrode plate 43 is mirror-symmetrical with respect to the vertical axis (for example, the compensation signal line Sense), and the first connection electrode 13, the second connection electrode 14, the third connection electrode 23,
  • the fourth connection electrode 24 , the fifth connection electrode 33 , the sixth connection electrode 34 and the third electrode plate 43 are mirror-symmetrical with respect to the vertical axis (for example, the compensation signal line Sense).
  • the third conductive layer may include: a plurality of via holes opened on the fourth insulating layer 64 and the fifth insulating layer 65 , and the plurality of via holes may include: a thirteenth conductive layer located in the pixel region 100 The via hole V13 and the fourteenth via hole V14.
  • the thirteenth via hole V13 is located at the position of the gap 44 between the second plate 42 and the third active layer 31 .
  • the fourteenth via hole V14 is located at the position of the opening 45 in the second electrode plate 42 .
  • the fourth conductive layer may include: a first anode layer 701 located in each pixel unit.
  • the first anode layer 701 in each pixel unit may include: a first anode 701R, a second anode 701G, a third anode 701B and a fourth anode 701W.
  • the first anode 701R, the second anode 701G and the third anode 701B are all formed in the pixel region 100 .
  • the fourth anode 701W includes: a main body formed in the pixel region 100 of the pixel unit and an extension part formed in the transparent region 200 of the pixel unit.
  • the main bodies of the first anode 701R, the second anode 701G, the third anode 701B, and the fourth anode 701W are sequentially arranged along the second direction DR2 .
  • the extension portion of the fourth anode 701W is located on the side opposite to the first direction DR1 of the first anode 701R, the second anode 701G, and the third anode 701B. In this way, the white sub-pixel area in the pixel unit can be extended to the transparent area in the pixel unit, which can increase the aperture ratio without affecting the transparency.
  • the fifth conductive layer may include: a second anode layer 702 located in each pixel unit.
  • the second anode layer 702 in each pixel unit may include: a fifth anode 702R, a sixth anode 702G, a seventh anode 702B, and an eighth anode 702W located in the pixel region 100 .
  • the fifth anode 702R, the sixth anode 702G, the seventh anode 702B, and the eighth anode 702W are sequentially arranged along the second direction DR2 .
  • the pixel definition layer 71 may include: a first pixel opening 71R in the first sub-pixel P1 exposing the fifth anode 702R, a second pixel in the second sub-pixel P2 exposing the sixth anode 702G The opening 71G, the third pixel opening 71B in the third sub-pixel P3 exposing the seventh anode 702B, and the fourth pixel opening 71W in the fourth sub-pixel P4 exposing the eighth anode 702W and the fourth anode 701W.
  • the first pixel opening 71R, the second pixel opening 71G, and the third pixel opening 71B are sequentially arranged along the second direction DR2 .
  • the first transparent sub-region 201 in the transparent region 200 of the pixel unit may include: The base 10 and the first insulating layer 61 , the third insulating layer 63 and the fourth insulating layer 64 stacked on the base 10 in sequence.
  • the second transparent sub-region 202 in the transparent region 200 of the pixel unit may include: the substrate 10 and the first insulating layer 61 , the third insulating layer 63 , the fourth insulating layer 64 and the first anode layer sequentially stacked on the substrate 10 701. In this way, the first anode layer of the white sub-pixel in the pixel unit is extended to the second transparent sub-region 202 in the pixel unit.
  • the display substrate provided by the exemplary embodiments of the present disclosure can be designed without reducing On the premise of the area of the transparent area, the pixel area can be increased to increase the pixel aperture ratio to a certain extent, thereby improving the display effect. Moreover, since the first anode layer is formed of a transparent conductive material, the display effect can be improved without affecting the transparency effect.
  • FIG. 10A to 10I are schematic diagrams of the preparation process of the display substrate shown in FIG. 6 , illustrating the layout structure of two pixel units of the display substrate, and FIG. 10J is a cross-sectional view of the display substrate shown in FIG. 10I along the AA' direction .
  • FIG. 10A to FIG. 10J the preparation process of the display substrate provided in the exemplary embodiment of the present disclosure will be described.
  • each pixel unit includes a pixel area 100 and a transparent area 200, each pixel unit includes a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3 and a fourth sub-pixel P4 , the pixel driving circuit of each sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor C.
  • the pixel driving circuits of the first sub-pixel P1 , the second sub-pixel P2 , the third sub-pixel P3 and the fourth sub-pixel P4 are sequentially arranged along the first direction DR1 .
  • the preparation process of the display substrate may include the following steps:
  • the first conductive layer may include: a first plate 41 located in the pixel region 100 and a compensation connection line 51 spanning four sub-pixels.
  • the first electrode plate 41 of the first sub-pixel P1 the first electrode plate 41 of the second sub-pixel P2, the first electrode plate 41 of the third sub-pixel P3, and the first electrode plate 41 of the fourth sub-pixel P4
  • the first pole plates 41 are arranged in sequence along the first direction DR1.
  • the semiconductor layer may include: the first active layer 11, the second active layer 21, the third active layer 31 and the second plate 42 of each sub-pixel located in the pixel region 100 .
  • the first active layer 11 , the second active layer 21 and the third active layer 31 in the second sub-pixel P2 and the third sub-pixel P3 are symmetrical with respect to the vertical axis.
  • the first active layer 11 and the second active layer 21 in the first sub-pixel P1 and the fourth sub-pixel P4 are symmetrical with respect to the vertical axis.
  • a gap 44 is provided between the second plate 42 in the first sub-pixel P1 and the third active layer 31, the second plates of the second sub-pixel P2, the third sub-pixel P3 and the fourth sub-pixel P4 Opening 45 is provided in 42 .
  • the second conductive layer may include: the first scanning signal line G1, the second scanning signal line G2, the power connection line 52 and the auxiliary power supply line 53, and the first gate electrode 12 of each sub-pixel. , the second gate electrode 22 and the third gate electrode 32 .
  • the first gate electrode 12, the second gate electrode 22 and the third gate electrode 32 in the first sub-pixel P1 and the fourth sub-pixel P4 are mirror-symmetrical with respect to the vertical axis
  • the first gate electrode 12, the second gate electrode 22 and the third gate electrode 32 are mirror-symmetrical with respect to the vertical axis.
  • a plurality of via holes are provided on the third insulating layer 63 , and the plurality of via holes may include: a first via hole V1 located in the pixel region 100 , a second via hole V2 , a third via hole V3, the fourth via V4, the fifth via V5, the sixth via V6, the seventh via V7, the eighth via V8, the ninth via V9, the tenth via V10, the eleventh via V11 and the twelfth via V12.
  • the eighth via hole V8 may be located in the first sub-pixel P1
  • the ninth via hole V9 may be located in the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4.
  • the third conductive layer may include: a first power supply line VDD, a second power supply line VSS, a compensation signal line Sense and four data signal lines Data formed in each pixel unit, and may also include : the first connection electrode 13, the second connection electrode 14, the third connection electrode 23, the fourth connection electrode 24, the fifth connection electrode 33, the sixth connection electrode 34 and the first connection electrode 34 located in each sub-pixel in the pixel area 100 Triode 43.
  • the compensation signal line Sense may be disposed between the second sub-pixel P2 and the third sub-pixel P3.
  • the first end of the fifth connection electrode 33 in the third sub-pixel P3 is connected to the compensation connection line 51 through the seventh via hole V7 in this sub-pixel, so that the compensation signal line Sense is connected to the compensation connection line 51, and the third sub-pixel
  • the second end of the fifth connection electrode 33 in the pixel P3 is connected to the first region of the third active layer 31 in the sub-pixel through the fifth via hole V5 in the sub-pixel, and the fifth connection in the third sub-pixel P3
  • the third end of the electrode 33 is connected to the compensation signal line Sense.
  • the three-electrode plate 43 is mirror-symmetrical with respect to the vertical axis (for example, the compensation signal line Sense), and the first connection electrode 13, the second connection electrode 14, the third connection electrode 23,
  • the fourth connection electrode 24 , the fifth connection electrode 33 , the sixth connection electrode 34 and the third electrode plate 43 are mirror-symmetrical with respect to the vertical axis (for example, the compensation signal line Sense).
  • the third conductive layer may include: a plurality of via holes opened on the fourth insulating layer 64 and the fifth insulating layer 65 , and the plurality of via holes may include: a thirteenth conductive layer located in the pixel region 100 The via hole V13 and the fourteenth via hole V14.
  • the thirteenth via hole V13 is disposed in the first sub-pixel P1 at the position of the gap 44 between the second plate 42 and the third active layer 31 in the first sub-pixel P1.
  • the fourteenth via hole V14 is respectively disposed in the second sub-pixel P2 , the third sub-pixel P3 and the fourth sub-pixel P4 , and the fourteenth via hole V14 is located at the position of the opening 45 in the second plate 42 .
  • the fourth conductive layer may include: a first anode layer 701 located in each pixel unit.
  • the first anode layer 701 in each pixel unit may include: a first anode 701R, a second anode 701G, a third anode 701B and a fourth anode 701W.
  • the first anode 701R, the second anode 701G and the third anode 701B are all formed in the pixel region 100 .
  • the fourth anode 701W includes: a main body part formed in the pixel region 100 in this pixel unit (for example, the first pixel unit) and a body part formed in the transparent region 200 in the adjacent pixel unit (for example, the second pixel unit). extension.
  • the main bodies of the first anode 701R, the second anode 701G, the third anode 701B, and the fourth anode 701W are sequentially arranged along the second direction DR2 .
  • the extension part of the fourth anode 701W in the first pixel unit is located in the first transparent sub-region 201 of the second pixel unit, and is located in the first pixel unit of the first anode 701R, the second anode 701G and the third anode 701B in the first pixel unit.
  • Direction DR1 is opposite to one side. In this way, the white sub-pixel area in this pixel unit can be expanded to the transparent area in the adjacent pixel unit, which can increase the aperture ratio without affecting the transparency.
  • the fifth conductive layer may include: a second anode layer 702 located in each pixel unit.
  • the second anode layer 702 in each pixel unit may include: a fifth anode 702R, a sixth anode 702G, a seventh anode 702B, and an eighth anode 702W located in the pixel region 100 .
  • the fifth anode 702R, the sixth anode 702G, the seventh anode 702B, and the eighth anode 702W are sequentially arranged along the second direction DR2 .
  • the pixel definition layer 71 may include: a first pixel opening 71R in the first sub-pixel P1 exposing the fifth anode 702R, a second pixel in the second sub-pixel P2 exposing the sixth anode 702G The opening 71G, the third pixel opening 71B in the third sub-pixel P3 exposing the seventh anode 702B, and the fourth pixel opening 71W in the fourth sub-pixel P4 exposing the eighth anode 702W and the fourth anode 701W.
  • the first pixel opening 71R, the second pixel opening 71G and the third pixel opening 71B are arranged in sequence in the second direction DR2.
  • the first transparent sub-region 201 in the transparent region 200 of the pixel unit may include: The base 10 and the first insulating layer 61 , the third insulating layer 63 , the fourth insulating layer 64 and the first anode layer 701 stacked on the base 10 in sequence.
  • the second transparent sub-region 202 in the transparent region 200 of the pixel unit may include: the substrate 10 and the first insulating layer 61 , the third insulating layer 63 and the fourth insulating layer 64 sequentially stacked on the substrate 10 . In this way, the first anode layer of the white sub-pixel in the pixel unit is extended to the first transparent sub-region 201 in the pixel unit.
  • the display substrate provided by the exemplary embodiments of the present disclosure can expand the first anode layer of the white sub-pixel in this pixel unit to the transparent area in the adjacent pixel unit, without reducing the On the premise of the area of the small transparent area, the pixel area can be increased to increase the pixel aperture ratio to a certain extent, thereby improving the display effect.
  • the first anode layer is formed of a transparent conductive material, the display effect can be improved without affecting the transparency effect.
  • the structures and preparation processes of the various display substrates listed above are merely illustrative, and those skilled in the art can change the corresponding structures and increase or decrease the patterning process according to the actual situation.
  • four sub-pixels may be arranged side by side along the first direction DR1 and so on.
  • the pixel driving circuit may adopt a structure such as 5T1C or 7T1C.
  • other electrodes or leads may also be arranged in the film layer structure.
  • the embodiments of the present disclosure do not limit this.
  • the present disclosure also provides a method for preparing a display substrate.
  • the display substrate includes: a plurality of pixel units, each pixel unit includes: a transparent area and a pixel area, and each pixel unit includes: a plurality of sub-pixels;
  • the preparation method may include: A driving circuit layer is formed on the substrate; a light-emitting structure layer is formed on the side of the driving circuit layer away from the substrate, and the light-emitting structure layer may include: a stacked first anode layer and a second anode layer, wherein the white sub-pixel in the plurality of sub-pixels The second anode layer is located in the pixel area of the pixel unit;
  • the first anode layer of the white sub-pixel includes: a main body located in the pixel area of the pixel unit and an extension located in the transparent area of the pixel unit, or the white sub-pixel
  • the first anode layer of the pixel includes: a main body part located in the pixel area of the pixel unit
  • the display substrate prepared by the exemplary embodiment of the present disclosure can increase the pixel area without reducing the area of the transparent area by extending the first anode layer of the white sub-pixel from the pixel area to the transparent area. , so that the pixel aperture ratio is increased to a certain extent, and thus the display effect can be improved. Moreover, since the first anode layer is usually formed of a transparent conductive material, the display effect can be improved without affecting the transparency effect.
  • Exemplary embodiments of the present disclosure also provide a display device.
  • the display device may include: the display substrate in one or more of the above-mentioned exemplary embodiments.
  • the display substrate may include, but is not limited to: an OLED display substrate or a Quantum-dot Light Emitting Diodes (Quantum-dot Light Emitting Diodes, QLED) display substrate and the like.
  • QLED Quantum-dot Light Emitting Diodes
  • the display device may include, but is not limited to: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator.
  • the embodiment of the present disclosure does not limit the type of the display device.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as limitations on the present disclosure.

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Abstract

一种显示基板及显示装置，该显示基板包括：透明区域和像素区域，像素区域包括：多个发光器件，所述多个发光器件包括：第一发光器件，所述第一发光器件的第一阳极层在显示基板平面的正投影与所述透明区域在显示基板平面的正投影部分交叠，所述第一发光器件的第二阳极层在显示基板平面的正投影位于所述像素区域在显示基板平面的正投影的范围之内。

Description

显示基板及显示装置 技术领域
本公开实施例涉及但不限于显示技术领域，尤其涉及一种显示基板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度等优点。随着显示技术的不断发展，以OLED为发光器件、由薄膜晶体管(Thin Film Transistor，TFT)进行信号控制、可弯曲的柔性显示(Flexible Display)装置已成为目前显示领域的主流产品。
随着显示技术的不断发展，OLED技术越来越多的应用于透明显示中。透明显示是显示技术一个重要的个性化显示领域，是指在透明状态下进行图像显示，观看者不仅可以看到显示装置中的影像，而且可以看到显示装置背后的景象。目前，透明显示装置通常是将每一个像素单元划分为像素区域和透明区域，像素区域设置像素驱动电路和发光器件实现图像显示，透明区域实现光线透过。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开实施例提供了一种显示基板，包括：透明区域和像素区域，像素区域包括：多个发光器件，所述多个发光器件包括：第一发光器件，所述第一发光器件的第一阳极层在显示基板平面的正投影与所述透明区域在显示基板平面的正投影部分交叠，所述第一发光器件的第二阳极层在显示基板平面的正投影位于所述像素区域在显示基板平面的正投影的范围之内。
第二方面，本公开实施例还提供了一种显示装置，包括上述实施例中所 述的显示基板。
本公开的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本公开而了解。本公开的其他优点可通过在说明书以及附图中所描述的方案来实现和获得。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中每一个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种透明OLED显示基板的结构示意图；
图2为一种像素驱动电路的等效电路示意图；
图3为本公开示例性实施例中的显示基板的第一种结构示意图；
图4为本公开示例性实施例中的显示基板的第二种结构示意图；
图5为本公开示例性实施例中的显示基板的第三种结构示意图；
图6为本公开示例性实施例中的显示基板的第四种结构示意图；
图7A为形成图3所示的显示基板中第一导电层后的示意图；
图7B为形成图3所示的显示基板中半导体层后的示意图；
图7C为形成图3所示的显示基板中第二导电层后的示意图；
图7D为形成图3所示的显示基板中第三绝缘层后的示意图；
图7E为形成图3所示的显示基板中第三导电层后的示意图；
图7F为形成图3所示的显示基板中第五绝缘层后的示意图；
图7G为形成图3所示的显示基板中第四导电层后的示意图；
图7H为形成图3所示的显示基板中第五导电层后的示意图；
图7I为形成图3所示的显示基板中像素定义层后的示意图；
图7J为图7I所示的显示基板沿A-A’方向的剖面图；
图8A为形成图4所示的显示基板中第一导电层后的示意图；
图8B为形成图4所示的显示基板中半导体层后的示意图；
图8C为形成图4所示的显示基板中第二导电层后的示意图；
图8D为形成图4所示的显示基板中第三绝缘层后的示意图；
图8E为形成图4所示的显示基板中第三导电层后的示意图；
图8F为形成图4所示的显示基板中第五绝缘层后的示意图；
图8G为形成图4所示的显示基板中第四导电层后的示意图；
图8H为形成图4所示的显示基板中第五导电层后的示意图；
图8I为形成图4所示的显示基板中像素定义层后的示意图；
图8J为图8I所示的显示基板沿A-A’方向的剖面图；
图9A为形成图5所示的显示基板中第一导电层后的示意图；
图9B为形成图5所示的显示基板中半导体层后的示意图；
图9C为形成图5所示的显示基板中第二导电层后的示意图；
图9D为形成图5所示的显示基板中第三绝缘层后的示意图；
图9E为形成图5所示的显示基板中第三导电层后的示意图；
图9F为形成图5所示的显示基板中第五绝缘层后的示意图；
图9G为形成图5所示的显示基板中第四导电层后的示意图；
图9H为形成图5所示的显示基板中第五导电层后的示意图；
图9I为形成图5所示的显示基板中像素定义层后的示意图；
图9J为图9I所示的显示基板沿A-A’方向的剖面图；
图10A为形成图6所示的显示基板中第一导电层后的示意图；
图10B为形成图6所示的显示基板中半导体层后的示意图；
图10C为形成图6所示的显示基板中第二导电层后的示意图；
图10D为形成图6所示的显示基板中第三绝缘层后的示意图；
图10E为形成图6所示的显示基板中第三导电层后的示意图；
图10F为形成图6所示的显示基板中第五绝缘层后的示意图；
图10G为形成图6所示的显示基板中第四导电层后的示意图；
图10H为形成图6所示的显示基板中第五导电层后的示意图；
图10I为形成图6所示的显示基板中像素定义层后的示意图；
图10J为图10I所示的显示基板沿A-A’方向的剖面图。
具体实施方式
本文描述了多个实施例，但是该描述是示例性的，而不是限制性的，在本文所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在示例性实施方式中进行了讨论，但是所公开的特征的许多其它组合方式也是可能的。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
在描述具有代表性的实施例时，说明书可能已经将方法或过程呈现为特定的步骤序列。然而，在该方法或过程不依赖于本文步骤的特定顺序的程度上，该方法或过程不应限于的特定顺序的步骤。如本领域普通技术人员将理解的，其它的步骤顺序也是可能的。因此，说明书中阐述的步骤的特定顺序不应被解释为对权利要求的限制。此外，针对该方法或过程的权利要求不应限于按照所写顺序执行它们的步骤，本领域技术人员可以容易地理解，这些顺序可以变化，并且仍然保持在本公开实施例的精神和范围内。
在附图中，有时为了明确起见，夸大表示了构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本公开示例性实施例中，为了方便起见，使用“中部”、“上”、“下”、 “前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本公开示例性实施例中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本公开示例性实施例中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”例如可以是电极或布线，或者是晶体管等开关元件，或者是电阻器、电感器或电容器等其它功能元件等。
在本公开示例性实施例中，晶体管是指至少包括栅电极(又可称为栅极或控制极)、漏电极(又可称为漏电极端子、漏区域或漏极)以及源电极(又可称为源电极端子、源区域或源极)这三个端子的元件。晶体管在漏电极与源电极之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本公开示例性实施例中，为了区分晶体管除栅电极之外的两极，直接描述了其中一极为第一极，另一极为第二极，其中，第一极可以为漏电极且第二极可以为源电极，或者，第一极可以为源电极且第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本公开示例性实施例中的晶体管均可以为薄膜晶体管(Thin Film Transistor，TFT)或场效应管(Field Effect Transistor，FET)或其它特性相 同的器件。例如，本公开实施例中使用的薄膜晶体管可以包括但不限于氧化物晶体管(Oxide TFT)或者低温多晶硅薄膜晶体管(Low Temperature Poly-silicon TFT，LTPS TFT)等。例如，薄膜晶体管可以选择底栅结构的薄膜晶体管或者顶栅结构的薄膜晶体管，只要能够实现开关功能即可。这里，本公开实施例对此不做限定。
在本公开示例性实施例中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
在本公开示例性实施例中，三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、近似矩形、近似梯形、近似五边形或近似六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
在本公开示例性实施例中，“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
在本公开示例性实施例中，“一体结构”可以是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的彼此连接的结构，它们的材料可以相同或不同。
在一种示例性实施例中，第一方向DR1可以是指水平方向或者扫描信号线的延伸方向等，第二方向DR2可以是指竖直方向或者数据信号线的延伸方向等，第三方向DR3可以是指显示基板的厚度方向或者垂直于显示基板平面的方向等。其中，第一方向DR1与第二方向DR2交叉，第一方向DR1与第三方向DR3交叉。例如，第一方向DR1和第二方向DR2可以相互垂直，第一方向DR1和第三方向DR3可以相互垂直。
随着显示技术的不断发展，OLED技术越来越多的应用于透明显示中。透明显示是显示技术中一个重要的个性化显示领域，是指在透明状态下进行图像显示，观看者不仅可以看到显示装置中的影像，而且可以看到显示装置背后的景象，可以给观看者带来不一样的视觉体验，使得观看者感受到的视觉冲击感更加强烈。
图1为一种透明OLED显示基板的结构示意图。如图1所示，在一些技 术中，透明OLED显示基板的显示区域(AA区)可以包括：阵列排布的多个像素(Pixel)单元P，每一个像素单元P可以包括：一个像素区域100和一个透明区域200，每一个像素单元P可以包括：多个子像素，多个子像素位于像素区域100。其中，像素区域100，可以称为像素开口率(Aperture Ratio，AR)区，设置像素驱动电路和发光器件(如，OLED)，被配置为通过控制OLED发光来实现图像显示。透明区域200，可以称为TR区，被配置为实现光线透过，从而实现透明状态下的图像显示，如此，观看者通过透明区域200可以看到透明OLED显示基板后面的景象，即透明显示。但是，这种像素设计方式，会导致像素开口率较低，影响显示效果。这里，在图1中，以每一个像素单元P包括：一个红色(Red，R)子像素、一个绿色(Green，G)子像素、一个蓝色(Blue，B)子像素和一个白色(White，W)子像素为例进行示意。
本公开实施例提供一种显示基板，显示基板可以包括：透明区域和像素区域，像素区域包括：多个发光器件，多个发光器件包括：第一发光器件，第一发光器件的第一阳极层在显示基板平面的正投影与透明区域在显示基板平面的正投影部分交叠，第一发光器件的第二阳极层在显示基板平面的正投影位于像素区域在显示基板平面的正投影的范围之内。如此，本公开示例性实施例所提供的显示基板，通过将第一发光器件的第一阳极层延伸至透明区域，可以在不减小透明区域的面积的前提下，实现增大像素区域，使像素开口率有一定程度的提升，从而，可以提升显示效果。而且，由于第一阳极层通常采用透明导电材料形成，因此，可以实现在提升显示效果的同时不影响透明效果。
这里，像素区域可以是指设置发光器件和用于驱动发光器件的像素驱动电路的区域，而透明区域可以是指未设置像素驱动电路的区域，具有较高的透光度以用于自然光的透光，其中，透明区域的透光度大于像素区域的透光度。例如，透明区域中多个膜层的透光度可以大于80％。
在一种示例性实施例中，第一发光器件的发光(Emitted-Light，EL)层在显示基板平面的正投影，与透明区域在显示基板平面的正投影部分交叠，且与像素区域在显示基板平面的正投影部分交叠。
在一种示例性实施例中，第一阳极层的透光度大于第二阳极层的透光度。
在一种示例性实施例中，第一阳极层采用透明导电材料。例如，透明导电材料可以包括：氧化铟锡或者氧化铟锌等。这里，本公开实施例对此不做限定。
在一种示例性实施例中，第二阳极层采用金属材料形成，或者，采用金属材料和透明导电材料形成。这里，本公开实施例对此不做限定。
在一种示例性实施例中，多个发光器件还可以包括：第二发光器件，第二发光器件的第一阳极层在显示基板平面的正投影、第二发光器件的第二阳极层在显示基板平面的正投影、以及第二发光器件的发光(EL)层在显示基板平面的正投影均位于像素区域在显示基板平面的正投影的范围之内。例如，第一发光器件可以为白色(W)发光器件，第二发光器件可以包括但不限于：红色(R)发光器件、绿色(G)发光器件或者蓝色(B)发光器件等其它颜色发光器件。如此，可以实现将透光度相对较低的其它颜色发光器件均设置于像素区域中。
在一种示例性实施例中，多个发光器件可以包括：一个第一发光器件和三个第二发光器件，第一发光器件包括：白色发光器件，三个第二发光器件可以包括：一个红色发光器件、一个绿色发光器件和一个蓝色发光器件，蓝色发光器件的第二阳极层的面积大于红色发光器件的第二阳极层的面积和绿色发光器件的第二阳极层的面积，白色发光器件的第二阳极层的面积小于红色发光器件的第二阳极层的面积和绿色发光器件的第二阳极层的面积。如此，可以实现减小白色发光器件在像素区域中所占用的面积，以实现至少增大蓝色发光器件在像素区域中所占用的面积。由于白色发光器件中的第一阳极层延伸至透明区域，因此，可以在不减小透明区域的面积的前提下，实现增大像素区域，使像素开口率有一定程度的提升，从而，可以提升显示效果。
在一种示例性实施例中，透明区域包括：沿第一方向依次设置的第一透明子区和第二透明子区，像素区域包括：沿第二方向依次设置的第一区和第二区，第一区包括：沿第一方向依次设置的第一子区和第二子区，第二区包括：沿第一方向依次设置的第三子区和第四子区；一个第一发光器件的第一阳极层在显示基板平面的正投影，与第一子区至第四子区中的一个子区在显 示基板平面的正投影至少部分交叠，且与第一透明子区和第二透明子区中的一个在显示基板平面的正投影至少部分交叠；三个第二发光器件的第一阳极层在显示基板平面的正投影，分别与第一子区至第四子区中的其它三个子区在显示基板平面的正投影至少部分交叠，且互不相同；第二方向与第一方向交叉。
在一种示例性实施例中，蓝色发光器件的第二阳极层在显示基板平面的正投影的长度，大于红色发光器件的第二阳极层在显示基板平面的正投影的长度、绿色发光器件的第二阳极层在显示基板平面的正投影的长度、以及白色发光器件的第二阳极层在显示基板平面的正投影的长度，长度是指沿第一方向的尺寸特征。如此，可以实现通过增大蓝色发光器件在像素区域中所占用的面积。
在一种示例性实施例中，透明区域包括：沿第一方向依次设置的第一透明子区和第二透明子区，像素区域包括：沿第二方向依次设置的第一区和第二区，第一区包括：沿第二方向依次设置的第五子区和第六子区，第二区包括：沿第二方向依次设置的第七子区和第八子区；一个第一发光器件的第一阳极层在显示基板平面的正投影，与第五子区至第八子区中的一个子区在显示基板平面的正投影至少部分交叠，且与第一透明子区和第二透明子区中的一个在显示基板平面的正投影至少部分交叠；三个第二发光器件的第一阳极层在显示基板平面的正投影，分别与第一子区至第五子区中的其它三个子区在显示基板平面的正投影至少部分交叠，且互不相同；第二方向与第一方向交叉。
在一种示例性实施例中，蓝色发光器件的第二阳极层在显示基板平面的正投影的宽度，大于红色发光器件的第二阳极层在显示基板平面的正投影的宽度、绿色发光器件的第二阳极层在显示基板平面的正投影的宽度、以及白色发光器件的第二阳极层在显示基板平面的正投影的宽度，宽度是指沿第二方向的尺寸特征。如此，可以实现通过增大蓝色发光器件在像素区域中所占用的面积。
在一种示例性实施例中，像素区域还可以包括：多个像素驱动电路，像素驱动电路被配置为驱动发光器件，多个像素驱动电路在显示基板平面的正 投影位于像素区域在显示基板平面的正投影的范围之内。如此，可以实现将透光度相对较低的像素驱动电路设置于像素区域中。
在一种示例性实施例中，像素驱动电路可以包括：第一晶体管、第二晶体管和第三晶体管，第一晶体管和第三晶体管位于第二晶体管的第二方向的两侧，且第一晶体管、第二晶体管和第三晶体管的沟道区域的延伸方向均为第二方向。如此，通过优化晶体管排布，可以减少像素驱动电路占用像素区域的面积，节省布图空间，利于像素尺寸的减小，实现较高的分辨率(Pixel Per Inch，PPI)，从而，实现较好的显示效果。这里，本公开实施例中所使用的“晶体管的沟道区域的延伸方向”可以是指晶体管的有源层的第一区与第二区之间的连接线的延伸方向，即晶体管的第一极与晶体管的第二极之间的连接线的延伸方向。
在一种示例性实施例中，像素驱动电路还可以包括：存储电容，存储电容位于第二晶体管和第三晶体管之间，且存储电容的延伸方向为第二方向。如此，通过优化晶体管和存储电容排布，可以减少像素驱动电路占用像素区域的面积，更节省布图空间，利于像素尺寸的减小，实现较高的分辨率(PPI)，从而，实现较好的显示效果。
在一种示例性实施例中，多个像素驱动电路可以沿第一方向并排设置。这里，本公开实施例中所使用的“并排”是指排列在一条直线上。
在一种示例性实施例中，像素驱动电路包括：第一晶体管、第二晶体管、第三晶体管和存储电容；在垂直于显示基板平面的方向上，显示基板可以包括：在基底上依次设置的第一导电层、半导体层、第二导电层和第三导电层；第一导电层包括：第一极板，半导体层包括：第一晶体管的有源层、第二晶体管的有源层、第三晶体管的有源层和第二极板，第二导电层包括：第一晶体管的栅电极、第二晶体管的栅电极和第三晶体管的栅电极，第三导电层可以包括：第一晶体管的第一极、第一晶体管的第二极、第二晶体管的第一极、第二晶体管的第二极、第三晶体管的第一极、第三晶体管的第二极和第三极板，第一极板和第二极板形成第一存储电容，第二极板和第三极板形成第二存储电容，第一存储电容和第二存储电容并联，以形成存储电容。
在一种示例性实施例中，第一导电层还包括：补偿连接线，第三导电层 还包括：补偿信号线，第三晶体管的第一极通过补偿连接线与补偿信号线连接。
在一种示例性实施例中，第二导电层包括：电源连接线，第三导电层还包括：第一电源线，第二晶体管的第一极通过电源连接线与第一电源线连接；第一电源线通过过孔与电源连接线连接，在第一晶体管的栅电极与第三晶体管的栅电极之间形成双层走线。
在一种示例性实施例中，第二导电层还包括：第一扫描信号线和第二扫描信号线，第一晶体管的栅电极与第一扫描信号线连接，第三晶体管的栅电极与第二扫描信号线连接。
在一种示例性实施例中，第三导电层还包括：数据信号线，第一晶体管的第一极与数据信号线连接。
在一种示例性实施例中，像素驱动电路可以包括但不限于采用：3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或者8T1C等电路结构。其中，“3T1C”中的“3T”是指3个晶体管，“1C”是指1个存储电容或多个电容并联之后的整体；4T1C、5T1C、5T2C、6T1C、7T1C或者8T1C等依次类推。这里，本公开实施例对此不做限定。
在一种示例性实施例中，以像素驱动电路采用3T1C结构为例，图2为一种像素驱动电路的等效电路示意图。如图2所示，像素驱动电路可以包括：3个晶体管(第一晶体管T1、第二晶体管T2和第三晶体管T3)和1个存储电容C；显示基板还包括：6个信号线(数据信号线Data、第一扫描信号线G1、第二扫描信号线G2、补偿信号线Sense、第一电源线VDD和第二电源线VSS)。其中，第一晶体管T1为开关晶体管，第二晶体管T2为驱动晶体管，第三晶体管T3为补偿晶体管。第一晶体管T1的栅电极耦接于第一扫描信号线G1，第一晶体管T1的第一极耦接于数据信号线Data，第一晶体管T1的第二极耦接于第二晶体管T2的栅电极，第一晶体管T1被配置为在第一扫描信号线G1控制下，接收数据信号线Data传输的数据信号，使第二晶体管T2的栅电极接收数据信号。第二晶体管T2的栅电极耦接于第一晶体管T1的第二极，第二晶体管T2的第一极耦接于第一电源线VDD，第二晶体管T2的第二极耦接于发光器件L的第一极，第二晶体管T2被配置为在其栅电 极所接收的数据信号控制下，在第二极产生相应的电流。第三晶体管T3的栅电极耦接于第二扫描信号线G2，第三晶体管T3的第一极耦接于补偿信号线Sense，第三晶体管T3的第二极耦接于第二晶体管T2的第二极，第三晶体管T3被配置为响应补偿时序提取第二晶体管T2的阈值电压Vth以及迁移率，以对阈值电压Vth进行补偿。发光器件L的第一极耦接于第二晶体管T2的第二极，发光器件L的第二极耦接于第二电源线VSS，发光器件L被配置为响应第二晶体管T2的第二极的电流而发出相应亮度的光。存储电容C的第一极与第二晶体管T2的栅电极耦接，存储电容C的第二极与第二晶体管T2的第二极耦接，存储电容C被配置为存储第二晶体管T2的栅电极的电位。
在一种示例性实施例中，第一电源线VDD的信号为持续提供高电平信号，第二电源线VSS的信号为低电平信号。
在一种示例性实施例中，第一晶体管T1到第三晶体管T3可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。在一种示例性实施例中，第一晶体管T1到第三晶体管T3可以包括P型晶体管和N型晶体管。
在一种示例性实施例中，第一扫描信号线S1、第二扫描信号线S2可以沿第一方向DR1延伸，第二电源线VSS、第一电源线VDD和数据信号线Data可以沿第二方向DR2延伸。
在一种示例性实施例中，发光器件L可以为具备发光性能的电子器件。例如，发光器件可以包括：有机电致发光二极管(OLED)或者量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)等。这里，本公开实施例对此不做限定。
在一种示例性实施例中，以发光器件L采用OLED为例，发光器件L可以包括：叠设的第一极(例如，作为阳极)、有机发光层和第二极(例如，作为阴极)。
在一种示例性实施例中，多个像素单元P的至少一个可以包括：四个子像素，其中，四个子像素中的一个子像素可以为白色(W)子像素，四个子 像素中的除了该一个子像素以外的另外三个子像素可以分别为红色(R)子像素、绿色(G)子像素和蓝色(B)子像素中任意一种且互不相同。例如，四个子像素可以包括：出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2、出射第三颜色光线的第三子像素P3和出射第四颜色光线的第四子像素P4，第一子像素P1可以是红色(R)子像素，第二子像素P2可以是绿色(G)子像素，第三子像素P3可以是蓝色(B)子像素，第四子像素P4可以是白色(W)子像素。这里，本公开实施例对此不做限定。
在一种示例性实施例中，以像素单元包括四个子像素为例，四个子像素可以采用矩形方式、竖直并列或者水平并列等方式排列。这里，本公开实施例对此不做限定。
在一种示例性实施例中，一个发光器件与对应的一个像素驱动电路可以划分为一个子像素。例如，白色(W)子像素可以包括一个白色发光器件以及与白色发光器件连接的一个像素驱动电路，红色(R)子像素可以包括一个红色发光器件以及与白色发光器件连接的一个像素驱动电路，绿色(G)子像素可以包括一个绿色发光器件以及与白色发光器件连接的一个像素驱动电路，蓝色(B)子像素可以包括一个蓝色发光器件以及与白色发光器件连接的一个像素驱动电路。
下面以第一子像素P1为红色(R)子像素，第二子像素P2为绿色(G)子像素，第三子像素P3为蓝色(B)子像素，第四子像素P4为白色(W)子像素为例，结合附图对显示基板的结构和制备过程进行说明。这里，以白色发光器件作为第一发光器件，红色发光器件、蓝色发光器件和绿色发光器件作为第二发光器件为例进行示意。
图3为本公开示例性实施例中的显示基板的第一种结构示意图。图4为本公开示例性实施例中的显示基板的第二种结构示意图。图5为本公开示例性实施例中的显示基板的第三种结构示意图。图6为本公开示例性实施例中的显示基板的第四种结构示意图。其中，在图3至图6中以显示基板上的两个像素单元为例进行示意。在图3和图4中以四个子像素可以采用矩形方式排列为例进行示意。在图5和图6中以四个子像素可以采用竖直并列为例进行示意。
在一种示例性实施例中，如图3至图6所示，显示基板可以包括：交替排布的多个像素区域100和多个透明区域200。显示基板还可以包括：阵列排布的多个像素(Pixel)单元，每一个像素单元可以包括：沿第一方向DR1依次设置的透明区域200和像素区域100。针对每一个像素单元，第一子像素P1、第二子像素P2和第三子像素P3的第二发光器件形成于本像素单元中的像素区域100。如图4和图5所示，第四子像素P4的第一发光器件形成于本像素单元中的像素区域100和透明区域200，或者，如图3和图6所示，第四子像素P4的第一发光器件形成于本像素单元中的像素区域100和相邻像素单元中的透明区域200。
在一种示例性实施例中，针对每一个像素单元，第一子像素P1至第四子像素P4的像素驱动电路均形成于本像素单元中的像素区域100。
在一种示例性实施例中，针对每一个像素单元，如图4和图5所示，第四子像素P4的第一发光器件中的第一电极层包括：位于本像素单元中的像素区域100的主体部和位于本像素单元中的透明区域200的延伸部，或者，如图3和图6所示，第四子像素P4的第一发光器件中的第一电极层包括：位于本像素单元中的像素区域100的主体部和位于相邻像素单元中的透明区域200的延伸部。如此，可以使得第一发光器件外扩至透明区域。
在一种示例性实施例中，如图3所示，在每一个像素单元中，透明区域200可以包括：沿第一方向DR1依次设置的第一透明子区201和第二透明子区202，像素区域100可以包括：沿第二方向DR2依次设置的第一区101和第二区102，第一区101可以包括：沿第一方向DR1依次设置的第一子区101-1和第二子区101-2，第二区102可以包括：沿第一方向DR1依次设置的第三子区102-1和第四子区102-2。例如，针对每一个像素单元，每一个第一子像素P1的第二发光器件形成于本像素单元中的第一子区101-1，每一个第二子像素P2的第二发光器件形成于本像素单元中的第二子区101-2，第三子像素P3的第二发光器件形成于本像素单元中的第三子区102-1，第四子像素P4的第一发光器件形成于本像素单元中的第四子区102-2和相邻像素单元中的第一透明子区201。
在一种示例性实施例中，如图3所示，每一个第四子像素P4的第一阳 极层可以包括：位于像素区域100的主体部和位于透明区域200的延伸部，主体部和延伸部可以位于相邻的两个像素单元中。例如，由于第一像素单元中的第四子区102-2位于像素区域100的右下侧位置，与第二像素单元的透明区域200中第一透明子区201邻近，因此，第一像素单元中的第四子像素P4的主体部可以设置于第一像素单元中的第四子区102-2，第一像素单元中的第四子像素P4的延伸部可以设置于第二像素单元中的第一透明子区201。如此，可以实现第一像素单元中的第四子像素P4(即白色子像素)外扩至第二像素单元中的透明区域，可以提升开口率。
当然，除了图3所示的示例性实施例方式之外，还可以将第四子像素P4的第一发光器件形成于本像素单元中的像素区域中的其它子区(例如，第二子区101-2)以及相邻像素单元中的第一透明子区201中。这里，本公开实施例对此不做限定。
在一种示例性实施例中，如图4所示，在每一个像素单元中，透明区域200可以包括：沿第一方向DR1依次设置的第一透明子区201和第二透明子区202，像素区域100可以包括：沿第二方向DR2依次设置的第一区101和第二区102，第一区101可以包括：沿第一方向DR1依次设置的第一子区101-1和第二子区101-2，第二区102可以包括：沿第一方向DR1依次设置的第三子区102-1和第四子区102-2。例如，针对每一个像素单元，每一个第一子像素P1的第二发光器件形成于本像素单元中的第一子区101-1，每一个第二子像素P2的第二发光器件形成于本像素单元中的第二子区101-2，第三子像素P3的第二发光器件形成于本像素单元中的第四子区102-2，第四子像素P4的第一发光器件形成于本像素单元中的第三子区102-1和第二透明子区202。
在一种示例性实施例中，如图4所示，每一个第四子像素P4的第一发光器件的第一阳极层可以包括：位于像素区域100的主体部和位于透明区域200的延伸部，主体部和延伸部可以位于同一个像素单元中。例如，由于第一像素单元中的第三子区102-1位于像素区域100的左下侧位置，与第一像素单元中的透明区域200中第二透明子区202邻近，因此，第一像素单元中的第四子像素P4的主体部可以设置于第一像素单元中的第三子区102-1，第一像素单元中的第四子像素P4的延伸部可以设置于第一像素单元中的第二 透明子区202。如此，可以实现第一像素单元中的第四子像素P4(即白色子像素)外扩至第一像素单元中的透明区域，可以提升开口率。
当然，除了图4所示的示例性实施例方式之外，还可以将第四子像素的第一发光器件形成于本像素单元中的像素区域中的其它子区(例如，第一子区101-1)以及第二透明子区202中。这里，本公开实施例对此不做限定。
在一种示例性实施例中，如图5所示，在每一个像素单元中，透明区域200可以包括：沿第一方向DR1依次设置的第一透明子区201和第二透明子区202，像素区域100可以包括：沿第二方向DR2依次设置的第一区101和第二区102，第一区101可以包括：沿第二方向DR2依次设置的第五子区101-3和第六子区101-4，第二区102可以包括：沿第二方向DR2依次设置的第七子区102-3和第八子区102-4。例如，针对每一个像素单元，每一个第一子像素P1的第二发光器件形成于本像素单元中的第五子区101-3，每一个第二子像素P2的第二发光器件形成于本像素单元中的第六子区101-4，第三子像素P3的第二发光器件形成于本像素单元中的第七子区102-3，第四子像素P4的第一发光器件形成于本像素单元中的第八子区102-4和第二透明子区202。
在一种示例性实施例中，如图5所示，每一个第四子像素P4的第一发光器件的第一阳极层可以包括：位于像素区域100的主体部和位于透明区域200的延伸部，主体部和延伸部可以位于同一个像素单元中。例如，由于第一像素单元中的第八子区102-4与第一像素单元中的第二透明子区202邻近，因此，第一像素单元中的第四子像素P4的主体部可以设置于第一像素单元中的第八子区102-4，第一像素单元中的第四子像素P4的延伸部可以设置于第一像素单元中的第二透明子区202。如此，可以实现第一像素单元中的第四子像素P4(即白色子像素)外扩至第一像素单元中的透明区域，可以提升开口率。
当然，除了图5所示的示例性实施例方式之外，还可以将第四子像素P4形成于本像素单元中的像素区域中的其它子区(例如，第五子区101-3、第六子区101-4和第七子区102-3中的任意一种位置)以及第二透明子区202中。这里，本公开实施例对此不做限定。
在一种示例性实施例中，如图6所示，在每一个像素单元中，透明区域 200可以包括：沿第一方向DR1依次设置的第一透明子区201和第二透明子区202，像素区域100可以包括：沿第二方向DR2依次设置的第一区101和第二区102，第一区101可以包括：沿第二方向DR2依次设置的第五子区101-3和第六子区101-4，第二区102可以包括：沿第二方向DR2依次设置的第七子区102-3和第八子区102-4。例如，针对每一个像素单元，每一个第一子像素P1的第二发光器件形成于本像素单元中的第五子区101-3，每一个第二子像素P2的第二发光器件形成于本像素单元中的第六子区101-4，第三子像素P3的第二发光器件形成于本像素单元中的第七子区102-3，第四子像素P4的第一发光器件形成于本像素单元中的第八子区102-4和相邻子像素中的第一透明子区201。
在一种示例性实施例中，如图6所示，每一个第四子像素P4的第一发光器件的第一阳极层可以包括：位于像素区域100的主体部和位于透明区域200的延伸部，主体部和延伸部可以位于相邻的两个像素单元中。例如，由于第一像素单元中的第八子区102-4与第二像素单元中的第一透明子区201邻近，因此，第一像素单元中的第四子像素P4的主体部可以设置于第一像素单元中的第八子区102-4，第一像素单元中的第四子像素P4的延伸部可以设置于第二像素单元中的第一透明子区201。如此，可以实现第一像素单元中的第四子像素P4(即白色子像素)外扩至第一像素单元中的透明区域，可以提升开口率。
当然，除了图6所示的示例性实施例方式之外，还可以将第四子像素P4的第一发光器件形成于本像素单元中的像素区域中的其它子区(例如，第五子区101-3、第六子区101-4和第七子区102-3中的任意一种位置)以及相邻子像素中的第一透明子区201中。这里，本公开实施例对此不做限定。
在一种示例性实施例中，在每一个像素单元中，像素区域100的面积可以约为像素单元的面积的30％至35％。
在一种示例性实施例中，在每一个像素单元中，透明区域200的面积可以约为像素单元的面积的42％至47％。例如，透明区域200的面积可以约为像素单元的面积的45％。这里，本公开实施例对此不做限定。
在一种示例性实施例中，在像素区域100中，红色(R)子像素的发光 器件所占用的面积可以约为像素区域100的面积的30％至36.37％，绿色(G)子像素的发光器件所在区域的面积可以约为像素区域100的面积的25％至29.1％，或者，蓝色(B)子像素的发光器件所在区域的面积可以约为像素区域100的面积的35％至40％。或者，在每一个像素单元中，白色(W)子像素的发光器件所在区域的面积可以约为像素单元的面积的40％至46.5％。这里，本公开实施例对此不做限定。
当然，除了上述实施例中所列出的多种示例性实施方式之外，还可以采用其它实施方式，例如，四个子像素采用水平并列方式排列，只要使得白色(W)子像素的第一阳极层包括位于像素区域的主体部和位于透明区域的延伸部即可。这里，本公开实施例对此不做限定。
下面通过显示基板的制备过程的示例说明显示基板的结构。本公开所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶处理。沉积可以采用溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用喷涂和旋涂中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。若在整个制作过程中该“薄膜”需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。本公开中所说的“A和B同层设置”是指，A和B通过同一次构图工艺同时形成。
在一种示例性实施例中，在垂直于显示基板的平面的方向(即第三方向DR3)上，显示基板可以包括：基底以及在基底上依次叠设的第一导电层、第一绝缘层、半导体层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层、第五绝缘层、第四导电层和第五导电层。
图7A至图7I为图3所示的显示基板制备过程的示意图，示意了显示基板的两个像素单元的版图结构，图7J为图7I所示的显示基板沿A-A’方向的剖面图。下面以图3所示显示基板的结构作参考，结合图7A至图7J，对本公开示例性实施例中提供的显示基板的制备过程进行说明。其中，图7A至图7I中，每一个像素单元包括像素区域100和透明区域200，每一个像素单 元包括第一子像素P1、第二子像素P2、第三子像素P3和第四子像素P4，每一个子像素的像素驱动电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容C。在像素区域100中，沿第一方向DR1依次设置第三子像素P3、第一子像素P1、第二子像素P2和第四子像素P4的像素驱动电路。
在一种示例性实施例中，显示基板的制备过程可以包括以下步骤：
(1)形成第一导电层。
在一种示例性实施例中，形成第一导电层可以包括：在基底上沉积第一导电薄膜，通过构图工艺对第一导电薄膜进行构图，在基底上形成第一导电层。
在一种示例性实施例中，第一导电层可以采用金属材料形成。例如，金属材料可以包括但不限于：银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或者上述列出的金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)等。第一导电层可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
在一种示例性实施例中，第一导电层可以称为遮挡(Shield，SHL)层。
在一种示例性实施例中，如图7A所示，第一导电层可以包括：补偿连接线51以及第一极板41。
在一种示例性实施例中，如图7A所示，补偿连接线51可以为沿着第一方向DR1延伸的条形结构。例如，补偿连接线51可以跨设在四个子像素中，被配置为与后续形成的补偿信号线Sense连接，使补偿信号线Sense向每一个子像素的第三晶体管T3提供补偿信号。
在一种示例性实施例中，如图7A所示，第一极板41可以设置在每一个子像素中，第一极板41既可以作为第一存储电容Cst1的一个极板，被配置为与后续形成的第二极板形成第一存储电容Cst1，第一极板41又可以作为遮挡层，被配置为对所在子像素中的晶体管进行遮光处理，降低照射到晶体管上的光强度，降低漏电流，从而减少光照对晶体管特性的影响。例如，四个第一极板41可以沿着第一方向DR1依次设置。例如，第一极板41的形状可以为沿着第二方向DR2延伸的呈条状的矩形结构，矩形结构的角部可以设 置倒角。此外，除了补偿连接线51位置，第一极板41可以完全覆盖每一个子像素的像素驱动电路区域。为了实现有效的遮挡，在第二方向DR2，第一极板41的长度可以大于后续形成的第一晶体管T1的栅电极与第三晶体管T3的栅电极之间的距离，或者，第一极板41的长度可以大于后续形成的第一晶体管的第一电极与第三晶体管的第一极之间的距离。
在一种示例性实施例中，第三子像素P3中的第一导电层图案与第四子像素P4中的第一导电层图案相对于垂直轴镜像对称，第一子像素P1中的第一导电层图案与第二子像素P2中的第一导电层图案相对于垂直轴镜像对称。
本次构图工艺后，第一导电层图案形成在像素区域100，透明区域200没有相应膜层。
(2)形成半导体层。
在一种示例性实施例中，形成半导体层可以包括：在形成前述结构的基底上，依次沉积第一绝缘薄膜和半导体薄膜，通过构图工艺对半导体薄膜进行构图，形成覆盖第一导电层的第一绝缘层61，以及设置在第一绝缘层61上的半导体层。
在一种示例性实施例中，第一绝缘层可以称为缓冲(Buffer)层，半导体层可以称为有源(Active，ACT)层。
在一种示例性实施例中，如图7B所示，半导体层可以包括：每一个子像素的第一有源层11、第二有源层21、第三有源层31和第二极板42。
在一种示例性实施例中，如图7B所示，第一有源层11作为第一晶体管T1的有源层，第二有源层21作为第二晶体管T2的有源层，第三有源层31作为第三晶体管T3的有源层。第一有源层31、第二有源层32和第三有源层33均包括沟道区域以及位于沟道区域两侧的第一区和第二区。
在一种示例性实施例中，如图7B所示，第一有源层11的形状可以为沿着第二方向DR2延伸的呈“Z”字形。
在一种示例性实施例中，如图7B所示，第二有源层21的形状可以为沿着第二方向DR2延伸的呈“I”字形。
在一种示例性实施例中，如图7B所示，第一有源层11、第二有源层21和第三有源层31在基底10上的正投影与第一极板41在基底10上的正投影存在交叠区域，使得作为遮挡层的第一极板41可以遮挡第一晶体管、第二晶体管和第三晶体管的沟道区域，避免光线对沟道产生影响，以避免沟道因生成光生漏电而影响显示效果。
在一种示例性实施例中，如图7B所示，第一有源层11、第二有源层21和第三有源层31在基底10上的正投影与第二极板42在基底10上的正投影间隔设置，即第一有源层11与第二极板42之间、第二有源层21与第二极板42之间以及第三有源层31与第二极板42之间没有交叠区域，有利于根据相关需求设计第一晶体管T1、第二晶体管T2和第三晶体管T3的沟道宽长比。
在一种示例性实施例中，第二极板34的形状可以为沿着第二方向DR2延伸的矩形状。例如，矩形状的角部可以设置倒角。例如，矩形状的边缘可以为折线。这里，本公开实施例对此不做限定。
在一种示例性实施例中，如图7B所示，第二极板42既作为第一存储电容Cst1的一个极板，又作为第二存储电容Cst2的一个极板。其中，第二极板42在基底10上的正投影与第一极板41在基底10上的正投影存在交叠区域，第二极板42被配置为与第一极板41形成第一存储电容Cst1。第二极板42在基底10上的正投影与后续形成的第三极板43在基底10上的正投影存在交叠区域，第二极板42还被配置为与后续形成的第三极板43形成第二存储电容Cst2。如此，通过第一存储电容Cst1和第二存储电容Cst2并联，以形成像素驱动电路的存储电容C，可以增大存储电容C的整体电容值。
在一种示例性实施例中，如图7B所示，第一子像素P1和第二子像素P2中的第二极板42与第三有源层31之间设置有间隔44，第三子像素P3和第四子像素P4的第二极板42中设置有开口45。
在一种示例性实施例中，第三子像素P3中的半导体层图案与第四子像素P4中的半导体层图案相对于垂直轴镜像对称。或者，第一子像素P1中的半导体层图案与第二子像素P2中的半导体层图案相对于垂直轴镜像对称。
在一种示例性实施例中，半导体层可以采用金属氧化物材料制成。例如， 金属氧化物材料可以包括但不限于：包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物、包含铟和镓和锌的氧化物等。例如，半导体层可以是单层、双层或者多层等。这里，本公开实施例对此不做限定。
在一种示例性实施例中，第一绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。
本次构图工艺后，半导体层图案形成在像素区域100，透明区域200包括基底10以及设置在基底10上的第一绝缘层61。
(3)形成第二导电层。
在一种示例性实施例中，形成第二导电层可以包括：在形成前述结构的基底上，依次沉积第二绝缘薄膜和第二导电薄膜，通过构图工艺对第二绝缘薄膜和第二导电薄膜进行构图，形成第二绝缘层62以及设置在第二绝缘层62上的第二导电层。第二绝缘层62与第二导电层图案相同。例如，第二绝缘层可以称为栅极绝缘(GI)层。例如，第二导电层可以称为栅金属(Gate，GT)层。
在一种示例性实施例中，第二绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。
在一种示例性实施例中，第二导电层可以采用金属材料形成。例如，金属材料可以包括但不限于：银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或者上述列出的金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)等。例如，第三导电层可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
在一种示例性实施例中，如图7C所示，第二导电层可以包括：第一扫描信号线G1、第二扫描信号线G2、电源连接线52和辅助电源线53，以及每一个子像素的第一栅电极12、第二栅电极22和第三栅电极32。
在一种示例性实施例中，如图7C所示，第一扫描信号线G1和第二扫描信号线G2可以为沿着第一方向DR1延伸的条形结构。例如，第一扫描信号线G1和第二扫描信号线G2可以跨设在第一子像素P1至第四子像素P4中。例如，第一扫描信号线G1和第二扫描信号线G2可以平行设置。第一扫描信号线Gn位于子像素的上侧，第二扫描信号线Sn位于子像素的下侧，
在一种示例性实施例中，第一扫描信号线G1和第二扫描信号线G2可以为等宽度设置。
在一种示例性实施例中，第一扫描信号线G1和第二扫描信号线G2可以相对于垂直轴(例如，后续形成的补偿信号线Sense)镜像对称设置。
在一种示例性实施例中，如图7C所示，第一栅电极12可以设置在每一个子像素中，作为第一晶体管T1的栅电极。在每一个子像素中，第一栅电极12在基底上的正投影与第一有源层11在基底上的正投影存在交叠区域。例如，第一栅电极12与第一扫描信号线G1可以为相互连接的一体结构。
在一种示例性实施例中，如图7C所示，第二栅电极22可以设置在每一个子像素中，作为第二晶体管T2的栅电极。第二栅电极22在基底上的正投影与第二有源层21在基底上的正投影存在交叠区域，且与第二极板42在基底上的正投影存在交叠区域。
在一种示例性实施例中，如图7C所示，第三栅电极32可以设置在每一个子像素中，作为第三晶体管T3的栅电极。第三栅电极32在基底上的正投影与第三有源层31基底上的正投影存在交叠区域。例如，第三栅电极32与第二扫描信号线G2可以为相互连接的一体结构。
在一种示例性实施例中，如图7C所示，电源连接线52可以为主体部分沿着第二方向DR2延伸的条形结构，电源连接线52可以包括：沿着第二方向DR2延伸的第一连接条和沿着第一方向DR1延伸的第二连接条。例如，电源连接线52的第一连接条被配置为通过后续形成的过孔与后续形成的第一电源线VDD连接，电源连接线52的第二连接条被配置为通过后续形成的过孔与后续形成的第三连接电极23连接，如此，一方面可以形成双层走线，保证电源信号传输的可靠性，并降低第一电源线VDD的电阻，另一方面， 可以使第三连接电极23与第三连接电极23。
在一种示例性实施例中，如图7C所示，辅助电源线53可以为沿着第二方向DR2延伸的条形结构。例如，辅助电源线53被配置为与后续形成的第二电源线VSS连接，形成双层走线，保证电源信号传输的可靠性，并降低第二电源线VSS的电阻。例如，辅助电源线53的主体部分和电源连接线52的主体部分(即第一连接条)可以相对于垂直轴(例如，后续形成的补偿信号线Sense)镜像对称设置。例如，电源连接线52的主体部分和辅助电源线53的主体部分可以平行设置。
在一种示例性实施例中，第二绝缘层62图案与第二导电层图案相同，即第二绝缘层62位于第二导电层的下方，第二导电层以外区域没有第二绝缘层62。
在一种示例性实施例中，第三子像素P3与第四子像素P4中的第一栅电极12、第二栅电极22和第三栅电极32相对于垂直轴镜像对称，第一子像素P1与第二子像素P2中的第一栅电极12、第二栅电极22和第三栅电极32相对于垂直轴镜像对称。
在一种示例性实施例中，本次工艺还可以包括导体化处理。其中，导体化处理是在形成第二导电层图案后，利用第一栅电极12、第二栅电极22和第三栅电极32作为遮挡进行等离子体处理，被第一栅电极12、第二栅电极22和第三栅电极32遮挡区域的半导体层(即半导体层与第一栅电极12、第二栅电极22和第三栅电极32重叠的区域)作为晶体管的沟道区域，未被第二金属层遮挡区域的半导体层被处理成导体化层，形成导体化的第二极板42和导体化的源漏区域(即位于晶体管的沟道区域两侧的晶体管的第一区和晶体管的第二区)。
在一种示例性实施例中，如图7B至图7E所示，所述第一晶体管T1和所述第三晶体管T2位于所述第二晶体管T2的第二方向的两侧，且所述第一晶体管T1、所述第二晶体管T2和所述第三晶体管T3的沟道区域的延伸方向均为第二方向。其中，在图7B至图7E中，晶体管的沟道区域的延伸方向采用点划线表示。例如，第一晶体管T1的沟道区域的延伸方向可以是指第一晶体管T1的第一极与第一晶体管T2的第二极之间的连接线的延伸方向。
在一种示例性实施例中，如图7B至图7E所示，存储电容C位于所述第二晶体管T1和所述第三晶体管T3之间，且所述存储电容C的延伸方向为第二方向。
在一种示例性实施例中，如图7B至图7E所示，四个子像素的像素驱动电路沿第一方向DR1并排设置。
本次构图工艺后，第二导电层图案形成在像素区域100，透明区域200包括基底10以及设置在基底10上的第一绝缘层61。
(4)形成第三绝缘层。
在一种示例性实施例中，形成第三绝缘层可以包括：在形成前述结构的基底上，沉积第三绝缘薄膜，通过构图工艺对第三绝缘薄膜进行构图，形成覆盖前述结构的第三绝缘层63图案。例如，第三绝缘层可以称为层间介质(ILD)层。
在一种示例性实施例中，如图7D所示，第三绝缘层63上设置有多个过孔，多个过孔可以包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十过孔V10、第十一过孔V11和第十二过孔V12。
在一种示例性实施例中，如图7D所示，第一过孔V1和第二过孔V2可以设置在每一个子像素，例如，第一过孔V1和第二过孔V2可以设置在每一个子像素的第一栅电极12两侧。针对每一个子像素，第一过孔V1在基底上的正投影位于本子像素中的第一有源层11的第一区在基底上的正投影的范围之内，第二过孔V2在基底上的正投影位于本子像素中的第一有源层11的第二区在基底上的正投影的范围之内。在一种示例性实施例中，第一过孔V1和第二过孔V2内的第三绝缘层63被刻蚀掉，暴露出第一有源层11两端的表面。第一过孔V1被配置为使后续形成的第一晶体管T1的第一极通过该过孔同时与第一有源层11的第一区和后续形成的数据信号线Data连接，第二过孔V2被配置为使后续形成的第一晶体管T1的第二极通过该过孔与第一有源层11的第二区连接。
在一种示例性实施例中，如图7D所示，第三过孔V3和第四过孔V4可 以设置在每一个子像素，例如，第三过孔V3和第四过孔V4可以设置在每一个子像素的第二栅电极22两侧。针对每一个子像素，第三过孔V3在基底上的正投影与本子像素中的第二有源层21的第一区在基底上的正投影存在交叠区域且与电源连接线52的第二连接条在基底上的正投影存在交叠区域，第四过孔V4在基底上的正投影位于本子像素中的第二有源层21的第二区在基底上的正投影的范围之内。在一种示例性实施例中，第三过孔V3为转接过孔，转接过孔由两个半孔组成，一个半孔形成在第二有源层21上，另一个半孔形成在电源连接线52的第二连接条上，两个半孔内的第三绝缘层63被刻蚀掉，使得两个半孔组成的转接过孔同时暴露出第二有源层21的表面和电源连接线52的第二连接条的表面。第四过孔V4内的第三绝缘层63被刻蚀掉，暴露出第二有源层21的表面。第三过孔V3被配置为使后续形成的第二晶体管T2的第一极通过该过孔同时与第二有源层21的第一区和电源连接线52的第二连接条连接，以便实现第二晶体管T2的第一极与后续形成的第一电源线VDD连接。第四过孔V4被配置为使后续形成的第二晶体管T2的第二极通过该过孔与第二有源层21的第二区连接。
在一种示例性实施例中，如图7D所示，第五过孔V5和第六过孔V6可以设置在每一个子像素，例如，第五过孔V5和第六过孔V6可以设置在每一个子像素的第三栅电极32两侧。针对每一个子像素，第五过孔V5在基底上的正投影位于本子像素中的第三有源层31的第一区在基底上的正投影的范围之内，第六过孔V6在基底上的正投影位于本子像素中的第三有源层31的第二区在基底上的正投影的范围之内。在一种示例性实施例中，第五过孔V5和第六过孔V6内的第三绝缘层63被刻蚀掉，暴露出第三有源层31两端的表面。第五过孔V5被配置为使后续形成的第三晶体管T3的第一极通过该过孔与第三有源层31的第一区连接。第六过孔V6被配置为使后续形成的第三晶体管T3的第二极通过该过孔与第三有源层31的第二区连接。
在一种示例性实施例中，如图7D所示，第七过孔V7可以设置在每一个子像素。第七过孔V7在基底上的正投影位于补偿连接线51在基底上的正投影的范围之内。第七过孔V7内的第一绝缘层61和第三绝缘层63被刻蚀掉，暴露出补偿连接线51的表面。第七过孔V7被配置为使后续形成的第三晶体 管T3的第一极通过该过孔与补偿连接线51连接，以便与补偿信号线Sense连接。
在一种示例性实施例中，如图7D所示，每一个子像素中可以设置第八过孔V8和第九过孔V9中的任意一种。第八过孔V8位于第二极板42与第三有源层31之间的间隔44所在位置，第九过孔V9位于第二极板42中的开口45所在位置。第八过孔V8在基底上的正投影位于第一极板41在基底上的正投影的范围之内，且与第二极板42在基底上的正投影不交叠。第九过孔V9在基底上的正投影位于第一极板41在基底上的正投影的范围之内，且与第二极板42在基底上的正投影不交叠。第八过孔V8和第九过孔V9内的第一绝缘层61和第三绝缘层63被刻蚀掉，暴露出第一极板41的表面。第八过孔V8被配置为使后续形成的第三极板43通过该过孔与第一极板41连接，第九过孔V9被配置为使后续形成的第三极板43通过该过孔与第一极板41连接。例如，第八过孔V8可以位于第一子像素P1和第二子像素P2中，第九过孔V9可以位于第三子像素P3和第四子像素P4中。例如，在同一个子像素中，多个第九过孔V9间隔设置。
在一种示例性实施例中，如图7D所示，第十过孔V10为转接过孔，转接过孔可以由两个半孔组成，一个半孔形成在第二栅电极22上，另一个半孔形成在第二极板42上，两个半孔内的第三绝缘层63被刻蚀掉，使得两个半孔组成的转接过孔同时暴露出第二栅电极22的表面和第二极板42的表面。第十过孔V10被配置为使后续形成的第一晶体管T1的第二极通过该过孔同时与第二栅电极22和第二极板42连接。
在一种示例性实施例中，如图7D所示，第十一过孔V11在基底上的正投影位于电源连接线52的第一连接条在基底上的正投影的范围之内。第十一过孔V11内的第三绝缘层63被刻蚀掉，暴露出电源连接线52的第一连接条的表面。第十一过孔V11被配置为使后续形成的第一电源线VDD通过该过孔与电源连接线52连接。例如，多个第十一过孔V11沿着第二方向DR2间隔设置，以增加第一电源线VDD与电源连接线52的连接可靠性。
在一种示例性实施例中，如图7D所示，第十二过孔V12在基底上的正投影位于辅助电源线53在基底上的正投影的范围之内。第十二过孔V12内 的第三绝缘层63被刻蚀掉，暴露出辅助电源线53的表面。第十二过孔V12被配置为使后续形成的第二电源线VSS通过该过孔与辅助电源线53连接。多个第十二过孔V12沿着第二方向DR2间隔设置，以增加第二电源线VSS与辅助电源线53的连接可靠性。
在一种示例性实施例中，第三绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。
本次构图工艺后，多个过孔图案形成在像素区域100，透明区域200包括在基底10上叠设的第一绝缘层61和第三绝缘层63。
(5)形成第三导电层。
在一种示例性实施例中，形成第三导电层可以包括：在形成前述结构的基底上，沉积第三导电薄膜，通过构图工艺对第三导电薄膜进行构图，在第三绝缘层63上形成第三导电层图案。例如，第三导电层可以称为源漏金属(SD)层。
在一种示例性实施例中，第三导电层可以采用金属材料形成。例如，金属材料可以包括但不限于：银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或者上述列出的金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)等。第三导电层可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
在一种示例性实施例中，如图7E所示，第三导电层可以包括：形成在每一个像素单元中的一条第一电源线VDD、一条第二电源线VSS、一条补偿信号线Sense和四条数据信号线Data，还可以包括：形成在每一个子像素中的第一连接电极13、第二连接电极14、第三连接电极23、第四连接电极24、第五连接电极33、第六连接电极34和第三极板43。
在一种示例性实施例中，如图7E所示，第一电源线VDD沿着第二方向DR2延伸。针对每一个像素单元，第一电源线VDD设置在远离透明区域200的一侧。第一电源线VDD被配置为通过多个第十一过孔V11与电源连接线52连接，使得第一电源线VDD通过电源连接线52分别与本像素单元中的每 一个子像素的第三连接电极23连接，在第一栅电极12与第三栅电极32之间形成双层走线，保证了电源信号传输的可靠性，并降低了第一电源线VDD的电阻。双层走线包括第二金属层的电源连接线52和第三金属层的第一电源线VDD。
如此，本公开示例性实施例通过设置一条第一电源线VDD和一条电源连接线52，实现了将电源信号分别写入四个子像素的第二晶体管T2。其中，第一电源线VDD沿着第二方向DR2延伸，电源连接线52包括沿着第二方向DR2延伸的第一连接条和沿着第一方向DR1延伸的第二连接条，第一电源线VDD通过第二连接条与第二晶体管T2连接。
在一种示例性实施例中，如图7E所示，第二电源线VSS沿着第二方向DR2延伸。针对每一个像素单元，第二电源线VSS设置在邻近透明区域200的一侧。第二电源线VSS被配置为通过多个第十二过孔V12与辅助电源线53连接，在第一栅电极12与第三栅电极32之间形成双层走线，双层走线包括第二金属层的辅助电源线53和第三金属层的第二电源线VSS。如此，可以保证电源信号传输的可靠性，并降低第二电源线VSS的电阻。
在一种示例性实施例中，如图7E所示，在平行于第一扫描信号线G1和第二扫描信号线G2方向(即第一方向DR1)，第一电源线VDD的宽度和第二电源线VSS的宽度均大于补偿信号线Sense的宽度，第一电源线VDD的宽度和第二电源线VSS的宽度均大于数据信号线Data的宽度。如此，可以降低第一电源线VDD和第二电源线VSS的电阻。
在一种示例性实施例中，如图7E所示，针对每一个像素单元，补偿信号线Sense设置在第一电源线VDD和第二电源线VSS之间，例如，补偿信号线Sense可以设置在第一子像素P1和第二子像素P2之间。
在一种示例性实施例中，如图7E所示，补偿信号线Sense的主体部分沿着第二方向DR2延伸。针对每一个像素单元，补偿信号线Sense上可以设置有第一凸出部(例如，位于第二子像素P2中的第五连接电极33)，第一凸出部的第一端通过本子像素内的第七过孔V7与补偿连接线51连接，使得补偿信号线Sense与补偿连接线51连接，第一凸出部的第二端通过本子像素内的第五过孔V5与本子像素中的第三有源层31的第一区连接，第一凸出部的 第三端与补偿信号线Sense连接。如此，一方面，第一凸出部可以作为第二子像素P2中的第三晶体管T3的第一极，实现将补偿信号线Sense提供的补偿信号写入位于第二子像素P2中的第三晶体管T3；另一方面，第一凸出部可以将补偿信号线Sense提供的补偿信号传输给跨接在四个子像素中的补偿连接线51，并且，由于补偿连接线51通过其它子像素内的第七过孔V7与其它子像素内的第五连接电极33连接，使得补偿连接线51可以将补偿信号传输至其它子像素内的第三晶体管T3，即补偿信号线Sense可以通过补偿连接线51将补偿信号写入其它子像素内的第三晶体管T3。
如此，本公开示例性实施例通过设置一条主体部分沿着第二方向DR2延伸的补偿信号线Sense和一条沿着第一方向DR1延伸的补偿连接线51，可以实现将补偿信号分别写入像素单元中的四个子像素的第三晶体管T3。其中，如图7E所示，补偿信号线Sense与第二子像素P2中的第三晶体管T3直接连接，补偿信号线Sense通过补偿连接线51分别与其它子像素中的第三晶体管T3连接。本公开示例性实施例通过在每一个像素单元的像素区域100的中部设置一条补偿信号线向四个子像素提供补偿信号，可以保证补偿信号在写入晶体管前RC延迟基本上相同，保证了显示均一性。
在一种示例性实施例中，如图7E所示，数据信号线Data可以设置在每一个子像素。数据信号线D的主体部分沿着第二方向DR2延伸。针对每一个子像素，数据信号线Data上可以设置有第二凸出部(即第一连接电极13)，第二凸出部的一端与数据信号线Data连接，第二凸出部的另一端通过本子像素内的第一过孔V1与第一有源层11的第一区连接，如此，第二凸出部可以作为第一晶体管T1的第一极，实现将数据信号写入第一晶体管T1。
在一种示例性实施例中，如图7E所示，针对每一个像素单元，两条数据信号线Data可以设置在第二电源线VSS和补偿信号线Sense之间，另外两条数据信号线Data可以设置在第一电源线VDD和补偿信号线Sense之间。
如此，本公开示例性实施例通过设置四条主体部分沿着第二方向DR2延伸的数据信号线Data，可以实现将数据信号分别写入四个子像素的第一晶体管T1。
在一种示例性实施例中，如图7E所示，第一电源线VDD、第二电源线 VSS、补偿信号线Sense和数据信号线Data的主体部分可以平行设置。
在一种示例性实施例中，如图7E所示，第一连接电极13，可以分别设置在每一个子像素，可以作为第一晶体管T1的第一极。针对每一个子像素，第一连接电极13与数据信号线Data为相互连接的一体结构，使得每一条数据信号线Data与所在子像素的第一连接电极13连接，其中，第一连接电极13的一端与数据信号线Data直接连接，第一连接电极13的另一端通过本子像素内的第一过孔V1与第一有源层11的第一区连接。例如，第一连接电极13可以为沿第一方向DR1延伸的条状结构。
在一种示例性实施例中，如图7E所示，第二连接电极14，可以分别设置在每一个子像素，可以作为第一晶体管T1的第二极，针对每一个子像素，第二连接电极14的一端通过第二过孔V2与第一有源层11的第二区连接，第二连接电极14的另一端通过第十过孔V10同时与第二栅电极22和第二极板42连接，如此，可以实现第二连接电极14、第二栅电极22和第二极板42具有相同的电位。例如，第二连接电极14可以为沿第二方向DR2延伸的条状结构。
在一种示例性实施例中，如图7E所示，第三连接电极23，可以分别设置在每一个子像素，可以作为第二晶体管T2的第一极。针对每一个子像素，第三连接电极23通过第三过孔V3同时与电源连接线52的第二连接条和第二有源层21的第一区连接，如此，由于电源连接线52与第一电源线VDD连接，因而，可以实现第三连接电极23与第一电源线VDD的连接，第三连接电极23可以将电源信号写入第二晶体管T2。例如，第三连接电极23可以为沿着第二方向DR2延伸的条形状。
在一种示例性实施例中，如图7E所示，第四连接电极24，可以分别设置在每一个子像素，可以作为第二晶体管T2的第二极。针对每一个子像素，第四连接电极24通过第四过孔V4与第二有源层21的第二区连接。
在一种示例性实施例中，如图7E所示，第五连接电极33，可以分别设置在每一个子像素，可以作为第三晶体管T3的第一极。例如，第二子像素P2中的第五连接电极33的第一端通过本子像素内的第七过孔V7与补偿连接线51连接，使得补偿信号线Sense与补偿连接线51连接，第二子像素P2 中的第五连接电极33的第二端通过本子像素内的第五过孔V5与本子像素中的第三有源层31的第一区连接，第二子像素P2中的第五连接电极33的第三端与补偿信号线Sense连接，如此，第二子像素P2中的第五连接电极33可以作为第二子像素P2中的第三晶体管T3的第一极，实现将补偿信号线Sense提供的补偿信号写入位于第二子像素P2中的第三晶体管T3和传输给跨接在四个子像素中的补偿连接线51。其它子像素(如，第一子像素P1、第三子像素P3和第四子像素P4)中的第五连接电极33通过本子像素内的第五过孔V5与本子像素中的第三有源层31的第一区连接，同时通过本子像素内的第七过孔V7与补偿连接线51连接，如此，由于补偿连接线51与补偿信号线Sense连接，因此，可以实现其它子像素中的第五连接电极33与补偿信号线Sense的连接，即可以实现补偿连接线51将补偿信号传输至其它子像素内的第三晶体管T3。
在一种示例性实施例中，如图7E所示，第六连接电极34，可以分别设置在每一个子像素，可以作为第三晶体管T3的第二极。针对每一个子像素，第六连接电极34通过第六过孔V6与第三有源层31的第二区连接。
在一种示例性实施例中，如图7E所示，第三极板43在基底10上的正投影与第二极板42在基底10上的正投影存在交叠区域，第三极板43与第二极板42形成第二存储电容Cst2。
在一种示例性实施例中，如图7E所示，第四连接电极24、第六连接电极34和第三极板43可以为相互连接的一体结构，如此，由于第三极板43通过第八过孔V8和第九过孔V9中的一种与第一极板41连接，因而，第四连接电极24同时与第一极板41和第三极板43连接，第六连接电极34同时与第一极板41和第三极板43连接，可以实现第四连接电极24、第六连接电极34、第一极板41和第三极板43具有相同的电位。
在一种示例性实施例中，如图7E所示，第一子像素P1与第二子像素P2中的第一连接电极13、第二连接电极14、第三连接电极23、第四连接电极24、第五连接电极33、第六连接电极34和第三极板43相对于垂直轴(例如，补偿信号线Sense)镜像对称，第三子像素P3与第四子像素P4中的第一连接电极13、第二连接电极14、第三连接电极23、第四连接电极24、第五连 接电极33、第六连接电极34和第三极板43相对于垂直轴(例如，补偿信号线Sense)镜像对称。
本次构图工艺后，第三导电层图案形成在像素区域100，透明区域200包括在基底10上叠设的第一绝缘层61和第三绝缘层63。
(6)形成第四绝缘层和第五绝缘层。
在一种示例性实施例中，在形成前述结构的基底上，沉积第四绝缘薄膜和第五绝缘薄膜，通过构图工艺对第四绝缘薄膜和第五绝缘薄膜进行构图，形成覆盖前述结构的第四绝缘层64以及设置在第四绝缘层64上的第五绝缘层65。例如，钝化(Passivation，PVX)层。例如，第五绝缘层可以称为平坦(PLN)层或者树脂(Resin)层。
在一种示例性实施例中，如图7F所示，第四绝缘层64和第五绝缘层65上开设有多个过孔，多个过孔可以包括：位于像素区域100中的第十三过孔V13和第十四过孔V14。
在一种示例性实施例中，如图7F所示，每一个子像素中可以设置第十三过孔V13和第十四过孔V14中的任意一种。例如，在第一子像素P1和第二子像素P2，第十三过孔V13位于第二极板42与第三有源层31之间的间隔44所在位置。又例如，在第三子像素P3和第四子像素P4，第十四过孔V14位于第二极板42中的开口45所在位置。
在一种示例性实施例中，如图7F所示，第十三过孔V13在基底上的正投影位于第三极板43在基底上的正投影的范围之内，且与第二极板42在基底上的正投影不交叠。第十四过孔V14在基底上的正投影位于第三极板43在基底上的正投影的范围之内，且与第二极板42在基底上的正投影不交叠。第十三过孔V13和第十四过孔V14内的第四绝缘层64和第五绝缘层65被刻蚀掉，暴露出第三极板43的表面。第十三过孔V13和第十四过孔V14被配置为使后续形成的第一阳极层701通过该过孔与第三极板43连接，如此，由于第三极板43同时与第一极板41、第四连接电极24和第六连接电极34连接，可以实现第一阳极层701与第一极板41、第二晶体管T2和第三晶体管T3连接。
在一种示例性实施例中，第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。
在一种示例性实施例中，第五绝缘层可以采用有机材料，例如，树脂(Resin)等。
本次构图工艺后，透明区域200包括在基底10上叠设的第一绝缘层61、、第三绝缘层63和第四绝缘层64。
(7)形成第四导电层。
在一种示例性实施例中，在形成前述结构的基底上，沉积第四导电薄膜，通过构图工艺对第四导电薄膜进行构图，形成第四导电层图案。
在一种示例性实施例中，第四导电层可以采用透明导电材料形成。例如，第四导电层可以采用氧化铟锡(ITO)或氧化铟锌(IZO)形成。如此，不仅能够满足形成的第一阳极层具有良好的透光性，还使得第一阳极层能够实现良好的导电性能。例如，以第四导电层采用ITO形成为例，第四导电层可以称为ITO1层。
在一种示例性实施例中，如图7G所示，第四导电层可以包括：位于每一个像素单元中的第一阳极层701。每一个像素单元中的第一阳极层701可以包括：第一阳极701R、第二阳极701G、第三阳极701B和第四阳极701W。其中，第一阳极701R、第二阳极701G和第三阳极701B形成在像素区域100。第四阳极701W形成在本像素单元中的像素区域100和相邻像素单元中的透明区域200。
在一种示例性实施例中，如图3和图7G所示，第一阳极701R可以作为第一子像素P1的第一阳极层，设置于像素区域100中的第一子区101-1。例如，第一阳极701R被配置为通过第一子像素P1中的第十三过孔V13与第三极板43连接，如此，由于第一子像素P1中的第三极板43、第二晶体管T2的第二极、第三晶体管T3的第二极是相互连接的一体结构，因此，可以实现第一阳极701R与存储电容C、第二晶体管T2的第二极、第三晶体管T3的第二极连接。
在一种示例性实施例中，如图3和图7G所示，第二阳极701G可以作为第二子像素P2的第一阳极层，设置于像素区域100中的第二子区101-2。例如，第二阳极701G被配置为通过第二子像素P2中的第十三过孔V13与第三极板43连接，如此，由于第二子像素P2中的第三极板43、第二晶体管T2的第二极、第三晶体管T3的第二极是相互连接的一体结构，因此，可以实现第二阳极701G与存储电容C、第二晶体管T2的第二极、第三晶体管T3的第二极连接。
在一种示例性实施例中，如图3和图7G所示，第三阳极701B可以作为第三子像素P3的第一阳极层，设置于像素区域100中的第三子区102-1。例如，第三阳极701B被配置为通过第三子像素P3中的第十四过孔V14与第三极板43连接，如此，由于第三子像素P3中的第三极板43、第二晶体管T2的第二极、第三晶体管T3的第二极是相互连接的一体结构，因此，可以实现第三阳极701B与存储电容C、第二晶体管T2的第二极、第三晶体管T3的第二极连接。
在一种示例性实施例中，如图3和图7G所示，第四阳极701W可以包括：位于像素区域100的主体部和位于透明区域200的延伸部，可以作为第四子像素P4(即白色子像素)的第一阳极层。例如，第四阳极701W被配置为通过第四子像素P4中的第十四过孔V14与第三极板43连接，如此，由于第四子像素P4中的第三极板43、第二晶体管T2的第二极、第三晶体管T3的第二极是相互连接的一体结构，因此，可以实现第四阳极701W与存储电容C、第二晶体管T2的第二极、第三晶体管T3的第二极连接。
在一种示例性实施例中，如图3和图7G所示，主体部和延伸部可以位于相邻的两个像素单元中。例如，针对第一像素单元的第四子像素P4的第一阳极层，主体部位于第一像素单元中的第四子区102-2，延伸部位于第二像素单元中的第一透明子区201，如此，可以实现第一像素单元中的白色子像素区外扩至第二像素单元中的透明区域，可以提升开口率。
在一种示例性实施例中，如图7G所示，第一阳极701R、第二阳极701G和第三阳极701B可以为矩形状。第四阳极701W的形状可以为呈“L”字形。
本次构图工艺后，透明区域200包括：在基底10上叠设的第一绝缘层 61、第三绝缘层63和第四绝缘层64，以及第四子像素P4(即白色子像素)的第一阳极层中的延伸部。
(8)形成第五导电层。
在一种示例性实施例中，在形成前述结构的基底上，沉积第五导电薄膜，通过构图工艺对第五导电薄膜进行构图，形成第五导电层图案。
在一种示例性实施例中，第五导电层可以采用金属材料形成，或者可以采用金属材料和透明导电材料形成。例如，金属材料可以包括但不限于：银(Ag)、铝(Al)和钼(Mo)中的任意一种或多种。例如，透明导电材料可以包括但不限于：氧化铟锡(ITO)或者氧化铟锌(IZO)。例如，第五导电层可以是单层结构，或者多层复合结构。例如，如第五导电层可以是由铝(Al)和氧化铟锡(ITO)形成设置的层叠结构(如，Al/ITO)，或者，可以是由钼(Mo)和氧化铟锡(ITO)形成设置的层叠结构(如，Mo/ITO)等，如此，使得形成的第二阳极层具有良好的导电性能。例如，第五导电层可以称为ITO2层。这里，本公开实施例对此不做限定。
在一种示例性实施例中，如图7H所示，第五导电层可以包括：位于每一个像素单元中的第二阳极层702。每一个像素单元中的第二阳极层702可以包括：位于像素区域100中的第五阳极702R、第六阳极702G和第七阳极702B以及第八阳极702W。
在一种示例性实施例中，第五阳极702R在基底上的正投影与第一阳极701R在基底上的正投影重叠，第五阳极702R与第一阳极701R连接。第六阳极702G在基底上的正投影与第二阳极701G在基底上的正投影重叠，第六阳极702G与第二阳极701G连接。第七阳极702B在基底上的正投影与第三阳极701B在基底上的正投影重叠，第七阳极702B与第三阳极701B连接。第八阳极702W在基底上的正投影与第四阳极701W的主体部在基底上的正投影重叠，第八阳极702W与第四阳极701W的主体部连接。
在一种示例性实施例中，如图7H所示，第五阳极702R、第六阳极702G和第七阳极702B以及第八阳极702W的形状可以为矩形状。第五阳极702R上设置有开口。
本次构图工艺后，透明区域200包括：在基底10上叠设的第一绝缘层61、第三绝缘层63和第四绝缘层64，以及第四子像素P4(即白色子像素)的第一阳极层中的延伸部。
(9)形成像素定义层(Pixel Define Layer，PDL)。
在一种示例性实施例中，形成像素定义层可以包括：如图17A和图17B所示，在形成前述结构的基底上涂覆像素定义薄膜，采用图案化工艺对像素定义薄膜进行图案化，形成像素定义层71。其中，像素定义层71可以至少包括：位于每一个子像素中的像素开口。
在一种示例性实施例中，如图7I所示，像素定义层71可以包括：位于第一子像素P1中暴露出第五阳极702R的第一像素开口71R、位于第二子像素P2中暴露出第六阳极702G的第二像素开口71G、位于第三子像素P3中暴露出第七阳极702B的第三像素开口71B、以及位于第四子像素P4中暴露出第八阳极702W与第四阳极701W的第四像素开口71W。
在一种示例性实施例中，不同子像素的像素开口的形状和面积可以不同。本公开示例性实施例通过将四个子像素设计成不同开口率，可以适应不同子像素的透过率，使得四个子像素的发光器件可以在不同电流时出射相同亮度，最大限度地优化了四个子像素发光器件的寿命，保证了产品寿命。
在一种示例性实施例中，像素定义层可以采用聚酰亚胺(PI)、亚克力或者聚对苯二甲酸乙二醇酯(PET)等材料制成。这里，本公开实施例对此不做限定。
在一种示例性实施例中，在制备像素定义层之后，显示基板的制备流程还可以包括：形成有机发光层，有机发光层通过像素开口与第二阳极层连接；在有机发光层上形成阴极，阴极与有机发光层连接。
在一种示例性实施例中，有机发光层可以采用蒸镀或喷墨打印工艺制备形成。例如，有机发光层可以通过采用精细金属掩模版(Fine Metal Mask，FMM)蒸镀制备形成，或者采用开放式掩膜版(Open Mask)蒸镀制备形成等。
在一种示例性实施例中，阴极可以为公共电极，即多个发光器件可以共用一整面的阴极。
在一种示例性实施例中，阴极可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或多种，或采用上述金属中任意一种或多种制成的合金。
在一种示例性实施例中，显示基板的制备流程还可以包括：在形成前述图案的基础上形成封装层，封装层形成在像素区域100和透明区域200。像素区域100的封装层包括无机材料的第一封装层、有机材料的第二封装层和无机材料的第三封装层，第一封装层设置在阴极上，第二封装层设置在第一封装层上，第三封装层设置在第二封装层上，形成无机材料/有机材料/无机材料的叠层结构。透明区域200的封装层包括无机材料的第一封装层和无机材料的第三封装层，第一封装层设置在阴极上，第三封装层设置在第一封装层上，形成无机材料/无机材料的叠层结构。
如图3、图7A至图7J所示，本公开实施例所提供的显示基板可以包括：
基底10；
设置在基底10上的第一导电层，第一导电层可以包括第一极板41和补偿连接线51；
覆盖第一导电层的第一绝缘层61；
设置在第一绝缘层61上的半导体层，半导体层可以包括第一有源层11、第二有源层21、第三有源层31和第二极板42，第二极板42在基底10上的正投影与第一极板41在基底10上的正投影存在交叠区域，第二极板42与第一极板41形成第一存储电容Cst1；
覆盖半导体层的第二绝缘层62；
设置在第二绝缘层62上的第二导电层，第二导电层可以包括：第一扫描信号线G1、第二扫描信号线G2、电源连接线52和辅助电源线53、第一栅电极12、第二栅电极22和第三栅电极32，第一栅电极12与第一扫描信号线G1为相互连接的一体结构，第三栅电极32与第二扫描信号线G2为相互连 接的一体结构；
覆盖第二导电层的第三绝缘层63，第三绝缘层63开设多个过孔；
设置在第三绝缘层63上的第三导电层，第三导电层可以包括：第一电源线VDD、第二电源线VSS、补偿信号线Sense、数据信号线Data、第一连接电极13、第二连接电极14、第三连接电极23、第四连接电极24、第五连接电极33、第六连接电极34和第三极板43，第一连接电极13与数据信号线Data为相互连接的一体结构，第四连接电极24、第六连接电极34和第三极板43为相互连接的一体结构，第三极板43在基底10上的正投影与第二极板42在基底10上的正投影存在交叠区域，第二极板42与第三极板43形成第二存储电容Cst2；
覆盖第三导电层的第四绝缘层64和第五绝缘层65，第四绝缘层64和第五绝缘层65开设多个过孔；
设置在第四绝缘层64和第五绝缘层65上的第四导电层，第四导电层可以包括第一阳极层701，第一阳极层701可以包括：位于像素区域100中的第一阳极701R、第二阳极701G、第三阳极701B、以及位于像素区域100和透明区域200中的第四阳极701W(即白色子像素的第一阳极层)；
设置在第四导电层上的第五导电层，第五导电层可以包括：第二阳极层702，第二阳极层702可以包括：位于像素区域100中的第五阳极702R、第六阳极702G和第七阳极702B以及第八阳极702W；
设置在第五绝缘层65上的像素定义层71，像素定义层71开设有暴露第二阳极层702的像素开口；
设置在像素开口内的有机发光层，有机发光层与第二阳极层702连接；
设置在有机发光层上的阴极；
覆盖上述结构的封装层。
在一种示例性实施例中，如图7J所示，在垂直于显示基板的平面的方向(即第三方向DR3)上，像素单元的透明区域200中的第一透明子区201可以包括：基底10以及在基底10上依次叠设的第一绝缘层61、第三绝缘层63、 第四绝缘层64和第一阳极层701。像素单元的透明区域200中的第二透明子区202可以包括：基底10以及在基底10上依次叠设的第一绝缘层61、第三绝缘层63和第四绝缘层64。
由上述内容可知，本公开示例性实施例所提供的显示基板，通过设置本像素单元中的白色子像素的第一阳极层外扩至相邻像素单元中的透明区域的设计，可以提升开口率。
图8A至图8I为图4所示的显示基板制备过程的示意图，示意了显示基板的一个像素单元的版图结构，图8J为图8I所示的显示基板沿A-A’方向的剖面图。下面以图4所示显示基板的结构作参考，结合图8A至图8J，对本公开示例性实施例中提供的显示基板的制备过程进行说明。其中，图8A至图8I中，每一个像素单元包括像素区域100和透明区域200，每一个像素单元包括第一子像素P1、第二子像素P2、第三子像素P3和第四子像素P4，每一个子像素的像素驱动电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容C。在像素区域100中，沿第一方向DR1依次设置第四子像素P4、第一子像素P1、第二子像素P2和第三子像素P3的像素驱动电路。
在一种示例性实施例中，显示基板的制备过程可以包括以下步骤：
(1)形成第一导电层。例如，如图8A所示，第一导电层可以包括：第一极板41和跨设在四个子像素中的补偿连接线51。例如，在像素区域100中，第四子像素P4的第一极板41、第一子像素P1的第一极板41、第二子像素P2的第一极板41、第三子像素P3的第一极板41沿第一方向DR1依次设置。
(2)形成半导体层。例如，如图8B所示，半导体层可以包括：每一个子像素的第一有源层11、第二有源层21、第三有源层31和第二极板42。例如，第四子像素P4中的半导体层图案与第三子像素P3中的半导体层图案相对于垂直轴对称，第一子像素P1中的半导体层图案与第二子像素P2中的半导体层图案相对于垂直轴镜像对称。例如，第一子像素P1和第二子像素P2中的第二极板42与第三有源层31之间设置有间隔44，第三子像素P3和第四子像素P4的第二极板42中设置有开口45。
(3)形成第二导电层。例如，如图8C所示，第二导电层可以包括：第一扫描信号线G1、第二扫描信号线G2、电源连接线52和辅助电源线53，以及每一个子像素的第一栅电极12、第二栅电极22和第三栅电极32。例如，第三子像素P3与第四子像素P4中的第一栅电极12、第二栅电极22和第三栅电极32相对于垂直轴镜像对称，第一子像素P1与第二子像素P2中的第一栅电极12、第二栅电极22和第三栅电极32相对于垂直轴镜像对称。
(4)形成第三绝缘层。例如，如图8D所示，第三绝缘层63上设置有多个过孔，多个过孔可以包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十过孔V10、第十一过孔V11和第十二过孔V12。例如，第八过孔V8可以位于第一子像素P1和第二子像素P2中，第九过孔V9可以位于第三子像素P3和第四子像素P4中。
(5)形成第三导电层。如图8E所示，第三导电层可以包括：形成在每一个像素单元中的一条第一电源线VDD、一条第二电源线VSS、一条补偿信号线Sense和四条数据信号线Data，还可以包括：形成在每一个子像素中的第一连接电极13、第二连接电极14、第三连接电极23、第四连接电极24、第五连接电极33、第六连接电极34和第三极板43。例如，补偿信号线Sense可以设置在第一子像素P1和第二子像素P2之间。例如，第二子像素P2中的第五连接电极33的第一端通过本子像素内的第七过孔V7与补偿连接线51连接，使得补偿信号线Sense与补偿连接线51连接，第二子像素P2中的第五连接电极33的第二端通过本子像素内的第五过孔V5与本子像素中的第三有源层31的第一区连接，第二子像素P2中的第五连接电极33的第三端与补偿信号线Sense连接。第一子像素P1与第二子像素P2中的第一连接电极13、第二连接电极14、第三连接电极23、第四连接电极24、第五连接电极33、第六连接电极34和第三极板43相对于垂直轴(例如，补偿信号线Sense)镜像对称，第三子像素P3与第四子像素P4中的第一连接电极13、第二连接电极14、第三连接电极23、第四连接电极24、第五连接电极33、第六连接电极34和第三极板43相对于垂直轴(例如，补偿信号线Sense)镜像对称。
(6)形成第四绝缘层和第五绝缘层。例如，如图8F所示，第三导电层 可以包括：第四绝缘层64和第五绝缘层65上开设有多个过孔，多个过孔可以包括：位于像素区域100中的第十三过孔V13和第十四过孔V14。例如，在第一子像素P1和第二子像素P2，第十三过孔V13位于第二极板42与第三有源层31之间的间隔44所在位置。例如，在第三子像素P3和第四子像素P4，第十四过孔V14位于第二极板42中的开口45所在位置。
(7)形成第四导电层。例如，如图8G所示，第四导电层可以包括：位于每一个像素单元中的第一阳极层701。每一个像素单元中的第一阳极层701可以包括：第一阳极701R、第二阳极701G、第三阳极701B和第四阳极701W。其中，每一个第一阳极701R、第二阳极701G和第三阳极701B均形成在像素区域100。第四阳极701W包括：形成在本像素单元中的像素区域100和中的主体部和形成在本像素单元中的透明区域200中的延伸部。例如，在像素区域100中，第一阳极701R和第二阳极701G沿第一方向DR1依次设置，第四阳极701W的主体部和第三阳极701B沿第一方向DR1依次设置，第四阳极701W的主体部位于第一阳极701R的第二方向DR2一侧，第三阳极701B位于第二阳极701G的第二方向DR2一侧。如此，可以实现本像素单元中的白色子像素区外扩至本像素单元中的透明区域，可以提升开口率，而且不影响透明度。
(8)形成第五导电层。例如，如图8H所示，第五导电层可以包括：位于每一个像素单元中的第二阳极层702。每一个像素单元中的第二阳极层702可以包括：位于像素区域100中的第五阳极702R、第六阳极702G和第七阳极702B以及第八阳极702W。例如，在像素区域100中，第五阳极702R、第六阳极702G沿第一方向DR1依次设置，第八阳极702W和第七阳极702B沿第一方向DR1依次设置，第八阳极702W位于第五阳极702R的第二方向DR2一侧，第七阳极702B位于第六阳极702G的第二方向DR2一侧。
(9)形成像素定义层。如图8I所示，像素定义层71可以包括：位于第一子像素P1中暴露出第五阳极702R的第一像素开口71R、位于第二子像素P2中暴露出第六阳极702G的第二像素开口71G、位于第三子像素P3中暴露出第七阳极702B的第三像素开口71B、以及位于第四子像素P4中暴露出第八阳极702W与第四阳极701W的第四像素开口71W。
在一种示例性实施例中，如图8J所示，在垂直于显示基板的平面的方向(即第三方向DR3)上，像素单元的透明区域200中的第一透明子区201可以包括：基底10以及在基底10上依次叠设的第一绝缘层61、第三绝缘层63和第四绝缘层64。像素单元的透明区域200中的第二透明子区202可以包括：基底10以及在基底10上依次叠设的第一绝缘层61、第三绝缘层63、第四绝缘层64和第一阳极层701。如此，实现将本像素单元中的白色子像素的第一阳极层外扩至本像素单元中的第二透明子区202。
以上图8A至图8J所示显示基板的制备方法的描述，与前述实施例的描述是类似的，具有相似的有益效果。对于本实施例中未披露的技术细节，本领域的技术人员请参照上述图7A至图7J所示显示基板的描述而理解，这里不再赘述。
由上述内容可知，本公开示例性实施例所提供的显示基板，通过设置本像素单元中的白色子像素的第一阳极层外扩至本像素单元中的透明区域的设计，可以在不减小透明区域的面积的前提下，实现增大像素区域，使像素开口率有一定程度的提升，从而，可以提升显示效果。而且，由于第一阳极层采用透明导电材料形成，可以实现在提升显示效果的同时不影响透明效果。
图9A至图9I为图5所示的显示基板制备过程的示意图，示意了显示基板的一个像素单元的版图结构，图9J为图9I所示的显示基板沿A-A’方向的剖面图。下面以图5所示显示基板的结构作参考，结合图9A至图9J，对本公开示例性实施例中提供的显示基板的制备过程进行说明。其中，图9A至图9I中，每一个像素单元可以包括：沿第一方向DR1依次设置的透明区域200和像素区域100，每一个像素单元包括：第一子像素P1、第二子像素P2、第三子像素P3和第四子像素P4，每一个子像素的像素驱动电路包括：第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容C。在像素区域100中，沿第一方向DR1依次设置第一子像素P1、第二子像素P2、第三子像素P3和第四子像素P4的像素驱动电路。
在一种示例性实施例中，显示基板的制备过程可以包括以下步骤：
(1)形成第一导电层。例如，如图9A所示，第一导电层可以包括：位于像素区域100中的第一极板41和跨设在四个子像素中的补偿连接线51。 例如，在像素区域100中，第一子像素P1的第一极板41、第二子像素P2的第一极板41、第三子像素P3的第一极板41和第四子像素P4的第一极板41沿第一方向DR1依次设置。
(2)形成半导体层。例如，如图9B所示，半导体层可以包括：位于像素区域100中的每一个子像素的第一有源层11、第二有源层21、第三有源层31和第二极板42。例如，第二子像素P2与第三子像素P3中的第一有源层11、第二有源层21和第三有源层31相对于垂直轴对称。例如，第一子像素P1与第四子像素P4中的第一有源层11和第二有源层21相对于垂直轴对称。例如，第一子像素P1中的第二极板42与第三有源层31之间设置有间隔44，第二子像素P2、第三子像素P3和第四子像素P4的第二极板42中设置有开口45。
(3)形成第二导电层。例如，如图9C所示，第二导电层可以包括：第一扫描信号线G1、第二扫描信号线G2、电源连接线52和辅助电源线53，以及每一个子像素的第一栅电极12、第二栅电极22和第三栅电极32。例如，第一子像素P1与第四子像素P4中的第一栅电极12、第二栅电极22和第三栅电极32相对于垂直轴镜像对称，第二子像素P2与第三子像素P3中的第一栅电极12、第二栅电极22和第三栅电极32相对于垂直轴镜像对称。
(4)形成第三绝缘层。例如，如图9D所示，第三绝缘层63上设置有多个过孔，多个过孔可以包括：位于像素区域100中的第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十过孔V10、第十一过孔V11和第十二过孔V12。例如，第八过孔V8可以位于第一子像素P1中，第九过孔V9可以位于第二子像素P2、第三子像素P3和第四子像素P4中。
(5)形成第三导电层。如图9E所示，第三导电层可以包括：形成在每一个像素单元中的一条第一电源线VDD、一条第二电源线VSS、一条补偿信号线Sense和四条数据信号线Data，还可以包括：位于像素区域100中的每一个子像素中的第一连接电极13、第二连接电极14、第三连接电极23、第四连接电极24、第五连接电极33、第六连接电极34和第三极板43。例如，补偿信号线Sense可以设置在第二子像素P2和第三子像素P3之间。例如， 第三子像素P3中的第五连接电极33的第一端通过本子像素内的第七过孔V7与补偿连接线51连接，使得补偿信号线Sense与补偿连接线51连接，第三子像素P3中的第五连接电极33的第二端通过本子像素内的第五过孔V5与本子像素中的第三有源层31的第一区连接，第三子像素P3中的第五连接电极33的第三端与补偿信号线Sense连接。第二子像素P2与第三子像素P3中的第一连接电极13、第二连接电极14、第三连接电极23、第四连接电极24、第五连接电极33、第六连接电极34和第三极板43相对于垂直轴(例如，补偿信号线Sense)镜像对称，第一子像素P1与第四子像素P4中的第一连接电极13、第二连接电极14、第三连接电极23、第四连接电极24、第五连接电极33、第六连接电极34和第三极板43相对于垂直轴(例如，补偿信号线Sense)镜像对称。
(6)形成第四绝缘层和第五绝缘层。例如，如图9F所示，第三导电层可以包括：第四绝缘层64和第五绝缘层65上开设有多个过孔，多个过孔可以包括：位于像素区域100中的第十三过孔V13和第十四过孔V14。例如，在第一子像素P1，第十三过孔V13位于第二极板42与第三有源层31之间的间隔44所在位置。例如，在第二子像素P2、第三子像素P3和第四子像素P4，第十四过孔V14位于第二极板42中的开口45所在位置。
(7)形成第四导电层。例如，如图9G所示，第四导电层可以包括：位于每一个像素单元中的第一阳极层701。每一个像素单元中的第一阳极层701可以包括：第一阳极701R、第二阳极701G、第三阳极701B和第四阳极701W。其中，第一阳极701R、第二阳极701G和第三阳极701B均形成在像素区域100。第四阳极701W包括：形成在本像素单元中的像素区域100中的主体部和形成在本像素单元中的透明区域200中的延伸部。例如，在像素区域100中，第一阳极701R、第二阳极701G、第三阳极701B以及第四阳极701W的主体部沿第二方向DR2依次设置。例如，第四阳极701W的延伸部位于第一阳极701R、第二阳极701G和第三阳极701B的第一方向DR1反方向一侧。如此，可以实现本像素单元中的白色子像素区外扩至本像素单元中的透明区域，可以提升开口率，而且不影响透明度。
(8)形成第五导电层。例如，如图9H所示，第五导电层可以包括：位 于每一个像素单元中的第二阳极层702。每一个像素单元中的第二阳极层702可以包括：位于像素区域100中的第五阳极702R、第六阳极702G和第七阳极702B以及第八阳极702W。例如，在像素区域100中，第五阳极702R、第六阳极702G、第七阳极702B以及第八阳极702W沿第二方向DR2依次设置。
(9)形成像素定义层。如图9I所示，像素定义层71可以包括：位于第一子像素P1中暴露出第五阳极702R的第一像素开口71R、位于第二子像素P2中暴露出第六阳极702G的第二像素开口71G、位于第三子像素P3中暴露出第七阳极702B的第三像素开口71B、以及位于第四子像素P4中暴露出第八阳极702W与第四阳极701W的第四像素开口71W。例如，在像素区域100中，第一像素开口71R、第二像素开口71G和第三像素开口71B沿第二方向DR2依次设置。
在一种示例性实施例中，如图9J所示，在垂直于显示基板的平面的方向(即第三方向DR3)上，像素单元的透明区域200中的第一透明子区201可以包括：基底10以及在基底10上依次叠设的第一绝缘层61、第三绝缘层63和第四绝缘层64。像素单元的透明区域200中的第二透明子区202可以包括：基底10以及在基底10上依次叠设的第一绝缘层61、第三绝缘层63、第四绝缘层64和第一阳极层701。如此，实现将本像素单元中的白色子像素的第一阳极层外扩至本像素单元中的第二透明子区202。
以上图9A至图9J所示显示基板的制备方法的描述，与前述实施例的描述是类似的，具有相似的有益效果。对于本实施例中未披露的技术细节，本领域的技术人员请参照上述图7A至图7J所示显示基板的描述而理解，这里不再赘述。
由上述内容可知，本公开示例性实施例所提供的显示基板，通过设置本像素单元中的白色子像素的第一阳极层外扩至本像素单元中的透明区域的设计，可以在不减小透明区域的面积的前提下，实现增大像素区域，使像素开口率有一定程度的提升，从而，可以提升显示效果。而且，由于第一阳极层采用透明导电材料形成，可以实现在提升显示效果的同时不影响透明效果。
图10A至图10I为图6所示的显示基板制备过程的示意图，示意了显示 基板的两个像素单元的版图结构，图10J为图10I所示的显示基板沿A-A’方向的剖面图。下面以图6所示显示基板的结构作参考，结合图10A至图10J，对本公开示例性实施例中提供的显示基板的制备过程进行说明。其中，图10A至图10I中，每一个像素单元包括像素区域100和透明区域200，每一个像素单元包括第一子像素P1、第二子像素P2、第三子像素P3和第四子像素P4，每一个子像素的像素驱动电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容C。在像素区域100中，沿第一方向DR1依次设置第一子像素P1、第二子像素P2、第三子像素P3和第四子像素P4的像素驱动电路。
在一种示例性实施例中，显示基板的制备过程可以包括以下步骤：
(1)形成第一导电层。例如，如图10A所示，第一导电层可以包括：位于像素区域100中的第一极板41和跨设在四个子像素中的补偿连接线51。例如，在像素区域100中，第一子像素P1的第一极板41、第二子像素P2的第一极板41、第三子像素P3的第一极板41和第四子像素P4的第一极板41沿第一方向DR1依次设置。
(2)形成半导体层。例如，如图10B所示，半导体层可以包括：位于像素区域100中的每一个子像素的第一有源层11、第二有源层21、第三有源层31和第二极板42。例如，第二子像素P2与第三子像素P3中的第一有源层11、第二有源层21和第三有源层31相对于垂直轴对称。例如，第一子像素P1与第四子像素P4中的第一有源层11和第二有源层21相对于垂直轴对称。例如，第一子像素P1中的第二极板42与第三有源层31之间设置有间隔44，第二子像素P2、第三子像素P3和第四子像素P4的第二极板42中设置有开口45。
(3)形成第二导电层。例如，如图10C所示，第二导电层可以包括：第一扫描信号线G1、第二扫描信号线G2、电源连接线52和辅助电源线53，以及每一个子像素的第一栅电极12、第二栅电极22和第三栅电极32。例如，第一子像素P1与第四子像素P4中的第一栅电极12、第二栅电极22和第三栅电极32相对于垂直轴镜像对称，第二子像素P2与第三子像素P3中的第一栅电极12、第二栅电极22和第三栅电极32相对于垂直轴镜像对称。
(4)形成第三绝缘层。例如，如图10D所示，第三绝缘层63上设置有多个过孔，多个过孔可以包括：位于像素区域100中的第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十过孔V10、第十一过孔V11和第十二过孔V12。例如，第八过孔V8可以位于第一子像素P1中，第九过孔V9可以位于第二子像素P2、第三子像素P3和第四子像素P4中。
(5)形成第三导电层。如图10E所示，第三导电层可以包括：形成在每一个像素单元中的一条第一电源线VDD、一条第二电源线VSS、一条补偿信号线Sense和四条数据信号线Data，还可以包括：位于像素区域100中的每一个子像素中的第一连接电极13、第二连接电极14、第三连接电极23、第四连接电极24、第五连接电极33、第六连接电极34和第三极板43。例如，补偿信号线Sense可以设置在第二子像素P2和第三子像素P3之间。例如，第三子像素P3中的第五连接电极33的第一端通过本子像素内的第七过孔V7与补偿连接线51连接，使得补偿信号线Sense与补偿连接线51连接，第三子像素P3中的第五连接电极33的第二端通过本子像素内的第五过孔V5与本子像素中的第三有源层31的第一区连接，第三子像素P3中的第五连接电极33的第三端与补偿信号线Sense连接。第二子像素P2与第三子像素P3中的第一连接电极13、第二连接电极14、第三连接电极23、第四连接电极24、第五连接电极33、第六连接电极34和第三极板43相对于垂直轴(例如，补偿信号线Sense)镜像对称，第一子像素P1与第四子像素P4中的第一连接电极13、第二连接电极14、第三连接电极23、第四连接电极24、第五连接电极33、第六连接电极34和第三极板43相对于垂直轴(例如，补偿信号线Sense)镜像对称。
(6)形成第四绝缘层和第五绝缘层。例如，如图10F所示，第三导电层可以包括：第四绝缘层64和第五绝缘层65上开设有多个过孔，多个过孔可以包括：位于像素区域100中的第十三过孔V13和第十四过孔V14。例如，第十三过孔V13设置在第一子像素P1中，位于第一子像素P1中的第二极板42与第三有源层31之间的间隔44所在位置。例如，第十四过孔V14分别设置在第二子像素P2、第三子像素P3和第四子像素P4中，第十四过孔V14 位于第二极板42中的开口45所在位置。
(7)形成第四导电层。例如，如图10G所示，第四导电层可以包括：位于每一个像素单元中的第一阳极层701。每一个像素单元中的第一阳极层701可以包括：第一阳极701R、第二阳极701G、第三阳极701B和第四阳极701W。其中，第一阳极701R、第二阳极701G和第三阳极701B均形成在像素区域100。第四阳极701W包括：形成在本像素单元(如，第一像素单元)中的像素区域100中的主体部和形成在相邻像素单元(如，第二像素单元)中的透明区域200中的延伸部。例如，在像素区域100中，第一阳极701R、第二阳极701G、第三阳极701B以及第四阳极701W的主体部沿第二方向DR2依次设置。例如，第一像素单元中第四阳极701W的延伸部位于第二像素单元的第一透明子区201，位于第一像素单元中第一阳极701R、第二阳极701G和第三阳极701B的第一方向DR1反方向一侧。如此，可以实现本像素单元中的白色子像素区外扩至相邻像素单元中的透明区域，可以提升开口率，而且不影响透明度。
(8)形成第五导电层。例如，如图10H所示，第五导电层可以包括：位于每一个像素单元中的第二阳极层702。每一个像素单元中的第二阳极层702可以包括：位于像素区域100中的第五阳极702R、第六阳极702G和第七阳极702B以及第八阳极702W。例如，在像素区域100中，第五阳极702R、第六阳极702G、第七阳极702B以及第八阳极702W沿第二方向DR2依次设置。
(9)形成像素定义层。如图10I所示，像素定义层71可以包括：位于第一子像素P1中暴露出第五阳极702R的第一像素开口71R、位于第二子像素P2中暴露出第六阳极702G的第二像素开口71G、位于第三子像素P3中暴露出第七阳极702B的第三像素开口71B、以及位于第四子像素P4中暴露出第八阳极702W与第四阳极701W的第四像素开口71W。例如，在像素区域100中，第一像素开口71R、第二像素开口71G和第三像素开口71B第二方向DR2依次设置。
在一种示例性实施例中，如图10J所示，在垂直于显示基板的平面的方向(即第三方向DR3)上，像素单元的透明区域200中的第一透明子区201 可以包括：基底10以及在基底10上依次叠设的第一绝缘层61、第三绝缘层63、第四绝缘层64和第一阳极层701。像素单元的透明区域200中的第二透明子区202可以包括：基底10以及在基底10上依次叠设的第一绝缘层61、第三绝缘层63和第四绝缘层64。如此，实现将本像素单元中的白色子像素的第一阳极层外扩至本像素单元中的第一透明子区201。
以上图10A至图10J所示显示基板的制备方法的描述，与前述实施例的描述是类似的，具有相似的有益效果。对于本实施例中未披露的技术细节，本领域的技术人员请参照上述图7A至图7J所示显示基板的描述而理解，这里不再赘述。
由上述内容可知，本公开示例性实施例所提供的显示基板，通过设置本像素单元中的白色子像素的第一阳极层外扩至相邻像素单元中的透明区域的设计，可以在不减小透明区域的面积的前提下，实现增大像素区域，使像素开口率有一定程度的提升，从而，可以提升显示效果。而且，由于第一阳极层采用透明导电材料形成，可以实现在提升显示效果的同时不影响透明效果。
以上所列出的多种显示基板的结构及其制备过程仅仅是示例性说明，本领域技术人员可以根据实际情况变更相应结构以及增加或减少图案化工艺。例如，四个子像素可以沿第一方向DR1并排设置等。又如，像素驱动电路可以采用5T1C或7T1C等结构。再如，膜层结构中还可以设置其它电极或引线。这里，本公开实施例对此不做限定。
本公开还提供了一种显示基板的制备方法，显示基板包括：多个像素单元，每一个像素单元包括：透明区域和像素区域，每一个像素单元包括：多个子像素；制备方法可以包括：在基底上形成驱动电路层；在驱动电路层远离基底一侧形成发光结构层，发光结构层可以包括：叠设的第一阳极层和第二阳极层，其中，多个子像素中的白色子像素的第二阳极层位于本像素单元的像素区域中；白色子像素的第一阳极层包括：位于本像素单元的像素区域中的主体部和位于本像素单元的透明区域的延伸部，或者，白色子像素的第一阳极层包括：位于本像素单元的像素区域中的主体部和位于相邻像素单元的透明区域的延伸部。
如此，本公开示例性实施例所制备的显示基板，通过将白色子像素的第一阳极层从像素区域延伸至透明区域，可以在不减小透明区域的面积的前提下，实现增大像素区域，使像素开口率有一定程度的提升，从而，可以提升显示效果。而且，由于第一阳极层通常采用透明导电材料形成，可以实现在提升显示效果的同时不影响透明效果。
以上制备方法实施例的描述，与上述显示基板实施例的描述是类似的，具有同显示基板实施例相似的有益效果。对于本公开制备方法实施例中未披露的技术细节，本领域的技术人员请参照本公开显示基板实施例中的描述而理解，这里不再赘述。
本公开示例性实施例还提供一种显示装置。该显示装置可以包括：上述一个或多个示例性实施例中的显示基板。
在一种示例性实施例中，显示基板可以包括但不限于：OLED显示基板或者量子点发光二极管(Quantum-dot Light Emitting Diodes，QLED)显示基板等。这里，本公开实施例对此不做限定。
在一种示例性实施例中，该显示装置可以包括但不限于：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或者导航仪等任何具有显示功能的产品或部件。这里，本公开实施例对显示装置的类型不做限定。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
以上显示装置实施例的描述，与上述显示基板实施例的描述是类似的，具有同显示基板实施例相似的有益效果。对于本公开显示装置实施例中未披露的技术细节，本领域的技术人员请参照本公开显示基板实施例中的描述而理解，这里不再赘述。
虽然本公开所揭露的实施方式如上，但上述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (21)

  1. 一种显示基板，包括：透明区域和像素区域，像素区域包括：多个发光器件，所述多个发光器件包括：第一发光器件，所述第一发光器件的第一阳极层在显示基板平面的正投影与所述透明区域在显示基板平面的正投影部分交叠，所述第一发光器件的第二阳极层在显示基板平面的正投影位于所述像素区域在显示基板平面的正投影的范围之内。
  2. 根据权利要求1所述的显示基板，其中，所述第一发光器件的发光层在显示基板平面的正投影，与所述透明区域在显示基板平面的正投影部分交叠，且与所述像素区域在显示基板平面的正投影部分交叠。
  3. 根据权利要求1所述的显示基板，其中，所述第一阳极层采用透明导电材料。
  4. 根据权利要求3所述的显示基板，其中，所述透明导电材料包括：氧化铟锡或者氧化铟锌。
  5. 根据权利要求1所述的显示基板，其中，所述第二阳极层采用金属材料形成，或者，采用金属材料和透明导电材料形成。
  6. 根据权利要求1所述的显示基板，其中，所述多个发光器件还包括：第二发光器件，所述第二发光器件的第一阳极层在显示基板平面的正投影、所述第二发光器件的第二阳极层在显示基板平面的正投影、以及所述第二发光器件的发光层在显示基板平面的正投影均位于所述像素区域在显示基板平面的正投影的范围之内。
  7. 根据权利要求6所述的显示基板，其中，所述多个发光器件包括：一个第一发光器件和三个第二发光器件，所述第一发光器件包括：白色发光器件，所述三个第二发光器件包括：一个红色发光器件、一个绿色发光器件和一个蓝色发光器件，所述蓝色发光器件的第二阳极层的面积大于所述红色发光器件的第二阳极层的面积和所述绿色发光器件的第二阳极层的面积，所述白色发光器件的第二阳极层的面积小于所述红色发光器件的第二阳极层的面积和所述绿色发光器件的第二阳极层的面积。
  8. 根据权利要求7所述的显示基板，其中，所述透明区域包括：沿第一 方向依次设置的第一透明子区和第二透明子区，所述像素区域包括：沿第二方向依次设置的第一区和第二区，第一区包括：沿第一方向依次设置的第一子区和第二子区，第二区包括：沿第一方向依次设置的第三子区和第四子区；所述一个第一发光器件的第一阳极层在显示基板平面的正投影，与第一子区至第四子区中的一个子区在显示基板平面的正投影至少部分交叠，且与第一透明子区和第二透明子区中的一个在显示基板平面的正投影至少部分交叠；所述三个第二发光器件的第一阳极层在显示基板平面的正投影，分别与第一子区至第四子区中的其它三个子区在显示基板平面的正投影至少部分交叠，且互不相同；第二方向与第一方向交叉。
  9. 根据权利要求8所述的显示基板，其中，所述蓝色发光器件的第二阳极层在显示基板平面的正投影的长度，大于所述红色发光器件的第二阳极层在显示基板平面的正投影的长度、所述绿色发光器件的第二阳极层在显示基板平面的正投影的长度、以及所述白色发光器件的第二阳极层在显示基板平面的正投影的长度，长度是指沿第一方向的尺寸特征。
  10. 根据权利要求7所述的显示基板，其中，所述透明区域包括：沿第一方向依次设置的第一透明子区和第二透明子区，所述像素区域包括：沿第二方向依次设置的第一区和第二区，第一区包括：沿第二方向依次设置的第五子区和第六子区，第二区包括：沿第二方向依次设置的第七子区和第八子区；所述一个第一发光器件的第一阳极层在显示基板平面的正投影，与第五子区至第八子区中的一个子区在显示基板平面的正投影至少部分交叠，且与第一透明子区和第二透明子区中的一个在显示基板平面的正投影至少部分交叠；所述三个第二发光器件的第一阳极层在显示基板平面的正投影，分别与第一子区至第五子区中的其它三个子区在显示基板平面的正投影至少部分交叠，且互不相同；第二方向与第一方向交叉。
  11. 根据权利要求10所述的显示基板，其中，所述蓝色发光器件的第二阳极层在显示基板平面的正投影的宽度，大于所述红色发光器件的第二阳极层在显示基板平面的正投影的宽度、所述绿色发光器件的第二阳极层在显示基板平面的正投影的宽度、以及所述白色发光器件的第二阳极层在显示基板平面的正投影的宽度，宽度是指沿第二方向的尺寸特征。
  12. 根据权利要求1至9任一项所述的显示基板，其中，所述像素区域还包括：多个像素驱动电路，所述像素驱动电路配置为驱动发光器件，所述多个像素驱动电路在显示基板平面的正投影位于所述像素区域在显示基板平面的正投影的范围之内。
  13. 根据权利要求12所述的显示基板，其中，所述像素驱动电路包括：第一晶体管、第二晶体管和第三晶体管，所述第一晶体管和所述第三晶体管位于所述第二晶体管的第二方向的两侧，且所述第一晶体管、所述第二晶体管和所述第三晶体管的沟道区域的延伸方向均为第二方向。
  14. 根据权利要求13所述的显示基板，其中，所述像素驱动电路还包括：存储电容，所述存储电容位于所述第二晶体管和所述第三晶体管之间，且所述存储电容的延伸方向为第二方向。
  15. 根据权利要求12所述的显示基板，其中，所述多个像素驱动电路沿第一方向并排设置。
  16. 根据权利要求12所述的显示基板，其中，所述像素驱动电路包括：第一晶体管、第二晶体管、第三晶体管和存储电容；
    在垂直于显示基板平面的方向上，所述显示基板包括：在基底上依次设置的第一导电层、半导体层、第二导电层和第三导电层；所述第一导电层包括：第一极板，所述半导体层包括：第一晶体管的有源层、第二晶体管的有源层、第三晶体管的有源层和第二极板，所述第二导电层包括：第一晶体管的栅电极、第二晶体管的栅电极和第三晶体管的栅电极，所述第三导电层包括：第一晶体管的第一极、第一晶体管的第二极、第二晶体管的第一极、第二晶体管的第二极、第三晶体管的第一极、第三晶体管的第二极和第三极板，所述第一极板和所述第二极板形成第一存储电容，所述第二极板和所述第三极板形成第二存储电容，所述第一存储电容和所述第二存储电容并联，以形成所述存储电容。
  17. 根据权利要求16所述的显示基板，其中，所述第一导电层还包括：补偿连接线，所述第三导电层还包括：补偿信号线，所述第三晶体管的第一极通过所述补偿连接线与所述补偿信号线连接。
  18. 根据权利要求16所述的显示基板，其中，所述第二导电层包括：电 源连接线，所述第三导电层还包括：第一电源线，所述第二晶体管的第一极通过所述电源连接线与所述第一电源线连接；所述第一电源线通过过孔与所述电源连接线连接，在所述第一晶体管的栅电极与所述第三晶体管的栅电极之间形成双层走线。
  19. 根据权利要求16所述的显示基板，其中，所述第二导电层还包括：第一扫描信号线和第二扫描信号线，所述第一晶体管的栅电极与所述第一扫描信号线连接，所述第三晶体管的栅电极与所述第二扫描信号线连接。
  20. 根据权利要求16所述的显示基板，其中，所述第三导电层还包括：数据信号线，所述第一晶体管的第一极与所述数据信号线连接。
  21. 一种显示装置，包括如权利要求1至20任一项所述的显示基板。
PCT/CN2021/141729 2021-12-27 2021-12-27 显示基板及显示装置 WO2023122895A1 (zh)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101930994A (zh) * 2010-08-12 2010-12-29 友达光电股份有限公司 有机发光装置的像素结构
US20140185129A1 (en) * 2012-12-31 2014-07-03 Lg Display Co., Ltd. Transparent display apparatus and a method for controlling the same
KR20180079095A (ko) * 2016-12-30 2018-07-10 엘지디스플레이 주식회사 투명 유기 발광 표시 장치
CN110544749A (zh) * 2018-05-29 2019-12-06 乐金显示有限公司 显示设备
CN111293158A (zh) * 2020-02-25 2020-06-16 昆山国显光电有限公司 显示面板和显示装置
CN111564476A (zh) * 2020-05-15 2020-08-21 合肥京东方卓印科技有限公司 显示基板及其制备方法、显示装置
CN113035904A (zh) * 2019-12-09 2021-06-25 乐金显示有限公司 透明显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101930994A (zh) * 2010-08-12 2010-12-29 友达光电股份有限公司 有机发光装置的像素结构
US20140185129A1 (en) * 2012-12-31 2014-07-03 Lg Display Co., Ltd. Transparent display apparatus and a method for controlling the same
KR20180079095A (ko) * 2016-12-30 2018-07-10 엘지디스플레이 주식회사 투명 유기 발광 표시 장치
CN110544749A (zh) * 2018-05-29 2019-12-06 乐金显示有限公司 显示设备
CN113035904A (zh) * 2019-12-09 2021-06-25 乐金显示有限公司 透明显示装置
CN111293158A (zh) * 2020-02-25 2020-06-16 昆山国显光电有限公司 显示面板和显示装置
CN111564476A (zh) * 2020-05-15 2020-08-21 合肥京东方卓印科技有限公司 显示基板及其制备方法、显示装置

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