WO2021218425A1 - 显示基板及其制备方法、显示装置 - Google Patents
显示基板及其制备方法、显示装置 Download PDFInfo
- Publication number
- WO2021218425A1 WO2021218425A1 PCT/CN2021/080055 CN2021080055W WO2021218425A1 WO 2021218425 A1 WO2021218425 A1 WO 2021218425A1 CN 2021080055 W CN2021080055 W CN 2021080055W WO 2021218425 A1 WO2021218425 A1 WO 2021218425A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- sensing
- layer
- electrode
- orthographic projection
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 238
- 238000004519 manufacturing process Methods 0.000 title description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 94
- 239000002184 metal Substances 0.000 claims abstract description 94
- 238000002161 passivation Methods 0.000 claims abstract description 39
- 238000001514 detection method Methods 0.000 claims description 47
- 238000000034 method Methods 0.000 claims description 32
- 239000003990 capacitor Substances 0.000 claims description 25
- 238000000504 luminescence detection Methods 0.000 claims description 19
- 239000010410 layer Substances 0.000 abstract description 387
- 239000011241 protective layer Substances 0.000 abstract 3
- 239000010408 film Substances 0.000 description 68
- 238000010586 diagram Methods 0.000 description 35
- 238000000059 patterning Methods 0.000 description 28
- 230000008569 process Effects 0.000 description 25
- 229910044991 metal oxide Inorganic materials 0.000 description 22
- 150000004706 metal oxides Chemical class 0.000 description 22
- 238000012546 transfer Methods 0.000 description 17
- 238000000151 deposition Methods 0.000 description 15
- 238000003860 storage Methods 0.000 description 11
- 239000010409 thin film Substances 0.000 description 11
- 230000000694 effects Effects 0.000 description 10
- 239000000463 material Substances 0.000 description 10
- 229910052738 indium Inorganic materials 0.000 description 8
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 230000007704 transition Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- 239000012780 transparent material Substances 0.000 description 3
- 238000011282 treatment Methods 0.000 description 3
- 229910052725 zinc Inorganic materials 0.000 description 3
- 239000011701 zinc Substances 0.000 description 3
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000004880 explosion Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical class [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910001257 Nb alloy Inorganic materials 0.000 description 1
- 229910000583 Nd alloy Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- UBSJOWMHLJZVDJ-UHFFFAOYSA-N aluminum neodymium Chemical compound [Al].[Nd] UBSJOWMHLJZVDJ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- DTSBBUTWIOVIBV-UHFFFAOYSA-N molybdenum niobium Chemical compound [Nb].[Mo] DTSBBUTWIOVIBV-UHFFFAOYSA-N 0.000 description 1
- 239000002365 multiple layer Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- -1 polyethylene terephthalate Polymers 0.000 description 1
- 229920000139 polyethylene terephthalate Polymers 0.000 description 1
- 239000005020 polyethylene terephthalate Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000011540 sensing material Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
Definitions
- the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display substrate, a preparation method thereof, and a display device.
- Organic Light Emitting Diode (English: Organic Light Emitting Diode, referred to as OLED) display substrates are widely used in mobile phones, tablets, digital cameras, etc. due to their advantages of low energy consumption, low production cost, self-luminescence, wide viewing angle and fast response speed. field.
- the OLED display substrate includes a plurality of sub-pixels distributed in an array, and each sub-pixel includes a coupled sub-pixel driving circuit and a light-emitting element.
- the sub-pixel driving circuit provides a driving current for the corresponding light-emitting element to drive the light-emitting element to emit light of a corresponding color. Since the luminous brightness of the light-emitting element will change during the use of the OLED display substrate, in order to improve the adverse effect of the change in the luminous brightness of the light-emitting element on the display effect, the sub-pixel is generally set to detect the brightness of the light emitted by the light-emitting element.
- the light-emitting detection device mainly includes a sensing thin film transistor and a PIN-type photodiode.
- the PIN-type photodiode receives the light emitted by the light-emitting element and will receive The light is converted into an electrical signal, so that the converted electrical signal can compensate the light emission of the light-emitting element.
- an embodiment of the present disclosure provides a display substrate including a plurality of display units, the display unit includes a plurality of sub-pixels, a light emission detection area is provided in the display unit, and the display substrate includes:
- a sensing transistor arranged on one side of the substrate, and located in the light-emitting detection area;
- the second metal layer is disposed on the side of the substrate facing the sensing transistor.
- the second metal layer includes a sensing scan line and a second power supply line spaced apart from each other, the sensing scan line and the second power supply The lines all extend in the first direction in the light-emitting detection area, and the sensing gate electrode of the sensing transistor is electrically connected to the sensing scan line;
- the first flat layer is disposed on the side of the sensing transistor and the second metal layer away from the substrate, the first flat layer is located in the light-emitting detection area, and the first flat layer is located on the substrate
- the orthographic projection on includes the sensing transistor
- the passivation protection layer is disposed on the side of the first flat layer away from the substrate, and the orthographic projection of the first flat layer on the substrate is located on the orthographic projection of the passivation protection layer on the substrate within range
- the PIN photodiode is arranged on the side of the passivation protection layer away from the substrate.
- the thickness of the passivation protection layer in a direction perpendicular to the substrate is 800 angstroms to 1200 angstroms.
- the PIN-type photodiode includes a first electrode, a PIN junction, and a second electrode that are sequentially stacked in a direction away from the passivation protection layer, and the first electrode is on the substrate.
- the orthographic projection of is located within the orthographic projection range of the first flat layer on the substrate.
- the distance between the boundary of the orthographic projection of the first electrode on the substrate and the boundary of the orthographic projection of the first flat layer on the substrate is d1, 2 ⁇ m ⁇ d1 ⁇ 4 ⁇ m .
- the orthographic projection of the PIN junction on the substrate lies within the orthographic projection range of the first electrode on the substrate, and the orthographic projection boundary of the PIN junction on the substrate The distance from the boundary of the orthographic projection of the first electrode on the substrate is d2, and 1 ⁇ m ⁇ d2 ⁇ 3 ⁇ m.
- the display substrate further includes a transparent conductive layer disposed on a side of the PIN-type photodiode away from the substrate, and the transparent conductive layer includes a conductive connection line and a third electrode that are disconnected from each other ,
- the third electrode is located in the sub-pixel area
- the display substrate further includes a fourth connection line located in the same layer as the first electrode, and the fourth connection line extends from the light emission detection area to the light emission Outside the detection area, the part of the conductive connection line located within the luminescence detection area is electrically connected to the second electrode, and the part of the conductive connection line located outside the luminescence detection area is electrically connected to the fourth connection Line is electrically connected, and the fourth connection line is electrically connected to the second power line.
- the display substrate further includes an organic light-emitting layer disposed on a side of the transparent conductive layer away from the base and a fourth electrode disposed on a side of the organic light-emitting layer away from the base,
- the third electrode, the organic light-emitting layer, and the fourth electrode constitute a light-emitting element, and the light-emitting element is located in a sub-pixel area.
- the orthographic projection of the PIN-type photodiode on the substrate and each sub-pixel in the display unit The orthographic projections of the light-emitting elements on the substrate all have overlapping areas.
- the display substrate may further include a sensing capacitor located in the light-emitting detection area, and the display substrate may further include a sensing drain electrode or a sensing source electrode located on the same layer as the sensing transistor.
- a fourth electrode plate and a fifth electrode plate, the fourth electrode plate and the fifth electrode plate are respectively located on both sides of the sensing transistor in the first direction, the fourth electrode plate and the fifth electrode plate.
- the electrode plates are all electrically connected to the second power line, and the orthographic projection of the fourth electrode plate on the substrate and the orthographic projection of the third electrode on the substrate have an overlapping area to form a first A sensing capacitor, the orthographic projection of the fifth electrode plate on the substrate and the orthographic projection of the third electrode on the substrate have an overlapping area to form a second sensing capacitor, the sensing capacitor It includes a first sensing capacitor and a second sensing capacitor.
- the display unit includes eight sub-pixels, the eight sub-pixels are arranged in an array of two rows and four columns, and the driving circuit of each sub-pixel is located on the side of the sub-pixel area away from the other row of sub-pixels, so The light emission detection area is located in the middle of the display unit in a second direction, and the second direction is a direction perpendicular to the first direction.
- the display substrate further includes a first metal layer located between the base and the sensing transistor, the first metal layer includes a sensing light-shielding layer, and the sensing light-shielding layer
- the orthographic projection on the substrate includes an orthographic projection of the sensing active layer of the sensing transistor on the substrate, and the sensing light shielding layer is electrically connected to the sensing scan line.
- the orthographic projection of the sensing transistor on the substrate and the orthographic projection of the PIN-type photodiode on the substrate at least partially overlap.
- the embodiments of the present disclosure also provide a method for preparing a display substrate, the display substrate includes a plurality of display units, the display unit includes a plurality of sub-pixels, the display unit is provided with a light-emitting detection area, so
- the methods include:
- a sensing transistor and a second metal layer are formed on one side of the substrate, the sensing transistor is located in the light-emitting detection area, the second metal layer includes a sensing scan line and a second power line spaced apart from each other, the sensing scan The line and the second power line both extend in the first direction in the light-emitting detection area, and the sensing gate electrode of the sensing transistor is electrically connected to the sensing scan line;
- a first flat layer is formed on the side of the sensing transistor and the second metal layer away from the substrate, the first flat layer is located in the light-emitting detection area, and the first flat layer is on the substrate
- the orthographic projection of includes the sensing transistor
- a passivation protection layer is formed on the side of the first flat layer away from the substrate, and the orthographic projection of the first flat layer on the substrate is located in the orthographic projection range of the passivation protection layer on the substrate Inside;
- a PIN-type photodiode is formed on the side of the passivation protection layer away from the substrate.
- an embodiment of the present disclosure also provides a display device including the above-mentioned display substrate.
- Figure 1 is a schematic diagram of a sub-pixel drive circuit
- Figure 2 is a schematic diagram of a luminescence detection circuit
- FIG. 3a is a schematic diagram of a top view structure of a display substrate in an exemplary embodiment of the present disclosure
- FIG. 3b is a schematic diagram of a top view structure of a display substrate in an exemplary embodiment of the present disclosure
- Figure 3c is a schematic cross-sectional view of A-A in Figure 3b;
- FIG. 4 is a schematic cross-sectional view of A-A of the display substrate after forming the fourth electrode in an exemplary embodiment of the present disclosure
- FIG. 5 is a schematic diagram after a first metal layer pattern is formed in an exemplary embodiment of the present disclosure
- Figure 6 is a schematic cross-sectional view of A-A in Figure 5;
- FIG. 7 is a schematic diagram after forming a pattern of a metal oxide layer in an exemplary embodiment of the present disclosure.
- Fig. 8 is a schematic cross-sectional view of A-A in Fig. 7;
- FIG. 9 is a schematic diagram after forming a second metal layer pattern in an exemplary embodiment of the present disclosure.
- Fig. 10 is a schematic cross-sectional view of A-A in Fig. 9;
- FIG. 11 is a schematic diagram after a third insulating layer pattern is formed in an exemplary embodiment of the present disclosure.
- Figure 12 is a schematic cross-sectional view of A-A in Figure 11;
- FIG. 13 is a schematic diagram after a third metal layer pattern is formed in an exemplary embodiment of the present disclosure.
- Fig. 14 is a schematic cross-sectional view of A-A in Fig. 13;
- FIG. 15 is a schematic diagram after forming a first flat layer pattern in an exemplary embodiment of the present disclosure.
- Fig. 16 is a schematic cross-sectional view of A-A in Fig. 15;
- FIG. 17 is a schematic diagram after a fifth insulating layer pattern is formed in an exemplary embodiment of the present disclosure.
- Fig. 18 is a schematic cross-sectional view of A-A in Fig. 17;
- FIG. 19 is a schematic diagram after forming a fourth metal layer pattern in an exemplary embodiment of the present disclosure.
- Fig. 20 is a schematic cross-sectional view of A-A in Fig. 19;
- FIG. 21 is a schematic diagram after forming a PIN knot pattern in an exemplary embodiment of the present disclosure.
- Fig. 22 is a schematic cross-sectional view of A-A in Fig. 21;
- FIG. 23 is a schematic diagram after forming a third electrode pattern in an exemplary embodiment of the present disclosure.
- Figure 24 is a schematic cross-sectional view of A-A in Figure 23;
- FIG. 25 is a schematic diagram after forming a second flat layer pattern in an exemplary embodiment of the present disclosure.
- Fig. 26 is a schematic cross-sectional view of A-A in Fig. 25.
- a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
- the transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
- the channel region refers to a region through which current mainly flows.
- it may be the drain electrode of the first electrode and the source electrode of the second electrode, or it may be the source electrode of the first electrode and the drain electrode of the second electrode.
- the functions of the "source electrode” and the “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged.
- parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore, it also includes a state where the angle is -5° or more and 5° or less.
- perpendicular refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore, also includes a state where an angle of 85° or more and 95° or less is included.
- A includes “B” to indicate that B overlaps with A or B is inside A; “A” in “B” indicates that A overlaps with B or A is inside B.
- the light-emitting detection device mainly includes a sensing thin film transistor and a PIN-type photodiode.
- the PIN-type photodiode When the light-emitting detection device is used to detect the intensity of the light emitted by the light-emitting element, the PIN-type photodiode receives the light emitted by the light-emitting element and will receive The light is converted into an electrical signal, so that the converted electrical signal can compensate for the light emission of the light-emitting element.
- the PIN area is larger, which will occupy a certain percentage of the aperture ratio. In a high PPI pixel design, the area of the PIN will cause the aperture ratio to be too small.
- the sensing thin film transistor stack can be placed under the PIN photodiode, and a flat layer can be added between the sensing thin film transistor and the PIN photodiode.
- the material of the flat layer is usually organic, and a dry etching process is used in the process of forming a PIN junction on the flat layer, and the dry etching process etches the flat layer to produce oxycarbon. Carbon oxide compounds will pollute the sidewalls of the PIN junction and affect the dark current of the PIN junction. In addition, in the subsequent high temperature, the flat layer will release gas, and there is a risk of film explosion, which may affect the quality of the PIN film, affect the dark current and signal-to-noise ratio of the PIN photodiode, and reduce the optical compensation effect.
- Fig. 1 is a schematic diagram of a sub-pixel driving circuit.
- the sub-pixel driving circuit may include a first transistor T1, a second transistor T2, a third transistor T3, and a first storage capacitor C ST .
- the first gate electrode of the first transistor T1 is connected to the control scan line Gn
- the first source electrode of the first transistor T1 is connected to the data line Dn
- the first drain electrode of the first transistor T1 is simultaneously connected to the second gate of the second transistor T2.
- the electrode is connected to a plate of the first storage capacitor C ST.
- the second source electrode of the second transistor T2 is connected to the first power line VDD, and the second drain electrode of the second transistor T2 is simultaneously connected to the other plate of the first storage capacitor C ST and the third drain electrode of the third transistor T3.
- the anode of the OLED is connected.
- the third gate electrode of the third transistor T3 is connected to the third scan line Sn, and the third source electrode of the third transistor T3 is connected to the compensation line Se1.
- the cathode of the OLED is connected to the second power line VSS.
- the third scan line Sn is shared with the control scan line Gn.
- Figure 2 is a schematic diagram of a luminescence detection circuit.
- the light emission detection circuit may include a sensing transistor T4, a PIN-type photodiode PIN, and a sensing capacitor C2.
- the sensing gate electrode of the sensing transistor T4 is connected to the sensing scan line G2
- the sensing gate electrode of the sensing transistor T4 is connected to the sensing line Se2
- the sensing drain electrode of the sensing transistor T4 is connected to the first of the PIN photodiode PIN.
- the second electrode of the PIN-type photodiode PIN is connected to the second power line VSS.
- the two pole plates of the sensing capacitor C2 are respectively connected to the first electrode and the second electrode of the PIN photodiode PIN.
- FIG. 3a is a schematic diagram of a top view structure of a display substrate in an exemplary embodiment of the present disclosure
- FIG. 3b is a schematic diagram of a top view structure of a display substrate in an exemplary embodiment of the present disclosure
- FIG. 3c is a schematic diagram of the AA cross-section in FIG.
- the AA cross-sectional schematic diagram of the display substrate after forming the fourth electrode in an exemplary embodiment is disclosed.
- the display substrate includes a plurality of display units
- FIG. 3 shows one of the display units.
- the display substrate includes a plurality of first power supply lines VDD extending in a second direction (the vertical direction in FIGS.
- the display substrate may further include a plurality of compensation connection lines 642 extending in a first direction (horizontal direction in FIGS. 3a and 3b) between the first power supply line VDD and the compensation line Se1, the compensation connection line 642 and the compensation line Se1 Electric connection.
- the compensation line Se1 includes a plurality of pairs, and two adjacent ones of the two adjacent pairs of compensation lines Se1, the first power line VDD, and the compensation line Se1 define one display unit 100.
- the display unit includes a plurality of sub-pixels, and the plurality of sub-pixels are arranged in an array.
- the display unit may include four data lines Dn extending in the second direction and sequentially juxtaposed in the first direction, that is, the horizontal direction, which are the first data line Dn, the second data line Dn, and the third data line Dn, respectively.
- the data line Dn and the fourth data line Dn are also included.
- the display unit also includes a sensing line Se2 extending in the second direction. The sensing line Se2 is located between the second data line Dn and the third data line Dn.
- the display unit includes two rows and four columns of sub-pixels, that is, 8 sub-pixels.
- the 8 sub-pixels can be R1 (i.e., the first sub-pixel P1), G1 (i.e., the second sub-pixel P2), B1 (i.e., the third sub-pixel P3), W1 (i.e., the fourth sub-pixel P4), and R2 (i.e., the fourth sub-pixel P4).
- the eight sub-pixels are arranged in two rows and four columns.
- the first column of sub-pixels (the first sub-pixel P1 and the fifth sub-pixel P5) are located between the compensation line Se1 and the first data line Dn, and the second column of sub-pixels (the second sub-pixel P2 and the sixth sub-pixel P6) are located in the second column.
- the third column of sub-pixels (the third sub-pixel P3 and the seventh sub-pixel P7) are located between the sensing line Se2 and the third data line Dn, and the fourth column of sub-pixels (the fourth sub-pixel)
- the pixel P4 and the eighth sub-pixel P8) are located between the fourth data line Dn and the first power supply line VDD.
- a luminescence detection area is provided in the display unit.
- the display substrate may further include a sensing scan line G2 and a second power supply line VSS extending in the first direction and located in the light emission detection area.
- the display substrate in a direction perpendicular to the display substrate, may include a base 10, and a sensing transistor 20 and a second metal layer disposed on one side of the base 10.
- the second metal layer may include a sensing scan line G2 and a second power supply line VSS.
- the sensing transistor 20 is located in the light emission detection area, and the sensing scan line G2 and the second power supply line VSS are isolated from each other, and both extend in the first direction (horizontal direction in FIG. 3) in the light emission detection area.
- the sensing gate electrode of the sensing transistor is electrically connected to the sensing scan line G2.
- the display substrate may further include a first flat layer 11 located in the luminescence detection area.
- the first flat layer 11 is disposed on the side of the sensing transistor 20 away from the substrate.
- the display substrate may further include a passivation protection layer 12 disposed on the side of the first flat layer 11 away from the base 10, and a PIN photodiode 30 disposed on the side of the passivation protection layer 12 away from the base 10.
- the PIN-type photodiode 30 is located in the light emission detection area.
- a passivation protection layer 12 is provided between the first flat layer 11 and the PIN-type photodiode 30, so that when the passivation protection layer 12 is away from the first flat layer 11, a PIN-type
- the passivation protection layer 12 can be used as a sacrificial layer to protect the first flat layer 11 from being etched during the dry etching process of forming the PIN, thereby avoiding pollution to the sidewall of the PIN, improving the performance of the PIN and ensuring It has a lower dark current and improved the optical compensation effect.
- the display substrate may further include a light-emitting element 40 arranged on a side of the PIN-type photodiode 30 away from the base 10 and located in the sub-pixel area.
- the PIN-type photodiode 30 is electrically connected to the sensing transistor 20.
- the orthographic projection of the PIN-type photodiode 30 on the substrate 10 and the orthographic projection of the light-emitting element 40 on the substrate 10 at least partially overlap, so that the PIN-type photodiode 30 can detect the luminous brightness of the light-emitting element 40 and emit light from the light-emitting element 40.
- the brightness is converted into an electrical signal, which is transmitted to the sensing transistor 20, and then transmitted to the corresponding control circuit.
- the thickness of the passivation protection layer 12 in a direction perpendicular to the substrate 10 is 800 angstroms to 1200 angstroms.
- the material of the first flat layer 11 is usually organic.
- the first flat layer 11 will release gas at a subsequent high temperature. Setting the thickness of the passivation protection layer 12 to be 800 angstroms to 1200 angstroms will not affect the first flat layer 11 to release gas.
- the thickness of the passivation protection layer 12 in a direction perpendicular to the substrate 10 is 1000 angstroms.
- the material of the passivation protection layer 12 may include at least one of silicon oxide and silicon nitride.
- the material of the first flat layer 11 may be an organic insulating material, such as a silicon-on-glass bonding structure material (SOG) or a resin material.
- SOG silicon-on-glass bonding structure material
- the display substrate may further include a fourth insulating layer 15 disposed between the sensing transistor 20 and the first flat layer 11, and the fourth insulating layer 15 covers the sensing transistor. 20 and the surface of the substrate 10 behind the second metal layer.
- the orthographic projection of the sensing transistor on the substrate 10 is within the orthographic projection range of the first flat layer 11 on the substrate 10. In this way, the range where the sensing transistor 20 is located is covered by the first flat layer 11 to ensure that the PIN-type photodiode 30 can be formed on a flat surface, and the performance of the PIN-type photodiode is ensured.
- the orthographic projection of the first planarization layer 11 on the substrate 10 is within the orthographic projection range of the passivation protection layer 12 on the substrate 10. It can also be said that the passivation protection layer 12 covers the entire surface of the first flat layer 11, so that the passivation protection layer 12 can better protect the first flat layer 11 and prevent the first flat layer 11 from being etched in the subsequent dry etching process.
- the PIN type photodiode 30 includes a first electrode 31, a PIN junction 32 and a second electrode 33 that are sequentially stacked in a direction away from the passivation protection layer 12.
- the orthographic projection of the first electrode 31 on the substrate 10 is within the orthographic projection of the first flat layer 11 on the substrate 10.
- the PIN-type photodiode 30 can be formed on a flat surface, ensuring the performance of the PIN-type photodiode 30.
- the first flat layer 11 will release gas in the subsequent high temperature, and the distance d that the orthographic projection boundary of the first electrode 31 on the substrate 10 is retracted relative to the orthographic projection boundary of the first flat layer 11 on the substrate 10 is set as 2 ⁇ m ⁇ d1 ⁇ 4 ⁇ m, it is possible to reserve enough air release space for the first flat layer 11 to avoid film explosion.
- setting d to 2 ⁇ m ⁇ d1 ⁇ 4 ⁇ m can also prevent the area of the first electrode 31 from being too small, thereby avoiding the area of the PIN photodiode from being too small, and ensuring the photosensitive area of the PIN photodiode.
- the orthographic projection of the PIN junction 32 on the substrate 10 is within the orthographic projection range of the first electrode 31 on the substrate 10, and the orthographic projection boundary of the PIN junction 32 on the substrate 10
- the orthographic projection of the second electrode 33 on the substrate 10 is within the orthographic projection range of the PIN junction 32 on the substrate 10, and the orthographic projection of the second electrode 33 on the substrate 10
- the distance between the boundary and the boundary of the orthographic projection of the PIN junction 32 on the substrate 10 is d3, and d3 is greater than zero.
- the orthographic projection of the PIN-type photodiode 30 on the substrate 10 and the orthographic projection of the sensing transistor 20 on the substrate 10 at least partially overlap. In this way, the area occupied by the light-emitting detection device can be reduced, and the aperture ratio of the display substrate can be increased.
- the orthographic projection of the sensing transistor 20 on the substrate 10 is within the range of the orthographic projection of the PIN-type photodiode 30 on the substrate 10. In this way, the footprint of the light-emitting detection device can be minimized.
- the area further increases the aperture ratio of the display substrate, which is conducive to achieving high PPI requirements.
- the first electrode 31 may use a light-shielding material, and the orthographic projection of the sensing transistor 20 on the substrate 10 is within the range of the orthographic projection of the first electrode 31 on the substrate 10. Therefore, the sensing transistor is completely covered by the PIN-type photodiode, which not only minimizes the area occupied by the light-emitting detection device in the direction parallel to the substrate 10, but also prevents the sensing transistor from being exposed to light. The influence of the luminescence detection circuit is guaranteed to have a small dark current, thereby effectively improving the signal-to-noise ratio of the luminescence detection circuit.
- the first electrode 31 is electrically connected to the source electrode or the drain electrode of the sensing transistor.
- the first electrode 31 may use a light-shielding material, for example, a metal material with light-shielding properties
- the second electrode 33 may use a transparent material, such as indium tin oxide or indium zinc oxide, but is not limited to this. .
- the second electrode 33 can be made of a transparent material, so that the PIN-type photodiode 30 can well receive the light emitted by the corresponding light-emitting element, thereby ensuring the detection accuracy of the light-emitting detection circuit.
- the display substrate may further include a sixth insulating layer 16 disposed on the side of the PIN-type photodiode 30 away from the base 10, and disposed on the side of the sixth insulating layer 16 away from the base 10
- the transparent conductive layer may include a third electrode 411 and a conductive connection line 412 that are disconnected from each other.
- the third electrode 411 is located in the sub-pixel area.
- the display substrate may further include a fourth connection line 38.
- the fourth connection line 38 and the first electrode 31 are located on the same layer, that is, the fourth connection line 38 and the first electrode 31 are formed by the same patterning process.
- the fourth connecting line 38 extends from the inside of the luminescence detection area to the outside of the luminescence detection area.
- One end of the conductive connection line 412 is electrically connected to the second electrode 33 through a via hole that passes through the second flat layer 17 and the sixth insulating layer 16, and the other end of the conductive connection line 412 passes through the second flat layer 17 and the sixth insulating layer.
- the via hole of the layer 16 is electrically connected to the fourth connection line 38.
- the fourth connection line 38 is electrically connected to the second power supply line VSS.
- the display substrate may further include a pixel defining layer 18 disposed on the side of the transparent conductive layer away from the base 10.
- the display substrate may further include an organic light-emitting layer 42 disposed on a side of the pixel defining layer 18 away from the base 10 and a fourth electrode 43 disposed on a side of the organic light-emitting layer 42 away from the base 10.
- the organic light emitting layer 42 is in contact with the third electrode 411 in an area outside the pixel defining layer 18.
- the light-emitting element 40 includes a third electrode 411, an organic light-emitting layer 42, and a fourth electrode 43 that are sequentially stacked in contact with each other.
- the material of the third electrode 411 may be a transparent material, such as indium tin oxide or indium zinc oxide. Therefore, the light emitted by the light-emitting element 40 can be irradiated onto the PIN-type photodiode 30 through the third electrode 411.
- each sub-pixel in the display unit includes a light-emitting element 40.
- the orthographic projection of the PIN-type photodiode on the substrate 10 partially overlaps the orthographic projection of the light-emitting elements 40 of one or at least two sub-pixels on the substrate 10.
- the orthographic projection of the PIN-type photodiode on the substrate 10 partially overlaps the orthographic projection of one light-emitting element 40 on the substrate 10, or the orthographic projection of the PIN-type photodiode on the substrate 10 and at least two light-emitting elements
- Each of the orthographic projections on the substrate 10 are partially overlapped, so that at least two light-emitting elements in a display unit can share a light-emitting detection device, further reducing the area occupied by the light-emitting detection area in the display substrate and increasing the display substrate The opening rate.
- the display unit may include 8 sub-pixels, and the orthographic projection of the light-emitting element in each sub-pixel on the substrate 10 is the same as the orthographic projection of the PIN-type photodiode 30 on the substrate 10. At least partially overlap. Therefore, 8 sub-pixels in one display unit can share one PIN-type photodiode. In this way, the area of the luminescence detection area can be minimized, and the aperture ratio of the display substrate can be increased.
- the 8 sub-pixels of the display unit are arranged in two rows and four columns.
- the driving circuit of each sub-pixel is located on the side of the sub-pixel area away from the other row of sub-pixels.
- the driving circuit of the first sub-pixel P1 is located on the side of the first sub-pixel P1 area away from the fifth sub-pixel P5 (ie, the first The upper side of the sub-pixel P1 area).
- the light-emitting detection area 200 is located in the middle of the display unit in the second direction, so that the PIN-type photodiode may have an overlapping area with the light-emitting element of each sub-pixel in the display unit.
- the second direction is the vertical direction, that is, the second direction is the direction in which the rows are arranged.
- the sensing transistor 20 may be a top-gate thin film transistor.
- the display substrate may further include a first metal layer disposed on a side of the base 10 and a first insulating layer 14 (also called a buffer layer 14) disposed on a side of the first metal layer away from the base 10 .
- the first metal layer may include the sensing light shielding layer 13.
- the orthographic projection of the sensing active layer of the sensing transistor 20 on the substrate 10 is within the orthographic projection of the sensing light shielding layer 13 on the substrate 10.
- the display substrate may further include a metal oxide layer disposed on a side of the first insulating layer 14 away from the base 10, and the metal oxide layer includes the sensing active layer 21 of the sensing transistor 20.
- the display substrate may further include a second insulating layer disposed on a side of the metal oxide layer facing away from the base 10 and a second metal layer disposed on a side of the second insulating layer facing away from the base 10.
- the second metal layer may include a sensing scan line G2 and a second power supply line VSS.
- the sensing scan line G2 and the second power supply line VSS are isolated from each other, and both extend in the first direction (horizontal direction in FIG. 3) in the light emission detection area.
- the portion where the sensing scan line G2 overlaps with the sensing active layer 21 serves as the sensing gate electrode 23.
- the display substrate may also include a third insulating layer 24 (also called an interlayer insulating layer 24) disposed on the side of the second metal layer away from the base 10 and a third metal layer disposed on the side of the third insulating layer 24 away from the base 10 .
- the third metal layer may include a sensing line Se2, a sensing source electrode 251 of the sensing transistor T4, a sensing drain electrode 252 of the sensing transistor T4, a VSS transfer line 253, a fourth electrode plate 254, a fifth electrode plate 255, and First connection line 256.
- the sensing line Se2 extends in the second direction (the vertical direction in FIG. 3).
- the sensing source electrode 251 of the sensing transistor T4 and the sensing line Se2 have an integral structure.
- the VSS transfer line 253 is connected to the second power line VSS through a via hole.
- the first connecting line 256 is electrically connected to the sensing light shielding layer 13 through the via hole, and the first connecting line 256 is electrically connected to the sensing scanning line G2 through the via hole, thereby electrically connecting the sensing light shielding layer 13 and the sensing scanning line G2 .
- the fourth electrode plate 254 and the fifth electrode plate 255 jointly serve as one electrode plate of the sensing capacitor C2, and form the sensing capacitor C2 with the first electrode 31.
- the display substrate may further include a fourth insulating layer 15 disposed on a side of the third metal layer away from the base 10, and the first flat layer 11 is located on a side of the fourth insulating layer 15 away from the base 10.
- the sensing transistor 20 is not limited to a top-gate thin film transistor. In other embodiments, the sensing transistor 20 may be a bottom-gate thin film transistor.
- the "patterning process” referred to in the present disclosure includes film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping treatments.
- the deposition can be any one or more of sputtering, evaporation and chemical vapor deposition
- the coating can be any one or more of spraying and spin coating
- the etching can be any of dry etching and wet etching.
- “Thin film” refers to a layer of film made by depositing or coating a certain material on a substrate.
- the "film” does not require a patterning process during the entire production process, the “film” can also be referred to as a "layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process.
- the “layer” after the patterning process contains at least one "pattern”.
- “A and B are arranged in the same layer” means that A and B are formed at the same time through the same patterning process.
- Each display unit includes a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, a fourth sub-pixel P4, a fifth sub-pixel P5, a sixth sub-pixel P6, a seventh sub-pixel P7, and an eighth sub-pixel.
- the eight sub-pixels are arranged in an array of two rows and four columns.
- the first row of sub-pixels includes a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 that are arranged in sequence.
- the sub-pixels include a fifth sub-pixel P5, a sixth sub-pixel P6, a seventh sub-pixel P7, and an eighth sub-pixel P8 that are arranged in sequence.
- the pixel driving circuit of each sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor.
- the eight sub-pixels of each display unit share a luminescence detection circuit.
- Forming a first metal layer pattern includes: depositing a first metal film on a substrate, patterning the first metal film through a patterning process, and forming a first metal layer pattern on the substrate 10, as shown in FIGS. 5 and 6
- FIG. 5 is a schematic diagram after forming the first metal layer pattern in an exemplary embodiment of the present disclosure
- FIG. 6 is a schematic diagram of the AA cross-sectional view in FIG. 5.
- the first metal layer pattern includes a first electrode plate 51, a VDD transfer line 50, a data connection line 56 and a sensing shielding layer 13.
- Each sub-pixel forms a first plate 51, and the first plate 51 of each sub-pixel is located on the side of the sub-pixel away from the other row.
- the first sub-pixel P1 is located in the first row, and the first sub-pixel P1 is located in the first row.
- a plate 51 is located on the side of the first sub-pixel away from the second row.
- the first plate 51 of the first sub-pixel P1 is located on the upper side
- the first plate 51 of the fifth sub-pixel P5 is located on the lower side. side.
- the first plates of the two rows of sub-pixels are symmetrically arranged with respect to the symmetry line of the two rows, as shown in FIG. 5.
- the number of VDD transition wires 50 is two. The two VDD transition wires 50 are respectively close to the first plate 51 on the upper side and the first plate 51 on the lower side.
- the VDD transition wires 50 span the four sub-pixels in the corresponding rows. Horizontal strip structure.
- the VDD transfer line 50 is configured to be electrically connected to the first power line VDD so as to provide a high voltage VDD signal to the source electrode of the second transistor of each sub-pixel.
- the number of data connection lines 56 is four, and the four data connection lines 56 are vertical straight lines arranged in parallel with each other.
- the four data connection lines 56 are located between the two VDD transfer lines 50.
- the four data connection lines 56 include a first data connection line, a second data connection line, a third data connection line, and a fourth data connection line that are sequentially parallel in the first direction.
- the first and second data connection lines are located between the first column of sub-pixels and the second column of sub-pixels, and the third and fourth data connection lines are located between the third column of sub-pixels and the fourth column of sub-pixels.
- the sensing shielding layer 13 is located in the middle of the display unit, the sensing shielding layer 13 is located in the light-emitting detection area, and the sensing shielding layer 13 has a block structure.
- the first plate 51 serves as a plate of the first storage capacitor, and is configured to form a first storage capacitor with a second plate formed subsequently, and the first plate 51 also serves as a shielding layer.
- the data connection line 56 is configured to connect two segments of data lines formed subsequently, so that the same column of sub-pixels share one data line.
- the sensing shielding layer 13 is configured to shield the sensing transistor T4 to ensure the performance of the thin film transistor 20.
- the first plate 51 pattern, the VDD transition line 50 pattern, and the fifth sub pixel P5 in the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4 The pattern of the first electrode plate 51 and the pattern of the VDD transfer line 50 in the sixth sub-pixel P6, the seventh sub-pixel P7, and the eighth sub-pixel P8 are mirror-symmetrical with respect to the horizontal axis of the display unit.
- the first metal layer pattern in the first column of sub-pixels (P1 and P5) is different from the first metal layer pattern in the fourth column of sub-pixels (P4 and P8).
- the layer pattern is mirror-symmetrical with respect to the vertical axis of the display unit.
- the first metal layer pattern in the second column of sub-pixels (P2 and P6) and the first metal layer pattern in the third column of sub-pixels (P3 and P7) are relative to the display unit.
- the vertical axis of the sub-pixels in the first column (P1 and P5) is mirror-symmetrical with the first metal layer pattern in the second column of sub-pixels (P2 and P6).
- the third column of sub-pixels (P3 and P6) is mirror-symmetrical.
- the first metal layer pattern in P7) is mirror-symmetrical to the first metal layer pattern in the fourth column of sub-pixels (P4 and P8).
- Forming a pattern of a metal oxide layer includes: sequentially depositing a first insulating film and a metal oxide film on the substrate 10 on which the aforementioned pattern is formed, and patterning the metal oxide film through a patterning process to form a covering first metal Layer pattern of the first insulating layer 14 (also called the buffer layer 14), and the metal oxide layer pattern formed on the first insulating layer, as shown in FIGS. 7 and 8.
- FIG. 7 is an exemplary embodiment of the present disclosure
- FIG. 8 is a schematic diagram of the AA cross-section in FIG. 7. As shown in FIGS.
- the metal oxide layer includes patterns of a first active layer 611, a second active layer 621, a third active layer 631, and a second plate 52 disposed in each sub-pixel, and The pattern of the sensing active layer 21 on the sensing shielding layer 13.
- the first active layer 611 serves as the active layer of the first transistor T1
- the second active layer 621 serves as the active layer of the second transistor T2
- the third active layer 631 serves as the active layer of the third transistor T3.
- the second plate 52 serves as a plate of the first storage capacitor and a plate of the second storage capacitor.
- the second plate 52 is configured to form a second storage capacitor with a third plate formed subsequently.
- the second active layer 621, the third active layer 631, and the second electrode plate 52 are in an integrated structure, so that the drain electrode of the second transistor T2 and the drain electrode of the third transistor T3 can pass through the second electrode after the conduction.
- the plate 52 is electrically connected, and the orthographic projection of the first active layer 611 on the substrate 10 and the orthographic projection of the second active layer 621, the third active layer 631 and the second electrode plate 52 on the substrate 10 are spaced apart, namely There is a gap between the first active layer 611 and the second active layer 621, and there is a gap between the first active layer 611 and the second plate 52, which is beneficial to design the first transistor, the second transistor and the second transistor according to relevant requirements.
- the pattern of the layer 631 and the second plate 52 is the same as the first active layer 611, the second active layer 621, and the first active layer 611, the second active layer 621 and the fifth sub-pixel P5, the sixth sub-pixel P6, the seventh sub-pixel P7, and the eighth sub-pixel P8.
- the patterns of the three active layers 631 and the second electrode plate 52 are mirror-symmetrical with respect to the horizontal axis of the display unit.
- the metal oxide layer pattern in the first column of sub-pixels (P1 and P5) is different from the metal oxide layer pattern in the fourth column of sub-pixels (P4 and P8).
- the layer pattern is mirror-symmetrical with respect to the vertical axis of the display unit.
- the metal oxide layer pattern in the second column of sub-pixels (P2 and P6) and the metal oxide layer pattern in the third column of sub-pixels (P3 and P7) are relative to the display unit
- the vertical axis of the sub-pixels (P1 and P5) in the first column of sub-pixels (P1 and P5) is mirror-symmetrical with the metal oxide layer patterns in the second column of sub-pixels (P2 and P6).
- the third column of sub-pixels (P3 and The metal oxide layer pattern in P7) is mirror-symmetrical to the metal oxide layer pattern in the fourth column of sub-pixels (P4 and P8).
- the orthographic projection of the pattern of the sensing active layer 21 on the substrate 10 is within the orthographic projection range of the sensing light shielding layer 13 on the substrate 10, so that the sensing light shielding layer 13 can completely shield the sensing material.
- the source layer 21 ensures the performance of the sensing transistor T4.
- Forming a second metal layer pattern includes: sequentially depositing a second insulating film and a second metal film on the substrate on which the aforementioned pattern is formed, and patterning the second insulating film and the second metal film through a patterning process to form
- the pattern of the second insulating layer 22 (also called the gate insulating layer 22) and the pattern of the second metal layer disposed on the second insulating layer 22 are shown in FIGS. 9 and 10, which is an exemplary embodiment of the present disclosure.
- FIG. 10 is a schematic diagram of the AA cross-sectional view in FIG. 9 after forming the second metal layer pattern in FIG. As shown in FIGS.
- the second metal layer pattern includes a compensation connection line 642, a control scan line Gn, a sensing scan line G2, and a second power supply line VSS formed in each display unit, and a second power supply line VSS formed in each display unit.
- the compensation connection line 642, the control scan line Gn, the sense scan line G2, and the second power supply line VSS are all arranged along the first direction, that is, the horizontal direction.
- the number of compensation connection lines 642 is two, and each compensation connection line 642 spans four sub-pixels in a corresponding row.
- the compensation connection line 642 is configured to be electrically connected to a compensation line Se1 formed subsequently to provide a compensation signal for each sub-pixel.
- the number of control scan lines Gn is two, and each control scan line Gn straddles the corresponding row of sub-pixels.
- the control scan line Gn straddles the first active layer 611 and the third active layer 631 of each sub-pixel, and the part of the control scan line Gn located above the first active layer 611 is used as the first gate electrode, and the control scan line The portion of Gn located above the third active layer 631 serves as a third gate electrode.
- the second gate electrode 622 is located above the second active layer 621.
- the second metal layer pattern located in the first row of sub-pixels and the second metal layer pattern located in the second row of sub-pixels are relative to the display unit.
- the horizontal axis is mirrored and symmetrical.
- the sensing scan line G2 extends in the first direction, that is, the horizontal direction, in the luminescence detection area, spans different display units, and is located above the sensing active layer 21.
- the portion of the sensing scan line G2 located above the sensing active layer 21 may be used as the gate electrode 23 of the sensing transistor T4.
- the second power line VSS is arranged close to the sensing scan line G2, and the second power line VSS extends in the first direction, that is, the horizontal direction, in the light-emitting detection area, and spans different display units. There is a gap between the orthographic projection of the second power line VSS on the substrate 10 and the orthographic projection of the sensing light shielding layer 13 on the substrate 10, as shown in FIG. 9.
- the second insulating layer pattern is the same as the second metal layer pattern, that is, the second insulating layer is located under the second metal layer, and there is no second insulating layer in regions other than the second metal layer.
- this process further includes conductive treatment.
- Conduction treatment includes after forming the second metal layer pattern, the compensation connection line 642, the control scan line Gn, the sense scan line G2, the second power line VSS and the second gate electrode 622 are used as shields to perform plasma treatment, which is controlled
- the scan line Gn, the second gate electrode 622, and the metal oxide layer shielded by the sensing scan line G2 serve as a transistor
- the metal oxide layer in the region not covered by the second metal layer is processed into a conductive layer to form a conductive second electrode plate 52 and a conductive source/drain region.
- Forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, and patterning the third insulating film through a patterning process to form a third insulating layer 24 (also called Interlayer insulating layer 24).
- FIG. 11 is a schematic diagram after forming a third insulating layer pattern in an exemplary embodiment of the present disclosure
- FIG. 12 is a schematic cross-sectional view taken along line A-A in FIG. 11.
- the third insulating layer 24 is provided with a plurality of via patterns.
- the via pattern includes: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, and a first via V1 located in each sub-pixel.
- the third insulating film in the first via hole V1 and the second via hole V2 is etched away, exposing the surface of the first active layer 611.
- the third insulating film in the third via hole V3 is etched away, exposing the surface of the second active layer 621.
- the third insulating film in the fourth via hole V4 is etched away, exposing the surface of the second gate electrode 622.
- the fifth via hole V5 is a via hole.
- the via hole is composed of two half holes, one half hole is formed on the third active layer 631, the other half hole is formed on the compensation connecting line 642, and the two half holes are formed on the third active layer 631.
- the third insulating film in the hole is etched away, so that the via hole composed of a half hole simultaneously exposes the surface of the third active layer 631 and the surface of the compensation connecting line 642.
- the third insulating film in the sixth via hole V6 is etched away, exposing the surface of the third active layer 631.
- the third insulating film in the seventh via hole V7 is etched away, exposing the surface of the first electrode plate 51.
- the third insulating film in the eighth via hole V8 is etched away, exposing the surface of the control scan line Gn.
- the third insulating film in the ninth via hole V9 is etched away, exposing the surface of the data connection line 56.
- the third insulating film in the tenth via V10 is etched away, exposing the surface of the compensation connection line 642.
- the third insulating film in the two eleventh via holes V11 is etched away, exposing the surface of the VDD transfer wire 50.
- the third insulating film in the twelfth via V12 and the thirteenth via V13 is etched away, exposing the surface of the sensing active layer.
- the third insulating layer in the fourteenth via V14, the fifteenth via V15, and the sixteenth via V16 is etched away, exposing the surface of the second power line VSS.
- the third insulating layer in the seventeenth via hole V17 is etched away, exposing the surface of the sensing light shielding layer 13.
- the third insulating layer in the eighteenth via V18 is etched away, exposing the surface of the sensing scan line G2.
- the via holes located in the upper and lower rows of the sub-pixels of the sensing scan line G2 are mirror-symmetrical with respect to the horizontal axis of the display unit.
- Forming the third metal layer pattern includes: depositing a third metal film on the substrate with the aforementioned pattern, patterning the third metal film through a patterning process, and forming a third metal layer on the third insulating layer 24 pattern.
- FIG. 13 is a schematic diagram after forming a third metal layer pattern in an exemplary embodiment of the present disclosure
- FIG. 14 is a schematic cross-sectional view of A-A in FIG. 13.
- the third metal layer includes: a third plate 53 formed in each sub-pixel, a first source electrode 613 of the first transistor T1, a first drain electrode of the first transistor T1, and a The second source electrode 623 of the second transistor T2, the second drain electrode 624 of the second transistor T2, the third source electrode 633 of the third transistor T3, and the fourth drain electrode of the third transistor T3 (shared with the second drain electrode 624) And a second connecting line 257.
- the third metal layer further includes: a first power line VDD formed on the left and right sides of the display unit, a compensation line Se1, a data line Dn formed between the first power line VDD on the left side and the first column of sub-pixels (P1 and P5) .
- the third metal layer further includes: a sensing line Se2, a sensing source electrode 251 of the sensing transistor T4, a sensing drain electrode 252 of the sensing transistor T4, a VSS transfer line 253, a fourth plate 254, and a fifth plate 255 ⁇ 256 ⁇ And the first connection line 256.
- the data line Dn spans the same column of sub-pixels of two display units, and the data line Dn extends from the sub-pixel of the previous display unit to the same column of sub-pixels of the next display unit.
- the data line Dn is connected to the data connection line 56 through the ninth via V9, thereby forming a data line for providing data to a column of sub-pixels.
- the first source electrode 613 of the first transistor T1 is electrically connected to the first active layer through the first via hole V1.
- the first source electrode 613 and the data line Dn form an integral structure, so that the data line Dn faces the first transistor T1.
- a gate electrode provides data signals.
- the first drain electrode of the first transistor T1 and the third electrode plate 53 are an integral structure, the third electrode plate 53 is connected to the first active layer through the second via hole V2, and the third electrode plate 53 is connected to the first active layer through the fourth via hole V4.
- the second gate electrode 622 of the second transistor T2 is connected, thereby electrically connecting the first drain electrode of the first transistor T1 and the second gate electrode of the second transistor T2.
- the first power line VDD is connected to the VDD transfer line 50 through the eleventh via V11.
- the second source electrode 623 is electrically connected to the VDD transfer line 50 through the sixth via hole V6, and the second source electrode 623 is connected to the second active layer of the second transistor T2 through the third via hole V3, so that the first power supply line VDD
- the VDD high voltage may be supplied to the second source electrode 623 of the second transistor T2.
- the compensation line Se1 is connected to the compensation connection line 642 through the tenth via 10.
- the third source electrode 633 of the third transistor T3 is connected to the third active layer through the fifth via hole V5, and the third source electrode 633 of the third transistor T3 is integrated with the compensation line Se1, so that the compensation line Se1 can be directed toward the third active layer.
- the third source electrode 633 of the three transistor T3 provides a compensation signal.
- the second drain electrode of the second transistor T2 and the third drain electrode of the third transistor T3 are connected through the second plate 52, and the third drain electrode of the third transistor T3 is shared with the second drain electrode 624 of the second transistor T2.
- the second drain electrode 624 is connected to the second electrode plate 52 through the sixth via hole V6.
- the second connection line 257 is connected to the control scan line Gn through the eighth via V8.
- the third metal layer pattern located in the first row of sub-pixels and the third metal layer pattern located in the second row of sub-pixels are relative to the display unit.
- the horizontal axis is mirrored and symmetrical.
- the sensing line Se2 is located at the vertical axis of the display unit, extends in the vertical direction and crosses the same column of display units.
- the sensing line Se2 and the sensing source electrode 251 of the sensing transistor T4 are an integral structure, and the sensing source electrode 251 of the sensing transistor T4 is connected to the sensing active layer of the sensing transistor through the thirteenth via V13, thereby,
- the sensing line Se2 can read a sensing signal from the sensing source electrode 251 of the sensing transistor T4.
- the sensing drain electrode 252 of the sensing transistor T4 is connected to the sensing active layer of the sensing transistor T4 through the twelfth via V12.
- the sensing drain electrode 252 of the sensing transistor T4 is configured to be electrically connected with the first electrode 31 of the PIN-type photodiode 30.
- the VSS transfer line 253 is electrically connected to the second power line VSS through the fifteenth via, and the VSS transfer line 253 is configured to be electrically connected to the second electrode 33 of the PIN-type photodiode 30.
- the fourth plate 254 is electrically connected to the second power line VSS through a sixteenth via hole, and the fifth plate 255 is electrically connected to the second power line VSS through a fourteenth via hole V14.
- the fourth electrode plate 254 and the fifth electrode plate 255 are configured to form a sensing capacitor C2 with the first electrode 31 (plate electrode) of the PIN-type photodiode 30.
- the first connection line 256 is electrically connected to the sensing light shielding layer 13 and the sensing scan line G2 through the seventeenth via V17 and the eighteenth via V18, respectively.
- the first flat layer 11 is formed. This step may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, and coating a first flat film on the fourth insulating film; exposing and developing the first flat film to form the first flat layer 11 pattern.
- FIG. 15 is a schematic diagram after forming a first flat layer pattern in an exemplary embodiment of the present disclosure
- FIG. 16 is a schematic cross-sectional view of A-A in FIG. 15.
- the orthographic projection of the first flat layer 11 on the substrate 10 covers the orthographic projection of the fourth electrode plate 254, the fifth electrode plate 255 and the sensing active layer 21 on the substrate 10.
- the orthographic projection of the first flat layer 11 on the substrate 10 and the orthographic projection of the VSS transfer line 253 on the substrate 10 partially overlap, that is, at least a part of the VSS transfer line 253 is located outside the area where the first flat layer 11 is located.
- the orthographic projection of the first flat layer 11 on the substrate 10 and the orthographic projection of the sensing drain electrode 252 on the substrate 10 partially overlap, that is, at least a part of the sensing drain electrode 252 is located in the area where the first flat layer 11 is located. outside.
- a fifth insulating layer is formed. This step may include: depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, and patterning the fifth insulating film and the fourth insulating film through a patterning process to form the fifth insulating layer 12 and the fourth insulating layer 15. A plurality of via patterns are opened on the fifth insulating layer 12.
- FIG. 17 is a schematic diagram after forming a fifth insulating layer pattern in an exemplary embodiment of the present disclosure
- FIG. 18 is a schematic cross-sectional view taken along the line A-A in FIG. 17.
- the multiple via patterns include: a nineteenth via V19 and a twentieth via V20.
- the nineteenth via hole V19 is located outside the region of the first flat layer 11 and above the sensing drain electrode 252.
- the fifth insulating film and the fourth insulating film in the nineteenth via hole V19 are etched away, exposing the sensing leakage The surface of the pole 252.
- the twentieth via hole V20 is located outside the area of the first flat layer 11 and above the VSS transfer line 253.
- the fifth insulating film and the fourth insulating film in the twentieth via hole V20 are etched away, exposing the VSS switch The surface of wiring 253.
- the multiple via patterns further include: a twenty-first via V21, a twenty-second via V22, and a twenty-third via V23 located in each sub-pixel.
- the twenty-first via V21 is located on the second drain electrode 624 of the second transistor T2, and the fifth insulating film and the fourth insulating film in the twenty-first via V21 are etched away, exposing the second drain electrode 624 s surface.
- the twenty-second via hole V22 is located on the third electrode plate 53, and the fifth insulating film and the fourth insulating film in the twenty-second via hole V22 are etched away, exposing the surface of the third electrode plate 53.
- the twenty-third via hole V23 is located on the second connecting line 257.
- the fifth insulating film and the fourth insulating film in the twenty-third via hole V23 are etched away, exposing the surface of the second connecting line 257.
- the connection line 257 is connected to the control scan line Gn.
- the via pattern located in the sub-pixel is mirror-symmetrical with respect to the vertical symmetry axis.
- the via patterns in the first sub-pixel P1 and the second sub-pixel P2 are mirror-symmetric, and the via patterns in the third sub-pixel P3 and the fourth sub-pixel P4 are mirror-symmetric.
- the via patterns in the upper sub-pixel and the lower sub-pixel are mirror-symmetrical.
- a fourth metal layer pattern is formed. This step may include: depositing a fourth metal layer film on the substrate on which the aforementioned pattern is formed, patterning the fourth metal layer film through a patterning process, and forming a fourth metal layer pattern on the fifth insulating layer 12.
- FIG. 19 is a schematic diagram after forming a fourth metal layer pattern in an exemplary embodiment of the present disclosure
- FIG. 20 is a schematic cross-sectional view taken along line A-A in FIG. 19.
- the fourth metal layer pattern includes: a first barrier 35, a second barrier 36 and a third connecting line 37 located in each sub-pixel.
- the first barrier 35 is connected to the second connecting line 257 through the twenty-third via hole V23, and the second connecting line 257 is connected to the control scan line Gn. Therefore, the first barrier 35 has the same potential as the first gate electrode of the first transistor T1.
- the first baffle plate 25 covers the first transistor T1 and the third transistor T3, and the first baffle plate 25 can prevent subsequent generation of hydrogen from affecting the thin film transistors located under the first baffle plate 25.
- the second baffle 36 is connected to the third electrode plate 53 through the twenty-second via hole V22, so that the second baffle 36 has the same potential as the second gate electrode of the second transistor T2.
- the second baffle 36 covers the second transistor T2, and the second baffle 36 can prevent the subsequently generated hydrogen from affecting the thin film transistors located under the first baffle 25.
- the third connection line 37 is located above the second drain electrode 624 of the second transistor T2, and the third connection line 37 is connected to the second drain electrode 624 of the second transistor T2 through the twenty-first via V21.
- the fourth metal layer pattern located in the sub-pixel is mirror-symmetrical with respect to the vertical symmetry axis.
- the fourth metal layer pattern in the first sub-pixel P1 and the second sub-pixel P2 is mirror-symmetrical
- the fourth metal layer pattern in the third sub-pixel P3 and the fourth sub-pixel P4 is mirror-symmetrical.
- the fourth metal layer patterns in the upper sub-pixels (ie, P1 to P4 sub-pixels) and the lower sub-pixels (ie, P5 to P6 sub-pixels) are mirror-symmetrical.
- the fourth metal layer pattern may further include: a fifth connection line 39, a first electrode 31, and a fourth connection line 38.
- the orthographic projection of the first electrode 31 on the substrate 10 is within the orthographic projection of the first flat layer 11 on the substrate 10.
- the fifth connection line 39 is electrically connected to the sensing drain electrode 252 of the sensing transistor T4 through the nineteenth via.
- the fifth connecting wire 39 and the first electrode 31 are an integral structure, so that the first electrode 31 is electrically connected to the sensing drain electrode 252 through the fifth connecting wire 39.
- the fourth connection line 38 is electrically connected to the VSS transfer line 253 through the twentieth via V20.
- This step may include: depositing a PIN film on the substrate on which the aforementioned pattern is formed, and patterning the PIN film through a patterning process to form a PIN junction.
- FIG. 21 is a schematic diagram after forming a PIN knot pattern in an exemplary embodiment of the present disclosure
- FIG. 22 is a schematic cross-sectional view of A-A in FIG. 21.
- the PIN junction 32 is located on the first electrode 31, and the orthographic projection of the PIN junction 32 on the substrate 10 is within the orthographic projection range of the first electrode 31 on the substrate 10.
- This step may include: depositing a transparent conductive film on the substrate on which the aforementioned pattern is formed, and patterning the transparent conductive film through a patterning process to form a pattern of the third electrode 33.
- FIG. 23 is a schematic diagram after forming a third electrode pattern in an exemplary embodiment of the present disclosure
- FIG. 24 is a schematic cross-sectional view taken along line A-A in FIG. 23.
- the third electrode pattern includes a third electrode 33, and the orthographic projection of the third electrode 33 on the substrate is within the orthographic projection range of the PIN junction 32 on the substrate 10.
- a sixth insulating layer and a second flat layer are formed.
- This step may include: depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed, coating a second flat film on the sixth insulating film; exposing and developing the second flat film, and etching the sixth insulating film, The sixth insulating layer 16 and the second flat layer 17 are formed.
- FIG. 25 is a schematic diagram after the second flat layer pattern is formed in an exemplary embodiment of the present disclosure
- FIG. 26 is a schematic cross-sectional view of A-A in FIG. 25.
- the sixth insulating layer 16 and the second flat layer 17 are provided with a plurality of via patterns, and the plurality of via patterns includes: a twenty-fourth via V24 located in each sub-pixel, And the twenty-fifth via V25 and the twenty-sixth via V26.
- the sixth insulating film and the second flat film in the twenty-fourth via hole V24 are removed, and the surface of the third connecting line 37 is exposed.
- the third connection line 37 is electrically connected to the second drain electrode of the second transistor T2.
- the sixth insulating film and the second flat film in the twenty-fifth via hole V25 are removed, exposing the surface of the third electrode 33.
- the sixth insulating film and the second flat film of the twenty-sixth via V26 are removed, exposing the surface of the fourth connecting line 38.
- the fourth connection line 38 is electrically connected to the VSS transfer line 253.
- This step may include: depositing a transparent conductive film on the substrate on which the aforementioned pattern is formed, and patterning the transparent conductive film through a patterning process to form a transparent conductive layer pattern.
- the transparent conductive layer pattern may include a third electrode 411 in each sub-pixel and a conductive connection line 412.
- the third electrode 411 is connected to the third connection line 37 through the twenty-fourth via V24, and the third connection line 37 is connected to the second drain electrode 624 of the second transistor T2, so that the third electrode 411 is connected to the second transistor T2.
- the second drain electrode 624 is connected.
- the third electrode 411 may be the anode of the light emitting element 40.
- the conductive connection line 412 is connected to the second electrode 33 through the twenty-fifth via V25, the conductive connection line 412 is also connected to the fourth connection line 38 through the twenty-sixth via V26, and the fourth connection line 38 is connected to the second power line.
- VSS is connected, so that the conductive connection line 412 connects the second electrode 33 with the second power supply line VSS.
- the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer may use metal materials, such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo). ), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can be a single-layer structure or a multilayer composite structure, such as Mo/Cu/ Mo et al.
- metal materials such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo).
- alloy materials of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb)
- AlNd aluminum neodymium alloy
- MoNb molybdenum-niobium alloy
- the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer may be silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). Any one or more of) may be a single layer, multiple layers or composite layers.
- the first insulating layer is called the buffer layer, which is used to improve the water and oxygen resistance of the substrate
- the second insulating layer is called the gate insulating (GI) layer
- the third insulating layer is called the interlayer insulation (ILD)
- the fourth insulating layer is called a passivation (PVX) layer.
- the thickness of the second insulating layer is smaller than the thickness of the third insulating layer, and the thickness of the first insulating layer is smaller than the sum of the thickness of the second insulating layer and the third insulating layer. Under the premise of ensuring the insulating effect, the capacity of the storage capacitor is increased.
- the fifth insulating layer is called the passivation protection layer 12.
- the passivation protection layer 12 can be used as a sacrificial layer to protect the first
- the flat layer 11 is not etched during the dry etching process of forming the PIN, thereby avoiding contamination to the sidewall of the PIN, improving the performance of the PIN, ensuring a lower dark current, and improving the optical compensation effect.
- the flat layer can be made of organic materials
- the transparent conductive film can be made of indium tin oxide (ITO) or indium zinc oxide (IZO)
- the pixel definition layer can be made of polyimide, acrylic or polyethylene terephthalate.
- the cathode can be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or made of any one or more of the above metals Alloy.
- the thickness of the first insulating layer is 3000 angstroms to 5000 angstroms
- the thickness of the second insulating layer is 1000 angstroms to 2000 angstroms
- the thickness of the third insulating layer is 4500 angstroms to 7000 angstroms
- the fourth insulating layer has a thickness of 4500 angstroms to 7000 angstroms.
- the thickness of the layer is 3000 angstroms to 5000 angstroms.
- the thickness of the first metal layer is 80 angstroms to 1200 angstroms
- the thickness of the second metal layer is 3000 angstroms to 5000 angstroms
- the thickness of the third metal layer is 3000 angstroms to 9000 angstroms.
- the metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten and indium and zinc, an oxide containing titanium and indium, and an oxide containing titanium. And oxides of indium and tin, oxides containing indium and zinc, oxides containing silicon and indium and tin, or oxides containing indium, gallium and zinc, etc.
- the metal oxide layer may be a single layer, or may be a double layer, or may be a multilayer.
- the embodiments of the present disclosure also provide a method for preparing a display substrate, and the method may include:
- a sensing transistor and a second metal layer are formed on one side of the substrate, the sensing transistor is located in the light-emitting detection area, the second metal layer includes a sensing scan line and a second power line spaced apart from each other, the sensing scan The line and the second power line both extend in the first direction in the light-emitting detection area, and the sensing gate electrode of the sensing transistor is electrically connected to the sensing scan line;
- a first flat layer is formed on the side of the sensing transistor and the second metal layer away from the substrate, the first flat layer is located in the light-emitting detection area, and the first flat layer is on the substrate
- the orthographic projection of includes the sensing transistor
- a passivation protection layer is formed on the side of the first flat layer away from the substrate, and the orthographic projection of the first flat layer on the substrate is located in the orthographic projection range of the passivation protection layer on the substrate Inside;
- a PIN-type photodiode is formed on the side of the passivation protection layer away from the substrate.
- the embodiments of the present disclosure also provide a display device, which includes the display substrate adopting the foregoing embodiments.
- the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and so on.
- the terms “installed”, “connected”, and “connected” should be understood in a broad sense, unless otherwise clearly specified and limited. For example, they may be fixedly connected or detachable. Connected or integrally connected; it may be a mechanical connection or an electrical connection; it may be directly connected, or may be indirectly connected through an intermediary, or may be internal communication between two components. For those of ordinary skill in the art, the specific meanings of the above-mentioned terms in the present disclosure can be understood in specific situations.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Electromagnetism (AREA)
- Life Sciences & Earth Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Sustainable Development (AREA)
- Electroluminescent Light Sources (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Description
Claims (13)
- 一种显示基板,包括多个显示单元,所述显示单元包括多个子像素,所述显示单元内设置有发光检测区域,所述显示基板包括:基底;感测晶体管,设置在所述所基底的一侧,位于所述发光检测区域;第二金属层,设置在所述基底朝向所述感测晶体管的一侧,所述第二金属层包括彼此间隔的感测扫描线和第二电源线,所述感测扫描线和第二电源线在所述发光检测区域均沿第一方向延伸,所述感测晶体管的感测栅电极与所述感测扫描线电连接;第一平坦层,设置在所述感测晶体管和所述第二金属层背离所述基底的一侧,所述第一平坦层位于所述发光检测区域,所述第一平坦层在所述基底上的正投影包含所述感测晶体管;钝化保护层,设置在所述第一平坦层背离所述基底的一侧,所述第一平坦层在所述基底上的正投影位于所述钝化保护层在所述基底上的正投影范围内;PIN型光电二极管,设置在所述钝化保护层背离所述基底的一侧。
- 根据权利要求1所述的显示基板,其中,所述钝化保护层在垂直于所述基底方向的厚度为800埃至1200埃。
- 根据权利要求1所述的显示基板,其中,所述PIN型光电二极管包括沿远离所述钝化保护层的方向依次层叠设置的第一电极、PIN结和第二电极,所述第一电极在所述基底上的正投影位于所述第一平坦层在所述基底上的正投影范围内。
- 根据权利要求3所述的显示基板,其中,所述第一电极在所述基底上的正投影边界与所述第一平坦层在所述基底上的正投影边界之间的距离为d1,2μm≤d1≤4μm。
- 根据权利要求3所述的显示基板,其中,所述PIN结在所述基底上的正投影位于所述第一电极在所述基底上的正投影范围内,所述PIN结在所述 基底上的正投影边界与所述第一电极在所述基底上的正投影边界之间的距离为d2,1μm≤d2≤3μm。
- 根据权利要求3所述的显示基板,其中,所述显示基板还包括设置在所述PIN型光电二极管背离所述基底一侧的透明导电层,所述透明导电层包括彼此断开的导电连接线和第三电极,所述第三电极位于子像素区域,所述显示基板还包括与所述第一电极位于同一层的第四连接线,所述第四连接线从所述发光检测区域内延伸至所述发光检测区域之外,所述导电连接线位于所述发光检测区域之内的部分与所述第二电极电连接,所述导电连接线位于所述发光检测区域之外的部分与所述第四连接线电连接,所述第四连接线与所述第二电源线电连接。
- 根据权利要求6所述的显示基板,其中,所述显示基板还包括设置在所述透明导电层背离所述基底一侧的有机发光层以及设置在所述有机发光层背离所述基底一侧的第四电极,所述第三电极、有机发光层和所述第四电极构成发光元件,所述发光元件位于子像素区域内,所述PIN型光电二极管在所述基底上的正投影与显示单元中每个子像素的发光元件在所述基底上的正投影均存在交叠区域。
- 根据权利要求3所述的显示基板,其中,所述显示基板还可以包括位于发光检测区域的感测电容,所述显示基板还包括与所述感测晶体管的感测漏电极或感测源电极位于同一层的第四极板和第五极板,所述第四极板和所述第五极板在第一方向上分别位于所述感测晶体管的两侧,所述第四极板和所述第五极板均与所述第二电源线电连接,所述第四极板在所述基底上的正投影与所述第三电极在所述基底上的正投影存在交叠区域,以形成第一感测电容,所述第五极板在所述基底上的正投影与所述第三电极在所述基底上的正投影存在交叠区域,以形成第二感测电容,所述感测电容包括第一感测电容和第二感测电容。
- 根据权利要求1至8中任意一项所述的显示基板,其中,所述显示单元包括八个子像素,八个子像素呈两行四列阵列式排布,每个子像素的驱动电路位于子像素区域远离另一行子像素的一侧,所述发光检测区域在第二方向上位于显示单元的中部,所述第二方向为与所述第一方向相垂直的方向。
- 根据权利要求1至8中任意一项所述的显示基板,其中,所述显示基板还包括位于所述基底和所述感测晶体管之间的第一金属层,所述第一金属层包括感测遮光层,所述感测遮光层在所述基底上的正投影包含所述感测晶体管的感测有源层在所述基底上的正投影,所述感测遮光层与所述感测扫描线电连接。
- 根据权利要求1至8中任意一项所述的显示基板,其中,所述感测晶体管在所述基底上的正投影与所述PIN型光电二极管在所述基底上的正投影至少部分重叠。
- 一种显示基板的制备方法,所述显示基板包括多个显示单元,所述显示单元包括多个子像素,所述显示单元内设置有发光检测区域,所述方法包括:在基底的一侧形成感测晶体管和第二金属层,所述感测晶体管位于发光检测区域,所述第二金属层包括彼此间隔的感测扫描线和第二电源线,所述感测扫描线和第二电源线在所述发光检测区域均沿第一方向延伸,所述感测晶体管的感测栅电极与所述感测扫描线电连接;在所述感测晶体管和所述第二金属层背离所述基底的一侧形成第一平坦层,所述第一平坦层位于所述发光检测区域,所述第一平坦层在所述基底上的正投影包含所述感测晶体管;在所述第一平坦层背离所述基底的一侧形成钝化保护层,所述第一平坦层在所述基底上的正投影位于所述钝化保护层在所述基底上的正投影范围内;在所述钝化保护层背离所述基底的一侧形成PIN型光电二极管。
- 一种显示装置,包括权利要求1至11中任意一项所述的显示基板。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010344100.1A CN111509014B (zh) | 2020-04-27 | 2020-04-27 | 一种显示基板及其制备方法、显示装置 |
CN202010344100.1 | 2020-04-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2021218425A1 true WO2021218425A1 (zh) | 2021-11-04 |
Family
ID=71864928
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2021/080055 WO2021218425A1 (zh) | 2020-04-27 | 2021-03-10 | 显示基板及其制备方法、显示装置 |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN111509014B (zh) |
WO (1) | WO2021218425A1 (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111509014B (zh) * | 2020-04-27 | 2022-05-06 | 京东方科技集团股份有限公司 | 一种显示基板及其制备方法、显示装置 |
WO2022099587A1 (zh) * | 2020-11-13 | 2022-05-19 | 京东方科技集团股份有限公司 | 有机电致发光显示基板及制作方法、显示面板、显示装置 |
CN113113437B (zh) * | 2021-03-29 | 2022-09-09 | 武汉华星光电技术有限公司 | 阵列基板及其制备方法 |
EP4207296A4 (en) | 2021-04-30 | 2024-05-29 | BOE Technology Group Co., Ltd. | DISPLAY SUBSTRATE AND DISPLAY DEVICE |
CN116210046A (zh) * | 2021-09-30 | 2023-06-02 | 京东方科技集团股份有限公司 | 显示基板及其制备方法、显示装置 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120168761A1 (en) * | 2011-01-05 | 2012-07-05 | Electronics And Telecommunications Research Institute | Active matrix organic light emitting diode and method for manufacturing the same |
CN110660356A (zh) * | 2019-09-30 | 2020-01-07 | 京东方科技集团股份有限公司 | 一种显示基板及其制作方法、显示装置 |
CN110718575A (zh) * | 2019-10-22 | 2020-01-21 | 京东方科技集团股份有限公司 | 透明oled显示面板、显示装置和驱动方法 |
CN110767722A (zh) * | 2019-09-11 | 2020-02-07 | 京东方科技集团股份有限公司 | 一种显示基板及其制作方法、显示面板及显示装置 |
CN110808272A (zh) * | 2019-11-14 | 2020-02-18 | 京东方科技集团股份有限公司 | 一种显示面板及其制备方法、显示装置 |
CN110867473A (zh) * | 2019-11-26 | 2020-03-06 | 京东方科技集团股份有限公司 | 显示基板、显示面板及显示装置 |
CN111509014A (zh) * | 2020-04-27 | 2020-08-07 | 京东方科技集团股份有限公司 | 一种显示基板及其制备方法、显示装置 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102546985B1 (ko) * | 2016-11-21 | 2023-06-27 | 엘지디스플레이 주식회사 | 대면적 초고해상도 평판 표시장치 |
-
2020
- 2020-04-27 CN CN202010344100.1A patent/CN111509014B/zh active Active
-
2021
- 2021-03-10 WO PCT/CN2021/080055 patent/WO2021218425A1/zh active Application Filing
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120168761A1 (en) * | 2011-01-05 | 2012-07-05 | Electronics And Telecommunications Research Institute | Active matrix organic light emitting diode and method for manufacturing the same |
CN110767722A (zh) * | 2019-09-11 | 2020-02-07 | 京东方科技集团股份有限公司 | 一种显示基板及其制作方法、显示面板及显示装置 |
CN110660356A (zh) * | 2019-09-30 | 2020-01-07 | 京东方科技集团股份有限公司 | 一种显示基板及其制作方法、显示装置 |
CN110718575A (zh) * | 2019-10-22 | 2020-01-21 | 京东方科技集团股份有限公司 | 透明oled显示面板、显示装置和驱动方法 |
CN110808272A (zh) * | 2019-11-14 | 2020-02-18 | 京东方科技集团股份有限公司 | 一种显示面板及其制备方法、显示装置 |
CN110867473A (zh) * | 2019-11-26 | 2020-03-06 | 京东方科技集团股份有限公司 | 显示基板、显示面板及显示装置 |
CN111509014A (zh) * | 2020-04-27 | 2020-08-07 | 京东方科技集团股份有限公司 | 一种显示基板及其制备方法、显示装置 |
Also Published As
Publication number | Publication date |
---|---|
CN111509014B (zh) | 2022-05-06 |
CN111509014A (zh) | 2020-08-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2021218425A1 (zh) | 显示基板及其制备方法、显示装置 | |
WO2022037287A1 (zh) | 显示基板和显示装置 | |
WO2021227744A1 (zh) | 显示基板及其制备方法、显示装置 | |
WO2021212313A1 (zh) | 显示基板及其制备方法、显示装置 | |
US20220262886A1 (en) | Display substrate and method for manufacturing the same, and display apparatus | |
US11985842B2 (en) | Display substrate with display area having different pixel density regions, method of manufacturing the same, and electronic apparatus | |
KR20180068634A (ko) | 유기 발광 표시 장치 | |
KR20140143916A (ko) | 유기 발광 표시 장치 및 이의 제조 방법 | |
WO2021227040A9 (zh) | 显示基板及其制备方法、显示装置 | |
US11895879B2 (en) | Display substrate and preparation method thereof, and display apparatus | |
WO2022001405A1 (zh) | 显示基板及其制备方法、显示装置 | |
US11882729B2 (en) | Display substrate and method for manufacturing the same, and display apparatus | |
CN218447107U (zh) | 显示基板及显示装置 | |
WO2024055785A1 (zh) | 显示基板及显示装置 | |
CN111682031A (zh) | 一种显示基板及其制备方法、显示装置 | |
WO2021227065A1 (zh) | 显示面板和电子装置 | |
WO2022017050A1 (zh) | 显示基板及其制备方法、显示装置 | |
WO2024060884A1 (zh) | 显示基板及其制备方法、显示装置 | |
US20220344448A1 (en) | Display Substrate and Preparation Method Thereof, and Display Apparatus | |
CN113555400A (zh) | 显示基板及其制备方法、显示装置 | |
US20230363208A1 (en) | Display Substrate, Manufacturing Method Thereof, and Display Apparatus | |
CN114981973A (zh) | 显示基板及其制备方法、显示装置 | |
WO2023050347A1 (zh) | 显示基板及其制备方法、显示装置 | |
US20240224599A1 (en) | Display substrate, manufacturing method thereof and display device | |
WO2024113186A1 (zh) | 一种显示基板及其制备方法、显示装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 21796180 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 21796180 Country of ref document: EP Kind code of ref document: A1 |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 21796180 Country of ref document: EP Kind code of ref document: A1 |
|
32PN | Ep: public notification in the ep bulletin as address of the adressee cannot be established |
Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 30/06/2023) |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 21796180 Country of ref document: EP Kind code of ref document: A1 |