WO2021238478A1 - 一种显示面板及其制作方法、显示装置 - Google Patents

一种显示面板及其制作方法、显示装置 Download PDF

Info

Publication number
WO2021238478A1
WO2021238478A1 PCT/CN2021/087372 CN2021087372W WO2021238478A1 WO 2021238478 A1 WO2021238478 A1 WO 2021238478A1 CN 2021087372 W CN2021087372 W CN 2021087372W WO 2021238478 A1 WO2021238478 A1 WO 2021238478A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
transistor
pixel
orthographic projection
sub
Prior art date
Application number
PCT/CN2021/087372
Other languages
English (en)
French (fr)
Inventor
尚庭华
周洋
于鹏飞
罗正位
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/637,248 priority Critical patent/US20220285458A1/en
Publication of WO2021238478A1 publication Critical patent/WO2021238478A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel, a manufacturing method thereof, and a display device.
  • a light-emitting function layer is provided on the side of the anode layer facing away from the substrate of the display panel, and a flat layer is provided on the side of the anode layer facing the substrate
  • the material of the flat layer is generally polyimide organic polymer.
  • the polyimide polymer material is generally formed by the polymerization of oligomers.
  • the by-product during the polymerization reaction is water, and polyimide also has certain characteristics. The water absorption.
  • the conventional heating method cannot completely release the water molecules in the flat layer.
  • the water molecules in the flat layer will escape during the use of the display product. Corrodes the light-emitting functional layer, shortening the life of the display product.
  • the purpose of the present disclosure is to provide a display panel, a manufacturing method thereof, and a display device.
  • a first aspect of the present disclosure provides a display panel, including: a substrate, and a plurality of pixel units arranged on the substrate, the plurality of pixel units are arranged in an array, and each pixel unit includes a plurality of sub-pixels;
  • the sub-pixel includes a sub-pixel driving circuit, a flat layer, and an anode pattern that are sequentially stacked in a direction away from the substrate; the anode pattern in at least part of the sub-pixel includes a middle part and an edge part surrounding the middle part,
  • the surface of the flat layer facing away from the substrate has a groove, and the orthographic projection of the groove on the substrate surrounds the orthographic projection of the middle part on the substrate, and at least part of the edge part is on the substrate.
  • the orthographic projection on the substrate is located inside the orthographic projection of the groove on the substrate.
  • the groove includes a groove bottom and a groove wall, and the orthographic projection of the edge portion on the substrate overlaps the orthographic projection of the groove bottom of the groove on the substrate.
  • the sub-pixels further include a compensation pattern located on the side of the flat layer facing the substrate, the orthographic projection of the compensation pattern on the substrate and at least part of the grooves in the flat layer The orthographic projections on the base overlap.
  • the orthographic projection of the compensation pattern on the substrate overlaps the orthographic projection of the middle part of the anode pattern on the substrate.
  • the pixel unit includes a red sub-pixel, a blue sub-pixel, and a green sub-pixel; the red sub-pixel and the green sub-pixel are located in the same column along the second direction, and the blue sub-pixel Located in the other column; the green sub-pixels include:
  • a first power signal line pattern, at least a part of the first power signal line pattern extends along the second direction;
  • a first flat layer, a rectangular first groove is formed on the first flat layer, and the first groove includes a first portion and a second portion that are opposed to each other along the second direction, and are opposed to each other along the first direction.
  • the third part and the fourth part are arranged, and the orthographic projection of the first part on the substrate overlaps the orthographic projection of the first compensation pattern on the substrate.
  • the pixel unit includes a red sub-pixel, a blue sub-pixel, and a green sub-pixel; the red sub-pixel and the green sub-pixel are located in the same column along the second direction, and the blue sub-pixel Located in the other column; the blue sub-pixels include:
  • a second power signal line pattern, at least part of the second power signal line pattern extends along the second direction;
  • a second compensation pattern coupled to the second power signal line pattern, the second compensation pattern protruding from the second power signal line pattern along a first direction, and the second compensation pattern along the second direction extend;
  • a second flat layer, a rectangular second groove is formed on the second flat layer, and the second groove includes a fifth part and a sixth part opposite to each other along the second direction, and along the first direction
  • the seventh part and the eighth part are arranged oppositely, and the orthographic projection of the seventh part on the substrate overlaps the orthographic projection of the second compensation pattern on the substrate.
  • the sub-pixel includes a power signal line pattern, at least a part of the power signal line pattern extends along a second direction, and the power signal line pattern includes a first power source portion and a second power source portion along a line perpendicular to the In the direction of the second direction, the width of the first power supply part is greater than the width of the second power supply part;
  • the orthographic projection of the first power supply portion on the substrate overlaps the orthographic projection of the middle part of the anode pattern on the substrate.
  • the sub-pixel further includes:
  • a power signal line pattern, at least a part of the power signal line pattern extends along the second direction;
  • a data line pattern, at least a part of the data line pattern extends along the second direction;
  • the sub-pixel driving circuit includes a driving transistor.
  • the orthographic projection of the power signal line pattern on the substrate, and the orthographic projection of the output electrode of the driving transistor on the substrate are the same as the orthographic projection on the substrate. Between the orthographic projections of the data line graphics on the substrate;
  • the orthographic projection of the power signal line pattern on the substrate overlaps the orthographic projection of the groove of the flat layer on the substrate; and/or the orthographic projection of the power signal line pattern on the substrate The projection overlaps with the orthographic projection of the middle part of the anode pattern on the substrate;
  • the orthographic projection of the data line pattern on the substrate overlaps with the orthographic projection of the groove of the flat layer on the substrate; and/or the orthographic projection of the data line pattern on the substrate overlaps The orthographic projections of the middle part of the anode pattern on the substrate overlap.
  • the sub-pixel further includes:
  • a first conductive connection portion, at least part of the first conductive connection portion extends along the second direction;
  • the sub-pixel driving circuit includes a driving transistor and a first transistor, a first electrode of the first transistor is coupled to a second electrode of the driving transistor, and the second electrode of the first transistor passes through the first conductive
  • the connecting portion is coupled to the gate of the driving transistor
  • the orthographic projection of the first conductive connection portion on the substrate overlaps the orthographic projection of the groove of the flat layer on the substrate; and/or the first conductive connection portion is on the substrate
  • the orthographic projection of is overlapped with the orthographic projection of the middle part of the anode pattern on the substrate.
  • the sub-pixel further includes:
  • a second conductive connection portion extends along the second direction
  • An initialization signal line pattern extends in a first direction, and the first direction intersects the second direction;
  • a reset signal line pattern the reset signal line pattern extending along the first direction
  • the sub-pixel driving circuit includes a seventh transistor, the gate of the seventh transistor is coupled to the corresponding reset signal line pattern, and the first electrode of the seventh transistor is connected to the corresponding initialization via the second conductive connection portion.
  • the signal line pattern is coupled, and the second electrode of the seventh transistor is coupled to the corresponding anode pattern;
  • the orthographic projection of the second conductive connection portion on the substrate overlaps the orthographic projection of the groove of the flat layer on the substrate; and/or, the second conductive connection portion is on the substrate
  • the orthographic projection of is overlapped with the orthographic projection of the middle part of the anode pattern on the substrate.
  • the sub-pixel further includes:
  • the pixel defining layer located on the side of the anode pattern facing away from the substrate, the pixel defining layer has a pixel opening, and the orthographic projection of the pixel opening on the substrate is located in the middle of the anode pattern. The interior of the orthographic projection on the substrate.
  • the sub-pixels are distributed in an array, and the sub-pixels further include:
  • Power signal line pattern data line pattern, initialization signal line pattern, gate line pattern, light emission control signal line pattern, reset signal line pattern, first conductive connection part and second conductive connection part;
  • the sub-pixel driving circuit includes: a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;
  • the gate of the driving transistor is coupled to the second electrode of the first transistor through the corresponding first conductive connection portion, and the first electrode of the driving transistor is coupled to the second electrode of the fifth transistor , The second electrode of the driving transistor is coupled to the first electrode of the first transistor;
  • the gate of the first transistor is coupled to the gate line pattern
  • the gate of the second transistor is coupled to the reset signal line pattern in the next sub-pixel adjacent in the second direction, and the first electrode of the second transistor is connected to the next adjacent sub-pixel in the second direction.
  • the initialization signal line pattern in the sub-pixel is coupled, and the second electrode of the second transistor is coupled to the gate of the driving transistor;
  • the gate of the fourth transistor is coupled to the gate line pattern, the first electrode of the fourth transistor is coupled to the data line pattern, and the second electrode of the fourth transistor is connected to the driving transistor.
  • the gate of the fifth transistor is coupled to the light emission control signal line pattern, and the first electrode of the fifth transistor is coupled to the power signal line pattern;
  • the gate of the sixth transistor is coupled to the light emission control signal line pattern, the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor is coupled to the The light-emitting element in the sub-pixel is coupled;
  • the gate of the seventh transistor is coupled to the corresponding reset signal line pattern, the first electrode of the seventh transistor is coupled to the corresponding initialization signal line pattern, and the second electrode of the seventh transistor is coupled to the corresponding anode Graphics coupling.
  • a second aspect of the present disclosure provides a display device including the above-mentioned display panel.
  • a third aspect of the present disclosure provides a manufacturing method of a display panel, the manufacturing method includes:
  • fabricating a plurality of pixel units on a substrate the plurality of pixel units are arranged in an array, and each pixel unit includes a plurality of sub-pixels;
  • the sub-pixel includes a sub-pixel driving circuit, a flat layer, and an anode pattern that are sequentially stacked in a direction away from the substrate; the anode pattern in at least part of the sub-pixel includes a middle part and an edge part surrounding the middle part,
  • the surface of the flat layer facing away from the substrate has a groove, the orthographic projection of the groove on the substrate surrounds the orthographic projection of the middle part on the substrate, and at least part of the edge part is on the substrate.
  • the orthographic projection on the substrate is located inside the orthographic projection of the groove on the substrate.
  • the sub-pixel includes a power signal line pattern and a compensation pattern
  • the manufacturing method further includes:
  • the power signal line pattern and the compensation pattern are formed at the same time, the compensation pattern is located on the surface of the flat layer facing the substrate, and the orthographic projection of the compensation pattern on the substrate is at least part of the The orthographic projection of the groove of the flat layer on the substrate overlaps, and/or the orthographic projection of the compensation pattern on the substrate overlaps the orthographic projection of the middle part of the anode pattern on the substrate .
  • FIG. 1 is a circuit diagram of a sub-pixel driving circuit provided by an embodiment of the disclosure
  • FIG. 2 is a timing diagram of a sub-pixel driving circuit provided by an embodiment of the disclosure
  • FIG. 3 is a schematic diagram of the layout of three sub-pixel driving circuits provided by an embodiment of the disclosure.
  • FIG. 4 is a schematic diagram of the layout of the active layer in FIG. 3;
  • FIG. 5 is a schematic diagram of the layout of the first gate metal layer in FIG. 3;
  • FIG. 6 is a schematic diagram of the layout of the second gate metal layer in FIG. 3;
  • FIG. 7 is a schematic diagram of the layout of the source and drain metal layers in FIG. 3;
  • FIG. 8 is a schematic diagram of the anode pattern and the layout of the source and drain metal layers in FIG. 3;
  • Fig. 9 is a schematic cross-sectional view along the A1A2 direction in Fig. 8;
  • FIG. 10 is a schematic diagram of the layout of the source and drain metal layers and the trenches in the flat layer provided by the embodiments of the present disclosure
  • FIG. 11 is a schematic diagram of a single-layer layout of the source and drain metal layers in FIG. 10;
  • FIG. 12 is a schematic diagram of the layout of the trenches in the flat layer in FIG. 10; FIG.
  • FIG. 13 is a schematic diagram of the layout of the flat layer trenches and anode patterns provided by the embodiments of the disclosure.
  • Fig. 14 is a schematic cross-sectional view taken along the direction B1B2 in Fig. 13;
  • Fig. 15 is a schematic cross-sectional view taken along the direction C1C2 in Fig. 13;
  • Fig. 16 is a schematic cross-sectional view taken along the direction D1D2 in Fig. 13.
  • each pixel unit includes a plurality of sub-pixels.
  • Each sub-pixel includes a sub-pixel driving circuit, a power signal line pattern 901, a data line pattern 908, a gate line pattern 902, a light-emission control signal line pattern 903, a reset signal line pattern 905, an initialization signal line pattern 904, and an anode pattern 320; At least part of the power signal line pattern 901 and the data line pattern 908 extend along the second direction; the gate line pattern 902, the light-emitting control signal line pattern 903, the reset signal line pattern 905, and the initialization signal
  • the line patterns 904 all extend along a first direction, and the first direction intersects the second direction.
  • the first direction includes the X direction
  • the second direction includes the Y direction.
  • the multiple sub-pixel drive circuits included in the display panel can be divided into multiple rows of sub-pixel drive circuits arranged in sequence along the second direction, and multiple columns of sub-pixel drive circuits arranged in sequence along the first direction.
  • the initialization signal line patterns 904 corresponding to the sub-pixel driving circuits in the same row are electrically connected in order to form an integrated structure;
  • the gate line patterns 902 corresponding to the sub-pixel driving circuits in the same row are electrically connected in order to form
  • the light-emitting control signal line patterns 903 corresponding to the sub-pixel drive circuits located in the same row are electrically connected in order to form an integrated structure;
  • the reset signal line patterns 905 corresponding to the sub-pixel drive circuits located in the same row are sequentially electrically connected Are connected to form an integrated structure;
  • the data line patterns 908 corresponding to the sub-pixel drive circuits located in the same column are electrically connected in sequence to form an integrated structure;
  • each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits sequentially arranged along the X direction.
  • the initialization signal line pattern 904, the gate line pattern 902, the light emission control signal line pattern 903, and the reset signal line pattern 905 are all arranged in the X direction.
  • the multiple sub-pixel driving circuits included in each row of sub-pixel driving circuits can respectively correspond to the initialization signal line pattern 904, the gate line pattern 902, the light emission control signal line pattern 903, and the reset signal line pattern 905.
  • Each column of sub-pixel drive circuits includes a plurality of sub-pixel drive circuits arranged in sequence along the Y direction, the data line pattern 908 and the power signal line pattern 901 both extend along the Y direction, and each column of sub-pixel drive circuit includes multiple sub-pixel drive circuits
  • the pixel driving circuits can be respectively coupled to the corresponding data line pattern 908 and power signal line pattern 901.
  • the sub-pixel driving circuit includes 7 thin film transistors and 1 capacitor.
  • Each transistor included in the sub-pixel driving circuit adopts a P-type transistor, wherein the first transistor T1 has a double-gate structure, the gate 201g of the first transistor T1 is coupled to the gate line pattern 902, and the source S1 of the first transistor T1 It is coupled to the drain D3 of the third transistor T3 (ie, the driving transistor), and the drain D1 of the first transistor T1 is coupled to the gate 203g of the third transistor T3.
  • the second transistor T2 has a double-gate structure.
  • the gate 202g of the second transistor T2 is coupled to the reset signal line pattern 905' in the next sub-pixel adjacent in the second direction.
  • the source of the second transistor T2 The pole S2 is coupled to the initialization signal line pattern 904' in the next sub-pixel, and the drain D2 of the second transistor T2 is coupled to the gate 203g of the third transistor T3.
  • the gate 204g of the fourth transistor T4 is coupled to the gate line pattern 902, the source S4 of the fourth transistor T4 is coupled to the data line pattern 908, and the drain D4 of the fourth transistor T4 is coupled to the source of the third transistor T3. S3 is coupled.
  • the gate 205g of the fifth transistor T5 is coupled to the light emission control signal line pattern 903, the source S5 of the fifth transistor T5 is coupled to the power signal line pattern 901, and the drain D5 of the fifth transistor T5 is coupled to the source of the third transistor T3 ⁇ S3 is coupled.
  • the gate 206g of the sixth transistor T6 is coupled to the light emission control signal line pattern 903, the source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is coupled to the anode pattern catch.
  • the gate 207g of the seventh transistor T7 is coupled to the reset signal line pattern 905, the drain D7 of the seventh transistor T7 is coupled to the anode pattern, and the source S7 of the seventh transistor T7 is coupled to the initialization signal line pattern 904 catch.
  • the first plate Cst1 of the storage capacitor Cst is multiplexed as the gate 203g of the third transistor T3, and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern 901.
  • each work cycle includes a reset period P1, a write compensation period P2, and a light emitting period P3.
  • E1 represents the emission control signal transmitted on the emission control signal line pattern 903 in the current sub-pixel
  • R1 represents the reset signal transmitted on the reset signal line pattern 905 in the current sub-pixel
  • D1 represents the data in the current sub-pixel.
  • the data signal transmitted on the line pattern 908, G1 represents the gate scan signal transmitted on the gate line pattern 902 in the current sub-pixel
  • R1' represents the reset in the next sub-pixel adjacent to the current sub-pixel in the second direction
  • the reset signal transmitted on the signal line pattern 905' When the display panel function is working, scan line by line from bottom to top.
  • the reset signal input by the reset signal line pattern 905' is at an active level
  • the second transistor T2 is turned on
  • the initialization signal transmitted by the initialization signal line pattern 904' is input to the third
  • the gate 203g of the transistor T3 makes the gate-source voltage Vgs held on the third transistor T3 in the previous frame cleared to reset the gate 203g of the third transistor T3.
  • the reset signal input from the reset signal line pattern 905' is at an inactive level
  • the second transistor T2 is turned off
  • the gate scanning signal input from the gate line pattern 902 is at an active level
  • controls the first transistor T1 and the fourth transistor T4 are turned on
  • the data line pattern 908 writes a data signal, and is transmitted to the source S3 of the third transistor T3 through the fourth transistor T4, and at the same time, the first transistor T1 and the fourth transistor T4 are turned on
  • the third transistor T3 is formed into a diode structure. Therefore, the first transistor T1, the third transistor T3, and the fourth transistor T4 work together to realize the threshold voltage compensation of the third transistor T3.
  • the potential of the gate 203g of the third transistor T3 is controlled to finally reach Vdata+Vth, where Vdata represents the voltage value of the data signal, and Vth represents the threshold voltage of the third transistor T3.
  • the reset signal input by the reset signal line pattern 905 is at an active level
  • the seventh transistor T7 is controlled to be turned on
  • the initialization signal transmitted by the initialization signal line pattern 904 is input to the anode of the light-emitting element EL , Control the light-emitting element EL to not emit light.
  • the light emission control signal written in the light emission control signal line pattern 903 is at an effective level, and the fifth transistor T5 and the sixth transistor T6 are controlled to be turned on, so that the power signal transmitted by the power signal line pattern 901 is input to the third The source S3 of the transistor T3, and the gate 203g of the third transistor T3 is kept at Vdata+Vth, so that the third transistor T3 is turned on.
  • the corresponding gate-source voltage of the third transistor T3 is Vdata+Vth-VDD, where VDD is According to the voltage value corresponding to the power signal, the leakage current generated based on the gate-source voltage flows to the anode of the corresponding light-emitting element EL to drive the corresponding light-emitting element EL to emit light.
  • each film layer corresponding to the display sub-pixel drive circuit is as follows:
  • the active film layer, the gate insulating layer, the first gate metal layer, the first interlayer insulating layer, the second gate metal layer, the second interlayer insulating layer, the first source and drain are stacked in sequence in the direction away from the substrate The metal layer and the third interlayer insulating layer.
  • the active film layer is used to form the channel region (such as 101pg ⁇ 107pg) of each transistor in the display sub-pixel driving circuit, the source formation region and the drain formation region, the source formation region and the drain
  • the active film layer corresponding to the formation region has better conductivity than the active film layer corresponding to the channel region due to the doping effect;
  • the active film layer can be made of amorphous silicon, polysilicon, oxide semiconductor materials, etc.
  • the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the active film layer corresponding to the source formation region and the drain formation region can directly serve as the corresponding source (such as: S1 to S7) and drain (such as: D1 to D7), or also
  • the source electrode contacting the source electrode formation region can be made of a metal material
  • the drain electrode contacting the drain electrode formation region can be made of a metal material.
  • the first gate metal layer is used to form the gate of each transistor in the sub-pixel driving circuit (e.g., 201g ⁇ 207g), and the gate line pattern 902, the light emission control signal line pattern 903, and the reset
  • the signal line pattern 905 and other structures, the gate 203g of the third transistor T3 in each sub-pixel driving circuit is multiplexed as the first plate Cst1 of the second storage capacitor Cst in the sub-pixel driving circuit.
  • the second gate metal layer is used to form a second plate Cst2 of the second storage capacitor Cst, a shielding pattern 801 with a shielding effect, and an initialization signal line pattern 904 included in the display substrate.
  • the first source/drain metal layer is used to form a data line pattern 908, a power signal line pattern 901 and some conductive connections included in the display panel.
  • the gate 201g of the first transistor T1 covers the first channel region 101pg
  • the gate 202g of the second transistor T2 covers the second channel region 102pg
  • the gate of the third transistor T3 The gate 203g covers the third channel region 103pg
  • the gate 204g of the fourth transistor T4 covers the fourth channel region 104pg
  • the gate 205g of the fifth transistor T5 covers the fifth channel region 105pg
  • the gate of the sixth transistor T6 206g covers the sixth channel region 106pg
  • the gate 207g of the seventh transistor T7 covers the seventh channel region 107pg.
  • the gate 203g of the third transistor T3 is multiplexed as the first plate Cst1 of the storage capacitor Cst, and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern 901.
  • the gate 204g of the fourth transistor T4 in the second direction (such as the Y direction), the gate 204g of the fourth transistor T4, the gate 201g of the first transistor T1, and the gate of the second transistor T2
  • the gate 202g is located on the first side of the gate of the driving transistor (that is, the gate 203g of the third transistor T3), the gate of the seventh transistor T7, the gate 206g of the sixth transistor T6, and the gate of the fifth transistor T5 They are all located on the second side of the gate of the driving transistor.
  • the first side and the second side of the gate of the driving transistor are two opposite sides along the second direction. Further, the first side of the gate of the driving transistor may be the bottom of the gate of the driving transistor.
  • the second side of the gate of the driving transistor may be the upper side of the gate of the driving transistor.
  • the lower side for example, the side of the display panel for bonding the IC is the lower side of the display panel, and the lower side of the gate of the driving transistor is the side of the gate of the driving transistor closer to the IC.
  • the upper side is the opposite side of the lower side, for example, the side of the gate of the driving transistor farther away from the IC.
  • the gate 204g of the fourth transistor T4 and the gate 205g of the fifth transistor T5 are both located on the third side of the gate of the driving transistor, and the gate 201g of the first transistor T1 and the second transistor T1
  • the gates 206g of the six transistors T6 are all located on the fourth side of the gate of the driving transistor.
  • the third side and the fourth side of the gate of the driving transistor are opposite sides along the first direction; further, the third side of the gate of the driving transistor may be the right side of the gate of the driving transistor, The fourth side of the gate of the driving transistor may be the left side of the gate of the driving transistor.
  • the data line pattern 908 is located on the right side of the power signal line pattern 901
  • the power signal line pattern 901 is located on the left side of the data line pattern 908.
  • Figure 9 is a schematic cross-sectional view along the A1A2 direction in Figure 8.
  • the black origin in Figure 9 represents water molecules
  • the dashed line with arrows in Figure 9 represents the diffusion path of water molecules. It can be seen that although the channel for the diffusion of water molecules to the right is narrowed in the direction perpendicular to the substrate of the display panel, there is still a larger diffusion channel to the left, so that the water molecules can still perform the light-emitting function along the left channel.
  • the layer EL is severely corroded.
  • the pixel structure in the above-mentioned display panel needs to be further optimized to solve the problem that water molecules in the flat layer slowly escape during the use of the display product and corrode the light-emitting function layer.
  • an embodiment of the present disclosure provides a display panel, including: a substrate, and a plurality of pixel units arranged on the substrate, the plurality of pixel units are arranged in an array, Each pixel unit includes a plurality of sub-pixels; the sub-pixels include sub-pixel drive circuits, a flat layer PLN, and an anode pattern 320 that are stacked in sequence; At the edge portion of the middle part, the surface of the flat layer PLN facing away from the substrate has a groove 310, and the orthographic projection of the groove 310 on the substrate surrounds the orthographic projection of the middle part on the substrate, At least part of the orthographic projection of the edge portion on the substrate is located inside the orthographic projection of the groove 310 on the substrate.
  • the display panel may include a plurality of pixel units distributed in an array, each pixel unit includes a plurality of sub-pixels, for example, each pixel unit includes a red sub-pixel R, a green sub-pixel G and One blue sub-pixel B; or each pixel unit includes one red sub-pixel R, two green sub-pixels G and one blue sub-pixel B.
  • Each sub-pixel includes a sub-pixel driving circuit, a flat layer PLN, and an anode pattern 320 that are sequentially stacked in a direction away from the substrate.
  • the sub-pixel driving circuit may be a 7T1C structure (that is, including: 7 thin film transistors and a storage capacitor), but it is not limited to this.
  • the sub-pixel driving circuit is coupled to the anode pattern 320 in the sub-pixel, and is used to provide driving signals for the anode pattern 320.
  • each sub-pixel further includes a light-emitting function layer EL located on the side of the anode pattern 320 away from the substrate, and a cathode layer.
  • the light-emitting function layer EL may specifically include: a hole injection layer, a hole transport layer , Organic light-emitting material layer, electron transport layer and electron injection layer.
  • the flat layer PLN is located between the sub-pixel driving circuit and the anode pattern 320, and its function is to flatten the level difference of the surface of the sub-pixel driving circuit away from the substrate, so that the anode pattern 320 formed thereon is more flat. , To avoid the color cast phenomenon of the display panel.
  • the surface of the flat layer PLN facing away from the substrate has a groove 310.
  • the specific structure of the groove 310 is various.
  • the groove 310 is formed on the substrate.
  • the orthographic projection is a closed structure, or the orthographic projection of the groove 310 on the substrate is a non-closed structure.
  • the depth of the trench 310 is less than the minimum thickness of the flat layer PLN; this arrangement allows the flat layer PLN to still be able to remove it at the trench 310
  • the structure below is completely covered, which can better prevent the structure on the upper surface of the flat layer PLN (such as the anode pattern 320) and the structure on the lower surface of the flat layer PLN (such as the source and drain metal layer) from short-circuiting at the trench 310 .
  • the trench 310 penetrates the planarization layer PLN; this arrangement allows the trench 310 to expose the structure (such as an insulating film layer) underneath it. When this arrangement is set, it is necessary to ensure At the trench 310, the structures located on the upper and lower sides of the flat layer PLN will not be short-circuited at the trench 310.
  • mark 40 in FIG. 14 represents the substrate and some film layers formed on the substrate.
  • the flat layer PLN can be made by using half-tone mask technology.
  • the flat layer PLN formed by the half-tone mask exposure process may include: a via hole penetrating the flat layer PLN, and the via hole is used for coupling
  • the anode pattern 320 and the sub-pixel driving circuit are respectively located on both sides of the flat layer PLN; it may also include the trench 310. Along the direction perpendicular to the substrate, the depth of the trench 310 is smaller than the minimum of the flat layer PLN. thickness.
  • the anode pattern 320 in at least part of the sub-pixels may specifically include a middle part and an edge part surrounding the middle part, and the middle part and the edge part are formed as an integral structure.
  • the orthographic projection of the groove 310 on the substrate surrounds the orthographic projection of the intermediate portion on the substrate, and at least part of the orthographic projection of the edge portion on the substrate is located in the groove 310 on the substrate. The interior of the orthographic projection on the base.
  • L3 represents the width of the anode pattern 320 into the bottom of the trench 310 along the Y direction
  • L4 represents the width of the film thickness transition zone of the flat layer PLN at the wall of the trench 310 along the Y direction
  • L5 represents the width along the Y direction.
  • the boundary of the pixel defining layer PDL at the pixel opening formed by it exceeds the width of the transition area.
  • the design values of L3 and L4 need to be greater than 2 ⁇ m.
  • the Z direction in FIG. 14 represents a direction perpendicular to the substrate.
  • the flat layer PLN is provided with grooves 310 on the surface facing away from the substrate, so that the flat layer PLN is formed to have a middle height and a peripheral surface.
  • the orthographic projection of the intermediate portion on the substrate is surrounded by the orthographic projection of the groove 310 on the substrate, and at least part of the orthographic projection of the edge portion on the substrate is located at the
  • the interior of the orthographic projection of the trench 310 on the substrate enables the anode pattern 320 to cover the portion of the planarization layer PLN surrounded by the trench 310, and at least a portion of the planarization layer PLN located inside the trench 310, such as As shown in FIG. 14, this arrangement not only compresses the diffusion channels of water molecules in the flat layer PLN (as shown in FIG. 14, the thickness of the flat layer PLN at the bottom of the trench 310 is reduced relative to the thickness of other parts of the flat layer PLN).
  • the display panel provided by the embodiment of the present disclosure, the water molecules are compressed from the flat layer PLN.
  • the diffusion channel and the extension of the path for water molecules to diffuse out of the flat layer PLN effectively slow down the release speed of water in the flat layer PLN, thereby slowing down the erosion of water molecules on the light-emitting function layer EL, and realizing the improvement of the display panel The beneficial effects of longevity.
  • the surface of the flat layer PLN facing away from the substrate is provided with a groove 310, so that at the groove 310, the flat layer PLN is perpendicular to the The thickness in the direction of the substrate is reduced, so that the volume of the flat layer PLN at the trench 310 is reduced, so that the total amount of residual moisture in the flat layer PLN is reduced, thereby effectively reducing the effect of water molecules on the light-emitting function.
  • the erosion of the layer EL achieves the beneficial effect of improving the life of the display panel.
  • the groove 310 includes a groove bottom and a groove wall, and the orthographic projection of the edge portion on the substrate overlaps the orthographic projection of the groove bottom of the groove 310 on the substrate.
  • the degree of overlap between the anode pattern 320 and the groove 310 can be set according to actual needs.
  • an orthographic projection of the edge portion of the anode pattern 320 on the substrate is set to be the same as that of the groove 310.
  • the orthographic projections of the groove walls of the groove 310 on the substrate overlap.
  • the orthographic projection of the edge portion of the anode pattern 320 on the substrate is set to overlap with the orthographic projection of the groove bottom of the groove 310 on the substrate.
  • the orthographic projection of the edge portion of the anode pattern 320 on the substrate is set to completely cover the orthographic projection of the groove bottom of the groove 310 on the substrate.
  • the release speed of water in the flat layer PLN is effectively slowed down, thereby slowing down the light-emitting function of the water molecules
  • the erosion of the layer EL achieves the beneficial effect of improving the life of the display panel.
  • the sub-pixel further includes a compensation pattern 906 located on the side of the flat layer PLN facing the substrate, and the compensation pattern 906
  • the orthographic projection on the substrate overlaps the orthographic projection of at least part of the trench 310 of the flat layer PLN on the substrate.
  • the orthographic projection of the compensation pattern 906 on the substrate overlaps the orthographic projection of at least part of the groove bottom of the groove 310 of the flat layer PLN on the substrate.
  • the compensation pattern 906 may be specifically located between the substrate and at least a part of the flat layer PLN, and the compensation pattern 906 is in contact with the surface of the flat layer PLN facing the substrate.
  • the compensation pattern 906 is made of the source and drain metal layers in the display panel, that is, the compensation pattern 906 is made of the same layer and the same material as the power signal line pattern 901 and the data line pattern 908 in the display panel.
  • the power signal line pattern 901 and the data line pattern 908 are formed in the same patterning process.
  • the thickness of the flat layer PLN is not uniform in the direction perpendicular to the substrate, and the flat layer PLN is used to cover the first
  • the thickness of a part of a structure is relatively thin
  • the thickness of a part of the flat layer PLN for covering the second structure is relatively thick.
  • the height of the surface of the first structure facing away from the substrate It is higher than the height of the surface of the second structure facing away from the substrate.
  • the above-mentioned arrangement of the orthographic projection of the compensation pattern 906 on the substrate overlaps the orthographic projection of at least part of the groove 310 of the flat layer PLN on the substrate, so that at the groove 310, the flat
  • the thickness of the layer PLN in the direction perpendicular to the substrate is further reduced, so that the diffusion channels of water molecules in the flat layer PLN are further compressed (as shown in FIG. 15 and FIG. 16 in the flat layer PLN at the bottom of the trench 310) The thickness is further reduced).
  • the release speed of the water in the flat layer PLN is more effectively slowed down, thereby being more effective
  • the erosion of the light-emitting function layer EL by water molecules is slowed down, and the beneficial effect of improving the life of the display panel is realized.
  • the above-mentioned arrangement of the orthographic projection of the compensation pattern 906 on the substrate overlaps the orthographic projection of at least part of the groove 310 of the flat layer PLN on the substrate, so that at the groove 310,
  • the thickness of the flat layer PLN in the direction perpendicular to the substrate is further reduced, so that the volume of the flat layer PLN at the trench 310 is further reduced, so that the total amount of residual moisture in the flat layer PLN is reduced Therefore, the erosion of the light-emitting function layer EL by water molecules is more effectively reduced, and the beneficial effect of improving the life of the display panel is realized.
  • the orthographic projection of the compensation pattern 906 on the substrate overlaps the orthographic projection of the middle portion of the anode pattern 320 on the substrate.
  • the orthographic projection of the compensation pattern 906 on the substrate and the orthographic projection of the middle part of the anode pattern 320 on the substrate overlap, so that in the area covered by the middle part, the flat layer
  • the thickness of the PLN in the direction perpendicular to the substrate is further reduced, so that the volume of the area covered by the flat layer PLN in the middle portion is further reduced, so that the total amount of residual moisture in the flat layer PLN is reduced Therefore, the erosion of the light-emitting function layer EL by water molecules is more effectively reduced, and the beneficial effect of improving the life of the display panel is realized.
  • the pixel unit includes a red sub-pixel R, a blue sub-pixel B, and a green sub-pixel G; and the red sub-pixel along the second direction
  • the pixel R and the green sub-pixel G are located in the same column, and the blue sub-pixel B is located in another column;
  • the green sub-pixel G includes:
  • a first power signal line pattern, at least a part of the first power signal line pattern extends along the second direction;
  • a first compensation pattern 9061 coupled to the first power signal line pattern, the first compensation pattern 9061 extending along a first direction, and the first direction intersects the second direction;
  • the first flat layer has a rectangular first groove 3101 formed on the first flat layer, and the first groove 3101 includes first portions disposed opposite to each other along the second direction. 3101a and the second part 3101b, as well as the third part 3101c and the fourth part 3101d disposed oppositely along the first direction, the orthographic projection of the first part 3101a on the substrate and the first compensation pattern 9061 on the substrate The orthographic projections overlap.
  • FIG. 13 shows the layout of the source and drain metal layers, the trench 310 of the flat layer PLN, and the anode pattern 320 in the three sub-pixels (RGB) included in one pixel unit.
  • the first power signal line pattern and the first compensation pattern 9061 are formed as an integral structure. This arrangement not only enables the first compensation pattern 9061 to have the same stable potential as the first power signal line pattern 901, but also enables the first compensation pattern 9061 to have the same stable potential as the first power signal line pattern. Formed in the patterning process.
  • a rectangular first trench 3101 is formed on the first flat layer, and the first trench 3101 includes a first portion 3101a and a second portion 3101b disposed oppositely along the second direction, and The third part 3101c and the fourth part 3101d are arranged oppositely in one direction, the first part 3101a and the second part 3101b both extend along the first direction, and the third part 3101c and the fourth part 3101d are both along the first direction. Extend in two directions.
  • the above-mentioned arrangement of the orthographic projection of the first part 3101a on the substrate overlaps the orthographic projection of the first compensation pattern 9061 on the substrate, so that at the position of the first part 3101a of the first groove 3101,
  • the thickness of the first flat layer in the direction perpendicular to the substrate is further reduced, so that the diffusion channels of water molecules in the first flat layer are further compressed (as shown in FIG. 15, the first flat layer is in the first flat layer).
  • the thickness of the bottom of the trench 3101 is further reduced). Therefore, in the display panel provided by the above embodiment, by further compressing the channel through which water molecules diffuse out of the first flat layer, the moisture in the first flat layer is more effectively slowed down.
  • the release speed of the light-emitting function layer is effectively slowed down by the water molecules to the luminescent function layer EL, and the beneficial effect of improving the life of the display panel is realized.
  • the above-mentioned arrangement of the orthographic projection of the first part 3101a on the substrate overlaps the orthographic projection of the first compensation pattern 9061 on the substrate, so that the first part 3101a of the first groove 3101 is located Position, the thickness of the first flat layer in the direction perpendicular to the substrate is further reduced, so that the volume of the first flat layer at the first trench 3101 is further reduced, so that the first flat layer
  • the residual total amount of moisture in the layer is reduced, thereby more effectively reducing the erosion of the light-emitting function layer EL by water molecules, and achieving the beneficial effect of improving the life of the display panel.
  • the pixel unit includes a red sub-pixel R, a blue sub-pixel B, and a green sub-pixel G;
  • the red sub-pixel R and the green sub-pixel G are located in the same column, and the blue sub-pixel B is located in another column;
  • the blue sub-pixel B includes:
  • a second power signal line pattern, at least part of the second power signal line pattern extends along the second direction;
  • the second flat layer has a rectangular second groove 3102 formed on the second flat layer, and the second groove 3102 includes a fifth part 3102a and a fifth part 3102a and The sixth part 3102b, and the seventh part 3102c and the eighth part 3102d disposed oppositely along the first direction, the orthographic projection of the seventh part 3102c on the substrate and the second compensation pattern 9062 on the substrate The orthographic projections overlap.
  • the second power signal line pattern and the second compensation pattern 9062 are formed as an integral structure. This arrangement not only enables the second compensation pattern 9062 to have the same stable potential as the second power signal line pattern, but also enables the second compensation pattern 9062 to be patterned with the second power signal line pattern at one time. Formed in the process.
  • a rectangular second groove 3102 is formed on the second flat layer, and the second groove 3102 includes a fifth portion 3102a and a sixth portion 3102b that are arranged opposite to each other along the second direction, and The seventh portion 3102c and the eighth portion 3102d are arranged opposite to each other in the first direction, the fifth portion 3102a and the sixth portion 3102b both extend in the first direction, and the seventh portion 3102c and the eighth portion 3102d are both Extend in the second direction.
  • the above arrangement of the orthographic projection of the seventh portion 3102c on the substrate overlaps the orthographic projection of the second compensation pattern 9062 on the substrate, so that the seventh portion 3102c of the second groove 3102 is located Position, the thickness of the second flat layer in the direction perpendicular to the substrate is further reduced, so that the diffusion channels of water molecules in the second flat layer are further compressed (as shown in FIG. The thickness of the bottom of the second groove 3102 is further reduced). Therefore, in the display panel provided by the above embodiment, by further compressing the channel through which water molecules diffuse out of the second flat layer, the second flat layer is more effectively slowed down. The release rate of the middle water, thereby more effectively slowing down the erosion of the light-emitting function layer EL by water molecules, and achieving the beneficial effect of increasing the life of the display panel.
  • the above-mentioned arrangement of the orthographic projection of the seventh part 3102c on the substrate overlaps the orthographic projection of the second compensation pattern 9062 on the substrate, so that the seventh part of the second groove 3102 At the position of 3102c, the thickness of the second flat layer in the direction perpendicular to the substrate is further reduced, so that the volume of the second flat layer at the second trench 3102 is further reduced, so that the first The total amount of residual moisture in the two flat layers is reduced, thereby more effectively reducing the erosion of the light-emitting function layer EL by water molecules, and achieving the beneficial effect of improving the life of the display panel.
  • the red sub-pixel R includes a third flat layer, a rectangular third trench 3103 is formed on the third flat layer, and the third trench 3103 includes The ninth part 3103a and the tenth part 3103b are arranged, and the eleventh part 3103c and the twelfth part 3103d are arranged oppositely along the first direction.
  • the flat layer PLN included in each sub-pixel is formed as an integral structure, and the flat layer PLN of the integral structure can effectively flatten the side of each sub-pixel driving circuit in the display panel facing away from the substrate. The difference.
  • the sub-pixel includes a power signal line pattern 901, at least part of the power signal line pattern 901 extends along the second direction, and the power signal line pattern 901 includes The first power supply portion 9012 and the second power supply portion 9011, in a direction perpendicular to the second direction, the width L2 of the first power supply portion 9012 is greater than the width L1 of the second power supply portion 9011;
  • the orthographic projection of the power supply portion 9012 on the substrate overlaps the orthographic projection of the middle portion of the anode pattern 320 on the substrate.
  • the power signal line pattern 901 may specifically include a first power source part 9012 and a second power source part 9011.
  • the first power source part 9012 and the second power source part 9011 are along the second direction. Alternately arranged, the adjacent first part and the second part are coupled together.
  • the first power source part 9012 and the second power source part 9011 are formed as an integral structure.
  • the minimum width of the first power supply part 9012 is greater than the maximum width of the second power supply part 9011.
  • the above-mentioned arrangement of the orthographic projection of the first power supply portion 9012 on the substrate overlaps the orthographic projection of the middle part of the anode pattern 320 on the substrate, so that the area covered by the middle part of the anode pattern 320 is overlapped
  • the thickness of the flat layer PLN in the direction perpendicular to the substrate is effectively reduced, so that the volume of the flat layer PLN is reduced, so that the total amount of residual moisture in the flat layer PLN is reduced, and furthermore
  • the erosion of the light-emitting function layer EL by water molecules is effectively reduced, and the beneficial effect of improving the life of the display panel is realized.
  • the sub-pixel further includes:
  • a power signal line pattern 901, at least part of the power signal line pattern 901 extends along the second direction;
  • a data line pattern 908 at least part of the data line pattern 908 extends along the second direction;
  • the sub-pixel driving circuit includes a driving transistor.
  • the orthographic projection of the power signal line pattern 901 on the substrate, the orthographic projection of the output electrode of the driving transistor on the substrate, and The data line pattern 908 is between the orthographic projections on the substrate;
  • the orthographic projection of the power signal line pattern 901 on the substrate overlaps the orthographic projection of the groove 310 of the flat layer PLN on the substrate; and/or, the power signal line pattern 901 is on the substrate
  • the orthographic projection on the substrate overlaps the orthographic projection of the middle part of the anode pattern 320 on the substrate;
  • the orthographic projection of the data line pattern 908 on the substrate overlaps the orthographic projection of the groove 310 of the flat layer PLN on the substrate; and/or, the data line pattern 908 is on the substrate
  • the orthographic projection of is overlapped with the orthographic projection of the middle part of the anode pattern 320 on the substrate.
  • the driving transistor includes a gate, a first electrode, and a second electrode.
  • the first electrode of the driving transistor can be used as the input electrode of the driving transistor, and the second electrode of the driving transistor can be used as the input electrode of the driving transistor.
  • the input electrode of the driving transistor can receive the power signal transmitted by the power signal line pattern 901.
  • the power signal line pattern 901, the data line pattern 908, and the specific layout of the driving transistor are various.
  • the power signal line pattern 901 is formed on the substrate.
  • Orthographic projection located between the orthographic projection of the output electrode of the driving transistor on the substrate and the orthographic projection of the data line pattern 908 on the substrate; or, in a sub-pixel, the data line
  • the orthographic projection of the pattern 908 on the substrate is located between the orthographic projection of the output electrode of the driving transistor on the substrate and the orthographic projection of the power signal line pattern 901 on the substrate.
  • the above-mentioned arrangement of the orthographic projection of the power signal line pattern 901 on the substrate overlaps the orthographic projection of the groove 310 of the flat layer PLN on the substrate; and/or, the power signal line pattern 901 is The orthographic projection on the substrate overlaps the orthographic projection of the middle portion of the anode pattern 320 on the substrate.
  • the orthographic projection of the data line pattern 908 on the substrate overlaps the orthographic projection of the groove 310 of the flat layer PLN on the substrate; and/or, the data line pattern 908 is on the substrate
  • the orthographic projection on the substrate overlaps the orthographic projection of the middle part of the anode pattern 320 on the substrate; both can make the flat layer PLN in the direction perpendicular to the substrate at the groove 310
  • the thickness is further reduced, so that the diffusion channels of water molecules in the flat layer PLN are further compressed, which more effectively slows down the release speed of water in the flat layer PLN, and slows down the erosion of water molecules on the light-emitting function layer EL.
  • the beneficial effect of improving the life of the display panel is realized.
  • the above arrangement method further reduces the volume of the flat layer PLN at the trench 310, so that the total amount of residual moisture in the flat layer PLN is reduced, thereby more effectively reducing the effect of water molecules on the light-emitting function layer EL. Corrosion, to achieve the beneficial effect of improving the life of the display panel.
  • the above arrangement also enables the thickness of the flat layer PLN in the direction perpendicular to the substrate to be effectively reduced in the area covered by the middle part of the anode pattern 320, so that the volume of the flat layer PLN is reduced.
  • the total amount of residual moisture in the flat layer PLN is reduced, thereby more effectively reducing the erosion of the light-emitting function layer EL by water molecules, and achieving the beneficial effect of improving the life of the display panel.
  • the sub-pixel further includes:
  • the sub-pixel driving circuit includes a driving transistor and a first transistor, a first electrode of the first transistor is coupled to a second electrode of the driving transistor, and the second electrode of the first transistor passes through the first conductive
  • the connecting portion 907 is coupled to the gate of the driving transistor
  • the orthographic projection of the first conductive connection portion 907 on the substrate overlaps the orthographic projection of the trench 310 of the flat layer PLN on the substrate; and/or, the first conductive connection portion 907 is The orthographic projection on the substrate overlaps the orthographic projection of the middle portion of the anode pattern 320 on the substrate.
  • the sub-pixel driving circuit includes a driving transistor and a first transistor, and the first transistor is connected between the second electrode of the driving transistor and the gate of the driving transistor, and is used for matching the driving transistor during the compensation period.
  • the driving transistor performs threshold voltage compensation.
  • the above-mentioned orthographic projection of the first conductive connection portion 907 on the substrate overlaps the orthographic projection of the trench 310 of the flat layer PLN on the substrate; and/or, the first conductive connection portion
  • the orthographic projection of 907 on the substrate overlaps the orthographic projection of the middle part of the anode pattern 320 on the substrate, so that at the groove 310, the flat layer PLN is perpendicular to the substrate.
  • the thickness in the direction is reduced, so that the diffusion channels of water molecules in the flat layer PLN are further compressed, which more effectively slows down the release speed of water in the flat layer PLN, and slows down the water molecules to the light-emitting function layer EL. Corrosion, to achieve the beneficial effect of improving the life of the display panel.
  • the above arrangement method further reduces the volume of the flat layer PLN at the trench 310, so that the total amount of residual moisture in the flat layer PLN is reduced, thereby more effectively reducing the effect of water molecules on the light-emitting function layer EL. Corrosion, to achieve the beneficial effect of improving the life of the display panel.
  • the above arrangement also enables the thickness of the flat layer PLN in the direction perpendicular to the substrate to be effectively reduced in the area covered by the middle part of the anode pattern 320, so that the volume of the flat layer PLN is reduced. By being reduced, the total amount of residual moisture in the flat layer PLN is reduced, thereby more effectively reducing the erosion of the light-emitting function layer EL by water molecules, and achieving the beneficial effect of improving the life of the display panel.
  • the sub-pixel further includes:
  • An initialization signal line pattern 904 at least part of the initialization signal line pattern 904 extends along a first direction, and the first direction intersects the second direction;
  • the sub-pixel driving circuit includes a seventh transistor, the gate of the seventh transistor is coupled to the corresponding reset signal line pattern 905, and the first electrode of the seventh transistor is connected to the corresponding reset signal line pattern 905 through the second conductive connection portion 909
  • the initialization signal line pattern 904 of is coupled, and the second electrode of the seventh transistor is coupled to the corresponding anode pattern 320;
  • the orthographic projection of the second conductive connection portion 909 on the substrate overlaps the orthographic projection of the trench 310 of the flat layer PLN on the substrate; and/or, the second conductive connection portion 909 is The orthographic projection on the substrate overlaps the orthographic projection of the middle portion of the anode pattern 320 on the substrate.
  • the seventh transistor is used to transmit the initialization signal line transmitted on the initialization signal line pattern 904 to the corresponding anode pattern 320 under the control of the reset signal transmitted on the reset signal line pattern 905 to achieve The potential on the anode pattern 320 is reset.
  • the above-mentioned orthographic projection of the second conductive connecting portion 909 on the substrate overlaps the orthographic projection of the trench 310 of the flat layer PLN on the substrate; and/or, the second conductive connecting portion
  • the orthographic projection of 909 on the substrate overlaps the orthographic projection of the middle part of the anode pattern 320 on the substrate, so that at the groove 310, the flat layer PLN is perpendicular to the substrate.
  • the thickness in the direction is thinned, so that the diffusion channels of water molecules in the flat layer PLN are further compressed, which more effectively slows down the release speed of water in the flat layer PLN, and slows down the water molecules to the light-emitting function layer EL. Corrosion, to achieve the beneficial effect of improving the life of the display panel.
  • the above arrangement also reduces the volume of the flat layer PLN at the trench 310, so that the total amount of residual moisture in the flat layer PLN is reduced, thereby more effectively reducing the effect of water molecules on the light-emitting function layer EL. Corrosion, to achieve the beneficial effect of improving the life of the display panel.
  • the above arrangement also enables the thickness of the flat layer PLN in the direction perpendicular to the substrate to be effectively reduced in the area covered by the middle part of the anode pattern 320, so that the volume of the flat layer PLN is reduced. By being reduced, the total amount of residual moisture in the flat layer PLN is reduced, thereby more effectively reducing the erosion of the light-emitting function layer EL by water molecules, and achieving the beneficial effect of improving the life of the display panel.
  • the sub-pixels further include: a pixel defining layer PDL on the side of the anode pattern 320 facing away from the substrate, and the pixel defining layer PDL has pixels The opening, the orthographic projection of the pixel opening on the substrate, is located inside the orthographic projection of the middle part of the anode pattern 320 on the substrate.
  • the sub-pixel further includes: a pixel defining layer PDL on the side of the anode pattern 320 facing away from the substrate, the pixel defining layer PDL has a pixel opening, and the pixel opening can expose the anode pattern At least part of the middle part of 320, the side of the pixel defining layer PDL facing away from the substrate is further formed with a light-emitting function layer EL, and the part of the light-emitting function layer EL located in the pixel opening can be in line with the middle part. At least part of the contact.
  • the above-mentioned arrangement of the orthographic projection of the pixel opening on the substrate is located inside the orthographic projection of the middle portion of the anode pattern 320 on the substrate, so that the light-emitting function layer EL is in contact with the anode pattern 320
  • the part has good flatness, so as to better ensure the production yield and luminous effect of the light-emitting function layer EL.
  • the sub-pixels are arranged in an array, and the sub-pixels further include:
  • the sub-pixel driving circuit includes: a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;
  • the gate of the driving transistor is coupled to the second electrode of the first transistor through the corresponding first conductive connection portion, and the first electrode of the driving transistor is coupled to the second electrode of the fifth transistor , The second electrode of the driving transistor is coupled to the first electrode of the first transistor;
  • the gate of the first transistor is coupled to the gate line pattern
  • the gate of the second transistor is coupled to the reset signal line pattern in the next sub-pixel adjacent in the second direction, and the first electrode of the second transistor is connected to the next adjacent sub-pixel in the second direction.
  • the initialization signal line pattern in the sub-pixel is coupled, and the second electrode of the second transistor is coupled to the gate of the driving transistor;
  • the gate of the fourth transistor is coupled to the gate line pattern, the first electrode of the fourth transistor is coupled to the data line pattern, and the second electrode of the fourth transistor is connected to the driving transistor.
  • the gate of the fifth transistor is coupled to the light emission control signal line pattern, and the first electrode of the fifth transistor is coupled to the power signal line pattern;
  • the gate of the sixth transistor is coupled to the light emission control signal line pattern, the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor is coupled to the The light-emitting element in the sub-pixel is coupled;
  • the gate of the seventh transistor is coupled to the corresponding reset signal line pattern, the first electrode of the seventh transistor is coupled to the corresponding initialization signal line pattern, and the second electrode of the seventh transistor is coupled to the corresponding anode Graphics coupling.
  • each transistor included in the sub-pixel driving circuit adopts a P-type transistor, and the first electrode of each transistor has a source electrode and the second electrode has a drain electrode.
  • the first transistor T1 has a double-gate structure, the gate 201g of the first transistor T1 is coupled to the gate line pattern 902, and the source S1 of the first transistor T1 is coupled to the drain D3 of the third transistor T3 (i.e., the driving transistor), The drain D1 of the first transistor T1 is coupled to the gate 203g of the third transistor T3.
  • the second transistor T2 has a double-gate structure.
  • the gate 202g of the second transistor T2 is coupled to the reset signal line pattern 905' in the next sub-pixel adjacent in the second direction.
  • the source of the second transistor T2 The pole S2 is coupled to the initialization signal line pattern 904' in the next sub-pixel, and the drain D2 of the second transistor T2 is coupled to the gate 203g of the third transistor T3.
  • the gate 204g of the fourth transistor T4 is coupled to the gate line pattern 902, the source S4 of the fourth transistor T4 is coupled to the data line pattern 908, and the drain D4 of the fourth transistor T4 is coupled to the source of the third transistor T3. S3 is coupled.
  • the gate 205g of the fifth transistor T5 is coupled to the light emission control signal line pattern 903, the source S5 of the fifth transistor T5 is coupled to the power signal line pattern 901, and the drain D5 of the fifth transistor T5 is coupled to the source of the third transistor T3 ⁇ S3 is coupled.
  • the gate 206g of the sixth transistor T6 is coupled to the light emission control signal line pattern 903, the source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is coupled to the anode pattern catch.
  • the gate 207g of the seventh transistor T7 is coupled to the reset signal line pattern 905, the drain D7 of the seventh transistor T7 is coupled to the anode pattern, and the source S7 of the seventh transistor T7 is coupled to the initialization signal line pattern 904 catch.
  • the first plate Cst1 of the storage capacitor Cst is multiplexed as the gate 203g of the third transistor T3, and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern 901.
  • the embodiments of the present disclosure also provide a display device, including the display panel provided in the above-mentioned embodiments.
  • the surface of the flat layer PLN facing away from the substrate is provided with grooves 310, so that the flat layer PLN is formed into a structure with a middle height and a low circumference; at the same time, the grooves 310 are arranged.
  • the orthographic projection of the groove 310 on the substrate surrounds the orthographic projection of the middle portion on the substrate, and the orthographic projection of the edge portion on the substrate is located on the orthographic projection of the groove 310 on the substrate
  • the anode pattern 320 can cover the part of the flat layer PLN surrounded by the trench 310, and at least part of the flat layer PLN located inside the trench 310. As shown in FIG.
  • this arrangement is not only suitable for water
  • the diffusion channels of the molecules in the flat layer PLN are compressed (as shown in Figure 14, the thickness of the flat layer PLN at the bottom of the trench 310 is reduced relative to the thickness of other parts of the flat layer PLN), and it also extends the water molecules reaching the light-emitting function layer ELEL. Diffusion path (the dotted arrow in FIG. 14 indicates the diffusion path of water molecules). Therefore, in the display panel provided by the above embodiment, the channel through which water molecules diffuse out of the flat layer PLN is compressed, and the water molecules from the flat layer PLN are extended.
  • the path that diffuses out of the flat layer effectively slows down the release speed of water in the flat layer PLN, thereby slowing down the erosion of the light-emitting function layer EL by water molecules, and achieving the beneficial effect of improving the life of the display panel.
  • the surface of the flat layer PLN facing away from the substrate has a groove 310, so that at the groove 310, the flat layer PLN is perpendicular to the substrate.
  • the thickness of the flat layer PLN at the groove 310 is reduced, so that the total amount of residual moisture in the flat layer PLN is reduced, thereby effectively reducing the effect of water molecules on the light-emitting function layer.
  • the erosion of EL achieves the beneficial effect of improving the life of the display panel.
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned display panel, it also has the above-mentioned beneficial effects, which will not be repeated here.
  • the display device may be any product or component with a display function, such as a TV, a monitor, a digital photo frame, a mobile phone, a tablet computer, and the like.
  • the embodiment of the present disclosure also provides a manufacturing method of the display panel, and the manufacturing method includes:
  • fabricating a plurality of pixel units on a substrate the plurality of pixel units are arranged in an array, and each pixel unit includes a plurality of sub-pixels;
  • the sub-pixel includes a sub-pixel driving circuit, a flat layer PLN, and an anode pattern 320 that are sequentially stacked in a direction away from the substrate; at least a part of the anode pattern 320 in the sub-pixel includes a middle part and a surrounding part.
  • the surface of the flat layer PLN facing away from the substrate has a groove 310, and the orthographic projection of the groove 310 on the substrate surrounds the orthographic projection of the intermediate portion on the substrate, at least partially The orthographic projection of the edge portion on the substrate is located inside the orthographic projection of the groove 310 on the substrate.
  • the step of fabricating the sub-pixels included in the pixel unit specifically includes: first forming a sub-pixel driving circuit on a substrate, and then fabricating a flat layer PLN on the side of the sub-pixel driving circuit facing away from the substrate, and forming a flat layer PLN on the side of the sub-pixel driving circuit facing away from the substrate.
  • a trench 310 is formed on the layer PLN, and then an anode pattern 320 is formed on the side of the flat layer PLN facing away from the substrate.
  • the surface of the flat layer PLN facing away from the substrate is provided with grooves 310, so that the flat layer PLN is formed into a structure with a middle height and a low circumference;
  • the orthographic projection of the intermediate portion on the substrate is surrounded by the orthographic projection of the groove 310 on the substrate, and at least part of the orthographic projection of the edge portion on the substrate is located in the groove 310
  • the anode pattern 320 can cover the portion of the flat layer PLN surrounded by the trench 310, and at least a portion of the flat layer PLN located inside the trench 310, as shown in FIG.
  • This arrangement not only compresses the diffusion channels of water molecules in the flat layer PLN (as shown in Figure 14, the thickness of the flat layer PLN at the bottom of the trench 310 is reduced relative to the thickness of other parts of the flat layer PLN), but also extends The diffusion path of water molecules reaching the light-emitting functional layer ELEL (the dotted arrow in FIG. 14 indicates the diffusion path of water molecules).
  • the water molecules are compressed from the flat layer PLN
  • the channel that diffuses out of the flat layer and the extension of the path for water molecules to diffuse out of the flat layer PLN effectively slow down the release of water in the flat layer PLN, thereby slowing down the erosion of water molecules on the light-emitting functional layer EL, and achieving improved display
  • the beneficial effect of the panel life
  • the surface of the flat layer PLN facing away from the substrate has a groove 310, so that at the groove 310, the flat layer PLN
  • the thickness in the direction perpendicular to the substrate is reduced, so that the volume of the flat layer PLN at the trench 310 is reduced, so that the total amount of residual moisture in the flat layer PLN is reduced, thereby effectively reducing
  • the erosion of the light-emitting function layer EL by water molecules achieves the beneficial effect of improving the life of the display panel.
  • the sub-pixel includes a power signal line pattern 901 and a compensation pattern 906, and the manufacturing method further includes:
  • the power signal line pattern 901 and the compensation pattern 906 are formed at the same time.
  • the compensation pattern 906 is located on the side of the flat layer PLN facing the substrate.
  • the compensation pattern 906 is on the positive side of the substrate.
  • the projection overlaps with the orthographic projection of at least a part of the groove 310 of the flat layer PLN on the substrate, and/or the orthographic projection of the compensation pattern 906 on the substrate and the middle part of the anode pattern 320 The orthographic projections on the substrate overlap.
  • the power signal line pattern 901 and the compensation pattern 906 may be formed as an integral structure, so that the compensation pattern 906 has the same stable potential as the power signal line pattern 901, and the compensation pattern 906 It can be formed with the power signal line pattern 901 in one patterning process.
  • the orthographic projection of the compensation pattern 906 on the substrate By setting the orthographic projection of the compensation pattern 906 on the substrate to overlap with the orthographic projection of at least part of the groove 310 of the flat layer PLN on the substrate, so that at the groove 310, the flat
  • the thickness of the layer PLN in the direction perpendicular to the substrate is further reduced, so that the diffusion channels of water molecules in the flat layer PLN are further compressed (as shown in FIG. 15 and FIG. 16 in the flat layer PLN at the bottom of the trench 310) The thickness is further reduced).
  • the release speed of the water in the flat layer PLN is more effectively slowed down, thereby being more effective
  • the erosion of the light-emitting function layer EL by water molecules is slowed down, and the beneficial effect of improving the life of the display panel is realized.
  • the orthographic projection of the compensation pattern 906 on the substrate is set to overlap with the orthographic projection of at least part of the groove 310 of the flat layer PLN on the substrate, so that at the groove 310.
  • the thickness of the flat layer PLN in the direction perpendicular to the substrate is further reduced, so that the volume of the flat layer PLN at the trench 310 is further reduced, so that the total amount of residual moisture in the flat layer PLN is reduced Therefore, the erosion of the light-emitting function layer EL by water molecules is more effectively reduced, and the beneficial effect of improving the life of the display panel is realized.
  • the orthographic projection of the compensation pattern 906 on the substrate and the orthographic projection of the middle part of the anode pattern 320 on the substrate are further reduced, so that the volume of the flat layer PLN in the area covered by the middle part is further reduced, so that the total amount of residual moisture in the flat layer PLN The amount is reduced, thereby more effectively reducing the erosion of the light-emitting function layer EL by water molecules, and achieving the beneficial effect of improving the life of the display panel.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本公开提供一种显示面板及其制作方法、显示装置。显示面板包括：基底，以及设置在基底上的多个像素单元，多个像素单元呈阵列分布，每个像素单元均包括多个子像素；子像素包括依次层叠设置的子像素驱动电路、平坦层和阳极图形；至少部分子像素中的阳极图形包括中间部分和包围中间部分的边缘部分，平坦层背向基底的表面具有沟槽，沟槽在基底上的正投影包围中间部分在基底上的正投影，至少部分边缘部分在基底上的正投影位于沟槽在基底上的正投影的内部。

Description

一种显示面板及其制作方法、显示装置
相关申请的交叉引用
本申请主张在2020年05月27日在中国提交的中国专利申请号No.202010461694.4的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及其制作方法、显示装置。
背景技术
有机发光二极管(英文：Organic Light-Emitting Diode；简称：OLED)显示产品中，阳极层背向显示面板的基底的一侧设置有发光功能层，阳极层面向所述基底的一侧设置有平坦层，平坦层的材质一般为聚酰亚胺类有机高分子，聚酰亚胺高分子材料一般由低聚物聚合形成，在发生聚合反应时的副产物为水，而且聚酰亚胺还具备一定的吸水性。
显示面板制备过程中，由于平坦层被结构致密的阳极层覆盖，常规加热的方法无法使平坦层中的水分子完全释放出来，导致显示产品使用过程中，平坦层中的水分子会逸出，侵蚀发光功能层，使显示产品寿命缩减。
发明内容
本公开的目的在于提供一种显示面板及其制作方法、显示装置。
为了实现上述目的，本公开提供如下技术方案：
本公开的第一方面提供一种显示面板，包括：基底，以及设置在所述基底上的多个像素单元，所述多个像素单元呈阵列分布，每个像素单元均包括多个子像素；
所述子像素包括沿远离所述基底的方向依次层叠设置的子像素驱动电路、平坦层和阳极图形；至少部分子像素中的所述阳极图形包括中间部分和包围所述中间部分的边缘部分，所述平坦层背向所述基底的表面具有沟槽， 所述沟槽在所述基底上的正投影包围所述中间部分在所述基底上的正投影，至少部分所述边缘部分在所述基底上的正投影位于所述沟槽在所述基底上的正投影的内部。
可选的，所述沟槽包括槽底和槽壁，所述边缘部分在所述基底上的正投影，与所述沟槽的槽底在所述基底上的正投影交叠。
可选的，所述子像素还包括位于所述平坦层朝向所述基底的一侧的补偿图形，所述补偿图形在所述基底上的正投影与至少部分所述平坦层的沟槽在所述基底上的正投影交叠。
可选的，所述补偿图形在所述基底上的正投影与所述阳极图形的中间部分在所述基底上的正投影交叠。
可选的，所述像素单元包括一个红色子像素、一个蓝色子像素和一个绿色子像素；沿第二方向所述红色子像素与所述绿色子像素位于同一列，所述蓝色子像素位于另一列；所述绿色子像素包括：
第一电源信号线图形，所述第一电源信号线图形的至少部分沿第二方向延伸；
与所述第一电源信号线图形耦接的第一补偿图形，所述第一补偿图形沿第一方向延伸，所述第一方向与所述第二方向相交；
第一平坦层，所述第一平坦层上形成有矩形的第一沟槽，所述第一沟槽包括沿所述第二方向相对设置的第一部分和第二部分，以及沿第一方向相对设置的第三部分和第四部分，所述第一部分在所述基底上的正投影与所述第一补偿图形在所述基底上的正投影交叠。
可选的，所述像素单元包括一个红色子像素、一个蓝色子像素和一个绿色子像素；沿第二方向所述红色子像素与所述绿色子像素位于同一列，所述蓝色子像素位于另一列；所述蓝色子像素包括：
第二电源信号线图形，所述第二电源信号线图形的至少部分沿第二方向延伸；
与所述第二电源信号线图形耦接的第二补偿图形，所述第二补偿图形沿第一方向突出于所述第二电源信号线图形，所述第二补偿图形沿所述第二方向延伸；
第二平坦层，所述第二平坦层上形成有矩形的第二沟槽，所述第二沟槽包括沿所述第二方向相对设置的第五部分和第六部分，以及沿第一方向相对设置的第七部分和第八部分，所述第七部分在所述基底上的正投影与所述第二补偿图形在所述基底上的正投影交叠。
可选的，所述子像素包括电源信号线图形，所述电源信号线图形的至少部分沿第二方向延伸，所述电源信号线图形包括第一电源部和第二电源部，沿垂直于所述第二方向的方向上，所述第一电源部的宽度大于所述第二电源部的宽度；
所述第一电源部在所述基底上的正投影与所述阳极图形的中间部分在所述基底上的正投影交叠。
可选的，所述子像素还包括：
电源信号线图形，所述电源信号线图形的至少部分沿第二方向延伸；
数据线图形，所述数据线图形的至少部分沿所述第二方向延伸；
所述子像素驱动电路包括驱动晶体管，在一个子像素中，所述电源信号线图形在所述基底上的正投影，位于所述驱动晶体管的输出电极在所述基底上的正投影，与所述数据线图形在所述基底上的正投影之间；
所述电源信号线图形在所述基底上的正投影与所述平坦层的沟槽在所述基底上的正投影交叠；和/或，所述电源信号线图形在所述基底上的正投影与所述阳极图形的中间部分在所述基底上的正投影交叠；
所述数据线图形在所述基底上的正投影与所述平坦层的沟槽在所述基底上的正投影交叠；和/或，所述数据线图形在所述基底上的正投影与所述阳极图形的中间部分在所述基底上的正投影交叠。
可选的，所述子像素还包括：
第一导电连接部，所述第一导电连接部的至少部分沿第二方向延伸；
所述子像素驱动电路包括驱动晶体管和第一晶体管，所述第一晶体管的第一极与所述驱动晶体管的第二极耦接，所述第一晶体管的第二极通过所述第一导电连接部与所述驱动晶体管的栅极耦接；
所述第一导电连接部在所述基底上的正投影与所述平坦层的沟槽在所述基底上的正投影交叠；和/或，所述第一导电连接部在所述基底上的正投影与 所述阳极图形的中间部分在所述基底上的正投影交叠。
可选的，所述子像素还包括：
第二导电连接部，所述第二导电连接部的至少部分沿第二方向延伸；
初始化信号线图形，所述初始化信号线图形的至少部分沿第一方向延伸，所述第一方向与所述第二方向相交；
复位信号线图形，所述复位信号线图形沿所述第一方向延伸；
所述子像素驱动电路包括第七晶体管，所述第七晶体管的栅极与对应的复位信号线图形耦接，所述第七晶体管的第一极通过所述第二导电连接部与对应的初始化信号线图形耦接，所述第七晶体管的第二极与对应的所述阳极图形耦接；
所述第二导电连接部在所述基底上的正投影与所述平坦层的沟槽在所述基底上的正投影交叠；和/或，所述第二导电连接部在所述基底上的正投影与所述阳极图形的中间部分在所述基底上的正投影交叠。
可选的，所述子像素还包括：
位于所述阳极图形背向所述基底的一侧的像素界定层，所述像素界定层具有像素开口，所述像素开口在所述基底上的正投影，位于所述阳极图形的中间部分在所述基底上的正投影的内部。
可选的，所述子像素呈阵列分布，所述子像素还包括：
电源信号线图形、数据线图形、初始化信号线图形、栅线图形、发光控制信号线图形、复位信号线图形、第一导电连接部和第二导电连接部；
所述子像素驱动电路包括：驱动晶体管、第一晶体管、第二晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管；
所述驱动晶体管的栅极通过对应的所述第一导电连接部与所述第一晶体管的第二极耦接，所述驱动晶体管的第一极与所述第五晶体管的第二极耦接，所述驱动晶体管的第二极与所述第一晶体管的第一极耦接；
所述第一晶体管的栅极与所述栅线图形耦接；
所述第二晶体管的栅极与沿第二方向相邻的下一个子像素中的所述复位信号线图形耦接，所述第二晶体管的第一极与沿第二方向相邻的下一个子像素中的所述初始化信号线图形耦接，所述第二晶体管的第二极与所述驱动晶 体管的栅极耦接；
所述第四晶体管的栅极与所述栅线图形耦接，所述第四晶体管的第一极与所述数据线图形耦接，所述第四晶体管的第二极与所述驱动晶体管的第一极耦接；
所述第五晶体管的栅极与所述发光控制信号线图形耦接，所述第五晶体管的第一极与所述电源信号线图形耦接；
所述第六晶体管的栅极与所述发光控制信号线图形耦接，所述第六晶体管的第一极与所述驱动晶体管的第二极耦接，所述第六晶体管的第二极与所述子像素中的发光元件耦接；
所述第七晶体管的栅极与对应的复位信号线图形耦接，所述第七晶体管的第一极与对应的初始化信号线图形耦接，所述第七晶体管的第二极与对应的阳极图形耦接。
基于上述显示面板的技术方案，本公开的第二方面提供一种显示装置，包括上述显示面板。
基于上述显示面板的技术方案，本公开的第三方面提供一种显示面板的制作方法，所述制作方法包括：
在基底上制作多个像素单元，所述多个像素单元呈阵列分布，每个像素单元均包括多个子像素；
所述子像素包括沿远离所述基底的方向依次层叠设置的子像素驱动电路、平坦层和阳极图形；至少部分子像素中的所述阳极图形包括中间部分和包围所述中间部分的边缘部分，所述平坦层背向所述基底的表面具有沟槽，所述沟槽在所述基底上的正投影包围所述中间部分在所述基底上的正投影，至少部分所述边缘部分在所述基底上的正投影位于所述沟槽在所述基底上的正投影的内部。
可选的，所述子像素包括电源信号线图形和补偿图形，所述制作方法还包括：
通过一次构图工艺，同时形成所述电源信号线图形与补偿图形，所述补偿图形位于所述平坦层朝向所述基底的表面，所述补偿图形在所述基底上的正投影与至少部分所述平坦层的沟槽在所述基底上的正投影交叠，和/或，所 述补偿图形在所述基底上的正投影与所述阳极图形的中间部分在所述基底上的正投影交叠。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的子像素驱动电路的电路图；
图2为本公开实施例提供的子像素驱动电路的时序图；
图3为本公开实施例提供的三个子像素驱动电路的布局示意图；
图4为图3中有源层的布局示意图；
图5为图3中第一栅金属层的布局示意图；
图6为图3中第二栅金属层的布局示意图；
图7为图3中源漏金属层的布局示意图；
图8为阳极图形与图3中源漏金属层布局示意图；
图9为图8中沿A1A2方向的截面示意图；
图10为本公开实施例提供的源漏金属层和平坦层沟槽的布局示意图；
图11为图10中的源漏金属层的单层布局示意图；
图12为图10中的平坦层沟槽的布局示意图；
图13为本公开实施例提供的平坦层沟槽和阳极图形的布局示意图；
图14为图13中沿B1B2方向的截面示意图；
图15为图13中沿C1C2方向的截面示意图；
图16为图13中沿D1D2方向的截面示意图。
具体实施方式
为了进一步说明本公开实施例提供的显示面板及其制作方法、显示装置，下面结合说明书附图进行详细描述。
如图3和图8所示，本公开提供一种显示面板，该显示面板包括呈阵列 分布的多个像素单元，每个像素单元均包括多个子像素。每个子像素均包括子像素驱动电路、电源信号线图形901、数据线图形908、栅线图形902、发光控制信号线图形903、复位信号线图形905、初始化信号线图形904和阳极图形320；所述电源信号线图形901的至少部分和所述数据线图形908沿第二方向延伸；所述栅线图形902、所述发光控制信号线图形903、所述复位信号线图形905、所述初始化信号线图形904均沿第一方向延伸，所述第一方向与所述第二方向相交。示例性的，所述第一方向包括X方向，所述第二方向包括Y方向。
如图3所示，所述显示面板中包括的多个子像素驱动电路能够划分为沿所述第二方向依次排列的多行子像素驱动电路，以及沿所述第一方向依次排列的多列子像素驱动电路，位于同一行的子像素驱动电路对应的所述初始化信号线图形904依次电连接，形成为一体结构；位于同一行的子像素驱动电路对应的所述栅线图形902依次电连接，形成为一体结构；位于同一行的子像素驱动电路对应的所述发光控制信号线图形903依次电连接，形成为一体结构；位于同一行的子像素驱动电路对应的所述复位信号线图形905依次电连接，形成为一体结构；位于同一列的子像素驱动电路对应的所述数据线图形908依次电连接，形成为一体结构；位于同一列的子像素驱动电路对应的所述电源信号线图形901依次电连接，形成为一体结构。
示例性的，每行子像素驱动电路均包括沿X方向依次排列的多个子像素驱动电路，所述初始化信号线图形904、栅线图形902、发光控制信号线图形903和复位信号线图形905均沿所述X方向延伸，每行子像素驱动电路中包括的多个子像素驱动电路均能够分别与对应的初始化信号线图形904，栅线图形902，发光控制信号线图形903和复位信号线图形905耦接；每列子像素驱动电路均包括沿Y方向依次排列的多个子像素驱动电路，数据线图形908和电源信号线图形901均沿所述Y方向延伸，每列子像素驱动电路中包括的多个子像素驱动电路均能够分别与对应的数据线图形908和电源信号线图形901耦接。
如图1和图3所示，以一个子像素驱动电路为例，该子像素驱动电路包括7个薄膜晶体管和1个电容。该子像素驱动电路包括的各晶体管均采用P 型晶体管，其中，第一晶体管T1为双栅结构，第一晶体管T1的栅极201g与栅线图形902耦接，第一晶体管T1的源极S1与第三晶体管T3(即驱动晶体管)的漏极D3耦接，第一晶体管T1的漏极D1与第三晶体管T3的栅极203g耦接。
第二晶体管T2为双栅结构，第二晶体管T2的栅极202g与沿所述第二方向相邻的下一个子像素中的所述复位信号线图形905'耦接，第二晶体管T2的源极S2与所述下一个子像素中的初始化信号线图形904'耦接，第二晶体管T2的漏极D2与第三晶体管T3的栅极203g耦接。
第四晶体管T4的栅极204g与所述栅线图形902耦接，第四晶体管T4的源极S4与数据线图形908耦接，第四晶体管T4的漏极D4与第三晶体管T3的源极S3耦接。
第五晶体管T5的栅极205g与发光控制信号线图形903耦接，第五晶体管T5的源极S5与电源信号线图形901耦接，第五晶体管T5的漏极D5与第三晶体管T3的源极S3耦接。
第六晶体管T6的栅极206g与发光控制信号线图形903耦接，第六晶体管T6的源极S6与第三晶体管T3的漏极D3耦接，第六晶体管T6的漏极D6与阳极图形耦接。
第七晶体管T7的栅极207g与所述复位信号线图形905耦接，第七晶体管T7的漏极D7与阳极图形耦接，第七晶体管T7的源极S7与所述初始化信号线图形904耦接。
存储电容Cst的第一极板Cst1复用为第三晶体管T3的栅极203g，存储电容Cst的第二极板Cst2与所述电源信号线图形901耦接。
如图1和图2所示，上述结构的显示子像素驱动电路在工作时，每个工作周期均包括复位时段P1、写入补偿时段P2和发光时段P3。图2中，E1代表当前子像素中的发光控制信号线图形903上传输的发光控制信号，R1代表当前子像素中的复位信号线图形905上传输的复位信号，D1代表当前子像素中的数据线图形908上传输的数据信号，G1代表当前子像素中的栅线图形902上传输的栅极扫描信号，R1'代表当前子像素沿所述第二方向相邻的下一个子像素中的复位信号线图形905'上传输的复位信号。显示面板功能工作时， 按照自下向上的方向逐行扫描。
在所述第一复位时段P1，所述复位信号线图形905’输入的复位信号处于有效电平，第二晶体管T2导通，将由所述初始化信号线图形904’传输的初始化信号输入至第三晶体管T3的栅极203g，使得前一帧保持在第三晶体管T3上的栅源电压Vgs被清零，实现对第三晶体管T3的栅极203g复位。
在写入补偿时段P2，所述复位信号线图形905’输入的复位信号处于非有效电平，第二晶体管T2截止，栅线图形902输入的栅极扫描信号处于有效电平，控制第一晶体管T1和第四晶体管T4导通，数据线图形908写入数据信号，并经所述第四晶体管T4传输至第三晶体管T3的源极S3，同时，第一晶体管T1和第四晶体管T4导通，使得第三晶体管T3形成为二极管结构，因此通过第一晶体管T1、第三晶体管T3和第四晶体管T4配合工作，实现对第三晶体管T3的阈值电压补偿，当补偿的时间足够长时，可控制第三晶体管T3的栅极203g电位最终达到Vdata+Vth，其中，Vdata代表数据信号电压值，Vth代表第三晶体管T3的阈值电压。
在写入补偿时段P2，所述复位信号线图形905输入的复位信号处于有效电平，控制第七晶体管T7导通，由所述初始化信号线图形904传输的初始化信号输入至发光元件EL的阳极，控制发光元件EL不发光。
在发光时段P3，发光控制信号线图形903写入的发光控制信号处于有效电平，控制第五晶体管T5和第六晶体管T6导通，使得由电源信号线图形901传输的电源信号输入至第三晶体管T3的源极S3，同时由于第三晶体管T3的栅极203g保持在Vdata+Vth，使得第三晶体管T3导通，第三晶体管T3对应的栅源电压为Vdata+Vth-VDD，其中VDD为电源信号对应的电压值，基于该栅源电压产生的漏电流流向对应的发光元件EL的阳极，驱动对应的发光元件EL发光。
如图4～7所示，在制作上述显示子像素驱动电路时，显示子像素驱动电路对应的各膜层的布局如下：
沿远离基底的方向上依次层叠设置的有源膜层、栅极绝缘层、第一栅金属层、第一层间绝缘层、第二栅金属层、第二层间绝缘层、第一源漏金属层和第三层间绝缘层。
如图4所示，有源膜层用于形成显示子像素驱动电路中各晶体管的沟道区(如：101pg～107pg)，源极形成区和漏极形成区，源极形成区和漏极形成区对应的有源膜层由于掺杂作用，导电性能会优于沟道区对应的有源膜层；有源膜层可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
另外，值得注意，所述源极形成区和漏极形成区对应的有源膜层可直接作为对应的源极(如：S1～S7)和漏极(如：D1～D7)，或者，也可以采用金属材料制作与所述源极形成区接触的源极，采用金属材料制作与所述漏极形成区接触的漏极。
如图5所示，第一栅金属层用于形成子像素驱动电路中各晶体管的栅极(如：201g～207g)，以及显示面板包括的栅线图形902、发光控制信号线图形903、复位信号线图形905等结构，每个子像素驱动电路中的第三晶体管T3的栅极203g均复用为该子像素驱动电路中的第二存储电容Cst的第一极板Cst1。
如图6所示，第二栅金属层用于形成第二存储电容Cst的第二极板Cst2，具有屏蔽作用的遮挡图形801，以及显示基板包括的初始化信号线图形904。
如图7所示，第一源漏金属层用于形成显示面板包括的数据线图形908、电源信号线图形901和一些导电连接部。
更详细地说，请继续参阅图3～5，第一晶体管T1的栅极201g覆盖第一沟道区101pg，第二晶体管T2的栅极202g覆盖第二沟道区102pg，第三晶体管T3的栅极203g覆盖第三沟道区103pg，第四晶体管T4的栅极204g覆盖第四沟道区104pg，第五晶体管T5的栅极205g覆盖第五沟道区105pg，第六晶体管T6的栅极206g覆盖第六沟道区106pg，第七晶体管T7的栅极207g覆盖第七沟道区107pg。第三晶体管T3的栅极203g复用为存储电容Cst的第一极板Cst1，存储电容Cst的第二极板Cst2与电源信号线图形901耦接。
另外，如图3所示，本公开提供的显示面板中，在第二方向(如Y方向)上，第四晶体管T4的栅极204g、第一晶体管T1的栅极201g和第二晶体管T2的栅极202g均位于驱动晶体管的栅极(即第三晶体管T3的栅极203g)的第一侧，第七晶体管T7的栅极、第六晶体管T6的栅极206g、第五晶体管 T5的栅极均位于驱动晶体管的栅极的第二侧。示例性的，所述驱动晶体管的栅极的第一侧和第二侧为沿第二方向相对的两侧，进一步地，驱动晶体管的栅极的第一侧可以为驱动晶体管的栅极的下侧，驱动晶体管的栅极的第二侧可以为驱动晶体管的栅极的上侧。所述下侧，例如显示面板的用于绑定IC的一侧为显示面板的下侧，驱动晶体管的栅极的下侧，为驱动晶体管的栅极的更靠近IC的一侧。所述上侧为下侧的相对侧，例如为驱动晶体管的栅极的更远离IC的一侧。
在第一方向(如X方向)上，第四晶体管T4的栅极204g和第五晶体管T5的栅极205g均位于驱动晶体管的栅极的第三侧，第一晶体管T1的栅极201g和第六晶体管T6的栅极206g均位于驱动晶体管的栅极的第四侧。示例性的，驱动晶体管的栅极的第三侧和第四侧为沿第一方向相对的两侧；进一步地，驱动晶体管的栅极的第三侧可以为驱动晶体管的栅极的右侧，驱动晶体管的栅极的第四侧可以为驱动晶体管的栅极的左侧。所述左侧和右侧，例如在同一子像素中，数据线图形908位于电源信号线图形901右侧，电源信号线图形901位于数据线图形908左侧。
上述显示面板虽然能够改善显示产品使用过程中，平坦层中的水分子缓慢逸出，侵蚀发光功能层的问题，但改善效果有限。具体参见图8和图9，图9为图8中沿A1A2方向的截面示意图，图9中的黑色原点代表水分子，图9中带有箭头的虚线代表水分子扩散路径。可见，水分子向右侧扩散的通道虽然在垂直于显示面板的基底的方向上缩窄，但其向左侧仍然存在较大的扩散通道，使得水分子仍然能够沿着左侧通道对发光功能层EL产生严重的侵蚀。
因此，上述显示面板中的像素结构还需要进一步优化，以解决显示产品使用过程中，平坦层中的水分子缓慢逸出，侵蚀发光功能层的问题。
如图10、图13和图14所示，本公开实施例提供了一种显示面板，包括：基底，以及设置在所述基底上的多个像素单元，所述多个像素单元呈阵列分布，每个像素单元均包括多个子像素；所述子像素包括依次层叠设置的子像素驱动电路、平坦层PLN和阳极图形320；至少部分子像素中的所述阳极图形320包括中间部分和包围所述中间部分的边缘部分，所述平坦层PLN背向 所述基底的表面具有沟槽310，所述沟槽310在所述基底上的正投影包围所述中间部分在所述基底上的正投影，至少部分所述边缘部分在所述基底上的正投影位于所述沟槽310在所述基底上的正投影的内部。
具体地，所述显示面板可包括呈阵列分布的多个像素单元，每个像素单元均包括多个子像素，示例性的，每个像素单元均包括一个红色子像素R，一个绿色子像素G和一个蓝色子像素B；或者每个像素单元均包括一个红色子像素R，两个绿色子像素G和一个蓝色子像素B。
每个子像素均包括沿远离所述基底的方向依次层叠设置的子像素驱动电路、平坦层PLN和阳极图形320。所述子像素驱动电路可选为7T1C结构(即包括：7个薄膜晶体管和一个存储电容)，但不仅限于此。所述子像素驱动电路与其所在子像素中的阳极图形320耦接，用于为该阳极图形320提供驱动信号。
示例性的，每个子像素还包括位于阳极图形320背向所述基底的一侧的发光功能层EL，和阴极层，所述发光功能层EL可具体包括：空穴注入层、空穴传输层、有机发光材料层、电子传输层和电子注入层。显示面板工作时，阴极层上施加有负电源信号，子像素驱动电路为对应耦接的阳极图形320提供驱动信号，从而控制所述发光材料层发光，实现显示面板的显示功能。
所述平坦层PLN位于所述子像素驱动电路与所述阳极图形320之间，其作用是平坦子像素驱动电路背向所述基底的表面的段差，使得形成为其上的阳极图形320更加平坦，以避免所述显示面板出现色偏现象。
如图14所示，所述平坦层PLN背向所述基底的表面具有沟槽310，所述沟槽310的具体结构多种多样，示例性的，所述沟槽310在所述基底上的正投影为闭合结构，或者，所述沟槽310在所述基底上的正投影为非闭合结构。示例性的，沿垂直于所述基底的方向上，所述沟槽310的深度小于所述平坦层PLN的最小厚度；这种设置方式使得所述平坦层PLN在沟槽310处仍然能够将其下方的结构完全覆盖，能够更好的避免位于平坦层PLN上表面的结构(如：阳极图形320)与位于平坦层PLN下表面的结构(如：源漏金属层)在沟槽310处发生短路。示例性的，所述沟槽310贯穿所述平坦层PLN；这种设置方式使得沟槽310能够将位于其下方的结构(如：绝缘膜层)暴露出 来，当设置这种方式时，需要保证在沟槽310处，位于平坦层PLN上、下两侧的结构不会在沟槽310处发生短路。
需要说明图14中的标记40代表基底，以及形成在基底上的一些膜层。
所述平坦层PLN可具体采用半色调掩膜技术制作，利用半色调掩膜板曝光工艺形成的平坦层PLN中，可以包括：贯穿所述平坦层PLN的过孔，该过孔用于耦接分别位于平坦层PLN两侧的阳极图形320和子像素驱动电路；还可以包括所述沟槽310，沿垂直于所述基底的方向上，所述沟槽310的深度小于所述平坦层PLN的最小厚度。
至少部分子像素中的所述阳极图形320可具体包括中间部分和包围所述中间部分的边缘部分，所述中间部分和所述边缘部分形成为一体结构。所述沟槽310在所述基底上的正投影包围所述中间部分在所述基底上的正投影，至少部分所述边缘部分在所述基底上的正投影位于所述沟槽310在所述基底上的正投影的内部。
图14中，L3代表沿Y方向阳极图形320进入沟槽310槽底的宽度，L4代表平坦层PLN在沟槽310槽壁处的膜层厚度过渡区沿Y方向的宽度，L5代表沿Y方向像素界定层PDL在其形成的像素开口处的边界超出过渡区的宽度，为避免结构设计受不同膜层制作时的设备对位偏差影响，L3和L4的设计值需大于2μm。需要说明，图14中的Z方向代表垂直于基底的方向。
根据上述显示面板的具体结构可知，本公开实施例提供的显示面板中，通过设置所述平坦层PLN背向所述基底的表面具有沟槽310，使得所述平坦层PLN形成为中间高，四周低的结构；同时通过设置所述沟槽310在所述基底上的正投影包围所述中间部分在所述基底上的正投影，至少部分所述边缘部分在所述基底上的正投影位于所述沟槽310在所述基底上的正投影的内部，使得阳极图形320能够覆盖所述平坦层PLN中被沟槽310包围的部分，以及平坦层PLN中位于沟槽310内部的至少部分，如图14所示，这种设置方式不仅对水分子在平坦层PLN内的扩散通道实现了压缩(如图14中平坦层PLN在沟槽310底部的厚度相对于平坦层PLN其它部分的厚度减小)，还延长水分子到达发光功能层EL的扩散路径(图14中的虚线箭头指示水分子的扩散路径)，因此，本公开实施例提供的显示面板中，通过压缩水分子从平 坦层PLN中扩散出来的通道，以及延长水分子从平坦层PLN中扩散出来的路径，有效减慢了平坦层PLN中水分的释放速度，从而减慢了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
另外，本公开实施例提供的显示面板中，通过设置所述平坦层PLN背向所述基底的表面具有沟槽310，使得在所述沟槽310处，所述平坦层PLN在垂直于所述基底的方向上的厚度被减薄，从而使得所述平坦层PLN在沟槽310处的体积缩小，使得所述平坦层PLN内水分的残余总量减少，进而有效的减少了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
在一些实施例中，所述沟槽310包括槽底和槽壁，所述边缘部分在所述基底上的正投影，与所述沟槽310的槽底在所述基底上的正投影交叠。
具体地，所述阳极图形320与所述沟槽310的交叠程度可根据实际需要设置，示例性的，设置所述阳极图形320的边缘部分在所述基底上的正投影，与所述沟槽310的槽壁在所述基底上的正投影交叠。
示例性的，设置所述阳极图形320的边缘部分在所述基底上的正投影，与所述沟槽310的槽底在所述基底上的正投影交叠。
示例性的，设置所述阳极图形320的边缘部分在所述基底上的正投影，完全覆盖所述沟槽310的槽底在所述基底上的正投影。
上述设置所述边缘部分在所述基底上的正投影，与所述沟槽310的槽底在所述基底上的正投影交叠，使得所述阳极图形320能够覆盖所述平坦层PLN中位于沟槽310槽底的至少部分，如图14所示，这种设置方式不仅对水分子在平坦层PLN内的扩散通道实现了压缩(如图14中平坦层PLN在沟槽310底部的厚度相对于平坦层PLN其它部分的厚度减小)，还延长水分子到达发光功能层ELEL的扩散路径(图14中的虚线箭头指示水分子的扩散路径)，因此，上述实施例提供的显示面板中，通过压缩水分子从平坦层PLN中扩散出来的通道，以及延长水分子从平坦层PLN中扩散出来的路径，有效减慢了平坦层PLN中水分的释放速度，从而减慢了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
如图11、图13、图15和图16所示，在一些实施例中，所述子像素还包 括位于所述平坦层PLN朝向所述基底的一侧的补偿图形906，所述补偿图形906在所述基底上的正投影与至少部分所述平坦层PLN的沟槽310在所述基底上的正投影交叠。
示例性的，所述补偿图形906在所述基底上的正投影与至少部分所述平坦层PLN的沟槽310的槽底在所述基底上的正投影交叠。
示例性的，所述补偿图形906可具体位于所述基底与至少部分所述平坦层PLN之间，且所述补偿图形906与所述平坦层PLN朝向所述基底的表面接触。
示例性的，所述补偿图形906采用所述显示面板中的源漏金属层制作，即与所述显示面板中的电源信号线图形901和数据线图形908同层同材料设置，能够与所述电源信号线图形901和所述数据线图形908在同一次构图工艺中形成。
由于所述平坦层PLN用于平坦其所覆盖的结构的段差，因此，在垂直于所述基底的方向上，所述平坦层PLN的厚度不均一，且所述平坦层PLN中用于覆盖第一结构的部分厚度较薄，所述平坦层PLN中用于覆盖第二结构的部分厚度较厚，在垂直于所述基底的方向上，所述第一结构背向所述基底的表面的高度高于所述第二结构背向所述基底的表面的高度。
上述设置所述补偿图形906在所述基底上的正投影与至少部分所述平坦层PLN的沟槽310在所述基底上的正投影交叠，使得在所述沟槽310处，所述平坦层PLN在垂直于所述基底的方向上的厚度被进一步减薄，从而使得水分子在平坦层PLN内的扩散通道被进一步压缩(如图15和图16中平坦层PLN在沟槽310底部的厚度进一步减小)，因此，上述实施例提供的显示面板中，通过进一步压缩水分子从平坦层PLN中扩散出来的通道，更有效的减慢了平坦层PLN中水分的释放速度，从而更有效减慢了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
另外，上述设置所述补偿图形906在所述基底上的正投影与至少部分所述平坦层PLN的沟槽310在所述基底上的正投影交叠，使得在所述沟槽310处，所述平坦层PLN在垂直于所述基底的方向上的厚度被进一步减薄，从而使得所述平坦层PLN在沟槽310处的体积进一步缩小，使得所述平坦层PLN 内水分的残余总量减少，进而更有效的减少了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
如图15所示，在一些实施例中，所述补偿图形906在所述基底上的正投影与所述阳极图形320的中间部分在所述基底上的正投影交叠。
上述通过设置所述补偿图形906在所述基底上的正投影与所述阳极图形320的中间部分在所述基底上的正投影交叠，使得在所述中间部分覆盖的区域，所述平坦层PLN在垂直于所述基底的方向上的厚度被进一步减薄，从而使得所述平坦层PLN在所述中间部分覆盖的区域的体积进一步缩小，使得所述平坦层PLN内水分的残余总量减少，进而更有效的减少了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
如图12、图13和图15所示，在一些实施例中，所述像素单元包括一个红色子像素R、一个蓝色子像素B和一个绿色子像素G；沿第二方向所述红色子像素R与所述绿色子像素G位于同一列，所述蓝色子像素B位于另一列；所述绿色子像素G包括：
第一电源信号线图形，所述第一电源信号线图形的至少部分沿第二方向延伸；
与所述第一电源信号线图形耦接的第一补偿图形9061，所述第一补偿图形9061沿第一方向延伸，所述第一方向与所述第二方向相交；
如图10～图12所示，第一平坦层，所述第一平坦层上形成有矩形的第一沟槽3101，所述第一沟槽3101包括沿所述第二方向相对设置的第一部分3101a和第二部分3101b，以及沿第一方向相对设置的第三部分3101c和第四部分3101d，所述第一部分3101a在所述基底上的正投影与所述第一补偿图形9061在所述基底上的正投影交叠。
具体地，如图13所示，图13中示出了一个像素单元包括的三个子像素(RGB)中源漏金属层、平坦层PLN的沟槽310和阳极图形320的布局。
示例性的，如图11所示，所述第一电源信号线图形与所述第一补偿图形9061形成为一体结构。这种设置方式不仅使得所述第一补偿图形9061具有与所述第一电源信号线图形901相同的稳定电位，还使得所述第一补偿图形9061能够与所述第一电源信号线图形在一次构图工艺中形成。
示例性的，所述第一平坦层上形成有矩形的第一沟槽3101，所述第一沟槽3101包括沿所述第二方向相对设置的第一部分3101a和第二部分3101b，以及沿第一方向相对设置的第三部分3101c和第四部分3101d，所述第一部分3101a和所述第二部分3101b均沿第一方向延伸，所述第三部分3101c和所述第四部分3101d均沿第二方向延伸。
上述设置所述第一部分3101a在所述基底上的正投影与所述第一补偿图形9061在所述基底上的正投影交叠，使得在所述第一沟槽3101的第一部分3101a所在位置，所述第一平坦层在垂直于所述基底的方向上的厚度被进一步减薄，从而使得水分子在第一平坦层内的扩散通道被进一步压缩(如图15中第一平坦层在第一沟槽3101底部的厚度进一步减小)，因此，上述实施例提供的显示面板中，通过进一步压缩水分子从第一平坦层中扩散出来的通道，更有效的减慢了第一平坦层中水分的释放速度，从而更有效减慢了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
另外，上述设置所述第一部分3101a在所述基底上的正投影与所述第一补偿图形9061在所述基底上的正投影交叠，使得在所述第一沟槽3101的第一部分3101a所在位置，所述第一平坦层在垂直于所述基底的方向上的厚度被进一步减薄，从而使得所述第一平坦层在第一沟槽3101处的体积进一步缩小，使得所述第一平坦层内水分的残余总量减少，进而更有效的减少了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
如图11、图12、图13和图16所示，在一些实施例中，所述像素单元包括一个红色子像素R、一个蓝色子像素B和一个绿色子像素G；沿第二方向所述红色子像素R与所述绿色子像素G位于同一列，所述蓝色子像素B位于另一列；所述蓝色子像素B包括：
第二电源信号线图形，所述第二电源信号线图形的至少部分沿第二方向延伸；
如图11所示，与所述第二电源信号线图形耦接的第二补偿图形9062，所述第二补偿图形9062沿第一方向突出于所述第二电源信号线图形，所述第二补偿图形9062沿所述第二方向延伸；
如图12所示，第二平坦层，所述第二平坦层上形成有矩形的第二沟槽 3102，所述第二沟槽3102包括沿所述第二方向相对设置的第五部分3102a和第六部分3102b，以及沿第一方向相对设置的第七部分3102c和第八部分3102d，所述第七部分3102c在所述基底上的正投影与所述第二补偿图形9062在所述基底上的正投影交叠。
示例性的，所述第二电源信号线图形与所述第二补偿图形9062形成为一体结构。这种设置方式不仅使得所述第二补偿图形9062具有与所述第二电源信号线图形相同的稳定电位，还使得所述第二补偿图形9062能够与所述第二电源信号线图形在一次构图工艺中形成。
示例性的，所述第二平坦层上形成有矩形的第二沟槽3102，所述第二沟槽3102包括沿所述第二方向相对设置的第五部分3102a和第六部分3102b，以及沿第一方向相对设置的第七部分3102c和第八部分3102d，所述第五部分3102a和所述第六部分3102b均沿第一方向延伸，所述第七部分3102c和所述第八部分3102d均沿第二方向延伸。
上述设置所述第七部分3102c在所述基底上的正投影与所述第二补偿图形9062在所述基底上的正投影交叠，使得在所述第二沟槽3102的第七部分3102c所在位置，所述第二平坦层在垂直于所述基底的方向上的厚度被进一步减薄，从而使得水分子在第二平坦层内的扩散通道被进一步压缩(如图16中第二平坦层在第二沟槽3102底部的厚度进一步减小)，因此，上述实施例提供的显示面板中，通过进一步压缩水分子从第二平坦层中扩散出来的通道，更有效的减慢了第二平坦层中水分的释放速度，从而更有效减慢了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
另外，上述设置所述第七部分3102c在所述基底上的正投影与所述第二补偿图形9062在所述基底上的正投影交叠，使得在所述第二沟槽3102的第七部分3102c所在位置，所述第二平坦层在垂直于所述基底的方向上的厚度被进一步减薄，从而使得所述第二平坦层在第二沟槽3102处的体积进一步缩小，使得所述第二平坦层内水分的残余总量减少，进而更有效的减少了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
如图12所示，所述红色子像素R包括第三平坦层，所述第三平坦层上形成有矩形的第三沟槽3103，所述第三沟槽3103包括沿所述第二方向相对设 置的第九部分3103a和第十部分3103b，以及沿第一方向相对设置的第十一部分3103c和第十二部分3103d。
需要说明，上述实施例提供的显示面板中，各子像素中包括的平坦层PLN形成为一体结构，该一体结构的平坦层PLN能够有效平坦显示面板中各子像素驱动电路背向基底的一侧的段差。
如图11和图13所示，在一些实施例中，所述子像素包括电源信号线图形901，所述电源信号线图形901的至少部分沿第二方向延伸，所述电源信号线图形901包括第一电源部9012和第二电源部9011，沿垂直于所述第二方向的方向上，所述第一电源部9012的宽度L2大于所述第二电源部9011的宽度L1；所述第一电源部9012在所述基底上的正投影与所述阳极图形320的中间部分在所述基底上的正投影交叠。
具体地，所述电源信号线图形901可具体包括第一电源部9012和第二电源部9011，示例性的，所述第一电源部9012与所述第二电源部9011沿所述第二方向交替排列，相邻的所述第一部分与所述第二部分耦接在一起。示例性的，所述第一电源部9012和第二电源部9011形成为一体结构。
示例性的，可设置沿垂直于所述第二方向的方向上，所述第一电源部9012的最小宽度大于所述第二电源部9011的最大宽度。
上述设置所述第一电源部9012在所述基底上的正投影与所述阳极图形320的中间部分在所述基底上的正投影交叠，使得在所述阳极图形320的中间部分覆盖的区域，所述平坦层PLN在垂直于所述基底的方向上的厚度被有效减薄，从而使得所述平坦层PLN的体积被缩小，使得所述平坦层PLN内水分的残余总量减少，进而更有效的减少了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
如图13所示，在一些实施例中，所述子像素还包括：
电源信号线图形901，所述电源信号线图形901的至少部分沿第二方向延伸；
数据线图形908，所述数据线图形908的至少部分沿所述第二方向延伸；
所述子像素驱动电路包括驱动晶体管，在一个子像素中，所述电源信号线图形901在所述基底上的正投影，位于所述驱动晶体管的输出电极在所述 基底上的正投影，与所述数据线图形908在所述基底上的正投影之间；
所述电源信号线图形901在所述基底上的正投影与所述平坦层PLN的沟槽310在所述基底上的正投影交叠；和/或，所述电源信号线图形901在所述基底上的正投影与所述阳极图形320的中间部分在所述基底上的正投影交叠；
所述数据线图形908在所述基底上的正投影与所述平坦层PLN的沟槽310在所述基底上的正投影交叠；和/或，所述数据线图形908在所述基底上的正投影与所述阳极图形320的中间部分在所述基底上的正投影交叠。
具体地，所述驱动晶体管包括栅极、第一极和第二极，所述驱动晶体管的第一极可作为驱动晶体管的输入电极，所述驱动晶体管的第二极可作为所述驱动晶体管的输出电极。所述驱动晶体管的输入电极能够接收所述电源信号线图形901传输的电源信号。
所述电源信号线图形901、所述数据线图形908和所述驱动晶体管的具体布局方式多种多样，示例性的，在一个子像素中，所述电源信号线图形901在所述基底上的正投影，位于所述驱动晶体管的输出电极在所述基底上的正投影，与所述数据线图形908在所述基底上的正投影之间；或者，在一个子像素中，所述数据线图形908在所述基底上的正投影，位于所述驱动晶体管的输出电极在所述基底上的正投影，与所述电源信号线图形901在所述基底上的正投影之间。
上述设置所述电源信号线图形901在所述基底上的正投影与所述平坦层PLN的沟槽310在所述基底上的正投影交叠；和/或，所述电源信号线图形901在所述基底上的正投影与所述阳极图形320的中间部分在所述基底上的正投影交叠。以及所述数据线图形908在所述基底上的正投影与所述平坦层PLN的沟槽310在所述基底上的正投影交叠；和/或，所述数据线图形908在所述基底上的正投影与所述阳极图形320的中间部分在所述基底上的正投影交叠；均能够使得在所述沟槽310处，所述平坦层PLN在垂直于所述基底的方向上的厚度被进一步减薄，从而使得水分子在平坦层PLN内的扩散通道被进一步压缩，更有效的减慢了平坦层PLN中水分的释放速度，减慢了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
另外，上述设置方式还使得所述平坦层PLN在沟槽310处的体积进一步缩小，使得所述平坦层PLN内水分的残余总量减少，进而更有效的减少了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
此外，上述设置方式还使得在所述阳极图形320的中间部分覆盖的区域，所述平坦层PLN在垂直于所述基底的方向上的厚度被有效减薄，从而使得所述平坦层PLN的体积被缩小，使得所述平坦层PLN内水分的残余总量减少，进而更有效的减少了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
如图13所示，在一些实施例中，所述子像素还包括：
第一导电连接部907，所述第一导电连接部907的至少部分沿第二方向延伸；
所述子像素驱动电路包括驱动晶体管和第一晶体管，所述第一晶体管的第一极与所述驱动晶体管的第二极耦接，所述第一晶体管的第二极通过所述第一导电连接部907与所述驱动晶体管的栅极耦接；
所述第一导电连接部907在所述基底上的正投影与所述平坦层PLN的沟槽310在所述基底上的正投影交叠；和/或，所述第一导电连接部907在所述基底上的正投影与所述阳极图形320的中间部分在所述基底上的正投影交叠。
具体地，所述子像素驱动电路包括驱动晶体管和第一晶体管，所述第一晶体管接在所述驱动晶体管的第二极与所述驱动晶体管的栅极之间，用于在补偿时段对所述驱动晶体管进行阈值电压补偿。
上述设置所述第一导电连接部907在所述基底上的正投影与所述平坦层PLN的沟槽310在所述基底上的正投影交叠；和/或，所述第一导电连接部907在所述基底上的正投影与所述阳极图形320的中间部分在所述基底上的正投影交叠，使得在所述沟槽310处，所述平坦层PLN在垂直于所述基底的方向上的厚度被减薄，从而使得水分子在平坦层PLN内的扩散通道被进一步压缩，更有效的减慢了平坦层PLN中水分的释放速度，减慢了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
另外，上述设置方式还使得所述平坦层PLN在沟槽310处的体积进一步 缩小，使得所述平坦层PLN内水分的残余总量减少，进而更有效的减少了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。此外，上述设置方式还使得在所述阳极图形320的中间部分覆盖的区域，所述平坦层PLN在垂直于所述基底的方向上的厚度被有效减薄，从而使得所述平坦层PLN的体积被缩小，使得所述平坦层PLN内水分的残余总量减少，进而更有效的减少了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
如图13所示，在一些实施例中，所述子像素还包括：
第二导电连接部909，所述第二导电连接部909的至少部分沿第二方向延伸；
初始化信号线图形904，所述初始化信号线图形904的至少部分沿第一方向延伸，所述第一方向与所述第二方向相交；
复位信号线图形905，所述复位信号线图形905沿所述第一方向延伸；
所述子像素驱动电路包括第七晶体管，所述第七晶体管的栅极与对应的复位信号线图形905耦接，所述第七晶体管的第一极通过所述第二导电连接部909与对应的初始化信号线图形904耦接，所述第七晶体管的第二极与对应的所述阳极图形320耦接；
所述第二导电连接部909在所述基底上的正投影与所述平坦层PLN的沟槽310在所述基底上的正投影交叠；和/或，所述第二导电连接部909在所述基底上的正投影与所述阳极图形320的中间部分在所述基底上的正投影交叠。
具体地，所述第七晶体管用于在所述复位信号线图形905上传输的复位信号的控制下，将所述初始化信号线图形904上传输的初始化信号线传输至对应的阳极图形320，实现对所述阳极图形320上的电位进行复位。
上述设置所述第二导电连接部909在所述基底上的正投影与所述平坦层PLN的沟槽310在所述基底上的正投影交叠；和/或，所述第二导电连接部909在所述基底上的正投影与所述阳极图形320的中间部分在所述基底上的正投影交叠，使得在所述沟槽310处，所述平坦层PLN在垂直于所述基底的方向上的厚度被减薄，从而使得水分子在平坦层PLN内的扩散通道被进一步压缩， 更有效的减慢了平坦层PLN中水分的释放速度，减慢了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
另外，上述设置方式还使得所述平坦层PLN在沟槽310处的体积被缩小，使得所述平坦层PLN内水分的残余总量减少，进而更有效的减少了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。此外，上述设置方式还使得在所述阳极图形320的中间部分覆盖的区域，所述平坦层PLN在垂直于所述基底的方向上的厚度被有效减薄，从而使得所述平坦层PLN的体积被缩小，使得所述平坦层PLN内水分的残余总量减少，进而更有效的减少了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
如图14～图16所示，在一些实施例中，所述子像素还包括：位于所述阳极图形320背向所述基底的一侧的像素界定层PDL，所述像素界定层PDL具有像素开口，所述像素开口在所述基底上的正投影，位于所述阳极图形320的中间部分在所述基底上的正投影的内部。
具体地，所述子像素还包括：位于所述阳极图形320背向所述基底的一侧的像素界定层PDL，所述像素界定层PDL具有像素开口，所述像素开口能够暴露所述阳极图形320的中间部分中的至少部分，所述像素界定层PDL背向基底的一侧还形成有发光功能层EL，所述发光功能层EL位于所述像素开口中的部分能够与所述中间部分中的至少部分接触。
上述设置所述像素开口在所述基底上的正投影，位于所述阳极图形320的中间部分在所述基底上的正投影的内部，使得所述发光功能层EL与所述阳极图形320接触的部分具有良好的平坦性，从而更好的保证了所述发光功能层EL的制作良率和发光效果。
在一些实施例中，所述子像素呈阵列分布，所述子像素还包括：
电源信号线图形901、数据线图形908、初始化信号线图形904、栅线图形902、发光控制信号线图形903、复位信号线图形905；
所述子像素驱动电路包括：驱动晶体管、第一晶体管、第二晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管；
所述驱动晶体管的栅极通过对应的所述第一导电连接部与所述第一晶体管的第二极耦接，所述驱动晶体管的第一极与所述第五晶体管的第二极耦接， 所述驱动晶体管的第二极与所述第一晶体管的第一极耦接；
所述第一晶体管的栅极与所述栅线图形耦接；
所述第二晶体管的栅极与沿第二方向相邻的下一个子像素中的所述复位信号线图形耦接，所述第二晶体管的第一极与沿第二方向相邻的下一个子像素中的所述初始化信号线图形耦接，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接；
所述第四晶体管的栅极与所述栅线图形耦接，所述第四晶体管的第一极与所述数据线图形耦接，所述第四晶体管的第二极与所述驱动晶体管的第一极耦接；
所述第五晶体管的栅极与所述发光控制信号线图形耦接，所述第五晶体管的第一极与所述电源信号线图形耦接；
所述第六晶体管的栅极与所述发光控制信号线图形耦接，所述第六晶体管的第一极与所述驱动晶体管的第二极耦接，所述第六晶体管的第二极与所述子像素中的发光元件耦接；
所述第七晶体管的栅极与对应的复位信号线图形耦接，所述第七晶体管的第一极与对应的初始化信号线图形耦接，所述第七晶体管的第二极与对应的阳极图形耦接。
具体地，如图1和图3所示，所述子像素驱动电路包括的各晶体管均采用P型晶体管，各晶体管的第一极为源极，第二极为漏极。
第一晶体管T1为双栅结构，第一晶体管T1的栅极201g与栅线图形902耦接，第一晶体管T1的源极S1与第三晶体管T3(即驱动晶体管)的漏极D3耦接，第一晶体管T1的漏极D1与第三晶体管T3的栅极203g耦接。
第二晶体管T2为双栅结构，第二晶体管T2的栅极202g与沿所述第二方向相邻的下一个子像素中的所述复位信号线图形905'耦接，第二晶体管T2的源极S2与所述下一个子像素中的初始化信号线图形904'耦接，第二晶体管T2的漏极D2与第三晶体管T3的栅极203g耦接。
第四晶体管T4的栅极204g与所述栅线图形902耦接，第四晶体管T4的源极S4与数据线图形908耦接，第四晶体管T4的漏极D4与第三晶体管T3的源极S3耦接。
第五晶体管T5的栅极205g与发光控制信号线图形903耦接，第五晶体管T5的源极S5与电源信号线图形901耦接，第五晶体管T5的漏极D5与第三晶体管T3的源极S3耦接。
第六晶体管T6的栅极206g与发光控制信号线图形903耦接，第六晶体管T6的源极S6与第三晶体管T3的漏极D3耦接，第六晶体管T6的漏极D6与阳极图形耦接。
第七晶体管T7的栅极207g与所述复位信号线图形905耦接，第七晶体管T7的漏极D7与阳极图形耦接，第七晶体管T7的源极S7与所述初始化信号线图形904耦接。
存储电容Cst的第一极板Cst1复用为第三晶体管T3的栅极203g，存储电容Cst的第二极板Cst2与所述电源信号线图形901耦接。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示面板。
上述实施例提供的显示面板中，通过设置所述平坦层PLN背向所述基底的表面具有沟槽310，使得所述平坦层PLN形成为中间高，四周低的结构；同时通过设置所述沟槽310在所述基底上的正投影包围所述中间部分在所述基底上的正投影，所述边缘部分在所述基底上的正投影位于所述沟槽310在所述基底上的正投影的内部，使得阳极图形320能够覆盖所述平坦层PLN中被沟槽310包围的部分，以及平坦层PLN中位于沟槽310内部的至少部分，如图14所示，这种设置方式不仅对水分子在平坦层PLN内的扩散通道实现了压缩(如图14中平坦层PLN在沟槽310底部的厚度相对于平坦层PLN其它部分的厚度减小)，还延长水分子到达发光功能层ELEL的扩散路径(图14中的虚线箭头指示水分子的扩散路径)，因此，上述实施例提供的显示面板中，通过压缩水分子从平坦层PLN中扩散出来的通道，以及延长水分子从平坦层PLN中扩散出来的路径，有效减慢了平坦层PLN中水分的释放速度，从而减慢了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。另外，上述实施例提供的显示面板中，通过设置所述平坦层PLN背向所述基底的表面具有沟槽310，使得在所述沟槽310处，所述平坦层PLN在垂直于所述基底的方向上的厚度被减薄，从而使得所述平坦层PLN在沟槽310处的体积缩小，使得所述平坦层PLN内水分的残余总量减少，进而有效的减少了 水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
因此，本公开实施例提供的显示装置在包括上述显示面板时，同样具有上述有益效果，此处不再赘述。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
本公开实施例还提供了显示面板的制作方法，所述制作方法包括：
在基底上制作多个像素单元，所述多个像素单元呈阵列分布，每个像素单元均包括多个子像素；
所述子像素包括沿远离所述基底的方向依次层叠设置的子像素驱动电路、平坦层PLN和阳极图形320；至少部分子像素中的所述阳极图形320包括中间部分和包围所述中间部分的边缘部分，所述平坦层PLN背向所述基底的表面具有沟槽310，所述沟槽310在所述基底上的正投影包围所述中间部分在所述基底上的正投影，至少部分所述边缘部分在所述基底上的正投影位于所述沟槽310在所述基底上的正投影的内部。
具体地，制作所述像素单元中包括的子像素的步骤具体包括：先在基底上形成子像素驱动电路，然后在子像素驱动电路背向基底的一侧制作平坦层PLN，并在所述平坦层PLN上形成沟槽310，然后在所述平坦层PLN背向所述基底的一侧制作阳极图形320。
采用本公开实施例提供的制作方法制作的显示面板中，通过设置所述平坦层PLN背向所述基底的表面具有沟槽310，使得所述平坦层PLN形成为中间高，四周低的结构；同时通过设置所述沟槽310在所述基底上的正投影包围所述中间部分在所述基底上的正投影，至少部分所述边缘部分在所述基底上的正投影位于所述沟槽310在所述基底上的正投影的内部，使得阳极图形320能够覆盖所述平坦层PLN中被沟槽310包围的部分，以及平坦层PLN中位于沟槽310内部的至少部分，如图14所示，这种设置方式不仅对水分子在平坦层PLN内的扩散通道实现了压缩(如图14中平坦层PLN在沟槽310底部的厚度相对于平坦层PLN其它部分的厚度减小)，还延长水分子到达发光功能层ELEL的扩散路径(图14中的虚线箭头指示水分子的扩散路径)，因此，采用本公开实施例提供的制作方法制作的显示面板中，通过压缩水分子 从平坦层PLN中扩散出来的通道，以及延长水分子从平坦层PLN中扩散出来的路径，有效减慢了平坦层PLN中水分的释放速度，从而减慢了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
另外，采用本公开实施例提供的制作方法制作的显示面板中，通过设置所述平坦层PLN背向所述基底的表面具有沟槽310，使得在所述沟槽310处，所述平坦层PLN在垂直于所述基底的方向上的厚度被减薄，从而使得所述平坦层PLN在沟槽310处的体积缩小，使得所述平坦层PLN内水分的残余总量减少，进而有效的减少了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
在一些实施例中，所述子像素包括电源信号线图形901和补偿图形906，所述制作方法还包括：
通过一次构图工艺，同时形成所述电源信号线图形901与补偿图形906，所述补偿图形906位于所述平坦层PLN朝向所述基底的一侧，所述补偿图形906在所述基底上的正投影与至少部分所述平坦层PLN的沟槽310在所述基底上的正投影交叠，和/或，所述补偿图形906在所述基底上的正投影与所述阳极图形320的中间部分在所述基底上的正投影交叠。
具体地，所述电源信号线图形901与所述补偿图形906可形成为一体结构，从而使得所述补偿图形906具有与所述电源信号线图形901相同的稳定电位，还使得所述补偿图形906能够与所述电源信号线图形901在一次构图工艺中形成。
通过设置所述补偿图形906在所述基底上的正投影与至少部分所述平坦层PLN的沟槽310在所述基底上的正投影交叠，使得在所述沟槽310处，所述平坦层PLN在垂直于所述基底的方向上的厚度被进一步减薄，从而使得水分子在平坦层PLN内的扩散通道被进一步压缩(如图15和图16中平坦层PLN在沟槽310底部的厚度进一步减小)，因此，上述实施例提供的显示面板中，通过进一步压缩水分子从平坦层PLN中扩散出来的通道，更有效的减慢了平坦层PLN中水分的释放速度，从而更有效减慢了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
另外，通过设置所述补偿图形906在所述基底上的正投影与至少部分所 述平坦层PLN的沟槽310在所述基底上的正投影交叠，使得在所述沟槽310处，所述平坦层PLN在垂直于所述基底的方向上的厚度被进一步减薄，从而使得所述平坦层PLN在沟槽310处的体积进一步缩小，使得所述平坦层PLN内水分的残余总量减少，进而更有效的减少了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
此外，上述通过设置所述补偿图形906在所述基底上的正投影与所述阳极图形320的中间部分在所述基底上的正投影交叠，使得在所述中间部分覆盖的区域，所述平坦层PLN在垂直于所述基底的方向上的厚度被进一步减薄，从而使得所述平坦层PLN在所述中间部分覆盖的区域的体积进一步缩小，使得所述平坦层PLN内水分的残余总量减少，进而更有效的减少了水分子对发光功能层EL的侵蚀，实现提升显示面板寿命的有益效果。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种显示面板，包括：基底，以及设置在所述基底上的多个像素单元，所述多个像素单元呈阵列分布，每个像素单元均包括多个子像素；
    所述子像素包括依次层叠设置的子像素驱动电路、平坦层和阳极图形；至少部分子像素中的所述阳极图形包括中间部分和包围所述中间部分的边缘部分，所述平坦层背向所述基底的表面具有沟槽，所述沟槽在所述基底上的正投影包围所述中间部分在所述基底上的正投影，至少部分所述边缘部分在所述基底上的正投影位于所述沟槽在所述基底上的正投影的内部。
  2. 根据权利要求1所述的显示面板，其中，所述沟槽包括槽底和槽壁，所述边缘部分在所述基底上的正投影，与所述沟槽的槽底在所述基底上的正投影交叠。
  3. 根据权利要求1所述的显示面板，其中，所述子像素还包括位于所述平坦层朝向所述基底的一侧的补偿图形，所述补偿图形在所述基底上的正投影与至少部分所述平坦层的沟槽在所述基底上的正投影交叠。
  4. 根据权利要求3所述的显示面板，其中，所述补偿图形在所述基底上的正投影与所述阳极图形的中间部分在所述基底上的正投影交叠。
  5. 根据权利要求4所述的显示面板，其中，所述像素单元包括一个红色子像素、一个蓝色子像素和一个绿色子像素；沿第二方向所述红色子像素与所述绿色子像素位于同一列，所述蓝色子像素位于另一列；所述绿色子像素包括：
    第一电源信号线图形，所述第一电源信号线图形的至少部分沿第二方向延伸；
    与所述第一电源信号线图形耦接的第一补偿图形，所述第一补偿图形沿第一方向延伸，所述第一方向与所述第二方向相交；
    第一平坦层，所述第一平坦层上形成有矩形的第一沟槽，所述第一沟槽包括沿所述第二方向相对设置的第一部分和第二部分，以及沿第一方向相对设置的第三部分和第四部分，所述第一部分在所述基底上的正投影与所述第一补偿图形在所述基底上的正投影交叠。
  6. 根据权利要求4所述的显示面板，其中，所述像素单元包括一个红色子像素、一个蓝色子像素和一个绿色子像素；沿第二方向所述红色子像素与所述绿色子像素位于同一列，所述蓝色子像素位于另一列；所述蓝色子像素包括：
    第二电源信号线图形，所述第二电源信号线图形的至少部分沿第二方向延伸；
    与所述第二电源信号线图形耦接的第二补偿图形，所述第二补偿图形沿第一方向突出于所述第二电源信号线图形，所述第二补偿图形沿所述第二方向延伸；
    第二平坦层，所述第二平坦层上形成有矩形的第二沟槽，所述第二沟槽包括沿所述第二方向相对设置的第五部分和第六部分，以及沿第一方向相对设置的第七部分和第八部分，所述第七部分在所述基底上的正投影与所述第二补偿图形在所述基底上的正投影交叠。
  7. 根据权利要求1所述的显示面板，其中，所述子像素包括电源信号线图形，所述电源信号线图形的至少部分沿第二方向延伸，所述电源信号线图形包括第一电源部和第二电源部，沿垂直于所述第二方向的方向上，所述第一电源部的宽度大于所述第二电源部的宽度；
    所述第一电源部在所述基底上的正投影与所述阳极图形的中间部分在所述基底上的正投影交叠。
  8. 根据权利要求1所述的显示面板，其中，所述子像素还包括：
    电源信号线图形，所述电源信号线图形的至少部分沿第二方向延伸；
    数据线图形，所述数据线图形的至少部分沿所述第二方向延伸；
    所述子像素驱动电路包括驱动晶体管，在一个子像素中，所述电源信号线图形在所述基底上的正投影，位于所述驱动晶体管的输出电极在所述基底上的正投影，与所述数据线图形在所述基底上的正投影之间；
    所述电源信号线图形在所述基底上的正投影与所述平坦层的沟槽在所述基底上的正投影交叠；和/或，所述电源信号线图形在所述基底上的正投影与所述阳极图形的中间部分在所述基底上的正投影交叠；
    所述数据线图形在所述基底上的正投影与所述平坦层的沟槽在所述基底 上的正投影交叠；和/或，所述数据线图形在所述基底上的正投影与所述阳极图形的中间部分在所述基底上的正投影交叠。
  9. 根据权利要求1所述的显示面板，其中，所述子像素还包括：
    第一导电连接部，所述第一导电连接部的至少部分沿第二方向延伸；
    所述子像素驱动电路包括驱动晶体管和第一晶体管，所述第一晶体管的第一极与所述驱动晶体管的第二极耦接，所述第一晶体管的第二极通过所述第一导电连接部与所述驱动晶体管的栅极耦接；
    所述第一导电连接部在所述基底上的正投影与所述平坦层的沟槽在所述基底上的正投影交叠；和/或，所述第一导电连接部在所述基底上的正投影与所述阳极图形的中间部分在所述基底上的正投影交叠。
  10. 根据权利要求1所述的显示面板，其中，所述子像素还包括：
    第二导电连接部，所述第二导电连接部的至少部分沿第二方向延伸；
    初始化信号线图形，所述初始化信号线图形的至少部分沿第一方向延伸，所述第一方向与所述第二方向相交；
    复位信号线图形，所述复位信号线图形沿所述第一方向延伸；
    所述子像素驱动电路包括第七晶体管，所述第七晶体管的栅极与对应的复位信号线图形耦接，所述第七晶体管的第一极通过所述第二导电连接部与对应的初始化信号线图形耦接，所述第七晶体管的第二极与对应的所述阳极图形耦接；
    所述第二导电连接部在所述基底上的正投影与所述平坦层的沟槽在所述基底上的正投影交叠；和/或，所述第二导电连接部在所述基底上的正投影与所述阳极图形的中间部分在所述基底上的正投影交叠。
  11. 根据权利要求1所述的显示面板，其中，所述子像素还包括：
    位于所述阳极图形背向所述基底的一侧的像素界定层，所述像素界定层具有像素开口，所述像素开口在所述基底上的正投影，位于所述阳极图形的中间部分在所述基底上的正投影的内部。
  12. 根据权利要求1所述的显示面板，其中，所述子像素呈阵列分布，所述子像素还包括：
    电源信号线图形、数据线图形、初始化信号线图形、栅线图形、发光控 制信号线图形、复位信号线图形；
    所述子像素驱动电路包括：驱动晶体管、第一晶体管、第二晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管；
    所述驱动晶体管的栅极通过对应的第一导电连接部与所述第一晶体管的第二极耦接，所述驱动晶体管的第一极与所述第五晶体管的第二极耦接，所述驱动晶体管的第二极与所述第一晶体管的第一极耦接；
    所述第一晶体管的栅极与所述栅线图形耦接；
    所述第二晶体管的栅极与沿第二方向相邻的下一个子像素中的所述复位信号线图形耦接，所述第二晶体管的第一极与沿第二方向相邻的下一个子像素中的所述初始化信号线图形耦接，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接；
    所述第四晶体管的栅极与所述栅线图形耦接，所述第四晶体管的第一极与所述数据线图形耦接，所述第四晶体管的第二极与所述驱动晶体管的第一极耦接；
    所述第五晶体管的栅极与所述发光控制信号线图形耦接，所述第五晶体管的第一极与所述电源信号线图形耦接；
    所述第六晶体管的栅极与所述发光控制信号线图形耦接，所述第六晶体管的第一极与所述驱动晶体管的第二极耦接，所述第六晶体管的第二极与所述子像素中的发光元件耦接；
    所述第七晶体管的栅极与对应的复位信号线图形耦接，所述第七晶体管的第一极与对应的初始化信号线图形耦接，所述第七晶体管的第二极与对应的阳极图形耦接。
  13. 一种显示装置，包括如权利要求1～12中任一项所述的显示面板。
  14. 一种显示面板的制作方法，所述制作方法包括：
    在基底上制作多个像素单元，所述多个像素单元呈阵列分布，每个像素单元均包括多个子像素；
    所述子像素包括沿远离所述基底的方向依次层叠设置的子像素驱动电路、平坦层和阳极图形；至少部分子像素中的所述阳极图形包括中间部分和包围所述中间部分的边缘部分，所述平坦层背向所述基底的表面具有沟槽， 所述沟槽在所述基底上的正投影包围所述中间部分在所述基底上的正投影，至少部分所述边缘部分在所述基底上的正投影位于所述沟槽在所述基底上的正投影的内部。
  15. 根据权利要求14所述的显示面板的制作方法，其中，所述子像素包括电源信号线图形和补偿图形，所述制作方法还包括：
    通过一次构图工艺，同时形成所述电源信号线图形与补偿图形，所述补偿图形位于所述平坦层朝向所述基底的表面，所述补偿图形在所述基底上的正投影与至少部分所述平坦层的沟槽在所述基底上的正投影交叠，和/或，所述补偿图形在所述基底上的正投影与所述阳极图形的中间部分在所述基底上的正投影交叠。
PCT/CN2021/087372 2020-05-27 2021-04-15 一种显示面板及其制作方法、显示装置 WO2021238478A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/637,248 US20220285458A1 (en) 2020-05-27 2021-04-15 Display panel, method for manufacturing the same and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010461694.4A CN111584599B (zh) 2020-05-27 2020-05-27 一种显示面板及其制作方法、显示装置
CN202010461694.4 2020-05-27

Publications (1)

Publication Number Publication Date
WO2021238478A1 true WO2021238478A1 (zh) 2021-12-02

Family

ID=72111148

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/087372 WO2021238478A1 (zh) 2020-05-27 2021-04-15 一种显示面板及其制作方法、显示装置

Country Status (3)

Country Link
US (1) US20220285458A1 (zh)
CN (1) CN111584599B (zh)
WO (1) WO2021238478A1 (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111584599B (zh) * 2020-05-27 2023-04-07 京东方科技集团股份有限公司 一种显示面板及其制作方法、显示装置
CN115835699A (zh) * 2020-08-31 2023-03-21 京东方科技集团股份有限公司 一种显示基板和显示装置
WO2022041244A1 (zh) * 2020-08-31 2022-03-03 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示装置
CN114616616B (zh) * 2020-08-31 2023-12-22 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示装置
US20220328588A1 (en) 2020-09-10 2022-10-13 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate and display panel
US11974463B2 (en) * 2020-10-19 2024-04-30 Chengdu Boe Optoelectronics Technology Co., Ltd. Array substrate and display apparatus
US20220416005A1 (en) * 2020-10-20 2022-12-29 Chengdu Boe Optoelectronics Technology Co., Ltd. Display panel and display device
CN114902320A (zh) * 2020-11-12 2022-08-12 京东方科技集团股份有限公司 显示基板及其驱动方法、显示装置
CN112435629B (zh) * 2020-11-24 2023-04-18 京东方科技集团股份有限公司 一种显示基板、显示装置
WO2022126366A1 (zh) * 2020-12-15 2022-06-23 京东方科技集团股份有限公司 显示基板和显示装置
CN112885884B (zh) * 2021-01-29 2023-06-27 鄂尔多斯市源盛光电有限责任公司 显示面板及其制造方法、显示装置
US20230180550A1 (en) * 2021-02-04 2023-06-08 Boe Technology Group Co., Ltd. Array substrate and display device
CN116325147A (zh) * 2021-08-24 2023-06-23 京东方科技集团股份有限公司 显示面板、显示装置
CN116830184A (zh) * 2022-01-10 2023-09-29 京东方科技集团股份有限公司 显示基板和显示装置
WO2023130439A1 (zh) * 2022-01-10 2023-07-13 京东方科技集团股份有限公司 显示基板和显示装置
CN115440789B (zh) * 2022-11-09 2023-04-28 北京京东方技术开发有限公司 显示面板和显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108565358A (zh) * 2018-01-19 2018-09-21 昆山国显光电有限公司 一种阳极刻蚀的方法及显示屏
CN109671762A (zh) * 2018-12-21 2019-04-23 武汉华星光电半导体显示技术有限公司 柔性显示面板、其制造方法及柔性显示装置
CN109950295A (zh) * 2019-04-10 2019-06-28 合肥鑫晟光电科技有限公司 Oled显示基板、oled显示装置、亮度补偿方法
CN111584599A (zh) * 2020-05-27 2020-08-25 京东方科技集团股份有限公司 一种显示面板及其制作方法、显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100711161B1 (ko) * 2002-09-12 2007-04-24 도시바 마쯔시따 디스플레이 테크놀로지 컴퍼니, 리미티드 유기 ｅｌ 디스플레이
JP2011044271A (ja) * 2009-08-19 2011-03-03 Panasonic Corp 表示パネル装置、表示装置、及び表示パネル装置の製造方法
JP6546387B2 (ja) * 2014-10-28 2019-07-17 株式会社ジャパンディスプレイ 表示装置
KR102648132B1 (ko) * 2016-12-26 2024-03-15 엘지디스플레이 주식회사 전계발광 표시장치
CN107968110B (zh) * 2017-11-21 2020-05-01 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置及其制作方法
CN109888119A (zh) * 2019-03-22 2019-06-14 合肥鑫晟光电科技有限公司 发光器件及其制作方法、显示装置
CN114759071A (zh) * 2019-04-09 2022-07-15 京东方科技集团股份有限公司 显示基板及其制造方法、显示装置
CN109994533B (zh) * 2019-04-17 2021-01-19 京东方科技集团股份有限公司 阵列基板、显示面板及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108565358A (zh) * 2018-01-19 2018-09-21 昆山国显光电有限公司 一种阳极刻蚀的方法及显示屏
CN109671762A (zh) * 2018-12-21 2019-04-23 武汉华星光电半导体显示技术有限公司 柔性显示面板、其制造方法及柔性显示装置
CN109950295A (zh) * 2019-04-10 2019-06-28 合肥鑫晟光电科技有限公司 Oled显示基板、oled显示装置、亮度补偿方法
CN111584599A (zh) * 2020-05-27 2020-08-25 京东方科技集团股份有限公司 一种显示面板及其制作方法、显示装置

Also Published As

Publication number Publication date
CN111584599B (zh) 2023-04-07
US20220285458A1 (en) 2022-09-08
CN111584599A (zh) 2020-08-25

Similar Documents

Publication Publication Date Title
WO2021238478A1 (zh) 一种显示面板及其制作方法、显示装置
US11744111B2 (en) Display device
WO2021227760A1 (zh) 一种显示面板及其制作方法、显示装置
WO2021104481A1 (zh) 显示基板、显示装置
WO2021227759A1 (zh) 一种显示面板及其制作方法、显示装置
WO2021227758A1 (zh) 一种显示面板及其制作方法、显示装置
WO2021227761A1 (zh) 一种显示面板及其制作方法、显示装置
CN100539233C (zh) 双面板型有机电致发光显示装置
CN113853643B (zh) 显示基板及其制作方法、显示装置
WO2021102999A1 (zh) 显示基板及显示装置
WO2020238288A1 (zh) 阵列基板及其制备方法、显示装置
WO2021189323A9 (zh) 显示面板及其制作方法、显示装置
WO2021097754A1 (zh) 显示面板及其制作方法、显示装置
WO2021103010A1 (zh) 显示基板及显示装置
WO2021258318A1 (zh) 显示基板及其制作方法、显示装置
US11877482B2 (en) Display substrate and method for manufacturing the same, driving method and display device
WO2021227023A1 (zh) 显示面板及其制作方法、显示装置
WO2022041237A1 (zh) 一种显示基板及其制作方法、显示装置
WO2022041238A1 (zh) 一种显示基板及其制作方法、显示装置
WO2024000317A1 (zh) 显示面板及显示装置
WO2022041246A1 (zh) 一种显示基板及其制作方法、显示装置
WO2022226818A1 (zh) 显示基板、显示面板和显示基板制造方法
WO2022246808A1 (zh) 显示装置、显示面板及其制造方法
WO2023130439A1 (zh) 显示基板和显示装置
CN117641977A (zh) 显示面板及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21813698

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21813698

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 23.6.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 21813698

Country of ref document: EP

Kind code of ref document: A1