WO2024086976A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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WO2024086976A1
WO2024086976A1 PCT/CN2022/127055 CN2022127055W WO2024086976A1 WO 2024086976 A1 WO2024086976 A1 WO 2024086976A1 CN 2022127055 W CN2022127055 W CN 2022127055W WO 2024086976 A1 WO2024086976 A1 WO 2024086976A1
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electrode
plate
substrate
layer
transistor
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PCT/CN2022/127055
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English (en)
French (fr)
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WO2024086976A9 (zh
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黄耀
周洋
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to CN202280003733.3A priority Critical patent/CN118251770A/zh
Priority to PCT/CN2022/127055 priority patent/WO2024086976A1/zh
Publication of WO2024086976A1 publication Critical patent/WO2024086976A1/zh
Publication of WO2024086976A9 publication Critical patent/WO2024086976A9/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

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  • This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT thin film transistors
  • the present disclosure provides a display substrate, including multiple circuit units, at least one circuit unit includes a pixel driving circuit, the pixel driving circuit includes a storage capacitor and multiple oxide transistors, the storage capacitor includes at least a first capacitor plate and a second capacitor plate, the orthographic projection of the first capacitor plate on the plane of the display substrate and the orthographic projection of the second capacitor plate on the plane of the display substrate at least partially overlap, and a capacitor insulating layer is arranged between the first capacitor plate and the second capacitor plate; on a plane perpendicular to the display substrate, at least one circuit unit includes a semiconductor layer and a first source-drain metal layer arranged on a substrate in a direction away from the substrate, at least one capacitor insulating layer is arranged on a side of the semiconductor layer close to the substrate, or at least one capacitor insulating layer is arranged on a side of the first source-drain metal layer away from the substrate.
  • At least one circuit unit includes at least a blocking conductive layer, a first insulating layer, a first gate metal layer, a second insulating layer, a semiconductor layer, a third insulating layer, a second gate metal layer, a fourth insulating layer and a first source-drain metal layer, which are arranged in sequence on the substrate in a direction away from the substrate, the first capacitor plate includes a first plate arranged in the blocking conductive layer, the second capacitor plate includes a second plate arranged in the first gate metal layer, the orthographic projection of the first plate on the substrate at least partially overlaps with the orthographic projection of the second plate on the substrate, and the first plate and the second plate constitute a first storage capacitor.
  • the first capacitor plate further includes a third plate disposed in the second gate metal layer, an orthographic projection of the third plate on the substrate at least partially overlaps an orthographic projection of the second plate on the substrate, and the third plate and the second plate constitute a second storage capacitor.
  • the third electrode plate is connected to the first electrode plate via a connecting electrode, and the first storage capacitor and the second storage capacitor constitute storage capacitors in a parallel structure.
  • the multiple oxide transistors include at least a driving transistor, the driving transistor includes a bottom gate electrode and a top gate electrode, the bottom gate electrode of the driving transistor is arranged in the first gate metal layer, the top gate electrode of the driving transistor is arranged in the second gate metal layer, the bottom gate electrode of the driving transistor and the second electrode plate are an integral structure connected to each other, and the top gate electrode of the driving transistor and the third electrode plate are an integral structure connected to each other.
  • the plurality of oxide transistors further include a compensation transistor and a first reset transistor, wherein a first electrode of the first reset transistor is connected to a first initial signal line, a second electrode of the compensation transistor is connected to a first electrode of the driving transistor, and the second electrode of the first reset transistor and the first electrode of the compensation transistor are connected to a top gate electrode of the driving transistor.
  • the plurality of oxide transistors further include a light emitting transistor and a second reset transistor, a first electrode of the light emitting transistor being connected to a second electrode of the driving transistor, a first electrode of the second reset transistor being connected to a second initial signal line, and a second electrode of the light emitting transistor and a second electrode of the second reset transistor being connected to a bottom gate electrode of the driving transistor.
  • At least one circuit unit includes at least a blocking conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first gate metal layer, a fourth insulating layer, a first source-drain metal layer, a first flat layer, and a second source-drain metal layer, which are arranged in sequence on the substrate in a direction away from the substrate, the first capacitor plate includes a fourth plate arranged in the first source-drain metal layer, the second capacitor plate includes a fifth plate arranged in the second source-drain metal layer, the orthographic projection of the fourth plate on the substrate at least partially overlaps with the orthographic projection of the fifth plate on the substrate, and the fourth plate and the fifth plate constitute a third storage capacitor.
  • the first source-drain metal layer and the first flat layer are further provided with a fifth insulating layer, a flat groove is provided on the first flat layer, the first flat layer in the flat groove is removed to expose the fifth insulating layer, the fifth electrode plate is provided in the flat groove, and the orthographic projection of the flat groove on the substrate includes the orthographic projections of the fourth electrode plate and the second electrode plate on the substrate.
  • At least one circuit unit further includes a second flat layer disposed on a side of the second source-drain metal layer away from the substrate and a third source-drain metal layer disposed on a side of the second flat layer away from the substrate
  • the first capacitor plate further includes a sixth plate disposed in the third source-drain metal layer, an orthographic projection of the sixth plate on the substrate at least partially overlaps with an orthographic projection of the fifth plate on the substrate, and the fifth plate and the sixth plate constitute a fourth storage capacitor.
  • the sixth electrode plate is connected to the fourth electrode plate via a connecting electrode, and the third storage capacitor and the fourth storage capacitor constitute storage capacitors in a parallel structure.
  • the multiple oxide transistors include at least a driving transistor, the driving transistor including a bottom gate electrode and a top gate electrode, the bottom gate electrode of the driving transistor is arranged in the blocking conductive layer, the top gate electrode of the driving transistor is arranged in the first conductive layer, and the fourth electrode is connected to the top gate electrode of the driving transistor through a via.
  • the plurality of oxide transistors further include a compensation transistor and a first reset transistor, wherein a first electrode of the first reset transistor is connected to a first initial signal line, a second electrode of the compensation transistor is connected to a first electrode of the driving transistor, and the second electrode of the first reset transistor and the first electrode of the compensation transistor are connected to a top gate electrode of the driving transistor.
  • the plurality of oxide transistors further include a data write transistor having a first electrode connected to a data signal line, and a second electrode of the data write transistor and a second electrode of the drive transistor connected to a bottom gate electrode of the drive transistor.
  • the present disclosure further provides a display device, comprising the aforementioned display substrate.
  • the present disclosure further provides a method for preparing a display substrate, wherein the display substrate includes a plurality of circuit units, at least one circuit unit includes a pixel driving circuit, the pixel driving circuit includes a storage capacitor and a plurality of oxide transistors, the storage capacitor includes a first capacitor plate and a second capacitor plate, an orthographic projection of the first capacitor plate on a plane of the display substrate and an orthographic projection of the second capacitor plate on the plane of the display substrate at least partially overlap, and a capacitor insulating layer is provided between the first capacitor plate and the second capacitor plate; the preparation method includes:
  • a semiconductor layer and a first source-drain metal layer are formed on a substrate along a direction away from the substrate, and at least one capacitor insulating layer is arranged on a side of the semiconductor layer close to the substrate, or at least one capacitor insulating layer is arranged on a side of the first source-drain metal layer away from the substrate.
  • FIG1 is a schematic structural diagram of a display device
  • FIG2 is a schematic diagram of a planar structure of a display substrate
  • FIG3 is a schematic diagram of a cross-sectional structure of a display substrate
  • FIG4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • FIG5 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure
  • Fig. 6A is a schematic cross-sectional view taken along line A-A in Fig. 5;
  • Fig. 6B is a schematic cross-sectional view taken along line B-B in Fig. 5;
  • FIG6C is an equivalent circuit diagram of the pixel driving circuit shown in FIG5 ;
  • FIG7 is a schematic diagram of a display substrate after a shielding conductive layer pattern is formed according to the present disclosure
  • FIGS. 8A and 8B are schematic diagrams of a display substrate after a first conductive layer pattern is formed according to the present disclosure
  • FIGS. 9A and 9B are schematic diagrams of a display substrate after a semiconductor layer pattern is formed according to the present disclosure.
  • FIGS. 10A and 10B are schematic diagrams of a display substrate after a second conductive layer pattern is formed according to the present disclosure
  • FIG11 is a schematic diagram of a display substrate after a fourth insulating layer pattern is formed according to the present disclosure.
  • FIGS. 12A and 12B are schematic diagrams of a display substrate after a third conductive layer pattern is formed according to the present disclosure
  • FIG13 is a schematic diagram of a display substrate after forming a first flat layer pattern according to the present disclosure.
  • FIGS. 14A and 14B are schematic diagrams of a display substrate after a fourth conductive layer pattern is formed on the display substrate according to the present disclosure
  • 14C and 14D are schematic diagrams of a display substrate according to the present disclosure after another fourth conductive layer pattern is formed;
  • FIGS. 14E and 14F are schematic diagrams of a display substrate according to the present disclosure after forming another fourth conductive layer pattern
  • FIGS. 14G and 14H are schematic diagrams of a display substrate according to the present disclosure after forming another fourth conductive layer pattern
  • FIG15 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure.
  • FIG16A is a schematic cross-sectional view taken along the C-C line in FIG15 ;
  • FIG16B is a schematic cross-sectional view taken along the line D-D in FIG15 ;
  • FIG16C is an equivalent circuit diagram of the pixel driving circuit shown in FIG15 ;
  • FIG17 is a schematic diagram of another display substrate after forming a shielding conductive layer pattern according to the present disclosure.
  • FIG18 is a schematic diagram of another display substrate after a semiconductor layer pattern is formed in the present disclosure.
  • FIG19 is a schematic diagram of another display substrate after forming a first conductive layer pattern according to the present disclosure.
  • FIG20 is a schematic diagram of another display substrate after a fourth insulating layer pattern is formed in the present disclosure.
  • FIG21 is a schematic diagram of another display substrate after a third conductive layer pattern is formed in the present disclosure.
  • FIG22 is a schematic diagram of another display substrate after forming a first flat layer pattern according to the present disclosure.
  • FIG23 is a schematic diagram of another display substrate after a fourth conductive layer pattern is formed in the present disclosure.
  • FIG24 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure.
  • Fig. 25A is a schematic cross-sectional view taken along line E-E in Fig. 24;
  • FIG25B is a schematic cross-sectional view taken along line F-F in FIG24 ;
  • FIG25C is an equivalent circuit diagram of the pixel driving circuit shown in FIG24 ;
  • FIG26 is a schematic diagram of another display substrate after forming a shielding conductive layer pattern according to the present disclosure.
  • FIG27 is a schematic diagram of another display substrate after a semiconductor layer pattern is formed in the present disclosure.
  • FIG28 is a schematic diagram of another display substrate after forming a first conductive layer pattern according to the present disclosure.
  • FIG29 is a schematic diagram of another display substrate after forming a second conductive layer pattern according to the present disclosure.
  • FIG30 is a schematic diagram of another display substrate after a fourth insulating layer pattern is formed in the present disclosure.
  • FIG31 is a schematic diagram of another display substrate after a third conductive layer pattern is formed in the present disclosure.
  • FIG32 is a schematic diagram of another display substrate after forming a first flat layer pattern according to the present disclosure.
  • FIG33 is a schematic diagram of another display substrate after a fourth conductive layer pattern is formed in the present disclosure.
  • FIG34 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure.
  • FIG35 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure.
  • FIG. 36 is a schematic diagram of a planar structure of yet another display substrate according to an exemplary embodiment of the present disclosure.
  • 16 shielding electrode
  • 20 driving circuit layer
  • 21 first active layer
  • 61 anode connection electrode
  • 62 first power line
  • 63 data signal line
  • 64 initial connection line
  • 71 first electrode plate
  • 72 second electrode plate
  • 91 first insulating layer
  • 92 second insulating layer
  • 93 third insulating layer
  • the proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values shown in the drawings.
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the “source electrode” and the “drain electrode” may be interchanged, and the “source terminal” and the “drain terminal” may be interchanged.
  • electrical connection includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the “element having some electrical function” as long as it can transmit and receive electrical signals between the connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film”.
  • insulating film may be replaced by “insulating layer”.
  • triangles, rectangles, trapezoids, pentagons or hexagons are not strictly defined, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc., and may have some small deformations caused by tolerances, and may have chamfers, arc edges and deformations, etc.
  • "About" in this disclosure means that the limits are not strictly defined, and the values within the range of process and measurement errors are allowed.
  • FIG1 is a schematic diagram of the structure of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, wherein the timing controller is respectively connected to the data driver, the scan driver, and the light emitting driver, wherein the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo).
  • D1 to Dn data signal lines
  • S1 to Sm scan signal lines
  • E1 to Eo light emitting signal lines
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit may include a pixel driving circuit, and the pixel driving circuit is connected to the scan signal line, the light emitting signal line, and the data signal line.
  • the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, may provide a clock signal suitable for the specifications of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specifications of the light emitting driver, an emission stop signal, etc. to the light emitting driver.
  • the data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using grayscale values and control signals received from the timing controller. For example, the data driver can sample grayscale values using a clock signal, and apply data voltages corresponding to grayscale values to data signal lines D1 to Dn in units of unit lines, where n can be a natural number.
  • the scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with conduction level pulses to scan signal lines S1 to Sm.
  • the scan driver can be constructed in the form of a shift register, and can sequentially transmit scan start signals provided in the form of conduction level pulses to the next level circuit under the control of the clock signal to generate scan signals, where m can be a natural number.
  • the light-emitting driver can generate emission signals to be provided to light-emitting signal lines E1, E2, E3, ... and Eo by receiving clock signals, emission stop signals, etc. from the timing controller.
  • the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo.
  • the light emitting driver may be constructed in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number.
  • FIG2 is a schematic diagram of a planar structure of a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix manner, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light.
  • Each sub-pixel may include a circuit unit and a light-emitting device, and the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to a scanning signal line, a light-emitting signal line, and a data signal line, and the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device.
  • the light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel in which it is located, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.
  • the first sub-pixel P1 may be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light
  • the third sub-pixel P3 may be a green sub-pixel (G) emitting green light.
  • the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal, and the three sub-pixels may be arranged in a horizontal parallel, vertical parallel or triangular manner, which is not limited in the present disclosure.
  • a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.
  • FIG3 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of four sub-pixels.
  • the display substrate may include a driving circuit layer 20 disposed on a substrate 10, a light emitting structure layer 30 disposed on a side of the driving circuit layer 20 away from the substrate 10, and an encapsulation structure layer 40 disposed on a side of the light emitting structure layer 30 away from the substrate 10.
  • the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.
  • the substrate 10 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 20 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor.
  • the light-emitting structure layer 30 may include a plurality of light-emitting devices, each of which may include at least an anode, a pixel definition layer, an organic light-emitting layer and a cathode, the anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode.
  • the encapsulation structure layer 40 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, forming an inorganic material/organic material/inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 30.
  • OLED display technology matures and its yield rate continues to increase, the cost of OLED display devices continues to decrease, allowing OLED display devices to be gradually applied to more fields, such as medium and large-sized electronic products.
  • LTPS low-temperature polysilicon
  • An exemplary embodiment of the present disclosure provides a display substrate, including multiple circuit units, at least one circuit unit includes a pixel driving circuit, the pixel driving circuit includes a storage capacitor and multiple oxide transistors, the storage capacitor includes at least a first capacitor plate and a second capacitor plate, the orthographic projection of the first capacitor plate on the plane of the display substrate and the orthographic projection of the second capacitor plate on the plane of the display substrate at least partially overlap, and a capacitor insulating layer is arranged between the first capacitor plate and the second capacitor plate; on a plane perpendicular to the display substrate, at least one circuit unit includes a semiconductor layer and a first source-drain metal layer arranged on a substrate in a direction away from the substrate, at least one capacitor insulating layer is arranged on a side of the semiconductor layer close to the substrate, or at least one capacitor insulating layer is arranged on a side of the first source-drain metal layer away from the substrate.
  • At least one circuit unit includes at least a blocking conductive layer, a first insulating layer, a first gate metal layer, a second insulating layer, a semiconductor layer, a third insulating layer, a second gate metal layer, a fourth insulating layer and a first source-drain metal layer, which are arranged in sequence on the substrate in a direction away from the substrate, the first capacitor plate includes a first plate arranged in the blocking conductive layer, the second capacitor plate includes a second plate arranged in the first gate metal layer, the orthographic projection of the first plate on the substrate at least partially overlaps with the orthographic projection of the second plate on the substrate, and the first plate and the second plate constitute a first storage capacitor.
  • the first capacitor plate further includes a third plate disposed in the second gate metal layer, an orthographic projection of the third plate on the substrate at least partially overlaps an orthographic projection of the second plate on the substrate, and the third plate and the second plate constitute a second storage capacitor.
  • the third electrode plate is connected to the first electrode plate via a connecting electrode, and the first storage capacitor and the second storage capacitor constitute storage capacitors in a parallel structure.
  • At least one circuit unit includes at least a blocking conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first gate metal layer, a fourth insulating layer, a first source-drain metal layer, a first flat layer, and a second source-drain metal layer, which are arranged in sequence on the substrate along a direction away from the substrate, the first capacitor plate includes a fourth plate arranged in the first source-drain metal layer, the second capacitor plate includes a fifth plate arranged in the second source-drain metal layer, the orthographic projection of the fourth plate on the substrate at least partially overlaps with the orthographic projection of the fifth plate on the substrate, and the fourth plate and the fifth plate constitute a third storage capacitor.
  • At least one circuit unit further includes a second flat layer disposed on a side of the second source-drain metal layer away from the substrate and a third source-drain metal layer disposed on a side of the second flat layer away from the substrate
  • the first capacitor plate further includes a sixth plate disposed in the third source-drain metal layer, an orthographic projection of the sixth plate on the substrate at least partially overlaps with an orthographic projection of the fifth plate on the substrate, and the fifth plate and the sixth plate constitute a fourth storage capacitor.
  • the sixth electrode plate is connected to the fourth electrode plate via a connecting electrode, and the third storage capacitor and the fourth storage capacitor constitute storage capacitors in a parallel structure.
  • the material of the semiconductor layer may include indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the exemplary embodiments of the present disclosure are not limited thereto.
  • the material of the semiconductor layer may be other metal oxide materials.
  • the display substrate of the present disclosure is illustrated below by means of some examples.
  • FIG4 is an equivalent circuit diagram of a pixel driving circuit of an exemplary embodiment of the present disclosure.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • the pixel driving circuit of the exemplary embodiment of the present disclosure may include 7 transistors (a first transistor T1 to a seventh transistor T7) and a storage capacitor C, and the pixel driving circuit is respectively connected to 9 signal lines (a first scanning signal line S1, a second scanning signal line S2, a third scanning signal line S3, a fourth scanning signal line S4, a light emitting signal line E, a first initial signal line INIT1, a second initial signal line INIT2, a data signal line D and a first power line VDD).
  • 9 signal lines a first scanning signal line S1, a second scanning signal line S2, a third scanning signal line S3, a fourth scanning signal line S4, a light emitting signal line E, a first initial signal line INIT1, a second initial signal line INIT2, a data signal line D and a first power line VDD.
  • the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4.
  • the first node N1 is respectively connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C
  • the second node N2 is respectively connected to the second electrode of the second transistor T2, the first electrode of the third transistor T3, and the second electrode of the fifth transistor T5
  • the third node N3 is respectively connected to the second electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the first electrode of the sixth transistor T6,
  • the fourth node N4 is respectively connected to the second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7, and the second end of the storage capacitor C
  • the fourth node N4 is also connected to the anode of the light emitting device EL.
  • a first end of the storage capacitor C is connected to the first node N1, and a second end of the storage capacitor C is connected to the fourth node N4, that is, the first end of the storage capacitor C is connected to the gate electrode of the third transistor T3, and the second end of the storage capacitor C is connected to the anode of the light emitting device EL.
  • a gate electrode of the first transistor T1 is connected to the third scan signal line S3, a first electrode of the first transistor T1 is connected to the first initialization signal line INIT1, and a second electrode of the first transistor T1 is connected to the first node N1.
  • an on-level scan signal is applied to the third scan signal line S3, the first transistor T1 is turned on, and the first initialization voltage is transmitted to the first end of the storage capacitor C, so that the storage capacitor C is initialized.
  • a gate electrode of the second transistor T2 is connected to the first scan signal line S1
  • a first electrode of the second transistor T2 is connected to the first node N1
  • a second electrode of the second transistor T2 is connected to the second node N2.
  • the second transistor T2 connects the gate electrode of the third transistor T3 to the first electrode of the third transistor T3.
  • the gate electrode of the third transistor T3 is connected to the first node N1, that is, the gate electrode of the third transistor T3 is connected to the first end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the third transistor T3 can be called a driving transistor, and the third transistor T3 determines the size of the driving current flowing between the first power line VDD and the light emitting device according to the potential difference between its gate electrode and the first electrode.
  • a gate electrode of the fourth transistor T4 is connected to the second scan signal line S2, a first electrode of the fourth transistor T4 is connected to the data signal line D, and a second electrode of the fourth transistor T4 is connected to the third node N3.
  • the fourth transistor T4 inputs a data voltage of the data signal line D to the third node N3.
  • a gate electrode of the fifth transistor T5 is connected to the light emitting signal line E, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2.
  • a gate electrode of the sixth transistor T6 is connected to the light emitting signal line E, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4.
  • a gate electrode of the seventh transistor T7 is connected to the fourth scan signal line S4, a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4.
  • the seventh transistor T7 transmits the second initial voltage to the first electrode of the light emitting device to initialize or release the charge accumulated in the first electrode of the light emitting device EL.
  • the light emitting device EL may be an OLED including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode).
  • the seven transistors of the pixel driving circuit may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.
  • the seven transistors of the pixel driving circuit may be oxide thin film transistors.
  • the active layer of the oxide thin film transistor may be oxide semiconductor (Oxide).
  • the oxide thin film transistor has advantages such as low leakage current.
  • the display substrate provided with the oxide thin film transistor can realize low-frequency driving, reduce power consumption, and improve display quality.
  • the second pole of the light-emitting device is connected to the second power line VSS
  • the first power line VDD can be configured to provide a constant first voltage signal to the pixel driving circuit
  • the second power line VSS can be configured to provide a constant second voltage signal to the pixel driving circuit
  • the first voltage signal is greater than the second voltage signal.
  • the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel driving circuit
  • the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel driving circuit.
  • the first initial signal may be different from the second initial signal.
  • the first initial signal and the second initial signal may be constant voltage signals, and their sizes may be, for example, between the first voltage signal provided by the first power line VDD and the second voltage signal provided by the second power line VSS, but are not limited thereto.
  • the first initial signal and the second initial signal may be the same, and only the first initial signal line may be set to provide the first initial signal.
  • the operation process of the pixel driving circuit may include the following stages.
  • the first stage A1 is called the initialization stage.
  • the high level signal provided by the third scanning signal line S3 turns on the first transistor T1, and the first initial signal provided by the first initial signal line INIT1 is provided to the first node N1 to initialize the first node N1 and clear the original data voltage in the storage capacitor C.
  • the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off, and the light emitting element EL does not emit light.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the first scanning signal line S1, the second scanning signal line S2 and the fourth scanning signal line S4 provide high-level signals to turn on the second transistor T2, the fourth transistor T4 and the seventh transistor T7.
  • the third transistor T3 is turned on.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage Vd output by the data signal line D is provided to the first node N1 through the third node N3, the turned-on third transistor T3, the second node N2, and the turned-on second transistor T2, and the difference between the data voltage Vd output by the data signal line D and the threshold voltage Vth of the third transistor T3 is charged into the storage capacitor C.
  • the seventh transistor T7 is turned on so that the second initial signal provided by the second initial signal line INIT2 is provided to the anode of the light-emitting element EL, the anode of the light-emitting element EL is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and it is ensured that the light-emitting element EL does not emit light.
  • the first transistor T1, the fifth transistor T5 and the sixth transistor T6 are disconnected.
  • the third stage A3 is called the light emitting stage.
  • the light emitting control line E provides a high level signal to turn on the fifth transistor T5 and the sixth transistor T6.
  • the first voltage signal output by the first power line VDD provides a driving voltage to the anode of the light emitting element EL through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the light emitting element EL to emit light.
  • the driving current flowing through the third transistor T3 (i.e., the driving transistor) is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vd-
  • )-Vth] 2 K ⁇ [Vdd-Vd] 2 .
  • I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting element EL
  • K is a constant
  • Vgs is the voltage difference between the gate and the first electrode of the third transistor T3
  • Vth is the threshold voltage of the third transistor T3
  • Vd is the data voltage output by the data signal line D
  • Vdd is the first voltage signal output by the first power line VDD.
  • the current flowing through the light emitting element EL has nothing to do with the threshold voltage of the third transistor T3.
  • the pixel driving circuit of this embodiment can better compensate for the threshold voltage of the third transistor T3.
  • FIG5 is a schematic diagram of a planar structure of a display substrate of an exemplary embodiment of the present disclosure, illustrating the structure of a pixel driving circuit in a circuit unit
  • FIG6A is a schematic cross-sectional diagram along the A-A direction in FIG5
  • FIG6B is a schematic cross-sectional diagram along the B-B direction in FIG5
  • FIG6C is an equivalent circuit diagram of the pixel driving circuit shown in FIG5 .
  • the display substrate in a direction perpendicular to the display substrate, may include a driving circuit layer disposed on a substrate, a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate, and an encapsulation structure layer disposed on a side of the light emitting structure layer away from the substrate.
  • the driving circuit layer may include circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit includes a pixel driving circuit, and the pixel driving circuit may include a storage capacitor, a first transistor T1 to a seventh transistor T7, and the first transistor T1 to the seventh transistor T7 are oxide transistors.
  • the driving circuit layer may include at least: a shielding conductive layer arranged on the substrate 10, a first insulating layer 91 arranged on the side of the shielding conductive layer away from the substrate, a first conductive layer arranged on the side of the first insulating layer 91 away from the substrate, a second insulating layer 92 arranged on the side of the first conductive layer away from the substrate, a semiconductor layer arranged on the side of the second insulating layer 92 away from the substrate, a third insulating layer 93 arranged on the side of the semiconductor layer away from the substrate, a second conductive layer arranged on the side of the third insulating layer 93 away from the substrate, a fourth insulating layer 94 arranged on the side of the second conductive layer away from the substrate, and a third conductive layer arranged on the side of the fourth insulating layer 94 away from the substrate.
  • the shielding conductive layer may include at least a first electrode 71 of a storage capacitor, the first conductive layer may include at least a second electrode 72 of a storage capacitor, the semiconductor layer may include at least an active layer of the first transistor to an active layer of a seventh transistor, the second conductive layer may include at least a third electrode 73 of the storage capacitor, and the third conductive layer may include at least a plurality of connecting electrodes.
  • the orthographic projection of the first electrode plate 71 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 72 on the substrate, the first electrode plate 71 and the second electrode plate 72 constitute a first storage capacitor, and the first insulating layer 91 is a capacitor insulating layer disposed between the first electrode plate 71 and the second electrode plate 72.
  • the orthographic projection of the third electrode plate 73 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 72 on the substrate, the second electrode plate 72 and the third electrode plate 73 constitute a second storage capacitor, and the first storage capacitor and the second storage capacitor constitute a storage capacitor in a parallel structure.
  • the first transistor T1 to the seventh transistor T7 may each include a bottom gate electrode and a top gate electrode, the bottom gate electrode may be disposed in the first conductive layer, and the top gate electrode may be disposed in the second conductive layer.
  • the third electrode plate 73 in the second conductive layer may serve as the top gate electrode of the third transistor T3 and be connected to the first node N1 of the pixel driving circuit
  • the second electrode plate 72 in the first conductive layer may serve as the bottom gate electrode of the third transistor T3 to shield the third transistor T3 and be connected to the fourth node N4 of the pixel driving circuit, as shown in FIG6C .
  • the second conductive layer may further include a first initial sub-line 41 and a second initial sub-line 42
  • the plurality of connecting electrodes of the third conductive layer may include at least: a first connecting electrode 51, a second connecting electrode 52, a third connecting electrode 53, a fourth connecting electrode 54, a fifth connecting electrode 55, a sixth connecting electrode 56, a seventh connecting electrode 57, an eighth connecting electrode 58, a ninth connecting electrode 59 and a tenth connecting electrode 60.
  • the first connection electrode 51 can serve as a first node electrode (N1 node electrode) of a pixel driving circuit, a first end of the first connection electrode 51 is connected to the third electrode plate 73 through a via, and a second end of the first connection electrode 51 is connected to the second region of the first active layer (also the first region of the second active layer) through a via, thereby achieving the same potential for the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the third electrode plate 73 (the top gate electrode of the third transistor T3).
  • the second connection electrode 52 can be connected to the first region of the fifth active layer through a via hole. Since the second connection electrode 52 is configured to be connected to the first power line, the first power line writes the first power voltage into the first electrode of the fifth transistor T5 through the second connection electrode 52.
  • the third connection electrode 53 can serve as the second node electrode (N2 node electrode) of the pixel driving circuit, and the first end of the third connection electrode 53 is connected to the second region of the second active layer (also the first region of the third active layer) through a via, and the second end of the third connection electrode 53 is connected to the second region of the fifth active layer through a via, thereby achieving the same potential for the second electrode of the second transistor T2, the first electrode of the third transistor T3, and the second electrode of the fifth transistor T5.
  • the fourth connection electrode 54 can serve as a data input electrode of the pixel driving circuit.
  • the fourth connection electrode 54 is connected to the first area of the fourth active layer 24 through a via. Since the fourth connection electrode 54 is configured to be connected to the data signal line, the data signal line writes the data signal into the first electrode of the fourth transistor T4 through the fourth connection electrode 54.
  • the fifth connection electrode 55 can serve as the third node electrode (N3 node electrode) of the pixel driving circuit.
  • the fifth connection electrode 55 is connected to the second region of the fourth active layer 24 (also the second region of the third active layer) through a via hole.
  • the fifth connection electrode 55 is connected to the first region of the sixth active layer through a via hole, thereby achieving the same potential for the second electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the first electrode of the sixth transistor T6.
  • the sixth connection electrode 56 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through a via hole, thereby achieving the second electrodes of the sixth transistor T6 and the seventh transistor T7 to have the same potential.
  • the seventh connection electrode 57 can be used as the fourth node electrode (N4 node electrode) of the pixel driving circuit.
  • the seventh connection electrode 57 is connected to the second electrode plate 72 through a via hole, and on the other hand, the seventh connection electrode 57 is connected to the sixth connection electrode 56 through an anode connection electrode (not shown), thereby achieving the second electrode plate 72 of the storage capacitor, the second electrode of the sixth transistor T6, and the second electrode of the seventh transistor T7 having the same potential. Since the second electrode plate 72 also serves as the bottom gate electrode of the third transistor T3, the bottom gate electrode of the third transistor T3 has the potential of the fourth node electrode N4.
  • the first end of the tenth connecting electrode 60 is connected to the first electrode plate 71 through a via, and the second end of the tenth connecting electrode 60 is connected to the third electrode plate 73 through a via, thereby achieving that the first electrode plate 71 and the third electrode plate 73 have the same potential, and the first electrode plate 71, the second electrode plate 72 and the third electrode plate 73 constitute a storage capacitor of a parallel structure.
  • the first initial sub-lines 41 may be arranged at intervals along the first direction X, and the first initial sub-lines 41 adjacent to each other in the first direction X are connected to each other through the eighth connection electrode 58 to form a first initial signal line extending along the first direction X.
  • the eighth connection electrode 58 is also connected to the first region of the first active layer through a via hole, thereby enabling the first initial signal line to write the first initial voltage into the first electrode of the first transistor T1.
  • the second initial sub-lines 42 may be arranged at intervals along the first direction X, and the second initial sub-lines 42 adjacent to each other in the first direction X are connected to each other through the ninth connection electrode 59 to form a second initial signal line extending along the first direction X.
  • the ninth connection electrode 59 is also connected to the first region of the seventh active layer through a via hole, thereby enabling the second initial signal line to write the second initial voltage into the first electrode of the seventh transistor T7.
  • the "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials.
  • Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition
  • coating can be any one or more of spraying, spin coating, and inkjet printing
  • etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure.
  • Thin film refers to a layer of thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the "A and B are arranged in the same layer” in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A” or "the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • a process of preparing a display substrate may include the following operations.
  • Forming a blocking conductive layer pattern may include: depositing a blocking film on a substrate, patterning the blocking film by a patterning process, and forming a blocking conductive layer pattern on the substrate, as shown in FIG. 7 .
  • the shielding conductive layer pattern may include at least a first electrode plate 71 .
  • the first electrode plate 71 may be rectangular in shape, and the corners of the rectangle may be chamfered.
  • the first electrode plate 71 may serve as a plate of a storage capacitor.
  • a first connection block 81 is further connected to one side of the first electrode plate 71 in the first direction X.
  • the first connection block 81 is configured to be connected to a tenth connection electrode formed subsequently to achieve mutual connection between the first electrode plate 71 and a third electrode plate formed subsequently.
  • the material of the blocking conductive layer may be metal molybdenum (Mo), and the thickness of the blocking conductive layer may be about 80 nm to 120 nm.
  • the thickness of the blocking conductive layer may be about 100 nm.
  • forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process, forming a first insulating layer covering the shielding conductive layer pattern, and a first conductive layer pattern disposed on the first insulating layer, as shown in FIGS. 8A and 8B , where FIG. 8B is a plan view of the first conductive layer in FIG. 8A .
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern may include at least a first shielding line 11 , a second shielding line 12 , a third shielding line 13 , a fourth shielding line 14 , a fifth shielding line 15 and a second plate 72 of a storage capacitor.
  • the shapes of the first shielding line 11, the second shielding line 12, the third shielding line 13, the fourth shielding line 14 and the fifth shielding line 15 may be straight lines extending along the first direction X.
  • the first shielding line 11 may be located on the side of the second plate 72 in the opposite direction of the second direction Y, and the first shielding line 11 is configured to shield the second transistor T2 and serve as the bottom gate electrode of the second transistor T2.
  • the second shielding line 12 may be located on the side of the second plate 72 in the second direction Y, and the second shielding line 12 is configured to shield the fourth transistor T4 and serve as the bottom gate electrode of the fourth transistor T4.
  • the third shielding line 13 may be located on the side of the first shielding line 11 away from the second plate 72, and the third shielding line 13 is configured to shield the first transistor T1 and serve as the bottom gate electrode of the first transistor T1.
  • the fourth shielding line 14 may be located on the side of the second shielding line 12 away from the second plate 72, and the fourth shielding line 14 is configured to shield the seventh transistor T7 and serve as the bottom gate electrode of the seventh transistor T7.
  • the fifth shielding line 15 may be located between the second shielding line 12 and the fourth shielding line 14 , and the fifth shielding line 15 is configured to shield the fifth transistor T5 and the sixth transistor T6 and serve as the bottom gate electrode of the fifth transistor T5 and the sixth transistor T6 .
  • a extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions.
  • a extends along direction B means “the main part of A extends along direction B".
  • the second electrode plate 72 can be located between the first shielding line 11 and the second shielding line 12, the outline of the second electrode plate 72 can be rectangular, the corners of the rectangle can be chamfered, the orthographic projection of the second electrode plate 72 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 71 on the substrate, and the second electrode plate 72 can serve as another electrode plate of the storage capacitor.
  • the second electrode plate 72 is also configured to shield a third transistor to be formed subsequently and serve as a bottom gate electrode of the third transistor T3 .
  • the first insulating layer is a capacitor insulating layer disposed between the first electrode plate and the second electrode plate, the material of the first insulating layer may be SiNx, and the thickness of the first insulating layer may be about 100 nm to 170 nm. For example, the thickness of the first insulating layer may be about 130 nm.
  • the material of the first conductive layer may be Mo, and the thickness of the first conductive layer may be about 200 nm to 300 nm.
  • the thickness of the first conductive layer may be about 250 nm.
  • Forming a semiconductor layer pattern may include: sequentially depositing a second insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process to form a second insulating layer covering the first conductive layer, and a semiconductor layer pattern disposed on the second insulating layer, as shown in FIGS. 9A and 9B , where FIG. 9B is a plan view schematic diagram of the semiconductor layer in FIG. 9A .
  • the semiconductor layer pattern may include at least the first active layer 21 of the first transistor T1 to the seventh active layer 27 of the seventh transistor T7, and the first active layer 21, the second active layer 22, the third active layer 23 and the fourth active layer 24 are an integral structure connected to each other.
  • the first active layer 21, the second active layer 22, and the fifth active layer 25 may be located on the same side of the third active layer 23, and the second active layer 22 and the fourth active layer 24 may be located on different sides of the third active layer 23.
  • the first active layer 21 and the second active layer 22 may be located on a side of the third active layer 23 in the opposite direction of the second direction Y, and the fourth active layer 24, the fifth active layer 25, the sixth active layer 26, and the seventh active layer 27 may be located on a side of the third active layer 23 in the second direction Y.
  • the third active layer 23 may have an “n” shape, and the first to seventh active layers 21 , 22 , 24 to 27 may have an “I” shape or an “L” shape.
  • the orthographic projection of the third active layer 23 on the substrate may be located within the range of the orthographic projection of the second electrode plate 72 on the substrate, so that the channel region of the third transistor T3 may be effectively shielded by the second electrode plate 72 .
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the second region 21-2 of the first active layer may serve as the first region 22-1 of the second active layer (i.e., the second region 21-2 of the first active layer is directly connected to the first region 22-1 of the second active layer)
  • the second region 22-2 of the second active layer may serve as the first region 23-1 of the third active layer (i.e., the second region 22-2 of the second active layer is directly connected to the first region 23-1 of the third active layer)
  • the second region 23-2 of the third active layer may serve as the second region 24-2 of the fourth active layer (i.e., the second region 24-2 of the third active layer).
  • the second region 23-2 of the sixth active layer is directly connected to the second region 24-2 of the fourth active layer
  • the second region 26-2 of the sixth active layer can serve as the second region 27-2 of the seventh active layer (i.e., the second region 26-2 of the sixth active layer is directly connected to the second region 27-2 of the seventh active layer)
  • the first region 21-1 of the first active layer, the first region 24-1 of the fourth active layer, the first region 25-1 of the fifth active layer, the second region 25-2 of the fifth active layer, the first region 26-1 of the sixth active layer and the first region 27-1 of the seventh active layer can be set separately.
  • the semiconductor layer may be made of oxide, and the first to seventh transistors T1 to T7 are all oxide transistors.
  • the semiconductor layer may be made of indium gallium zinc oxide (IGZO) having high electron mobility.
  • IGZO indium gallium zinc oxide
  • the thickness of the semiconductor layer may be about 20 nm to 40 nm.
  • the thickness of the semiconductor layer may be about 30 nm.
  • the material of the second insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.
  • the second insulating layer may be SiN/SiO.
  • the thickness of the second insulating layer may be about 350nm to 450nm.
  • the thickness of SiN in the second insulating layer may be about 100nm
  • the thickness of SiO in the second insulating layer may be about 300nm
  • the total thickness of the second insulating layer may be about 400nm.
  • Forming a second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the semiconductor layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIGS. 10A and 10B , where FIG. 10B is a plan view schematic diagram of the second conductive layer in FIG. 10A .
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the second conductive layer pattern may include at least first scan signal line 31 , second scan signal line 32 , third scan signal line 33 , fourth scan signal line 34 , light emission control line 35 , first initial sub-line 41 , second initial sub-line 42 and third electrode 73 .
  • the contour of the third electrode plate 73 can be rectangular, and the corners of the rectangle can be chamfered.
  • the orthographic projection of the third electrode plate 73 on the substrate at least partially overlaps with the orthographic projection of the third active layer on the substrate, and the orthographic projection of the third electrode plate 73 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 72 on the substrate.
  • the third electrode plate 73 can serve as the top gate electrode of the third transistor T3.
  • the third electrode plate 73 can serve as another electrode plate of the storage capacitor.
  • the first electrode plate 71, the second electrode plate 72 and the third electrode plate 73 constitute a storage capacitor of the parallel structure of the pixel driving circuit.
  • an opening 43 is provided on the third electrode plate 73.
  • the opening 43 may be rectangular and may be located in the middle of the third electrode plate 73, so that the third electrode plate 73 forms a ring structure.
  • the opening 43 exposes the third insulating layer, and the orthographic projection of the second electrode plate 72 on the substrate includes the orthographic projection of the opening 43 on the substrate.
  • the opening 43 is configured to accommodate a first via hole formed subsequently, and the first via hole is located in the opening 43 and exposes the second electrode plate 72, so that the second electrode of the first transistor T1 formed subsequently is connected to the second electrode plate 72.
  • a second connection block 82 is further connected to one side of the third electrode plate 73 in the first direction X.
  • the second connection block 82 is configured to be connected to a tenth connection electrode formed subsequently to achieve mutual connection between the first electrode plate 71 and the third electrode plate 73 .
  • the shapes of the first scan signal line 31 , the second scan signal line 32 , the third scan signal line 33 , the fourth scan signal line 34 , and the light emission control line 35 may be straight lines extending along the first direction X.
  • the first scan signal line 31 may be located on a side of the third electrode plate 73 in the opposite direction of the second direction Y, and the region where the first scan signal line 31 overlaps the second active layer serves as a top gate electrode of the second transistor T2 .
  • the orthographic projection of the first scan signal line 31 on the substrate may be located within the range of the orthographic projection of the first shielding line 11 on the substrate, so that the channel region of the second transistor T2 may be effectively shielded by the first shielding line 11 .
  • the second scan signal line 32 may be located at one side of the third electrode plate 73 in the second direction Y, and a region where the second scan signal line 32 overlaps the fourth active layer serves as a top gate electrode of the fourth transistor T4 .
  • the orthographic projection of the second scan signal line 32 on the substrate may be located within the range of the orthographic projection of the second shielding line 12 on the substrate, so that the channel region of the fourth transistor T4 may be effectively shielded by the second shielding line 12 .
  • the third scan signal line 33 may be located on a side of the first scan signal line 31 away from the third electrode plate 73 , and a region where the third scan signal line 33 overlaps the first active layer serves as a top gate electrode of the first transistor T1 .
  • the orthographic projection of the third scan signal line 33 on the substrate may be located within the range of the orthographic projection of the third shielding line 13 on the substrate, so that the channel region of the first transistor T1 may be effectively shielded by the third shielding line 13 .
  • the fourth scan signal line 34 may be located on a side of the second scan signal line 32 away from the third electrode plate 73 , and an area where the fourth scan signal line 34 overlaps the seventh active layer serves as a top gate electrode of the seventh transistor T7 .
  • the orthographic projection of the fourth scan signal line 34 on the substrate may be located within the range of the orthographic projection of the fourth shielding line 14 on the substrate, so that the channel region of the seventh transistor T7 may be effectively shielded by the fourth shielding line 14 .
  • the light emitting control line 35 can be located between the second scanning signal line 32 and the fourth scanning signal line 34, and the area where the light emitting control line 35 overlaps with the fifth active layer serves as the top gate electrode of the fifth transistor T5, and the area where the light emitting control line 35 overlaps with the sixth active layer serves as the top gate electrode of the sixth transistor T6.
  • the orthographic projection of the light emitting control line 35 on the substrate may be located within the range of the orthographic projection of the fifth shielding line 15 on the substrate, so that the channel regions of the fifth transistor T5 and the sixth transistor T6 may be effectively shielded by the fifth shielding line 15 .
  • the shape of the first initial sub-line 41 may be a line shape in which the main part extends along the first direction X.
  • the first initial sub-line 41 may be disposed between the first regions of the first active layers of the adjacent circuit units in the first direction X.
  • the first initial sub-line 41 may be located on a side of the third scan signal line 33 away from the third electrode plate 73.
  • the first initial sub-line 41 is configured to constitute a first initial signal line that transmits a first initial signal and extends along the first direction X using an eighth connection electrode formed subsequently.
  • the second initial sub-line 42 may be in the shape of a line whose main portion extends along the first direction X. In the first direction X, the second initial sub-line 42 may be disposed between the first regions of the seventh active layer of adjacent circuit units in the first direction X. In the second direction Y, the second initial sub-line 42 may be located on a side of the fourth scan signal line 34 away from the third electrode plate 73. The second initial sub-line 42 is configured to form a second initial signal line that transmits a second initial signal and extends along the first direction X using a ninth connection electrode formed subsequently.
  • the third insulating layer is a capacitor insulating layer disposed between the second electrode plate and the third electrode plate.
  • the material of the third insulating layer may be SiO, and the thickness of the third insulating layer may be about 100 nm to 170 nm. For example, the thickness of the third insulating layer may be about 140 nm.
  • the second conductive layer may be made of Mo, and the thickness of the second conductive layer may be about 200 nm to 300 nm.
  • the thickness of the second conductive layer may be about 250 nm.
  • Forming a fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein a plurality of vias are disposed on the fourth insulating layer, as shown in FIG. 11 .
  • the plurality of vias include at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18 and a nineteenth via V19.
  • the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the opening 43 on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the first via hole V1 are etched away to expose the surface of the second electrode plate 72, and the first via hole V1 is configured to connect a subsequently formed first connecting electrode to the second electrode plate 72 through the via hole.
  • the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second region of the first active layer (also the first region of the second active layer) on the substrate, the fourth insulating layer and the third insulating layer in the second via hole V2 are etched away to expose the surface of the second region of the first active layer, and the second via hole V2 is configured to connect a subsequently formed first connecting electrode to the second region of the first active layer (also the first region of the second active layer) through the via hole.
  • the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of the fifth active layer on the substrate, the fourth insulating layer and the third insulating layer in the third via hole V3 are etched away to expose the surface of the first area of the fifth active layer, and the third via hole V3 is configured to connect a subsequently formed second connecting electrode to the first area of the fifth active layer through the via hole.
  • the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second region of the fifth active layer on the substrate, the fourth insulating layer and the third insulating layer in the fourth via hole V4 are etched away to expose the surface of the second region of the fifth active layer, and the fourth via hole V4 is configured to connect a subsequently formed third connecting electrode to the second region of the fifth active layer through the via hole.
  • the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the second region of the second active layer (also the first region of the third active layer) on the substrate, the fourth insulating layer and the third insulating layer in the fifth via hole V5 are etched away to expose the surface of the second region of the second active layer, and the fifth via hole V5 is configured to connect a subsequently formed third connecting electrode to the second region of the second active layer (also the first region of the third active layer) through the via hole.
  • the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first area of the fourth active layer on the substrate, the fourth insulating layer and the third insulating layer in the sixth via hole V6 are etched away to expose the surface of the first area of the fourth active layer, and the sixth via hole V6 is configured to connect a subsequently formed fourth connecting electrode to the first area of the fourth active layer through the via hole.
  • the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the second area of the fourth active layer (also the second area of the third active layer) on the substrate, the fourth insulating layer and the third insulating layer in the seventh via hole V7 are etched away to expose the surface of the second area of the fourth active layer, and the seventh via hole V7 is configured to connect a subsequently formed fifth connecting electrode to the second area of the fourth active layer (also the second area of the third active layer) through the via hole.
  • the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the first region of the sixth active layer on the substrate, the fourth insulating layer and the third insulating layer in the eighth via hole V8 are etched away to expose the surface of the first region of the sixth active layer, and the eighth via hole V8 is configured to connect a subsequently formed fifth connecting electrode to the first region of the sixth active layer through the via hole.
  • the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the second area of the sixth active layer (also the second area of the seventh active layer) on the substrate, the fourth insulating layer and the third insulating layer in the ninth via hole V9 are etched away to expose the surface of the second area of the sixth active layer, and the ninth via hole V9 is configured to connect a subsequently formed sixth connecting electrode to the second area of the sixth active layer (also the second area of the seventh active layer) through the via hole.
  • the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the third electrode plate 73 on the substrate, the fourth insulating layer in the eleventh via hole V11 is etched away to expose the surface of the first electrode plate 71, and the eleventh via hole V11 is configured to connect a subsequently formed first connecting electrode to the third electrode plate 73 through the via hole.
  • the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the fourth insulating layer and the third insulating layer in the twelfth via hole V12 are etched away to expose the surface of the first region of the first active layer, and the twelfth via hole V12 is configured to connect a subsequently formed eighth connecting electrode to the first region of the first active layer through the via hole.
  • the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the fourth insulating layer and the third insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the first region of the seventh active layer, and the thirteenth via hole V13 is configured to connect a subsequently formed ninth connecting electrode to the first region of the seventh active layer through the via hole.
  • the orthographic projections of the fourteenth via hole V14 and the fifteenth via hole V15 on the substrate are located within the range of the orthographic projections of the first initial sub-line 41 on the substrate, the fourth insulating layer in the fourteenth via hole V14 and the fifteenth via hole V15 is etched away to expose the surface of the first initial sub-line 41, and the fourteenth via hole V14 and the fifteenth via hole V15 are configured to enable the subsequently formed eighth connecting electrode to connect adjacent first initial sub-lines 41 to each other through the via hole.
  • the orthographic projections of the sixteenth via hole V16 and the seventeenth via hole V17 on the substrate are located within the range of the orthographic projections of the second initial sub-line 42 on the substrate, the fourth insulating layer in the sixteenth via hole V16 and the seventeenth via hole V17 is etched away to expose the surface of the second initial sub-line 42, and the sixteenth via hole V16 and the seventeenth via hole V17 are configured to enable the subsequently formed ninth connecting electrode to connect adjacent second initial sub-lines 42 to each other through the via hole.
  • the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the first connecting block 81 of the first electrode plate 71 on the substrate, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer in the eighteenth via hole V18 are etched away to expose the surface of the first connecting block 81, and the eighteenth via hole V18 is configured to connect the subsequently formed tenth connecting electrode to the first electrode plate 71 through the via hole.
  • the orthographic projection of the nineteenth via hole V19 on the substrate is located within the range of the orthographic projection of the second connecting block 82 of the third electrode plate 73 on the substrate, the fourth insulating layer in the nineteenth via hole V19 is etched away to expose the surface of the second connecting block 82, and the nineteenth via hole V19 is configured to connect the subsequently formed tenth connecting electrode to the third electrode plate 73 through the via hole.
  • the material of the fourth insulating layer may be SiO, and the thickness of the fourth insulating layer may be about 500 nm to 600 nm.
  • the thickness of the second insulating layer may be about 550 nm.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the fourth insulating layer, as shown in FIGS. 12A and 12B , where FIG. 12B is a plan view of the third conductive layer in FIG. 12A .
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the third conductive layer may include at least a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57, an eighth connection electrode 58, a ninth connection electrode 59 and a tenth connection electrode 60.
  • the shape of the first connection electrode 51 can be a zigzag shape with the main part extending along the second direction Y.
  • the first end of the first connection electrode 51 is connected to the third electrode plate 73 through the eleventh via hole V11, and the second end of the first connection electrode 51 is connected to the second region of the first active layer (also the first region of the second active layer) through the second via hole V2, so that the second electrode of the first transistor T1, the first electrode of the second transistor T2 and the third electrode plate 73 (also the top gate electrode of the third transistor T3) have the same potential.
  • the first connection electrode 51 can serve as the first node N1 of the pixel driving circuit.
  • the second connection electrode 52 may be in a polygonal shape and connected to the first region of the fifth active layer through the third via hole V3. In an exemplary embodiment, the second connection electrode 52 is configured to be connected to a first power line formed subsequently.
  • the third connection electrode 53 may be in the shape of a strip having a main portion extending along the second direction Y, a first end of the third connection electrode 53 is connected to the second region of the fifth active layer through a fourth via hole V4, and a second end of the third connection electrode 53 is connected to the second region of the second active layer through a fifth via hole V5.
  • the third connection electrode 53 may serve as a second node N2 of the pixel driving circuit.
  • the fourth connection electrode 54 may be in the shape of a strip having a main portion extending along the second direction Y, and the fourth connection electrode 54 is connected to the first region of the fourth active layer through a sixth via hole V6.
  • the fourth connection electrode 54 may serve as a first electrode (referred to as a data input electrode) of the fourth transistor T4, and the fourth connection electrode 54 is configured to be connected to a subsequently formed data signal line.
  • the fifth connection electrode 55 may be in a zigzag shape with a main portion extending along the second direction Y. A first end of the fifth connection electrode 55 is connected to the second region of the fourth active layer (also the second region of the third active layer) through a seventh via hole V7, and a second end of the fifth connection electrode 55 is connected to the first region of the sixth active layer through an eighth via hole V8.
  • the fifth connection electrode 55 may serve as a third node N3 of the pixel driving circuit.
  • the sixth connection electrode 56 may be polygonal in shape and connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the ninth via hole V9. In an exemplary embodiment, the sixth connection electrode 56 is configured to be connected to a subsequently formed anode connection electrode.
  • the shape of the seventh connection electrode 57 may be polygonal, and the seventh connection electrode 57 is connected to the second electrode plate 72 through the first via hole V1.
  • the seventh connection electrode 57 may serve as a fourth node N4 of the pixel driving circuit, and is configured to be connected to the sixth connection electrode 56 through an anode connection electrode formed subsequently.
  • the shape of the eighth connection electrode 58 can be a strip shape with the main part extending along the first direction X.
  • the middle part of the eighth connection electrode 58 is connected to the first area of the first active layer through the twelfth via hole V12, and the two ends of the eighth connection electrode 58 are respectively connected to the first initial sub-lines 41 located on both sides of the first area of the first active layer through the fourteenth via hole V14 and the fifteenth via hole V15.
  • connection between adjacent first initial sub-lines 41 is realized to form a first initial signal line
  • connection between the first initial signal line and the first electrode of the first transistor T1 is realized, so that the first initial voltage transmitted by the first initial signal line is written into the first electrode of the first transistor T1.
  • the shape of the ninth connection electrode 59 can be a strip shape with the main part extending along the first direction X.
  • the middle part of the ninth connection electrode 59 is connected to the first area of the seventh active layer through the thirteenth via hole V13, and the two ends of the ninth connection electrode 59 are respectively connected to the second initial sub-lines 42 located on both sides of the first area of the seventh active layer through the sixteenth via hole V16 and the seventeenth via hole V17.
  • the connection between adjacent second initial sub-lines 42 is realized to form a second initial signal line.
  • the connection between the second initial signal line and the first electrode of the seventh transistor T7 is realized, so that the second initial voltage transmitted by the second initial signal line is written into the first electrode of the seventh transistor T7.
  • the shape of the tenth connecting electrode 60 can be a strip shape with the main part extending along the second direction Y, the first end of the tenth connecting electrode 60 is connected to the first connecting block 81 of the first electrode plate 71 through the eighteenth via hole V18, and the second end of the tenth connecting electrode 60 is connected to the second connecting block 82 of the third electrode plate 73 through the nineteenth via hole V19, thereby realizing the mutual connection between the first electrode plate 71 and the third electrode plate 73, so that the first electrode plate 71 and the third electrode plate 73 have the same electric potential.
  • the first connection electrode 51 serves as the first node N1 of the pixel driving circuit, and thus the first electrode plate 71 and the third electrode plate 73 have the potential of the first node N1 of the pixel driving circuit.
  • the second electrode plate 72 is connected to the seventh connection electrode 57 through the via hole, and the seventh connection electrode 57 serves as the fourth node N4 of the pixel driving circuit, the second electrode plate 72 has the potential of the fourth node N4 of the pixel driving circuit.
  • the first electrode plate 71, the second electrode plate 72 and the third electrode plate 73 constitute a storage capacitor of a parallel structure
  • the first electrode plate 71 having the potential of the first node N1 and the second electrode plate 72 having the potential of the fourth node N4 constitute a first storage capacitor
  • the third electrode plate 73 having the potential of the first node N1 and the second electrode plate 72 having the potential of the fourth node N4 constitute a second storage capacitor
  • the first storage capacitor and the second storage capacitor are in a parallel structure.
  • the third conductive layer may adopt a multilayer composite structure, such as Ti (titanium) / Al (aluminum) / Ti (titanium), etc., and the thickness of the third conductive layer may be about 600nm to 700nm.
  • the thickness of the two Ti layers in the third conductive layer may be about 50nm respectively
  • the thickness of the Al layer in the third conductive layer may be about 550nm
  • the total thickness of the third conductive layer may be about 650nm.
  • Forming a first planar layer pattern may include: first depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, then coating the first planar film, patterning the first planar film and the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer pattern and a first planar layer disposed on the fifth insulating layer, wherein a plurality of vias are disposed on the first planar layer, as shown in FIG. 13 .
  • the plurality of via holes on the fifth insulating layer and the first planar layer may include at least a twenty-first via hole V21 , a twenty-second via hole V22 , a twenty-third via hole V23 , a twenty-fourth via hole V24 , and a twenty-fifth via hole V25 .
  • the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the second connecting electrode 52 on the substrate, the first flat layer and the fifth insulating layer in the twenty-first via hole V21 are etched away to expose the surface of the second connecting electrode 52, and the twenty-first via hole V21 is configured to connect a subsequently formed first power line to the second connecting electrode 52 through the via hole.
  • the orthographic projection of the twenty-second via hole V22 on the substrate is within the range of the orthographic projection of the fourth connecting electrode 54 on the substrate, the first flat layer and the fifth insulating layer in the twenty-second via hole V22 are etched away to expose the surface of the fourth connecting electrode 54, and the twenty-second via hole V22 is configured to connect a subsequently formed data signal line to the fourth connecting electrode 54 through the via hole.
  • the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the sixth connecting electrode 56 on the substrate, the first flat layer and the fifth insulating layer in the twenty-third via hole V23 are etched away to expose the surface of the sixth connecting electrode 56, and the twenty-third via hole V23 is configured to connect a subsequently formed anode connecting electrode to the sixth connecting electrode 56 through the via hole.
  • the orthographic projection of the twenty-fourth via hole V24 on the substrate is within the range of the orthographic projection of the seventh connecting electrode 57 on the substrate, the first flat layer and the fifth insulating layer in the twenty-fourth via hole V24 are etched away to expose the surface of the seventh connecting electrode 57, and the twenty-fourth via hole V24 is configured to connect a subsequently formed anode connecting electrode to the seventh connecting electrode 57 through the via hole.
  • the orthographic projection of the twenty-fifth via hole V25 on the substrate is within the range of the orthographic projection of the ninth connecting electrode 59 on the substrate, the first flat layer and the fifth insulating layer in the twenty-fifth via hole V25 are etched away to expose the surface of the ninth connecting electrode 59, and the twenty-fifth via hole V25 is configured to connect a subsequently formed initial connecting line to the ninth connecting electrode 59 through the via hole.
  • the fifth insulating layer may be referred to as a passivation (PVX) layer, and the material of the fifth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.
  • the fifth insulating layer may be SiO/SiNx, and the thickness of the fifth insulating layer may be about 200nm to 400nm.
  • the thickness of SiO in the fifth insulating layer may be about 200nm
  • the thickness of SiNx in the fifth insulating layer may be about 100nm
  • the total thickness of the fifth insulating layer may be about 300nm.
  • the first planar layer may be made of an organic material, such as resin or polyimide, and the thickness of the first planar layer may be about 1000 nm to 2000 nm.
  • the thickness of the first planar layer may be about 1500 nm.
  • forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the first flat layer, as shown in FIGS. 14A and 14B , where FIG. 14B is a schematic plan view of the fourth conductive layer in FIG. 14A .
  • the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the fourth conductive layer may include at least an anode connection electrode 61 , a first power supply line 62 , a data signal line 63 , and an initial connection line 64 .
  • the shape of the anode connection electrode 61 can be a zigzag shape with the main part extending along the second direction Y, the first end of the anode connection electrode 61 is connected to the sixth connection electrode 56 through the twenty-third via hole V23, and the second end of the anode connection electrode 61 is connected to the seventh connection electrode 57 through the twenty-fourth via hole V24.
  • the sixth connection electrode 56 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the via hole, and the seventh connection electrode 57 is connected to the second electrode plate 72 through the via hole, the second electrode plate 72, the second electrode of the sixth transistor T6, and the second electrode of the seventh transistor T7 have the same potential, that is, the potential of the fourth node N4 in the pixel driving circuit, and the anode connection electrode 61 can be called a fourth node connection line.
  • the anode connection electrode 61 is configured to be connected to the anode formed subsequently, so that the pixel driving circuit can output a driving current to the light-emitting device.
  • the orthographic projection of the anode connection electrode 61 on the substrate may at least partially overlap with the orthographic projection of the second scan signal line 32 on the substrate, and the orthographic projection of the anode connection electrode 61 on the substrate may at least partially overlap with the orthographic projection of the light emitting control line 35 on the substrate.
  • the shape of the first power line 62 may be a straight line or a folded line with a main portion extending along the second direction Y, and the first power line 62 is connected to the second connection electrode 52 through the twenty-first via hole V21. Since the second connection electrode 52 is connected to the first region of the fifth active layer through the via hole, the first power line 62 can write the first power signal to the first electrode of the fifth transistor T5.
  • the positive projection of the first power line 62 on the substrate can at least partially overlap with the positive projections of the first connection electrode 51 and the third connection electrode 53 on the substrate, respectively, so that the first power line 62 can serve as a shielding electrode, which can effectively shield the influence of data voltage jumps on key nodes in the pixel driving circuit, avoid the data voltage jumps affecting the potential of the key nodes of the pixel driving circuit, and improve the display effect.
  • the data signal line 63 may be in the shape of a straight line with a main portion extending along the second direction Y, and the data signal line 63 is connected to the fourth connection electrode 54 through the twenty-second via hole V22. Since the fourth connection electrode 54 is connected to the first region of the fourth active layer through the via hole, the data signal line 63 is connected to the first electrode of the fourth transistor T4, and the data signal line 63 can write a data signal to the first electrode of the fourth transistor T4.
  • the shape of the initial connection line 64 can be a straight line or a folded line with the main part extending along the second direction Y, and the initial connection line 64 is connected to the ninth connection electrode 59 through the twenty-fifth via hole V25.
  • the initial connection line 64 is connected to the ninth connection electrode 59, so that the second initial signal line extending along the first direction X and the initial connection line 64 extending along the second direction Y constitute an initial connection line of a network connection structure in the display area, which can minimize the resistance of the initial signal line, reduce the voltage drop of the initial voltage, and effectively improve the uniformity of the initial voltage in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.
  • the initial connection line 64, the ninth connection electrode 59 and the second initial sub-line 42 are respectively arranged in different conductive layers, the initial connection line 64 is connected to the ninth connection electrode 59 through a via hole, and the ninth connection electrode 59 is connected to the second initial sub-line 42 through a via hole.
  • the fourth conductive layer may adopt a multi-layer composite structure, such as Ti/Al/Ti, etc., and the thickness of the third conductive layer may be about 600nm to 700nm.
  • the thicknesses of the two Ti layers in the fourth conductive layer may be about 50nm and 30nm respectively
  • the thickness of the Al layer in the third conductive layer may be about 550nm
  • the total thickness of the third conductive layer may be about 630nm.
  • FIG14C is a schematic diagram of a display substrate of the present disclosure after another fourth conductive layer pattern is formed
  • FIG14D is a plan schematic diagram of the fourth conductive layer in FIG14C.
  • the structures of the anode connection electrode 61, the first power line 62, the data signal line 63, and the initial connection line 64 in the fourth conductive layer of this embodiment are substantially the same as those shown in FIG14A and FIG14B, except that a first bump 61-1 is provided on the anode connection electrode 61.
  • the first bump 61 - 1 may be polygonal in shape, may be disposed on one side of the anode connection electrode 61 in the first direction X and/or on a side in the opposite direction of the first direction X, and may be connected to the anode connection electrode 61 .
  • the positive projection of the first bump 61-1 on the substrate can at least partially overlap with the positive projection of the light-emitting control line 35 on the substrate, and the first bump 61-1 is configured to increase the first coupling capacitance between the anode connecting electrode 61 and the light-emitting control line 35.
  • the high-level conduction signal can pull up the potential of the fourth node N4 in the pixel driving circuit through the first coupling capacitor, which is conducive to bright state display.
  • FIG14E is a schematic diagram of a display substrate of the present disclosure after forming another fourth conductive layer pattern
  • FIG14F is a plan schematic diagram of the fourth conductive layer in FIG14E.
  • the structures of the anode connection electrode 61, the first power line 62, the data signal line 63 and the initial connection line 64 in the fourth conductive layer of this embodiment are substantially the same as those shown in FIG14A and FIG14B, except that a second bump 61-2 is provided on the anode connection electrode 61.
  • the second bump 61 - 2 may be polygonal in shape, may be disposed on one side of the anode connection electrode 61 in the first direction X and/or on a side in the opposite direction of the first direction X, and may be connected to the anode connection electrode 61 .
  • the positive projection of the second bump 61-2 on the substrate can at least partially overlap with the positive projection of the second scanning signal line 32 on the substrate, and the second bump 61-2 is configured to increase the second coupling capacitance between the anode connecting electrode 61 and the second scanning signal line 32.
  • the low-level shutdown signal can pull down the potential of the fourth node N4 in the pixel driving circuit through the second coupling capacitance, which is conducive to dark state display.
  • the schemes of Figures 14C and 14E can be combined, that is, a first bump 61-1 and a second bump 61-2 are respectively provided on the anode connecting electrode 61, and the orthographic projection of the first bump 61-1 on the substrate can at least partially overlap with the orthographic projection of the light-emitting control line 35 on the substrate, and the orthographic projection of the second bump 61-2 on the substrate can at least partially overlap with the orthographic projection of the second scanning signal line 32 on the substrate.
  • the orthographic projections of the anode connecting electrode 61 and the first bump 61-1 on the substrate and the orthographic projection of the light emitting control line 35 on the substrate may have a first overlapping area
  • the orthographic projections of the anode connecting electrode 61 and the second bump 61-2 on the substrate and the orthographic projection of the second scanning signal line 32 on the substrate may have a second overlapping area
  • the first overlapping area and the second overlapping area may be substantially equal, and the influence of the first coupling capacitor and the second coupling capacitor may be adjusted to a certain extent.
  • FIG14G is a schematic diagram of a display substrate of the present disclosure after forming another fourth conductive layer pattern
  • FIG14H is a plan schematic diagram of the fourth conductive layer in FIG14G.
  • the structure of the anode connection electrode 61, the data signal line 63 and the initial connection line 64 in the fourth conductive layer of this embodiment is substantially the same as the structure shown in FIG14A and FIG14B, except that the first power line 62 is provided with a avoidance structure 62-1.
  • the avoidance structure 62 - 1 may be located in the region where the third connection electrode 53 is located.
  • the avoidance structure 62 - 1 may be in a “C” shape so that the first power line 62 is bent in a direction away from the anode connection electrode 61 .
  • the avoidance structure 62-1 can reduce the overlapping area between the first power line 62 and the third connection electrode 53, thereby reducing the parasitic capacitance of the second node N2 in the pixel driving circuit.
  • the avoidance structure 62-1 causes the first power line 62 to bend in a direction away from the anode connecting electrode 61, a larger space can be left between the first power line 62 and the anode connecting electrode 61, which is beneficial for setting the first bump 61-1 and/or the second bump 61-2, and is beneficial for the design of the coupling capacitor of the fourth node N4 in the pixel driving circuit.
  • FIG. 14A , FIG. 14C , FIG. 14E , and FIG. 14G may be arbitrarily combined according to actual conditions, and the present disclosure is not limited thereto.
  • a second flat film is coated on the substrate on which the aforementioned pattern is formed, and the second flat film is patterned using a patterning process to form a second flat layer covering the fourth conductive layer pattern, and an anode via is provided on the second flat layer, and the orthographic projection of the anode via on the substrate is within the range of the orthographic projection of the anode connecting electrode 61 on the substrate, and the anode via is configured to connect a subsequently formed anode to the anode connecting electrode 61 through the via.
  • the second planar layer may be made of an organic material, such as resin or polyimide, and the thickness of the second planar layer may be about 1000 nm to 2000 nm.
  • the thickness of the second planar layer may be about 1500 nm.
  • the drive circuit layer is prepared on the substrate.
  • the drive circuit layer may include a plurality of circuit units, each of which may include a pixel drive circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a light emitting control line, a first initial signal line and a second initial signal line, a first power line and a data signal line connected to the pixel drive circuit.
  • the drive circuit layer may include a shielding conductive layer, a first insulating layer, a first conductive layer, a second insulating layer, a semiconductor layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a first flat layer, a fourth conductive layer and a second flat layer sequentially arranged on the substrate.
  • the shielding conductive layer may include at least the first plate of the storage capacitor, the first conductive layer may include at least the second plate of the storage capacitor and multiple shielding lines, the semiconductor layer may include at least the active layer of the first transistor to the seventh transistor, the second conductive layer may include at least the third plate of the storage capacitor, multiple scanning signal lines, a light-emitting control line, a first initial sub-line and a second initial sub-line, the third conductive layer may include at least multiple connecting electrodes, and the fourth conductive layer may include at least an anode connecting electrode, a first power line and a data signal line.
  • the substrate may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate may include, but is not limited to, one or more of glass and quartz
  • the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked.
  • the materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, and the first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-si).
  • a light emitting structure layer may be prepared on the driving circuit layer, and a packaging structure layer may be prepared on the light emitting structure layer, which will not be described in detail here.
  • the first plate, the second plate and the third plate of the storage capacitor of the exemplary embodiment of the present disclosure are respectively located in the shielding conductive layer, the first conductive layer and the second conductive layer, the first plate and the second plate form a first storage capacitor, the second plate and the third plate form a second storage capacitor, and the first storage capacitor and the second storage capacitor constitute a storage capacitor in a parallel structure.
  • the capacitor insulating layer between the first plate and the second plate of the present disclosure adopts silicon nitride to ensure the capacitance performance.
  • the bottom gate electrodes of the multiple transistors of the present disclosure are arranged in the first conductive layer, and the top gate electrodes of the multiple transistors are arranged in the second conductive layer, which can effectively ensure the shielding of the oxide transistors and improve the electrical performance of the transistors.
  • the preparation process of the present disclosure can be well compatible with the existing preparation process, the process is simple to implement, easy to implement, high production efficiency, low production cost, and high yield rate.
  • the present disclosure sets the first insulating layer (capacitor insulating layer) of silicon nitride on the side of the semiconductor layer close to the substrate, that is, the capacitor insulating layer between the first electrode plate and the second electrode plate is not located between the semiconductor layer and the third conductive layer, and the semiconductor layer and the first insulating layer are separated by a second insulating layer, so that the penetration of hydrogen in the first insulating layer can be blocked, thereby avoiding the influence of hydrogen on the characteristics of the oxide thin film transistor and improving the characteristic stability of the oxide thin film transistor.
  • FIG15 is a schematic diagram of the planar structure of another display substrate of an exemplary embodiment of the present disclosure, illustrating the structure of a pixel driving circuit in a circuit unit
  • FIG16A is a schematic cross-sectional diagram along the C-C direction in FIG15
  • FIG16B is a schematic cross-sectional diagram along the D-D direction in FIG15
  • FIG16C is an equivalent circuit diagram of the pixel driving circuit shown in FIG15.
  • the display substrate in a direction perpendicular to the display substrate, may include a driving circuit layer disposed on a substrate, a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate, and an encapsulation structure layer disposed on a side of the light emitting structure layer away from the substrate.
  • the driving circuit layer may include circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit includes a pixel driving circuit, and the pixel driving circuit may include a storage capacitor, a first transistor T1 to a seventh transistor T7, and the first transistor T1 to the seventh transistor T7 are oxide transistors.
  • the driving circuit layer may include at least: a shielding conductive layer arranged on the substrate 10, a first insulating layer 91 arranged on the side of the shielding conductive layer away from the substrate, a semiconductor layer arranged on the side of the first insulating layer 91 away from the substrate, a second insulating layer 92 arranged on the side of the semiconductor layer away from the substrate, a first conductive layer arranged on the side of the second insulating layer 92 away from the substrate, a fourth insulating layer 94 arranged on the side of the first conductive layer away from the substrate, a third conductive layer arranged on the side of the fourth insulating layer 94 away from the substrate, a fifth insulating layer 95 and a first planar layer 96 arranged on the side of the third conductive layer away from the substrate, and a fourth conductive layer arranged on the side of the first planar layer 96 away from the substrate.
  • the blocking conductive layer may include at least a blocking electrode 16 and a plurality of blocking lines
  • the semiconductor layer may include at least an active layer of a first transistor T1 to an active layer of a seventh transistor T7
  • the first conductive layer may include at least a plurality of scanning signal lines and a third gate electrode 44
  • the third conductive layer may include at least a fourth plate 74 of a storage capacitor and a plurality of connecting electrodes
  • the fourth conductive layer may include at least an anode connecting electrode 61, a data signal line 63 and a fifth plate 75 of a storage capacitor
  • the orthographic projection of the fourth plate 74 on the substrate at least partially overlaps with the orthographic projection of the fifth plate 75 on the substrate
  • the fourth plate 74 and the fifth plate 75 constitute a storage capacitor.
  • a flat groove 96-1 is provided on the first flat layer 96, and the first flat layer in the flat groove 96-1 is removed to expose the fifth insulating layer 95.
  • the fifth electrode plate 75 may be provided on the fifth insulating layer 95 in the flat groove 96-1, and the orthographic projection of the flat groove 96-1 on the substrate includes the orthographic projections of the fourth electrode plate 74 and the fifth electrode plate 75 on the substrate, so that only the fifth insulating layer is provided between the fourth electrode plate 74 and the fifth electrode plate 75, and the fifth insulating layer 95 serves as a capacitive insulating layer between the fourth electrode plate 74 and the fifth electrode plate 75.
  • the first transistor T1 to the seventh transistor T7 may each include a bottom gate electrode and a top gate electrode, the bottom gate electrode may be disposed in the shielding conductive layer, and the top gate electrode may be disposed in the first conductive layer.
  • the third gate electrode 44 in the first conductive layer may serve as the top gate electrode of the third transistor T3, connected to the first node N1 of the pixel driving circuit
  • the shielding electrode 16 in the shielding conductive layer may serve as the bottom gate electrode of the third transistor T3, shielding the third transistor T3, and connected to the third node N3 of the pixel driving circuit, as shown in FIG16C .
  • the first conductive layer may further include a first initial sub-line 41 and a second initial sub-line 42
  • the plurality of connection electrodes of the third conductive layer may include at least a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, an eighth connection electrode 58, and a ninth connection electrode 59.
  • the connection structure of the second connection electrode 52, the third connection electrode 53, the fourth connection electrode 54, the sixth connection electrode 56, the eighth connection electrode 58, and the ninth connection electrode 59 of this embodiment is substantially the same as that of the aforementioned embodiment.
  • the first connection electrode 51 can be used as a first node electrode (N1 node electrode) of the pixel driving circuit, the first end of the first connection electrode 51 is connected to the fourth electrode plate 74, and the second end of the first connection electrode 51 is connected to the second region of the first active layer (also the first region of the second active layer) through a via hole. Since the fourth electrode plate 74 is connected to the third gate electrode 44 through the via hole, the second electrode of the first transistor T1, the first electrode of the second transistor T2, the third gate electrode 44 (the top gate electrode of the third transistor T3) and the fourth electrode plate 74 of the storage capacitor have the same potential.
  • the fifth connection electrode 55 can be used as a third node electrode (N3 node electrode) of the pixel driving circuit.
  • the first end of the fifth connection electrode 55 is connected to the first region of the sixth active layer through a via hole
  • the second end of the fifth connection electrode 55 is connected to the shielding electrode 16 through a via hole
  • the middle of the fifth connection electrode 55 is connected to the second region of the fourth active layer (also the second region of the third active layer) through a via hole, thereby achieving the second electrode of the third transistor T3, the second electrode of the fourth transistor T4, the first electrode of the sixth transistor T6 and the shielding electrode 16 (the bottom gate electrode of the third transistor T3) have the same potential.
  • the anode connection electrode 61 can serve as the fourth node electrode (N4 node electrode) of the pixel driving circuit, the first end of the anode connection electrode 61 is connected to the sixth connection electrode 56 through a via, and the second end of the anode connection electrode 61 is connected to the fifth electrode plate 75, thereby achieving the same potential for the second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7 and the fifth electrode plate 75 of the storage capacitor.
  • the preparation process of the display substrate of the present exemplary embodiment may include the following operations.
  • Forming a blocking conductive layer pattern may include: depositing a blocking film on a substrate, patterning the blocking film through a patterning process, and forming a blocking conductive layer pattern on the substrate, as shown in FIG. 17 .
  • the shielding conductive layer pattern may include at least: a first shielding line 11, a second shielding line 12, a third shielding line 13, a fourth shielding line 14, a fifth shielding line 15 and a shielding electrode 16, and the structure of the first shielding line 11 to the fifth shielding line 15 is basically the same as the aforementioned embodiment.
  • the shielding electrode 16 may be in a rectangular shape, and the shielding electrode 16 is configured to shield the third transistor T3 and simultaneously serve as a bottom gate electrode of the third transistor T3 .
  • a third connection block 83 is further connected to one side of the shielding electrode 16 in the first direction X, and the third connection block 83 is configured to be connected to a fifth connection electrode formed subsequently.
  • the material and thickness of the blocking conductive layer may be substantially the same as those of the aforementioned embodiment.
  • Forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process to form a first insulating layer covering the shielding conductive layer, and a semiconductor layer pattern disposed on the first insulating layer, as shown in FIG. 18 .
  • the semiconductor layer pattern may include at least a first active layer 21, a second active layer 22, a third active layer 23, a fourth active layer 24, a fifth active layer 25, a sixth active layer 26 and a seventh active layer 27, and the structures of the first to seventh active layers 21 to 27 may be substantially the same as those in the aforementioned embodiments, and the orthographic projection of the third active layer 23 on the substrate at least partially overlaps with the orthographic projection of the shielding electrode 16 on the substrate.
  • the conductor layer may be made of indium gallium zinc oxide (IGZO) with high electron mobility
  • the material of the first insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.
  • the thickness of the semiconductor layer and the first insulating layer may be substantially the same as in the aforementioned embodiment.
  • Forming a first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG. 19 .
  • the first conductive layer pattern includes at least: a first scan signal line 31, a second scan signal line 32, a third scan signal line 33, a fourth scan signal line 34, a light-emitting control line 35, a first initial sub-line 41, a second initial sub-line 42 and a third gate electrode 44, and the structures of the first scan signal line 31 to the fourth scan signal line 34, the light-emitting control line 35, the first initial sub-line 41 and the second initial sub-line 42 can be substantially the same as those in the aforementioned embodiments.
  • the outline of the third gate electrode 44 may be rectangular, the corners of the rectangle may be chamfered, the orthographic projection of the third gate electrode 44 on the substrate at least partially overlaps with the orthographic projection of the third active layer 23 on the substrate, and the third gate electrode 44 is configured to serve as the top gate electrode of the third transistor T3.
  • materials and thicknesses of the second insulating layer and the first conductive layer may be substantially the same as those of the previous embodiment.
  • Forming a fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the first conductive layer, wherein a plurality of vias are disposed on the fourth insulating layer, as shown in FIG. 20 .
  • the plurality of vias include at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16 and a seventeenth via V17, and the structures of the second via V2 to the ninth via V9 and the twelfth via V12 to the seventeenth via V17 may be substantially the same as those of the aforementioned embodiments.
  • the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the third gate electrode 44 on the substrate, the fourth insulating layer in the first via hole V1 is etched away to expose the surface of the third gate electrode 44, and the first via hole V1 is configured to connect the subsequently formed fourth electrode to the third gate electrode 44 through the via hole.
  • the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the third connecting block 83 of the shielding electrode 16 on the substrate, the fourth insulating layer, the second insulating layer and the first insulating layer in the tenth via hole V10 are etched away to expose the surface of the third connecting block 83, and the tenth via hole V10 is configured to connect the subsequently formed fifth connecting electrode 55 to the shielding electrode 16 through the via hole.
  • the material and thickness of the fourth insulating layer may be substantially the same as those of the previous embodiment.
  • Forming a third conductive layer pattern may include: depositing a third conductive film on the substrate having the aforementioned pattern, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the fourth insulating layer, as shown in FIG. 21 .
  • the third conductive layer includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, an eighth connection electrode 58, a ninth connection electrode 59 and a fourth plate 74 of the storage capacitor, and the structures of the second connection electrodes 52 to the sixth connection electrodes 56 and the eighth connection electrodes 58 to the ninth connection electrodes 59 may be substantially the same as those in the aforementioned embodiments.
  • the shape of the fourth electrode plate 74 can be rectangular, the orthographic projection of the fourth electrode plate 74 on the substrate at least partially overlaps with the orthographic projection of the third gate electrode 44 on the substrate, the fourth electrode plate 74 is connected to the third gate electrode 44 through the first via V1, and the fourth electrode plate 74 can serve as a plate of the storage capacitor.
  • the ratio of the orthogonal projection area of the fourth electrode plate 74 on the substrate to the orthogonal projection area of the third gate electrode 44 on the substrate may be greater than 50%.
  • the ratio of the orthogonal projection area of the fourth electrode plate 74 on the substrate to the orthogonal projection area of the third gate electrode 44 on the substrate may be about 60%, or about 70%, or about 80%, or about 90%.
  • the fourth electrode 74 may include at least: an overlapping area where the orthographic projection on the substrate overlaps with the orthographic projection of the third gate electrode 44 on the substrate, and a non-overlapping area where the orthographic projection on the substrate does not overlap with the orthographic projection of the third gate electrode 44 on the substrate, and the width of the overlapping area may be greater than the width of the non-overlapping area, and the width may be the dimension of the fourth electrode 74 in the first direction X.
  • the first connection electrode 51 may serve as a first node electrode (N1 node electrode) of the pixel driving circuit.
  • the first connection electrode 51 may be in the shape of a strip extending along the first direction X, the first end of the first connection electrode 51 is directly connected to the fourth electrode plate 74, and the second end of the first connection electrode 51 is connected to the second region of the first active layer (also the first region of the second active layer) through the second via hole V2. Since the fourth electrode plate 74 is connected to the third gate electrode 44 through the via hole, the second electrode of the first transistor T1, the first electrode of the second transistor T2, the third gate electrode 44 (the top gate electrode of the third transistor T3), and the fourth electrode plate 74 of the storage capacitor have the same potential.
  • the first connection electrode 51 and the fourth electrode plate 74 of the storage capacitor may be an integral structure connected to each other.
  • the fifth connection electrode 55 can be used as the third node electrode (N3 node electrode) of the pixel driving circuit.
  • the shape of the fifth connection electrode 55 can be a zigzag shape in which the main part extends along the second direction Y.
  • the first end of the fifth connection electrode 55 is connected to the first area of the sixth active layer through the eighth via hole V8, and the second end of the fifth connection electrode 55 is connected to the third connection block 83 of the shielding electrode 16 through the tenth via hole V10.
  • the middle part of the fifth connection electrode 55 located between the first end and the second end is connected to the second area of the fourth active layer (also the second area of the third active layer) through the seventh via hole V7, thereby achieving the second electrode of the third transistor T3, the second electrode of the fourth transistor T4, the first electrode of the sixth transistor T6 and the shielding electrode 16 (the bottom gate electrode of the third transistor T3) have the same potential.
  • the shielding electrode 16 serves as the bottom gate electrode of the third transistor T3 and has the potential of the third node N3 of the pixel driving circuit
  • the third gate electrode 44 serves as the top gate electrode of the third transistor T3 and has the potential of the first node N1 of the pixel driving circuit
  • the positive projection of the third gate electrode 44 on the substrate at least partially overlaps with the positive projection of the shielding electrode 16 on the substrate.
  • the material and thickness of the third conductive layer may be substantially the same as those of the previous embodiment.
  • Forming a first planar layer pattern may include: first depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, then coating the first planar film, patterning the first planar film and the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer pattern and a first planar layer disposed on the fifth insulating layer, wherein the first planar layer is provided with a planar groove and a plurality of vias, as shown in FIG. 22 .
  • the plurality of via holes include at least a twenty-first via hole V21 , a twenty-second via hole V22 , a twenty-third via hole V23 , and a twenty-fifth via hole V25 , and the structures of the via holes may be substantially the same as those in the aforementioned embodiment.
  • the flat groove 96-1 can be opened in the area where the fourth electrode plate 74 is located, the first flat layer in the flat groove 96-1 is removed, exposing the fifth insulating layer covering the fourth electrode plate 74, and the orthographic projection of the flat groove 96-1 on the substrate includes the orthographic projection of the fourth electrode plate 74 on the substrate.
  • the flat groove 96-1 is configured to accommodate the fifth electrode plate formed subsequently, so that only the fifth insulating layer is provided between the fourth electrode plate 74 and the fifth electrode plate to increase the capacity of the storage capacitor.
  • the fifth insulating layer is a capacitive insulating layer disposed between the fourth electrode plate and the fifth electrode plate, which may be referred to as a passivation (PVX) layer.
  • the material of the fifth insulating layer may be SiNx, and the thickness of the fifth insulating layer may be approximately 200 nm to 300 nm. For example, the thickness of the fifth insulating layer may be approximately 250 nm.
  • the material and thickness of the first planarization layer may be substantially the same as those of the aforementioned embodiment.
  • Forming a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate having the aforementioned pattern, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the first planar layer, as shown in FIG. 23 .
  • the fourth conductive layer includes at least: an anode connection electrode 61 , a first power line 62 , a data signal line 63 , an initial connection line 64 , and a fifth plate 75 of a storage capacitor.
  • the shape of the anode connection electrode 61 can be a zigzag shape with the main part extending along the second direction Y, the first end of the anode connection electrode 61 is connected to the sixth connection electrode 56 through the twenty-third via hole V23, and the second end of the anode connection electrode 61 is connected to the fifth electrode plate 75.
  • the anode connection electrode 61 may be provided with a first bump, or may be provided with a second bump, or may be provided with a first bump and a second bump, which is not limited in the present disclosure.
  • the fifth electrode plate 75 can be rectangular in shape and is disposed in the flat groove 96-1.
  • the orthographic projection of the fifth electrode plate 75 on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate 74 on the substrate.
  • the fifth electrode plate 75 can serve as another electrode plate of the storage capacitor.
  • the fourth electrode plate 74 and the fifth electrode plate 75 constitute the storage capacitor of the pixel driving circuit.
  • the orthographic projection of the fifth electrode plate 75 on the substrate at least partially overlaps the orthographic projection of the third gate electrode 44 on the substrate.
  • the ratio of the orthographic projection area of the fifth electrode plate 75 on the substrate to the orthographic projection area of the third gate electrode 44 on the substrate may be greater than 50%.
  • the ratio of the orthographic projection area of the fifth electrode plate 75 on the substrate to the orthographic projection area of the third gate electrode 44 on the substrate may be about 60%, or about 70%, or about 80%, or about 90%.
  • the fifth electrode 75 may include at least: an overlapping area where the orthographic projection on the substrate overlaps with the orthographic projection of the third gate electrode 44 on the substrate, and a non-overlapping area where the orthographic projection on the substrate does not overlap with the orthographic projection of the third gate electrode 44 on the substrate, and the width of the overlapping area may be greater than the width of the non-overlapping area, and the width may be the dimension of the fifth electrode 75 in the first direction X.
  • the anode connection electrode 61 and the fifth electrode plate 75 may be an integral structure connected to each other. Since the sixth connection electrode 56 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through a via hole, the fifth electrode plate 75, the second electrode of the sixth transistor T6, and the second electrode of the seventh transistor T7 have the same potential, that is, the potential of the fourth node N4 of the pixel driving circuit.
  • the structures of the first power line 62, the data signal line 63 and the initial connection line 64 may be substantially the same as those in the aforementioned embodiment, or, an avoidance structure may be provided on the first power line 62 and/or the initial connection line 64, the avoidance structure causing the first power line 62 and/or the initial connection line 64 to bend in a direction away from the fifth electrode plate 75, thereby leaving a corresponding space for providing the fifth electrode plate 75.
  • the material and thickness of the fourth conductive layer may be substantially the same as those of the previous embodiment.
  • a second flat film is coated on the substrate on which the aforementioned pattern is formed, and the second flat film is patterned using a patterning process to form a second flat layer covering the fourth conductive layer pattern, wherein an anode via hole is provided on the second flat layer, and the orthographic projection of the anode via hole on the substrate is located within the range of the orthographic projection of the anode connection electrode on the substrate, and the anode via hole is configured to connect the subsequently formed anode to the anode connection electrode through the via hole.
  • the material and thickness of the second flat layer may be substantially the same as those in the aforementioned embodiment.
  • the drive circuit layer is prepared on the substrate.
  • the drive circuit layer may include a plurality of circuit units, each of which may include a pixel drive circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a light emitting control line, a first initial signal line and a second initial signal line, a first power line and a data signal line connected to the pixel drive circuit.
  • the drive circuit layer may include a shielding conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a first flat layer, a fourth conductive layer and a second flat layer sequentially arranged on the substrate.
  • the blocking conductive layer may include at least a blocking electrode and multiple blocking lines
  • the semiconductor layer may include at least an active layer of the first transistor to the seventh transistor
  • the first conductive layer may include at least multiple scanning signal lines and a third gate electrode
  • the third conductive layer may include at least a fourth plate of the storage capacitor and multiple connecting electrodes
  • the fourth conductive layer may include at least a fifth plate of the storage capacitor, an anode connecting electrode, a first power line and a data signal line
  • the orthographic projection of the fourth plate on the substrate at least partially overlaps with the orthographic projection of the fifth plate on the substrate
  • the fourth plate and the fifth plate constitute a storage capacitor.
  • the fourth plate and the fifth plate of the storage capacitor of the exemplary embodiment of the present disclosure are respectively arranged in the third conductive layer and the fourth conductive layer, and the capacitor insulating layer between the fourth plate and the fifth plate adopts silicon nitride, which can ensure the capacitor performance.
  • the present disclosure arranges the fifth insulating layer (capacitor insulating layer) using silicon nitride on the side of the third conductive layer away from the substrate, that is, the capacitor insulating layer between the fourth plate and the fifth plate is not located between the semiconductor layer and the third conductive layer, so that the penetration of hydrogen elements in the fifth insulating layer can be avoided, thereby avoiding the influence of hydrogen elements on the characteristics of the oxide thin film transistor, and improving the characteristic stability of the oxide thin film transistor.
  • the bottom gate electrodes of multiple transistors of the present disclosure are arranged in the shielding conductive layer, and the top gate electrodes of multiple transistors are arranged in the first conductive layer, which can effectively ensure the shielding of the oxide transistor and improve the electrical performance of the transistor.
  • the present disclosure cancels the third insulating layer and the second conductive layer, which not only reduces the one-time patterning process, but also avoids the penetration of hydrogen (H) elements in the third insulating layer using SiNx, thereby avoiding the influence of hydrogen elements on the characteristics of the oxide thin film transistor, and improving the characteristic stability of the oxide thin film transistor.
  • the preparation process disclosed in the present invention is well compatible with the existing preparation process, and the process is simple to realize, easy to implement, has high production efficiency, low production cost and high yield rate.
  • FIG24 is a schematic diagram of a planar structure of another display substrate of an exemplary embodiment of the present disclosure, illustrating the structure of a pixel driving circuit in a circuit unit
  • FIG25A is a schematic cross-sectional diagram along the E-E direction in FIG24
  • FIG25B is a schematic cross-sectional diagram along the F-F direction in FIG24
  • FIG25C is an equivalent circuit diagram of the pixel driving circuit shown in FIG24.
  • the display substrate in a direction perpendicular to the display substrate, may include a driving circuit layer disposed on a substrate, a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate, and an encapsulation structure layer disposed on a side of the light emitting structure layer away from the substrate.
  • the driving circuit layer may include circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit includes a pixel driving circuit, and the pixel driving circuit may include a storage capacitor, a first transistor T1 to a seventh transistor T7, and the first transistor T1 to the seventh transistor T7 are oxide transistors.
  • the driving circuit layer may include at least: a shielding conductive layer arranged on the substrate 10, a first insulating layer 91 arranged on the side of the shielding conductive layer away from the substrate, a semiconductor layer arranged on the side of the first insulating layer 91 away from the substrate, a second insulating layer 92 arranged on the side of the semiconductor layer away from the substrate, a first conductive layer arranged on the side of the second insulating layer 92 away from the substrate, a third insulating layer 93 arranged on the side of the first conductive layer away from the substrate, a second conductive layer arranged on the side of the third insulating layer 93 away from the substrate, a fourth insulating layer 94 arranged on the side of the second conductive layer away from the substrate, and a third conductive layer arranged on the side of the fourth insulating layer 94 away from the substrate.
  • the blocking conductive layer may include at least a blocking electrode 16 and a plurality of blocking lines
  • the semiconductor layer may include at least an active layer of a first transistor to an active layer of a seventh transistor
  • the first conductive layer may include at least a seventh electrode 77 of a storage capacitor and a plurality of scanning signal lines
  • the second conductive layer may include at least an eighth electrode 78 of a storage capacitor
  • the third conductive layer may include at least a plurality of connecting electrodes.
  • the seventh plate 77 of the storage capacitor can be set in the first conductive layer, and the eighth plate 78 of the storage capacitor can be set in the second conductive layer.
  • the orthographic projection of the seventh plate 77 on the substrate at least partially overlaps with the orthographic projection of the eighth plate 78 on the substrate, and the third insulating layer 93 is a capacitor insulating layer set between the seventh plate 77 and the eighth plate 78.
  • the first transistor T1 to the seventh transistor T7 may each include a bottom gate electrode and a top gate electrode, the bottom gate electrode may be disposed in the shielding conductive layer, and the top gate electrode may be disposed in the first conductive layer.
  • the seventh electrode plate 77 in the first conductive layer may serve as the top gate electrode of the third transistor T3, that is, the top gate electrode and the seventh electrode plate 77 of the third transistor T3 are an integral structure connected to each other.
  • the shielding electrode 16 in the shielding conductive layer may serve as the bottom gate electrode of the third transistor T3 to shield the third transistor T3, and is connected to the third node N3 of the pixel driving circuit, as shown in FIG25C.
  • the third conductive layer may include at least a first connection electrode 51 , a second connection electrode 52 , a third connection electrode 53 , a fourth connection electrode 54 , a fifth connection electrode 55 , a sixth connection electrode 56 , and a seventh connection electrode 57 .
  • the first connection electrode 51 can serve as the first node electrode (N1 node electrode) of the pixel driving circuit, and the first end of the first connection electrode 51 is connected to the seventh electrode plate 77 through a via, and the second end of the first connection electrode 51 is connected to the second region of the first active layer (also the first region of the second active layer) through a via, thereby achieving the same potential for the seventh electrode plate 77 of the storage capacitor, the second electrode of the first transistor T1, and the first electrode of the second transistor T2.
  • the second connection electrode 52 may be connected to the first region of the fifth active layer through a via hole. Since the second connection electrode 52 is connected to the first power line, the first power line writes the first power voltage into the first electrode of the fifth transistor T5 through the second connection electrode 52.
  • the third connection electrode 53 can serve as the second node electrode (N2 node electrode) of the pixel driving circuit, and the first end of the third connection electrode 53 is connected to the second region of the second active layer (also the first region of the third active layer) through a via, and the second end of the third connection electrode 53 is connected to the second region of the fifth active layer through a via, thereby achieving the same potential for the second electrode of the second transistor T2, the first electrode of the third transistor T3, and the second electrode of the fifth transistor T5.
  • the fourth connection electrode 54 can serve as a data input electrode of the pixel driving circuit.
  • the fourth connection electrode 54 is connected to the first area of the fourth active layer 24 through a via. Since the fourth connection electrode 54 is connected to the data signal line, the data signal line writes the data signal into the first electrode of the fourth transistor T4 through the fourth connection electrode 54.
  • the fifth connection electrode 55 can serve as the third node electrode (N3 node electrode) of the pixel driving circuit.
  • the fifth connection electrode 55 is connected to the second region of the fourth active layer (also the second region of the third active layer) through a via hole.
  • the fifth connection electrode 55 is connected to the first region of the sixth active layer through a via hole, thereby achieving the same potential for the second electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the first electrode of the sixth transistor T6.
  • the fifth connection electrode 55 is also connected to the shielding electrode 16 through a via hole, thereby achieving connection between the second electrode of the third transistor T3 and the bottom gate electrode of the third transistor T3 .
  • the sixth connection electrode 56 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through a via hole, thereby achieving the second electrodes of the sixth transistor T6 and the seventh transistor T7 to have the same potential.
  • the seventh connecting electrode 57 can serve as the fourth node electrode (N4 node electrode) of the pixel driving circuit.
  • the fifth connecting electrode 55 is connected to the eighth plate 78 through a via, and on the other hand, the fifth connecting electrode 55 is connected to the sixth connecting electrode 56 through an anode connecting electrode, thereby achieving the same potential of the eighth plate 78 of the storage capacitor, the second electrode of the sixth transistor T6, and the second electrode of the seventh transistor T7.
  • the second conductive layer may further include first and second preliminary sub-lines 41 and 42
  • the third conductive layer may further include eighth and ninth connection electrodes 58 and 59 , and the above structures may be substantially the same as the aforementioned embodiments.
  • the preparation process of the display substrate of the present exemplary embodiment may include the following operations.
  • forming a blocking conductive layer pattern may include: depositing a blocking film on a substrate, patterning the blocking film by a patterning process, and forming a blocking conductive layer pattern on the substrate, as shown in FIG. 26 .
  • the shielding conductive layer pattern may include at least: a first shielding line 11, a second shielding line 12, a third shielding line 13, a fourth shielding line 14, a fifth shielding line 15 and a shielding electrode 16, and the structure of the first shielding line 11 to the fifth shielding line 15 is basically the same as the aforementioned embodiment.
  • the shielding electrode 16 may be in an "n" shape and may be located between the first shielding line 11 and the second shielding line 12.
  • the shielding electrode 16 is configured to shield the third transistor T3 to reduce the influence of light on the electrical characteristics of the third transistor T3, and is configured as a bottom gate electrode of the third transistor T3.
  • a third connection block 83 is further connected to one side of the shielding electrode 16 in the first direction X, and the third connection block 83 is configured to be connected to a fifth connection electrode formed subsequently.
  • the material and thickness of the blocking conductive layer may be substantially the same as those of the aforementioned embodiment.
  • forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process to form a first insulating layer covering the shielding conductive layer, and a semiconductor layer pattern disposed on the first insulating layer, as shown in FIG. 27 .
  • the semiconductor layer pattern may include at least a first active layer 21, a second active layer 22, a third active layer 23, a fourth active layer 24, a fifth active layer 25, a sixth active layer 26 and a seventh active layer 27, and the structures of the first to seventh active layers 21 to 27 may be substantially the same as those in the aforementioned embodiments, and the orthographic projection of the third active layer 23 on the substrate at least partially overlaps with the orthographic projection of the shielding electrode 16 on the substrate.
  • the conductor layer may be made of indium gallium zinc oxide (IGZO) with high electron mobility
  • the material of the first insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.
  • the thickness of the semiconductor layer and the first insulating layer may be substantially the same as in the aforementioned embodiment.
  • forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG. 28 .
  • the first conductive layer pattern includes at least: a first scan signal line 31, a second scan signal line 32, a third scan signal line 33, a fourth scan signal line 34, a light-emitting control line 35 and a seventh plate 77 of a storage capacitor, and the structure of the first scan signal line 31 to the fourth scan signal line 34 and the light-emitting control line 35 may be substantially the same as that of the aforementioned embodiment.
  • the shape of the seventh electrode plate 77 may be rectangular, the corners of the rectangle may be chamfered, and the orthographic projection of the seventh electrode plate 77 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate.
  • the seventh electrode plate 77 may simultaneously serve as a plate of the storage capacitor and a top gate electrode of the third transistor T3 (driving transistor).
  • materials and thicknesses of the second insulating layer and the first conductive layer may be substantially the same as those of the previous embodiment.
  • forming the second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG. 29 .
  • the second conductive layer pattern of each circuit unit includes at least: a first initial sub-line 41, a second initial sub-line 42 and an eighth plate 78 of the storage capacitor, and the structures of the first initial sub-line 41 and the second initial sub-line 42 can be substantially the same as the aforementioned embodiment.
  • the outline of the eighth plate 78 can be rectangular, and the corners of the rectangle can be chamfered.
  • the orthographic projection of the eighth plate 78 on the substrate at least partially overlaps with the orthographic projection of the seventh plate 77 on the substrate.
  • the eighth plate 78 can serve as another plate of the storage capacitor, and the seventh plate 77 and the eighth plate 78 constitute the storage capacitor of the pixel driving circuit.
  • an opening 43 is provided on the eighth electrode plate 78.
  • the opening 43 may be rectangular and may be located in the middle of the eighth electrode plate 78, so that the eighth electrode plate 78 forms a ring structure.
  • the opening 43 exposes the third insulating layer covering the seventh electrode plate 77, and the orthographic projection of the seventh electrode plate 77 on the substrate includes the orthographic projection of the opening 43 on the substrate.
  • the opening 43 is configured to accommodate a first via hole formed subsequently, and the first via hole is located in the opening 43 and exposes the seventh electrode plate 77, so that the first connecting electrode formed subsequently is connected to the seventh electrode plate 77.
  • the third insulating layer is a capacitor insulating layer disposed between the seventh plate and the eighth plate, which may be referred to as a second gate insulating (GI2) layer.
  • the material of the third insulating layer may be SiNx, and the thickness of the third insulating layer may be approximately 100 nm to 170 nm.
  • the thickness of the second insulating layer may be approximately 130 nm.
  • the material and thickness of the second conductive layer may be substantially the same as those of the aforementioned embodiment.
  • Forming a fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein a plurality of vias are disposed on the fourth insulating layer, as shown in FIG. 30 .
  • the plurality of vias include at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16 and a seventeenth via V17.
  • the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the opening 43 on the substrate, the fourth insulating layer and the third insulating layer in the first via hole V1 are etched away to expose the surface of the seventh electrode plate 77, and the first via hole V1 is configured to connect a subsequently formed first connecting electrode to the seventh electrode plate 77 through the via hole.
  • the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second area of the first active layer (also the first area of the second active layer) on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the second area of the first active layer, and the second via hole V2 is configured to connect a subsequently formed first connecting electrode to the second area of the first active layer (also the first area of the second active layer) through the via hole.
  • the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of the fifth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the third via hole V3 are etched away to expose the surface of the first area of the fifth active layer, and the third via hole V3 is configured to connect a subsequently formed second connecting electrode to the first area of the fifth active layer through the via hole.
  • the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second region of the fifth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the second region of the fifth active layer, and the fourth via hole V4 is configured to connect a subsequently formed third connecting electrode to the second region of the fifth active layer through the via hole.
  • the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the second area of the second active layer (also the first area of the third active layer) on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the second area of the second active layer, and the fifth via hole V5 is configured to connect a subsequently formed third connecting electrode to the second area of the second area of the second active layer (also the first area of the third active layer) through the via hole.
  • the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first area of the fourth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the first area of the fourth active layer, and the sixth via hole V6 is configured to connect a subsequently formed fourth connecting electrode to the first area of the fourth active layer through the via hole.
  • the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the second area of the fourth active layer (also the second area of the third active layer) on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the second area of the fourth active layer, and the seventh via hole V7 is configured to connect a subsequently formed fifth connecting electrode to the second area of the fourth active layer (also the second area of the third active layer) through the via hole.
  • the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the first region of the sixth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the eighth via hole V8 are etched away to expose the surface of the first region of the sixth active layer, and the eighth via hole V8 is configured to connect a subsequently formed fifth connecting electrode to the first region of the sixth active layer through the via hole.
  • the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the second area of the sixth active layer (also the second area of the seventh active layer) on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the ninth via hole V9 are etched away to expose the surface of the second area of the sixth active layer, and the ninth via hole V9 is configured to connect a subsequently formed sixth connecting electrode to the second area of the sixth active layer (also the second area of the seventh active layer) through the via hole.
  • the orthographic projection of the tenth via hole V10 on the substrate is within the range of the orthographic projection of the blocking electrode 16 on the substrate, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer in the tenth via hole V10 are etched away to expose the surface of the third connecting block 83 of the blocking electrode 16, and the tenth via hole V10 is configured to connect the subsequently formed fifth connecting electrode to the blocking electrode 16 through the via hole.
  • the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the eighth electrode plate 78 on the substrate, the fourth insulating layer in the eleventh via hole V11 is etched away to expose the surface of the eighth electrode plate 78, and the eleventh via hole V11 is configured to connect the subsequently formed seventh connecting electrode to the eighth electrode plate 78 through the via hole.
  • the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the twelfth via hole V12 are etched away to expose the surface of the first region of the first active layer, and the twelfth via hole V12 is configured to connect a subsequently formed eighth connecting electrode to the first region of the first active layer through the via hole.
  • the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the first region of the seventh active layer, and the thirteenth via hole V13 is configured to connect a subsequently formed ninth connecting electrode to the first region of the seventh active layer through the via hole.
  • the orthographic projections of the fourteenth via hole V14 and the fifteenth via hole V15 on the substrate are located within the range of the orthographic projections of the first initial sub-line 41 on the substrate, the fourth insulating layer in the fourteenth via hole V14 and the fifteenth via hole V15 is etched away to expose the surface of the first initial sub-line 41, and the fourteenth via hole V14 and the fifteenth via hole V15 are configured to enable the subsequently formed eighth connecting electrode to connect adjacent first initial sub-lines 41 to each other through the via hole.
  • the orthographic projections of the sixteenth via hole V16 and the seventeenth via hole V17 on the substrate are located within the range of the orthographic projections of the second initial sub-line 42 on the substrate, the fourth insulating layer in the sixteenth via hole V16 and the seventeenth via hole V17 is etched away to expose the surface of the second initial sub-line 42, and the sixteenth via hole V16 and the seventeenth via hole V17 are configured to enable the subsequently formed ninth connecting electrode to connect adjacent second initial sub-lines 42 to each other through the via hole.
  • the material and thickness of the fourth insulating layer may be substantially the same as those of the previous embodiment.
  • Forming a third conductive layer pattern may include: depositing a third conductive film on the substrate having the aforementioned pattern, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the fourth insulating layer, as shown in FIG. 31 .
  • the third conductive layer of each circuit unit includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57, an eighth connection electrode 58 and a ninth connection electrode 59.
  • the shape of the first connection electrode 51 can be a zigzag shape with the main part extending along the second direction Y.
  • the first end of the first connection electrode 51 is connected to the seventh electrode plate 77 through the first via hole V1
  • the second end of the first connection electrode 51 is connected to the second area of the first active layer (also the first area of the second active layer) through the second via hole V2, so that the seventh electrode plate 77, the second electrode of the first transistor T1, and the first electrode of the second transistor T2 have the same potential.
  • the first connection electrode 51 can serve as the first node N1 of the pixel driving circuit.
  • the second connection electrode 52 may be in a polygonal shape and connected to the first region of the fifth active layer through the third via hole V3. In an exemplary embodiment, the second connection electrode 52 is configured to be connected to a first power line formed subsequently.
  • the third connection electrode 53 may be in a strip shape with a main portion extending along the second direction Y, a first end of the third connection electrode 53 is connected to the second region of the fifth active layer through a fourth via hole V4, and a second end of the third connection electrode 53 is connected to the second region of the second active layer through a fifth via hole V5.
  • the third connection electrode 53 may serve as a second node N2 of the pixel driving circuit.
  • the fourth connection electrode 54 may be in the shape of a strip having a main portion extending along the second direction Y, and the fourth connection electrode 54 is connected to the first region of the fourth active layer through a sixth via hole V6.
  • the fourth connection electrode 54 may serve as a first electrode (referred to as a data input electrode) of the fourth transistor T4, and the fourth connection electrode 54 is configured to be connected to a subsequently formed data signal line.
  • the shape of the fifth connection electrode 55 can be a zigzag shape in which the main part extends along the second direction Y, the first end of the fifth connection electrode 55 is connected to the first area of the sixth active layer through the eighth via hole V8, the second end of the fifth connection electrode 55 is connected to the third connection block 83 of the shielding electrode 16 through the tenth via hole V10, the third end of the fifth connection electrode 55 is connected to the second area of the fourth active layer through the seventh via hole V7, and the third end of the fifth connection electrode 55 is located between the first end and the second end.
  • the fifth connection electrode 55 can serve as the third node N3 of the pixel driving circuit.
  • the shape of the sixth connection electrode 56 may be polygonal, and the sixth connection electrode 56 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the ninth via hole V9.
  • the sixth connection electrode 56 may serve as a fourth node N4 of the pixel driving circuit and is configured to be connected to a subsequently formed anode connection electrode.
  • the seventh connection electrode 57 may be polygonal in shape and connected to the eighth electrode plate 78 through the eleventh via hole V11.
  • the seventh connection electrode 57 may serve as a fourth node N4 of the pixel driving circuit and is configured to be connected to a subsequently formed anode connection electrode.
  • the shape of the eighth connection electrode 58 can be a strip shape with the main part extending along the first direction X.
  • the middle part of the eighth connection electrode 58 is connected to the first area of the first active layer through the twelfth via hole V12, and the two ends of the eighth connection electrode 58 are respectively connected to the first initial sub-lines 41 located on both sides of the first area of the first active layer through the fourteenth via hole V14 and the fifteenth via hole V15.
  • connection between adjacent first initial sub-lines 41 is realized to form a first initial signal line
  • connection between the first initial signal line and the first electrode of the first transistor T1 is realized, so that the first initial voltage transmitted by the first initial signal line is written into the first electrode of the first transistor T1.
  • the shape of the ninth connection electrode 59 can be a strip shape with the main part extending along the first direction X.
  • the middle part of the ninth connection electrode 59 is connected to the first area of the seventh active layer through the thirteenth via hole V13, and the two ends of the ninth connection electrode 59 are respectively connected to the second initial sub-lines 42 located on both sides of the first area of the seventh active layer through the sixteenth via hole V16 and the seventeenth via hole V17.
  • the connection between adjacent second initial sub-lines 42 is realized to form a second initial signal line.
  • the connection between the second initial signal line and the first electrode of the seventh transistor T7 is realized, so that the second initial voltage transmitted by the second initial signal line is written into the first electrode of the seventh transistor T7.
  • the material and thickness of the third conductive layer may be substantially the same as those of the previous embodiment.
  • forming the first planar layer pattern may include: first depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, then coating the first planar film, patterning the first planar film and the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer pattern and a first planar layer disposed on the fifth insulating layer, wherein a plurality of vias are disposed on the first planar layer, as shown in FIG. 32 .
  • the plurality of vias in each circuit unit includes at least a twenty-first via V21 , a twenty-second via V22 , a twenty-third via V23 , a twenty-fourth via V24 , and a twenty-fifth via V25 .
  • the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the second connecting electrode 52 on the substrate, the first flat layer and the fifth insulating layer in the twenty-first via hole V21 are etched away to expose the surface of the second connecting electrode 52, and the twenty-first via hole V21 is configured to connect a subsequently formed first power line to the second connecting electrode 52 through the via hole.
  • the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 54 on the substrate, the first flat layer and the fifth insulating layer in the twenty-second via hole V22 are etched away to expose the surface of the fourth connecting electrode 54, and the twenty-second via hole V22 is configured to connect a subsequently formed data signal line to the fourth connecting electrode 54 through the via hole.
  • the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the sixth connecting electrode 56 on the substrate, the first flat layer and the fifth insulating layer in the twenty-third via hole V23 are etched away to expose the surface of the sixth connecting electrode 56, and the twenty-third via hole V23 is configured to connect a subsequently formed anode connecting electrode to the sixth connecting electrode 56 through the via hole.
  • the orthographic projection of the twenty-fourth via hole V24 on the substrate is within the range of the orthographic projection of the seventh connecting electrode 57 on the substrate, the first flat layer and the fifth insulating layer in the twenty-fourth via hole V24 are etched away to expose the surface of the seventh connecting electrode 57, and the twenty-fourth via hole V24 is configured to connect a subsequently formed anode connecting electrode to the seventh connecting electrode 57 through the via hole.
  • the orthographic projection of the twenty-fifth via hole V25 on the substrate is within the range of the orthographic projection of the ninth connecting electrode 59 on the substrate, the first flat layer and the fifth insulating layer in the twenty-fifth via hole V25 are etched away to expose the surface of the ninth connecting electrode 59, and the twenty-fifth via hole V25 is configured to connect a subsequently formed initial connecting line to the ninth connecting electrode 59 through the via hole.
  • the material and thickness of the first planarization layer may be substantially the same as those of the previous embodiment.
  • Forming a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate having the aforementioned pattern, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the first planar layer, as shown in FIG. 33 .
  • the fourth conductive layer of each circuit unit includes at least an anode connection electrode 61 , a first power supply line 62 , a data signal line 63 , and an initial connection line 64 .
  • the shape of the anode connection electrode 61 can be a zigzag shape with the main part extending along the second direction Y, the first end of the anode connection electrode 61 is connected to the sixth connection electrode 56 through the twenty-third via hole V23, and the second end of the anode connection electrode 61 is connected to the seventh connection electrode 57 through the twenty-fourth via hole V24.
  • the sixth connection electrode 56 is connected to the second area of the sixth active layer (also the second area of the seventh active layer) through the via hole, and the seventh connection electrode 57 is connected to the eighth electrode plate 78 through the via hole, the eighth electrode plate 78, the second electrode of the sixth transistor T6, and the second electrode of the seventh transistor T7 have the same potential (the fourth node N4 of the pixel driving circuit).
  • the anode connection electrode 61 is configured to be connected to the anode formed subsequently, so that the pixel driving circuit can output a driving current to the light-emitting device.
  • the anode connection electrode 61 may be provided with a first bump, or may be provided with a second bump, or may be provided with a first bump and a second bump, which is not limited in the present disclosure.
  • the shape of the first power line 62 may be a straight line or a folded line with a main portion extending along the second direction Y, and the first power line 62 is connected to the second connection electrode 52 through the twenty-first via hole V21. Since the second connection electrode 52 is connected to the first region of the fifth active layer through the via hole, the first power line 62 can write the first power signal to the first electrode of the fifth transistor T5.
  • the positive projection of the first power line 62 on the substrate can at least partially overlap with the positive projection of the first connecting electrode 51 on the substrate, so that the first power line 62 can serve as a shielding electrode, which can effectively shield the influence of data voltage jumps on key nodes in the pixel driving circuit, avoid the data voltage jumps affecting the potential of the key nodes of the pixel driving circuit, and improve the display effect.
  • the positive projection of the first power line 62 on the substrate can at least partially overlap with the positive projection of the third connecting electrode 53 on the substrate, so that the first power line 62 can serve as a shielding electrode, which can effectively shield the influence of data voltage jumps on key nodes in the pixel driving circuit, avoid the data voltage jumps affecting the potential of the key nodes of the pixel driving circuit, and improve the display effect.
  • the data signal line 63 may be in the shape of a straight line with a main portion extending along the second direction Y, and the data signal line 63 is connected to the fourth connection electrode 54 through the twenty-second via hole V22. Since the fourth connection electrode 54 is connected to the first region of the fourth active layer through the via hole, the data signal line 63 is connected to the first electrode of the fourth transistor T4, and the data signal line 63 can write a data signal to the first electrode of the fourth transistor T4.
  • the shape of the initial connection line 64 can be a straight line or a folded line with the main part extending along the second direction Y, and the initial connection line 64 is connected to the ninth connection electrode 59 through the twenty-fifth via hole V25.
  • the initial connection line 64 is connected to the ninth connection electrode 59, so that the second initial signal line extending along the first direction X and the initial connection line 64 extending along the second direction Y constitute an initial connection line of a network connection structure in the display area, which can minimize the resistance of the initial signal line, reduce the voltage drop of the initial voltage, and effectively improve the uniformity of the initial voltage in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.
  • the initial connection line 64, the ninth connection electrode 59 and the second initial sub-line 42 are respectively arranged in different conductive layers, the initial connection line 64 is connected to the ninth connection electrode 59 through a via, and the ninth connection electrode 59 is connected to the second initial sub-line 42 through a via.
  • the material and thickness of the fourth conductive layer may be substantially the same as those of the previous embodiment.
  • a second flat film is coated on the substrate on which the aforementioned pattern is formed, and the second flat film is patterned by a patterning process to form a second flat layer covering the fourth conductive layer pattern, wherein an anode via hole is provided on the second flat layer, and the orthographic projection of the anode via hole on the substrate is located within the range of the orthographic projection of the anode connection electrode on the substrate, and the anode via hole is configured to connect the subsequently formed anode to the anode connection electrode through the via hole.
  • the material and thickness of the second flat layer may be substantially the same as those in the aforementioned embodiment.
  • the drive circuit layer is prepared on the substrate.
  • the drive circuit layer may include a plurality of circuit units, each of which may include a pixel drive circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a light emitting control line, a first initial signal line and a second initial signal line, a first power line and a data signal line connected to the pixel drive circuit.
  • the drive circuit layer may include a shielding conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a first flat layer, a fourth conductive layer and a second flat layer sequentially arranged on the substrate.
  • the blocking conductive layer may include at least a blocking electrode and multiple blocking lines
  • the semiconductor layer may include at least the active layer of the first transistor to the seventh transistor
  • the first conductive layer may include at least the first plate of the storage capacitor and multiple scanning signal lines
  • the second conductive layer may include at least the second plate of the storage capacitor
  • the third conductive layer may include at least the first connecting electrode to the ninth connecting electrode
  • the fourth conductive layer may include at least the anode connecting electrode, the first power line and the data signal line.
  • the two plates of the storage capacitor of this exemplary embodiment are respectively located in the first conductive layer and the second conductive layer, and the third insulating layer between the first conductive layer and the second conductive layer adopts silicon nitride, which can ensure the capacitance performance.
  • the bottom gate electrodes of multiple transistors are arranged in the shielding conductive layer, and the top gate electrodes of multiple transistors are arranged in the first conductive layer, which can effectively ensure the shielding of the oxide transistor and improve the electrical performance of the transistor.
  • the preparation process disclosed in the present invention can be well compatible with the existing preparation process, the process is simple to realize, easy to implement, high production efficiency, low production cost, and high yield rate.
  • Fig. 34 is a schematic diagram of a planar structure of another display substrate of an exemplary embodiment of the present disclosure.
  • the main structure of this exemplary embodiment is substantially the same as the main structure shown in Fig. 15, except that the driving circuit layer may further include: a second flat layer 97 disposed on a side of the fourth conductive layer away from the substrate and a fifth conductive layer disposed on a side of the second flat layer 97 away from the substrate.
  • the third conductive layer may include at least a fourth plate 74 of a storage capacitor
  • the fourth conductive layer may include at least a fifth plate 75 of a storage capacitor
  • the fifth conductive layer may include at least a sixth plate 76 of a storage capacitor.
  • the orthographic projection of the fourth plate 74 on the substrate at least partially overlaps with the orthographic projection of the fifth plate 75 on the substrate, the fourth plate 74 and the fifth plate 75 constitute a third storage capacitor
  • the orthographic projection of the sixth plate 76 on the substrate at least partially overlaps with the orthographic projection of the fifth plate 75 on the substrate
  • the fifth plate 75 and the sixth plate 76 constitute a fourth storage capacitor
  • the third storage capacitor and the fourth storage capacitor constitute a storage capacitor in a parallel structure.
  • the fourth electrode 74 can be connected to the third gate electrode 44 through a via
  • the sixth electrode 76 can be connected to the third gate electrode 44 or the fourth electrode 74 through a via, so that the fourth electrode 74 and the sixth electrode 76 have the same potential
  • the fifth electrode 75 can be connected to the anode connection electrode
  • the fourth electrode 74 located in the third conductive layer, the fifth electrode 75 located in the fourth conductive layer, and the sixth electrode 76 located in the fifth conductive layer constitute a storage capacitor in a parallel structure.
  • first planar layer 96 may be provided between the third conductive layer and the fourth conductive layer, or a fifth insulating layer and the first planar layer 96 may be provided, and the driving circuit layer may include the third insulating layer and the second conductive layer, which is not limited in the present disclosure.
  • Fig. 35 is a schematic diagram of a planar structure of another display substrate of an exemplary embodiment of the present disclosure.
  • the main structure of this exemplary embodiment is substantially the same as the main structure shown in Fig. 15, except that the driving circuit layer may further include: a second flat layer 97 disposed on a side of the fourth conductive layer away from the substrate and a fifth conductive layer disposed on a side of the second flat layer 97 away from the substrate.
  • the fourth electrode plate is not provided in the third conductive layer
  • the fourth conductive layer may include at least the fifth electrode plate 75 of the storage capacitor
  • the fifth conductive layer may include at least the sixth electrode plate 76 of the storage capacitor
  • the orthographic projection of the sixth electrode plate 76 on the substrate at least partially overlaps with the orthographic projection of the fifth electrode plate 75 on the substrate
  • the fifth electrode plate 75 and the sixth electrode plate 76 constitute a storage capacitor.
  • the fifth electrode plate 75 can be connected to the anode connecting electrode, and the fifth electrode plate 75 has a potential of the fourth node.
  • the sixth electrode plate 76 can be connected to the third gate electrode 44 through a via, and the sixth electrode plate 76 has a potential of the first node.
  • the fifth electrode plate 75 located in the fourth conductive layer and the sixth electrode plate 76 located in the fifth conductive layer constitute a storage capacitor.
  • Fig. 36 is a schematic diagram of a planar structure of another display substrate of an exemplary embodiment of the present disclosure.
  • the main structure of this exemplary embodiment is substantially the same as the main structure shown in Fig. 15, except that the driving circuit layer may further include: a second flat layer 97 disposed on a side of the fourth conductive layer away from the substrate and a fifth conductive layer disposed on a side of the second flat layer 97 away from the substrate.
  • the third conductive layer may include at least a fourth electrode plate 74 of a storage capacitor, no fifth electrode plate is provided in the fourth conductive layer, the fifth conductive layer may include at least a sixth electrode plate 76 of a storage capacitor, the orthographic projection of the sixth electrode plate 76 on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate 74 on the substrate, and the fourth electrode plate 74 and the sixth electrode plate 76 constitute a storage capacitor.
  • the fourth electrode 74 can be connected to the third gate electrode 44 through a via, the fourth electrode 74 has a potential of the first node, the sixth electrode 76 can be connected to the anode connection electrode, the sixth electrode 76 has a potential of the fourth node, and the fourth electrode 74 located in the third conductive layer and the sixth electrode 76 located in the fifth conductive layer constitute a storage capacitor.
  • the storage capacitor structure shown in Figure 5 the storage capacitor structure shown in Figure 15, the storage capacitor structure shown in Figure 24, and the storage capacitor structures shown in Figures 34 to 36 can be combined with each other to form a storage capacitor structure in which multiple storage capacitors are connected in parallel to maximize the capacity of the storage capacitor, which is not limited in the present disclosure.
  • the structure and preparation process shown above in the present disclosure are merely exemplary.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.
  • the display substrate of the present disclosure may be applied to other display devices having a pixel driving circuit, such as a quantum dot display, etc., which is not limited in the present disclosure.
  • the present disclosure also provides a method for preparing a display substrate to manufacture the display substrate provided in the above embodiment.
  • the display substrate includes a plurality of circuit units, at least one circuit unit includes a pixel driving circuit, the pixel driving circuit includes a storage capacitor and a plurality of oxide transistors, the storage capacitor includes a first capacitor plate and a second capacitor plate, the orthographic projection of the first capacitor plate on the display substrate plane at least partially overlaps the orthographic projection of the second capacitor plate on the display substrate plane, and a capacitor insulating layer is provided between the first capacitor plate and the second capacitor plate;
  • the preparation method includes:
  • a semiconductor layer and a first source-drain metal layer are formed on a substrate along a direction away from the substrate, and at least one capacitor insulating layer is arranged on a side of the semiconductor layer close to the substrate, or at least one capacitor insulating layer is arranged on a side of the first source-drain metal layer away from the substrate.
  • the present disclosure also provides a display device, which includes the aforementioned display substrate.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc., but the embodiments of the present invention are not limited thereto.

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示基板及其制备方法、显示装置。显示基板包括多个电路单元，至少一个电路单元包括像素驱动电路，像素驱动电路包括存储电容和多个氧化物晶体管，存储电容包括第一电容极板和第二电容极板，第一电容极板和第二电容极板之间设置有电容绝缘层；在垂直于显示基板的平面上，至少一个电路单元包括在基底上沿着远离基底的方向设置的半导体层和第一源漏金属层，至少一个电容绝缘层设置在半导体层靠近基底的一侧，或者，至少一个电容绝缘层设置在第一源漏金属层远离基底的一侧。

Description

显示基板及其制备方法、显示装置 技术领域
本文涉及但不限于显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，包括多个电路单元，至少一个电路单元包括像素驱动电路，所述像素驱动电路包括存储电容和多个氧化物晶体管，所述存储电容至少包括第一电容极板和第二电容极板，所述第一电容极板在显示基板平面上的正投影与所述第二电容极板在显示基板平面上的正投影至少部分交叠，所述第一电容极板和第二电容极板之间设置有电容绝缘层；在垂直于所述显示基板的平面上，至少一个电路单元包括在基底上沿着远离所述基底的方向设置的半导体层和第一源漏金属层，至少一个电容绝缘层设置在所述半导体层靠近所述基底的一侧，或者，至少一个电容绝缘层设置在所述第一源漏金属层远离所述基底的一侧。
在示例性实施方式中，在垂直于所述显示基板的平面上，至少一个电路单元至少包括在基底上沿着远离所述基底的方向依次设置的遮挡导电层、第 一绝缘层、第一栅金属层、第二绝缘层、半导体层、第三绝缘层、第二栅金属层、第四绝缘层和第一源漏金属层，所述第一电容极板包括设置在所述遮挡导电层中的第一极板，所述第二电容极板包括设置在所述第一栅金属层中的第二极板，所述第一极板在所述基底上的正投影与所述第二极板在所述基底上的正投影至少部分交叠，所述第一极板和第二极板构成第一存储电容。
在示例性实施方式中，所述第一电容极板还包括设置在所述第二栅金属层中的第三极板，所述第三极板在所述基底上的正投影与所述第二极板在所述基底上的正投影至少部分交叠，所述第三极板和第二极板构成第二存储电容。
在示例性实施方式中，所述第三极板通过连接电极与所述第一极板连接，所述第一存储电容和第二存储电容构成并联结构的存储电容。
在示例性实施方式中，所述多个氧化物晶体管至少包括驱动晶体管，所述驱动晶体管包括底栅电极和顶栅电极，所述驱动晶体管的底栅电极设置在所述第一栅金属层中，所述驱动晶体管的顶栅电极设置在所述第二栅金属层中，所述驱动晶体管的底栅电极和所述第二极板为相互连接的一体结构，所述驱动晶体管的顶栅电极和所述第三极板为相互连接的一体结构。
在示例性实施方式中，多个氧化物晶体管还包括补偿晶体管和第一复位晶体管，所述第一复位晶体管的第一极与第一初始信号线连接，所述补偿晶体管的第二极与所述驱动晶体管的第一极连接，所述第一复位晶体管的第二极和所述补偿晶体管的第一极与所述驱动晶体管的顶栅电极连接。
在示例性实施方式中，多个氧化物晶体管还包括发光晶体管和第二复位晶体管，所述发光晶体管的第一极与所述驱动晶体管的第二极连接，所述第二复位晶体管的第一极与第二初始信号线连接，所述发光晶体管的第二极和所述第二复位晶体管的第二极与所述驱动晶体管的底栅电极连接。
在示例性实施方式中，在垂直于所述显示基板的平面上，至少一个电路单元至少包括在基底上沿着远离所述基底的方向依次设置的遮挡导电层、第一绝缘层、半导体层、第二绝缘层、第一栅金属层、第四绝缘层、第一源漏金属层、第一平坦层和第二源漏金属层，所述第一电容极板包括设置在所述 第一源漏金属层中的第四极板，所述第二电容极板包括设置在所述第二源漏金属层中的第五极板，所述第四极板在所述基底上的正投影与所述第五极板在所述基底上的正投影至少部分交叠，所述第四极板和第五极板构成第三存储电容。
在示例性实施方式中，所述第一源漏金属层和第一平坦层还设置有第五绝缘层，所述第一平坦层上设置有平坦凹槽，所述平坦凹槽内的第一平坦层被去掉，暴露出所述第五绝缘层，所述第五极板设置在所述平坦凹槽内，所述平坦凹槽在所述基底上的正投影包含所述第四极板和所述第二极板在所述基底上的正投影。
在示例性实施方式中，至少一个电路单元还包括设置在所述第二源漏金属层远离所述基底一侧的第二平坦层和设置在所述第二平坦层远离所述基底一侧的第三源漏金属层，所述第一电容极板还包括设置在所述第三源漏金属层中的第六极板，所述第六极板在所述基底上的正投影与所述第五极板在所述基底上的正投影至少部分交叠，所述第五极板和第六极板构成第四存储电容。
在示例性实施方式中，所述第六极板通过连接电极与所述第四极板连接，所述第三存储电容和第四存储电容构成并联结构的存储电容。
在示例性实施方式中，所述多个氧化物晶体管至少包括驱动晶体管，所述驱动晶体管包括底栅电极和顶栅电极，所述驱动晶体管的底栅电极设置在所述遮挡导电层中，所述驱动晶体管的顶栅电极设置在所述第一导电层中，所述第四极板通过过孔与所述驱动晶体管的顶栅电极连接。
在示例性实施方式中，多个氧化物晶体管还包括补偿晶体管和第一复位晶体管，所述第一复位晶体管的第一极与第一初始信号线连接，所述补偿晶体管的第二极与所述驱动晶体管的第一极连接，所述第一复位晶体管的第二极和所述补偿晶体管的第一极与所述驱动晶体管的顶栅电极连接。
在示例性实施方式中，多个氧化物晶体管还包括数据写入晶体管，所述数据写入晶体管的第一极与数据信号线连接，所述数据写入晶体管的第二极和所述驱动晶体管的第二极与所述驱动晶体管的底栅电极连接。
另一方面，本公开还提供了一种显示装置，包括前述的显示基板。
又一方面，本公开还提供了一种显示基板的制备方法，所述显示基板包括多个电路单元，至少一个电路单元包括像素驱动电路，所述像素驱动电路包括存储电容和多个氧化物晶体管，所述存储电容包括第一电容极板和第二电容极板，所述第一电容极板在显示基板平面上的正投影与所述第二电容极板在显示基板平面上的正投影至少部分交叠，所述第一电容极板和第二电容极板之间设置有电容绝缘层；所述制备方法包括：
在基底上沿着远离所述基底的方向形成半导体层和第一源漏金属层，至少一个电容绝缘层设置在所述半导体层靠近所述基底的一侧，或者，至少一个电容绝缘层设置在所述第一源漏金属层远离所述基底的一侧。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示基板的平面结构示意图；
图3为一种显示基板的剖面结构示意图；
图4为本公开示例性实施例一种像素驱动电路的等效电路图；
图5为本公开示例性实施例一种显示基板的平面结构示意图；
图6A为图5中A-A向的剖面示意图；
图6B为图5中B-B向的剖面示意图；
图6C为图5所示像素驱动电路的等效电路图；
图7为本公开一种显示基板形成遮挡导电层图案后的示意图；
图8A和图8B为本公开一种显示基板形成第一导电层图案后的示意图；
图9A和图9B为本公开一种显示基板形成半导体层图案后的示意图；
图10A和图10B为本公开一种显示基板形成第二导电层图案后的示意图；
图11为本公开一种显示基板形成第四绝缘层图案后的示意图；
图12A和图12B为本公开一种显示基板形成第三导电层图案后的示意图；
图13为本公开一种显示基板形成第一平坦层图案后的示意图；
图14A和图14B为本公开一种显示基板形成一种第四导电层图案后的示意图；
图14C和图14D为本公开一种显示基板形成另一种第四导电层图案后的示意图；
图14E和图14F为本公开一种显示基板形成又一种第四导电层图案后的示意图；
图14G和图14H为本公开一种显示基板形成又一种第四导电层图案后的示意图；
图15为本公开示例性实施例另一种显示基板的平面结构示意图；
图16A为图15中C-C向的剖面示意图；
图16B为图15中D-D向的剖面示意图；
图16C为图15所示像素驱动电路的等效电路图；
图17为本公开另一种显示基板形成遮挡导电层图案后的示意图；
图18为本公开另一种显示基板形成半导体层图案后的示意图；
图19为本公开另一种显示基板形成第一导电层图案后的示意图；
图20为本公开另一种显示基板形成第四绝缘层图案后的示意图；
图21为本公开另一种显示基板形成第三导电层图案后的示意图；
图22为本公开另一种显示基板形成第一平坦层图案后的示意图；
图23为本公开另一种显示基板形成第四导电层图案后的示意图；
图24为本公开示例性实施例又一种显示基板的平面结构示意图；
图25A为图24中E-E向的剖面示意图；
图25B为图24中F-F向的剖面示意图；
图25C为图24所示像素驱动电路的等效电路图；
图26为本公开又一种显示基板形成遮挡导电层图案后的示意图；
图27为本公开又一种显示基板形成半导体层图案后的示意图；
图28为本公开又一种显示基板形成第一导电层图案后的示意图；
图29为本公开又一种显示基板形成第二导电层图案后的示意图；
图30为本公开又一种显示基板形成第四绝缘层图案后的示意图；
图31为本公开又一种显示基板形成第三导电层图案后的示意图；
图32为本公开又一种显示基板形成第一平坦层图案后的示意图；
图33为本公开又一种显示基板形成第四导电层图案后的示意图；
图34为本公开示例性实施例又一种显示基板的平面结构示意图；
图35为本公开示例性实施例又一种显示基板的平面结构示意图；
图36为本公开示例性实施例又一种显示基板的平面结构示意图。
附图标记说明:
10—基底；             11—第一遮挡线；       12—第二遮挡线；
13—第二遮挡线；       14—第四遮挡线；       15—第五遮挡线；
16—遮挡电极；         20—驱动电路层；       21—第一有源层；
22—第二有源层；       23—第三有源层；       24—第四有源层；
25—第五有源层；       26—第六有源层；       27—第七有源层；
30—发光结构层；       31—第一扫描信号线；   32—第二扫描信号线；
33—第三扫描信号线；   34—第四扫描信号线；   35—发光控制线；
40—封装结构层；       41—第一初始子线；     42—第二初始子线；
43—开口；             44—第三栅电极；       51—第一连接电极；
52—第二连接电极；     53—第三连接电极；     54—第四连接电极；
55—第五连接电极；      56—第六连接电极；      57—第七连接电极；
58—第八连接电极；      59—第九连接电极；      60—第十连接电极；
61—阳极连接电极；      62—第一电源线；        63—数据信号线；
64—初始连接线；        71—第一极板；          72—第二极板；
73—第三极板；          74—第四极板；          75—第五极板；
76—第六极板；          77—第七极板；          78—第八极板；
81—第一连接块；        82—第二连接块；        83—第三连接块；
91—第一绝缘层；        92—第二绝缘层；        93—第三绝缘层；
94—第四绝缘层；        95—第五绝缘层；        96—第一平坦层；
97—第二平坦层。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的 词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线状成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线状成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括像素驱动电路，像素驱动电路与扫描信号线、发光信号线和数据信号线连接。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以单元行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉 冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
图2为一种显示基板的平面结构示意图。如图2所示，显示基板可以包括以矩阵方式排布的多个像素单元P，至少一个像素单元P可以包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3。每个子像素可以均包括电路单元和发光器件，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、发光信号线和数据信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光器件输出相应的电流。每个子像素中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形，三个子像素可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
在示例性实施方式中，像素单元可以包括四个子像素，四个子像素可以采用水平并列、竖直并列或正方形等方式排列，本公开在此不做限定。
图3为一种显示基板的剖面结构示意图，示意了四个子像素的结构。如图3所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底10上的驱动电路层20、设置在驱动电路层20远离基底10一侧的发光结构层30以及设置在发光结构层30远离基底10一侧的封装结构层40。在一些可能的实现方式中，显示基板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，基底10可以是柔性基底，或者可以是刚性基底。驱动电路层20可以包括多个电路单元，每个电路单元可以至少包括由多 个晶体管和存储电容构成的像素驱动电路。发光结构层30可以包括多个发光器件，每个发光器件可以至少包括阳极、像素定义层、有机发光层和阴极，阳极与像素驱动电路连接，有机发光层与阳极连接，阴极与有机发光层连接，有机发光层在阳极和阴极驱动下出射相应颜色的光线。封装结构层40可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，形成无机材料/有机材料/无机材料叠层结构，可以保证外界水汽无法进入发光结构层30。
随着OLED显示技术的逐渐成熟和良率不断提高，OLED显示装置的成本不断下降，使得OLED显示装置逐渐应用于更多领域，例如中大尺寸的电子产品领域。随着显示基板的尺寸的增大，由于采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)薄膜晶体管的显示基板的良率下降，导致成本偏高，因而全部采用氧化物(Oxide)晶体管的显示基板开始被重视。
本公开示例性实施例提供一种显示基板，包括多个电路单元，至少一个电路单元包括像素驱动电路，所述像素驱动电路包括存储电容和多个氧化物晶体管，所述存储电容至少包括第一电容极板和第二电容极板，所述第一电容极板在显示基板平面上的正投影与所述第二电容极板在显示基板平面上的正投影至少部分交叠，所述第一电容极板和第二电容极板之间设置有电容绝缘层；在垂直于所述显示基板的平面上，至少一个电路单元包括在基底上沿着远离所述基底的方向设置的半导体层和第一源漏金属层，至少一个电容绝缘层设置在所述半导体层靠近所述基底的一侧，或者，至少一个电容绝缘层设置在所述第一源漏金属层远离所述基底的一侧。
在一种示例性实施方式中，在垂直于所述显示基板的平面上，至少一个电路单元至少包括在基底上沿着远离所述基底的方向依次设置的遮挡导电层、第一绝缘层、第一栅金属层、第二绝缘层、半导体层、第三绝缘层、第二栅金属层、第四绝缘层和第一源漏金属层，所述第一电容极板包括设置在所述遮挡导电层中的第一极板，所述第二电容极板包括设置在所述第一栅金属层中的第二极板，所述第一极板在所述基底上的正投影与所述第二极板在所述基底上的正投影至少部分交叠，所述第一极板和第二极板构成第一存储 电容。
在示例性实施方式中，所述第一电容极板还包括设置在所述第二栅金属层中的第三极板，所述第三极板在所述基底上的正投影与所述第二极板在所述基底上的正投影至少部分交叠，所述第三极板和第二极板构成第二存储电容。
在示例性实施方式中，所述第三极板通过连接电极与所述第一极板连接，所述第一存储电容和第二存储电容构成并联结构的存储电容。
在另一种示例性实施方式中，在垂直于所述显示基板的平面上，至少一个电路单元至少包括在基底上沿着远离所述基底的方向依次设置的遮挡导电层、第一绝缘层、半导体层、第二绝缘层、第一栅金属层、第四绝缘层、第一源漏金属层、第一平坦层和第二源漏金属层，所述第一电容极板包括设置在所述第一源漏金属层中的第四极板，所述第二电容极板包括设置在所述第二源漏金属层中的第五极板，所述第四极板在所述基底上的正投影与所述第五极板在所述基底上的正投影至少部分交叠，所述第四极板和第五极板构成第三存储电容。
在示例性实施方式中，至少一个电路单元还包括设置在所述第二源漏金属层远离所述基底一侧的第二平坦层和设置在所述第二平坦层远离所述基底一侧的第三源漏金属层，所述第一电容极板还包括设置在所述第三源漏金属层中的第六极板，所述第六极板在所述基底上的正投影与所述第五极板在所述基底上的正投影至少部分交叠，所述第五极板和第六极板构成第四存储电容。
在示例性实施方式中，所述第六极板通过连接电极与所述第四极板连接，所述第三存储电容和第四存储电容构成并联结构的存储电容。
在示例性实施方式中，所述半导体层的材料可以包括氧化铟镓锌(IGZO)。然而，本公开示例性实施例对此并不限定。例如，所述半导体层的材料可以采用其他金属氧化物材料。
下面通过一些示例对本公开显示基板进行举例说明。
图4为本公开示例性实施例一种像素驱动电路的等效电路图。在示例性 实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。如图4所示，本公开示例性实施例的像素驱动电路可以包括7个晶体管(第一晶体管T1至第七晶体管T7)和1个存储电容C，像素驱动电路分别与9条信号线(第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3、第四扫描信号线S4、发光信号线E、第一初始信号线INIT1、第二初始信号线INIT2、数据信号线D和第一电源线VDD)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2、第三节点N3和第四节点N4。其中，第一节点N1分别与第一晶体管T1的第二极、第二晶体管T2的第一极、第三晶体管T3的栅电极和存储电容C的第一端连接，第二节点N2分别与第二晶体管T2的第二极、第三晶体管T3的第一极和第五晶体管T5的第二极连接，第三节点N3分别与第三晶体管T3的第二极、第四晶体管T4的第二极和第六晶体管T6的第一极连接，第四节点N4分别与第六晶体管T6的第二极、第七晶体管T7的第二极和存储电容C的第二端连接，第四节点N4还与发光器件EL的阳极连接。
在示例性实施方式中，存储电容C的第一端与第一节点N1连接，存储电容C的第二端与第四节点N4连接，即存储电容C的第一端与第三晶体管T3的栅电极连接，存储电容C的第二端与发光器件EL的阳极连接。
在示例性实施方式中，第一晶体管T1的栅电极与第三扫描信号线S3连接，第一晶体管T1的第一极与第一初始信号线INIT1连接，第一晶体管T1的第二极与第一节点N1连接。当导通电平扫描信号施加到第三扫描信号线S3时，第一晶体管T1导通，将第一初始化电压传输到存储电容C的第一端，实现存储电容C的初始化。
在示例性实施方式中，第二晶体管T2的栅电极与第一扫描信号线S1连接，第二晶体管T2的第一极与第一节点N1连接，第二晶体管T2的第二极与第二节点N2连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的栅电极与第三晶体管T3的第一极连接。
在示例性实施方式中，第三晶体管T3的栅电极与第一节点N1连接，即第三晶体管T3的栅电极与存储电容C的第一端连接，第三晶体管T3的第一极与第二节点N2连接，第三晶体管T3的第二极与第三节点N3连接。第三 晶体管T3可以称为驱动晶体管，第三晶体管T3根据其栅电极与第一极之间的电位差来确定在第一电源线VDD与发光器件之间流动的驱动电流的大小。
在示例性实施方式中，第四晶体管T4的栅电极与第二扫描信号线S2连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第三节点N3连接。当导通电平扫描信号施加到第二扫描信号线S2时，第四晶体管T4使数据信号线D的数据电压输入到第三节点N3。
在示例性实施方式中，第五晶体管T5的栅电极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第二节点N2连接。第六晶体管T6的栅电极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与第四节点N4连接。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与发光器件之间形成驱动电流路径而使发光器件发光。
在示例性实施方式中，第七晶体管T7的栅电极与第四扫描信号线S4连接，第七晶体管T7的第一极与第二初始信号线INIT2连接，第七晶体管T7的第二极与第四节点N4连接。当导通电平扫描信号施加到第四扫描信号线S4时，第七晶体管T7将第二初始电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件EL的第一极中累积的电荷量。
在示例性实施方式中，发光器件EL可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，或者可以是QLED，包括叠设的第一极(阳极)、量子点发光层和第二极(阴极)。
在示例性实施方式中，像素驱动电路的七个晶体管可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。
在示例性实施方式中，像素驱动电路的七个晶体管可以采用氧化物薄膜晶体管。氧化物薄膜晶体管的有源层可以采用氧化物半导体(Oxide)。氧化物薄膜晶体管具有漏电流低等优点，采用设置氧化物薄膜晶体管的显示基 板，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第一电源线VDD可以配置为向像素驱动电路提供恒定的第一电压信号，第二电源线VSS可以配置为向像素驱动电路提供恒定的第二电压信号，并且第一电压信大于第二电压信号。第一初始信号线INIT1可以配置为向像素驱动电路提供第一初始信号，第二初始信号线INIT2可以配置为向像素驱动电路提供第二初始信号。例如，第一初始信号可以不同于第二初始信号。第一初始信号和第二初始信号可以为恒压信号，其大小例如可以介于第一电源线VDD提供的第一电压信号和第二电源线VSS提供的第二电压信号之间，但不限于此。在一些可能的示例性实施方式中，第一初始信号与第二初始信号可以相同，可以仅设置第一初始信号线来提供第一初始信号。
在示例性实施方式中，以像素驱动电路包括的第一晶体管T1至第七晶体管T7均为N型晶体管为例，像素驱动电路的工作过程可以包括以下阶段。
第一阶段A1，称为初始化阶段。第三扫描信号线S3提供的高电平信号使第一晶体管T1导通，第一初始信号线INIT1提供的第一初始信号被提供至第一节点N1，对第一节点N1进行初始化，清除存储电容C中原有数据电压。此阶段第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6以及第七晶体管T7断开，发光元件EL不发光。
第二阶段A2，称为数据写入阶段或者阈值补偿阶段。第一扫描信号线S1、第二扫描信号线S2和第四扫描信号线S4提供高电平信号，使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。此阶段由于存储电容C的第一端为高电平，因此第三晶体管T3导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压Vd经过第三节点N3、导通的第三晶体管T3、第二节点N2、导通的第二晶体管T2提供至第一节点N1，并将数据信号线D输出的数据电压Vd与第三晶体管T3的阈值电压Vth之差充入存储电容C。第七晶体管T7导通使得第二初始信号线INIT2提供的第二初始信号提供至发光元件EL的阳极，对发光元件EL的阳极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保发光元件EL不发光。此 阶段第一晶体管T1、第五晶体管T5和第六晶体管T6断开。
第三阶段A3，称为发光阶段。发光控制线E提供高电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的第一电压信号通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向发光元件EL的阳极提供驱动电压，驱动发光元件EL发光。
在像素驱动电路的驱动过程中，流过第三晶体管T3(即驱动晶体管)的驱动电流由其栅极和第一极之间的电压差决定。由于第一节点N1的电压为Vd-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K×(Vgs-Vth) 2＝K×[(Vdd-Vd+|Vth|)-Vth] 2＝K×[Vdd-Vd] 2。
其中，I为流过第三晶体管T3的驱动电流，也就是驱动发光元件EL的驱动电流，K为常数，Vgs为第三晶体管T3的栅极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的第一电压信号。
由上式中可以看到，流经发光元件EL的电流与第三晶体管T3的阈值电压无关。本实施例的像素驱动电路可以较好地补偿第三晶体管T3的阈值电压。
图5为本公开示例性实施例一种显示基板的平面结构示意图，示意了一个电路单元中像素驱动电路的结构，图6A为图5中A-A向的剖面示意图，图6B为图5中B-B向的剖面示意图，图6C为图5所示像素驱动电路的等效电路图。在示例性实施方式中，在垂直于显示基板的方向上，显示基板可以包括设置在基底上的驱动电路层、设置在驱动电路层远离基底一侧的发光结构层以及设置在发光结构层远离基底一侧的封装结构层。在平行于显示基板的方向上，驱动电路层可以包括构成多个单元行和多个单元列的电路单元，至少一个电路单元包括像素驱动电路，像素驱动电路可以包括存储电容、第一晶体管T1至第七晶体管T7，第一晶体管T1至第七晶体管T7为氧化物晶体管。
如图5、图6A和图6B所示，在示例性实施方式中，驱动电路层可以至少包括：设置在基底10上的遮挡导电层，设置在遮挡导电层远离基底一侧的第一绝缘层91，设置在第一绝缘层91远离基底一侧的第一导电层，设置在 第一导电层远离基底一侧的第二绝缘层92，设置在第二绝缘层92远离基底一侧的半导体层，设置在半导体层远离基底一侧的第三绝缘层93，设置在第三绝缘层93远离基底一侧的第二导电层，设置在第二导电层远离基底一侧的第四绝缘层94，设置在第四绝缘层94远离基底一侧的第三导电层。
在示例性实施方式中，遮挡导电层可以至少包括存储电容的第一极板71，第一导电层可以至少包括存储电容的第二极板72，半导体层可以至少包括第一晶体管的有源层至第七晶体管的有源层，第二导电层可以至少包括存储电容的第三极板73，第三导电层可以至少包括多个连接电极。
在示例性实施方式中，第一极板71在基底上的正投影与第二极板72在基底上的正投影至少部分交叠，第一极板71和第二极板72构成第一存储电容，第一绝缘层91为设置在第一极板71和第二极板72之间的电容绝缘层。第三极板73在基底上的正投影与第二极板72在基底上的正投影至少部分交叠，第二极板72和第三极板73构成第二存储电容，第一存储电容和第二存储电容构成并联结构的存储电容。
在示例性实施方式中，第一晶体管T1至第七晶体管T7可以均包括底栅电极和顶栅电极，底栅电极可以设置在第一导电层中，顶栅电极可以设置在第二导电层中。例如，以第三晶体管T3为例，第二导电层中的第三极板73可以作为第三晶体管T3的顶栅电极，且与像素驱动电路的第一节点N1连接，第一导电层中的第二极板72可以作为第三晶体管T3的底栅电极，实现对第三晶体管T3的遮挡，且与像素驱动电路的第四节点N4连接，如图6C所示。
在示例性实施方式中，第二导电层还可以包括第一初始子线41和第二初始子线42，第三导电层的多个连接电极可以至少包括：第一连接电极51、第二连接电极52、第三连接电极53、第四连接电极54、第五连接电极55、第六连接电极56、第七连接电极57、第八连接电极58、第九连接电极59和第十连接电极60。
在示例性实施方式中，第一连接电极51可以作为像素驱动电路的第一节点电极(N1节点电极)，第一连接电极51的第一端通过过孔与第三极板73连接，第一连接电极51的第二端通过过孔与第一有源层的第二区(也是第二有源层的第一区)连接，因而实现了第一晶体管T1的第二极、第二晶 体管T2的第一极和第三极板73(第三晶体管T3的顶栅电极)具有相同的电位。
在示例性实施方式中，第二连接电极52可以通过过孔与第五有源层的第一区连接，由于第二连接电极52被配置为与第一电源线连接，因而实现了第一电源线通过第二连接电极52将第一电源电压写入第五晶体管T5的第一极。
在示例性实施方式中，第三连接电极53可以作为像素驱动电路的第二节点电极(N2节点电极)，第三连接电极53的第一端通过过孔与第二有源层的第二区(也是第三有源层的第一区)连接，第三连接电极53的第二端通过过孔与第五有源层的第二区连接，因而实现了第二晶体管T2的第二极、第三晶体管T3的第一极和第五晶体管T5的第二极具有相同的电位。
在示例性实施方式中，第四连接电极54可以作为像素驱动电路的数据输入电极，第四连接电极54通过过孔与第四有源层24的第一区连接，由于第四连接电极54被配置为与数据信号线连接，因而实现了数据信号线通过第四连接电极54将数据信号写入第四晶体管T4的第一极。
在示例性实施方式中，第五连接电极55可以作为像素驱动电路的第三节点电极(N3节点电极)，一方面，第五连接电极55通过过孔与第四有源层24的第二区(也是第三有源层的第二区)连接，另一方面，第五连接电极55通过过孔与第六有源层的第一区连接，因而实现了第三晶体管T3的第二极、第四晶体管T4的第二极和第六晶体管T6的第一极具有相同的电位。
在示例性实施方式中，第六连接电极56通过过孔与第六有源层的第二区(也是第七有源层的第二区)连接，因而实现了第六晶体管T6的第二极和第七晶体管T7的第二极具有相同的电位。
在示例性实施方式中，第七连接电极57可以作为像素驱动电路的第四节点电极(N4节点电极)，一方面，第七连接电极57通过过孔与第二极板72连接，另一方面，第七连接电极57通过阳极连接电极(未示出)与第六连接电极56连接，因而实现了存储电容的第二极板72、第六晶体管T6的第二极和第七晶体管T7的第二极的具有相同的电位。由于第二极板72同时作为第三晶体管T3的底栅电极，因而第三晶体管T3的底栅电极具有第四节点 电极N4的电位。
在示例性实施方式中，第十连接电极60的第一端通过过孔与第一极板71连接，第十连接电极60的第二端通过过孔与第三极板73连接，因而实现了第一极板71和第三极板73具有相同的电位，第一极板71、第二极板72和第三极板73构成并联结构的存储电容。
在示例性实施方式中，第一初始子线41可以沿着第一方向X间隔设置，在第一方向X相邻的第一初始子线41通过第八连接电极58相互连接，形成沿着第一方向X延伸的第一初始信号线。第八连接电极58还通过过孔与第一有源层的第一区连接，因而实现了第一初始信号线将第一初始电压写入第一晶体管T1的第一极。第二初始子线42可以沿着第一方向X间隔设置，在第一方向X相邻的第二初始子线42通过第九连接电极59相互连接，形成沿着第一方向X延伸的第二初始信号线。第九连接电极59还通过过孔与第七有源层的第一区连接，因而实现了第二初始信号线将第二初始电压写入第七晶体管T7的第一极。
下面通过本示例性实施例显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多8种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施方式中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，显示基板的制备过程可以包括如下操作。
(11)形成遮挡导电层图案。在示例性实施方式中，形成遮挡导电层图案可以包括：在基底上沉积遮挡薄膜，通过图案化工艺对遮挡薄膜进行图案化，在基底上形成遮挡导电层图案，如图7所示。
在示例性实施方式中，遮挡导电层图案可以至少包括第一极板71，第一极板71的形状可以为矩形状，矩形状的角部可以设置倒角，第一极板71可以作为存储电容的一个极板。
在示例性实施方式中，第一极板71第一方向X的一侧还连接有第一连接块81，第一连接块81被配置与后续形成的第十连接电极连接，实现第一极板71与后续形成的第三极板的相互连接。
在示例性实施方式中，遮挡导电层的材料可以采用金属钼(Mo)，遮挡导电层的厚度可以约为80nm至120nm。例如，遮挡导电层的厚度可以约为100nm左右。
(12)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第一绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖遮挡导电层图案的第一绝缘层，以及设置在第一绝缘层上的第一导电层图案，如图8A和图8B所示，图8B为图8A中第一导电层的平面示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，第一导电层图案可以至少包括：第一遮挡线11、第二遮挡线12、第三遮挡线13、第四遮挡线14、第五遮挡线15和存储电容的第二极板72。
在示例性实施方式中，第一遮挡线11、第二遮挡线12、第三遮挡线13、第四遮挡线14和第五遮挡线15的形状可以为沿着第一方向X延伸的直线状。第一遮挡线11可以位于第二极板72第二方向Y的反方向的一侧，第一遮挡线11被配置为对第二晶体管T2进行遮挡且作为第二晶体管T2的底栅电极。第二遮挡线12可以位于第二极板72第二方向Y的一侧，第二遮挡线12被配置为对第四晶体管T4进行遮挡且作为第四晶体管T4的底栅电极。第三遮 挡线13可以位于第一遮挡线11远离第二极板72的一侧，第三遮挡线13被配置为对第一晶体管T1进行遮挡且作为第一晶体管T1的底栅电极。第四遮挡线14可以位于第二遮挡线12远离第二极板72的一侧，第四遮挡线14被配置为对第七晶体管T7进行遮挡且作为第七晶体管T7的底栅电极。第五遮挡线15可以位于第二遮挡线12和第四遮挡线14之间，第五遮挡线15被配置为对第五晶体管T5和第六晶体管T6进行遮挡且作为第五晶体管T5和第六晶体管T6的底栅电极。
本公开中，A沿着B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分是线、线段或条形状体，主要部分沿着B方向伸展，且主要部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。以下描述中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。
在示例性实施方式中，第二极板72可以位于第一遮挡线11和第二遮挡线12之间，第二极板72的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二极板72在基底上的正投影与第一极板71在基底上的正投影至少部分交叠，第二极板72可以作为存储电容的另一个极板。
在示例性实施方式中，第二极板72还被配置为对后续形成的第三晶体管进行遮挡，且作为第三晶体管T3的底栅电极。
在示例性实施方式中，第一绝缘层为设置在第一极板和第二极板之间的电容绝缘层，第一绝缘层的材料可以采用SiNx，第一绝缘层的厚度可以约为100nm至170nm。例如，第一绝缘层的厚度可以约为130nm左右。
在示例性实施方式中，第一导电层的材料可以采用Mo，第一导电层的厚度可以约为200nm至300nm。例如，第一导电层的厚度可以约为250nm左右。
(13)形成半导体层图案。在示例性实施方式中，形成半导体层图案可以包括：在基底上依次沉积第二绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖第一导电层的第二绝缘层，以及设置在第二绝缘层上的半导体层图案，如图9A和图9B所示，图9B为图9A中半导体层的平面示意图。
在示例性实施方式中，半导体层图案可以至少包括第一晶体管T1的第一有源层21至第七晶体管T7的第七有源层27，且第一有源层21、第二有源层22、第三有源层23和第四有源层24为相互连接的一体结构。
在示例性实施方式中，在第一方向X上，第一有源层21、第二有源层22和第五有源层25可以位于第三有源层23的同一侧，第二有源层22和第四有源层24可以位于第三有源层23的不同侧。在第二方向Y上，第一有源层21和第二有源层22可以位于第三有源层23第二方向Y的反方向的一侧，第四有源层24、第五有源层25、第六有源层26和第七有源层27可以位于第三有源层23第二方向Y的一侧。
在示例性实施方式中，第三有源层23的形状可以呈“n”字形，第一有源层21、第二有源层22、第四有源层24至第七有源层27的形状可以呈“I”字形或者“L”字形。
在示例性实施方式中，第三有源层23在基底上的正投影可以位于第二极板72在基底上的正投影的范围之内，使得第三晶体管T3的沟道区域可以被第二极板72有效遮挡。
在示例性实施方式中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第一有源层的第二区21-2可以作为第二有源层的第一区22-1(即第一有源层的第二区21-2与第二有源层的第一区22-1直接连接)，第二有源层的第二区22-2可以作为第三有源层的第一区23-1(即第二有源层的第二区22-2与第三有源层的第一区23-1直接连接)，第三有源层的第二区23-2可以作为第四有源层的第二区24-2(即第三有源层的第二区23-2与第四有源层的第二区24-2直接连接)，第六有源层的第二区26-2可以作为第七有源层的第二区27-2(即第六有源层的第二区26-2与第七有源层的第二区27-2直接连接)，第一有源层的第一区21-1、第四有源层的第一区24-1、第五有源层的第一区25-1、第五有源层的第二区25-2、第六有源层的第一区26-1和第七有源层的第一区27-1可以单独设置。
在示例性实施方式中，半导体层可以采用氧化物，第一晶体管T1至第七晶体管T7均为氧化物晶体管。在示例性实施方式中，半导体层可以采用 电子迁移率较高的氧化铟镓锌(IGZO)。
在示例性实施方式中，半导体层的厚度可以约为20nm至40nm。例如，半导体层的厚度可以约为30nm左右。
在示例性实施方式中，第二绝缘层的材料可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。例如，第二绝缘层可以采用SiN/SiO。第二绝缘层的厚度可以约为350nm至450nm。例如，第二绝缘层中SiN的厚度可以约为100nm左右，第二绝缘层中SiO的厚度可以约为300nm左右，第二绝缘层的总厚度可以约为400nm左右。
(14)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成覆盖半导体层的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，如图10A和图10B所示，图10B为图10A中第二导电层的平面示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，第二导电层图案可以至少包括：第一扫描信号线31、第二扫描信号线32、第三扫描信号线33、第四扫描信号线34、发光控制线35、第一初始子线41、第二初始子线42和第三极板73。
在示例性实施方式中，第三极板73的轮廓可以为矩形状，矩形状的角部可以设置倒角，第三极板73在基底上的正投影与第三有源层在基底上的正投影至少部分交叠，第三极板73在基底上的正投影与第二极板72在基底上的正投影至少部分交叠，一方面，第三极板73可以作为第三晶体管T3的顶栅电极，另一方面，第三极板73可以作为存储电容的又一个极板，第一极板71、第二极板72和第三极板73构成像素驱动电路并联结构的存储电容。
在示例性实施方式中，第三极板73上设置有开口43，开口43的形状可以为矩形状，可以位于第三极板73的中部，使第三极板73形成环形结构。开口43暴露出第三绝缘层，且第二极板72在基底上的正投影包含开口43在基底上的正投影。在示例性实施方式中，开口43被配置为容置后续形成的第一过孔，第一过孔位于开口43内并暴露出第二极板72，使后续形成的第 一晶体管T1的第二极与第二极板72连接。
在示例性实施方式中，第三极板73第一方向X的一侧还连接有第二连接块82，第二连接块82被配置与后续形成的第十连接电极连接，实现第一极板71与第三极板73的相互连接。
在示例性实施方式中，第一扫描信号线31、第二扫描信号线32、第三扫描信号线33、第四扫描信号线34和发光控制线35的形状可以为沿着第一方向X延伸的直线状。
在示例性实施方式中，第一扫描信号线31可以位于第三极板73第二方向Y的反方向的一侧，第一扫描信号线31与第二有源层相重叠的区域作为第二晶体管T2的顶栅电极。
在示例性实施方式中，第一扫描信号线31在基底上的正投影可以位于第一遮挡线11在基底上的正投影的范围之内，使得第二晶体管T2的沟道区域可以被第一遮挡线11有效遮挡。
在示例性实施方式中，第二扫描信号线32可以位于第三极板73第二方向Y的一侧，第二扫描信号线32与第四有源层相重叠的区域作为第四晶体管T4的顶栅电极。
在示例性实施方式中，第二扫描信号线32在基底上的正投影可以位于第二遮挡线12在基底上的正投影的范围之内，使得第四晶体管T4的沟道区域可以被第二遮挡线12有效遮挡。
在示例性实施方式中，第三扫描信号线33可以位于第一扫描信号线31远离第三极板73的一侧，第三扫描信号线33与第一有源层相重叠的区域作为第一晶体管T1的顶栅电极。
在示例性实施方式中，第三扫描信号线33在基底上的正投影可以位于第三遮挡线13在基底上的正投影的范围之内，使得第一晶体管T1的沟道区域可以被第三遮挡线13有效遮挡。
在示例性实施方式中，第四扫描信号线34可以位于第二扫描信号线32远离第三极板73的一侧，第四扫描信号线34与第七有源层相重叠的区域作为第七晶体管T7的顶栅电极。
在示例性实施方式中，第四扫描信号线34在基底上的正投影可以位于第四遮挡线14在基底上的正投影的范围之内，使得第七晶体管T7的沟道区域可以被第四遮挡线14有效遮挡。
在示例性实施方式中，发光控制线35可以位于第二扫描信号线32和第四扫描信号线34之间，发光控制线35与第五有源层相重叠的区域作为第五晶体管T5的顶栅电极，发光控制线35与第六有源层相重叠的区域作为第六晶体管T6的顶栅电极。
在示例性实施方式中，发光控制线35在基底上的正投影可以位于第五遮挡线15在基底上的正投影的范围之内，使得第五晶体管T5和第六晶体管T6的沟道区域可以被第五遮挡线15有效遮挡。
在示例性实施方式中，第一初始子线41的形状可以为主体部分沿着第一方向X延伸的线形状。在第一方向X上，第一初始子线41可以设置在第一方向X上相邻电路单元的第一有源层的第一区之间。在第二方向Y上，第一初始子线41可以位于第三扫描信号线33远离第三极板73的一侧。第一初始子线41被配置为利用后续形成的第八连接电极构成传输第一初始信号且沿着第一方向X延伸的第一初始信号线。
在示例性实施方式中，第二初始子线42的形状可以为主体部分沿着第一方向X延伸的线形状。在第一方向X上，第二初始子线42可以设置在第一方向X上相邻电路单元的第七有源层的第一区之间。在第二方向Y上，第二初始子线42可以位于第四扫描信号线34远离第三极板73的一侧。第二初始子线42被配置为利用后续形成的第九连接电极构成传输第二初始信号且沿着第一方向X延伸的第二初始信号线。
在示例性实施方式中，第三绝缘层为设置在第二极板和第三极板之间的电容绝缘层，第三绝缘层的材料可以采用SiO，第三绝缘层的厚度可以约为100nm至170nm。例如，第三绝缘层的厚度可以约为140nm左右。
在示例性实施方式中，第二导电层的层材料可以采用Mo，第二导电层的厚度可以约为200nm至300nm。例如，第二导电层的厚度可以约为250nm左右。
(15)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层，第四绝缘层上设置有多个过孔，如图11所示。
在示例性实施方式中，多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十一过孔V11、第十二过孔V12、第十三过孔V13、第十三过孔V13、第十四过孔V14、第十五过孔V15、第十六过孔V16、第十七过孔V17、第十八过孔V18和第十九过孔V19。
在示例性实施方式中，第一过孔V1在基底上的正投影位于开口43在基底上的正投影的范围之内，第一过孔V1内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二极板72的表面，第一过孔V1配置为使后续形成的第一连接电极通过该过孔与第二极板72连接。
在示例性实施方式中，第二过孔V2在基底上的正投影位于第一有源层的第二区(也是第二有源层的第一区)在基底上的正投影的范围之内，第二过孔V2内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一有源层的第二区的表面，第二过孔V2被配置为使后续形成的第一连接电极通过该过孔与第一有源层的第二区(也是第二有源层的第一区)连接。
在示例性实施方式中，第三过孔V3在基底上的正投影位于第五有源层的第一区在基底上的正投影的范围之内，第三过孔V3内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面，第三过孔V3被配置为使后续形成的第二连接电极通过该过孔与第五有源层的第一区连接。
在示例性实施方式中，第四过孔V4在基底上的正投影位于第五有源层的第二区在基底上的正投影的范围之内，第四过孔V4内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第五有源层的第二区的表面，第四过孔V4被配置为使后续形成的第三连接电极通过该过孔与第五有源层的第二区连接。
在示例性实施方式中，第五过孔V5在基底上的正投影位于第二有源层的第二区(也是第三有源层的第一区)在基底上的正投影的范围之内，第五过孔V5内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第二有源层的第二 区的表面，第五过孔V5被配置为使后续形成的第三连接电极通过该过孔与第二有源层的第二区(也是第三有源层的第一区)连接。
在示例性实施方式中，第六过孔V6在基底上的正投影位于第四有源层的第一区在基底上的正投影的范围之内，第六过孔V6内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面，第六过孔V6被配置为使后续形成的第四连接电极通过该过孔与第四有源层的第一区连接。
在示例性实施方式中，第七过孔V7在基底上的正投影位于第四有源层的第二区(也是第三有源层的第二区)在基底上的正投影的范围之内，第七过孔V7内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第四有源层的第二区的表面，第七过孔V7被配置为使后续形成的第五连接电极通过该过孔与第四有源层的第二区(也是第三有源层的第二区)连接。
在示例性实施方式中，第八过孔V8在基底上的正投影位于第六有源层的第一区在基底上的正投影的范围之内，第八过孔V8内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第六有源层的第一区的表面，第八过孔V8被配置为使后续形成的第五连接电极通过该过孔与第六有源层的第一区连接。
在示例性实施方式中，第九过孔V9在基底上的正投影位于第六有源层的第二区(也是第七有源层的第二区)在基底上的正投影的范围之内，第九过孔V9内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第六有源层的第二区的表面，第九过孔V9被配置为使后续形成的第六连接电极通过该过孔与第六有源层的第二区(也是第七有源层的第二区)连接。
在示例性实施方式中，第十一过孔V11在基底上的正投影位于第三极板73在基底上的正投影的范围之内，第十一过孔V11内的第四绝缘层被刻蚀掉，暴露出第一极板71的表面，第十一过孔V11被配置为使后续形成的第一连接电极通过该过孔与第三极板73连接。
在示例性实施方式中，第十二过孔V12在基底上的正投影位于第一有源层的第一区在基底上的正投影的范围之内，第十二过孔V12内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一有源层的第一区的表面，第十二过孔V12被配置为使后续形成的第八连接电极通过该过孔与第一有源层的第一区连接。
在示例性实施方式中，第十三过孔V13在基底上的正投影位于第七有源层的第一区在基底上的正投影的范围之内，第十三过孔V13内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第七有源层的第一区的表面，第十三过孔V13被配置为使后续形成的第九连接电极通过该过孔与第七有源层的第一区连接。
在示例性实施方式中，第十四过孔V14和第十五过孔V15在基底上的正投影位于第一初始子线41在基底上的正投影的范围之内，第十四过孔V14和第十五过孔V15内的第四绝缘层被刻蚀掉，暴露出第一初始子线41的表面，第十四过孔V14和第十五过孔V15被配置为使后续形成的第八连接电极通过该过孔使相邻的第一初始子线41相互连接。
在示例性实施方式中，第十六过孔V16和第十七过孔V17在基底上的正投影位于第二初始子线42在基底上的正投影的范围之内，第十六过孔V16和第十七过孔V17内的第四绝缘层被刻蚀掉，暴露出第二初始子线42的表面，第十六过孔V16和第十七过孔V17被配置为使后续形成的第九连接电极通过该过孔孔使相邻的第二初始子线42相互连接。
在示例性实施方式中，第十八过孔V18在基底上的正投影位于第一极板71的第一连接块81在基底上的正投影的范围之内，第十八过孔V18内的第四绝缘层、第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第一连接块81的表面，第十八过孔V18被配置为使后续形成的第十连接电极通过该过孔与第一极板71连接。
在示例性实施方式中，第十九过孔V19在基底上的正投影位于第三极板73的第二连接块82在基底上的正投影的范围之内，第十九过孔V19内的第四绝缘层被刻蚀掉，暴露出第二连接块82的表面，第十九过孔V19被配置为使后续形成的第十连接电极通过该过孔与第三极板73连接。
在示例性实施方式中，第四绝缘层的材料可以采用SiO，第四绝缘层的厚度可以约为500nm至600nm。例如，第二绝缘层的厚度可以约为550nm左右。
(16)形成第三导电层图案。在示例性实施方式中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对 第三导电薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，如图12A和图12B所示，图12B为图12A中第三导电层的平面示意图。在示例性实施方式中，第三导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，第三导电层可以至少包括：第一连接电极51、第二连接电极52、第三连接电极53、第四连接电极54、第五连接电极55、第六连接电极56、第七连接电极57、第八连接电极58、第九连接电极59和第十连接电极60。
在示例性实施方式中，第一连接电极51的形状可以为主体部分沿着第二方向Y延伸的折线状，第一连接电极51的第一端通过第十一过孔V11与第三极板73连接，第一连接电极51的第二端通过第二过孔V2与第一有源层的第二区(也是第二有源层的第一区)连接，使第一晶体管T1的第二极、第二晶体管T2的第一极和第三极板73(也是第三晶体管T3的顶栅电极)具有相同的电位。在示例性实施方式中，第一连接电极51可以作为像素驱动电路的第一节点N1。
在示例性实施方式中，第二连接电极52的形状可以为多边形状，第二连接电极52通过第三过孔V3与第五有源层的第一区连接。在示例性实施方式中，第二连接电极52被配置为与后续形成的第一电源线连接。
在示例性实施方式中，第三连接电极53的形状可以为主体部分沿着第二方向Y延伸的条形状，第三连接电极53的第一端通过第四过孔V4与第五有源层的第二区连接，第三连接电极53的第二端通过第五过孔V5与第二有源层的第二区连接。在示例性实施方式中，第三连接电极53可以作为像素驱动电路的第二节点N2。
在示例性实施方式中，第四连接电极54的形状可以为主体部分沿着第二方向Y延伸的条形状，第四连接电极54通过第六过孔V6与第四有源层的第一区连接。在示例性实施方式中，第四连接电极54可以作为第四晶体管T4的第一极(称为数据输入电极)，第四连接电极54被配置为与后续形成的数据信号线连接。
在示例性实施方式中，第五连接电极55的形状可以为主体部分沿着第二方向Y延伸的折线状，第五连接电极55的第一端通过第七过孔V7与第四有 源层的第二区(也是第三有源层的第二区)连接，第五连接电极55的第二端通过第八过孔V8与第六有源层的第一区连接。在示例性实施方式中，第五连接电极55可以作为像素驱动电路的第三节点N3。
在示例性实施方式中，第六连接电极56的形状可以为多边形状，第六连接电极56通过第九过孔V9与第六有源层的第二区(也是第七有源层的第二区)连接。在示例性实施方式中，第六连接电极56被配置为与后续形成的阳极连接电极连接。
在示例性实施方式中，第七连接电极57的形状可以为多边形状，第七连接电极57通过第一过孔V1与第二极板72连接。在示例性实施方式中，第七连接电极57可以作为像素驱动电路的第四节点N4，被配置为通过后续形成的阳极连接电极与第六连接电极56连接。
在示例性实施方式中，第八连接电极58的形状可以为主体部分沿着第一方向X延伸的条形状，第八连接电极58的中部通过第十二过孔V12与第一有源层的第一区连接，第八连接电极58的两端分别通过第十四过孔V14和第十五过孔V15与位于第一有源层的第一区两侧的第一初始子线41连接，一方面实现了相邻的第一初始子线41之间的连接，形成第一初始信号线，另一方面实现了第一初始信号线与第一晶体管T1的第一极的连接，使第一初始信号线传输的第一初始电压写入第一晶体管T1的第一极。
在示例性实施方式中，第九连接电极59的形状可以为主体部分沿着第一方向X延伸的条形状，第九连接电极59的中部通过第十三过孔V13与第七有源层的第一区连接，第九连接电极59的两端分别通过第十六过孔V16和第十七过孔V17与位于第七有源层的第一区两侧的第二初始子线42连接，一方面实现了相邻的第二初始子线42之间的连接，形成第二初始信号线，另一方面实现了第二初始信号线与第七晶体管T7的第一极的连接，使第二初始信号线传输的第二初始电压写入第七晶体管T7的第一极。
在示例性实施方式中，第十连接电极60的形状可以为主体部分沿着第二方向Y延伸的条形状，第十连接电极60的第一端通过第十八过孔V18与第一极板71的第一连接块81连接，第十连接电极60的第二端通过第十九过孔V19与第三极板73的第二连接块82连接，实现了第一极板71与第三极板 73的相互连接，使得第一极板71和第三极板73具有相同的电位。
在示例性实施方式中，由于第一极板71与第三极板73通过第十连接电极60相互连接，而第三极板73通过过孔与第一连接电极51连接，第一连接电极51作为像素驱动电路的第一节点N1，因而第一极板71与第三极板73具有像素驱动电路的第一节点N1的电位。由于第二极板72通过过孔与第七连接电极57连接，而第七连接电极57作为像素驱动电路的第四节点N4，因而第二极板72具有像素驱动电路的第四节点N4的电位。这样，第一极板71、第二极板72和第三极板73构成并联结构的存储电容，具有第一节点N1电位的第一极板71与具有第四节点N4电位的第二极板72构成第一存储电容，具有第一节点N1电位的第三极板73与具有第四节点N4电位的第二极板72构成第二存储电容，第一存储电容和第二存储电容为并联结构。
在示例性实施方式中，第三导电层可以采用多层复合结构，如Ti(钛)/Al(铝)/Ti(钛)等，第三导电层的厚度可以约为600nm至700nm。例如，第三导电层中两个Ti层的厚度可以分别约为50nm左右，第三导电层中Al层的厚度可以约为550nm左右，第三导电层的总厚度可以约为650nm左右。
(17)形成第一平坦层图案。在示例性实施方式中，形成第一平坦层图案可以包括：在形成前述图案的基底上，先沉积第五绝缘薄膜，然后涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜和第五绝缘薄膜进行图案化，形成覆盖第三导电层图案的第五绝缘层以及设置在第五绝缘层上的第一平坦层，第一平坦层上设置有多个过孔，如图13所示。
在示例性实施方式中，第五绝缘层和第一平坦层上多个过孔可以至少包括第二十一过孔V21、第二十二过孔V22、第二十三过孔V23、第二十四过孔V24和第二十五过孔V25。
在示例性实施方式中，第二十一过孔V21在基底上的正投影位于第二连接电极52在基底上的正投影的范围之内，第二十一过孔V21内的第一平坦层和第五绝缘层被刻蚀掉，暴露出第二连接电极52的表面，第二十一过孔V21被配置为使后续形成的第一电源线通过该过孔与第二连接电极52连接。
在示例性实施方式中，第二十二过孔V22在基底上的正投影位于第四连接电极54在基底上的正投影的范围之内，第二十二过孔V22内的第一平坦 层和第五绝缘层被刻蚀掉，暴露出第四连接电极54的表面，第二十二过孔V22被配置为使后续形成的数据信号线通过该过孔与第四连接电极54连接。
在示例性实施方式中，第二十三过孔V23在基底上的正投影位于第六连接电极56在基底上的正投影的范围之内，第二十三过孔V23内的第一平坦层和第五绝缘层被刻蚀掉，暴露出第六连接电极56的表面，第二十三过孔V23被配置为使后续形成的阳极连接电极通过该过孔与第六连接电极56连接。
在示例性实施方式中，第二十四过孔V24在基底上的正投影位于第七连接电极57在基底上的正投影的范围之内，第二十四过孔V24内的第一平坦层和第五绝缘层被刻蚀掉，暴露出第七连接电极57的表面，第二十四过孔V24被配置为使后续形成的阳极连接电极通过该过孔与第七连接电极57连接。
在示例性实施方式中，第二十五过孔V25在基底上的正投影位于第九连接电极59在基底上的正投影的范围之内，第二十五过孔V25内的第一平坦层和第五绝缘层被刻蚀掉，暴露出第九连接电极59的表面，第二十五过孔V25被配置为使后续形成的初始连接线通过该过孔与第九连接电极59连接。
在示例性实施方式中，第五绝缘层可以称为钝化(PVX)层，第五绝缘层的材料可以采用可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。例如，第五绝缘层可以采用SiO/SiNx，第五绝缘层的厚度可以约为200nm至400nm。例如，第五绝缘层中SiO的厚度可以约为200nm左右，第五绝缘层中SiNx的厚度可以约为100nm左右，第五绝缘层的总厚度可以约为300nm左右。
在示例性实施方式中，第一平坦层可以采用有机材料，如树脂或聚酰亚胺等，第一平坦层的厚度可以约为1000nm至2000nm。例如，第一平坦层的厚度可以约为1500nm左右。
(18)形成第四导电层图案。在示例性实施方式中，形成第四导电层可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第一平坦层上的第四导电层，如图14A和图14B所示，图14B为图14A中第四导电层的平面示意图。在示例性实 施方式中，第四导电层可以称为第二源漏金属(SD2)层。
在示例性实施方式中，第四导电层可以至少包括：阳极连接电极61、第一电源线62、数据信号线63和初始连接线64。
在示例性实施方式中，阳极连接电极61的形状可以为主体部分沿着第二方向Y延伸的折线状，阳极连接电极61的第一端通过第二十三过孔V23与第六连接电极56连接，阳极连接电极61的第二端通过第二十四过孔V24与第七连接电极57连接。由于第六连接电极56通过过孔与第六有源层的第二区(也是第七有源层的第二区)连接，第七连接电极57通过过孔与第二极板72连接，因而实现了第二极板72、第六晶体管T6的第二极和第七晶体管T7的第二极具有相同的电位，即像素驱动电路中第四节点N4的电位，阳极连接电极61可以称为第四节点连接线。在示例性实施方式中，阳极连接电极61被配置为与后续形成的阳极连接，因而可以实现像素驱动电路向发光器件输出驱动电流。
在示例性实施方式中，阳极连接电极61在基底上的正投影可以与第二扫描信号线32在基底上的正投影至少部分交叠，阳极连接电极61在基底上的正投影可以与发光控制线35在基底上的正投影至少部分交叠。
在示例性实施方式中，第一电源线62的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状，第一电源线62通过第二十一过孔V21与第二连接电极52连接。由于第二连接电极52通过过孔与第五有源层的第一区连接，因而实现了第一电源线62可以将第一电源信号写入第五晶体管T5的第一极。
在示例性实施方式中，第一电源线62在基底上的正投影可以分别与第一连接电极51和第三连接电极53在基底上的正投影至少部分交叠，使得第一电源线62可以作为屏蔽电极，可以有效屏蔽数据电压跳变对像素驱动电路中关键节点的影响，避免了数据电压跳变影响像素驱动电路的关键节点的电位，提高了显示效果。
在示例性实施方式中，数据信号线63的形状可以为主体部分沿着第二方向Y延伸的直线状，数据信号线63通过第二十二过孔V22与第四连接电极54连接。由于第四连接电极54通过过孔与第四有源层的第一区连接，因而 实现了数据信号线63与第四晶体管T4的第一极的连接，数据信号线63可以将数据信号写入第四晶体管T4的第一极。
在示例性实施方式中，初始连接线64的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状，初始连接线64通过第二十五过孔V25与第九连接电极59连接。由于第二初始子线42和第九连接电极59构成传输第二初始信号的第二初始信号线，初始连接线64与第九连接电极59连接，使得沿着第一方向X延伸的第二初始信号线和沿着第二方向Y延伸的初始连接线64在显示区域构成网络连通结构的初始连接线，可以最大限度地降低了初始信号线的电阻，减小了初始电压的压降，而且有效提升了显示基板中初始电压的均一性，有效提升了显示均一性，提高了显示品质和显示质量。
在示例性实施方式中，初始连接线64、第九连接电极59和第二初始子线42分别设置在不同的导电层中，初始连接线64通过过孔与第九连接电极59连接，第九连接电极59通过过孔与第二初始子线42连接。
在示例性实施方式中，第四导电层可以采用多层复合结构，如Ti/Al/Ti等，第三导电层的厚度可以约为600nm至700nm。例如，第四导电层中两个Ti层的厚度可以分别约为50nm和30nm左右，第三导电层中Al层的厚度可以约为550nm左右，第三导电层的总厚度可以约为630nm左右。
图14C为本公开一种显示基板形成另一种第四导电层图案后的示意图，图14D为图14C中第四导电层的平面示意图。在示例性实施方式中，本实施例第四导电层中阳极连接电极61、第一电源线62、数据信号线63和初始连接线64的结构与如图14A和图14B所示结构基本上相同，所不同的是，阳极连接电极61上设置有第一凸块61-1。
在示例性实施方式中，第一凸块61-1的形状可以为多边形状，可以设置在阳极连接电极61第一方向X的一侧和/或第一方向X的反方向的一侧，且与阳极连接电极61连接。
在示例性实施方式中，第一凸块61-1在基底上的正投影可以与发光控制线35在基底上的正投影至少部分交叠，第一凸块61-1被配置为增加阳极连接电极61与发光控制线35之间的第一耦合电容，在发光控制线35输出高 电平导通信号时，高电平导通信号通过第一耦合电容可以拉高像素驱动电路中第四节点N4的电位，有利于亮态显示。
图14E为本公开一种显示基板形成又一种第四导电层图案后的示意图，图14F为图14E中第四导电层的平面示意图。在示例性实施方式中，本实施例第四导电层中阳极连接电极61、第一电源线62、数据信号线63和初始连接线64的结构与如图14A和图14B所示结构基本上相同，所不同的是，阳极连接电极61上设置有第二凸块61-2。
在示例性实施方式中，第二凸块61-2的形状可以为多边形状，可以设置在阳极连接电极61第一方向X的一侧和/或第一方向X的反方向的一侧，且与阳极连接电极61连接。
在示例性实施方式中，第二凸块61-2在基底上的正投影可以与第二扫描信号线32在基底上的正投影至少部分交叠，第二凸块61-2被配置为增加阳极连接电极61与第二扫描信号线32之间的第二耦合电容，在第二扫描信号线32输出低电平关断信号时，低电平关断信号通过第二耦合电容可以拉低像素驱动电路中第四节点N4的电位，有利于暗态显示。
在示例性实施方式中，可以将图14C和图14E的方案结合起来，即阳极连接电极61上分别设置有第一凸块61-1和第二凸块61-2，第一凸块61-1在基底上的正投影可以与发光控制线35在基底上的正投影至少部分交叠，第二凸块61-2在基底上的正投影可以与第二扫描信号线32在基底上的正投影至少部分交叠。
在示例性实施方式中，阳极连接电极61和第一凸块61-1在基底上的正投影与发光控制线35在基底上的正投影可以具有第一重叠面积，阳极连接电极61和第二凸块61-2在基底上的正投影与第二扫描信号线32在基底上的正投影可以具有第二重叠面积，第一重叠面积和第二重叠面积可以基本上相等，可以在一定程度上调节第一耦合电容和第二耦合电容的影响。
图14G为本公开一种显示基板形成又一种第四导电层图案后的示意图，图14H为图14G中第四导电层的平面示意图。在示例性实施方式中，本实施例第四导电层中阳极连接电极61、数据信号线63和初始连接线64的结构 与如图14A和图14B所示结构基本上相同，所不同的是，第一电源线62上设置有避让结构62-1。
在示例性实施方式中，避让结构62-1可以位于第三连接电极53所在区域。避让结构62-1的形状可以是“C”字形状，使得第一电源线62向着远离阳极连接电极61的方向弯折。
在示例性实施方式中，由于第三连接电极53作为像素驱动电路的第二节点N2，第一电源线62与第三连接电极53之间交叠会导致第二节点N2的寄生电容，因而避让结构62-1可以减小第一电源线62与第三连接电极53之间的交叠面积，降低像素驱动电路中第二节点N2的寄生电容。
在示例性实施方式中，由于避让结构62-1使得第一电源线62向着远离阳极连接电极61的方向弯折，因而可以在第一电源线62和阳极连接电极61之间留出较大的空间，有利于设置第一凸块61-1和/或第二凸块61-2，有利于像素驱动电路中第四节点N4的耦合电容设计。
在示例性实施方式中，可以根据实际情况，将图14A、图14C、图14E和图14G的方案任意组合，本公开在此不做限定。
随后，在形成前述图案的基底上，涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成覆盖第四导电层图案的第二平坦层，第二平坦层上设置有阳极过孔，阳极过孔在基底上的正投影位于阳极连接电极61在基底上的正投影的范围之内，阳极过孔被配置为使后续形成的阳极通过该过孔与阳极连接电极61连接。
在示例性实施方式中，第二平坦层可以采用有机材料，如树脂或聚酰亚胺等，第二平坦层的厚度可以约为1000nm至2000nm。例如，第二平坦层的厚度可以约为1500nm左右。
至此，在基底上制备完成驱动电路层。在平行于显示基板的平面内，驱动电路层可以包括多个电路单元，每个电路单元可以包括像素驱动电路，以及与像素驱动电路连接的第一扫描信号线、第二扫描信号线、第三扫描信号线、第四扫描信号线、发光控制线、第一初始信号线和第二初始信号线、第一电源线和数据信号线。在垂直于显示基板的平面内，所述驱动电路层可以 包括在基底上依次设置的遮挡导电层、第一绝缘层、第一导电层、第二绝缘层、半导体层、第三绝缘层、第二导电层、第四绝缘层、第三导电层、第五绝缘层、第一平坦层、第四导电层和第二平坦层。遮挡导电层可以至少包括存储电容的第一极板，第一导电层可以至少包括存储电容的第二极板和多条遮挡线，半导体层可以至少包括第一晶体管至第七晶体管的有源层，第二导电层可以至少包括存储电容的第三极板、多条扫描信号线、发光控制线、第一初始子线和第二初始子线，第三导电层可以至少包括多个连接电极，第四导电层可以至少包括阳极连接电极、第一电源线和数据信号线。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性基底可以包括但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施方式中，制备完成驱动电路层后，可以在驱动电路层上制备发光结构层，在发光结构层上制备封装结构层，这里不再赘述。
从以上描述的显示基板的结构以及制备过程可以看出，本公开示例性实施例存储电容的第一极板、第二极板和第三极板分别位于遮挡导电层、第一导电层和第二导电层，第一极板和第二极板形成第一存储电容，第二极板和第三极板形成第二存储电容，第一存储电容和第二存储电容构成并联结构的存储电容。本公开第一极板和第二极板之间的电容绝缘层采用硅氮化物，可以确保电容性能。本公开多个晶体管的底栅电极设置在第一导电层，多个晶体管的顶栅电极设置在第二导电层，可以有效保证对氧化物晶体管的遮挡，可以提高晶体管的电学性能。本公开的制备工艺可以很好地与现有制备工艺 兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
研究发现，硅氮化物的氢(H)含量较多，氢元素入侵半导体层会导致氧化物薄膜晶体管特性负偏以及负偏置温度应力(NBTS)信赖性恶化，导致显示基板的工艺调试难度较大。本公开通过将采用硅氮化物的第一绝缘层(电容绝缘层)设置在半导体层靠近基底的一侧，即第一极板和第二极板之间的电容绝缘层没有位于半导体层和第三导电层之间，且半导体层与第一绝缘层之间还间隔有第二绝缘层，因而可以阻挡第一绝缘层中氢元素的渗透，从而避免了氢元素对氧化物薄膜晶体管的特性的影响，提升氧化物薄膜晶体管的特性稳定性。
图15为本公开示例性实施例另一种显示基板的平面结构示意图，示意了一个电路单元中像素驱动电路的结构，图16A为图15中C-C向的剖面示意图，图16B为图15中D-D向的剖面示意图，图16C为图15所示像素驱动电路的等效电路图。在示例性实施方式中，在垂直于显示基板的方向上，显示基板可以包括设置在基底上的驱动电路层、设置在驱动电路层远离基底一侧的发光结构层以及设置在发光结构层远离基底一侧的封装结构层。在平行于显示基板的方向上，驱动电路层可以包括构成多个单元行和多个单元列的电路单元，至少一个电路单元包括像素驱动电路，像素驱动电路可以包括存储电容、第一晶体管T1至第七晶体管T7，第一晶体管T1至第七晶体管T7为氧化物晶体管。
如图15、图16A和图16B所示，在示例性实施方式中，驱动电路层可以至少包括：设置在基底10上的遮挡导电层，设置在遮挡导电层远离基底一侧的第一绝缘层91，设置在第一绝缘层91远离基底一侧的半导体层，设置在半导体层远离基底一侧的第二绝缘层92，设置在第二绝缘层92远离基底一侧的第一导电层，设置在第一导电层远离基底一侧的第四绝缘层94，设置在第四绝缘层94远离基底一侧的第三导电层，设置在第三导电层远离基底一侧的第五绝缘层95和第一平坦层96，设置在第一平坦层96远离基底一侧的第四导电层。
在示例性实施方式中，在示例性实施方式中，遮挡导电层可以至少包括遮挡电极16和多条遮挡线，半导体层可以至少包括第一晶体管T1的有源层 至第七晶体管T7的有源层，第一导电层可以至少包括多条扫描信号线和第三栅电极44，第三导电层可以至少包括存储电容的第四极板74和多个连接电极，第四导电层可以至少包括阳极连接电极61、数据信号线63和存储电容的第五极板75，第四极板74在基底上的正投影与第五极板75在基底上的正投影至少部分交叠，第四极板74和第五极板75构成存储电容。
在示例性实施方式中，第一平坦层96上设置有平坦凹槽96-1，平坦凹槽96-1内的第一平坦层被去掉，暴露出第五绝缘层95。第五极板75可以设置在平坦凹槽96-1内的第五绝缘层95上，平坦凹槽96-1在基底上的正投影包含第四极板74和第五极板75在基底上的正投影，因而第四极板74和第五极板75之间仅设置有第五绝缘层，第五绝缘层95作为第四极板74和第五极板75之间的电容绝缘层。
在示例性实施方式中，第一晶体管T1至第七晶体管T7可以均包括底栅电极和顶栅电极，底栅电极可以设置在遮挡导电层中，顶栅电极可以设置在第一导电层中。例如，以第三晶体管T3为例，第一导电层中的第三栅电极44可以作为第三晶体管T3的顶栅电极，与像素驱动电路的第一节点N1连接，遮挡导电层中的遮挡电极16可以作为第三晶体管T3的底栅电极，实现对第三晶体管T3的遮挡，且与像素驱动电路的第三节点N3连接，如图16C所示。
在示例性实施方式中，第一导电层还可以包括第一初始子线41和第二初始子线42，第三导电层的多个连接电极可以至少包括：第一连接电极51、第二连接电极52、第三连接电极53、第四连接电极54、第五连接电极55、第六连接电极56、第八连接电极58和第九连接电极59。本实施例第二连接电极52、第三连接电极53、第四连接电极54、第六连接电极56、第八连接电极58和第九连接电极59的连接结构与前述实施例基本上相同。
在示例性实施方式中，第一连接电极51可以作为像素驱动电路的第一节点电极(N1节点电极)，第一连接电极51的第一端与第四极板74连接，第一连接电极51的第二端通过过孔与第一有源层的第二区(也是第二有源层的第一区)连接。由于第四极板74通过过孔与第三栅电极44连接，因而实现了第一晶体管T1的第二极、第二晶体管T2的第一极、第三栅电极44(第 三晶体管T3的顶栅电极)和存储电容的第四极板74具有相同的电位。
在示例性实施方式中，第五连接电极55可以作为像素驱动电路的第三节点电极(N3节点电极)。第五连接电极55的第一端通过过孔与第六有源层的第一区连接，第五连接电极55的第二端通过过孔与遮挡电极16连接，第五连接电极55的中部通过过孔与第四有源层的第二区(也是第三有源层的第二区)连接，因而实现了第三晶体管T3的第二极、第四晶体管T4的第二极、第六晶体管T6的第一极和遮挡电极16(第三晶体管T3的底栅电极)具有相同的电位。
在示例性实施方式中，阳极连接电极61可以作为像素驱动电路的第四节点电极(N4节点电极)，阳极连接电极61的第一端通过过孔与第六连接电极56连接，阳极连接电极61的第二端与第五极板75连接，因而实现了第六晶体管T6的第二极、第七晶体管T7的第二极和存储电容的第五极板75具有相同的电位。
在示例性实施方式中，本示例性实施例显示基板的制备过程可以包括如下操作。
(21)形成遮挡导电层图案。在示例性实施方式中，形成遮挡导电层图案可以包括：在基底上沉积遮挡薄膜，通过图案化工艺对遮挡薄膜进行图案化，在基底上形成遮挡导电层图案，如图17所示。
在示例性实施方式中，遮挡导电层图案可以至少包括：第一遮挡线11、第二遮挡线12、第三遮挡线13、第四遮挡线14、第五遮挡线15和遮挡电极16，第一遮挡线11至第五遮挡线15的结构与前述实施例基本上相同。
在示例性实施方式中，遮挡电极16的形状可以为矩形状，遮挡电极16被配置为对第三晶体管T3进行遮挡，同时作为第三晶体管T3的底栅电极。
在示例性实施方式中，遮挡电极16第一方向X的一侧还连接有第三连接块83，第三连接块83被配置与后续形成的第五连接电极连接。
在示例性实施方式中，遮挡导电层的材料和厚度可以与前述实施例基本上相同。
(22)形成半导体层图案。在示例性实施方式中，形成半导体层图案可 以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖遮挡导电层的第一绝缘层，以及设置在第一绝缘层上的半导体层图案，如图18所示。
在示例性实施方式中，半导体层图案可以至少包括第一有源层21、第二有源层22、第三有源层23、第四有源层24、第五有源层25、第六有源层26和第七有源层27，第一有源层21至第七有源层27的结构可以与前述实施例基本上相同，第三有源层23在基底上的正投影与遮挡电极16在基底上的正投影至少部分交叠。
在示例性实施方式中，导体层可以采用电子迁移率较高的氧化铟镓锌(IGZO)，第一绝缘层的材料可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。半导体层和第一绝缘层的厚度可以与前述实施例基本上相同。
(23)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，如图19所示。
在示例性实施方式中，第一导电层图案至少包括：第一扫描信号线31、第二扫描信号线32、第三扫描信号线33、第四扫描信号线34、发光控制线35、第一初始子线41、第二初始子线42和第三栅电极44，第一扫描信号线31至第四扫描信号线34、发光控制线35、第一初始子线41和第二初始子线42的结构可以与前述实施例基本上相同。
在示例性实施方式中，第三栅电极44的轮廓可以为矩形状，矩形状的角部可以设置倒角，第三栅电极44在基底上的正投影与第三有源层23在基底上的正投影至少部分交叠，第三栅电极44被配置为作为第三晶体管T3的顶栅电极。
在示例性实施方式中，第二绝缘层和第一导电层的材料和厚度可以与前述实施例基本上相同。
(24)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图 案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第一导电层的第四绝缘层，第四绝缘层上设置有多个过孔，如图20所示。
在示例性实施方式中，多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十过孔V10、第十二过孔V12、第十三过孔V13、第十四过孔V14、第十五过孔V15、第十六过孔V16和第十七过孔V17，第二过孔V2至第九过孔V9、第十二过孔V12至第十七过孔V17的结构可以与前述实施例基本上相同。
在示例性实施方式中，第一过孔V1在基底上的正投影位于第三栅电极44在基底上的正投影的范围之内，第一过孔V1内的第四绝缘层被刻蚀掉，暴露出第三栅电极44的表面，第一过孔V1配置为使后续形成的第四极板通过该过孔与第三栅电极44连接。
在示例性实施方式中，第十过孔V10在基底上的正投影位于遮挡电极16的第三连接块83在基底上的正投影的范围之内，第十过孔V10内的第四绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第三连接块83的表面，第十过孔V10配置为使后续形成的第五连接电极55通过该过孔与遮挡电极16连接。
在示例性实施方式中，第四绝缘层的材料和厚度可以与前述实施例基本上相同。
(25)形成第三导电层图案。在示例性实施方式中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，如图21所示。
在示例性实施方式中，第三导电层至少包括：第一连接电极51、第二连接电极52、第三连接电极53、第四连接电极54、第五连接电极55、第六连接电极56、第八连接电极58、第九连接电极59和存储电容的第四极板74，第二连接电极52至第六连接电极56、第八连接电极58至第九连接电极59的结构可以与前述实施例基本上相同。
在示例性实施方式中，第四极板74的形状可以为矩形状，第四极板74在基底上的正投影与第三栅电极44在基底上的正投影至少部分交叠，第四极板74通过第一过孔V1与第三栅电极44连接，第四极板74可以作为存储电容的一个极板。
在示例性实施方式中，第四极板74在基底上的正投影面积与第三栅电极44在基底上的正投影面积之比可以大于50％。例如，第四极板74在基底上的正投影面积与第三栅电极44在基底上的正投影面积之比可以约为60％左右，或者可以约为70％左右，或者可以约为80％左右，或者可以约为90％左右。
在示例性实施方式中，第四极板74可以至少包括：在基底上的正投影与第三栅电极44在基底上的正投影重叠的重叠区域，以及在基底上的正投影与第三栅电极44在基底上的正投影没有重叠的非重叠区域，重叠区域的宽度可以大于非重叠区域的宽度，宽度可以是第四极板74第一方向X的尺寸。
在示例性实施方式中，第一连接电极51可以作为像素驱动电路的第一节点电极(N1节点电极)。第一连接电极51的形状可以为沿着第一方向X延伸的条形状，第一连接电极51的第一端与第四极板74直接连接，第一连接电极51的第二端通过第二过孔V2与第一有源层的第二区(也是第二有源层的第一区)连接。由于第四极板74通过过孔与第三栅电极44连接，因而实现了第一晶体管T1的第二极、第二晶体管T2的第一极、第三栅电极44(第三晶体管T3的顶栅电极)和存储电容的第四极板74具有相同的电位。
在示例性实施方式中，第一连接电极51和存储电容的第四极板74可以为相互连接的一体结构。
在示例性实施方式中，第五连接电极55可以作为像素驱动电路的第三节点电极(N3节点电极)。第五连接电极55的形状可以为主体部分沿着第二方向Y延伸的折线状，第五连接电极55的第一端通过第八过孔V8与第六有源层的第一区连接，第五连接电极55的第二端通过第十过孔V10与遮挡电极16的第三连接块83连接，第五连接电极55中位于第一端与第二端之间的中部通过第七过孔V7与第四有源层的第二区(也是第三有源层的第二区)连接，因而实现了第三晶体管T3的第二极、第四晶体管T4的第二极、第六 晶体管T6的第一极和遮挡电极16(第三晶体管T3的底栅电极)具有相同的电位。
在示例性实施方式中，遮挡电极16作为第三晶体管T3的底栅电极，具有像素驱动电路的第三节点N3的电位，第三栅电极44作为第三晶体管T3的顶栅电极，具有像素驱动电路的第一节点N1的电位，第三栅电极44在基底上的正投影与遮挡电极16在基底上的正投影至少部分交叠。在第六晶体管T6导通的发光阶段，由于第三节点N3的电位和第四节点N4的电位相同，因而遮挡导电层的遮挡电极16和第一导电层的第三栅电极44可以形成像素驱动电路的辅助存储电容。
在示例性实施方式中，第三导电层的材料和厚度可以与前述实施例基本上相同。
(26)形成第一平坦层图案。在示例性实施方式中，形成第一平坦层图案可以包括：在形成前述图案的基底上，先沉积第五绝缘薄膜，然后涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜和第五绝缘薄膜进行图案化，形成覆盖第三导电层图案的第五绝缘层以及设置在第五绝缘层上的第一平坦层，第一平坦层上设置有平坦凹槽和多个过孔，如图22所示。
在示例性实施方式中，多个过孔至少包括：第二十一过孔V21、第二十二过孔V22、第二十三过孔V23和第二十五过孔V25，上述过孔的结构可以与前述实施例基本上相同。
在示例性实施方式中，平坦凹槽96-1可以开设在第四极板74所在区域，平坦凹槽96-1内的第一平坦层被去掉，暴露出覆盖第四极板74的第五绝缘层，平坦凹槽96-1在基底上的正投影包含第四极板74在基底上的正投影。平坦凹槽96-1被配置为容置后续形成的第五极板，使第四极板74与第五极板之间仅设置有第五绝缘层，以增加存储电容的容量。
在示例性实施方式中，第五绝缘层为设置在第四极板和第五极板之间的电容绝缘层，可以称为钝化(PVX)层，第五绝缘层的材料可以采用SiNx，第五绝缘层的厚度可以约为200nm至300nm。例如，第五绝缘层的厚度可以约为250nm左右。
在示例性实施方式中，第一平坦层的材料和厚度可以与前述实施例基本 上相同。
(27)形成第四导电层图案。在示例性实施方式中，形成第四导电层可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第一平坦层上的第四导电层，如图23所示。
在示例性实施方式中，第四导电层至少包括：阳极连接电极61、第一电源线62、数据信号线63和初始连接线64和存储电容的第五极板75。
在示例性实施方式中，阳极连接电极61的形状可以为主体部分沿着第二方向Y延伸的折线状，阳极连接电极61的第一端通过第二十三过孔V23与第六连接电极56连接，阳极连接电极61的第二端与第五极板75连接。
在示例性实施方式中，阳极连接电极61上可以设置有第一凸块，或者可以设置有第二凸块，或者可以设置有第一凸块和第二凸块，本公开在此不做限定。
在示例性实施方式中，第五极板75的形状可以为矩形状，设置在平坦凹槽96-1内，第五极板75在基底上的正投影与第四极板74在基底上的正投影至少部分交叠，第五极板75可以作为存储电容的另一个极板，第四极板74和第五极板75构成像素驱动电路的存储电容。
在示例性实施方式中，第五极板75在基底上的正投影与第三栅电极44在基底上的正投影至少部分交叠。第五极板75在基底上的正投影面积与第三栅电极44在基底上的正投影面积之比可以大于50％。例如，第五极板75在基底上的正投影面积与第三栅电极44在基底上的正投影面积之比可以约为60％左右，或者可以约为70％左右，或者可以约为80％左右，或者可以约为90％左右。
在示例性实施方式中，第五极板75可以至少包括：在基底上的正投影与第三栅电极44在基底上的正投影重叠的重叠区域，以及在基底上的正投影与第三栅电极44在基底上的正投影没有重叠的非重叠区域，重叠区域的宽度可以大于非重叠区域的宽度，宽度可以是第五极板75第一方向X的尺寸。
在示例性实施方式中，阳极连接电极61和第五极板75可以为相互连接 的一体结构。由于第六连接电极56通过过孔与第六有源层的第二区(也是第七有源层的第二区)连接，因而实现了第五极板75、第六晶体管T6的第二极和第七晶体管T7的第二极具有相同的电位，即像素驱动电路的第四节点N4的电位。
在示例性实施方式中，第一电源线62、数据信号线63和初始连接线64的结构可以与前述实施例可以基本上相同，或者，第一电源线62和/或初始连接线64上可以设置有避让结构，避让结构使得第一电源线62和/或初始连接线64向着远离第五极板75的方向弯折，为设置第五极板75留出相应的空间。
在示例性实施方式中，第四导电层的材料和厚度可以与前述实施例基本上相同。
随后，在形成前述图案的基底上，涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成覆盖第四导电层图案的第二平坦层，第二平坦层上设置有阳极过孔，阳极过孔在基底上的正投影位于阳极连接电极在基底上的正投影的范围之内，阳极过孔被配置为使后续形成的阳极通过该过孔与阳极连接电极连接。在示例性实施方式中，第二平坦层的材料和厚度可以与前述实施例基本上相同。
至此，在基底上制备完成驱动电路层。在平行于显示基板的平面内，驱动电路层可以包括多个电路单元，每个电路单元可以包括像素驱动电路，以及与像素驱动电路连接的第一扫描信号线、第二扫描信号线、第三扫描信号线、第四扫描信号线、发光控制线、第一初始信号线和第二初始信号线、第一电源线和数据信号线。在垂直于显示基板的平面内，所述驱动电路层可以包括在基底上依次设置的遮挡导电层、第一绝缘层、半导体层、第二绝缘层、第一导电层、第四绝缘层、第三导电层、第五绝缘层、第一平坦层、第四导电层和第二平坦层。遮挡导电层可以至少包括遮挡电极和多条遮挡线，半导体层可以至少包括第一晶体管至第七晶体管的有源层，第一导电层可以至少包括多条扫描信号线和第三栅电极，第三导电层可以至少包括存储电容的第四极板和多个连接电极，第四导电层可以至少包括存储电容的第五极板、阳极连接电极、第一电源线和数据信号线，第四极板在基底上的正投影与第五 极板在基底上的正投影至少部分交叠，第四极板和第五极板构成存储电容。
本公开示例性实施例存储电容的第四极板和第五极板分别设置在第三导电层和第四导电层，且第四极板和第五极板之间的电容绝缘层采用硅氮化物，可以确保电容性能。本公开通过将采用硅氮化物的第五绝缘层(电容绝缘层)设置在第三导电层远离基底的一侧，即第四极板和第五极板之间的电容绝缘层没有位于半导体层和第三导电层之间，因而可以避免第五绝缘层中氢元素的渗透，从而避免了氢元素对氧化物薄膜晶体管的特性的影响，提升氧化物薄膜晶体管的特性稳定性。本公开多个晶体管的底栅电极设置在遮挡导电层，多个晶体管的顶栅电极设置在第一导电层，可以有效保证对氧化物晶体管的遮挡，可以提高晶体管的电学性能。本公开取消了第三绝缘层和第二导电层，不仅减少了一次图案化工艺，而且可以规避采用SiNx的第三绝缘层中氢(H)元素的渗透，从而避免了氢元素对氧化物薄膜晶体管的特性的影响，提升氧化物薄膜晶体管的特性稳定性。本公开的制备工艺可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
图24为本公开示例性实施例又一种显示基板的平面结构示意图，示意了一个电路单元中像素驱动电路的结构，图25A为图24中E-E向的剖面示意图，图25B为图24中F-F向的剖面示意图，图25C为图24所示像素驱动电路的等效电路图。在示例性实施方式中，在垂直于显示基板的方向上，显示基板可以包括设置在基底上的驱动电路层、设置在驱动电路层远离基底一侧的发光结构层以及设置在发光结构层远离基底一侧的封装结构层。在平行于显示基板的方向上，驱动电路层可以包括构成多个单元行和多个单元列的电路单元，至少一个电路单元包括像素驱动电路，像素驱动电路可以包括存储电容、第一晶体管T1至第七晶体管T7，第一晶体管T1至第七晶体管T7为氧化物晶体管。
如图24、图25A和图25B所示，在示例性实施方式中，驱动电路层可以至少包括：设置在基底10上的遮挡导电层，设置在遮挡导电层远离基底一侧的第一绝缘层91，设置在第一绝缘层91远离基底一侧的半导体层，设置在半导体层远离基底一侧的第二绝缘层92，设置在第二绝缘层92远离基底 一侧的第一导电层，设置在第一导电层远离基底一侧的第三绝缘层93，设置在第三绝缘层93远离基底一侧的第二导电层，设置在第二导电层远离基底一侧的第四绝缘层94，设置在第四绝缘层94远离基底一侧的第三导电层。
在示例性实施方式中，遮挡导电层可以至少包括遮挡电极16和多条遮挡线，半导体层可以至少包括第一晶体管的有源层至第七晶体管的有源层，第一导电层可以至少包括存储电容的第七极板77和多条扫描信号线，第二导电层可以至少包括存储电容的第八极板78，第三导电层可以至少包括多个连接电极。
在示例性实施方式中，存储电容的第七极板77可以设置在第一导电层中，存储电容的第八极板78可以设置在第二导电层中，第七极板77在基底上的正投影与第八极板78在基底上的正投影至少部分交叠，第三绝缘层93为设置在第七极板77和第八极板78之间的电容绝缘层。
在示例性实施方式中，第一晶体管T1至第七晶体管T7可以均包括底栅电极和顶栅电极，底栅电极可以设置在遮挡导电层中，顶栅电极可以设置在第一导电层中。例如，以第三晶体管T3为例，第一导电层中的第七极板77可以作为第三晶体管T3的顶栅电极，即第三晶体管T3的顶栅电极和第七极板77为相互连接的一体结构。遮挡导电层中的遮挡电极16可以作为第三晶体管T3的底栅电极，实现对第三晶体管T3的遮挡，且与像素驱动电路的第三节点N3连接，如图25C所示。
在示例性实施方式中，第三导电层可以至少包括：第一连接电极51、第二连接电极52、第三连接电极53、第四连接电极54、第五连接电极55、第六连接电极56和第七连接电极57。
在示例性实施方式中，第一连接电极51可以作为像素驱动电路的第一节点电极(N1节点电极)，第一连接电极51的第一端通过过孔与第七极板77连接，第一连接电极51的第二端通过过孔与第一有源层的第二区(也是第二有源层的第一区)连接，因而实现了存储电容的第七极板77、第一晶体管T1的第二极和第二晶体管T2的第一极具有相同的电位。
在示例性实施方式中，第二连接电极52可以通过过孔与第五有源层的第一区连接，由于第二连接电极52与第一电源线连接，因而实现了第一电源 线通过第二连接电极52将第一电源电压写入第五晶体管T5的第一极。
在示例性实施方式中，第三连接电极53可以作为像素驱动电路的第二节点电极(N2节点电极)，第三连接电极53的第一端通过过孔与第二有源层的第二区(也是第三有源层的第一区)连接，第三连接电极53的第二端通过过孔与第五有源层的第二区连接，因而实现了第二晶体管T2的第二极、第三晶体管T3的第一极和第五晶体管T5的第二极具有相同的电位。
在示例性实施方式中，第四连接电极54可以作为像素驱动电路的数据输入电极，第四连接电极54通过过孔与第四有源层24的第一区连接，由于第四连接电极54与数据信号线连接，因而实现了数据信号线通过第四连接电极54将数据信号写入第四晶体管T4的第一极。
在示例性实施方式中，第五连接电极55可以作为像素驱动电路的第三节点电极(N3节点电极)，一方面，第五连接电极55通过过孔与第四有源层的第二区(也是第三有源层的第二区)连接，另一方面，第五连接电极55通过过孔与第六有源层的第一区连接，因而实现了第三晶体管T3的第二极、第四晶体管T4的第二极和第六晶体管T6的第一极具有相同的电位。
在示例性实施方式中，第五连接电极55还通过过孔与遮挡电极16连接，因而实现了第三晶体管T3的第二极与第三晶体管T3的底栅电极之间的连接。
在示例性实施方式中，第六连接电极56通过过孔与第六有源层的第二区(也是第七有源层的第二区)连接，因而实现了第六晶体管T6的第二极和第七晶体管T7的第二极具有相同的电位。
在示例性实施方式中，第七连接电极57可以作为像素驱动电路的第四节点电极(N4节点电极)，一方面，第五连接电极55通过过孔与第八极板78连接，另一方面，第五连接电极55通过阳极连接电极与第六连接电极56连接，因而实现了存储电容的第八极板78、第六晶体管T6的第二极和第七晶体管T7的第二极的具有相同的电位。
在示例性实施方式中，第二导电层还可以包括第一初始子线41和第二初始子线42，第三导电层还可以包括第八连接电极58和第九连接电极59， 上述结构可以与前述实施例基本上相同。
在示例性实施方式中，本示例性实施例显示基板的制备过程可以包括如下操作。
(31)形成遮挡导电层图案。在示例性实施方式中，形成遮挡导电层图案可以包括：在基底上沉积遮挡薄膜，通过图案化工艺对遮挡薄膜进行图案化，在基底上形成遮挡导电层图案，如图26所示。
在示例性实施方式中，遮挡导电层图案可以至少包括：第一遮挡线11、第二遮挡线12、第三遮挡线13、第四遮挡线14、第五遮挡线15和遮挡电极16，第一遮挡线11至第五遮挡线15的结构与前述实施例基本上相同。
在示例性实施方式中，遮挡电极16的形状可以为“n”字形，可以位于第一遮挡线11和第二遮挡线12之间，遮挡电极16被配置为对第三晶体管T3进行遮挡，减少光线对第三晶体管T3电学特性的影响，同时被配置作为第三晶体管T3的底栅电极。
在示例性实施方式中，遮挡电极16第一方向X的一侧还连接有第三连接块83，第三连接块83被配置与后续形成的第五连接电极连接。
在示例性实施方式中，遮挡导电层的材料和厚度可以与前述实施例基本上相同。
(32)形成半导体层图案。在示例性实施方式中，形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖遮挡导电层的第一绝缘层，以及设置在第一绝缘层上的半导体层图案，如图27所示。
在示例性实施方式中，半导体层图案可以至少包括第一有源层21、第二有源层22、第三有源层23、第四有源层24、第五有源层25、第六有源层26和第七有源层27，第一有源层21至第七有源层27的结构可以与前述实施例基本上相同，第三有源层23在基底上的正投影与遮挡电极16在基底上的正投影至少部分交叠。
在示例性实施方式中，导体层可以采用电子迁移率较高的氧化铟镓锌(IGZO)，第一绝缘层的材料可以采用硅氧化物(SiOx)、硅氮化物(SiNx) 和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。半导体层和第一绝缘层的厚度可以与前述实施例基本上相同。
(33)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，如图28所示。
在示例性实施方式中，第一导电层图案至少包括：第一扫描信号线31、第二扫描信号线32、第三扫描信号线33、第四扫描信号线34、发光控制线35和存储电容的第七极板77，第一扫描信号线31至第四扫描信号线34、发光控制线35的结构可以与前述实施例基本上相同。
在示例性实施方式中，第七极板77的形状可以为矩形状，矩形状的角部可以设置倒角，第七极板77在基底上的正投影与第三晶体管T3的第三有源层在基底上的正投影至少部分交叠。在示例性实施方式中，第七极板77可以同时作为存储电容的一个极板和第三晶体管T3(驱动晶体管)的顶栅电极。
在示例性实施方式中，第二绝缘层和第一导电层的材料和厚度可以与前述实施例基本上相同。
(34)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，如图29所示。
在示例性实施方式中，每个电路单元的第二导电层图案至少包括：第一初始子线41、第二初始子线42和存储电容的第八极板78，第一初始子线41和第二初始子线42的结构可以与前述实施例基本上相同。
在示例性实施方式中，第八极板78的轮廓可以为矩形状，矩形状的角部可以设置倒角，第八极板78在基底上的正投影与第七极板77在基底上的正投影至少部分交叠，第八极板78可以作为存储电容的另一个极板，第七极板77和第八极板78构成像素驱动电路的存储电容。
在示例性实施方式中，第八极板78上设置有开口43，开口43的形状可以为矩形状，可以位于第八极板78的中部，使第八极板78形成环形结构。开口43暴露出覆盖第七极板77的第三绝缘层，且第七极板77在基底上的正投影包含开口43在基底上的正投影。在示例性实施方式中，开口43被配置为容置后续形成的第一过孔，第一过孔位于开口43内并暴露出第七极板77，使后续形成的第一连接电极与第七极板77连接。
在示例性实施方式中，第三绝缘层为设置在第七极板和第八极板之间的电容绝缘层，可以称为第二栅绝缘(GI2)层，第三绝缘层的材料可以采用SiNx，第三绝缘层的厚度可以约为100nm至170nm。例如，第二绝缘层的厚度可以约为130nm左右。在示例性实施方式中，第二导电层的材料和厚度可以与前述实施例基本上相同。
(55)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层，第四绝缘层上设置有多个过孔，如图30所示。
在示例性实施方式中，多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十过孔V10、第十一过孔V11、第十二过孔V12、第十三过孔V13、第十四过孔V14、第十五过孔V15、第十六过孔V16和第十七过孔V17。
在示例性实施方式中，第一过孔V1在基底上的正投影位于开口43在基底上的正投影的范围之内，第一过孔V1内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第七极板77的表面，第一过孔V1配置为使后续形成的第一连接电极通过该过孔与第七极板77连接。
在示例性实施方式中，第二过孔V2在基底上的正投影位于第一有源层的第二区(也是第二有源层的第一区)在基底上的正投影的范围之内，第二过孔V2内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第二区的表面，第二过孔V2被配置为使后续形成的第一连接电极通过该过孔与第一有源层的第二区(也是第二有源层的第一区)连接。
在示例性实施方式中，第三过孔V3在基底上的正投影位于第五有源层的第一区在基底上的正投影的范围之内，第三过孔V3内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面，第三过孔V3被配置为使后续形成的第二连接电极通过该过孔与第五有源层的第一区连接。
在示例性实施方式中，第四过孔V4在基底上的正投影位于第五有源层的第二区在基底上的正投影的范围之内，第四过孔V4内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第二区的表面，第四过孔V4被配置为使后续形成的第三连接电极通过该过孔与第五有源层的第二区连接。
在示例性实施方式中，第五过孔V5在基底上的正投影位于第二有源层的第二区(也是第三有源层的第一区)在基底上的正投影的范围之内，第五过孔V5内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二有源层的第二区的表面，第五过孔V5被配置为使后续形成的第三连接电极通过该过孔与第二有源层的第二区的第二区(也是第三有源层的第一区)连接。
在示例性实施方式中，第六过孔V6在基底上的正投影位于第四有源层的第一区在基底上的正投影的范围之内，第六过孔V6内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面，第六过孔V6被配置为使后续形成的第四连接电极通过该过孔与第四有源层的第一区连接。
在示例性实施方式中，第七过孔V7在基底上的正投影位于第四有源层的第二区(也是第三有源层的第二区)在基底上的正投影的范围之内，第七过孔V7内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第二区的表面，第七过孔V7被配置为使后续形成的第五连接电极通过该过孔与第四有源层的第二区(也是第三有源层的第二区)连接。
在示例性实施方式中，第八过孔V8在基底上的正投影位于第六有源层的第一区在基底上的正投影的范围之内，第八过孔V8内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第一区的表面，第八 过孔V8被配置为使后续形成的第五连接电极通过该过孔与第六有源层的第一区连接。
在示例性实施方式中，第九过孔V9在基底上的正投影位于第六有源层的第二区(也是第七有源层的第二区)在基底上的正投影的范围之内，第九过孔V9内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第二区的表面，第九过孔V9被配置为使后续形成的第六连接电极通过该过孔与第六有源层的第二区(也是第七有源层的第二区)连接。
在示例性实施方式中，第十过孔V10在基底上的正投影位于遮挡电极16在基底上的正投影的范围之内，第十过孔V10内的第四绝缘层、第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出遮挡电极16的第三连接块83的表面，第十过孔V10被配置为使后续形成的第五连接电极通过该过孔与遮挡电极16连接。
在示例性实施方式中，第十一过孔V11在基底上的正投影位于第八极板78在基底上的正投影的范围之内，第十一过孔V11内的第四绝缘层被刻蚀掉，暴露出第八极板78的表面，第十一过孔V11被配置为使后续形成的第七连接电极通过该过孔与第八极板78连接。
在示例性实施方式中，第十二过孔V12在基底上的正投影位于第一有源层的第一区在基底上的正投影的范围之内，第十二过孔V12内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第一区的表面，第十二过孔V12被配置为使后续形成的第八连接电极通过该过孔与第一有源层的第一区连接。
在示例性实施方式中，第十三过孔V13在基底上的正投影位于第七有源层的第一区在基底上的正投影的范围之内，第十三过孔V13内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第一区的表面，第十三过孔V13被配置为使后续形成的第九连接电极通过该过孔与第七有源层的第一区连接。
在示例性实施方式中，第十四过孔V14和第十五过孔V15在基底上的正投影位于第一初始子线41在基底上的正投影的范围之内，第十四过孔V14和第十五过孔V15内的第四绝缘层被刻蚀掉，暴露出第一初始子线41的表 面，第十四过孔V14和第十五过孔V15被配置为使后续形成的第八连接电极通过该过孔使相邻的第一初始子线41相互连接。
在示例性实施方式中，第十六过孔V16和第十七过孔V17在基底上的正投影位于第二初始子线42在基底上的正投影的范围之内，第十六过孔V16和第十七过孔V17内的第四绝缘层被刻蚀掉，暴露出第二初始子线42的表面，第十六过孔V16和第十七过孔V17被配置为使后续形成的第九连接电极通过该过孔孔使相邻的第二初始子线42相互连接。
在示例性实施方式中，第四绝缘层的材料和厚度可以与前述实施例基本上相同。
(36)形成第三导电层图案。在示例性实施方式中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，如图31所示。
在示例性实施方式中，每个电路单元的第三导电层至少包括：第一连接电极51、第二连接电极52、第三连接电极53、第四连接电极54、第五连接电极55、第六连接电极56、第七连接电极57、第八连接电极58和第九连接电极59。
在示例性实施方式中，第一连接电极51的形状可以为主体部分沿着第二方向Y延伸的折线状，第一连接电极51的第一端通过第一过孔V1与第七极板77连接，第一连接电极51的第二端通过第二过孔V2与第一有源层的第二区(也是第二有源层的第一区)连接，使第七极板77、第一晶体管T1的第二极和第二晶体管T2的第一极具有相同的电位。在示例性实施方式中，第一连接电极51可以作为像素驱动电路的第一节点N1。
在示例性实施方式中，第二连接电极52的形状可以为多边形状，第二连接电极52通过第三过孔V3与第五有源层的第一区连接。在示例性实施方式中，第二连接电极52被配置为与后续形成的第一电源线连接。
在示例性实施方式中，第三连接电极53的形状可以为主体部分沿着第二方向Y延伸的条形状，第三连接电极53的第一端通过第四过孔V4与第五有源层的第二区连接，第三连接电极53的第二端通过第五过孔V5与第二有源 层的第二区连接。在示例性实施方式中，第三连接电极53可以作为像素驱动电路的第二节点N2。
在示例性实施方式中，第四连接电极54的形状可以为主体部分沿着第二方向Y延伸的条形状，第四连接电极54通过第六过孔V6与第四有源层的第一区连接。在示例性实施方式中，第四连接电极54可以作为第四晶体管T4的第一极(称为数据输入电极)，第四连接电极54被配置为与后续形成的数据信号线连接。
在示例性实施方式中，第五连接电极55的形状可以为主体部分沿着第二方向Y延伸的折线状，第五连接电极55的第一端通过第八过孔V8与第六有源层的第一区连接，第五连接电极55的第二端通过第十过孔V10与遮挡电极16的第三连接块83连接，第五连接电极55的第三端通过第七过孔V7与第四有源层的第二区连接，第五连接电极55的第三端位于第一端与第二端之间。在示例性实施方式中，第五连接电极55可以作为像素驱动电路的第三节点N3。
在示例性实施方式中，第六连接电极56的形状可以为多边形状，第六连接电极56通过第九过孔V9与第六有源层的第二区(也是第七有源层的第二区)连接。在示例性实施方式中，第六连接电极56可以作为像素驱动电路的第四节点N4，被配置为与后续形成的阳极连接电极连接。
在示例性实施方式中，第七连接电极57的形状可以为多边形状，第七连接电极57通过第十一过孔V11与第八极板78连接。在示例性实施方式中，第七连接电极57可以作为像素驱动电路的第四节点N4，被配置为与后续形成的阳极连接电极连接。
在示例性实施方式中，第八连接电极58的形状可以为主体部分沿着第一方向X延伸的条形状，第八连接电极58的中部通过第十二过孔V12与第一有源层的第一区连接，第八连接电极58的两端分别通过第十四过孔V14和第十五过孔V15与位于第一有源层的第一区两侧的第一初始子线41连接，一方面实现了相邻的第一初始子线41之间的连接，形成第一初始信号线，另一方面实现了第一初始信号线与第一晶体管T1的第一极的连接，使第一初始信号线传输的第一初始电压写入第一晶体管T1的第一极。
在示例性实施方式中，第九连接电极59的形状可以为主体部分沿着第一方向X延伸的条形状，第九连接电极59的中部通过第十三过孔V13与第七有源层的第一区连接，第九连接电极59的两端分别通过第十六过孔V16和第十七过孔V17与位于第七有源层的第一区两侧的第二初始子线42连接，一方面实现了相邻的第二初始子线42之间的连接，形成第二初始信号线，另一方面实现了第二初始信号线与第七晶体管T7的第一极的连接，使第二初始信号线传输的第二初始电压写入第七晶体管T7的第一极。
在示例性实施方式中，第三导电层的材料和厚度可以与前述实施例基本上相同。
(37)形成第一平坦层图案。在示例性实施方式中，形成第一平坦层图案可以包括：在形成前述图案的基底上，先沉积第五绝缘薄膜，然后涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜和第五绝缘薄膜进行图案化，形成覆盖第三导电层图案的第五绝缘层以及设置在第五绝缘层上的第一平坦层，第一平坦层上设置有多个过孔，如图32所示。
在示例性实施方式中，每个电路单元中的多个过孔至少包括：第二十一过孔V21、第二十二过孔V22、第二十三过孔V23、第二十四过孔V24和第二十五过孔V25。
在示例性实施方式中，第二十一过孔V21在基底上的正投影位于第二连接电极52在基底上的正投影的范围之内，第二十一过孔V21内的第一平坦层和第五绝缘层被刻蚀掉，暴露出第二连接电极52的表面，第二十一过孔V21被配置为使后续形成的第一电源线通过该过孔与第二连接电极52连接。
在示例性实施方式中，第二十二过孔V22在基底上的正投影位于第四连接电极54在基底上的正投影的范围之内，第二十二过孔V22内的第一平坦层和第五绝缘层被刻蚀掉，暴露出第四连接电极54的表面，第二十二过孔V22被配置为使后续形成的数据信号线通过该过孔与第四连接电极54连接。
在示例性实施方式中，第二十三过孔V23在基底上的正投影位于第六连接电极56在基底上的正投影的范围之内，第二十三过孔V23内的第一平坦层和第五绝缘层被刻蚀掉，暴露出第六连接电极56的表面，第二十三过孔V23被配置为使后续形成的阳极连接电极通过该过孔与第六连接电极56连 接。
在示例性实施方式中，第二十四过孔V24在基底上的正投影位于第七连接电极57在基底上的正投影的范围之内，第二十四过孔V24内的第一平坦层和第五绝缘层被刻蚀掉，暴露出第七连接电极57的表面，第二十四过孔V24被配置为使后续形成的阳极连接电极通过该过孔与第七连接电极57连接。
在示例性实施方式中，第二十五过孔V25在基底上的正投影位于第九连接电极59在基底上的正投影的范围之内，第二十五过孔V25内的第一平坦层和第五绝缘层被刻蚀掉，暴露出第九连接电极59的表面，第二十五过孔V25被配置为使后续形成的初始连接线通过该过孔与第九连接电极59连接。
在示例性实施方式中，第一平坦层的材料和厚度可以与前述实施例基本上相同。
(38)形成第四导电层图案。在示例性实施方式中，形成第四导电层可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第一平坦层上的第四导电层，如图33所示。
在示例性实施方式中，每个电路单元的第四导电层至少包括：阳极连接电极61、第一电源线62、数据信号线63和初始连接线64。
在示例性实施方式中，阳极连接电极61的形状可以为主体部分沿着第二方向Y延伸的折线状，阳极连接电极61的第一端通过第二十三过孔V23与第六连接电极56连接，阳极连接电极61的第二端通过第二十四过孔V24与第七连接电极57连接。由于第六连接电极56通过过孔与第六有源层的第二区(也是第七有源层的第二区)连接，第七连接电极57通过过孔与第八极板78连接，因而实现了第八极板78、第六晶体管T6的第二极和第七晶体管T7的第二极具有相同的电位(像素驱动电路的第四节点N4)。在示例性实施方式中，阳极连接电极61被配置为与后续形成的阳极连接，因而可以实现像素驱动电路向发光器件输出驱动电流。
在示例性实施方式中，阳极连接电极61上可以设置有第一凸块，或者可以设置有第二凸块，或者可以设置有第一凸块和第二凸块，本公开在此不做 限定。
在示例性实施方式中，第一电源线62的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状，第一电源线62通过第二十一过孔V21与第二连接电极52连接。由于第二连接电极52通过过孔与第五有源层的第一区连接，因而实现了第一电源线62可以将第一电源信号写入第五晶体管T5的第一极。
在示例性实施方式中，第一电源线62在基底上的正投影可以与第一连接电极51在基底上的正投影至少部分交叠，使得第一电源线62可以作为屏蔽电极，可以有效屏蔽数据电压跳变对像素驱动电路中关键节点的影响，避免了数据电压跳变影响像素驱动电路的关键节点的电位，提高了显示效果。
在示例性实施方式中，第一电源线62在基底上的正投影可以与第三连接电极53在基底上的正投影至少部分交叠，使得第一电源线62可以作为屏蔽电极，可以有效屏蔽数据电压跳变对像素驱动电路中关键节点的影响，避免了数据电压跳变影响像素驱动电路的关键节点的电位，提高了显示效果。
在示例性实施方式中，数据信号线63的形状可以为主体部分沿着第二方向Y延伸的直线状，数据信号线63通过第二十二过孔V22与第四连接电极54连接。由于第四连接电极54通过过孔与第四有源层的第一区连接，因而实现了数据信号线63与第四晶体管T4的第一极的连接，数据信号线63可以将数据信号写入第四晶体管T4的第一极。
在示例性实施方式中，初始连接线64的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状，初始连接线64通过第二十五过孔V25与第九连接电极59连接。由于第二初始子线42和第九连接电极59构成传输第二初始信号的第二初始信号线，初始连接线64与第九连接电极59连接，使得沿着第一方向X延伸的第二初始信号线和沿着第二方向Y延伸的初始连接线64在显示区域构成网络连通结构的初始连接线，可以最大限度地降低了初始信号线的电阻，减小了初始电压的压降，而且有效提升了显示基板中初始电压的均一性，有效提升了显示均一性，提高了显示品质和显示质量。
在示例性实施方式中，初始连接线64、第九连接电极59和第二初始子线42分别设置在不同的导电层中，初始连接线64通过过孔与第九连接电极 59连接，第九连接电极59通过过孔与第二初始子线42连接。
在示例性实施方式中，第四导电层的材料和厚度可以与前述实施例基本上相同。
随后，在形成前述图案的基底上，涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成覆盖第四导电层图案的第二平坦层，第二平坦层上设置有阳极过孔，阳极过孔在基底上的正投影位于阳极连接电极在基底上的正投影的范围之内，阳极过孔被配置为使后续形成的阳极通过该过孔与阳极连接电极连接。在示例性实施方式中，第二平坦层的材料和厚度可以与前述实施例基本上相同。
至此，在基底上制备完成驱动电路层。在平行于显示基板的平面内，驱动电路层可以包括多个电路单元，每个电路单元可以包括像素驱动电路，以及与像素驱动电路连接的第一扫描信号线、第二扫描信号线、第三扫描信号线、第四扫描信号线、发光控制线、第一初始信号线和第二初始信号线、第一电源线和数据信号线。在垂直于显示基板的平面内，所述驱动电路层可以包括在基底上依次设置的遮挡导电层、第一绝缘层、半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层、第三导电层、第五绝缘层、第一平坦层、第四导电层和第二平坦层。遮挡导电层可以至少包括遮挡电极和多条遮挡线，半导体层可以至少包括第一晶体管至第七晶体管的有源层，第一导电层可以至少包括存储电容的第一极板和多条扫描信号线，第二导电层可以至少包括存储电容的第二极板、第一初始子线和第二初始子线，第三导电层可以至少包括第一连接电极至第九连接电极，第四导电层可以至少包括阳极连接电极、第一电源线和数据信号线。
从以上描述的显示基板的结构以及制备过程可以看出，本示例性实施例存储电容的两个极板分别位于第一导电层和第二导电层，且第一导电层和第二导电层之间的第三绝缘层采用硅氮化物，可以确保电容性能。本示例性实施例多个晶体管的底栅电极设置在遮挡导电层，多个晶体管的顶栅电极设置在第一导电层，可以有效保证对氧化物晶体管的遮挡，提高晶体管的电学性能。本公开的制备工艺可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
图34为本公开示例性实施例又一种显示基板的平面结构示意图。如图34所示，本示例性实施例的主体结构与图15所示的主体结构基本上相同，所不同的是，驱动电路层还可以包括：设置在第四导电层远离基底一侧的第二平坦层97和设置在第二平坦层97远离基底一侧的第五导电层。
在示例性实施方式中，第三导电层可以至少包括存储电容的第四极板74，第四导电层可以至少包括存储电容的第五极板75，第五导电层可以至少包括存储电容的第六极板76。第四极板74在基底上的正投影与第五极板75在基底上的正投影至少部分交叠，第四极板74和第五极板75构成第三存储电容，第六极板76在基底上的正投影与第五极板75在基底上的正投影至少部分交叠，第五极板75和第六极板76构成第四存储电容，第三存储电容和第四存储电容构成并联结构的存储电容。
在示例性实施方式中，第四极板74可以通过过孔与第三栅电极44连接，第六极板76可以通过过孔与第三栅电极44或者第四极板74连接，因而第四极板74和第六极板76具有相同的电位，第五极板75可以与阳极连接电极连接，位于第三导电层中的第四极板74、位于第四导电层中的第五极板75和位于第五导电层中的第六极板76构成并联结构的的存储电容。
在示例性实施方式中，第三导电层与第四导电层之间可以仅设置有第一平坦层96，或者可以设置有第五绝缘层和第一平坦层96，驱动电路层中可以包括第三绝缘层和第二导电层，本公开在此不做限定。
图35为本公开示例性实施例又一种显示基板的平面结构示意图。如图35所示，本示例性实施例的主体结构与图15所示的主体结构基本上相同，所不同的是，驱动电路层还可以包括：设置在第四导电层远离基底一侧的第二平坦层97和设置在第二平坦层97远离基底一侧的第五导电层。
在示例性实施方式中，第三导电层中没有设置第四极板，第四导电层可以至少包括存储电容的第五极板75，第五导电层可以至少包括存储电容的第六极板76，第六极板76在基底上的正投影与第五极板75在基底上的正投影至少部分交叠，第五极板75和第六极板76构成存储电容。
在示例性实施方式中，第五极板75可以与阳极连接电极连接，第五极板 75具有第四节点的电位，第六极板76可以通过过孔与第三栅电极44连接，第六极板76具有第一节点的电位，位于第四导电层中的第五极板75和位于第五导电层中的第六极板76构成存储电容。
图36为本公开示例性实施例又一种显示基板的平面结构示意图。如图36所示，本示例性实施例的主体结构与图15所示的主体结构基本上相同，所不同的是，驱动电路层还可以包括：设置在第四导电层远离基底一侧的第二平坦层97和设置在第二平坦层97远离基底一侧的第五导电层。
在示例性实施方式中，第三导电层可以至少包括存储电容的第四极板74，第四导电层中没有设置第五极板，第五导电层可以至少包括存储电容的第六极板76，第六极板76在基底上的正投影与第四极板74在基底上的正投影至少部分交叠，第四极板74和第六极板76构成存储电容。
在示例性实施方式中，第四极板74可以通过过孔与第三栅电极44，第四极板74具有第一节点的电位，第六极板76可以与阳极连接电极连接，第六极板76具有第四节点的电位，位于第三导电层中的第四极板74和位于第五导电层中的第六极板76构成存储电容。
在示例性实施方式中，图5所示的存储电容结构、图15所示的存储电容结构、图24所示的存储电容结构、图34至图36所示存储电容的结构可以相互组合，形成多个存储电容并联的存储电容结构，以最大限度地提高存储电容的容量，本公开在此不做限定。
本公开前述所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开在此不做限定。
在示例性实施方式中，本公开显示基板可以应用于具有像素驱动电路的其它显示装置中，如量子点显示等，本公开在此不做限定。
本公开还提供一种显示基板的制备方法，以制作上述实施例提供的显示基板。在示例性实施方式中，所述显示基板包括多个电路单元，至少一个电路单元包括像素驱动电路，所述像素驱动电路包括存储电容和多个氧化物晶体管，所述存储电容包括第一电容极板和第二电容极板，所述第一电容极板 在显示基板平面上的正投影与所述第二电容极板在显示基板平面上的正投影至少部分交叠，所述第一电容极板和第二电容极板之间设置有电容绝缘层；所述制备方法包括：
在基底上沿着远离所述基底的方向形成半导体层和第一源漏金属层，至少一个电容绝缘层设置在所述半导体层靠近所述基底的一侧，或者，至少一个电容绝缘层设置在所述第一源漏金属层远离所述基底的一侧。
本公开还提供一种显示装置，显示装置包括前述的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (16)

  1. 一种显示基板，包括多个电路单元，至少一个电路单元包括像素驱动电路，所述像素驱动电路包括存储电容和多个氧化物晶体管，所述存储电容至少包括第一电容极板和第二电容极板，所述第一电容极板在显示基板平面上的正投影与所述第二电容极板在显示基板平面上的正投影至少部分交叠，所述第一电容极板和第二电容极板之间设置有电容绝缘层；在垂直于所述显示基板的平面上，至少一个电路单元包括在基底上沿着远离所述基底的方向设置的半导体层和第一源漏金属层，至少一个电容绝缘层设置在所述半导体层靠近所述基底的一侧，或者，至少一个电容绝缘层设置在所述第一源漏金属层远离所述基底的一侧。
  2. 根据权利要求1所述的显示基板，其中，在垂直于所述显示基板的平面上，至少一个电路单元至少包括在基底上沿着远离所述基底的方向依次设置的遮挡导电层、第一绝缘层、第一栅金属层、第二绝缘层、半导体层、第三绝缘层、第二栅金属层、第四绝缘层和第一源漏金属层，所述第一电容极板包括设置在所述遮挡导电层中的第一极板，所述第二电容极板包括设置在所述第一栅金属层中的第二极板，所述第一极板在所述基底上的正投影与所述第二极板在所述基底上的正投影至少部分交叠，所述第一极板和第二极板构成第一存储电容。
  3. 根据权利要求2所述的显示基板，其中，所述第一电容极板还包括设置在所述第二栅金属层中的第三极板，所述第三极板在所述基底上的正投影与所述第二极板在所述基底上的正投影至少部分交叠，所述第三极板和第二极板构成第二存储电容。
  4. 根据权利要求3所述的显示基板，其中，所述第三极板通过连接电极与所述第一极板连接，所述第一存储电容和第二存储电容构成并联结构的存储电容。
  5. 根据权利要求4所述的显示基板，其中，所述多个氧化物晶体管至少包括驱动晶体管，所述驱动晶体管包括底栅电极和顶栅电极，所述驱动晶体管的底栅电极设置在所述第一栅金属层中，所述驱动晶体管的顶栅电极设 置在所述第二栅金属层中，所述驱动晶体管的底栅电极和所述第二极板为相互连接的一体结构，所述驱动晶体管的顶栅电极和所述第三极板为相互连接的一体结构。
  6. 根据权利要求5所述的显示基板，其中，多个氧化物晶体管还包括补偿晶体管和第一复位晶体管，所述第一复位晶体管的第一极与第一初始信号线连接，所述补偿晶体管的第二极与所述驱动晶体管的第一极连接，所述第一复位晶体管的第二极和所述补偿晶体管的第一极与所述驱动晶体管的顶栅电极连接。
  7. 根据权利要求5所述的显示基板，其中，多个氧化物晶体管还包括发光晶体管和第二复位晶体管，所述发光晶体管的第一极与所述驱动晶体管的第二极连接，所述第二复位晶体管的第一极与第二初始信号线连接，所述发光晶体管的第二极和所述第二复位晶体管的第二极与所述驱动晶体管的底栅电极连接。
  8. 根据权利要求1所述的显示基板，其中，在垂直于所述显示基板的平面上，至少一个电路单元至少包括在基底上沿着远离所述基底的方向依次设置的遮挡导电层、第一绝缘层、半导体层、第二绝缘层、第一栅金属层、第四绝缘层、第一源漏金属层、第一平坦层和第二源漏金属层，所述第一电容极板包括设置在所述第一源漏金属层中的第四极板，所述第二电容极板包括设置在所述第二源漏金属层中的第五极板，所述第四极板在所述基底上的正投影与所述第五极板在所述基底上的正投影至少部分交叠，所述第四极板和第五极板构成第三存储电容。
  9. 根据权利要求8所述的显示基板，其中，所述第一源漏金属层和第一平坦层还设置有第五绝缘层，所述第一平坦层上设置有平坦凹槽，所述平坦凹槽内的第一平坦层被去掉，暴露出所述第五绝缘层，所述第五极板设置在所述平坦凹槽内，所述平坦凹槽在所述基底上的正投影包含所述第四极板和所述第二极板在所述基底上的正投影。
  10. 根据权利要求8所述的显示基板，其中，至少一个电路单元还包括设置在所述第二源漏金属层远离所述基底一侧的第二平坦层和设置在所述第二平坦层远离所述基底一侧的第三源漏金属层，所述第一电容极板还包括设 置在所述第三源漏金属层中的第六极板，所述第六极板在所述基底上的正投影与所述第五极板在所述基底上的正投影至少部分交叠，所述第五极板和第六极板构成第四存储电容。
  11. 根据权利要求10所述的显示基板，其中，所述第六极板通过连接电极与所述第四极板连接，所述第三存储电容和第四存储电容构成并联结构的存储电容。
  12. 根据权利要求8所述的显示基板，其中，所述多个氧化物晶体管至少包括驱动晶体管，所述驱动晶体管包括底栅电极和顶栅电极，所述驱动晶体管的底栅电极设置在所述遮挡导电层中，所述驱动晶体管的顶栅电极设置在所述第一导电层中，所述第四极板通过过孔与所述驱动晶体管的顶栅电极连接。
  13. 根据权利要求12所述的显示基板，其中，多个氧化物晶体管还包括补偿晶体管和第一复位晶体管，所述第一复位晶体管的第一极与第一初始信号线连接，所述补偿晶体管的第二极与所述驱动晶体管的第一极连接，所述第一复位晶体管的第二极和所述补偿晶体管的第一极与所述驱动晶体管的顶栅电极连接。
  14. 根据权利要求12所述的显示基板，其中，多个氧化物晶体管还包括数据写入晶体管，所述数据写入晶体管的第一极与数据信号线连接，所述数据写入晶体管的第二极和所述驱动晶体管的第二极与所述驱动晶体管的底栅电极连接。
  15. 一种显示装置，包括如权利要求1至14任一项所述的显示基板。
  16. 一种显示基板的制备方法，所述显示基板包括多个电路单元，至少一个电路单元包括像素驱动电路，所述像素驱动电路包括存储电容和多个氧化物晶体管，所述存储电容包括第一电容极板和第二电容极板，所述第一电容极板在显示基板平面上的正投影与所述第二电容极板在显示基板平面上的正投影至少部分交叠，所述第一电容极板和第二电容极板之间设置有电容绝缘层；所述制备方法包括：
    在基底上沿着远离所述基底的方向形成半导体层和第一源漏金属层，至 少一个电容绝缘层设置在所述半导体层靠近所述基底的一侧，或者，至少一个电容绝缘层设置在所述第一源漏金属层远离所述基底的一侧。
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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160365404A1 (en) * 2015-06-11 2016-12-15 Samsung Display Co., Ltd. Thin film transistor substrate and organic light-emitting diode display including the same
CN110610684A (zh) * 2019-10-29 2019-12-24 厦门天马微电子有限公司 一种有机电致发光显示面板及显示装置
CN110649046A (zh) * 2019-11-01 2020-01-03 京东方科技集团股份有限公司 像素结构及制作方法、阵列基板、显示面板
CN111564476A (zh) * 2020-05-15 2020-08-21 合肥京东方卓印科技有限公司 显示基板及其制备方法、显示装置
CN112509519A (zh) * 2020-10-20 2021-03-16 厦门天马微电子有限公司 一种显示面板的驱动方法及显示装置
CN112614870A (zh) * 2019-10-04 2021-04-06 三星显示有限公司 显示装置
CN113261106A (zh) * 2019-11-28 2021-08-13 京东方科技集团股份有限公司 显示基板和显示装置
CN114586155A (zh) * 2020-09-30 2022-06-03 京东方科技集团股份有限公司 显示基板、显示面板和显示装置
CN115000092A (zh) * 2022-05-31 2022-09-02 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160365404A1 (en) * 2015-06-11 2016-12-15 Samsung Display Co., Ltd. Thin film transistor substrate and organic light-emitting diode display including the same
CN112614870A (zh) * 2019-10-04 2021-04-06 三星显示有限公司 显示装置
CN110610684A (zh) * 2019-10-29 2019-12-24 厦门天马微电子有限公司 一种有机电致发光显示面板及显示装置
CN110649046A (zh) * 2019-11-01 2020-01-03 京东方科技集团股份有限公司 像素结构及制作方法、阵列基板、显示面板
CN113261106A (zh) * 2019-11-28 2021-08-13 京东方科技集团股份有限公司 显示基板和显示装置
CN111564476A (zh) * 2020-05-15 2020-08-21 合肥京东方卓印科技有限公司 显示基板及其制备方法、显示装置
CN114586155A (zh) * 2020-09-30 2022-06-03 京东方科技集团股份有限公司 显示基板、显示面板和显示装置
CN112509519A (zh) * 2020-10-20 2021-03-16 厦门天马微电子有限公司 一种显示面板的驱动方法及显示装置
CN115000092A (zh) * 2022-05-31 2022-09-02 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

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