WO2022198377A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2022198377A1
WO2022198377A1 PCT/CN2021/082057 CN2021082057W WO2022198377A1 WO 2022198377 A1 WO2022198377 A1 WO 2022198377A1 CN 2021082057 W CN2021082057 W CN 2021082057W WO 2022198377 A1 WO2022198377 A1 WO 2022198377A1
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Prior art keywords
layer
segment
transistor
electrode
region
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PCT/CN2021/082057
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English (en)
French (fr)
Inventor
李梅
刘利宾
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP21932012.4A priority Critical patent/EP4123718A4/en
Priority to CN202180000547.XA priority patent/CN115398632A/zh
Priority to US17/630,172 priority patent/US20230380227A1/en
Priority to PCT/CN2021/082057 priority patent/WO2022198377A1/zh
Publication of WO2022198377A1 publication Critical patent/WO2022198377A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • This article relates to, but is not limited to, the field of display technology, and specifically relates to a display substrate, a manufacturing method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • TFT Thin Film Transistor
  • the present disclosure provides a display substrate, in a plane parallel to the display substrate, the display substrate includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit, and the pixel driving circuit at least includes a driving transistor; the driving transistor
  • the active layer includes a channel region, the channel region includes a drain end segment extending along the first direction, a middle segment connected with the drain end segment, and a source end segment connected with the middle segment; the drain end segment
  • the end section has a first width at a first end away from the middle section, and the drain end section has a second width at a second end close to the middle section; the first width is greater than the second width;
  • the first width and the second width are the dimensions of the drain end section in a second direction, and the first direction intersects with the second direction.
  • the active layer of the driving transistor further includes a first region connected to the drain terminal segment and a second region connected to the source terminal segment, one end of the first region is connected to the A first end of the drain end segment is connected, and the other end of the first region is connected to a transistor receiving a data signal; in a plane parallel to the display substrate, the shape of the source end segment includes a rectangle.
  • the shape of the drain segment in a plane parallel to the display substrate, includes a trapezoid, the trapezoid includes a trapezoid lower base and a trapezoid upper base, and the first end of the drain segment is a trapezoid lower base.
  • the bottom has a first width, and the second end of the drain end section is a trapezoidal upper bottom with a second width.
  • the shape of the drain segment includes a combination of a trapezoid and a rectangle, the trapezoid includes a trapezoid lower base and a trapezoid upper base, and the rectangle includes a rectangular lower side and a rectangle.
  • the upper side of the rectangle; the first end of the drain end segment is a trapezoidal lower bottom with a first width, the upper trapezoidal bottom is connected to the lower side of the rectangle and has a second width, and the second end of the drain segment is the top of the rectangle.
  • the shape of the drain segment in a plane parallel to the display substrate, includes a combination of a rectangle and a trapezoid, the rectangle includes a lower side of a rectangle and an upper side of the rectangle, and the trapezoid includes a lower base and a trapezoid upper bottom; the first end of the drain end section is a rectangular lower side, the rectangular upper side is connected with the trapezoidal lower bottom and has a first width, and the second end of the drain end section is a trapezoidal upper bottom with a second width.
  • the shape of the drain segment in a plane parallel to the display substrate, includes a combination of a first trapezoid and a second trapezoid, and the first trapezoid includes a first trapezoid lower base and a first trapezoid
  • the upper bottom, the second trapezoid includes a second trapezoidal lower bottom and a second trapezoidal upper bottom; the first end of the drain end section is a first trapezoidal lower bottom with a first width, and the first trapezoidal upper bottom and the The second trapezoidal lower bottom is connected, and the second end of the drain end section is the second trapezoidal upper bottom and has a second width.
  • the ratio of the first width to the second width is 1.5 to 5.
  • the included angle between at least one side of the trapezoid and the first direction is greater than 0° and less than 90°.
  • the display substrate in a plane perpendicular to the display substrate, includes a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially arranged on a substrate;
  • the semiconductor layer includes The active layer of a plurality of polysilicon transistors, the first conductive layer includes the gate electrodes of the plurality of polysilicon transistors and the first plate of the storage capacitor, the second conductive layer includes the second plate of the storage capacitor, the first plate
  • the three conductive layers include first power lines, data signal lines, and first and second electrodes of a plurality of polysilicon transistors.
  • the display substrate in a plane perpendicular to the display substrate, includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, and a third conductive layer that are sequentially arranged on the substrate layer, a fourth conductive layer and a fifth conductive layer;
  • the first semiconductor layer includes active layers of a plurality of polysilicon transistors
  • the first conductive layer includes gate electrodes of a plurality of polysilicon transistors and a first plate of a storage capacitor
  • the second conductive layer includes the second electrode plate of the storage capacitor
  • the second semiconductor layer includes the active layers of a plurality of oxide transistors
  • the third conductive layer includes the gate electrodes of a plurality of oxide transistors
  • the fourth conductive layer includes first and second electrodes of a plurality of polysilicon transistors and first and second electrodes of a plurality of oxide transistors
  • the fifth conductive layer includes a first power supply line and a data signal line.
  • the middle segment of the channel region includes a second channel segment, a third channel segment and a fourth channel segment; the second end of the drain segment is connected to the second channel segment.
  • the first end of the second channel segment is connected to the first end of the third channel segment after extending in the opposite direction of the second direction; the first end of the third channel segment After extending along the first direction, the two ends are connected to the first end of the fourth channel segment; the second end of the fourth channel segment is connected to the first end of the source end segment after extending along the second direction ; the second end of the source end segment is connected to the second region of the active layer.
  • the present disclosure also provides a display device including the aforementioned display substrate.
  • the present disclosure also provides a preparation method of a display substrate, in a plane parallel to the display substrate, the display substrate includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit, and the pixel driving circuit at least includes a driving transistor;
  • the preparation method includes:
  • a semiconductor layer or a first semiconductor layer is formed on a substrate; the semiconductor layer or the first semiconductor layer includes at least an active layer of a driving transistor, and the active layer of the driving transistor includes a channel region, and the channel region includes a a drain end segment extending in a first direction, a middle segment connected with the drain end segment, and a source end segment connected with the middle segment; the drain end segment has a first width at a first end away from the middle segment , the drain end segment has a second width at the second end near the middle segment; the first width is greater than the second width; the first width and the second width are the width of the drain end segment at the first The dimension in two directions, the first direction intersects with the second direction.
  • 1 is a schematic structural diagram of a display device
  • FIG. 2 is a schematic plan view of a display substrate
  • FIG. 3 is a schematic cross-sectional structure diagram of a display substrate
  • FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG. 6 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure.
  • FIG. 7a is a schematic diagram of a display substrate of the present disclosure after a semiconductor layer pattern is formed
  • Figure 7b is a cross-sectional view taken along the A-A direction in Figure 7a;
  • FIG. 8a is a schematic diagram of a display substrate after forming a first conductive layer pattern according to the disclosure
  • Figure 8b is a cross-sectional view taken along the A-A direction in Figure 8a;
  • FIG. 8c is an enlarged view of the channel region of the drive transistor in FIG. 8a;
  • 8d to 8i are schematic diagrams of several first channel segments according to exemplary embodiments of the present disclosure.
  • 9a is a schematic diagram of a display substrate after forming a second conductive layer pattern according to the disclosure.
  • Figure 9b is a cross-sectional view taken along the A-A direction in Figure 9a;
  • 10a is a schematic diagram of a display substrate after forming a fourth insulating layer pattern according to the disclosure.
  • Figure 10b is a cross-sectional view taken along the A-A direction in Figure 10b;
  • 11a is a schematic diagram of a display substrate after forming a third conductive layer pattern according to the disclosure.
  • Figure 11b is a cross-sectional view taken along the A-A direction in Figure 11a;
  • FIG. 12a is a schematic diagram of a display substrate of the present disclosure after a flat layer pattern is formed
  • Figure 12b is a cross-sectional view taken along the A-A direction in Figure 12a;
  • FIG. 13a is a schematic diagram of a display substrate of the present disclosure after an anode pattern is formed
  • Figure 13b is a cross-sectional view taken along the A-A direction in Figure 13a;
  • FIG. 14 is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure.
  • 15a is a schematic diagram of another display substrate of the present disclosure after a first semiconductor layer pattern is formed
  • Figure 15b is a sectional view taken along the direction B-B in Figure 15a;
  • 16a is a schematic diagram of another display substrate of the present disclosure after a first conductive layer pattern is formed
  • Figure 16b is a sectional view taken along the direction B-B in Figure 16a;
  • 17a is a schematic diagram of another display substrate of the present disclosure after a second conductive layer pattern is formed;
  • Figure 17b is a sectional view taken along the direction B-B in Figure 17a;
  • 18a is a schematic diagram of another display substrate of the present disclosure after a second semiconductor layer pattern is formed;
  • Figure 18b is a sectional view taken along the direction B-B in Figure 18a;
  • 19a is a schematic diagram of another display substrate of the present disclosure after a third conductive layer pattern is formed;
  • Figure 19b is a sectional view taken along the direction B-B in Figure 19a;
  • 20a is a schematic diagram of another display substrate of the present disclosure after a polysilicon via pattern is formed
  • Figure 20b is a sectional view taken along the direction B-B in Figure 20a;
  • 21a is a schematic diagram of another display substrate of the present disclosure after forming an oxide via pattern
  • Figure 21b is a sectional view taken along the direction B-B in Figure 21a;
  • 22a is a schematic diagram of another display substrate of the present disclosure after a fourth conductive layer pattern is formed;
  • Figure 22b is a sectional view taken along the direction B-B in Figure 22a;
  • 23a is a schematic diagram of another display substrate of the present disclosure after forming a first flat layer pattern
  • Figure 23b is a sectional view taken along the direction B-B in Figure 23a;
  • 24a is a schematic diagram of another display substrate of the present disclosure after a fifth conductive layer pattern is formed;
  • Figure 24b is a sectional view taken along the direction B-B in Figure 24a;
  • 25 is a schematic diagram of another display substrate of the present disclosure after forming a second flat layer pattern
  • FIG. 26 is a schematic diagram of another display substrate of the present disclosure after an anode pattern is formed.
  • 21 the first scanning signal line
  • 22 the second scanning signal line
  • 23 the light-emitting control line
  • 103 light emitting structure layer
  • 104 encapsulation layer
  • 301 anode
  • 302 pixel definition layer
  • 303 organic light-emitting layer
  • 304 cathode
  • 401 the first encapsulation layer
  • 402 the second encapsulation layer
  • 403 the third encapsulation layer.
  • the terms “installed”, “connected” and “connected” should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other, and “source terminal” and “drain terminal” may be interchanged with each other.
  • electrically connected includes the case where constituent elements are connected together by means of elements having some electrical function.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having a certain electrical effect” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • film and “layer” are interchangeable.
  • conductive layer may be replaced by “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • FIG. 1 is a schematic structural diagram of a display device.
  • the OLED display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array
  • the pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), a plurality of light-emitting signal lines (E1 to Eo), and a plurality of sub-pixels Pxij.
  • the timing controller may supply grayscale values and control signals suitable for the specification of the data driver to the data driver, and may supply a clock signal, a scan start signal, etc.
  • the driver can supply the light-emitting driver with a clock signal, an emission stop signal, and the like suitable for the specifications of the light-emitting driver.
  • the data driver may generate data voltages to be supplied to the data signal lines D1 , D2 , D3 , . . . and Dn using the grayscale values and control signals received from the timing controller. For example, the data driver may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data signal lines D1 to Dn in pixel row units, where n may be a natural number.
  • the scan driver may generate scan signals to be supplied to the scan signal lines S1 , S2 , S3 , . . .
  • the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm.
  • the scan driver may be constructed in the form of a shift register, and may generate the scan signal in such a manner that a scan start signal supplied in the form of an on-level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal , m can be a natural number.
  • the light emission driver may generate emission signals to be supplied to the light emission signal lines E1, E2, E3, . . . and Eo by receiving a clock signal, an emission stop signal, and the like from the timing controller.
  • the light emission driver may sequentially supply emission signals having off-level pulses to the light emission signal lines E1 to Eo.
  • the light-emitting driver may be constructed in the form of a shift register, and may generate the emission signal in such a manner that the emission stop signal provided in the form of an off-level pulse is sequentially transmitted to the next stage circuit under the control of the clock signal, o Can be a natural number.
  • the pixel array may include a plurality of sub-pixels Pxij. Each sub-pixel Pxij may be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light-emitting signal line, and i and j may be natural numbers.
  • the sub-pixel Pxij may refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and to the j-th data signal line.
  • FIG. 2 is a schematic plan view of a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one of the plurality of pixel units P includes a first light-emitting unit (sub-pixel) P1 that emits light of a first color, a second light-emitting unit P1 that emits light of a first color, and a The second light-emitting unit P2 for color light and the third light-emitting unit P3 for emitting light of the third color, the first light-emitting unit P1, the second light-emitting unit P2 and the third light-emitting unit P3 all include pixel driving circuits and light-emitting devices.
  • the pixel driving circuits in the first light emitting unit P1, the second light emitting unit P2 and the third light emitting unit P3 are respectively connected with the scanning signal line, the data signal line and the light emitting signal line, and the pixel driving circuit is configured to connect the scanning signal line and the light emitting signal line. Under the control of the line, the data voltage transmitted by the data signal line is received, and the corresponding current is output to the light-emitting device.
  • the light-emitting devices in the first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 are respectively connected to the pixel driving circuit of the light-emitting unit, and the light-emitting devices are configured to respond to the current output by the pixel driving circuit of the light-emitting unit. Brightness of light.
  • the pixel unit P may include a red (R) light-emitting unit, a green (G) light-emitting unit, and a blue (B) light-emitting unit, or may include a red light-emitting unit, a green light-emitting unit, and a blue light-emitting unit and white light-emitting units, which are not limited in the present disclosure.
  • the shape of the light emitting unit in the pixel unit may be a rectangle shape, a diamond shape, a pentagon shape or a hexagon shape.
  • the pixel unit includes three light-emitting units, the three light-emitting units can be arranged horizontally, vertically, or in a square pattern.
  • the pixel unit includes four light-emitting units, the four light-emitting units can be horizontally, vertically, or square. (Square) arrangement, which is not limited in the present disclosure.
  • Fig. 3 is a schematic cross-sectional structure diagram of a display substrate, illustrating the structure of three sub-pixels of the OLED display substrate.
  • the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate, and a light-emitting structure layer
  • the layer 103 is the encapsulation layer 104 on the side away from the substrate.
  • the display substrate may include other film layers, such as spacer columns, etc., which are not limited in the present disclosure.
  • the substrate 101 may be a flexible substrate, or it may be a rigid substrate.
  • the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting the pixel driving circuit. In FIG. 3 , only one driving transistor 210 and one storage capacitor 211 are used as an example for illustration.
  • the light-emitting structure layer 103 of each sub-pixel may include a plurality of film layers constituting a light-emitting device, and the plurality of film layers may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304.
  • the anode 301 is connected to the driving transistor 210 through a via hole.
  • the drain electrode is connected, the organic light-emitting layer 303 is connected to the anode 301, the cathode 304 is connected to the organic light-emitting layer 303, and the organic light-emitting layer 303 is driven by the anode 301 and the cathode 304 to emit light of the corresponding color.
  • the encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403.
  • the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials.
  • the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that the outside water vapor cannot enter the light emitting structure layer 103 .
  • the organic light-emitting layer 303 may include a stacked hole injection layer (Hole Injection Layer, HIL for short), a hole transport layer (Hole Transport Layer, HTL for short), an electron blocking layer (Electron Block Layer, EBL), Emitting Layer (EML), Hole Block Layer (HBL), Electron Transport Layer (ETL) and Electron Injection Layer (EIL) .
  • HIL Hole Injection Layer
  • HTL Hole Transport Layer
  • EBL Electron Block Layer
  • EML Electron Transport Layer
  • EIL Electron Injection Layer
  • the hole injection layer and the electron injection layer of all subpixels may be a common layer connected together
  • the hole transport layer and the electron transport layer of all subpixels may be a common layer connected together
  • all The hole blocking layers of the subpixels may be a common layer connected together
  • the light emitting layers and the electron blocking layers of adjacent subpixels may overlap slightly, or may be isolated.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure.
  • FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG. 4 , the pixel driving circuit may include 7 transistors (the first transistor T1 to the seventh transistor T7 ), a storage capacitor C and 7 signal lines (the data signal line D, the first scan signal line S1 , the third Two scan signal lines S2, light-emitting signal lines E, initial signal lines INIT, first power lines VDD and second power lines VSS).
  • the first end of the storage capacitor C is connected to the first power supply line VDD
  • the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the third transistor T3 Control pole connection.
  • the control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2.
  • the first transistor T1 transmits an initialization voltage to the gate of the third transistor T3 to initialize the charge amount of the gate of the third transistor T3.
  • the control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the third transistor T3 is connected to the first node N1.
  • the second pole of T3 is connected to the third node N3.
  • the third transistor T3 may be referred to as a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.
  • the control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 may be referred to as a switching transistor, a scan transistor, or the like, and enables the data voltage of the data signal line D to be input to the pixel driving circuit when an on-level scan signal is applied to the first scan signal line S1.
  • the control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device.
  • the fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors. When an on-level light emission signal is applied to the light emission signal line E, the fifth and sixth transistors T5 and T6 make the light emitting device emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.
  • the control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device.
  • the seventh transistor T7 transmits an initialization voltage to the first electrode of the light emitting device to initialize or discharge the amount of charge accumulated in the first electrode of the light emitting device to emit light The amount of charge accumulated in the first pole of the device.
  • the second pole of the light emitting device is connected to the second power supply line VSS, the signal of the second power supply line VSS is a low-level signal, and the signal of the first power supply line VDD is a continuous high-level signal.
  • the first scan signal line S1 is the scan signal line in the pixel driving circuit of the display row
  • the second scan signal line S2 is the scan signal line in the pixel driving circuit of the previous display row, that is, for the nth display row, the first scan signal
  • the line S1 is S(n)
  • the second scanning signal line S2 is S(n-1)
  • the second scanning signal line S2 of this display line is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display line
  • the signal lines can reduce the signal lines of the display panel and realize the narrow frame of the display panel.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.
  • the first to seventh transistors T1 to T7 may employ low temperature polysilicon thin film transistors, or may employ oxide thin film transistors, or may employ both low temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor adopts low temperature polysilicon (Low Temperature Poly-Silicon, LTPS for short), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide).
  • Low temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • Temperature Polycrystalline Oxide, referred to as LTPO) display substrate can take advantage of the two, can achieve low frequency drive, can reduce power consumption, can improve display quality.
  • the first scan signal line S1, the second scan signal line S2, the light emitting signal line E and the initial signal line INIT extend in the horizontal direction
  • the second power supply line VSS, the first power supply line VDD and the data signal line D extends in the vertical direction.
  • the light emitting device may be an organic electroluminescent diode (OLED) including a stacked first electrode (anode), an organic light emitting layer and a second electrode (cathode).
  • OLED organic electroluminescent diode
  • FIG. 5 is a working timing diagram of a pixel driving circuit. Exemplary embodiments of the present disclosure will be described below through the operation process of the pixel driving circuit illustrated in FIG. 4 .
  • the pixel driving circuit in FIG. 4 includes 7 transistors (the first transistor T1 to the sixth transistor T7 ), and 1 storage capacitors C and 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light-emitting signal line E, initial signal line INIT, first power supply line VDD and second power supply line VSS), all seven transistors are is a P-type transistor.
  • the working process of the pixel driving circuit may include:
  • the signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are a high-level signal.
  • the signal of the second scanning signal line S2 is a low level signal, which turns on the first transistor T1, and the signal of the initial signal line INIT is supplied to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off. At this stage, the OLED Not glowing.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scanning signal line S1 is a low-level signal
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are a high-level signal
  • the data The signal line D outputs the data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scan signal line S1 is a low level signal, so that the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned on.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output from the data signal line D is supplied to the second through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2 node N2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C, and the voltage at the second end (second node N2) of the storage capacitor C is Vd-
  • the seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is supplied to the first electrode of the OLED, initializes (resets) the first electrode of the OLED, clears the internal pre-stored voltage, completes the initialization, and ensures that the OLED does not emit light.
  • the signal of the second scanning signal line S2 is a high-level signal, so that the first transistor T1 is turned off.
  • the signal of the light-emitting signal line E is a high-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals.
  • the signal of the light-emitting signal line E is a low-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power line VDD passes through the fifth transistor T5, the third transistor T3 and the sixth transistor T5, which are turned on.
  • the transistor T6 provides a driving voltage to the first electrode of the OLED to drive the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the third transistor T3, that is, the driving current for driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor.
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power line VDD.
  • FIG. 6 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating a planar structure of a sub-pixel.
  • the sub-pixels of the display substrate are provided with a first scan signal line 21 , a second scan signal line 22 , a light emission control line 23 , an initial signal line 31 , and a first power supply Line 41, data signal line 42 and pixel drive circuit
  • the pixel drive circuit may include a plurality of transistors and a storage capacitor
  • the storage capacitor includes the first plate 24 and the second plate 32
  • the plurality of transistors may include first transistors to seventh transistor
  • the third transistor is a driving transistor.
  • the display substrate may include a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially disposed on the substrate.
  • the semiconductor layer may include active layers of a plurality of transistors.
  • the first conductive layer may include a first scan signal line 21 , a second scan signal line 22 , a light emission control line 23 , a first electrode plate 24 of a storage capacitor and gate electrodes of a plurality of transistors.
  • the second conductive layer may include the initial signal line 31 , the second electrode plate 32 of the storage capacitor, the shield electrode 33 and the electrode plate connection line 35 .
  • the third conductive layer may include first power lines 41 , data signal lines 42 , first connection electrodes 43 , second connection electrodes 44 and third connection electrodes 45 .
  • the display substrate may include a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer, the first insulating layer is disposed between the substrate and the semiconductor layer, and the second insulating layer is disposed between the substrate and the semiconductor layer. Between the semiconductor layer and the first conductive layer, the third insulating layer is provided between the first conductive layer and the second conductive layer, and the fourth insulating layer is provided between the second conductive layer and the third conductive layer.
  • the sub-pixels may be divided into a first region R1, a second region R2 and a third region R3, and the second region R2 is located between the first region R1 and the third region R3 between.
  • the first scan signal line 21 , the second scan signal line 22 and the initial signal line 31 extending along the first direction X are located in the first region R1 , the first electrode plate 24 and the second electrode plate 32 Located in the second region R2, the light emission control line 23 extending along the first direction X is located in the third region R3.
  • the first direction X and the second direction Y intersect.
  • the first direction X may be the direction of sub-pixel rows (horizontal direction)
  • the second direction Y may be the direction of sub-pixel columns (vertical direction).
  • the gate electrode of the first transistor is connected to the second scan signal line 22
  • the first electrode of the first transistor is connected to the initial signal line 31
  • the second electrode of the first transistor is connected to the first electrode of the second transistor respectively.
  • the gate electrode of the first electrode and the third transistor is connected to the first electrode plate 24 .
  • the gate electrode of the second transistor is connected to the first scan signal line 21, and the second electrode of the second transistor is connected to the second electrode of the third transistor and the first electrode of the sixth transistor, respectively.
  • the first electrode of the third transistor is connected to the second electrode of the fourth transistor and the second electrode of the fifth transistor, respectively.
  • the gate electrode of the fourth transistor is connected to the first scan signal line 21, the first electrode of the fourth transistor is connected to the data signal line 42, and the second electrode of the fourth transistor is connected to the first electrode of the third transistor.
  • the gate electrode of the fifth transistor is connected to the light-emitting signal line 23 , and the first electrode of the fifth transistor is connected to the first power line 41 and the second electrode plate 32 respectively.
  • the gate electrode of the sixth transistor is connected to the light-emitting signal line 23, and the second electrode of the sixth transistor is connected to the second electrode of the seventh transistor T7 and the first electrode of the light-emitting device, respectively.
  • the gate electrode of the seventh transistor is connected to the second scanning signal line 22, the first electrode of the seventh transistor is connected to the initial signal line 31, and the second electrode of the seventh transistor is respectively connected to the second electrode of the sixth transistor and the first electrode of the light emitting device.
  • One pole connection is provided.
  • the third insulating layer and the fourth insulating layer covering the first electrode plate 24 are provided with a first via hole V1, and one end of the first connection electrode 43 is connected to the first electrode plate through the first via hole V1 24 connection, the other end of the first connection electrode 43 is connected to the active layer of the first transistor and the active layer of the second transistor through a via hole, and the first connection electrode 43 can be used as the second electrode of the first transistor and the second transistor. the first pole.
  • the second connection electrode 44 may be connected to the initial signal line 31 and the active layer of the seventh transistor through via holes, respectively, and the first connection electrode 43 may serve as the first electrode and the first transistor of the seventh transistor. the first pole.
  • the third connection electrode 45 may be connected to the active layer of the sixth transistor and the active layer of the seventh transistor through a via hole, and the third connection electrode 45 may serve as the second electrode and the third electrode of the sixth transistor.
  • the fourth insulating layer covering the second electrode plate 32 is provided with a second via hole V2, and the first power line 41 is connected to the second electrode plate 32 through the second via hole V2.
  • the first power line 41 is connected to the shield electrode 33 through a via hole, and the orthographic projection of the shield electrode 33 on the substrate and the orthographic projection of the data signal line 42 on the substrate have an overlapping area.
  • the plate connection lines 35 are provided in the second conductive layer.
  • the plate connecting line 35 is straight and parallel to the first direction X.
  • the first end of the plate connecting line 35 is connected to the second plate 32 of the sub-pixel, and the second end extends along the first direction X or the opposite direction of the first direction X, and is connected to the second plate 32 of the adjacent sub-pixel. connect.
  • the second electrode plate 32 is provided with an opening 34, and the orthographic projection of the opening 34 on the substrate includes the orthographic projection of the first via V1 on the substrate.
  • the data signal line 42 may be connected to the active layer of the fourth transistor through a via hole.
  • the first electrode plate 24 serves as the gate electrode of the third transistor at the same time, the orthographic projection of the first electrode plate 24 on the substrate and the orthographic projection of the third active layer on the substrate have an overlapping area, and the overlapping area
  • the third active layer is used as the channel region of the third transistor.
  • the first end of the channel region is connected to the first region of the third active layer, and the first region of the third active layer is connected to the fourth transistor receiving the data signal.
  • the second end of the channel region is connected to the second region of the third active layer, and the second region of the third active layer is connected to the second transistor.
  • the channel region of the third transistor may include a drain end segment extending in the F1 direction, a middle segment extending in the F2 direction, and a source end segment extending in the F3 direction, the F1 direction, the F2 direction, and the F3 direction Can be the same, or can intersect.
  • the F1 direction and the F3 direction may be the same, and the F1 direction and the F2 direction may intersect.
  • the channel region of the third transistor may include a drain end segment extending along the first direction X, a source end segment extending along the first direction X, and a middle between the drain end segment and the source end segment part.
  • the drain end segment extending along the first direction X and the source end segment extending along the first direction X may be parallel, or there may be 10° between the extension line of the drain end segment and the extension line of the source end segment. ° below the included angle.
  • the first end of the drain segment is connected to the first region of the third active layer
  • the second end of the drain segment extends along the first direction X and then connected to the first end of the middle segment
  • the second end of the middle segment is connected to the source segment
  • the first end of the source end segment extends along the first direction X and is connected to the second region of the third active layer.
  • the drain end segment has a first width at a first end remote from the middle segment, and the drain end segment has a second width at a second end near the middle segment, the first width being greater than the second width such that the drain end segment A fan shape is formed in which the first width of the first end is greater than the second width of the second end.
  • the first width and the second width are dimensions in the second direction Y of the drain end segment.
  • the display substrate provided by the exemplary embodiment of the present disclosure, by setting the drain end section of the driving transistor into a fan shape, the problem of output unsaturation of the thin film transistor caused by the channel shortening is improved, and the output characteristic of the thin film transistor can be flattened.
  • the following is an exemplary description through the preparation process of the display substrate.
  • the "patterning process” mentioned in this disclosure includes photoresist coating, mask exposure, development, etching, stripping photoresist and other treatments, for organic materials, including Processes such as coating organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spraying, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings are not limited in the present disclosure.
  • “Film” refers to a thin film made of a material on a substrate by deposition, coating, or other processes.
  • the "thin film” may also be referred to as a "layer”. If the "thin film” needs a patterning process in the whole manufacturing process, it is called a "thin film” before the patterning process, and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is located within the range of the orthographic projection of A
  • the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A Overlaps the boundary of the orthographic projection of B.
  • A's orthographic projection includes B's orthographic projection means that the boundary of B's orthographic projection falls within the boundary of A's orthographic projection, or the boundary of A's orthographic projection overlaps with the boundary of B's orthographic projection.
  • the manufacturing process of the display substrate may include the following operations.
  • a semiconductor layer pattern is formed.
  • forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process, forming a first insulating layer covering the substrate, and disposing on the substrate.
  • the semiconductor layer on the first insulating layer is shown in FIG. 7a and FIG. 7b, and FIG. 7b is a cross-sectional view taken along the direction A-A in FIG. 7a.
  • the semiconductor layer of each sub-pixel may include the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7, and the first active layer 11 to the seventh active layer 11
  • the source layer 17 is an interconnected integral structure.
  • the first region R1 may include at least part of the first active layer 11 of the first transistor T1 , the second active layer 12 of the second transistor T2 , and the fourth active layer of the fourth transistor T4 14 and the seventh active layer 17 of the seventh transistor T7
  • the second region R2 may include at least part of the third active layer 13 of the third transistor T3
  • the third region R3 may include at least part of the third active layer 13 of the fifth transistor T5.
  • the first active layer 11 and the seventh active layer 17 are disposed on the side of the first region R1 away from the second region R2, and the second active layer 12 and the fourth active layer 14 are disposed adjacent to the first region R1 One side of the second region R2.
  • the shape of the first active layer 11 may be in the shape of "n"
  • the shape of the second active layer 12 may be in the shape of "7”
  • the shape of the third active layer 13 may be in the shape of "six”
  • the shape of the fourth active layer 14 may be in the shape of "1”
  • the shape of the fifth active layer 15, the sixth active layer 16 and the seventh active layer 17 may be in the shape of "L”.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first and second regions.
  • the first region 11-1 of the first active layer 11 simultaneously serves as the first region 17-1 of the seventh active layer 17, and the second region 11-2 of the first active layer 11 simultaneously serves as the first region 11-1 of the seventh active layer 17.
  • the first region 13-1 of the third active layer 13 simultaneously serves as the second region 14-2 of the fourth active layer 14 and the fifth active layer 15
  • the second region 15-2 of the third active layer 13 simultaneously serves as the second region 12-2 of the second active layer 12 and the first region 16-1 of the sixth active layer 16
  • the second region 16 - 2 of the sixth active layer 16 simultaneously serves as the second region 17 - 2 of the seventh active layer 17 .
  • the first region 14-1 of the fourth active layer 14 and the first region 15-1 of the fifth active layer 15 are provided separately.
  • the third active layer 13 of the third transistor includes a first region 13-1, a second region 13-2 and a channel region, and the channel region of the third active layer 13 is disposed on the first region 13-1. Between the region 13-1 and the second region 13-2, and both ends of the channel region are connected to the first region 13-1 and the second region 13-2, respectively.
  • the first region 13-1 of the third active layer 13 simultaneously serves as the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15, namely the third active layer 13
  • the first region 13-1 of the fourth active layer 14, the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15 are connected to each other.
  • the second region 13-2 of the third active layer 13 simultaneously serves as the second region 12-2 of the second active layer 12 and the first region 16-1 of the sixth active layer 16, that is, the third active layer 13
  • the second region 13-2 of the second active layer 12, the second region 12-2 of the second active layer 12 and the first region 16-1 of the sixth active layer 16 are connected to each other.
  • the display substrate includes a first insulating layer 91 disposed on the substrate 10 and a semiconductor layer disposed on the first insulating layer 91, and the semiconductor layer may include a first active layer 11 and a first active layer Three active layers 13 .
  • a first conductive layer pattern is formed.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first metal film on the substrate on which the foregoing pattern is formed, and patterning the first metal film through a patterning process to form A second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, the first conductive layer pattern at least includes: a first scan signal line 21, a second scan signal line 22, and a light-emitting control line 23 and the first plate 24 of the storage capacitor, as shown in FIG. 8a, FIG. 8b and FIG. 8c, FIG. 8b is a cross-sectional view of FIG. 8a along A-A, and FIG.
  • the first conductive layer may be referred to as a first gate metal (GATE 1) layer.
  • the first scan signal line 21 , the second scan signal line 22 and the light emission control line 23 extend along the first direction X.
  • the first scan signal line 21 and the second scan signal line 22 are arranged in the first region R1, the second scan signal line 22 is located on the side of the first scan signal line 21 away from the second region R2, and the light emission control line 23 is arranged in the first region R1.
  • the first plate 24 of the storage capacitor is arranged in the second region R2 , between the first scanning signal line 21 and the light-emitting control line 23 .
  • the first electrode plate 24 may be rectangular, the corners of the rectangle may be provided with chamfers, and the orthographic projection of the first electrode plate 24 on the substrate and the third active layer of the third transistor T3 are at The orthographic projections on the substrate have overlapping regions.
  • the first electrode plate 24 simultaneously serves as the gate electrode of the third transistor T3.
  • a region where the first scan signal line 21 overlaps with the fourth active layer of the fourth transistor T4 serves as a gate electrode of the fourth transistor T4.
  • the first scanning signal line 21 is provided with a gate block 21-1 protruding toward the side of the second scanning signal line 22, the orthographic projection of the gate block 21-1 on the substrate and the second active layer of the second transistor T2
  • the orthographic projection on the substrate has an overlapping area, and the overlapping area of the first scanning signal line 21 and the gate block 21-1 with the second active layer of the second transistor T2 serves as the gate electrode of the double gate structure of the second transistor T2.
  • the region where the second scan signal line 22 and the first active layer of the first transistor T1 overlap serves as the gate electrode of the double gate structure of the first transistor T1, and the second scan signal line 22 and the seventh active layer of the seventh transistor T7
  • the overlapping area serves as the gate electrode of the seventh transistor T7
  • the area where the light emission control line 23 and the fifth active layer of the fifth transistor T5 overlap serve as the gate electrode of the fifth transistor T5
  • the light emission control line 23 and the sixth transistor T6 The overlapping region of the sixth active layers serves as the gate electrode of the sixth transistor T6.
  • the first conductive layer can be used as a shield to conduct conductorization processing on the semiconductor layer, and the semiconductor layers in the region shielded by the first conductive layer form the first transistors T1 to T7 In the channel region of the transistor T7, the semiconductor layer in the region not shielded by the first conductive layer is conductive, that is, the first region and the second region from the first active layer to the seventh active layer are all conductive.
  • the display substrate includes a first insulating layer 91 disposed on the substrate 10, a semiconductor layer disposed on the first insulating layer 91, a second insulating layer 92 covering the semiconductor layer, and a second insulating layer 92 disposed on the substrate 10.
  • the first conductive layer on the second insulating layer 92, the semiconductor layer may include the first active layer 11 and the third active layer 13, the first conductive layer may include the first scan signal line 21, the second scan signal line 22, The light emission control line 23 and the first plate 24 of the storage capacitor.
  • the orthographic projection of the first electrode plate 24 on the substrate and the orthographic projection of the third active layer on the substrate have an overlapping area.
  • the first electrode plate 24 also serves as the gate electrode of the third transistor T3, and the third The region where the third active layer of the transistor T3 and the first electrode plate 24 overlap is used as the channel region 18 of the third transistor T3.
  • One end of the channel region 18 is connected to the first region 13-1 of the third active layer, and the other end is connected to the first region 13-1 of the third active layer.
  • One end is connected to the second region 13-2 of the third active layer.
  • the channel refers to the semiconductor layer between the first region and the second region in the active layer of the transistor, and the channel width to length ratio is the ratio of the channel width to the channel length, which is an important parameter in the transistor.
  • the channel length is the same, the larger the channel width, the faster the speed and the higher the power consumption.
  • the channel width is the same, the smaller the channel length, the faster the speed and the higher the power consumption.
  • the channel region 18 includes a first channel segment (drain segment) 18-1, a third channel segment 18-3, and a fifth channel segment (source segment) extending in the first direction X segment) 18-5, and a second channel segment 18-2 and a fourth channel segment 18-4 extending along the second direction Y, the first channel segment 18-1 is called a drain segment, and the fifth channel segment
  • the segment 18-5 is referred to as the source segment
  • the second channel segment 18-2, the third channel segment 18-3 and the fourth channel segment 18-4 are collectively referred to as the segment located between the drain segment and the source segment. middle section.
  • the first end of the first channel segment 18-1 is connected to the first region 13-1, and the second end extends along the first direction X and is connected to the first end of the second channel segment 18-2.
  • the first end of the second channel segment 18-2 is connected to the second end of the first channel segment 18-1, and the second end extends in the opposite direction of the second direction Y and is connected to the third channel segment 18-3.
  • the first end is connected.
  • the first end of the third channel segment 18-3 is connected to the second end of the second channel segment 18-2, and the second end extends along the first direction X and is connected to the first end of the fourth channel segment 18-4 connect.
  • the first end of the fourth channel segment 18-4 is connected to the second end of the third channel segment 18-3, and the second end extends along the second direction Y and is connected to the first end of the fifth channel segment 18-5 connect.
  • the first end of the fifth channel segment 18-5 is connected to the second end of the fourth channel segment 18-4, and the second end extends along the first direction X and is connected to the second region 13-2, forming a "ji" A zigzag channel region 18 .
  • the first end of the first channel segment 18-1 connected to the first region 13-1 (doped region) of the third active layer has a first width M1, which is connected to the third active layer.
  • the second end of the first channel segment 18-1 to which the second channel segment 18-2 (middle segment) of the layer is connected has a second width M2, both the first width and the second width refer to the first channel segment 18 -1 dimension in the second direction Y.
  • the fifth channel segment 18-5 may be rectangular in shape.
  • the first width M1 may be greater than the second width M2.
  • the ratio of the first width M1 to the second width M2 may be about 1.5 to 5.
  • the first width M1 may be about 1.5 ⁇ m to 25 ⁇ m, and the second width M2 may be about 1 ⁇ m to 5 ⁇ m.
  • the first channel segment 18-1 has a length L, which may be about 2 ⁇ m to 10 ⁇ m, and the length refers to a dimension of the first channel segment 18-1 in the first direction X.
  • the orthographic projection of the first electrode plate 24 (the gate electrode of the third transistor T3 ) on the substrate and the orthographic projection of the third active layer on the substrate have overlapping lines extending along the second direction Y , the overlapping line on the side of the first region 13-1 close to the third active layer is the first end of the first channel segment 18-1.
  • the first channel segment 18-1 extending along the first direction X and the second channel segment 18-2 extending along the second direction Y have a boundary line extending along the second direction Y, and the boundary line may be the first The second end of the channel segment 18-1.
  • the first channel segment 18 - 1 may include a first sub-segment 18 a and a second sub-segment 18 b arranged in sequence along the first direction X.
  • the first subsection 18a extends along the first direction X, the first end of the first subsection 18a is connected to the first area 13-1, and the second end of the first subsection 18a extends along the first direction X and is connected to the second subsection 13-1.
  • the first end of segment 18b is connected.
  • the first end of the second sub-segment 18b is connected to the second end of the first sub-segment 18a, and the second end of the second sub-segment 18b extends along the first direction X and is connected to the first end of the second channel segment 18-2 connect.
  • the first sub-segment 18a and the second sub-segment 18b may be divided in various ways.
  • the first subsection 18a and the second subsection 18b have different shapes, one is a rectangle and the other is a trapezoid, and the first subsection 18a and the second subsection 18b can be divided according to the boundary between the rectangle and the trapezoid.
  • the shapes of the first subsection 18a and the second subsection 18b are both trapezoids, one trapezoid has a larger base angle, and the other trapezoid has a smaller base angle.
  • the boundary line between the corner trapezoids divides the first subsection 18a and the second subsection 18b, which is not limited in the present disclosure.
  • the first end of the first sub-segment 18a remote from the second sub-segment 18b has a first width M1
  • the second end of the second sub-segment 18b remote from the first sub-segment 18a has a second width M2.
  • the first sub-segment 18a has a first length L1
  • the second sub-segment 18b has a second length L2
  • the length L may be about 2 ⁇ m to 10 ⁇ m
  • the first length L1 may be about 1 ⁇ m to 5 ⁇ m
  • the second length L2 may be about 1 ⁇ m to 5 ⁇ m.
  • the length L may be about 3 m
  • the first length L1 may be about 1.5 m
  • the second length L2 may be about 1.5 m.
  • 8d to 8i are schematic diagrams of several first channel segments according to exemplary embodiments of the present disclosure.
  • the shape of the first subsection 18a may be a trapezoid
  • the shape of the second subsection 18b may be a rectangle
  • the trapezoid includes a trapezoidal lower base and a trapezoidal upper base
  • the rectangle includes a rectangular lower side and a rectangular upper side.
  • the first end of the first subsection 18a serves as a trapezoidal lower base with a first width M1
  • the second end of the first subsection 18a serves as a trapezoidal upper base
  • the first end of the second subsection 18b serves as a rectangular lower side
  • the second subsection 18b serves as a rectangular lower side
  • the second end of the segment 18b serves as the upper side of the rectangle, and has a second width M2, and the upper bottom of the trapezoid is connected to the lower side of the rectangle, as shown in FIG. 8d.
  • the shape of the first subsection 18a may be a rectangle
  • the shape of the second subsection 18b may be a trapezoid
  • the rectangle includes a rectangular lower side and a rectangular upper side
  • the trapezoid includes a trapezoidal lower base and a trapezoidal upper base.
  • the first end of the first subsection 18a serves as the lower side of the rectangle and has a first width M1
  • the second end of the first subsection 18a serves as the upper side of the rectangle
  • the first end of the second subsection 18b serves as the lower bottom of the trapezoid
  • the second subsection 18b serves as the lower bottom of the trapezoid.
  • the second end of 18b is used as a trapezoidal upper base with a second width M2, and the upper side of the rectangle is connected with the trapezoidal lower base, as shown in FIG. 8e.
  • the shape of the first sub-section 18a may be a first trapezoid
  • the shape of the second sub-section 18b may be a second trapezoid
  • the first trapezoid includes a lower base of the first trapezoid and an upper trapezoid of the first trapezoid.
  • the second trapezoid includes a second trapezoid lower base and a second trapezoid upper base.
  • the first end of the first subsection 18a serves as a first trapezoidal lower base with a first width M1
  • the second end of the first subsection 18a serves as a first trapezoidal upper base
  • the first end of the second subsection 18b serves as a second Trapezoidal lower base
  • the second end of the second sub-section 18b serves as a second trapezoidal upper base with a second width M2
  • the first trapezoidal upper base is connected with the second trapezoidal lower base, as shown in FIG. 8f .
  • the overall shape of the first channel segment 18-1 is a trapezoid, and the first end of the first channel segment 18-1 serves as a trapezoidal lower base, having a first width M1, and the first channel segment 18-1 has a first width M1.
  • the second end of the track section 18-1 serves as a trapezoidal upper base with a second width M2, as shown in FIG. 8g.
  • the shape of the first subsection 18a may be a trapezoid
  • the shape of the second subsection 18b may be a rectangle
  • the trapezoid includes a trapezoidal lower base and a trapezoidal upper base
  • the rectangle includes a rectangular lower side and a rectangular upper side.
  • the first end of the first subsection 18a serves as a trapezoidal lower base with a first width M1
  • the second end of the first subsection 18a serves as a trapezoidal upper base
  • the first end of the second subsection 18b serves as a rectangular lower side
  • the second subsection 18b serves as a rectangular lower side
  • the second end of the segment 18b serves as the upper side of the rectangle and has a second width M2.
  • the upper trapezoidal base is connected to the lower side of the rectangle.
  • the width of the upper trapezoid base in the second direction is greater than the width of the lower side of the rectangle in the second direction, as shown in Figure 8h.
  • the shape of the first sub-section 18a may be a trumpet shape
  • the shape of the second sub-section 18b may be a rectangle
  • the trumpet shape includes a trumpet-shaped lower bottom and a trumpet-shaped upper bottom
  • the rectangle includes a rectangular lower side and the top of the rectangle.
  • the first end of the first sub-section 18a serves as a trumpet-shaped lower bottom with a first width M1
  • the second end of the first sub-section 18a serves as a trumpet-shaped upper bottom
  • the first end of the second sub-section 18b serves as a rectangular lower side
  • the first end of the second sub-section 18b serves as a rectangular lower side
  • the second end of the two sub-sections 18b serves as the upper side of the rectangle and has a second width M2.
  • the upper trumpet-shaped bottom is connected to the lower side of the rectangle.
  • the width of the upper trumpet-shaped bottom in the second direction is equal to the width of the lower side of the rectangle in the second direction, as shown in Figure 8i .
  • the first channel segment 18-1 may include a plurality of sub-segments arranged in sequence along the first direction X, which is not limited in the present disclosure.
  • the angle ⁇ between at least one side of the trapezoid and the first direction X may be greater than 0° and less than or equal to 90°. In a possible exemplary embodiment, at least one side of the trapezoid may be greater than 0° and less than or equal to 90°.
  • the included angle ⁇ between the side and the first direction X may be about 20° to 60°, for example, the included angle ⁇ may be about 30° to 40°.
  • the base angle ⁇ of the trapezoid may be about 30° to 70°, for example, the base angle ⁇ may be about 50° to 60°.
  • the trapezoid may be an isosceles trapezoid, or may be a non-isosceles trapezoid, such as a right-angled trapezoid, or the like.
  • the side of the trapezoid may be a straight line, or may be an arc, which is not limited in the present disclosure.
  • trapezoid, rectangle etc. mentioned in the present disclosure are not required to be trapezoids and rectangles in the strict sense, and arc edges, curved edges, chamfers, rounded corners, etc. may exist, which are not limited in the present disclosure.
  • the drain bias will change the effective channel length, but the source barrier remains constant, and the in-channel potential can be approximately dependent on the lateral electric field ⁇ x (controlled by the gate voltage) one-dimensional distribution.
  • the potential distribution in the channel becomes a two-dimensional distribution, depending on the lateral electric field ⁇ x , the channel will occur Short channel effects such as current Id is not saturated.
  • DIBL Drain Induced Barrier Lowering
  • the channel of one end of the third transistor T3 close to the drain electrode (the first region of the third active layer) is arranged in a fan shape, that is, the first channel segment 18-1 in the channel region 18 or The shape of the first sub-segment 18a in the first channel segment 18-1 is set as a trapezoid.
  • the leakage electric field can be dispersed, thereby reducing the With the lateral electric field ⁇ x , the drain electrode depletion region becomes shorter in the channel direction, thereby improving the output unsaturation problem of the thin film transistor caused by the shortening of the channel, and making the output characteristic of the thin film transistor flat.
  • the short-channel driving transistor with flat output characteristics proposed by the exemplary embodiments of the present disclosure can not only save space and facilitate high-resolution display, but also reduce the channel length and reduce the threshold voltage Vth of the driving transistor, which is conducive to reducing power consumption.
  • a second conductive layer pattern is formed.
  • forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second metal film on the substrate on which the foregoing pattern is formed, and patterning the second metal film using a patterning process to form A third insulating layer 93 covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer 93, the second conductive layer pattern at least includes: the initial signal line 31, the second electrode plate 32 of the storage capacitor, The shielding electrode 33 and the electrode plate connecting line 35 are as described in Fig. 9a and Fig. 9b, and Fig. 9b is a cross-sectional view taken along the direction A-A in Fig. 9a.
  • the second conductive layer may be referred to as a second gate metal (GATE 2) layer.
  • the initial signal line 31 extends along the first direction X, is disposed in the first region R1, and is located on the side of the second scan signal line 22 away from the second region R2.
  • the second electrode plate 32 of the storage capacitor is disposed in the second region R2 between the first scan signal line 21 and the light emission control line 23 .
  • the shielding electrode 33 is arranged in the first region R1, and the shielding electrode 33 is configured to shield the influence of the data voltage jump on the key nodes, so as to prevent the data voltage jump from affecting the potential of the key nodes of the pixel driving circuit and improve the display effect.
  • the initial signal lines 31 may be provided with unequal widths, and the width of the initial signal lines 31 is the dimension of the second direction Y of the initial signal lines 31 .
  • the initial signal line 31 includes a region overlapping with the semiconductor layer and a region not overlapping with the semiconductor layer.
  • the width of the initial signal line 31 in the region not overlapping with the semiconductor layer may be smaller than the width of the initial signal line 31 in the region overlapping with the semiconductor layer. width.
  • the outline of the second electrode plate 32 may be rectangular, the corners of the rectangular shape may be chamfered, and the orthographic projection of the second electrode plate 32 on the substrate is the same as that of the first electrode plate 24 on the substrate. Orthographic projections have overlapping areas.
  • the second pole plate 32 is provided with an opening 34, and the opening 34 may be located in the middle of the second region R2.
  • the opening 34 may be rectangular, so that the second electrode plate 32 forms an annular structure.
  • the opening 34 exposes the third insulating layer 93 covering the first electrode plate 24 , and the orthographic projection of the first electrode plate 24 on the substrate includes the orthographic projection of the opening 34 on the substrate.
  • the opening 34 is configured to accommodate a subsequently formed first via hole, and the first via hole is located in the opening 34 and exposes the first electrode plate 24 so that the second electrode of the subsequently formed first transistor T1 connected to the first pole plate 24 .
  • the electrode plate connecting line 35 is disposed between the second electrode plates 32 of adjacent sub-pixels in the first direction X, and the first end of the electrode plate connecting line 35 is connected to the second electrode plate 32 of this sub-pixel. connection, the second end of the plate connecting line 35 extends along the first direction X or the opposite direction of the first direction X, and is connected with the second plate 32 of the adjacent sub-pixel, that is, the plate connecting line 35 is configured to make The second electrode plates of adjacent sub-pixels in the first direction X are connected to each other.
  • the second electrode plates in a sub-pixel row are formed into an integral structure connected to each other through the electrode plate connecting lines 35, and the second electrode plates of the integral structure can be reused as power supply signal lines to ensure that one sub-pixel
  • the plurality of second electrode plates in the pixel row have the same potential, which is beneficial to improve the uniformity of the panel, avoid poor display of the display substrate, and ensure the display effect of the display substrate.
  • the orthographic projection of the edge of the second electrode plate 32 adjacent to the first region R1 on the substrate overlaps with the orthographic projection of the boundary line of the first region R1 and the second region R2 on the substrate, and the second electrode plate
  • the orthographic projection of the edge of 32 adjacent to the third region R3 on the substrate overlaps with the orthographic projection of the boundary line of the second region R2 and the third region R3 on the substrate, that is, the length of the second polar plate 32 is equal to the length of the second region R2
  • the length of the second pole plate 32 refers to the dimension of the second pole plate 32 in the second direction Y.
  • a first insulating layer 91 is arranged on the substrate 10
  • a semiconductor layer is arranged on the first insulating layer 91
  • a second insulating layer 92 covers the semiconductor layer
  • a first conductive layer is arranged On the second insulating layer 92
  • the third insulating layer 93 covers the first conductive layer
  • the second conductive layer is disposed on the third insulating layer 93
  • the second conductive layer at least includes the initial signal line 31 and the second plate of the storage capacitor 32
  • the second pole plate 32 of the storage capacitor is provided with an opening 34
  • the opening 34 exposes the third insulating layer 93 covering the first pole plate 24, the orthographic projection of the second pole plate 32 on the substrate and the first pole plate 24
  • the orthographic projections on the substrate have overlapping regions.
  • a fourth insulating layer pattern is formed.
  • forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the foregoing pattern is formed, and patterning the fourth insulating film by a patterning process to form a pattern covering the second conductive layer.
  • the fourth insulating layer, the fourth insulating layer is provided with a plurality of vias, and the plurality of vias at least include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via
  • the via hole V5 , the sixth via hole V6 , the seventh via hole V7 , the eighth via hole V8 and the ninth via hole V9 are shown in FIGS. 10 a and 10 b
  • FIG. 10 b is a cross-sectional view taken along the line A-A in FIG. 10 a .
  • the first via hole V1 is located in the opening 34 of the second electrode plate 32 , and the orthographic projection of the first via hole V1 on the substrate is located at the position of the orthographic projection of the opening 34 on the substrate.
  • the fourth insulating layer and the third insulating layer in the first via hole V1 are etched away, exposing the surface of the first electrode plate 24 .
  • the first via hole V1 is configured to connect the second electrode of the first transistor T1 formed subsequently to the first electrode plate 24 through the via hole.
  • the second via hole V2 is located in the region where the second electrode plate 32 is located, and the orthographic projection of the second via hole V2 on the substrate is within the range of the orthographic projection of the second electrode plate 32 on the substrate.
  • the fourth insulating layer in the two via holes V2 is etched away, exposing the surface of the second electrode plate 32 .
  • the second via hole V2 is configured so that the subsequently formed first power line is connected to the second electrode plate 32 through the via hole.
  • the second vias V2 serving as power vias may include multiple ones, and the multiple second vias V2 may be arranged in sequence along the second direction Y, and the first power supply lines and the second electrode plates 32 are added. connection reliability.
  • the third via hole V3 is located in the third region R3, the fourth insulating layer, the third insulating layer and the second insulating layer in the third via hole V3 are etched away, exposing the fifth active the surface of the first region of the layer.
  • the third via hole V3 is configured so that the first power supply line formed later is connected to the fifth active layer through the via hole.
  • the fourth via V4 is located in the third region R3, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via V4 are etched away, exposing the sixth active The surface of the second region of the layer (which is also the second region of the seventh active layer).
  • the fourth via hole V4 is configured so that the second electrode of the sixth transistor T6 formed subsequently is connected to the sixth active layer through the via hole, and the second electrode of the seventh transistor T7 formed subsequently is connected to the sixth active layer through the via hole. Seven active layer connections.
  • the fifth via V5 is located in the first region R1, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via V5 are etched away, exposing the fourth active the surface of the first region of the layer.
  • the fifth via hole V5 is configured to connect the data signal line formed subsequently to the fourth active layer through the via hole, and the fifth via hole V5 is called a data writing hole.
  • the sixth via hole V6 is located in the first region R1, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away, exposing the first active The surface of the second region of the layer (which is also the first region of the second active layer).
  • the sixth via hole V6 is configured so that the second electrode of the first transistor T1 formed subsequently is connected to the first active layer through the via hole, and the first electrode of the second transistor T2 formed subsequently is connected to the first active layer through the via hole. Two active layers are connected.
  • the seventh via hole V7 is located in the first region R1, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away, exposing the seventh active The surface of the first region of the layer (which is also the first region of the first active layer).
  • the seventh via hole V7 is configured so that the first electrode of the subsequently formed seventh transistor T7 is connected to the seventh active layer through the via hole, and the first electrode of the subsequently formed first transistor T1 is connected to the seventh active layer through the via hole.
  • An active layer connection is configured so that the first electrode of the subsequently formed seventh transistor T7 is connected to the seventh active layer through the via hole, and the first electrode of the subsequently formed first transistor T1 is connected to the seventh active layer through the via hole.
  • the eighth via hole V8 is located in the first region R1 , and the fourth insulating layer in the eighth via hole V8 is etched away to expose the surface of the shield electrode 33 .
  • the eighth via hole V8 is configured so that the first power supply line formed later is connected to the shield electrode 33 through the via hole.
  • the ninth via hole V9 is located in the first region R1 , and the fourth insulating layer in the ninth via hole V9 is etched away to expose the surface of the initial signal line 31 .
  • the ninth via hole V9 is configured so that the first electrode of the seventh transistor T7 (which is also the first electrode of the first transistor T1 ) to be formed subsequently is connected to the initial signal line 31 through the via hole.
  • a first insulating layer 91 is disposed on the substrate 10
  • a semiconductor layer is disposed on the first insulating layer 91
  • a second insulating layer 92 covers the semiconductor layer
  • a first conductive layer is disposed
  • the third insulating layer 93 covers the first conductive layer
  • the second conductive layer is provided on the third insulating layer 93
  • the fourth insulating layer 94 covers the second conductive layer
  • the fourth insulating layer 94 is provided
  • the plurality of via holes include at least a first via hole V1 and a sixth via hole V6.
  • the fourth insulating layer 94 and the third insulating layer 93 in the first via hole V1 are etched away, exposing the surface of the second electrode plate 32 .
  • the fourth insulating layer 94 , the third insulating layer 93 and the second insulating layer 92 in the sixth via hole V6 are etched away, exposing the surface of the first active layer 11 .
  • a third conductive layer pattern is formed.
  • forming the third conductive layer may include: depositing a third metal thin film on the substrate on which the aforementioned patterns are formed, patterning the third metal thin film by a patterning process, and forming a third metal thin film disposed on the fourth insulating layer
  • the third conductive layer, the third conductive layer at least includes: a first power line 41, a data signal line 42, a first connection electrode 43, a second connection electrode 44 and a third connection electrode 45, as shown in Figure 11a and Figure 11b , Figure 11b is a cross-sectional view taken along the A-A direction in Figure 11a.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the first power line 41 extends along the second direction Y.
  • the first power line 41 is connected to the second electrode plate 32 through the second via V2
  • the shield electrode 33 is connected to the shield electrode 33 through the eighth via hole V8 , and is connected to the fifth active layer through the third via hole V3 , so that the shield electrode 33 and the second electrode plate 32 have the same potential as the first power line 41 . Since the orthographic projection of the shielding electrode 33 on the substrate and the orthographic projection of the subsequently formed data signal line on the substrate have an overlapping area, and the shielding electrode 33 is connected to the first power line 41 , the impact of the data voltage jump on key nodes is effectively shielded. Influence, avoid the data voltage jump to affect the potential of the key node of the pixel driving circuit, and improve the display effect.
  • the data signal line 42 extends along the second direction Y, and the data signal line 42 is connected to the first region of the fourth active layer through the fifth via V5, so that the data signal transmitted by the data signal line 42 Write the fourth transistor T4.
  • the first connection electrode 43 extends along the second direction Y, and its first end passes through the sixth via hole V6 and the second region of the first active layer (which is also the second region of the second active layer). One area) connection, and its second end is connected to the first electrode plate 24 through the first via V1, so that the first electrode plate 24, the second electrode of the first transistor T1 and the first electrode of the second transistor T2 have the same potential.
  • the first connection electrode 43 may serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2.
  • the second connection electrode 44 extends along the second direction Y, its first end is connected to the initial signal line 31 through the ninth via hole V9, and the second end thereof is connected to the seventh via hole V7
  • the first region of the active layer (which is also the first region of the first active layer) is connected so that the first electrode of the seventh transistor T7 and the first electrode of the first transistor T1 have the same potential as the initial signal line 31 .
  • the second connection electrode 44 may serve as the first electrode of the seventh transistor T7 and the first electrode of the first transistor T1.
  • the third connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fourth via hole V4, so that the second region of the sixth transistor T6 The pole and the second pole of the seventh transistor T7 have the same potential.
  • the third connection electrode 45 may serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.
  • the third connection electrode 45 is configured to be connected to a subsequently formed anode.
  • the first power line 41 and the data signal line 42 may be straight lines of equal width, or straight lines of unequal width.
  • a first insulating layer 91 is disposed on the substrate 10
  • a semiconductor layer is disposed on the first insulating layer 91
  • a second insulating layer 92 covers the semiconductor layer
  • a first conductive layer is disposed
  • the third insulating layer 93 covers the first conductive layer
  • the second conductive layer is disposed on the third insulating layer 93
  • the fourth insulating layer 94 covers the second conductive layer
  • the third conductive layer is disposed on the third insulating layer 93.
  • the third conductive layer includes at least a first connection electrode 43 and a third connection electrode 45, and the first connection electrode 43 is connected to the first electrode plate 24 and the first electrode plate 24 and the first electrode plate 43 through the first via hole V1 and the sixth via hole V6 respectively.
  • the first active layer 11 of a transistor T1 is connected.
  • a flat layer pattern is formed.
  • forming the flattening layer pattern may include: coating a flattening film on the substrate on which the aforementioned pattern is formed, patterning the flattening film by a patterning process, forming a flattening layer covering the third conductive layer, and the flattening layer A tenth via hole V10 is provided on the top, as shown in FIG. 12a and FIG. 12b , and FIG. 12b is a cross-sectional view taken along the A-A direction in FIG. 12a .
  • the tenth via hole V10 is located in the region where the third connection electrode 45 is located, and the flat layer in the tenth via hole V10 is removed to expose the surface of the third connection electrode 45.
  • the tenth via hole V10 is configured so that the The anode formed subsequently is connected to the third connection electrode 45 through the via hole.
  • the first insulating layer 91 is disposed on the substrate 10
  • the semiconductor layer is disposed on the first insulating layer 91
  • the second insulating layer 92 covers the semiconductor layer
  • the first conductive layer is disposed
  • the third insulating layer 93 covers the first conductive layer
  • the second conductive layer is disposed on the third insulating layer 93
  • the fourth insulating layer 94 covers the second conductive layer
  • the third conductive layer is disposed on the third insulating layer 93.
  • a flat layer 95 covers the third conductive layer, and a tenth via V10 is provided on the flat layer. The flat layer 95 in the tenth via V10 is removed to expose the surface of the third connection electrode 45 .
  • An anode pattern is formed.
  • forming the anode pattern may include: depositing a transparent conductive film on the substrate on which the aforementioned pattern is formed, and patterning the transparent conductive film by a patterning process to form an anode 71 disposed on the flat layer, as shown in FIG. 13a and 13b, and Fig. 13b is a cross-sectional view taken along the line A-A in Fig. 13a.
  • the anode 71 may be in a hexagonal shape, and the anode 71 is connected to the third connection electrode 45 through the tenth via V10. Since the third connection electrode 45 serves as the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7, the anode 71 is connected to the sixth transistor T6 and the seventh transistor T7, so that the pixel driving circuit can drive the light-emitting device. glow.
  • a first insulating layer 91 is disposed on the substrate 10
  • a semiconductor layer is disposed on the first insulating layer 91
  • a second insulating layer 92 covers the semiconductor layer
  • a first conductive layer is disposed
  • the third insulating layer 93 covers the first conductive layer
  • the second conductive layer is disposed on the third insulating layer 93
  • the fourth insulating layer 94 covers the second conductive layer
  • the third conductive layer is disposed on the third insulating layer 93.
  • the flat layer 95 covers the third conductive layer
  • the anode 71 is disposed on the flat layer 95
  • the anode 71 is connected to the third connection electrode 45 through the tenth via hole.
  • the subsequent preparation process may include: coating a pixel definition film, patterning the pixel definition film through a patterning process to form a pixel definition layer, the pixel definition layer of each sub-pixel is provided with a pixel opening, and the pixel opening is The anode is exposed.
  • the organic light-emitting layer is formed by vapor deposition or inkjet printing process, and a cathode is formed on the organic light-emitting layer.
  • the encapsulation layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer can be made of inorganic materials, the second encapsulation layer can be made of organic materials, and the third encapsulation layer can be made of organic materials.
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that the outside water vapor cannot enter the light emitting structure layer.
  • the substrate may be a flexible substrate, or it may be a rigid substrate.
  • the rigid substrate can be but not limited to one or more of glass and quartz
  • the flexible substrate can be but not limited to polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone , one or more of polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer and a second inorganic material layer, the first flexible material layer and the second flexible material layer
  • the material of the material layer can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated soft polymer film, etc.
  • the material of the first inorganic material layer and the second inorganic material layer Silicon nitride (SiNx) or silicon oxide (SiOx) can be used to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).
  • the first conductive layer, the second conductive layer, and the third conductive layer may adopt a metal material, such as any one of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo).
  • a metal material such as any one of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo).
  • One or more, or alloy materials of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo and the like.
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), It can be a single layer, multiple layers or composite layers.
  • the first insulating layer is called the buffer layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer and the third insulating layer are called the gate insulating (GI) layer
  • the fourth insulating layer is called the interlayer insulation ( ILD) layer.
  • the flat layer can be made of organic materials
  • the transparent conductive film can be made of indium tin oxide ITO or indium zinc oxide IZO.
  • the active layer may use polysilicon (p-Si), that is, the present disclosure is applicable to LTPS thin film transistors.
  • FIG. 14 is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure, illustrating a planar structure of a sub-pixel.
  • the sub-pixels of the display substrate are provided with a first scan signal line 21 , a second scan signal line 22 , a light emission control line 23 , an initial signal line 52 , and a data signal line 61.
  • the first power supply line 62 and the pixel drive circuit, the pixel drive circuit may include a plurality of transistors and a storage capacitor, the storage capacitor includes a first plate and a second plate, and the plurality of transistors may include a first transistor to a seventh transistor,
  • the third transistor is a driving transistor.
  • the display substrate may include a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a Five conductive layers.
  • the first semiconductor layer may include an active layer of a plurality of polysilicon transistors
  • the first conductive layer may include a first scan signal line 21, a second scan signal line 22, a light emission control line 23, a storage capacitor
  • the first electrode plate and the gate electrodes of the plurality of polysilicon transistors, the second conductive layer may include the second electrode plate 32 of the storage capacitor, the electrode plate connecting line 35, the node electrode, the first shielding layer and the second shielding layer
  • the layers may include active layers of multiple oxide transistors
  • the third conductive layer may include first and second auxiliary signal lines 48 and 49 and gate electrodes of multiple oxide transistors
  • the fourth conductive layer may include power connections Line 51 , initial signal line 52 , fifth connection electrode, sixth connection electrode, seventh connection electrode and eighth connection electrode
  • the fifth conductive layer may include data signal line 61 , first power supply line 62 and anode connection electrode 63 .
  • the display substrate may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, a seventh insulating layer, a first planarization layer and a second flat layer, the first insulating layer is arranged between the substrate and the first semiconductor layer, the second insulating layer is arranged between the first semiconductor layer and the first conductive layer, and the third insulating layer is arranged between the first conductive layer and the first conductive layer.
  • the fourth insulating layer is disposed between the second conductive layer and the second semiconductor layer
  • the fifth insulating layer is disposed between the second semiconductor layer and the third conductive layer
  • the sixth insulating layer is disposed between the second conductive layer and the second semiconductor layer.
  • the seventh insulating layer and the first flat layer are arranged between the fourth conductive layer and the fifth conductive layer
  • the second flat layer is arranged between the fifth conductive layer and the anode.
  • the first scan signal line 21 extending along the first direction X is located in the first region R1
  • the first electrode plate and the second electrode plate are located in the second region R2
  • the first scanning signal line 21 extending along the first direction X is located in the first region R1.
  • the second scan signal line 22, the light emission control line 23 and the initial signal line 52 are located in the third region R3.
  • the gate electrode of the first transistor is connected to the second auxiliary signal line
  • the first electrode of the first transistor is connected to the initial signal line 52
  • the second electrode of the first transistor is connected to the first electrode of the second transistor, respectively.
  • the gate electrode of the third transistor is connected to the first electrode plate.
  • the gate electrode of the second transistor is connected to the first auxiliary signal line
  • the second electrode of the second transistor is connected to the second electrode of the third transistor and the first electrode of the sixth transistor, respectively.
  • the first electrode of the third transistor is connected to the second electrode of the fourth transistor and the second electrode of the fifth transistor, respectively.
  • the gate electrode of the fourth transistor is connected to the first scan signal line 21, the first electrode of the fourth transistor is connected to the data signal line 61 through the eighth connection electrode 56, and the second electrode of the fourth transistor is connected to the first electrode of the third transistor connect.
  • the gate electrode of the fifth transistor is connected to the light-emitting signal line 23 , and the first electrode of the fifth transistor is connected to the first power line 62 and the second electrode plate 32 respectively.
  • the gate electrode of the sixth transistor is connected to the light-emitting signal line 23 , and the second electrode of the sixth transistor is connected to the anode of the light-emitting device through the seventh connection electrode and the anode connection electrode 63 .
  • the gate electrode of the seventh transistor is connected to the second scan signal line 22, the first electrode of the seventh transistor is connected to the initial signal line 52, and the second electrode of the seventh transistor is connected to the second electrode of the sixth transistor.
  • the first electrode plate serves as the gate electrode of the third transistor at the same time, the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the third active layer on the substrate have an overlapping area, and the first electrode plate in the overlapping area has an overlapping area.
  • the three active layers serve as channel regions of the third transistor.
  • the structure of the channel region is similar to that in the foregoing embodiments, and the drain end segment of the channel region is in the shape of a fan, which will not be repeated here.
  • the manufacturing process of the display substrate of the present exemplary embodiment may include the following operations.
  • a first semiconductor layer pattern is formed.
  • forming the first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on the substrate, patterning the first semiconductor film through a patterning process, and forming a first semiconductor film covering the substrate.
  • the insulating layer and the first semiconductor layer disposed on the first insulating layer are shown in FIG. 15a and FIG. 15b, and FIG. 15b is a cross-sectional view taken along the direction B-B in FIG. 15a.
  • the first semiconductor layer of each sub-pixel may include the third active layer 13 of the third transistor T3 to the seventh active layer 17 of the seventh transistor T7, and the third active layer 13 to the seventh
  • the active layer 17 is an interconnected one-piece structure.
  • the fourth active layer 14 of the fourth transistor T4 is disposed in the first region R1
  • the third active layer 13 of the third transistor T3 is disposed in the second region R2
  • the third active layer 13 of the fifth transistor T5 is disposed in the second region R2.
  • the fifth active layer 15, the sixth active layer 16 of the sixth transistor T6, and the seventh active layer 17 of the seventh transistor T7 are disposed within the third region R3.
  • the seventh active layer 17 is disposed on the side of the third region R3 away from the second region R2, and the fifth active layer 15 and the sixth active layer 16 are disposed on the side of the third region R3 adjacent to the second region R2.
  • the shape of the third active layer 13 may be in the shape of a "ji"
  • the shape of the fourth active layer 14 may be in the shape of a "1”
  • the shape of the seventh active layer 17 may be an "L" shape.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first and second regions.
  • the first region 13-1 of the third active layer 13 simultaneously serves as the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15, That is, the first region 13-1 of the third active layer 13, the second region 14-2 of the fourth active layer 14, and the second region 15-2 of the fifth active layer 15 are connected to each other.
  • the second region 13-2 of the third active layer 13 simultaneously serves as the first region 16-1 of the sixth active layer 16, that is, the second region 13-2 of the third active layer 13 and the sixth active layer 16
  • the first regions 16-1 are connected to each other.
  • the second region 16-2 of the sixth active layer 16 simultaneously serves as the second region 17-2 of the seventh active layer 17, that is, the second region 16-2 of the sixth active layer 16 and the seventh active layer 17
  • the second regions 17-2 are connected to each other.
  • the first region 14-1 of the fourth active layer 14, the first region 15-1 of the fifth active layer 15, and the first region 17-1 of the seventh active layer 17 are provided separately.
  • the first semiconductor layer may adopt polysilicon (p-Si), that is, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are LTPS thin film transistors.
  • the display substrate includes a first insulating layer 91 disposed on the substrate 10 and a first semiconductor layer disposed on the first insulating layer 91, and the first semiconductor layer may include a sixth active layer Layer 16.
  • a first conductive layer pattern is formed.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first metal film on the substrate on which the foregoing pattern is formed, and patterning the first metal film through a patterning process to form A second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, the first conductive layer pattern at least includes: a first scan signal line 21, a second scan signal line 22, and a light-emitting control line 23 and the first plate 24 of the storage capacitor, as shown in FIG. 16a and FIG. 16b , and FIG. 16b is a cross-sectional view taken along the direction B-B in FIG. 16a .
  • the first conductive layer may be referred to as a first gate metal (GATE 1) layer.
  • the first scan signal line 21 , the second scan signal line 22 and the light emission control line 23 extend along the first direction X.
  • the first scan signal line 21 is arranged in the first region R1
  • the second scan signal line 22 and the light emission control line 23 are arranged in the third region R3
  • the second scan signal line 22 is located in the light emission control line 23 away from the second region R2.
  • the first plate 24 of the storage capacitor is arranged in the second region R2.
  • the first electrode plate 24 may be rectangular, the corners of the rectangle may be provided with chamfers, and the orthographic projection of the first electrode plate 24 on the substrate and the third active layer of the third transistor T3 are at The orthographic projection on the substrate has an overlapping area, the first electrode plate 24 serves as the gate electrode of the third transistor T3 at the same time, and the area where the third active layer of the third transistor T3 overlaps with the first electrode plate 24 serves as the gate electrode of the third transistor T3.
  • a channel region, one end of the channel region is connected to the first region of the third active layer, and the other end is connected to the second region of the third active layer.
  • the region where the first scan signal line 21 overlaps with the fourth active layer of the fourth transistor T4 serves as the gate electrode of the fourth transistor T4, and the region where the first electrode plate 24 overlaps with the third active layer of the third transistor T3
  • the region where the light emission control line 23 overlaps with the fifth active layer of the fifth transistor T5 serves as the gate electrode of the fifth transistor T5
  • the light emission control line 23 is connected to the sixth active layer of the sixth transistor T6.
  • the region where the source layers overlap serves as the gate electrode of the sixth transistor T6, and the region where the second scan signal line 22 and the seventh active layer of the seventh transistor T7 overlap serves as the gate electrode of the seventh transistor T7.
  • the first conductive layer can be used as a shield to conduct a conductorization process on the semiconductor layer, and the semiconductor layers in the region shielded by the first conductive layer form the third transistors T3 to T7 In the channel region of the transistor T7, the semiconductor layer in the region not shielded by the first conductive layer is conductive, that is, the first and second regions from the third active layer to the seventh active layer are all conductive.
  • the structure of the channel region of the third transistor T3 is the same as the previous embodiment, and the drain end segment of the channel region is fan-shaped, thereby improving the problem of output unsaturation of the thin film transistor caused by the shortening of the channel , the output characteristics of the thin film transistor can be made flat, and details are not repeated here.
  • the short-channel driving transistor with flat output characteristics proposed by the exemplary embodiments of the present disclosure can not only save space and facilitate high-resolution display, but also reduce the channel length and reduce the threshold voltage Vth of the driving transistor, which is conducive to reducing power consumption.
  • the display substrate includes a first insulating layer 91 disposed on the substrate 10, a first semiconductor layer disposed on the first insulating layer 91, and a second insulating layer covering the first semiconductor layer 92 and a first conductive layer disposed on the second insulating layer 92
  • the first conductive layer may include the first scan signal line 21 and the light emission control line 23 .
  • a second conductive layer pattern is formed.
  • forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second metal film on the substrate on which the foregoing pattern is formed, and patterning the second metal film using a patterning process to form The third insulating layer 93 covering the first conductive layer, and the second conductive layer pattern disposed on the third insulating layer 93, the second conductive layer pattern at least includes: the second electrode plate 32 of the storage capacitor and the electrode plate connecting line 35 , the node electrode 36 , the first shielding layer 37 and the second shielding layer 38 , as shown in FIGS. 17 a and 17 b , and FIG. 17 b is a cross-sectional view taken along the direction B-B in FIG. 17 a .
  • the second conductive layer may be referred to as a second gate metal (GATE 2) layer.
  • the second electrode plate 32 of the storage capacitor is disposed in the second region R2 between the second blocking layer 38 and the light-emitting control line 23 .
  • the contour of the second pole plate 32 may be rectangular, and the corners of the rectangle may be chamfered.
  • the orthographic projection of the second pole plate 32 on the substrate and the orthographic projection of the first pole plate 24 on the substrate may overlap.
  • the second pole plate 32 is provided with an opening 34, and the opening 34 may be located in the middle of the second region R2.
  • the opening 34 may be rectangular, so that the second electrode plate 32 forms an annular structure.
  • the opening 34 exposes the third insulating layer 93 covering the first electrode plate 24 , and the orthographic projection of the first electrode plate 24 on the substrate includes the orthographic projection of the opening 34 on the substrate.
  • the opening 34 is configured to accommodate a subsequently formed first via hole, and the first via hole is located in the opening 34 and exposes the first electrode plate 24 so that the second electrode of the subsequently formed first transistor T1 connected to the first pole plate 24 .
  • the electrode plate connecting line 35 is disposed between the second electrode plates 32 of adjacent sub-pixels in the first direction X, and the first end of the electrode plate connecting line 35 is connected to the second electrode plate 32 of this sub-pixel. connection, the second end of the plate connecting line 35 extends along the first direction X, and is connected to the second plate 32 of the adjacent sub-pixels in the first direction X, that is, the plate connecting line 35 is configured to make the first direction X
  • the second plates of the upper adjacent sub-pixels are connected to each other.
  • the second electrode plates in adjacent sub-pixels are formed into an interconnected integrated structure through the electrode plate connecting lines 35, and the second electrode plates of the integrated structure can be reused as power supply signal lines to ensure that the adjacent sub-pixels are connected to each other.
  • the second electrode plates in the sub-pixels have the same potential, which is beneficial to improve the uniformity of the panel, avoid poor display of the display substrate, and ensure the display effect of the display substrate.
  • the orthographic projection of the edge of the second electrode plate 32 adjacent to the first region R1 on the substrate overlaps with the orthographic projection of the boundary line of the first region R1 and the second region R2 on the substrate, and the second electrode plate
  • the orthographic projection of the edge of 32 adjacent to the third region R3 on the substrate overlaps with the orthographic projection of the boundary line of the second region R2 and the third region R3 on the substrate, that is, the length of the second polar plate 32 is equal to the length of the second region R2 .
  • the node electrode 36 is disposed in the first region R1, and the orthographic projection of the node electrode 36 on the substrate is within the range of the orthographic projection of the first scan signal line 21 on the substrate.
  • the first shielding layer 37 and the second shielding layer 38 extend along the first direction X and are disposed in the first region R1, and the first shielding layer 37 is located on the first scan signal line 21 away from the second region R2
  • the second blocking layer 38 is located on the side of the first scan signal line 21 adjacent to the second region R2.
  • the first shielding layer 37 is configured as a shielding layer for the first transistor, shielding the channel of the first transistor
  • the second shielding layer 38 is configured as a shielding layer for the second transistor, shielding the channel of the second transistor. The channel ensures the electrical properties of the oxide first transistor and the oxide second transistor.
  • the first insulating layer 91 is disposed on the substrate 10
  • the semiconductor layer is disposed on the first insulating layer 91
  • the second insulating layer 92 covers the semiconductor layer
  • the first conductive layer is disposed On the second insulating layer 92
  • the third insulating layer 93 covers the first conductive layer
  • the second conductive layer is disposed on the third insulating layer 93
  • the second conductive layer at least includes the plate connecting line 35 and the second shielding layer 38 .
  • a second semiconductor layer pattern is formed.
  • forming the second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a second semiconductor film on the substrate on which the foregoing pattern is formed, and patterning the second semiconductor film through a patterning process to form The fourth insulating layer covering the substrate and the second semiconductor layer disposed on the fourth insulating layer are shown in FIG. 18a and FIG. 18b, and FIG. 18b is a cross-sectional view taken along the direction B-B in FIG. 18a.
  • the second semiconductor layer of each sub-pixel may include the first active layer 11 of the first transistor T1 and the second active layer 12 of the second transistor T2, the first active layer 11 and the second active layer 12
  • the source layer 12 may be an interconnected unitary structure.
  • the shapes of the first active layer 11 and the second active layer 12 may be in a "1" shape.
  • the first region of the first active layer 11 is adjacent to the first region of the seventh active layer, and the second region of the first active layer 11 serves as the first region of the second active layer 12 at the same time.
  • the second region of the third active layer is adjacent to the second region of the third active layer.
  • the second semiconductor layer may use oxide, that is, the first transistor and the second transistor are oxide thin film transistors.
  • the first insulating layer 91 is disposed on the substrate 10
  • the first semiconductor layer is disposed on the first insulating layer 91
  • the second insulating layer 92 covers the first semiconductor layer
  • the second insulating layer 92 covers the first semiconductor layer.
  • a conductive layer is provided on the second insulating layer 92
  • the third insulating layer 93 covers the first conductive layer
  • the second conductive layer is provided on the third insulating layer 93
  • the fourth insulating layer 94 covers the second conductive layer
  • the second semiconductor layer includes at least the second active layer 12 .
  • a third conductive layer pattern is formed.
  • forming the third conductive layer pattern may include: sequentially depositing a fifth insulating film and a third metal film on the substrate on which the foregoing pattern is formed, and applying a patterning process to the third metal film and the fifth insulating film Patterning is performed to form a fifth insulating layer disposed on the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, the third conductive layer pattern at least including: the first auxiliary signal line 48 and the second The auxiliary signal line 49 is shown in Fig. 19a and Fig. 19b, and Fig. 19b is a cross-sectional view taken along the line B-B in Fig. 19a.
  • the third conductive layer may be referred to as a third gate metal (GATE3) layer.
  • the first auxiliary signal line 48 and the second auxiliary signal line 49 extend along the first direction X and are disposed in the first region R1, and the first auxiliary signal line 48 and the first auxiliary signal line 49
  • the scan signal line 21 is close to and has the same signal as the first scan signal line 21
  • the second auxiliary signal line 49 is close to the second scan signal line 22 on the Y side in the second direction and has the same signal as the second scan signal line 22 .
  • the first auxiliary signal line 48 and the first scan signal line 21 may be connected to the same signal source
  • the second auxiliary signal line 49 and the second scan signal line 22 may be connected to the same signal source.
  • the region where the first auxiliary signal line 48 overlaps with the second active layer serves as the second gate electrode of the second transistor, and the region where the second auxiliary signal line 49 overlaps with the first active layer serves as the first gate electrode. the first gate electrode of the transistor.
  • the orthographic projection of the first auxiliary signal line 48 on the substrate and the orthographic projection of the second shielding layer 38 on the substrate have an overlapping area
  • the orthographic projection of the shielding layer 37 on the substrate has an overlapping area, so the first shielding layer 37 can serve as a shielding layer for the first transistor, and the second shielding layer 38 can serve as a shielding layer for the second transistor.
  • the first insulating layer 91 is disposed on the substrate 10
  • the semiconductor layer is disposed on the first insulating layer 91
  • the second insulating layer 92 covers the first semiconductor layer
  • the first conductive layer is layer is arranged on the second insulating layer 92
  • the third insulating layer 93 covers the first conductive layer
  • the second conductive layer is arranged on the third insulating layer 93
  • the fourth insulating layer 94 covers the second conductive layer
  • the second semiconductor layer is arranged On the fourth insulating layer 94
  • the fifth insulating layer 95 is provided on the second active layer 12 in the second semiconductor layer
  • the first auxiliary signal line 48 is provided on the fifth insulating layer 95 .
  • the orthographic projection of the first auxiliary signal line 48 and the second auxiliary signal line 49 on the substrate is substantially the same as the orthographic projection of the fifth insulating layer 95 on the substrate, or the fifth insulating layer 95 is
  • the orthographic projection on the substrate may be wider than the orthographic projection of the first auxiliary signal line 48 and the second auxiliary signal line 49 on the substrate, so as to prevent the first auxiliary signal line 48 and the second auxiliary signal line 49 from being mixed with the second auxiliary signal line 48 during the manufacturing process.
  • the active layer 12 is in contact.
  • the fifth insulating film may not be patterned, and only the third metal film may be patterned to form the fifth insulating layer 95 covering the second active layer 12 and the fifth insulating layer 95 covering the entire substrate.
  • forming the polysilicon via pattern may include: depositing a sixth insulating film on the substrate on which the foregoing pattern is formed, patterning the sixth insulating film by a patterning process, and forming a sixth insulating film covering the third conductive layer Six insulating layers, the sixth insulating layer is provided with a plurality of via holes, and the plurality of via holes at least include: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole
  • the hole V5, the sixth via hole V6, the seventh via hole V7 and the thirteenth via hole V13 are shown in Figs. 20a and 20b, and Fig. 20b is a cross-sectional view taken along the B-B direction in Fig. 20a.
  • the first via hole V1 is located in the opening 34 of the second electrode plate 32, and the orthographic projection of the first via hole V1 on the substrate is located at Within the range, the sixth insulating layer, the fourth insulating layer and the third insulating layer in the first via hole V1 are etched away, exposing the surface of the first electrode plate 24 .
  • the first via hole V1 is configured to connect the second electrode of the first transistor T1 formed subsequently to the first electrode plate 24 through the via hole.
  • the second via hole V2 is located in the region where the second electrode plate 32 is located, and the orthographic projection of the second via hole V2 on the substrate is within the range of the orthographic projection of the second electrode plate 32 on the substrate.
  • the sixth insulating layer and the fourth insulating layer in the two via holes V2 are etched away, exposing the surface of the second electrode plate 32 .
  • the second via hole V2 is configured so that the subsequently formed first power line is connected to the second electrode plate 32 through the via hole.
  • the second vias V2 serving as power vias may include multiple ones, and the multiple second vias V2 may be arranged in sequence along the second direction Y, and the first power supply lines and the second electrode plates 32 are added. connection reliability.
  • the third via hole V3 is located in the third region R3, the sixth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the third via hole V3 are etched away, exposing the surface of the first region of the fifth active layer.
  • the third via hole V3 is configured so that the first power supply line formed later is connected to the fifth active layer through the via hole.
  • the fourth via hole V4 is located in the third region R3, the sixth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via hole V4 are etched away, exposing the surface of the second region of the sixth active layer (also the second region of the seventh active layer).
  • the fourth via hole V4 is configured so that the second electrode of the sixth transistor T6 formed subsequently is connected to the sixth active layer through the via hole, and the second electrode of the seventh transistor T7 formed subsequently is connected to the sixth active layer through the via hole. Seven active layer connections.
  • the fifth via hole V5 is located in the first region R1, and the sixth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away and exposed the surface of the first region of the fourth active layer.
  • the fifth via hole V5 is configured to connect the data signal line formed subsequently to the fourth active layer through the via hole.
  • the sixth via hole V6 is located in the second region R2, the sixth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away, exposing surface of the first region of the sixth active layer (also the second region of the third active layer).
  • the sixth via hole V6 is configured to connect the first electrode of the sixth transistor T6 (which is also the second electrode of the first transistor T1 and the first electrode of the second transistor T2) to the sixth active layer through the via hole. .
  • the seventh via hole V7 is located in the third region R3, and the sixth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away and exposed the surface of the first region of the seventh active layer.
  • the seventh via hole V7 is configured so that the first electrode of the seventh transistor T7 formed subsequently is connected to the seventh active layer through the via hole.
  • the thirteenth via hole V13 is located in the first region R1 , and the sixth insulating layer and the fourth insulating layer in the thirteenth via hole V13 are etched away, exposing the surface of the node electrode 36 .
  • the thirteenth via hole V13 is configured so that the second electrode of the first transistor T1 and the first electrode of the second transistor T2 to be formed later are connected to the node electrode 36 through the via hole.
  • the first insulating layer 91 is disposed on the substrate 10
  • the semiconductor layer is disposed on the first insulating layer 91
  • the second insulating layer 92 covers the first semiconductor layer
  • the first conductive layer is layer is arranged on the second insulating layer 92
  • the third insulating layer 93 covers the first conductive layer
  • the second conductive layer is arranged on the third insulating layer 93
  • the fourth insulating layer 94 covers the second conductive layer
  • the second semiconductor layer is arranged On the fourth insulating layer 94
  • the fifth insulating layer 95 is provided on the second semiconductor layer
  • the third conductive layer is provided on the fifth insulating layer 95
  • the sixth insulating layer 96 covers the third conductive layer
  • the sixth insulating layer 96 A plurality of via holes are provided on the top, and the plurality of via holes include at least a fourth via hole V4 and a sixth via hole V6.
  • the sixth insulating layer 94, the fourth insulating layer 94, the third insulating layer 93 and the second insulating layer 92 in the fourth via V4 and the sixth via V6 are etched away, exposing two parts of the sixth active layer respectively. end surface.
  • forming the oxide via hole pattern may include: on the substrate on which the foregoing pattern is formed, using a patterning process to form a plurality of via holes, the plurality of via holes at least include: a fourteenth via hole V14 , a tenth via hole V14 , a tenth via hole
  • the fifth via hole V15 and the sixteenth via hole V16 are shown in FIG. 21 a and FIG. 21 b
  • FIG. 21 b is a cross-sectional view taken along the direction B-B in FIG. 21 a .
  • the fourteenth via hole V14 is located in the first region R1, and the sixth insulating layer in the fourteenth via hole V14 is etched away, exposing the first region (also the first region of the second active layer) of the second active layer. the surface of the second region of an active layer).
  • the fifteenth via hole V15 is located in the second region R2, and the sixth insulating layer in the fifteenth via hole V15 is etched away, exposing the surface of the second region of the second active layer.
  • the sixteenth via hole V16 is located in the third region R3, and the sixth insulating layer in the sixteenth via hole V16 is etched away, exposing the surface of the first region of the first active layer.
  • the first insulating layer 91 is disposed on the substrate 10
  • the semiconductor layer is disposed on the first insulating layer 91
  • the second insulating layer 92 covers the first semiconductor layer
  • the first conductive layer is layer is arranged on the second insulating layer 92
  • the third insulating layer 93 covers the first conductive layer
  • the second conductive layer is arranged on the third insulating layer 93
  • the fourth insulating layer 94 covers the second conductive layer
  • the second semiconductor layer is arranged On the fourth insulating layer 94
  • the fifth insulating layer 95 is provided on the second semiconductor layer
  • the third conductive layer is provided on the fifth insulating layer 95
  • the sixth insulating layer 96 covers the third conductive layer
  • the sixth insulating layer 96 A plurality of via holes are provided on the top, and the plurality of via holes include at least a fourth via hole V4, a sixth via hole V6, a fourteenth via hole V14 and a fifteen
  • the sixth insulating layer 94, the fourth insulating layer 94, the third insulating layer 93 and the second insulating layer 92 in the fourth via V4 and the sixth via V6 are etched away, exposing two parts of the sixth active layer respectively.
  • the surfaces of the ends, the sixth insulating layer 94 in the fourteenth via hole V14 and the fifteenth via hole V15 are etched away, respectively exposing the surfaces of both ends of the second active layer.
  • a fourth conductive layer pattern is formed.
  • forming the fourth conductive layer may include: depositing a fourth metal thin film on the substrate on which the aforementioned patterns are formed, patterning the fourth metal thin film by a patterning process, and forming a fourth metal thin film disposed on the sixth insulating layer
  • the fourth conductive layer, the fourth conductive layer at least includes: power supply connection line 51, initial signal line 52, fifth connection electrode 53, sixth connection electrode 54, seventh connection electrode 55 and eighth connection electrode 56, as shown in Figure 22a
  • FIG. 22b is a cross-sectional view taken along the line B-B in FIG. 22a.
  • the fourth conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the zigzag-shaped power supply connection line 51 generally extends along the second direction Y, and the power supply connection line 51 is connected to the second electrode plate 32 through the second via V2 on the one hand, On the other hand, it is connected to the fifth active layer through the third via hole V3, and the power supply connection line 51 is configured to be connected to the first power supply line formed subsequently.
  • the initial signal line 52 extends along the first direction X and is disposed in the third region R3, and on the one hand, the initial signal line 52 is connected to the first region of the seventh active layer through the seventh via hole V7 On the other hand, it is connected to the first region of the first active layer through the sixteenth via V16, so that the first electrode of the seventh transistor T7 and the first electrode of the first transistor T1 have the same potential as the initial signal line 52 .
  • the fifth connection electrode 53 may have a "C" shape, the first end of which is connected to the first electrode plate 24 through the first via hole V1, and the second end of which is connected to the first electrode plate 24 through the fourteenth via hole V14.
  • the first region of the two active layers (also the second region of the first active layer) is connected, and the region between the first end and the second end is connected to the node electrode 36 through the thirteenth via V13, so that the first The plate 24, the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the node electrode 36 have the same potential.
  • the fifth connection electrode 53 may serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2.
  • the sixth connection electrode 54 may have a rectangular shape, and the sixth connection electrode 54 communicates with the first region of the sixth active layer (also the second region of the third active layer through the sixth via V6 on the one hand) On the other hand, it is connected to the second region of the second active layer through the fifteenth via V15, so that the second pole of the second transistor T2, the second pole of the third transistor T3 and the first pole of the sixth transistor One pole has the same potential.
  • the sixth connection electrode 54 may serve as the second electrode of the third transistor T3 and the second electrode of the second transistor T2.
  • the seventh connection electrode 55 may have a rectangular shape, and the seventh connection electrode 55 communicates with the second region of the sixth active layer (also the second region of the seventh active layer) through the fourth via hole V4 connected so that the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7 have the same potential.
  • the seventh connection electrode 55 may serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.
  • the seventh connection electrode 55 is configured to be connected to a subsequently formed anode connection electrode.
  • the eighth connection electrode 56 is connected with the first region of the fourth active layer through the fifth via hole V5. In an exemplary embodiment, the eighth connection electrode 56 is configured to be connected to a subsequently formed data signal line, so that the data signal transmitted by the data signal line is written into the fourth transistor T4.
  • the first insulating layer 91 is disposed on the substrate 10
  • the semiconductor layer is disposed on the first insulating layer 91
  • the second insulating layer 92 covers the first semiconductor layer
  • the first conductive layer is layer is arranged on the second insulating layer 92
  • the third insulating layer 93 covers the first conductive layer
  • the second conductive layer is arranged on the third insulating layer 93
  • the fourth insulating layer 94 covers the second conductive layer
  • the second semiconductor layer is arranged On the fourth insulating layer 94
  • the fifth insulating layer 95 is provided on the second semiconductor layer
  • the third conductive layer is provided on the fifth insulating layer 95
  • the sixth insulating layer 96 covers the third conductive layer
  • the sixth insulating layer 96 There are a plurality of via holes on it, the fourth conductive layer is arranged on the sixth insulating layer 96, and the fourth conductive layer at least includes the fifth connection electrode 53, the sixth connection
  • a seventh insulating layer and a first planarization layer pattern are formed.
  • forming the pattern of the seventh insulating layer and the first flattening layer may include: on the substrate on which the foregoing patterns are formed, firstly depositing a layer of a seventh insulating film, and then coating a layer of the first flattening film, using the pattern
  • the seventh insulating film and the first flat film are patterned by the chemical process to form a seventh insulating layer covering the fourth conductive layer and a first flat layer covering the seventh insulating layer, and the seventh insulating layer and the first flat layer are arranged on the
  • There are a plurality of via holes and the plurality of via holes include at least the twentieth via hole V20, the twenty-first via hole V21 and the twenty-second via hole V22, as shown in FIG. 23a and FIG. 23b, and FIG. 23b is in FIG. 23a Sectional view from B-B.
  • the twentieth via hole V20 is located in the region where the seventh connection electrode 55 is located, and the first flat layer and the seventh insulating layer in the twentieth via hole V20 are removed, exposing the surface of the seventh connection electrode 55 , the twentieth via hole V20 is configured so that the anode connection electrode formed subsequently is connected to the seventh connection electrode 55 through the via hole.
  • the twenty-first via hole V21 is located in the region where the eighth connection electrode 56 is located, the first flat layer and the seventh insulating layer in the twenty-first via hole V21 are removed, exposing the surface of the eighth connection electrode 56, and the twentieth A via hole V21 is configured so that the data signal line formed later is connected to the eighth connection electrode 56 through the via hole.
  • the twenty-second via hole V22 is located in the area where the power connection line 51 is located.
  • the first flat layer and the seventh insulating layer in the twenty-second via hole V22 are removed to expose the surface of the power supply connection line 51.
  • the hole V22 is configured so that the first power line formed later is connected to the power connection line 51 through the via hole.
  • the first insulating layer 91 is disposed on the substrate 10
  • the semiconductor layer is disposed on the first insulating layer 91
  • the second insulating layer 92 covers the first semiconductor layer
  • the first conductive layer is layer is arranged on the second insulating layer 92
  • the third insulating layer 93 covers the first conductive layer
  • the second conductive layer is arranged on the third insulating layer 93
  • the fourth insulating layer 94 covers the second conductive layer
  • the second semiconductor layer is arranged On the fourth insulating layer 94
  • the fifth insulating layer 95 is provided on the second semiconductor layer
  • the third conductive layer is provided on the fifth insulating layer 95
  • the sixth insulating layer 96 covers the third conductive layer
  • the fourth conductive layer is provided On the sixth insulating layer 96, the seventh insulating layer 97 and the first flat layer 98 cover the fourth conductive layer, and a plurality of via holes are opened on the seventh insulating layer
  • a fifth conductive layer pattern is formed.
  • forming the fifth conductive layer may include: depositing a fifth metal thin film on the substrate on which the aforementioned pattern is formed, patterning the fifth metal thin film by a patterning process, and forming the fifth metal thin film disposed on the first flat layer
  • the fifth conductive layer, the fifth conductive layer at least includes: data signal lines 61, first power lines 62 and anode connection electrodes 63, as shown in Figure 24a and Figure 24b, Figure 24b is a cross-sectional view of Figure 24a shown in the direction B-B .
  • the fifth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the data signal line 61 extends along the second direction Y, and the data signal line 61 is connected to the eighth connection electrode 56 through the twenty-first via hole V21. Since the eighth connection electrode 56 is connected to the first region of the fourth active layer through the fifth via hole, the connection between the data signal line 61 and the first electrode of the fourth transistor T4 is realized, and the data signal transmitted by the data signal line is realized.
  • the first power supply line 62 generally extends along the second direction Y, and is connected to the power supply connection line 51 through the twenty-second via hole V22 , so that the power supply connection line 51 has the same potential as the first power supply line 62 .
  • the first power supply line 62 can be rectangular, so that the first power supply line 62 can effectively shield the key nodes of the pixel driving circuit, avoid the potential influence of the key nodes of the pixel driving circuit, and improve the display effect.
  • the anode connection electrode 63 may be rectangular, the anode connection electrode 63 is connected to the seventh connection electrode 55 through the twentieth via hole V20 , and the anode connection electrode 63 is configured to be connected to a subsequently formed anode.
  • the first insulating layer 91 is disposed on the substrate 10
  • the semiconductor layer is disposed on the first insulating layer 91
  • the second insulating layer 92 covers the first semiconductor layer
  • the first conductive layer is layer is arranged on the second insulating layer 92
  • the third insulating layer 93 covers the first conductive layer
  • the second conductive layer is arranged on the third insulating layer 93
  • the fourth insulating layer 94 covers the second conductive layer
  • the second semiconductor layer is arranged On the fourth insulating layer 94
  • the fifth insulating layer 95 is provided on the second semiconductor layer
  • the third conductive layer is provided on the fifth insulating layer 95
  • the sixth insulating layer 96 covers the third conductive layer
  • the fourth conductive layer is provided On the sixth insulating layer 96, the seventh insulating layer 97 and the first flat layer 98 cover the fourth conductive layer, the fifth conductive layer is disposed on the first flat layer 98, the
  • forming the second flattening layer pattern may include: coating a second flattening film on the substrate on which the foregoing pattern is formed, and patterning the second flattening film by a patterning process to form a covering fifth conductive layer At least a twenty-third via hole V23 is disposed on the second flat layer, as shown in FIG. 25 .
  • the twenty-third via hole V23 is located in the region where the anode connection electrode 63 is located, the second flat layer in the twenty-third via hole V23 is removed, exposing the surface of the anode connection electrode 63, and the twentieth The three via holes V23 are arranged so that the anode to be formed subsequently is connected to the anode connection electrode 63 through the via holes.
  • An anode pattern is formed.
  • forming the anode pattern may include: depositing a transparent conductive film on the substrate on which the aforementioned pattern is formed, patterning the transparent conductive film by a patterning process to form the anode 71 disposed on the second flat layer, As shown in Figure 26.
  • the anode 71 has a hexagonal shape, and the anode 71 is connected to the anode connection electrode 63 through the twenty-third via hole V23. Since the anode connection electrode 63 is connected to the seventh connection electrode 55 through the twentieth via hole, and the seventh connection electrode 55 is connected to the sixth active layer through the fourth via hole, the pixel driving circuit can drive the light emitting device to emit light.
  • the subsequent preparation process may include: coating a pixel definition film, patterning the pixel definition film through a patterning process to form a pixel definition layer, the pixel definition layer of each sub-pixel is provided with a pixel opening, and the pixel opening is The anode is exposed.
  • the organic light-emitting layer is formed by vapor deposition or inkjet printing process, and a cathode is formed on the organic light-emitting layer.
  • the encapsulation layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer can be made of inorganic materials, the second encapsulation layer can be made of organic materials, and the third encapsulation layer can be made of organic materials.
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that the outside water vapor cannot enter the light emitting structure layer.
  • the structure and the preparation process thereof shown above in the present disclosure are only an exemplary illustration. In the exemplary embodiment, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • the display substrate of the present disclosure can be applied to a pixel driving circuit. In other display devices, such as quantum dot display, etc., the present disclosure does not limit it here.
  • the display substrate provided by the present disclosure increases the area of the channel near one end of the drain electrode by setting the drain end segment of the channel in the third transistor into a fan shape, Under the same drain electrode bias, the drain electric field can be dispersed, thereby reducing the lateral electric field, and the drain electrode depletion region is shortened in the channel direction, thereby improving the output unsaturation problem of the thin film transistor caused by the shortening of the channel.
  • the output characteristics of the thin film transistor can be made flat.
  • the short-channel driving transistor with flat output characteristic proposed by the exemplary embodiment of the present disclosure can not only save space and facilitate high-resolution display, but also reduce the channel length and the threshold voltage of the driving transistor, which is beneficial to reduce power consumption.
  • the preparation process of the present disclosure can be well compatible with the existing preparation process, and the process is simple to realize, easy to implement, high in production efficiency, low in production cost and high in yield.
  • the present disclosure also provides a method for fabricating a display substrate, so as to fabricate the display substrate provided by the above embodiments.
  • the display substrate in a plane parallel to the display substrate, the display substrate includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit, and the pixel driving circuit includes at least a driving transistor; the manufacturing method may include :
  • a semiconductor layer or a first semiconductor layer is formed on a substrate; the semiconductor layer or the first semiconductor layer includes at least an active layer of a driving transistor, and the active layer of the driving transistor includes a channel region, and the channel region includes a a drain end segment extending in a first direction, a source end segment extending along the first direction, and an intermediate segment located between the drain end segment and the source end segment; the drain end segment is at a first end away from the intermediate segment having a first width, the drain end segment has a second width at the second end near the middle segment; the first width is greater than the second width; the width is in the second direction of the drain end segment size, the first direction intersects the second direction.
  • the active layer of the driving transistor further includes a first region connected to the drain terminal segment and a second region connected to the source terminal segment, and one end of the first region is connected to the A first end of the drain end segment is connected, and the other end of the first region is connected to a transistor receiving a data signal; in a plane parallel to the display substrate, the shape of the source end segment includes a rectangle.
  • the shape of the drain segment in a plane parallel to the display substrate, includes a trapezoid, the trapezoid includes a trapezoid lower bottom and a trapezoid upper bottom, and the first end of the drain segment is a trapezoid lower
  • the bottom has a first width
  • the second end of the drain end section is a trapezoidal upper bottom with a second width.
  • the shape of the drain segment includes a combination of a trapezoid and a rectangle, the trapezoid includes a trapezoid lower base and a trapezoid upper base, and the rectangle includes a rectangular lower side and a rectangle.
  • the upper side of the rectangle; the first end of the drain end segment is a trapezoidal lower bottom with a first width, the upper trapezoidal bottom is connected to the lower side of the rectangle and has a second width, and the second end of the drain segment is the top of the rectangle.
  • the shape of the drain segment in a plane parallel to the display substrate, includes a combination of a rectangle and a trapezoid, the rectangle includes a lower side of a rectangle and an upper side of the rectangle, and the trapezoid includes a lower base and a trapezoid upper bottom; the first end of the drain end section is a rectangular lower side, the rectangular upper side is connected with the trapezoidal lower bottom and has a first width, and the second end of the drain end section is a trapezoidal upper bottom with a second width.
  • the shape of the drain segment in a plane parallel to the display substrate, includes a combination of a first trapezoid and a second trapezoid, and the first trapezoid includes a first trapezoid lower base and a first trapezoid
  • the upper bottom, the second trapezoid includes a second trapezoidal lower bottom and a second trapezoidal upper bottom; the first end of the drain end section is a first trapezoidal lower bottom with a first width, and the first trapezoidal upper bottom and the The second trapezoidal lower bottom is connected, and the second end of the drain end section is the second trapezoidal upper bottom and has a second width.
  • the ratio of the first width to the second width is 1.5 to 5.
  • the angle between the side of the trapezoid and the first direction is 20° to 60°.
  • the display substrate in a plane perpendicular to the display substrate, includes a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially arranged on a substrate;
  • the semiconductor layer includes The active layer of a plurality of polysilicon transistors, the first conductive layer includes the gate electrodes of the plurality of polysilicon transistors and the first plate of the storage capacitor, the second conductive layer includes the second plate of the storage capacitor, the first plate
  • the three conductive layers include first power lines, data signal lines, and first and second electrodes of a plurality of polysilicon transistors.
  • the display substrate in a plane perpendicular to the display substrate, includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, and a third conductive layer that are sequentially arranged on the substrate layer, a fourth conductive layer and a fifth conductive layer;
  • the first semiconductor layer includes active layers of a plurality of polysilicon transistors
  • the first conductive layer includes gate electrodes of a plurality of polysilicon transistors and a first plate of a storage capacitor
  • the second conductive layer includes the second electrode plate of the storage capacitor
  • the second semiconductor layer includes the active layers of a plurality of oxide transistors
  • the third conductive layer includes the gate electrodes of a plurality of oxide transistors
  • the fourth conductive layer includes first and second electrodes of a plurality of polysilicon transistors and first and second electrodes of a plurality of oxide transistors
  • the fifth conductive layer includes a first power supply line and a data signal line.
  • the middle segment of the channel region includes a second channel segment, a third channel segment and a fourth channel segment; the second end of the drain segment is connected to the second channel segment.
  • the first end of the second channel segment is connected to the first end of the third channel segment after extending in the opposite direction of the second direction; the first end of the third channel segment After extending along the first direction, the two ends are connected to the first end of the fourth channel segment; the second end of the fourth channel segment is connected to the first end of the source end segment after extending along the second direction ; the second end of the source end segment is connected to the second region of the active layer.
  • the present disclosure also provides a display device including the aforementioned display substrate.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, etc., which is not limited in the embodiment of the present invention.

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Abstract

一种显示基板及其制作方法、显示装置。在平行于显示基板的平面内，所述显示基板包括多个子像素，至少一个子像素包括像素驱动电路，所述像素驱动电路至少包括驱动晶体管；所述驱动晶体管的有源层包括沟道区，所述沟道区包括沿第一方向延伸的漏端段、与所述漏端段连接的中间段以及与所述中间段连接的源端段；所述漏端段在远离所述中间段的第一端具有第一宽度，所述漏端段在靠近所述中间段的第二端具有第二宽度；所述第一宽度大于所述第二宽度；所述第一宽度和第二宽度为所述漏端段在第二方向上的尺寸，所述第一方向与第二方向交叉。

Description

显示基板及其制作方法、显示装置 技术领域
本文涉及但不限于显示技术领域，具体涉及一种显示基板及其制作方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种显示基板，在平行于显示基板的平面内，所述显示基板包括多个子像素，至少一个子像素包括像素驱动电路，所述像素驱动电路至少包括驱动晶体管；所述驱动晶体管的有源层包括沟道区，所述沟道区包括沿第一方向延伸的漏端段、与所述漏端段连接的中间段以及与所述中间段连接的源端段；所述漏端段在远离所述中间段的第一端具有第一宽度，所述漏端段在靠近所述中间段的第二端具有第二宽度；所述第一宽度大于所述第二宽度；所述第一宽度和第二宽度为所述漏端段在第二方向上的尺寸，所述第一方向与第二方向交叉。
在示例性实施方式中，所述驱动晶体管的有源层还包括与所述漏端段连接的第一区和与所述源端段连接的第二区，所述第一区的一端与所述漏端段的第一端连接，所述第一区的另一端与接收数据信号的晶体管连接；在平行于显示基板的平面内，所述源端段的形状包括矩形。
在示例性实施方式中，在平行于显示基板的平面内，所述漏端段的形状包括梯形，所述梯形包括梯形下底和梯形上底，所述漏端段的第一端为梯形下底，具有第一宽度，所述漏端段的第二端为梯形上底，具有第二宽度。
在示例性实施方式中，在平行于显示基板的平面内，所述漏端段的形状包括梯形和矩形的组合体，所述梯形包括梯形下底和梯形上底，所述矩形包括矩形下边和矩形上边；所述漏端段的第一端为梯形下底，具有第一宽度，所述梯形上底与所述矩形下边连接，具有第二宽度，所述漏端段的第二端为所述矩形上边。
在示例性实施方式中，在平行于显示基板的平面内，所述漏端段的形状包括矩形和梯形的组合体，所述矩形包括矩形下边和矩形上边，所述梯形包括梯形下底和梯形上底；所述漏端段的第一端为矩形下边，所述矩形上边与所述梯形下底连接，具有第一宽度，所述漏端段的第二端为梯形上底，具有第二宽度。
在示例性实施方式中，在平行于显示基板的平面内，所述漏端段的形状包括第一梯形和第二梯形的组合体，所述第一梯形包括第一梯形下底和第一梯形上底，所述第二梯形包括第二梯形下底和第二梯形上底；所述漏端段的第一端为第一梯形下底，具有第一宽度，所述第一梯形上底与所述第二梯形下底连接，所述漏端段的第二端为所述第二梯形上底，具有第二宽度。
在示例性实施方式中，所述第一宽度与所述第二宽度之比为1.5至5。
在示例性实施方式中，梯形至少一个侧边与所述第一方向之间的夹角大于0°，小于90°。
在示例性实施方式中，在垂直于显示基板的平面内，所述显示基板包括在基底上依次设置的半导体层、第一导电层、第二导电层和第三导电层；所述半导体层包括多个多晶硅晶体管的有源层，所述第一导电层包括多个多晶硅晶体管的栅电极和存储电容的第一极板，所述第二导电层包括存储电容的第二极板，所述第三导电层包括第一电源线、数据信号线和多个多晶硅晶体管的第一极和第二极。
在示例性实施方式中，在垂直于显示基板的平面内，所述显示基板包括 在基底上依次设置的第一半导体层、第一导电层、第二导电层、第二半导体层、第三导电层、第四导电层和第五导电层；所述第一半导体层包括多个多晶硅晶体管的有源层，所述第一导电层包括多个多晶硅晶体管的栅电极和存储电容的第一极板，所述第二导电层包括存储电容的第二极板，所述第二半导体层包括多个氧化物晶体管的有源层，所述第三导电层包括多个氧化物晶体管的栅电极，所述第四导电层包括多个多晶硅晶体管的第一极和第二极以及多个氧化物晶体管的第一极和第二极，所述第五导电层包括第一电源线和数据信号线。
在示例性实施方式中，所述沟道区的中间段包括第二沟道段、第三沟道段和第四沟道段；所述漏端段的第二端与所述第二沟道段的第一端连接；所述第二沟道段的第二端沿第二方向的反方向延伸后与所述第三沟道段的第一端连接；所述第三沟道段的第二端沿第一方向延伸后与所述第四沟道段的第一端连接；所述第四沟道段的第二端沿第二方向延伸后与所述源端段的第一端连接；所述源端段的第二端与所述有源层的第二区连接。
本公开还提供了一种显示装置，包括前述的显示基板。
本公开还提供了一种显示基板的制备方法，在平行于显示基板的平面内，所述显示基板包括多个子像素，至少一个子像素包括像素驱动电路，所述像素驱动电路至少包括驱动晶体管；所述制备方法包括：
在基底上形成半导体层或第一半导体层；所述半导体层或第一半导体层至少包括驱动晶体管的有源层，所述驱动晶体管的有源层包括沟道区，所述沟道区包括沿第一方向延伸的漏端段、与所述漏端段连接的中间段以及与所述中间段连接的源端段；所述漏端段在远离所述中间段的第一端具有第一宽度，所述漏端段在靠近所述中间段的第二端具有第二宽度；所述第一宽度大于所述第二宽度；所述第一宽度和第二宽度为所述漏端段在第二方向上的尺寸，所述第一方向与第二方向交叉。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示基板的平面结构示意图；
图3为一种显示基板的剖面结构示意图；
图4为一种像素驱动电路的等效电路示意图；
图5为一种像素驱动电路的工作时序图；
图6为本公开示例性实施例一种显示基板的结构示意图；
图7a为本公开一种显示基板形成半导体层图案后的示意图；
图7b为图7a中A-A向的剖视图；
图8a为本公开一种显示基板形成第一导电层图案后的示意图；
图8b为图8a中A-A向的剖视图；
图8c为图8a中驱动晶体管沟道区域的放大图；
图8d至图8i为本公开示例性实施例几种第一沟道段的示意图；
图9a为本公开一种显示基板形成第二导电层图案后的示意图；
图9b为图9a中A-A向的剖视图；
图10a为本公开一种显示基板形成第四绝缘层图案后的示意图；
图10b为图10b中A-A向的剖视图；
图11a为本公开一种显示基板形成第三导电层图案后的示意图；
图11b为图11a中A-A向的剖视图；
图12a为本公开一种显示基板形成平坦层图案后的示意图；
图12b为图12a中A-A向的剖视图；
图13a为本公开一种显示基板形成阳极图案后的示意图；
图13b为图13a中A-A向的剖视图；
图14为本公开示例性实施例另一种显示基板的结构示意图；
图15a为本公开另一种显示基板形成第一半导体层图案后的示意图；
图15b为图15a中B-B向的剖视图；
图16a为本公开另一种显示基板形成第一导电层图案后的示意图；
图16b为图16a中B-B向的剖视图；
图17a为本公开另一种显示基板形成第二导电层图案后的示意图；
图17b为图17a中B-B向的剖视图；
图18a为本公开另一种显示基板形成第二半导体层图案后的示意图；
图18b为图18a中B-B向的剖视图；
图19a为本公开另一种显示基板形成第三导电层图案后的示意图；
图19b为图19a中B-B向的剖视图；
图20a为本公开另一种显示基板形成多晶硅过孔图案后的示意图；
图20b为图20a中B-B向的剖视图；
图21a为本公开另一种显示基板形成氧化物过孔图案后的示意图；
图21b为图21a中B-B向的剖视图；
图22a为本公开另一种显示基板形成第四导电层图案后的示意图；
图22b为图22a中B-B向的剖视图；
图23a为本公开另一种显示基板形成第一平坦层图案后的示意图；
图23b为图23a中B-B向的剖视图；
图24a为本公开另一种显示基板形成第五导电层图案后的示意图；
图24b为图24a中B-B向的剖视图；
图25为本公开另一种显示基板形成第二平坦层图案后的示意图；
图26为本公开另一种显示基板形成阳极图案后的示意图。
附图标记说明:
10—基底；             11—第一有源层；        12—第二有源层；
13—第三有源层；        14—第四有源层；        15—第五有源层；
16—第六有源层；        17—第七有源层；        18—沟道区；
21—第一扫描信号线；    22—第二扫描信号线；    23—发光控制线；
24—第一极板；          31—初始信号线；        32—第二极板；
33—屏蔽电极；          34—开口；              35—极板连接线；
36—节点电极；          37—第一遮挡层；        38—第二遮挡层；
41—第一电源线；        42—数据信号线；        43—第一连接电极；
44—第二连接电极；      45—第三连接电极；      48—第一辅助信号线；
49—第二辅助信号线；    51—电源连接线；        52—初始信号线；
53—第五连接电极；      54—第六连接电极；      55—第七连接电极；
56—第八连接电极；      61—数据信号线；        62—第一电源线；
63—阳极连接电极；      71—阳极；              91—第一绝缘层；
92—第二绝缘层；        93—第三绝缘层；        94—第四绝缘层；
95—第五绝缘层；        96—第六绝缘层；        97—第七绝缘层；
98—第一平坦层；        101—基底；             102—驱动电路层；
103—发光结构层；       104—封装层；           301—阳极；
302—像素定义层；       303—有机发光层；       304—阴极；
401—第一封装层；       402—第二封装层；       403—第三封装层。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚 度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接 在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，OLED显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，像素阵列可以包括多个扫描信号线(S1到Sm)、多个数据信号线(D1到Dn)、多个发光信号线(E1到Eo)和多个子像素Pxij。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器 接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。像素阵列可以包括多个子像素Pxij。每个子像素Pxij可以连接到对应的数据信号线、对应的扫描信号线和对应的发光信号线，i和j可以是自然数。子像素Pxij可以指其中晶体管连接到第i扫描信号线且连接到第j数据信号线的子像素。
图2为一种显示基板的平面结构示意图。如图2所示，显示基板可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个包括出射第一颜色光线的第一发光单元(子像素)P1、出射第二颜色光线的第二发光单元P2和出射第三颜色光线的第三发光单元P3，第一发光单元P1、第二发光单元P2和第三发光单元P3均包括像素驱动电路和发光器件。第一发光单元P1、第二发光单元P2和第三发光单元P3中的像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向所述发光器件输出相应的电流。第一发光单元P1、第二发光单元P2和第三发光单元P3中的发光器件分别与所在发光单元的像素驱动电路连接，发光器件被配置为响应所在发光单元的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，像素单元P中可以包括红色(R)发光单元、绿色(G)发光单元和蓝色(B)发光单元，或者可以包括红色发光单元、绿色发光单元、蓝色发光单元和白色发光单元，本公开在此不做限定。在示例性实施方式中，像素单元中发光单元的形状可以是矩形状、菱形、五边形或六边形。像素单元包括三个发光单元时，三个发光单元可以采用水平并列、竖直并列或品字方式排列，像素单元包括四个发光单元时，四个发光单元可以采用水平并列、竖直并列或正方形(Square)方式排列，本公开在此不做限定。
图3为一种显示基板的剖面结构示意图，示意了OLED显示基板三个子 像素的结构。如图3所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底一侧的发光结构层103以及设置在发光结构层103远离基底一侧的封装层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层102可以包括构成像素驱动电路的多个晶体管和存储电容，图3中仅以一个驱动晶体管210和一个存储电容211为例进行示意。每个子像素的发光结构层103可以包括构成发光器件的多个膜层，多个膜层可以包括阳极301、像素定义层302、有机发光层303和阴极304，阳极301通过过孔与驱动晶体管210的漏电极连接，有机发光层303与阳极301连接，阴极304与有机发光层303连接，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，有机发光层303可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层和电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层和电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层和电子阻挡层可以有少量的交叠，或者可以是隔离的。
在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C结构。图4为一种像素驱动电路的等效电路示意图。如图4所 示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)、1个存储电容C和7个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)。
在示例性实施方式中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的控制极连接。
第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管的第二极与第二节点N2连接。当导通电平扫描信号施加到第二扫描信号线S2时，第一晶体管T1将初始化电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的控制极与第二极连接。
第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的量。
第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据信号线D的数据电压输入到像素驱动电路。
第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三 节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管T7的控制极与第一扫描信号线S1连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与发光器件的第一极连接。当导通电平扫描信号施加到第一扫描信号线S1时，第七晶体管T7将初始化电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。第一扫描信号线S1为本显示行像素驱动电路中的扫描信号线，第二扫描信号线S2为上一显示行像素驱动电路中的扫描信号线，即对于第n显示行，第一扫描信号线S1为S(n)，第二扫描信号线S2为S(n-1)，本显示行的第二扫描信号线S2与上一显示行像素驱动电路中的第一扫描信号线S1为同一信号线，可以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物 (Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在示例性实施方式中，第一扫描信号线S1、第二扫描信号线S2、发光信号线E和初始信号线INIT沿水平方向延伸，第二电源线VSS、第一电源线VDD和数据信号线D沿竖直方向延伸。
在示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
图5为一种像素驱动电路的工作时序图。下面通过图4示例的像素驱动电路的工作过程说明本公开示例性实施例，图4中的像素驱动电路包括7个晶体管(第一晶体管T1到第六晶体管T7)、1个存储电容C和7个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)，7个晶体管均为P型晶体管。
在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1和发光信号线E的信号为高电平信号。第二扫描信号线S2的信号为低电平信号，使第一晶体管T1导通，初始信号线INIT的信号提供至第二节点N2，对存储电容C进行初始化，清除存储电容中原有数据电压。第一扫描信号线S1和发光信号线E的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线E的信号为高电平信号，数据信号线D输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2， 并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使得初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第二扫描信号线S2的信号为高电平信号，使第一晶体管T1断开。发光信号线E的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线E的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
图6为本公开示例性实施例一种显示基板的结构示意图，示意了一个子像素的平面结构。如图6所示，在平行于显示基板的平面内，显示基板的子像素中设置有第一扫描信号线21、第二扫描信号线22、发光控制线23、初始信号线31、第一电源线41、数据信号线42以及像素驱动电路，像素驱动电路可以包括多个晶体管和存储电容，存储电容包括第一极板24和第二极板32，多个晶体管可以包括第一晶体管至第七晶体管，第三晶体管为驱动晶体管。
在垂直于显示基板的平面内，显示基板可以包括在基底上依次设置的半导体层、第一导电层、第二导电层和第三导电层。在示例性实施例中，半导体层可以包括多个晶体管的有源层。第一导电层可以包括第一扫描信号线21、第二扫描信号线22、发光控制线23、存储电容的第一极板24和多个晶体管的栅电极。第二导电层可以包括初始信号线31、存储电容的第二极板32、屏蔽电极33和极板连接线35。第三导电层可以包括第一电源线41、数据信号线42、第一连接电极43、第二连接电极44和第三连接电极45。
在示例性实施方式中，显示基板可以包括第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层，第一绝缘层设置在基底与半导体层之间，第二绝缘层设置在半导体层和第一导电层之间，第三绝缘层设置在第一导电层与第二导电层之间，第四绝缘层设置在第二导电层与第三导电层之间。
在示例性实施方式中，沿着第二方向Y，子像素可以被划分为第一区域R1、第二区域R2和第三区域R3，第二区域R2位于第一区域R1和第三区域R3之间。在示例性实施方式中，沿着第一方向X延伸的第一扫描信号线21、第二扫描信号线22和初始信号线31位于第一区域R1，第一极板24和第二极板32位于第二区域R2，沿着第一方向X延伸的发光控制线23位于第三区域R3。本公开示例性实施例中，第一方向X与第二方向Y交叉。在一些示例性实施方式中，第一方向X可以是子像素行的方向(水平方向)，第二方向Y可以是子像素列的方向(竖直方向)。
在示例性实施方式中，第一晶体管的栅电极与第二扫描信号线22连接，第一晶体管的第一极与初始信号线31连接，第一晶体管的第二极分别与第二晶体管的第一极、第三晶体管的栅电极和第一极板24连接。第二晶体管的栅电极与第一扫描信号线21连接，第二晶体管的第二极分别与第三晶体管的第二极和第六晶体管的第一极连接。第三晶体管的第一极分别与第四晶体管的第二极和第五晶体管的第二极连接。第四晶体管的栅电极与第一扫描信号线21连接，第四晶体管的第一极与数据信号线42连接，第四晶体管的第二极与第三晶体管的第一极连接。第五晶体管的栅电极与发光信号线23连接，第五晶体管的第一极分别与第一电源线41和第二极板32连接。第六晶体管的栅电极与发光信号线23连接，第六晶体管的第二极分别与第七晶体管T7的 第二极和发光器件的第一极连接。第七晶体管的栅电极与第二扫描信号线22连接，第七晶体管的第一极与初始信号线31连接，第七晶体管的第二极分别与第六晶体管的第二极和发光器件的第一极连接。
在示例性实施方式中，覆盖第一极板24的第三绝缘层和第四绝缘层上开设有第一过孔V1，第一连接电极43的一端通过第一过孔V1与第一极板24连接，第一连接电极43的另一端通过过孔与第一晶体管的有源层和第二晶体管的有源层连接，第一连接电极43可以作为第一晶体管的第二极和第二晶体管的第一极。
在示例性实施方式中，第二连接电极44可以通过过孔分别与初始信号线31和第七晶体管的有源层连接，第一连接电极43可以作为第七晶体管的第一极和第一晶体管的第一极。
在示例性实施方式中，第三连接电极45可以通过过孔与第六晶体管的有源层和第七晶体管的有源层连接，第三连接电极45可以作为第六晶体管的第二极和第七晶体管的第二极。
在示例性实施方式中，覆盖第二极板32的第四绝缘层上开设有第二过孔V2，第一电源线41通过第二过孔V2与第二极板32连接。
在示例性实施方式中，第一电源线41通过过孔与屏蔽电极33连接，屏蔽电极33在基底上的正投影与数据信号线42在基底上的正投影存在重叠区域。
在示例性实施方式中，极板连接线35设置在第二导电层中。极板连接线35为直线形，与第一方向X平行。极板连接线35的第一端与本子像素的第二极板32连接，第二端沿着第一方向X或者第一方向X的反方向延伸，与相邻子像素的第二极板32连接。
在示例性实施方式中，第二极板32上设置有开口34，开口34在基底上的正投影包含第一过孔V1在基底上的正投影。
在示例性实施方式中，数据信号线42可以通过过孔与第四晶体管的有源层连接。
在示例性实施方式中，第一极板24同时作为第三晶体管的栅电极，第一 极板24在基底上的正投影与第三有源层在基底上的正投影存在重叠区域，重叠区域的第三有源层作为第三晶体管的沟道区。在示例性实施方式中，沟道区的第一端连接第三有源层的第一区，第三有源层的第一区与接收数据信号的第四晶体管连接。沟道区的第二端连接第三有源层的第二区，第三有源层的第二区与第二晶体管连接。
在示例性实施方式中，第三晶体管的沟道区可以包括沿F1方向延伸的漏端段、沿F2方向延伸的中间段以及沿F3方向延伸的源端段，F1方向、F2方向和F3方向可以相同，或者可以相交。在一个示例性实施例中，F1方向和F3方向可以相同，F1方向和F2方向可以相交。本示例性实施例中，第三晶体管的沟道区可以包括沿第一方向X延伸的漏端段、沿第一方向X延伸的源端段以及位于漏端段和源端段之间的中间段。本公开中，沿第一方向X延伸的漏端段与沿第一方向X延伸的源端段可以是平行的，或者可以是漏端段的延长线与源端段的延长线之间具有10°左右以下的夹角。漏端段的第一端连接第三有源层的第一区，漏端段的第二端沿第一方向X延伸后连接中间段的第一端，中间段的第二端连接源端段的第一端，源端段的第二端沿第一方向X延伸后连接第三有源层的第二区。
在示例性实施方式中，漏端段远离中间段的第一端具有第一宽度，漏端段在靠近中间段的第二端具有第二宽度，第一宽度大于第二宽度，使得漏端段形成第一端的第一宽度大于第二端的第二宽度的扇形状。在示例性实施方式中，第一宽度和第二宽度为漏端段第二方向Y上的尺寸。
本公开示例性实施例提供的显示基板，通过将驱动晶体管中漏端段设置成扇形状，改善了因沟道变短引起的薄膜晶体管输出不饱和问题，可以使薄膜晶体管的输出特性平坦。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某 一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。“A的正投影包含B的正投影”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，显示基板的制备过程可以包括如下操作。
(11)形成半导体层图案。在示例性实施例中，形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖基底的第一绝缘层，以及设置在第一绝缘层上的半导体层，如图7a和图7b所示，图7b为图7a中A-A向的剖视图。
在示例性实施例中，每个子像素的半导体层可以包括第一晶体管T1的第一有源层11至第七晶体管T7的第七有源层17，且第一有源层11至第七有源层17为相互连接的一体结构。
在示例性实施例中，第一区域R1可以包括至少部分的第一晶体管T1的第一有源层11、第二晶体管T2的第二有源层12、第四晶体管T4的第四有源层14和第七晶体管T7的第七有源层17，第二区域R2可以包括至少部分的第三晶体管T3的第三有源层13，第三区域R3可以包括至少部分的第五晶体管T5的第五有源层15和第六晶体管T6的第六有源层16。第一有源层11和第七有源层17设置在第一区域R1内远离第二区域R2的一侧，第二有源层12和第四有源层14设置在第一区域R1内邻近第二区域R2的一侧。
在示例性实施例中，第一有源层11的形状可以呈“n”字形，第二有源层12的形状可以呈“7”字形，第三有源层13的形状可以呈“几”字形，第四有源层14的形状可以呈“1”字形，第五有源层15、第六有源层16和第七有源层17的形状可以呈“L”字形。
在示例性实施例中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施例中，第一有源层11的第一区11-1同时作为第七有源层17的第一区17-1，第一有源层11的第二区11-2同时作为第二有源层12的第一区12-1，第三有源层13的第一区13-1同时作为第四有源层14的第二区14-2和第五有源层15的第二区15-2，第三有源层13的第二区13-2同时作为第二有源层12的第二区12-2和第六有源层16的第一区16-1，第六有源层16的第二区16-2同时作为第七有源层17的第二区17-2。在示例性实施例中，第四有源层14的第一区14-1和第五有源层15的第一区15-1单独设置。
在示例性实施例中，第三晶体管的第三有源层13包括第一区13-1、第二区13-2和沟道区，第三有源层13的沟道区设置在第一区13-1和第二区13-2之间，且沟道区的两端分别与第一区13-1和第二区13-2连接。第三有源层13的第一区13-1同时作为第四有源层14的第二区14-2和第五有源层15的第二区15-2，即第三有源层13的第一区13-1、第四有源层14的第二区14-2和第五有源层15的第二区15-2之间相互连接。第三有源层13的第二区13-2同时作为第二有源层12的第二区12-2和第六有源层16的第一区16-1，即第三有源层13的第二区13-2、第二有源层12的第二区12-2和第六有源层16的第一区16-1之间相互连接。
如图7b所示，本次工艺后，显示基板包括设置在基底10上的第一绝缘层91和设置在第一绝缘层91上的半导体层，半导体层可以包括第一有源层11和第三有源层13。
(12)形成第一导电层图案。在示例性实施例中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，第一导电层图案至少包括：第一扫描信号线21、第二扫描信号线22、发光控制线23和存储电容的第一极板24，如图8a、图8b和图8c所示，图8b为图8a中A-A向的剖视图，图8c为图8a中驱动晶体管沟道区域的放大图。在示例性实施例中，第一导电层可以称为第一栅金属(GATE 1)层。
在示例性实施例中，第一扫描信号线21、第二扫描信号线22和发光控制线23沿第一方向X延伸。第一扫描信号线21和第二扫描信号线22设置在第一区域R1内，第二扫描信号线22位于第一扫描信号线21远离第二区域R2的一侧，发光控制线23设置在第三区域R3内，存储电容的第一极板24设置在第二区域R2内，位于第一扫描信号线21和发光控制线23之间。
在示例性实施例中，第一极板24可以为矩形状，矩形状的角部可以设置倒角，第一极板24在基底上的正投影与第三晶体管T3的第三有源层在基底上的正投影存在重叠区域。在示例性实施例中，第一极板24同时作为第三晶体管T3的栅电极。
在示例性实施例中，第一扫描信号线21与第四晶体管T4的第四有源层相重叠的区域作为第四晶体管T4的栅电极。第一扫描信号线21设置有向第二扫描信号线22一侧凸起的栅极块21-1，栅极块21-1在基底上的正投影与第二晶体管T2的第二有源层在基底上的正投影存在重叠区域，第一扫描信号线21和栅极块21-1与第二晶体管T2的第二有源层相重叠的区域作为第二晶体管T2双栅结构的栅电极。第二扫描信号线22与第一晶体管T1的第一有源层相重叠的区域作为第一晶体管T1双栅结构的栅电极，第二扫描信号线22与第七晶体管T7的第七有源层相重叠的区域作为第七晶体管T7的栅电极，发光控制线23与第五晶体管T5的第五有源层相重叠的区域作为第五晶体管T5的栅电极，发光控制线23与第六晶体管T6的第六有源层相重叠的区域作为第六晶体管T6的栅电极。
在示例性实施例中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第七晶体管T7的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一有源层至第七有源层的第一区和第二区均被导体化。
如图8b所示，本次工艺后，显示基板包括设置在基底10上的第一绝缘层91、设置在第一绝缘层91上的半导体层、覆盖半导体层的第二绝缘层92和设置在第二绝缘层92上的第一导电层，半导体层可以包括第一有源层11和第三有源层13，第一导电层可以包括第一扫描信号线21、第二扫描信号线22、发光控制线23和存储电容的第一极板24。
如图8c所示，第一极板24在基底上的正投影与第三有源层在基底上的正投影存在重叠区域，第一极板24同时作为第三晶体管T3的栅电极，第三晶体管T3的第三有源层与第一极板24相重叠的区域作为第三晶体管T3的沟道区18，沟道区18的一端连接第三有源层的第一区13-1，另一端连接第三有源层的第二区13-2。沟道(channel)是指晶体管的有源层中第一区和第二区之间的半导体层，沟道宽长比为沟道宽度与沟道长度的比例，是晶体管中重要的参数。当沟道长度相同时，沟道宽度越大，速度也越快，功耗也越大。当沟道宽度相同时，沟道长度越小，速度也越快，功耗也大。
在示例性实施例中，沟道区18包括沿第一方向X延伸的第一沟道段(漏端段)18-1、第三沟道段18-3和第五沟道段(源端段)18-5，以及沿第二方向Y延伸的第二沟道段18-2和第四沟道段18-4，第一沟道段18-1称为漏端段，第五沟道段18-5称为源端段，第二沟道段18-2、第三沟道段18-3和第四沟道段18-4一起称为位于漏端段和源端段之间的中间段。第一沟道段18-1的第一端与第一区13-1连接，第二端沿第一方向X延伸后与第二沟道段18-2的第一端连接。第二沟道段18-2的第一端与第一沟道段18-1的第二端连接，第二端沿第二方向Y的反方向延伸后与第三沟道段18-3的第一端连接。第三沟道段18-3的第一端与第二沟道段18-2的第二端连接，第二端沿第一方向X延伸后与第四沟道段18-4的第一端连接。第四沟道段18-4的第一端与第三沟道段18-3的第二端连接，第二端沿第二方向Y延伸后与第五沟道段18-5的第一端连接。第五沟道段18-5的第一端与第四沟道段18-4的第二端连接，第二端沿第一方向X延伸后与第二区13-2连接，形成“几”字形的沟道区18。
在示例性实施例中，与第三有源层的第一区13-1(掺杂区)连接的第一沟道段18-1的第一端具有第一宽度M1，与第三有源层的第二沟道段18-2(中间段)连接的第一沟道段18-1的第二端具有第二宽度M2，第一宽度和第二宽度均是指第一沟道段18-1在第二方向Y的尺寸。在示例性实施例中，第五沟道段18-5的形状可以为矩形。
在示例性实施例中，第一宽度M1可以大于第二宽度M2。
在示例性实施例中，第一宽度M1与第二宽度M2之比可以约为1.5至5。
在示例性实施例中，第一宽度M1可以约为1.5μm至25μm，第二宽度M2可以约为1μm至5μm。
在示例性实施例中，第一沟道段18-1具有长度L，长度L可以约为2μm至10μm，长度是指第一沟道段18-1在第一方向X的尺寸。
在示例性实施例中，第一极板24(第三晶体管T3的栅电极)在基底上的正投影与第三有源层在基底上的正投影具有沿着第二方向Y延伸的重叠线，靠近第三有源层的第一区13-1一侧的重叠线为第一沟道段18-1的第一端。沿第一方向X延伸的第一沟道段18-1与沿第二方向Y延伸的第二沟道段18-2具有沿着第二方向Y延伸的交界线，该交界线可以为第一沟道段18-1的第二端。
如图8c所示，在示例性实施例中，第一沟道段18-1可以包括沿第一方向X依次设置的第一子段18a和第二子段18b。第一子段18a沿第一方向X延伸，第一子段18a的第一端与第一区13-1连接，第一子段18a的第二端的沿第一方向X延伸后与第二子段18b的第一端连接。第二子段18b的第一端与第一子段18a的第二端连接，第二子段18b的第二端的沿第一方向X延伸后与第二沟道段18-2的第一端连接。
在示例性实施例中，第一子段18a和第二子段18b可以按照多种方式进行划分。例如，对于第一子段18a和第二子段18b形状不同，一个是矩形，另一个是梯形，可以按照矩形与梯形之间的分界线划分第一子段18a和第二子段18b。又如，对于第一子段18a和第二子段18b形状均是梯形，一个梯形具有较大的底角，另一个梯形具有较小的底角，可以按照较大底角梯形与较小底角梯形之间的分界线划分第一子段18a和第二子段18b，本公开在此不做限定。
在示例性实施例中，第一子段18a远离第二子段18b的第一端具有第一宽度M1，第二子段18b远离第一子段18a的第二端具有第二宽度M2。
在示例性实施例中，第一子段18a具有第一长度L1，第二子段18b具有第二长度L2，第一沟道段18-1的长度L＝L1+L2。
在示例性实施例中，长度L可以约为2μm至10μm，第一长度L1可以约为1μm至5μm，第二长度L2可以约为1μm至5μm。例如，长度L可以约 为3μm，第一长度L1可以约为1.5μm，第二长度L2可以约为1.5μm。
图8d至图8i为本公开示例性实施例几种第一沟道段的示意图。
在示例性实施例中，第一子段18a的形状可以为梯形，第二子段18b的形状可以为矩形，梯形包括梯形下底和梯形上底，矩形包括矩形下边和矩形上边。第一子段18a的第一端作为梯形下底，具有第一宽度M1，第一子段18a的第二端作为梯形上底，第二子段18b的第一端作为矩形下边，第二子段18b的第二端作为矩形上边，具有第二宽度M2，梯形上底与矩形下边连接，如图8d所示。
在一种可能的实施方案中，第一子段18a的形状可以为矩形，第二子段18b的形状可以为梯形，矩形包括矩形下边和矩形上边，梯形包括梯形下底和梯形上底。第一子段18a的第一端作为矩形下边，具有第一宽度M1，第一子段18a的第二端作为矩形上边，第二子段18b的第一端作为梯形下底，第二子段18b的第二端作为梯形上底，具有第二宽度M2，矩形上边与梯形下底连接，如图8e所示。
在另一种可能的实施方案中，第一子段18a的形状可以为第一梯形，第二子段18b的形状可以为第二梯形，第一梯形包括第一梯形下底和第一梯形上底，第二梯形包括第二梯形下底和第二梯形上底。第一子段18a的第一端作为第一梯形下底，具有第一宽度M1，第一子段18a的第二端作为第一梯形上底，第二子段18b的第一端作为第二梯形下底，第二子段18b的第二端作为第二梯形上底，具有第二宽度M2，第一梯形上底与第二梯形下底连接，如图8f所示。
在又一种可能的实施方案中，第一沟道段18-1整体的形状为梯形，第一沟道段18-1的第一端作为梯形下底，具有第一宽度M1，第一沟道段18-1的第二端作为梯形上底，具有第二宽度M2，如图8g所示。
在又一种可能的实施方案中，第一子段18a的形状可以为梯形，第二子段18b的形状可以为矩形，梯形包括梯形下底和梯形上底，矩形包括矩形下边和矩形上边。第一子段18a的第一端作为梯形下底，具有第一宽度M1，第一子段18a的第二端作为梯形上底，第二子段18b的第一端作为矩形下边，第二子段18b的第二端作为矩形上边，具有第二宽度M2，梯形上底与矩形 下边连接，梯形上底第二方向的宽度大于矩形下边第二方向的宽度，如图8h所示。
在又一种可能的实施方案中，第一子段18a的形状可以为喇叭形，第二子段18b的形状可以为矩形，喇叭形包括喇叭形下底和喇叭形上底，矩形包括矩形下边和矩形上边。第一子段18a的第一端作为喇叭形下底，具有第一宽度M1，第一子段18a的第二端作为喇叭形上底，第二子段18b的第一端作为矩形下边，第二子段18b的第二端作为矩形上边，具有第二宽度M2，喇叭形上底与矩形下边连接，喇叭形上底第二方向的宽度等于矩形下边第二方向的宽度，如图8i所示。
在一种可能的实施方案中，第一沟道段18-1可以包括沿第一方向X依次设置的多个子段，本公开在此不做限定。
在示例性实施例中，前述的梯形的至少一个侧边与第一方向X的夹角α可以大于0°，小于或等于90°在一种可能的示例性实施例中，梯形的至少一个侧边与第一方向X的夹角α可以约为20°至60°，例如夹角α可以约为30°至40°。在示例性实施例中，梯形的底角β可以约为30°至70°，例如底角β可以约为50°至60°。
在示例性实施例中，梯形可以是等腰梯形，或者可以是非等腰梯形，如直角梯形等。在示例性实施例中，梯形的侧边可以是直线，或者可以是弧线，本公开在此不做限定。
本公开中所说的“梯形、矩形”等并不要求是严格意义上的梯形和矩形，可以存在弧边、曲边、倒角或圆角等，本公开在此不做限定。
随着显示技术的发展，高扫描频率和高分辨率(Pixels Per Inch，简称PPI)显示已经成为趋势产品，具有更精细的画质显示，具有更高的显示品质。对于采用LTPS晶体管的像素驱动电路，为满足高频显示的需求，需要提高驱动晶体管的充电率，为满足高分辨率显示，需要减小驱动晶体管和存储电容的尺寸，因而高扫描频率和高分辨率显示要求短沟道的驱动晶体管(第三晶体管T3)。短沟道的驱动晶体管不仅可以提高像素驱动电路充电率，而且可以降低饱和压降，从而降低功耗。但研究表明，短沟道的驱动晶体管会引发驱动晶体管输出特性上翘问题。对于工作在饱和区的长沟道薄膜晶体管，漏 电极偏压会改变有效沟道长度，但源电极势垒保持常数，沟道内电势可以近似为依赖于横向电场ε x(受栅电极电压控制)的一维分布。对于短沟道薄膜晶体管，在源电极和漏电极的耗尽区长度之和可以与沟道长度相比拟时，沟道内电势分布变成两维分布，依赖于横向电场ε x，会发生沟道电流Id不饱和等短沟道效应。若沟道长度继续缩小至源电极和漏电极的耗尽区长度之和与沟道长度几乎相等时，会产生更严重的漏致势垒降低(Drain Induced Barrier Lowering，简称DIBL)效应，这时漏电极偏压会使源端势垒降低，源电极沟道载流子浓度不固定，额外的载流子注入会导致电流显著增加，无论在亚阈值区或饱和区，薄膜晶体管都无法正常工作。
本公开示例性实施例通过将第三晶体管T3靠近漏电极(第三有源层的第一区)一端的沟道设置成扇形状，即将沟道区18中第一沟道段18-1或者第一沟道段18-1中第一子段18a的形状设置成梯形状，通过增加靠近漏电极一端沟道的面积，在相同的漏电极偏压下，可以使漏电场分散，从而减小横向电场ε x，漏电极耗尽区在沟道方向变短，从而改善了因沟道变短引起的薄膜晶体管输出不饱和问题，可以使薄膜晶体管的输出特性平坦。本公开示例性实施例提出的输出特性平坦的短沟道驱动晶体管不仅可以节省空间，有利于高分辨率显示，而且沟道长度减小，驱动晶体管的阈值电压Vth降低，有利于降低功耗。
(13)形成第二导电层图案。在示例性实施例中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二金属薄膜，采用图案化工艺对第二金属薄膜进行图案化，形成覆盖第一导电层的第三绝缘层93，以及设置在第三绝缘层93上的第二导电层图案，第二导电层图案至少包括：初始信号线31、存储电容的第二极板32、屏蔽电极33和极板连接线35，如图9a和图9b所述，图9b为图9a中A-A向的剖视图。在示例性实施例中，第二导电层可以称为第二栅金属(GATE 2)层。
如图9a所示，在示例性实施例中，初始信号线31沿第一方向X延伸，设置在第一区域R1内，位于第二扫描信号线22远离第二区域R2的一侧。存储电容的第二极板32设置在第二区域R2内，位于第一扫描信号线21和发光控制线23之间。屏蔽电极33设置在第一区域R1内，屏蔽电极33配置 为屏蔽数据电压跳变对关键节点的影响，避免数据电压跳变影响像素驱动电路的关键节点的电位，提高显示效果。
在示例性实施例中，初始信号线31可以为非等宽度设置，初始信号线31的宽度为初始信号线31第二方向Y的尺寸。初始信号线31包括与半导体层相重叠的区域和与半导体层不相重叠的区域，与半导体层不相重叠的区域初始信号线31的宽度可以小于与半导体层相重叠的区域初始信号线31的宽度。
在示例性实施例中，第二极板32的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二极板32在基底上的正投影与第一极板24在基底上的正投影存在重叠区域。第二极板32上设置有开口34，开口34可以位于第二区域R2的中部。开口34可以为矩形，使第二极板32形成环形结构。开口34暴露出覆盖第一极板24的第三绝缘层93，且第一极板24在基底上的正投影包含开口34在基底上的正投影。在示例性实施例中，开口34配置为容置后续形成的第一过孔，第一过孔位于开口34内并暴露出第一极板24，使后续形成的第一晶体管T1的第二极与第一极板24连接。
在示例性实施例中，极板连接线35设置在第一方向X上相邻子像素的第二极板32之间，极板连接线35的第一端与本子像素的第二极板32连接，极板连接线35的第二端沿着第一方向X或者第一方向X的反方向延伸，并与相邻子像素的第二极板32连接，即极板连接线35配置为使第一方向X上相邻子像素的第二极板相互连接。在示例性实施例中，通过极板连接线35，使一子像素行中的第二极板形成相互连接的一体结构，一体结构的第二极板可以复用为电源信号线，保证一子像素行中的多个第二极板具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施例中，第二极板32邻近第一区域R1的边缘在基底上的正投影与第一区域R1与第二区域R2的交界线在基底上的正投影重叠，第二极板32邻近第三区域R3的边缘在基底上的正投影与第二区域R2与第三区域R3的交界线在基底上的正投影重叠，即第二极板32的长度等于第二区域R2的长度，第二极板32的长度是指第二极板32第二方向Y上的尺寸。
如图9b所示，在垂直于基底的平面内，第一绝缘层91设置在基底10上，半导体层设置在第一绝缘层91上，第二绝缘层92覆盖半导体层，第一导电层设置在第二绝缘层92上，第三绝缘层93覆盖第一导电层，第二导电层设置在第三绝缘层93上，第二导电层至少包括初始信号线31和存储电容的第二极板32，存储电容的第二极板32上设置有开口34，开口34暴露出覆盖第一极板24的第三绝缘层93，第二极板32在基底上的正投影与第一极板24在基底上的正投影存在重叠区域。
(14)形成第四绝缘层图案。在示例性实施例中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层，第四绝缘层上设置有多个过孔，多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8和第九过孔V9，如图10a和图10b所示，图10b为图10a中A-A向的剖视图。
如图10a所示，在示例性实施例中，第一过孔V1位于第二极板32的开口34内，第一过孔V1在基底上的正投影位于开口34在基底上的正投影的范围之内，第一过孔V1内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一极板24的表面。第一过孔V1配置为使后续形成的第一晶体管T1的第二极与通过该过孔与第一极板24连接。
在示例性实施例中，第二过孔V2位于第二极板32所在区域，第二过孔V2在基底上的正投影位于第二极板32在基底上的正投影的范围之内，第二过孔V2内的第四绝缘层被刻蚀掉，暴露出第二极板32的表面。第二过孔V2配置为使后续形成的第一电源线通过该过孔与第二极板32连接。在示例性实施例中，作为电源过孔的第二过孔V2可以包括多个，多个第二过孔V2可以沿着第二方向Y依次排列，增加第一电源线与第二极板32的连接可靠性。
在示例性实施例中，第三过孔V3位于第三区域R3，第三过孔V3内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面。第三过孔V3配置为使后续形成的第一电源线通过该过孔与第五 有源层连接。
在示例性实施例中，第四过孔V4位于第三区域R3，第四过孔V4内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第二区(也是第七有源层的第二区)的表面。第四过孔V4配置为使后续形成的第六晶体管T6的第二极通过该过孔与第六有源层连接，以及使后续形成的第七晶体管T7的第二极通过该过孔与第七有源层连接。
在示例性实施例中，第五过孔V5位于第一区域R1，第五过孔V5内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面。第五过孔V5配置为使后续形成的数据信号线通过该过孔与第四有源层连接，第五过孔V5称为数据写入孔。
在示例性实施例中，第六过孔V6位于第一区域R1，第六过孔V6内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第二区(也是第二有源层的第一区)的表面。第六过孔V6配置为使后续形成的第一晶体管T1的第二极通过该过孔与第一有源层连接，以及使后续形成的第二晶体管T2的第一极通过该过孔与第二有源层连接。
在示例性实施例中，第七过孔V7位于第一区域R1，第七过孔V7内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第一区(也是第一有源层的第一区)的表面。第七过孔V7配置为使后续形成的第七晶体管T7的第一极通过该过孔与第七有源层连接，以及使后续形成的第一晶体管T1的第一极通过该过孔与第一有源层连接。
在示例性实施例中，第八过孔V8位于第一区域R1，第八过孔V8内的第四绝缘层被刻蚀掉，暴露出屏蔽电极33的表面。第八过孔V8配置为使后续形成的第一电源线通过该过孔与屏蔽电极33连接。
在示例性实施例中，第九过孔V9位于第一区域R1，第九过孔V9内的第四绝缘层被刻蚀掉，暴露出初始信号线31的表面。第九过孔V9配置为使后续形成的第七晶体管T7的第一极(也是第一晶体管T1的第一极)通过该过孔与初始信号线31连接。
如图10b所示，在垂直于基底的平面内，第一绝缘层91设置在基底10上，半导体层设置在第一绝缘层91上，第二绝缘层92覆盖半导体层，第一 导电层设置在第二绝缘层92上，第三绝缘层93覆盖第一导电层，第二导电层设置在第三绝缘层93上，第四绝缘层94覆盖第二导电层，第四绝缘层94上设置有多个过孔，多个过孔至少包括第一过孔V1和第六过孔V6。第一过孔V1内的第四绝缘层94和第三绝缘层93被刻蚀掉，暴露出第二极板32的表面。第六过孔V6内的第四绝缘层94、第三绝缘层93和第二绝缘层92被刻蚀掉，暴露出第一有源层11的表面。
(15)形成第三导电层图案。在示例性实施例中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三金属薄膜，采用图案化工艺对第三金属薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，第三导电层至少包括：第一电源线41、数据信号线42、第一连接电极43、第二连接电极44和第三连接电极45，如图11a和图11b所示，图11b为图11a中A-A向的剖视图。在示例性实施例中，第三导电层可以称为第一源漏金属(SD1)层。
如图11a所示，在示例性实施例中，第一电源线41沿着第二方向Y延伸，第一电源线41一方面通过第二过孔V2与第二极板32连接，另一方面通过第八过孔V8与屏蔽电极33连接，又一方面通过第三过孔V3与第五有源层连接，使屏蔽电极33和第二极板32具有与第一电源线41相同的电位。由于屏蔽电极33在基底上的正投影与后续形成的数据信号线在基底上的正投影存在重叠区域，且屏蔽电极33与第一电源线41连接，有效屏蔽了数据电压跳变对关键节点的影响，避免了数据电压跳变影响像素驱动电路的关键节点的电位，提高了显示效果。
在示例性实施例中，数据信号线42沿着第二方向Y延伸，数据信号线42通过第五过孔V5与第四有源层的第一区连接，使数据信号线42传输的数据信号写入第四晶体管T4。
在示例性实施例中，第一连接电极43沿着第二方向Y延伸，其第一端通过通过第六过孔V6与第一有源层的第二区(也是第二有源层的第一区)连接，其第二端通过第一过孔V1与第一极板24连接，使第一极板24、第一晶体管T1的第二极和第二晶体管T2的第一极具有相同的电位。在示例性实施例中，第一连接电极43可以作为第一晶体管T1的第二极和第二晶体管T2 的第一极。
在示例性实施例中，第二连接电极44沿着第二方向Y延伸，其第一端通过第九过孔V9与初始信号线31连接，其第二端通过第七过孔V7与第七有源层的第一区(也是第一有源层的第一区)连接，使第七晶体管T7的第一极和第一晶体管T1的第一极具有与初始信号线31相同的电位。在示例性实施例中，第二连接电极44可以作为第七晶体管T7的第一极和第一晶体管T1的第一极。
在示例性实施例中，第三连接电极45通过第四过孔V4与第六有源层的第二区(也是第七有源层的第二区)连接，使第六晶体管T6的第二极和第七晶体管T7的第二极具有相同的电位。在示例性实施例中，第三连接电极45可以作为第六晶体管T6的第二极和第七晶体管T7的第二极。在示例性实施例中，第三连接电极45配置为与后续形成的阳极连接。
在示例性实施例中，第一电源线41和数据信号线42可以为等宽度直线，或者为非等宽度的直线。
如图11b所示，在垂直于基底的平面内，第一绝缘层91设置在基底10上，半导体层设置在第一绝缘层91上，第二绝缘层92覆盖半导体层，第一导电层设置在第二绝缘层92上，第三绝缘层93覆盖第一导电层，第二导电层设置在第三绝缘层93上，第四绝缘层94覆盖第二导电层，第三导电层设置在第四绝缘层94上，第三导电层至少包括第一连接电极43和第三连接电极45，第一连接电极43分别通过第一过孔V1和第六过孔V6与第一极板24和第一晶体管T1的第一有源层11连接。
(16)形成平坦层图案。在示例性实施例中，形成平坦层图案可以包括：在形成前述图案的基底上，涂覆平坦薄膜，采用图案化工艺对平坦薄膜进行图案化，形成覆盖第三导电层的平坦层，平坦层上设置有第十过孔V10，如图12a和图12b所示，图12b为图12a中A-A向的剖视图。
如图12a所示，第十过孔V10位于第三连接电极45所在区域，第十过孔V10内的平坦层被去掉，暴露出第三连接电极45的表面，第十过孔V10配置为使后续形成的阳极通过该过孔与第三连接电极45连接。
如图12b所示，在垂直于基底的平面内，第一绝缘层91设置在基底10 上，半导体层设置在第一绝缘层91上，第二绝缘层92覆盖半导体层，第一导电层设置在第二绝缘层92上，第三绝缘层93覆盖第一导电层，第二导电层设置在第三绝缘层93上，第四绝缘层94覆盖第二导电层，第三导电层设置在第四绝缘层94上，平坦层95覆盖第三导电层，平坦层上设置有第十过孔V10，第十过孔V10内的平坦层95被去掉，暴露出第三连接电极45的表面。
(17)形成阳极图案。在示例性实施例中，形成阳极图案可以包括：在形成前述图案的基底上，沉积透明导电薄膜，采用图案化工艺对透明导电薄膜进行图案化，形成设置在平坦层上的阳极71，如图13a和图13b所示，图13b为图13a中A-A向的剖视图所示。
如图13a所示，阳极71可以为六边形状，阳极71通过第十过孔V10与第三连接电极45连接。由于第三连接电极45作为第六晶体管T6的第二极和第七晶体管T7的第二极，因而阳极71与第六晶体管T6和第七晶体管T7的连接，实现了像素驱动电路可以驱动发光器件发光。
如图13b所示，在垂直于基底的平面内，第一绝缘层91设置在基底10上，半导体层设置在第一绝缘层91上，第二绝缘层92覆盖半导体层，第一导电层设置在第二绝缘层92上，第三绝缘层93覆盖第一导电层，第二导电层设置在第三绝缘层93上，第四绝缘层94覆盖第二导电层，第三导电层设置在第四绝缘层94上，平坦层95覆盖第三导电层，阳极71设置在平坦层95上，阳极71通过第十过孔与第三连接电极45连接。
在示例性实施例中，后续制备流程可以包括：涂覆像素定义薄膜，通过图案化工艺对像素定义薄膜进行图案化，形成像素定义层，每个子像素的像素定义层设置有像素开口，像素开口暴露出阳极。采用蒸镀或喷墨打印工艺形成有机发光层，在有机发光层上形成阴极。形成封装层，封装层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性衬底可以为但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限 于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施例中，第一导电层、第二导电层和第三导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层称为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层称为栅绝缘(GI)层，第四绝缘层称为层间绝缘(ILD)层。平坦层可以采用有机材料，透明导电薄膜可以采用氧化铟锡ITO或氧化铟锌IZO。有源层可以采用多晶硅(p-Si)，即本公开适用于LTPS薄膜晶体管。
图14为本公开示例性实施例另一种显示基板的结构示意图，示意了一个子像素的平面结构。如图14所示，在平行于显示基板的平面内，显示基板的子像素中设置有第一扫描信号线21、第二扫描信号线22、发光控制线23、初始信号线52、数据信号线61、第一电源线62和像素驱动电路，像素驱动电路可以包括多个晶体管和存储电容，存储电容包括第一极板和第二极板，多个晶体管可以包括第一晶体管至第七晶体管，第三晶体管为驱动晶体管。
在垂直于显示基板的平面内，显示基板可以包括在基底上依次设置的第一半导体层、第一导电层、第二导电层、第二半导体层、第三导电层、第四导电层和第五导电层。在示例性实施例中，第一半导体层可以包括多个多晶硅晶体管的有源层，第一导电层可以包括第一扫描信号线21、第二扫描信号 线22、发光控制线23、存储电容的第一极板和多个多晶硅晶体管的栅电极，第二导电层可以包括存储电容的第二极板32、极板连接线35、节点电极、第一遮挡层和第二遮挡层，第二半导体层可以包括多个氧化物晶体管的有源层，第三导电层可以包括第一辅助信号线48和第二辅助信号线49和多个氧化物晶体管的栅电极，第四导电层可以包括电源连接线51、初始信号线52、第五连接电极、第六连接电极、第七连接电极和第八连接电极，第五导电层可以包括数据信号线61、第一电源线62和阳极连接电极63。
在示例性实施方式中，显示基板可以包括第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层、第六绝缘层、第七绝缘层、第一平坦层和第二平坦层，第一绝缘层设置在基底与第一半导体层之间，第二绝缘层设置在第一半导体层和第一导电层之间，第三绝缘层设置在第一导电层与第二导电层之间，第四绝缘层设置在第二导电层与第二半导体层之间，第五绝缘层设置在第二半导体层与第三导电层之间，第六绝缘层设置在第三导电层与第四导电层之间，第七绝缘层和第一平坦层设置在第四导电层与第五导电层之间，第二平坦层设置在第五导电层与阳极之间。
在示例性实施方式中，沿着第一方向X延伸的第一扫描信号线21位于第一区域R1，第一极板和第二极板位于第二区域R2，沿着第一方向X延伸的第二扫描信号线22、发光控制线23和初始信号线52位于第三区域R3。
在示例性实施方式中，第一晶体管的栅电极与第二辅助信号线连接，第一晶体管的第一极与初始信号线52连接，第一晶体管的第二极分别与第二晶体管的第一极、第三晶体管的栅电极和第一极板连接。第二晶体管的栅电极与第一辅助信号线连接，第二晶体管的第二极分别与第三晶体管的第二极和第六晶体管的第一极连接。第三晶体管的第一极分别与第四晶体管的第二极和第五晶体管的第二极连接。第四晶体管的栅电极与第一扫描信号线21连接，第四晶体管的第一极通过第八连接电极56与数据信号线61连接，第四晶体管的第二极与第三晶体管的第一极连接。第五晶体管的栅电极与发光信号线23连接，第五晶体管的第一极分别与第一电源线62和第二极板32连接。第六晶体管的栅电极与发光信号线23连接，第六晶体管的第二极通过第七连接电极和阳极连接电极63与发光器件的阳极连接。第七晶体管的栅电极与第 二扫描信号线22连接，第七晶体管的第一极与初始信号线52连接，第七晶体管的第二极与第六晶体管的第二极连接。
在示例性实施方式中，第一极板同时作为第三晶体管的栅电极，第一极板在基底上的正投影与第三有源层在基底上的正投影存在重叠区域，重叠区域的第三有源层作为第三晶体管的沟道区。在示例性实施方式中，沟道区的结构与前述实施例类似，沟道区的漏端段为扇形状，这里不再赘述。
在示例性实施方式中，本示例性实施例显示基板的制备过程可以包括如下操作。
(21)形成第一半导体层图案。在示例性实施例中，形成第一半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和第一半导体薄膜，通过图案化工艺对第一半导体薄膜进行图案化，形成覆盖基底的第一绝缘层，以及设置在第一绝缘层上的第一半导体层，如图15a和图15b所示，图15b为图15a中B-B向的剖视图。
如图15a所示，每个子像素的第一半导体层可以包括第三晶体管T3的第三有源层13至第七晶体管T7的第七有源层17，且第三有源层13至第七有源层17为相互连接的一体结构。
在示例性实施例中，第四晶体管T4的第四有源层14设置在第一区域R1内，第三晶体管T3的第三有源层13设置在第二区域R2内，第五晶体管T5的第五有源层15、第六晶体管T6的第六有源层16和第七晶体管T7的第七有源层17设置在第三区域R3内。第七有源层17设置在第三区域R3远离第二区域R2的一侧，第五有源层15和第六有源层16设置在第三区域R3邻近第二区域R2的一侧。
在示例性实施例中，第三有源层13的形状可以呈“几”字形，第四有源层14的形状可以呈“1”字形，第五有源层15、第六有源层16和第七有源层17的形状可以呈“L”字形。
在示例性实施例中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施例中，第三有源层13的第一区13-1同时作为第四有源层14的第二区14-2和第五有源层15的第二区 15-2，即第三有源层13的第一区13-1、第四有源层14的第二区14-2和第五有源层15的第二区15-2之间相互连接。第三有源层13的第二区13-2同时作为第六有源层16的第一区16-1，即第三有源层13的第二区13-2和第六有源层16的第一区16-1之间相互连接。第六有源层16的第二区16-2同时作为第七有源层17的第二区17-2，即第六有源层16的第二区16-2和第七有源层17的第二区17-2之间相互连接。第四有源层14的第一区14-1、第五有源层15的第一区15-1和第七有源层17的第一区17-1单独设置。
在示例性实施例中，第一半导体层可以采用多晶硅(p-Si)，即第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管为LTPS薄膜晶体管。
如图15b所示，本次工艺后，显示基板包括设置在基底10上的第一绝缘层91和设置在第一绝缘层91上的第一半导体层，第一半导体层可以包括第六有源层16。
(22)形成第一导电层图案。在示例性实施例中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，第一导电层图案至少包括：第一扫描信号线21、第二扫描信号线22、发光控制线23和存储电容的第一极板24，如图16a和图16b所示，图16b为图16a中B-B向的剖视图。在示例性实施例中，第一导电层可以称为第一栅金属(GATE 1)层。
在示例性实施例中，第一扫描信号线21、第二扫描信号线22和发光控制线23沿第一方向X延伸。第一扫描信号线21设置在第一区域R1内，第二扫描信号线22和发光控制线23设置在第三区域R3内，第二扫描信号线22位于发光控制线23远离第二区域R2的一侧，存储电容的第一极板24设置在第二区域R2内。
在示例性实施例中，第一极板24可以为矩形状，矩形状的角部可以设置倒角，第一极板24在基底上的正投影与第三晶体管T3的第三有源层在基底上的正投影存在重叠区域，第一极板24同时作为第三晶体管T3的栅电极，第三晶体管T3的第三有源层与第一极板24相重叠的区域作为第三晶体管T3 的沟道区，沟道区的一端连接第三有源层的第一区，另一端连接第三有源层的第二区。第一扫描信号线21与第四晶体管T4的第四有源层相重叠的区域作为第四晶体管T4的栅电极，第一极板24与第三晶体管T3的第三有源层相重叠的区域作为第三晶体管T3的栅电极，发光控制线23与第五晶体管T5的第五有源层相重叠的区域作为第五晶体管T5的栅电极，发光控制线23与第六晶体管T6的第六有源层相重叠的区域作为第六晶体管T6的栅电极，第二扫描信号线22与第七晶体管T7的第七有源层相重叠的区域作为第七晶体管T7的栅电极。
在示例性实施例中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第三晶体管T3至第七晶体管T7的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第三有源层至第七有源层的第一区和第二区均被导体化。
在示例性实施例中，第三晶体管T3的沟道区的结构与前述实施例相同，沟道区的漏端段为扇形状，从而改善了因沟道变短引起的薄膜晶体管输出不饱和问题，可以使薄膜晶体管的输出特性平坦，这里不再赘述。本公开示例性实施例提出的输出特性平坦的短沟道驱动晶体管不仅可以节省空间，有利于高分辨率显示，而且沟道长度减小，驱动晶体管的阈值电压Vth降低，有利于降低功耗。
如图16b所示，本次工艺后，显示基板包括设置在基底10上的第一绝缘层91、设置在第一绝缘层91上的第一半导体层、覆盖第一半导体层的第二绝缘层92和设置在第二绝缘层92上的第一导电层，第一导电层可以包括第一扫描信号线21发光控制线23。
(23)形成第二导电层图案。在示例性实施例中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二金属薄膜，采用图案化工艺对第二金属薄膜进行图案化，形成覆盖第一导电层的第三绝缘层93，以及设置在第三绝缘层93上的第二导电层图案，第二导电层图案至少包括：存储电容的第二极板32、极板连接线35、节点电极36、第一遮挡层37和第二遮挡层38，如图17a和图17b所示，图17b为图17a中B-B向的剖视图。在示例性实施例中，第二导电层可以称为第二栅金属(GATE 2)层。
如图17a所示，在示例性实施例中，存储电容的第二极板32设置在第二区域R2内，位于第二遮挡层38和发光控制线23之间。第二极板32的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二极板32在基底上的正投影与第一极板24在基底上的正投影存在重叠区域。第二极板32上设置有开口34，开口34可以位于第二区域R2的中部。开口34可以为矩形，使第二极板32形成环形结构。开口34暴露出覆盖第一极板24的第三绝缘层93，且第一极板24在基底上的正投影包含开口34在基底上的正投影。在示例性实施例中，开口34配置为容置后续形成的第一过孔，第一过孔位于开口34内并暴露出第一极板24，使后续形成的第一晶体管T1的第二极与第一极板24连接。
在示例性实施例中，极板连接线35设置在第一方向X上相邻子像素的第二极板32之间，极板连接线35的第一端与本子像素的第二极板32连接，极板连接线35的第二端沿着第一方向X延伸，并与第一方向X相邻子像素的第二极板32连接，即极板连接线35配置为使第一方向X上相邻子像素的第二极板相互连接。在示例性实施例中，通过极板连接线35，使相邻子像素中的第二极板形成相互连接的一体结构，一体结构的第二极板可以复用为电源信号线，保证相邻子像素中的第二极板具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施例中，第二极板32邻近第一区域R1的边缘在基底上的正投影与第一区域R1与第二区域R2的交界线在基底上的正投影重叠，第二极板32邻近第三区域R3的边缘在基底上的正投影与第二区域R2与第三区域R3的交界线在基底上的正投影重叠，即第二极板32的长度等于第二区域R2的长度。
在示例性实施例中，节点电极36设置在第一区域R1内，节点电极36在基底上的正投影位于第一扫描信号线21在基底上的正投影的范围之内。
在示例性实施例中，第一遮挡层37和第二遮挡层38沿第一方向X延伸，设置在第一区域R1内，第一遮挡层37位于第一扫描信号线21远离第二区域R2的一侧，第二遮挡层38位于第一扫描信号线21邻近第二区域R2 的一侧。在示例性实施例中，第一遮挡层37配置为作为第一晶体管的遮挡层，遮挡第一晶体管的沟道，第二遮挡层38配置为作为第二晶体管的遮挡层，遮挡第二晶体管的沟道，保证氧化物第一晶体管和氧化物第二晶体管的电学性能。
如图17b所示，在垂直于基底的平面内，第一绝缘层91设置在基底10上，半导体层设置在第一绝缘层91上，第二绝缘层92覆盖半导体层，第一导电层设置在第二绝缘层92上，第三绝缘层93覆盖第一导电层，第二导电层设置在第三绝缘层93上，第二导电层至少包括极板连接线35和第二遮挡层38。
(24)形成第二半导体层图案。在示例性实施例中，形成第二半导体层图案可以包括：在形成前述图案的基底上，依次沉积第四绝缘薄膜和第二半导体薄膜，通过图案化工艺对第二半导体薄膜进行图案化，形成覆盖基底的第四绝缘层，以及设置在第四绝缘层上的第二半导体层，如图18a和图18b所示，图18b为图18a中B-B向的剖视图。
如图18a所示，每个子像素的第二半导体层可以包括第一晶体管T1的第一有源层11和第二晶体管T2的第二有源层12，第一有源层11和第二有源层12可以为相互连接的一体结构。
在示例性实施例中，第一有源层11和第二有源层12的形状可以呈“1”字形。第一有源层11的第一区与第七有源层的第一区邻近，第一有源层11的第二区同时作为第二有源层12的第一区，第二有源层的第二区与第三有源层的第二区邻近。
在示例性实施例中，第二半导体层可以采用氧化物，即第一晶体管和第二晶体管为氧化物薄膜晶体管。
如图18b所示，在垂直于基底的平面内，第一绝缘层91设置在基底10上，第一半导体层设置在第一绝缘层91上，第二绝缘层92覆盖第一半导体层，第一导电层设置在第二绝缘层92上，第三绝缘层93覆盖第一导电层，第二导电层设置在第三绝缘层93上，第四绝缘层94覆盖第二导电层，第二半导体层设置在第四绝缘层94上，第二半导体层至少包括第二有源层12。
(25)形成第三导电层图案。在示例性实施例中，形成第三导电层图案可以包括：在形成前述图案的基底上，依次沉积第五绝缘薄膜和第三金属薄膜，采用图案化工艺对第三金属薄膜和第五绝缘薄膜进行图案化，形成设置在第二半导体层上的第五绝缘层，以及设置在第五绝缘层上的第三导电层图案，第三导电层图案至少包括：第一辅助信号线48和第二辅助信号线49，如图19a和图19b所示，图19b为图19a中B-B向的剖视图。在示例性实施例中，第三导电层可以称为第三栅金属(GATE3)层。
如图19a所示，在示例性实施例中，第一辅助信号线48和第二辅助信号线49沿第一方向X延伸，设置在第一区域R1内，第一辅助信号线48与第一扫描信号线21靠近，且与第一扫描信号线21具有相同的信号，第二辅助信号线49与第二方向Y一侧的第二扫描信号线22靠近，且与第二扫描信号线22具有相同的信号。在示例性实施例中，第一辅助信号线48和第一扫描信号线21可以连接相同的信号源，第二辅助信号线49和第二扫描信号线22可以连接相同的信号源。在示例性实施例中，第一辅助信号线48与第二有源层重叠的区域作为第二晶体管的第二栅电极，第二辅助信号线49与第一有源层重叠的区域作为第一晶体管的第一栅电极。
在示例性实施例中，第一辅助信号线48在基底上的正投影与第二遮挡层38在基底上的正投影有重叠区域，第二辅助信号线49在基底上的正投影与第一遮挡层37在基底上的正投影有重叠区域，因而第一遮挡层37可以作为第一晶体管的遮挡层，第二遮挡层38可以作为第二晶体管的遮挡层。
如图19b所示，在垂直于基底的平面内，第一绝缘层91设置在基底10上，半导体层设置在第一绝缘层91上，第二绝缘层92覆盖第一半导体层，第一导电层设置在第二绝缘层92上，第三绝缘层93覆盖第一导电层，第二导电层设置在第三绝缘层93上，第四绝缘层94覆盖第二导电层，第二半导体层设置在第四绝缘层94上，第五绝缘层95设置在第二半导体层中的第二有源层12上，第一辅助信号线48设置在第五绝缘层95上。在示例性实施例中，第一辅助信号线48和第二辅助信号线49在基底上的正投影与第五绝缘层95在基底上的正投影基本上相同，或者，第五绝缘层95在基底上的正投影可以较第一辅助信号线48和第二辅助信号线49在基底上的正投影外扩， 以防止制备工艺中第一辅助信号线48和第二辅助信号线49与第二有源层12接触。在示例性实施例中，可以不对第五绝缘薄膜进行图案化处理，仅对第三金属薄膜进行图案化处理，形成覆盖第二有源层12的第五绝缘层95，第五绝缘层95覆盖整个基底。
(25)形成多晶硅过孔图案。在示例性实施例中，形成多晶硅过孔图案可以包括：在形成前述图案的基底上，沉积第六绝缘薄膜，采用图案化工艺对第六绝缘薄膜进行图案化，形成覆盖第三导电层的第六绝缘层，第六绝缘层上设置有多个过孔，多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7和第十三过孔V13，如图20a和图20b所示，图20b为图20a中B-B向的剖视图。
如图20a所示，在示例性实施例中，第一过孔V1位于第二极板32的开口34内，第一过孔V1在基底上的正投影位于开口34在基底上的正投影的范围之内，第一过孔V1内的第六绝缘层、第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一极板24的表面。第一过孔V1配置为使后续形成的第一晶体管T1的第二极与通过该过孔与第一极板24连接。
在示例性实施例中，第二过孔V2位于第二极板32所在区域，第二过孔V2在基底上的正投影位于第二极板32在基底上的正投影的范围之内，第二过孔V2内的第六绝缘层和第四绝缘层被刻蚀掉，暴露出第二极板32的表面。第二过孔V2配置为使后续形成的第一电源线通过该过孔与第二极板32连接。在示例性实施例中，作为电源过孔的第二过孔V2可以包括多个，多个第二过孔V2可以沿着第二方向Y依次排列，增加第一电源线与第二极板32的连接可靠性。
在示例性实施例中，第三过孔V3位于第三区域R3，第三过孔V3内的第六绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面。第三过孔V3配置为使后续形成的第一电源线通过该过孔与第五有源层连接。
在示例性实施例中，第四过孔V4位于第三区域R3，第四过孔V4内的第六绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第二区(也是第七有源层的第二区)的表面。第四过孔V4配置为 使后续形成的第六晶体管T6的第二极通过该过孔与第六有源层连接，以及使后续形成的第七晶体管T7的第二极通过该过孔与第七有源层连接。
在示例性实施例中，第五过孔V5位于第一区域R1，第五过孔V5内的第六绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面。第五过孔V5配置为使后续形成的数据信号线通过该过孔与第四有源层连接。
在示例性实施例中，第六过孔V6位于第二区域R2，第六过孔V6内的第六绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第一区(也是第三有源层的第二区)的表面。第六过孔V6配置为使后续形成的第六晶体管T6的第一极(也是第一晶体管T1的第二极和第二晶体管T2的第一极)通过该过孔与第六有源层连接。
在示例性实施例中，第七过孔V7位于第三区域R3，第七过孔V7内的第六绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第一区的表面。第七过孔V7配置为使后续形成的第七晶体管T7的第一极通过该过孔与第七有源层连接。
在示例性实施例中，第十三过孔V13位于第一区域R1，第十三过孔V13内的第六绝缘层和第四绝缘层被刻蚀掉，暴露出节点电极36的表面。第十三过孔V13配置为使后续形成的第一晶体管T1的第二极和第二晶体管T2的第一极通过该过孔与节点电极36连接。
如图20b所示，在垂直于基底的平面内，第一绝缘层91设置在基底10上，半导体层设置在第一绝缘层91上，第二绝缘层92覆盖第一半导体层，第一导电层设置在第二绝缘层92上，第三绝缘层93覆盖第一导电层，第二导电层设置在第三绝缘层93上，第四绝缘层94覆盖第二导电层，第二半导体层设置在第四绝缘层94上，第五绝缘层95设置在第二半导体层上，第三导电层设置在第五绝缘层95上，第六绝缘层96覆盖第三导电层，第六绝缘层96上设置有多个过孔，多个过孔至少包括第四过孔V4和第六过孔V6。第四过孔V4和第六过孔V6内的第六绝缘层94、第四绝缘层94、第三绝缘层93和第二绝缘层92被刻蚀掉，分别暴露出第六有源层两端的表面。
(26)形成氧化物过孔图案。在示例性实施例中，形成氧化物过孔图案 可以包括：在形成前述图案的基底上，采用图案化工艺形成多个过孔，多个过孔至少包括：第十四过孔V14、第十五过孔V15和第十六过孔V16，如图21a和图21b所示，图21b为图21a中B-B向的剖视图。
在示例性实施例中，第十四过孔V14位于第一区域R1，第十四过孔V14内的第六绝缘层被刻蚀掉，暴露出第二有源层的第一区(也是第一有源层的第二区)的表面。第十五过孔V15位于第二区域R2，第十五过孔V15内的第六绝缘层被刻蚀掉，暴露出第二有源层的第二区的表面。第十六过孔V16位于第三区域R3，第十六过孔V16内的第六绝缘层被刻蚀掉，暴露出第一有源层的第一区的表面。
如图21b所示，在垂直于基底的平面内，第一绝缘层91设置在基底10上，半导体层设置在第一绝缘层91上，第二绝缘层92覆盖第一半导体层，第一导电层设置在第二绝缘层92上，第三绝缘层93覆盖第一导电层，第二导电层设置在第三绝缘层93上，第四绝缘层94覆盖第二导电层，第二半导体层设置在第四绝缘层94上，第五绝缘层95设置在第二半导体层上，第三导电层设置在第五绝缘层95上，第六绝缘层96覆盖第三导电层，第六绝缘层96上设置有多个过孔，多个过孔至少包括第四过孔V4、第六过孔V6、第十四过孔V14和第十五过孔V15。第四过孔V4和第六过孔V6内的第六绝缘层94、第四绝缘层94、第三绝缘层93和第二绝缘层92被刻蚀掉，分别暴露出第六有源层两端的表面，第十四过孔V14和第十五过孔V15内的第六绝缘层94被刻蚀掉，分别暴露出第二有源层两端的表面。
(27)形成第四导电层图案。在示例性实施例中，形成第四导电层可以包括：在形成前述图案的基底上，沉积第四金属薄膜，采用图案化工艺对第四金属薄膜进行图案化，形成设置在第六绝缘层上的第四导电层，第四导电层至少包括：电源连接线51、初始信号线52、第五连接电极53、第六连接电极54、第七连接电极55和第八连接电极56，如图22a和图22b所示，图22b为图22a中B-B向的剖视图。在示例性实施例中，第四导电层可以称为第一源漏金属(SD1)层。
如图22a所示，在示例性实施例中，折线形的电源连接线51总体上沿着第二方向Y延伸，电源连接线51一方面通过第二过孔V2与第二极板32连 接，另一方面通过第三过孔V3与第五有源层连接，电源连接线51配置为与后续形成的第一电源线连接。
在示例性实施例中，初始信号线52沿着第一方向X延伸，设置在第三区域R3内，初始信号线52一方面通过第七过孔V7与第七有源层的第一区连接，另一方面通过第十六过孔V16与第一有源层的第一区连接，使第七晶体管T7的第一极和第一晶体管T1的第一极具有与初始信号线52相同的电位。
在示例性实施例中，第五连接电极53可以呈“C”字形，其第一端通过第一过孔V1与第一极板24连接，其第二端通过第十四过孔V14与第二有源层的第一区(也是第一有源层的第二区)连接，其第一端与第二端之间的区域通过第十三过孔V13与节点电极36连接，使第一极板24、第一晶体管T1的第二极、第二晶体管T2的第一极和节点电极36具有相同的电位。在示例性实施例中，第五连接电极53可以作为第一晶体管T1的第二极和第二晶体管T2的第一极。
在示例性实施例中，第六连接电极54可以为矩形状，第六连接电极54一方面通过第六过孔V6与第六有源层的第一区(也是第三有源层的第二区)连接，另一方面通过第十五过孔V15与第二有源层的第二区连接，使第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管的第一极具有相同的电位。在示例性实施例中，第六连接电极54可以作为第三晶体管T3的第二极和第二晶体管T2的第二极。
在示例性实施例中，第七连接电极55可以为矩形状，第七连接电极55通过第四过孔V4与第六有源层的第二区(也是第七有源层的第二区)连接，使第六晶体管T6的第二极和第七晶体管T7的第二极具有相同的电位。在示例性实施例中，第七连接电极55可以作为第六晶体管T6的第二极和第七晶体管T7的第二极。在示例性实施例中，第七连接电极55配置为与后续形成的阳极连接电极连接。
在示例性实施例中，第八连接电极56通过第五过孔V5与第四有源层的第一区连接。在示例性实施例中，第八连接电极56配置为与后续形成的数据信号线连接，使数据信号线传输的数据信号写入第四晶体管T4。
如图22b所示，在垂直于基底的平面内，第一绝缘层91设置在基底10上，半导体层设置在第一绝缘层91上，第二绝缘层92覆盖第一半导体层，第一导电层设置在第二绝缘层92上，第三绝缘层93覆盖第一导电层，第二导电层设置在第三绝缘层93上，第四绝缘层94覆盖第二导电层，第二半导体层设置在第四绝缘层94上，第五绝缘层95设置在第二半导体层上，第三导电层设置在第五绝缘层95上，第六绝缘层96覆盖第三导电层，第六绝缘层96上设置有多个过孔，第四导电层设置在第六绝缘层96上，第四导电层至少包括第五连接电极53、第六连接电极54和第七连接电极55，第七连接电极55通过第四过孔V4与第六有源层的一端连接，第六连接电极54一方面通过第六过孔V6与第六有源层的另一端连接，另一方面通过第十五过孔V15与第二有源层的一端连接，第五连接电极53通过第十四过孔V14与第二有源层的另一端连接。
(28)形成第七绝缘层和第一平坦层图案。在示例性实施例中，形成第七绝缘层和第一平坦层图案可以包括：在形成前述图案的基底上，先沉积一层第七绝缘薄膜，然后涂覆一层第一平坦薄膜，采用图案化工艺对第七绝缘薄膜和第一平坦薄膜进行图案化，形成覆盖第四导电层的第七绝缘层和覆盖第七绝缘层的第一平坦层，第七绝缘层和第一平坦层上设置有多个过孔，多个过孔至少包括第二十过孔V20、第二十一过孔V21和第二十二过孔V22，如图23a和图23b所示，图23b为图23a中B-B向的剖视图。
如图23a所示，第二十过孔V20位于第七连接电极55所在区域，第二十过孔V20内的第一平坦层和第七绝缘层被去掉，暴露出第七连接电极55的表面，第二十过孔V20配置为使后续形成的阳极连接电极通过该过孔与第七连接电极55连接。第二十一过孔V21位于第八连接电极56所在区域，第二十一过孔V21内的第一平坦层和第七绝缘层被去掉，暴露出第八连接电极56的表面，第二十一过孔V21配置为使后续形成的数据信号线通过该过孔与第八连接电极56连接。第二十二过孔V22位于电源连接线51所在区域，第二十二过孔V22内的第一平坦层和第七绝缘层被去掉，暴露出电源连接线51的表面，第二十二过孔V22配置为使后续形成的第一电源线通过该过孔与电源连接线51连接。
如图23b所示，在垂直于基底的平面内，第一绝缘层91设置在基底10上，半导体层设置在第一绝缘层91上，第二绝缘层92覆盖第一半导体层，第一导电层设置在第二绝缘层92上，第三绝缘层93覆盖第一导电层，第二导电层设置在第三绝缘层93上，第四绝缘层94覆盖第二导电层，第二半导体层设置在第四绝缘层94上，第五绝缘层95设置在第二半导体层上，第三导电层设置在第五绝缘层95上，第六绝缘层96覆盖第三导电层，第四导电层设置在第六绝缘层96上，第七绝缘层97和第一平坦层98覆盖第四导电层，第七绝缘层97和第一平坦层98上开设有多个过孔，多个过孔至少包括第二十过孔V20，第二十过孔V20内的第一平坦层98和第七绝缘层97被去掉，暴露出第七连接电极55的表面。
(29)形成第五导电层图案。在示例性实施例中，形成第五导电层可以包括：在形成前述图案的基底上，沉积第五金属薄膜，采用图案化工艺对第五金属薄膜进行图案化，形成设置在第一平坦层上的第五导电层，第五导电层至少包括：数据信号线61、第一电源线62和阳极连接电极63，如图24a和图24b所示，图24b为图24a中B-B向的剖视图所示。在示例性实施例中，第五导电层可以称为第二源漏金属(SD2)层。
如图24a所示，数据信号线61沿着第二方向Y延伸，数据信号线61通过第二十一过孔V21与第八连接电极56连接。由于第八连接电极56通过第五过孔与第四有源层的第一区连接，因而实现了数据信号线61与第四晶体管T4的第一极的连接，使数据信号线传输的数据信号写入第四晶体管T4。第一电源线62总体上沿着第二方向Y延伸，通过第二十二过孔V22与电源连接线51连接，使电源连接线51具有与第一电源线62相同的电位。在第一区域R1和第二区域R2，第一电源线62可以为矩形状，使得第一电源线62可以有效屏蔽像素驱动电路的关键节点，避免了像素驱动电路关键节点的电位受影响，提高了显示效果。阳极连接电极63可以为矩形状，阳极连接电极63通过第二十过孔V20与第七连接电极55连接，阳极连接电极63配置为与后续形成的阳极连接。
如图24b所示，在垂直于基底的平面内，第一绝缘层91设置在基底10上，半导体层设置在第一绝缘层91上，第二绝缘层92覆盖第一半导体层， 第一导电层设置在第二绝缘层92上，第三绝缘层93覆盖第一导电层，第二导电层设置在第三绝缘层93上，第四绝缘层94覆盖第二导电层，第二半导体层设置在第四绝缘层94上，第五绝缘层95设置在第二半导体层上，第三导电层设置在第五绝缘层95上，第六绝缘层96覆盖第三导电层，第四导电层设置在第六绝缘层96上，第七绝缘层97和第一平坦层98覆盖第四导电层，第五导电层设置在第一平坦层98上，第五导电层至少包括阳极连接电极63，阳极连接电极63通过第二十过孔V20与第七连接电极55连接。
(30)形成第二平坦层图案。在示例性实施例中，形成第二平坦层图案可以包括：在形成前述图案的基底上，涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成覆盖第五导电层的第二平坦层，第二平坦层上至少设置有第二十三过孔V23，如图25所示。
在示例性实施例中，第二十三过孔V23位于阳极连接电极63所在区域，第二十三过孔V23内的第二平坦层被去掉，暴露出阳极连接电极63的表面，第二十三过孔V23配置为使后续形成的阳极通过该过孔与阳极连接电极63连接。
(31)形成阳极图案。在示例性实施例中，形成阳极图案可以包括：在形成前述图案的基底上，沉积透明导电薄膜，采用图案化工艺对透明导电薄膜进行图案化，形成设置在第二平坦层上的阳极71，如图26所示。
在示例性实施例中，阳极71为六边形状，阳极71通过第二十三过孔V23与阳极连接电极63连接。由于阳极连接电极63通过第二十过孔与第七连接电极55连接，第七连接电极55通过第四过孔与第六有源层连接，因而实现了像素驱动电路可以驱动发光器件发光。
在示例性实施例中，后续制备流程可以包括：涂覆像素定义薄膜，通过图案化工艺对像素定义薄膜进行图案化，形成像素定义层，每个子像素的像素定义层设置有像素开口，像素开口暴露出阳极。采用蒸镀或喷墨打印工艺形成有机发光层，在有机发光层上形成阴极。形成封装层，封装层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
本公开前述所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开显示基板可以应用于具有像素驱动电路的其它显示装置中，如量子点显示等，本公开在此不做限定。
从以上描述的显示基板的结构以及制备过程可以看出，本公开提供的显示基板，通过将第三晶体管中沟道的漏端段设置成扇形状，增加了靠近漏电极一端沟道的面积，在相同的漏电极偏压下，可以使漏电场分散，从而减小横向电场，漏电极耗尽区在沟道方向变短，从而改善了因沟道变短引起的薄膜晶体管输出不饱和问题，可以使薄膜晶体管的输出特性平坦。本公开示例性实施例提出的输出特性平坦的短沟道驱动晶体管不仅可以节省空间，有利于高分辨率显示，而且沟道长度减小，驱动晶体管的阈值电压降低，有利于降低功耗。本公开的制备工艺可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开还提供一种显示基板的制作方法，以制作上述实施例提供的显示基板。
在示例性实施例中，在平行于显示基板的平面内，所述显示基板包括多个子像素，至少一个子像素包括像素驱动电路，所述像素驱动电路至少包括驱动晶体管；所述制备方法可以包括：
在基底上形成半导体层或第一半导体层；所述半导体层或第一半导体层至少包括驱动晶体管的有源层，所述驱动晶体管的有源层包括沟道区，所述沟道区包括沿第一方向延伸的漏端段、沿第一方向延伸的源端段和位于所述漏端段与源端段之间的中间段；所述漏端段在远离所述中间段的第一端具有第一宽度，所述漏端段在靠近所述中间段的第二端具有第二宽度；所述第一宽度大于所述第二宽度；所述宽度为所述漏端段第二方向上的尺寸，所述第一方向与第二方向交叉。
在示例性实施例中，所述驱动晶体管的有源层还包括与所述漏端段连接的第一区和与所述源端段连接的第二区，所述第一区的一端与所述漏端段的第一端连接，所述第一区的另一端与接收数据信号的晶体管连接；在平行于显示基板的平面内，所述源端段的形状包括矩形。
在示例性实施例中，在平行于显示基板的平面内，所述漏端段的形状包括梯形，所述梯形包括梯形下底和梯形上底，所述漏端段的第一端为梯形下底，具有第一宽度，所述漏端段的第二端为梯形上底，具有第二宽度。
在示例性实施例中，在平行于显示基板的平面内，所述漏端段的形状包括梯形和矩形的组合体，所述梯形包括梯形下底和梯形上底，所述矩形包括矩形下边和矩形上边；所述漏端段的第一端为梯形下底，具有第一宽度，所述梯形上底与所述矩形下边连接，具有第二宽度，所述漏端段的第二端为所述矩形上边。
在示例性实施例中，在平行于显示基板的平面内，所述漏端段的形状包括矩形和梯形的组合体，所述矩形包括矩形下边和矩形上边，所述梯形包括梯形下底和梯形上底；所述漏端段的第一端为矩形下边，所述矩形上边与所述梯形下底连接，具有第一宽度，所述漏端段的第二端为梯形上底，具有第二宽度。
在示例性实施例中，在平行于显示基板的平面内，所述漏端段的形状包括第一梯形和第二梯形的组合体，所述第一梯形包括第一梯形下底和第一梯形上底，所述第二梯形包括第二梯形下底和第二梯形上底；所述漏端段的第一端为第一梯形下底，具有第一宽度，所述第一梯形上底与所述第二梯形下底连接，所述漏端段的第二端为所述第二梯形上底，具有第二宽度。
在示例性实施例中，所述第一宽度与所述第二宽度之比为1.5至5。
在示例性实施例中，梯形侧边与所述第一方向之间的夹角为20°至60°。
在示例性实施例中，在垂直于显示基板的平面内，所述显示基板包括在基底上依次设置的半导体层、第一导电层、第二导电层和第三导电层；所述半导体层包括多个多晶硅晶体管的有源层，所述第一导电层包括多个多晶硅晶体管的栅电极和存储电容的第一极板，所述第二导电层包括存储电容的第二极板，所述第三导电层包括第一电源线、数据信号线和多个多晶硅晶体管的第一极和第二极。
在示例性实施例中，在垂直于显示基板的平面内，所述显示基板包括在 基底上依次设置的第一半导体层、第一导电层、第二导电层、第二半导体层、第三导电层、第四导电层和第五导电层；所述第一半导体层包括多个多晶硅晶体管的有源层，所述第一导电层包括多个多晶硅晶体管的栅电极和存储电容的第一极板，所述第二导电层包括存储电容的第二极板，所述第二半导体层包括多个氧化物晶体管的有源层，所述第三导电层包括多个氧化物晶体管的栅电极，所述第四导电层包括多个多晶硅晶体管的第一极和第二极以及多个氧化物晶体管的第一极和第二极，所述第五导电层包括第一电源线和数据信号线。
在示例性实施例中，所述沟道区的中间段包括第二沟道段、第三沟道段和第四沟道段；所述漏端段的第二端与所述第二沟道段的第一端连接；所述第二沟道段的第二端沿第二方向的反方向延伸后与所述第三沟道段的第一端连接；所述第三沟道段的第二端沿第一方向延伸后与所述第四沟道段的第一端连接；所述第四沟道段的第二端沿第二方向延伸后与所述源端段的第一端连接；所述源端段的第二端与所述有源层的第二区连接。
本公开还提供一种显示装置，显示装置包括前述的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (13)

  1. 一种显示基板，在平行于显示基板的平面内，所述显示基板包括多个子像素，至少一个子像素包括像素驱动电路，所述像素驱动电路至少包括驱动晶体管；所述驱动晶体管的有源层包括沟道区，所述沟道区包括沿第一方向延伸的漏端段、与所述漏端段连接的中间段以及与所述中间段连接的源端段；所述漏端段在远离所述中间段的第一端具有第一宽度，所述漏端段在靠近所述中间段的第二端具有第二宽度；所述第一宽度大于所述第二宽度；所述第一宽度和第二宽度为所述漏端段在第二方向上的尺寸，所述第一方向与第二方向交叉。
  2. 根据权利要求1所述的显示基板，其中，所述驱动晶体管的有源层还包括与所述漏端段连接的第一区和与所述源端段连接的第二区，所述第一区的一端与所述漏端段的第一端连接，所述第一区的另一端与接收数据信号的晶体管连接；在平行于显示基板的平面内，所述源端段的形状包括矩形。
  3. 根据权利要求1所述的显示基板，其中，在平行于显示基板的平面内，所述漏端段的形状包括梯形，所述梯形包括梯形下底和梯形上底，所述漏端段的第一端为梯形下底，具有第一宽度，所述漏端段的第二端为梯形上底，具有第二宽度。
  4. 根据权利要求1所述的显示基板，其中，在平行于显示基板的平面内，所述漏端段的形状包括梯形和矩形的组合体，所述梯形包括梯形下底和梯形上底，所述矩形包括矩形下边和矩形上边；所述漏端段的第一端为梯形下底，具有第一宽度，所述梯形上底与所述矩形下边连接，具有第二宽度，所述漏端段的第二端为所述矩形上边。
  5. 根据权利要求1所述的显示基板，其中，在平行于显示基板的平面内，所述漏端段的形状包括矩形和梯形的组合体，所述矩形包括矩形下边和矩形上边，所述梯形包括梯形下底和梯形上底；所述漏端段的第一端为矩形下边，所述矩形上边与所述梯形下底连接，具有第一宽度，所述漏端段的第二端为梯形上底，具有第二宽度。
  6. 根据权利要求1所述的显示基板，其中，在平行于显示基板的平面 内，所述漏端段的形状包括第一梯形和第二梯形的组合体，所述第一梯形包括第一梯形下底和第一梯形上底，所述第二梯形包括第二梯形下底和第二梯形上底；所述漏端段的第一端为第一梯形下底，具有第一宽度，所述第一梯形上底与所述第二梯形下底连接，所述漏端段的第二端为所述第二梯形上底，具有第二宽度。
  7. 根据权利要求1至6任一项所述的显示基板，其中，所述第一宽度与所述第二宽度之比为1.5至5。
  8. 根据权利要求3至6任一项所述的显示基板，其中，梯形至少一个侧边与所述第一方向之间的夹角大于0°，小于90°。
  9. 根据权利要求1至6任一项所述的显示基板，在垂直于显示基板的平面内，所述显示基板包括在基底上依次设置的半导体层、第一导电层、第二导电层和第三导电层；所述半导体层包括多个多晶硅晶体管的有源层，所述第一导电层包括多个多晶硅晶体管的栅电极和存储电容的第一极板，所述第二导电层包括存储电容的第二极板，所述第三导电层包括第一电源线、数据信号线和多个多晶硅晶体管的第一极和第二极。
  10. 根据权利要求1至6任一项所述的显示基板，在垂直于显示基板的平面内，所述显示基板包括在基底上依次设置的第一半导体层、第一导电层、第二导电层、第二半导体层、第三导电层、第四导电层和第五导电层；所述第一半导体层包括多个多晶硅晶体管的有源层，所述第一导电层包括多个多晶硅晶体管的栅电极和存储电容的第一极板，所述第二导电层包括存储电容的第二极板，所述第二半导体层包括多个氧化物晶体管的有源层，所述第三导电层包括多个氧化物晶体管的栅电极，所述第四导电层包括多个多晶硅晶体管的第一极和第二极以及多个氧化物晶体管的第一极和第二极，所述第五导电层包括第一电源线和数据信号线。
  11. 根据权利要求1至6任一项所述的显示基板，所述沟道区的中间段包括第二沟道段、第三沟道段和第四沟道段；所述漏端段的第二端与所述第二沟道段的第一端连接；所述第二沟道段的第二端沿第二方向的反方向延伸后与所述第三沟道段的第一端连接；所述第三沟道段的第二端沿第一方向延伸后与所述第四沟道段的第一端连接；所述第四沟道段的第二端沿第二方向 延伸后与所述源端段的第一端连接；所述源端段的第二端与所述有源层的第二区连接。
  12. 一种显示装置，包括如权利要求1至11任一项所述的显示基板。
  13. 一种显示基板的制备方法，在平行于显示基板的平面内，所述显示基板包括多个子像素，至少一个子像素包括像素驱动电路，所述像素驱动电路至少包括驱动晶体管；所述制备方法包括：
    在基底上形成半导体层或第一半导体层；所述半导体层或第一半导体层至少包括驱动晶体管的有源层，所述驱动晶体管的有源层包括沟道区，所述沟道区包括沿第一方向延伸的漏端段、与所述漏端段连接的中间段以及与所述中间段连接的源端段；所述漏端段在远离所述中间段的第一端具有第一宽度，所述漏端段在靠近所述中间段的第二端具有第二宽度；所述第一宽度大于所述第二宽度；所述第一宽度和第二宽度为所述漏端段在第二方向上的尺寸，所述第一方向与第二方向交叉。
PCT/CN2021/082057 2021-03-22 2021-03-22 显示基板及其制作方法、显示装置 WO2022198377A1 (zh)

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