WO2022028132A1 - 显示基板、显示装置 - Google Patents

显示基板、显示装置 Download PDF

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Publication number
WO2022028132A1
WO2022028132A1 PCT/CN2021/101198 CN2021101198W WO2022028132A1 WO 2022028132 A1 WO2022028132 A1 WO 2022028132A1 CN 2021101198 W CN2021101198 W CN 2021101198W WO 2022028132 A1 WO2022028132 A1 WO 2022028132A1
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WIPO (PCT)
Prior art keywords
gate
leads
electrically connected
lines
data
Prior art date
Application number
PCT/CN2021/101198
Other languages
English (en)
French (fr)
Inventor
刘聪
周宏军
杜丽丽
魏锋
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180001565.XA priority Critical patent/CN114556568A/zh
Priority to US17/778,504 priority patent/US11917876B2/en
Publication of WO2022028132A1 publication Critical patent/WO2022028132A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B27/00—Optical systems or apparatus not provided for by any of the groups G02B1/00 - G02B26/00, G02B30/00
    • G02B27/01—Head-up displays
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N17/00—Diagnosis, testing or measuring for television systems or their details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
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    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the embodiments of the present disclosure relate to the field of display technology, and in particular, to a display substrate and a display device.
  • part of the units or circuits used for driving the display can be directly arranged on the display substrate.
  • Embodiments of the present disclosure provide a display substrate, which includes:
  • a substrate including a display area and a peripheral area surrounding the display area;
  • a plurality of data lines at least located in the display area and extending along the first direction, the plurality of data lines are electrically connected to the plurality of sub-pixels;
  • a plurality of gate lines at least located in the display area and extending along a second direction, the plurality of gate lines are electrically connected to the plurality of sub-pixels; the first direction and the second direction intersect;
  • the plurality of data leads include a first group of data leads and a second group of data leads;
  • a gate driving circuit located in the peripheral region and electrically connected to the plurality of gate lines;
  • a plurality of gate driving lines located in the peripheral region and at least partially surrounding the display region, the plurality of gate driving lines being electrically connected to the gate driving circuit;
  • the plurality of gate leads are electrically connected to the plurality of gate driving lines and the plurality of pads; the plurality of The gate leads are located between the first set of data leads and the second set of data leads.
  • the plurality of gate driving lines include gate activation signal lines, first gate clock signal lines, second gate clock signal lines, gate driving test lines, high-level signal lines, low-level signal lines level signal line.
  • the display substrate further includes:
  • control electrode lines at least located in the display area and extending along the second direction, the plurality of control electrode lines are electrically connected to the plurality of sub-pixels;
  • a gate driving circuit located in the peripheral region and electrically connected to the plurality of gate lines;
  • a plurality of gate driving lines located in the peripheral region and at least partially surrounding the display region, the plurality of gate driving lines are electrically connected to the gate driving circuit;
  • a plurality of control electrode leads located in the peripheral region and extending along the first direction, the plurality of control electrode leads are electrically connected to the plurality of control electrode driving lines and the plurality of pads; the plurality of The gate leads are located between the first group of data leads and the second group of data leads.
  • the plurality of gate drive lines include a gate start signal line, a first gate clock signal line, a second gate clock signal line, a gate drive test line, a high-level signal line, a low-level signal line level signal line.
  • the gate driving circuit and the gate driving circuit are located on two opposite sides of the display area along the second direction.
  • the display substrate further includes:
  • a multiplexing circuit located in the peripheral area and electrically connected to the plurality of data lines;
  • the multiplexing circuit being electrically connected to the plurality of data driving lines and the plurality of data leads;
  • multiplexing driving lines located in the peripheral region and at least partially surrounding the display region, the multiplexing driving lines being electrically connected to the multiplexing circuit
  • a plurality of multiplexing leads are located in the peripheral region and extend along the first direction, the multiplexing leads are electrically connected to the multiplexing driving lines and the multiple pads. connected; the multiplexing leads are located between the first group of data leads and the second group of data leads.
  • the plurality of gate driving lines, the plurality of multiplexing driving lines, the plurality of data driving lines are located at the gate driving circuit, and the multiplexing circuit is far away from all on the side of the display area.
  • the multiplexed driving lines are located on a side of the plurality of gate driving lines away from the display area;
  • the plurality of data driving lines are located on a side of the plurality of multiplexing driving lines away from the display area.
  • the display substrate further includes:
  • test circuit located in the peripheral area and electrically connected to the plurality of data lines
  • test driving lines located in the peripheral region and at least partially surrounding the display region, the plurality of test driving lines being electrically connected to the test circuit;
  • a plurality of test leads located in the peripheral area and extending along the first direction, the plurality of test leads are electrically connected with the plurality of test drive lines and the plurality of pads; the plurality of test leads are located in the between the first group of data leads and the second group of data leads.
  • the plurality of test drive lines include test data signal lines and test control signal lines.
  • the display substrate further includes:
  • a multiplexing circuit located in the peripheral area and electrically connected to the plurality of data lines;
  • test circuit and the multiplexing circuit are located on two opposite sides of the display area along the first direction;
  • the plurality of pads are located on a side of the multiplexing circuit away from the display area.
  • the display substrate further includes:
  • an electrostatic discharge drive line located in the peripheral region and at least partially surrounding the display region, the electrostatic discharge drive line is electrically connected to the electrostatic discharge circuit;
  • an electrostatic discharge lead located in the peripheral region and extending along the first direction, the electrostatic discharge lead is electrically connected to the electrostatic discharge drive line and the pad; the electrostatic discharge lead is located in the first group of data between the leads and the second group of data leads.
  • the display substrate further includes:
  • an initialization driving line located in the peripheral region and at least partially surrounding the display region, the initialization driving line being electrically connected to the plurality of sub-pixels;
  • an initialization lead located in the peripheral area and extending along the first direction, the initialization lead is electrically connected to the initialization drive line and the pad; the initialization lead is located between the first group of data leads and the between the second set of data leads.
  • the display substrate further includes:
  • a first power drive line located in the peripheral region and at least partially surrounding the display region, the first power drive line is electrically connected to the plurality of sub-pixels;
  • a first power lead located in the peripheral area and extending along the first direction, the first power lead is electrically connected to the first power drive line and the pad; the first power lead is located in the between the first group of data leads and the second group of data leads;
  • a second power drive line located in the peripheral region and at least partially surrounding the display region, the second power drive line is electrically connected to the plurality of sub-pixels;
  • the first group of data leads is on a side away from the second group of data leads, or is located on the side of the second group of data leads away from the first group of data leads.
  • the plurality of pads are located in an access area and are arranged along the second direction; the access area is located on one side of the display area along the first direction;
  • the plurality of gate leads and the plurality of data leads are located in a lead-out area; the lead-out area is located between the access area and the display area along the first direction;
  • the plurality of gate wires are located between the first group of data wires and the second group of data wires along the second direction.
  • a plurality of the pads electrically connected to the plurality of gate leads are located on a plurality of the pads electrically connected to the first set of data leads and between a plurality of the pads electrically connected to the second group of data leads.
  • the display substrate further includes:
  • control electrode lines at least located in the display area and extending along the second direction, the plurality of control electrode lines are electrically connected to the plurality of sub-pixels;
  • a gate driving circuit located in the peripheral region and electrically connected to the plurality of gate lines;
  • a plurality of gate driving lines located in the peripheral region and at least partially surrounding the display region, the plurality of gate driving lines are electrically connected to the gate driving circuit;
  • a plurality of control electrode leads located in the peripheral region and extending along the first direction, the plurality of control electrode leads are electrically connected to the plurality of control electrode driving lines and the plurality of pads; the plurality of The gate leads are located between the first group of data leads and the second group of data leads.
  • the display substrate further includes:
  • a first power drive line located in the peripheral region and at least partially surrounding the display region, the first power drive line is electrically connected to the plurality of sub-pixels;
  • a first power lead located in the peripheral area and extending along the first direction, the first power lead is electrically connected to the first power drive line and the pad; the first power lead is located in the between the first group of data leads and the second group of data leads;
  • a second power drive line located in the peripheral region and at least partially surrounding the display region, the second power drive line is electrically connected to the plurality of sub-pixels;
  • a second power lead located in the peripheral region and extending along the first direction, the second power lead is electrically connected to the second power drive line and the pad; the second power lead is located on the The first group of data leads is away from the side of the second group of data leads, or is located on the side of the second group of data leads away from the first group of data leads;
  • the pads electrically connected to the first power supply leads are located away from the pads electrically connected to the first set of data leads away from the pads electrically connected to the second set of data leads.
  • one side of the pad, or the side of the pad electrically connected to the second group of data leads away from the pad electrically connected to the first group of data leads;
  • the pads electrically connected to the second power supply leads are positioned away from the pads electrically connected to the first set of data leads away from the pads electrically connected to the second set of data leads. the side of the pads, or the side of the pads electrically connected to the second group of data leads away from the pads electrically connected to the first group of data leads.
  • the display area is substantially circular
  • the display substrate is substantially circular.
  • an embodiment of the present disclosure provides a display device, which includes:
  • FIG. 1 is a schematic top-view structure diagram of a display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a top-view structural schematic diagram of a part of lead distribution in a display substrate according to an embodiment of the present disclosure
  • FIG. 3 is a schematic partial structure diagram of an access area and a lead-out area in a display substrate according to an embodiment of the present disclosure
  • FIG. 4 is a schematic partial structure diagram of an access area and a lead-out area in another display substrate according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of positions occupied by some structures in a display substrate according to an embodiment of the present disclosure
  • FIG. 6 is a circuit diagram of a sub-pixel in a display substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic partial cross-sectional structural diagram of a sub-pixel in a display substrate provided by an embodiment of the present disclosure
  • FIG. 8 is a circuit diagram of a gate shift register in a display substrate according to an embodiment of the present disclosure.
  • FIG. 9 is a driving timing diagram of the gate shift register of FIG. 8;
  • FIG. 10 is a circuit diagram of a gate shift register in a display substrate according to an embodiment of the present disclosure.
  • FIG. 11 is a driving timing diagram of the gate shift register of FIG. 10;
  • FIG. 12 is a circuit diagram of a multiplexing unit in a display substrate according to an embodiment of the present disclosure
  • FIG. 13 is a circuit diagram of a test unit in a display substrate provided by an embodiment of the present disclosure.
  • FIG. 14 is a circuit diagram of an electrostatic discharge unit in a display substrate provided by an embodiment of the present disclosure.
  • FIG. 15 is a partially enlarged structural design layout of the position A of the display substrate of FIG. 3;
  • FIG. 16 is a partially enlarged structural design layout of the position B of the display substrate of FIG. 4;
  • FIG. 17 is a partially enlarged structural design layout of the C position of the display substrate of FIG. 4;
  • FIG. 18 is a partially enlarged structural design layout of the D position of the display substrate of FIG. 4;
  • 19 is a partially enlarged structural design layout of a position of a peripheral area of a display substrate according to an embodiment of the present disclosure
  • FIG. 20 is a structural design layout of a gate shift register in a display substrate according to an embodiment of the present disclosure
  • 21 is a structural design layout of a gate shift register in a display substrate according to an embodiment of the present disclosure.
  • FIG. 22 is a structural design layout of a multiplexing unit in a display substrate according to an embodiment of the present disclosure
  • FIG. 23 is a structural design layout of a test unit in a display substrate provided by an embodiment of the present disclosure
  • FIG. 24 is a structural design layout of an electrostatic discharge unit in a display substrate according to an embodiment of the present disclosure.
  • Embodiments of the present disclosure may be described with reference to plan views and/or cross-sectional views with the aid of idealized schematic illustrations of the present disclosure. Accordingly, example illustrations may be modified according to manufacturing techniques and/or tolerances.
  • Embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of configurations formed based on manufacturing processes.
  • the regions illustrated in the figures have schematic properties and the shapes of regions illustrated in the figures are illustrative of the specific shapes of regions of elements and are not intended to be limiting.
  • ordinal numbers such as “first”, “second”, and “third” are set to avoid confusion of constituent elements, rather than to limit the quantity.
  • the terms “installed”, “connected” and “connected” should be interpreted in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed should be interpreted in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a is substantially B means that, on the scale of the whole of A, it conforms to the feature B, but on a scale that is obviously smaller than the entirety of A, A may not completely conform to the feature B.
  • a is substantially circular means that A can be a perfect circle or ellipse, or it can be a circle or ellipse as a whole, but some of its details are not strictly circular: for example, A A small part of the boundary of A may be a straight line, a polyline, etc.; another example, the boundary of A may have some positions with protrusions, depressions, etc.; another example, a small part of the boundary of A may be similar to an arc but not strictly an arc For another example, the boundaries of different positions of A can be circular arcs with different diameters, etc.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrically connected includes a case where constituent elements are connected together by means of elements having a certain electrical effect.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having a certain electrical effect” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore also includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • an embodiment of the present disclosure provides a display substrate.
  • each of the drive lines, leads, and auxiliary leads corresponding to a circuit is a "set of lines", and "a set of lines" may actually have multiple lines, and in some drawings, one or more lines may be used. Two lines represent multiple lines in the same group.
  • the display substrate of the embodiment of the present disclosure is a substrate used in a display device, such as an array substrate provided with a thin film transistor (TFT) array, and may also be provided with a light emitting device (eg, organic light emitting diode) for display.
  • a display device such as an array substrate provided with a thin film transistor (TFT) array
  • a light emitting device eg, organic light emitting diode
  • the substrate 9 includes a display area 91 and a peripheral area 92 surrounding the display area 91;
  • a plurality of data lines 12 at least located in the display area 91 and extending along the first direction 991, and the plurality of data lines 12 are electrically connected to the plurality of sub-pixels 1;
  • a plurality of data leads 73 located in the peripheral area 92, are electrically connected with a plurality of data lines 12 and a plurality of pads 8; the plurality of data leads 73 include a first group of data leads 738 and a second group of data leads 739;
  • the gate driving circuit A41 is located in the peripheral region 92 and is electrically connected to the plurality of gate lines 13;
  • a plurality of gate driving lines 61 located in the peripheral region 92 and at least partially surrounding the display region 91, the plurality of gate driving lines 61 are electrically connected to the gate driving circuit A41;
  • a plurality of gate leads 71 are located in the peripheral region 92 and extend along the first direction 991.
  • the plurality of gate leads 71 are electrically connected to the plurality of gate driving lines 61 and the plurality of pads 8; the plurality of gate leads 71 are located in the first direction 991.
  • various structures in the display substrate of the embodiment of the present disclosure are provided on the “substrate 9 ”.
  • the substrate 9 is the basis for carrying other structures on the display substrate, which is a substantially sheet-like structure composed of materials such as glass, silicon (such as monocrystalline silicon), and polymer materials (such as polyimide). , which can be rigid or flexible, and the thickness can be on the order of millimeters.
  • the above substrate 9 includes a display area 91 in the middle, and a peripheral area 92 surrounding the display area 91 .
  • the above display area 91 is provided with a plurality of sub-pixels 1 for displaying.
  • each sub-pixel 1 refers to the smallest structure that can be used to independently display the desired content, that is, the smallest "dot" that can be independently controlled in the display device.
  • different sub-pixels 1 can have different colors, so that color display can be realized by light mixing of different sub-pixels 1 .
  • a color display When a color display is to be realized, a plurality of sub-pixels 1 of different colors can be arranged together to form a "pixel (or pixel unit)", that is, the light emitted by these sub-pixels 1 is mixed together to form a visual "dot" ;
  • pixel or pixel unit
  • three sub-pixels 1 of three colors of red, green and blue can form a pixel.
  • the data lines 12 extending along the first direction 991 and the gate lines 13 extending along the second direction 992 are further provided, wherein the first direction 991 intersects the second direction 992 ( (that is, not parallel to each other), so that each intersection of the data line 12 and the gate line 13 can define a sub-pixel 1, and through the joint control of the gate line 13 and the data line 12, the intersection of the two can be
  • the sub-pixel 1 performs display; in addition, the control electrode line 14 extending along the second direction 992 may also be provided in the display area 91 , which also functions to control the sub-pixel 1 .
  • the first direction 991 is perpendicular to the second direction 992, that is, the first direction 991 may be a column direction (in each drawing, the longitudinal direction, or the column direction), and the second direction 992 may be perpendicular to the column direction Row direction (transverse in each drawing, or row direction).
  • first direction 991 and the second direction 992 are actually only two opposite directions corresponding to the data line 12 and the gate line 13 (or the gate line 14 ), which are not necessarily the column direction and the row direction, and are not necessarily the same as the display direction.
  • the shape, location and placement of the substrate (or display device) are not necessarily related.
  • the sub-pixels 1 in the display area 91 can be arranged in an array, that is, the sub-pixels 1 can be arranged in multiple rows and columns, wherein each row of the sub-pixels 1 is connected to one gate line 13 and one gate line 14 , and each column of sub-pixels 1 is connected to a data line 12 .
  • each data line 12 , gate line 13 , and gate line 14 are not necessarily connected to the sub-pixels 1 in the same column and row.
  • the sub-pixel 1 may include a pixel circuit, and the pixel circuit may emit light with a desired brightness under the control of the corresponding gate line 13, the data line 12, and the like.
  • the pixel circuit may be a 7T1C structure (ie, including 7 transistors and 1 capacitor). Referring to FIG.
  • the pixel circuit of the above 7T1C may include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4 , the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the storage capacitor Cst, the organic light emitting diode OLED, the first reset terminal Reset, the second reset terminal Reset', the initialization signal terminal Vinit, and the gate line 13 terminal Gate, data line 12 terminal Data, control terminal EM, first power signal terminal VDD, second power signal terminal VSS and other structures; wherein, each transistor can be a P-type transistor (eg PMOS).
  • each transistor can be a P-type transistor (eg PMOS).
  • an organic light emitting diode OLED can be used as a light emitting device, which is specifically an organic light emitting diode display substrate, which is also an array substrate provided with a thin film transistor (TFT) array.
  • TFT thin film transistor
  • the third transistor T3 in each sub-pixel 1 is a driving transistor, and the specific structures and stacking relationships of some of the devices may be as follows:
  • the driving transistor (third transistor T3) includes:
  • the first active layer 111 on one side of the substrate 9;
  • the second insulating layer 192 (interlayer insulating layer ILD) on the side of the first insulating layer 191 away from the substrate 9;
  • the first source electrode 113 and the first drain electrode 114 of the first active layer 111 are electrically connected on the side of the second insulating layer 192 away from the substrate 9;
  • the storage capacitor Cst includes:
  • the first pole piece 121 is disposed in the same layer as the first gate electrode 112;
  • the second pole piece 122 is located between the first insulating layer 191 and the second insulating layer 192 .
  • sub-pixel 1 may also include other structures.
  • the data line 12 end Data can be connected to the data line 12
  • the gate line 13 end Gate can be connected to the gate line 13
  • the gate line 14 end EM can be connected to the gate line 14, the first reset terminal Reset and the second reset terminal
  • the terminal Reset' can be connected to the gate line 13 of the previous row at the same time
  • the second reset terminal Reset' can also be connected to the gate line 13 of the current row
  • other terminals such as the initialization signal terminal Vinit, the first power signal terminal VDD, the
  • the two power supply signal terminals (VSS) can also be connected to corresponding signal sources, and these signal sources can be "lines", or they can be integrated conductive structures.
  • the above data line 12 , gate line 13 , control electrode line 14 , and the signals of the signal source for supplying power to the initialization signal terminal Vinit, the first power signal terminal VDD, and the second power signal terminal VSS are essentially provided by the Various drive lines in the peripheral area 92 that surround or partially surround the display area 91 are directly (eg, the drive lines are directly connected to lines or signal sources in the display area 91 ) or indirectly (eg, the drive lines are connected to the display area 91 through certain units. line or signal source).
  • the pad 8 (Pad or Pin) refers to a structure in the peripheral region 92 of the display substrate that can acquire other signals and finally introduce the signals to the sub-pixels 1 .
  • the pad 8 can be used for bonding with a flexible circuit board (FPC) or a driver chip, so as to obtain signals from the FPC or the driver chip; alternatively, the pad 8 can also be used for testing with a test device The probes make contact to obtain a signal from the test probe (or feed back a signal to the test probe).
  • FPC flexible circuit board
  • driver chip a driver chip
  • the data leads 73 that are finally electrically connected to the data lines 12 include two groups, namely the first group of data leads 738 and the second group of data leads 739 , and most of the other leads (at least The gate leads 71 ), which are ultimately electrically connected to the gate lines 13 , are located “between” the first set of data leads 738 and the second set of data leads 739 .
  • the data lead 73 is on the "outside" (eg, the outside in the second direction 992 ) relative to the other test leads 75 .
  • the number of data leads 73 is usually the largest, so it needs to be transformed from extending along the first direction 991 (longitudinal) to extending around the display area 91 (ie, the data driving lines 63 ) that need to be occupied by the fan-out lines
  • the area of (Fanout) is also larger.
  • the data leads 73 are arranged on both sides of other leads (or closer to the side), so as to be closer to both sides of the peripheral area 92 , which facilitates fan-out, reduces the wiring area, and compresses the frame of the display device. width to achieve a narrow border design.
  • the dimension d1 in the second direction 992 can be saved, or the dimension h1 in the first direction 991 can be saved, the size of the peripheral area 92 can be reduced, and a narrow frame design can be realized.
  • the display area 91 is substantially circular; the display substrate is substantially circular.
  • the above display area 91 and the display substrate may be substantially circular, so that the peripheral area 92 outside the display area 91 is substantially “circular”,
  • the entire display device corresponding to the display substrate is also substantially circular, such as a circular "smart watch”.
  • the above shape is not a limitation on the specific form of the display substrate and each area therein, and the display substrate and each area therein may also be of other shapes.
  • the plurality of gate driving lines 61 include a gate activation signal line 611, a first gate clock signal line 612, a second gate clock signal line 613, a gate driving test line 614, a high level signal Line 615, low level signal line 616.
  • the above gate drive lines 61 may specifically include gate start signal lines 611 , first gate clock signal lines 612 , second gate clock signal lines 613 , gate drive test lines 614 , and high-level signal lines 615 , a low-level signal line 616 .
  • the gate driving circuit A41 may be composed of a plurality of gate driving units 41, and each gate driving unit 41 provides a gate driving signal to one gate line 13; wherein, each gate driving unit 41 may The second direction 992 (row direction in each drawing) is located on both sides of the display area 91, respectively, so as to provide gate driving signals for the gate lines 13 in different rows, or to provide the gate lines 13 from both sides at the same time.
  • pole drive signal double-sided drive
  • each gate driving unit 41 can be a gate shift register (GOA), and a plurality of gate shift registers are cascaded, so that the plurality of gate shift registers can respectively connect to a plurality of gate lines 13 Provide the drive signal.
  • GOA gate shift register
  • the specific forms of the gate shift register are various. Exemplarily, reference may be made to FIG. 8 , FIG. 20 , and FIG. 9 for the circuit structure and driving timing of the gate shift register.
  • the low level of each of the following signals may be specifically equal to the low-level signal VGL, and the high level of each signal may specifically be equal to the high-level signal VGH.
  • the first gate clock signal CK is at a low level
  • the second gate clock signal CB is at a high level
  • the gate enable signal GSTV is at a low level. Since the first gate clock signal CK is at a low level, the second gate transistor K2 is turned on, and the gate enable signal GSTV is transmitted to the third gate node N3 through the second gate transistor K2. Since the second gate transistor K2 has a threshold loss, the level of the third gate node N3 is GSTV-Vth2, ie VGL-Vth2, where Vth2 represents the threshold level of the second gate transistor K2.
  • the sixth gate transistor K6 Since the gate of the sixth gate transistor K6 receives the low-level signal VGL, the sixth gate transistor K6 is in an on state, whereby the level VGL-Vth2 is transmitted to the first gate node via the sixth gate transistor K6 N1.
  • the threshold level of the sixth gate transistor K6 is represented as Vth6.
  • the sixth gate transistor K6 since the sixth gate transistor K6 has a threshold loss, the level of the first gate node N1 is VGL-VthN1, where VthN1 is Vth2 and The smaller one in Vth6.
  • the level of the first gate node N1 can control the eighth gate transistor K8 to be turned on, and the second gate clock signal CB is used as the gate output signal GOUT via the eighth gate transistor K8, that is, in the input stage t1, the gate
  • the output signal GOUT is the second gate clock signal CB at a high level, that is, equal to VGH.
  • the first gate transistor K1 is turned on, and the low level signal VGL is transmitted to the second gate node N2 through the first gate transistor K1.
  • the level of the tri-gate node N3 is VGL-Vth2
  • the seventh gate transistor K7 is turned on, and the low-level first gate clock signal CK is transmitted to the second gate node N2 through the seventh gate transistor K7.
  • the threshold level of the seventh gate transistor K7 is represented as Vth7
  • the threshold level of the first gate transistor K1 is represented as Vth1.
  • the level of the second gate node N2 is VGL -Vth7-Vth2; and when Vth1>Vth7+Vth2, the level of the second gate node N2 is VGL-Vth1.
  • both the third gate transistor K3 and the fourth gate transistor K4 are turned on. Since the second gate clock signal CB is at a high level, the fifth gate transistor K5 is turned off.
  • the first gate clock signal CK is at a high level
  • the second gate clock signal CB is at a low level
  • the gate enable signal GSTV is at a high level.
  • the eighth gate transistor K8 is turned on, and the second gate clock signal CB is used as the gate output signal GOUT via the eighth gate transistor K8.
  • the level of one end of the second gate capacitor C2 connected to the first gate node N1 is VGL-VthN1, and the level of the other end is high level; and in the output stage t2, the second gate capacitance
  • the level of one end of C2 connected to the output terminal GOUT becomes VGL, and due to the bootstrap effect of the second gate capacitor C2, the level of one end of the second gate capacitor C2 connected to the first gate node N1 becomes 2VGL- VthN1-VGH, that is, the level of the first gate node N1 becomes 2VGL-VthN1-VGH, at this time, the sixth gate transistor K6 is turned off, the eighth gate transistor K8 can be better turned on, and the gate output signal GOUT It is the low level signal VGL.
  • the first gate clock signal CK is at a high level, so that both the second gate transistor K2 and the first gate transistor K1 are turned off.
  • the level of the third gate node N3 is still VGL-VthN1
  • the seventh gate transistor K7 is turned on, and the high-level first gate clock signal CK is transmitted to the second gate node N2 through the seventh gate transistor K7 , that is, the level of the second gate node N2 is VGH, so that both the third gate transistor K3 and the fourth gate transistor K4 are turned off. Since the second gate clock signal CB is at a low level, the fifth gate transistor K5 is turned on.
  • the first gate clock signal CK and the second gate clock signal CB are both at a high level, and the gate enable signal GSTV is at a high level.
  • the eighth gate transistor K8 is turned on, and the second gate clock signal CB is used as the gate output signal GOUT through the eighth gate transistor K8.
  • the gate output signal GOUT is the second gate clock signal CB with a high level , namely VGH. Due to the bootstrap effect of the second gate capacitor C2, the level of the first gate node N1 becomes VGL-VthN1.
  • the first gate clock signal CK is at a high level, so that both the second gate transistor K2 and the first gate transistor K1 are turned off.
  • the level of the first gate node N1 becomes VGL-VthN1, at this time, the sixth gate transistor K6 is turned on, the level of the third gate node N3 is also VGL-VthN1, and the seventh gate transistor K7 is turned on , the high-level first gate clock signal CK is transmitted to the second gate node N2 through the seventh gate transistor K7, that is, the level of the second gate node N2 is VGH, so that the third gate transistor K3 and the fourth gate transistor K4 are both turned off. Since the second gate clock signal CB is at a high level, the fifth gate transistor K5 is turned off.
  • the first gate clock signal CK is at a low level
  • the second gate clock signal CB is at a high level
  • the gate enable signal GSTV is at a high level. Since the first gate clock signal CK is at a low level, the second gate transistor K2 is turned on, and the gate enable signal GSTV is transmitted to the third gate node N3 through the second gate transistor K2. There is no threshold loss to pass a high level, the level of the third gate node N3 is VGH, and the seventh gate transistor K7 is turned off.
  • the sixth gate transistor K6 Since the sixth gate transistor K6 is in an on state, the level of the first gate node N1 is the same as that of the third gate node N3, that is, the level of the first gate node N1 is VGH, and the eighth gate transistor K8 deadline. Since the first gate clock signal CK is at a low level, the first gate transistor K1 is turned on, the level of the second gate node N2 is VGL-Vth1, the third gate transistor K3 and the fourth gate transistor K4 are both When turned on, the high-level signal VGH is transmitted through the third gate transistor K3 as the gate output signal GOUT, that is, the gate output signal is the high-level signal VGH.
  • the first gate clock signal is at a high level
  • the second gate clock signal is at a low level
  • the gate enable signal GSTV is at a high level.
  • the levels of the first gate node N1 and the third gate node N3 are VGH
  • the eighth gate transistor K8 and the seventh gate transistor K7 are both turned off.
  • the first gate clock signal CK is at a high level, so that both the second gate transistor K2 and the first gate transistor K1 are turned off.
  • the level of the second gate node N2 is still For VGL-Vth1
  • the third gate transistor K3 and the fourth gate transistor K4 are both turned on, and the high level signal VGH is used as the gate output signal GOUT via the third gate transistor K3, that is, the gate output signal is high level signal VGH.
  • the fifth gate transistor K5 is turned on, so that the high level signal VGH passes through the fourth gate transistor K4 and the fifth gate transistor K5 is transmitted to the third gate node N3 and the first gate node N1, so that the level of the first gate node N1 and the level of the third gate node N3 are maintained at a high level.
  • both the first gate clock signal CK and the second gate clock signal CB are at a high level, and the gate enable signal GSTV is at a high level.
  • the levels of the first gate node N1 and the third gate node N3 are VGH, and the eighth gate transistor K8 and the seventh gate transistor K7 are turned off.
  • the first gate clock signal CK is at a high level, so that both the second gate transistor K2 and the first gate transistor K1 are turned off, the level of the second gate node N2 is still VGL-Vth1, and the third gate transistor K3 and the fourth gate transistor K4 are both turned on.
  • the high-level signal VGH is used as the gate output signal GOUT through the third gate transistor K3, that is, the gate output signal is the high-level signal VGH.
  • the above first gate clock signal CK can be provided through the above first gate clock signal line 612
  • the second gate clock signal CB can be provided through the above second gate clock signal line 613
  • the high level signals VGH the high level signals VGH
  • the low-level signal VGL is respectively provided through the high-level signal line 615 and the low-level signal line 616 .
  • the gate start signal GSTV is provided by the gate output signal GOUT of the gate shift register of the previous stage, the gate start signal GSTV of the gate shift register of the first stage is provided through the gate start signal line 611, and the gate start signal of the last stage is provided by the gate start signal line 611.
  • the gate output signal GOUT generated by the pole shift register is also connected to the gate driving test line 614 to check whether the gate driving circuit A41 works normally.
  • the display substrate further includes:
  • control electrode lines 14 at least located in the display area 91 and extending along the second direction 992, and the plurality of control electrode lines 14 are electrically connected to the plurality of sub-pixels 1;
  • the gate driving circuit A42 is located in the peripheral area 92 and is electrically connected to the plurality of gate lines 14;
  • a plurality of gate driving lines 62 located in the peripheral region 92 and at least partially surrounding the display region 91, the plurality of gate driving lines 62 are electrically connected to the gate driving circuit A42;
  • a plurality of gate leads 72 are located in the peripheral region 92 and extend along the first direction 991.
  • the plurality of gate leads 72 are electrically connected to the plurality of gate drive lines 62 and the plurality of pads 8; the plurality of gate leads 72 are located in the first direction.
  • the signal of the above gate line 14 can be provided by the gate drive circuit A42, and the gate drive circuit A42 is driven by the gate drive line 62, and the gate drive line 62 is connected to the gate extending along the first direction 991.
  • the lead 72, the gate lead 72 is also located between the first group of data leads 738 and the second group of data leads 739 above.
  • the plurality of gate drive lines 62 include a gate start signal line 621, a first gate clock signal line, a second gate clock signal line 623, a gate drive test line 624, a high level signal line 615, low level signal line 616.
  • the gate driving circuit A42 may be composed of a plurality of gate driving units 42, and each gate driving unit 42 provides a gate driving signal to a gate line 14; wherein, each gate driving unit 42 may Located on both sides of the display area 91 along the second direction 992 (row direction in each drawing), respectively, to provide gate drive signals for the gate lines 14 in different rows, or to provide control for the gate lines 14 from both sides at the same time pole drive signal (double-sided drive).
  • each gate driving unit 42 can be one gate shift register (EM GOA), and multiple gate shift registers are cascaded, so that multiple gate shift registers can respectively connect to multiple gate lines 14 provides the drive signal.
  • EM GOA gate shift register
  • control pole shift register The specific forms of the control pole shift register are various. Exemplarily, reference may be made to Fig. 10, Fig. 21, and Fig. 11 for the circuit structure and driving timing of the gate shift register.
  • the low level of each of the following signals may be specifically equal to the low-level signal VGL, and the high level of each signal may specifically be equal to the high-level signal VGH.
  • the first gate clock signal CK' is at a low level, so the first gate transistor M1 and the third gate transistor M3 are turned on, and the turned-on first gate transistor M1 will be high
  • the level of the gate start signal ESTV is transmitted to the first gate node N1', so that the level of the first gate node N1' becomes a high level, so the second gate transistor M2 and the eighth gate transistor M8 And the tenth gate transistor M10 is turned off.
  • the turned-on third gate transistor M3 transmits the low-level low-level signal VGL to the second gate node N2', so that the level of the second gate node N2' becomes a low level, so
  • the fifth gate transistor M5 and the sixth gate transistor M6 are turned on. Since the second gate clock signal CB' is at a high level, the seventh gate transistor M7 is turned off.
  • the level of the fourth gate node N4 can be maintained at a high level, so that the ninth gate transistor M9 is turned off.
  • the gate output signal EMOUT maintains the previous low level.
  • the second gate clock signal CB' is at a low level, so the fourth gate transistor M4 and the seventh gate transistor M7 are turned on. Since the first gate clock signal CK' is at a high level, the first gate transistor M1 and the third gate transistor M3 are turned off. Due to the storage function of the first gate capacitor C1', the second gate node N2' can continue to maintain the low level of the previous stage, so the fifth gate transistor M5 and the sixth gate transistor M6 are turned on.
  • the high-level signal VGH is transmitted to the first gate node N1' through the turned-on fifth gate transistor M5 and the fourth gate transistor M4, so that the level of the first gate node N1' continues to maintain the previous stage.
  • the second gate transistor M2, the eighth gate transistor M8 and the tenth gate transistor M10 are turned off.
  • the low-level second gate clock signal CB' is transmitted to the fourth gate node N4' through the turned-on sixth gate transistor M6 and the seventh gate transistor M7, thereby making the fourth gate node N4 ' becomes a low level, so the ninth gate transistor M9 is turned on, and the turned-on ninth gate transistor M9 outputs a high-level signal VGH, so the gate output signal EMOUT is at a high level.
  • the first gate clock signal CK' is at a low level, so the first gate transistor M1 and the third gate transistor M3 are turned on.
  • the second gate clock signal CB' is at a high level, so the fourth gate transistor M4 and the seventh gate transistor M7 are turned off. Due to the storage function of the third gate capacitor C3', the level of the fourth gate node N4' can maintain the low level of the previous stage, so that the ninth gate transistor M9 remains in an on state, and the turned-on th
  • the nine-gate transistor M9 outputs the high level signal VGH, so the gate output signal EMOUT is still at a high level.
  • the first gate clock signal CK' is at a high level, so the first gate transistor M1 and the third gate transistor M3 are turned off.
  • the second gate clock signal CB' is at a low level, so the fourth gate transistor M4 and the seventh gate transistor M7 are turned on. Due to the storage function of the second gate capacitor C2', the level of the first gate node N1' maintains the high level of the previous stage, so that the second gate transistor M2, the eighth gate transistor M8 and the tenth gate transistor M8 are Gate transistor M10 is turned off. Due to the storage function of the first gate capacitor C1', the second gate node N2 continues to maintain the low level of the previous stage, so that the fifth gate transistor M5 and the sixth gate transistor M6 are turned on.
  • the low-level second gate clock signal CB' is transmitted to the fourth gate node N4' through the turned-on sixth gate transistor M6 and the seventh gate transistor M7, thereby making the fourth gate node N4 ' becomes low, so the ninth gate transistor M9 is turned on, and the turned on ninth gate transistor M9 outputs the high-level signal VGH, so the gate output signal EMOUT is still high.
  • the first gate clock signal CK' is at a low level, so the first gate transistor M1 and the third gate transistor M3 are turned on.
  • the second gate clock signal CB' is at a high level, so the fourth gate transistor M4 and the seventh gate transistor M7 are turned off.
  • the turned-on first gate transistor M1 transmits the low-level gate start signal ESTV to the first gate node N1', so that the level of the first gate node N1' becomes a low level, so the second gate
  • the gate transistor M2, the eighth gate transistor M8, and the tenth gate transistor M10 are turned on.
  • the turned-on second gate transistor M2 transmits the low-level first gate clock signal CK' to the second gate node N2', so that the level of the second gate node N2' can be further pulled down, so the first gate
  • the second gate node N2' continues to maintain the low level of the previous stage, so that the fifth gate transistor M5 and the sixth gate transistor M6 are turned on.
  • the turned-on eighth gate transistor M8 transmits the high-level signal VGH to the fourth gate node N4', so that the level of the fourth gate node N4 becomes a high level, so the ninth gate transistor M9 is cut off.
  • the turned-on tenth gate transistor M10 outputs the low level signal VGL, so the gate output signal EMOUT becomes the low level.
  • the above first gate clock signal CK' can be provided through the above first gate clock signal line 622, and the second gate clock signal CB' can be provided through the above second gate clock signal line 623, the high level signal The VGH and the low-level signal VGL are respectively provided through the high-level signal line 615 and the low-level signal line 616 .
  • the gate start signal ESTV is provided through the gate output signal EOUT of the upper stage gate shift register, the gate start signal ESTV of the first stage gate shift register is provided through the gate start signal line 621, and the last stage controls
  • the gate output signal EOUT generated by the pole shift register is also connected to the gate driving test line 624 to check whether the gate driving circuit A42 works normally.
  • the gate driving line 61 The high-level signal line 615 in the gate driving line 62 may actually be the same line, and the gate driving line 61 and the low-level signal line 616 in the gate driving line 62 may also be actually the same line.
  • the gate driving circuit A41 and the gate driving circuit A42 are located on two opposite sides of the display area 91 along the second direction 992 .
  • the gate driving circuit A41 and the gate driving circuit A42 correspond to the gate line 13 and the gate line 14 respectively, and the gate line 13 and the gate line 14 both extend along the second direction 992 , the wiring From a simple point of view, the gate driving circuit A41 (a plurality of gate driving units 41 ) and the gate driving circuit A42 (a plurality of gate driving units 42 ) may be disposed opposite to each other along the second direction 992 .
  • the display substrate further includes:
  • the multiplexing circuit A2 is located in the peripheral area 92 and is electrically connected to the plurality of data lines 12;
  • a plurality of data driving lines 63 are located in the peripheral area 92 and at least partially surround the display area 91, and the multiplexing circuit A2 is electrically connected to the plurality of data driving lines 63 and the plurality of data leads 73;
  • a plurality of multiplexing driving lines 64 located in the peripheral area 92 and at least partially surrounding the display area 91, the multiplexing driving lines 64 are electrically connected to the multiplexing circuit;
  • a plurality of multiplexing leads 74 are located in the peripheral region 92 and extend along the first direction 991, and the multiplexing leads 74 are electrically connected to the multiplexing drive lines 64 and the plurality of pads 8; Multiplexing leads 74 are located between a first set of data leads 738 and a second set of data leads 739 .
  • the display substrate may include a multiplexing circuit A2 for enabling each data driving line 63 under the control of a plurality of multiplexing driving lines 64 It can be turned on with different data lines 12 in a time-divisional manner. Therefore, each data driving line 63 (or each data lead 73 ) can correspond to a plurality of data lines 12 , thereby reducing the number of data driving lines 63 and data leads 73 (and corresponding pads 8 and chips) and simplifying the product structure, and it is easy to realize the narrow frame design of the display device.
  • a multiplexing circuit A2 for enabling each data driving line 63 under the control of a plurality of multiplexing driving lines 64 It can be turned on with different data lines 12 in a time-divisional manner. Therefore, each data driving line 63 (or each data lead 73 ) can correspond to a plurality of data lines 12 , thereby reducing the number of data driving lines 63 and data leads 73 (and corresponding pads 8 and chips) and simplifying the product structure,
  • the above multiplexing drive lines 64 also need to be connected to the pads 8 through the multiplexing leads 74 extending along the first direction 991, and the multiplexing leads 74 are also located in the above-mentioned first direction 991. between one set of data leads 738 and a second set of data leads 739 .
  • the multiplexing circuit A2 may include multiple multiplexing units 2 (MUX).
  • MUX multiple multiplexing units 2
  • the multiple multiplexing units 2 include m multiplexing transistors 21 (m is at least 2);
  • each multiplexing transistor 21 of each multiplexing unit 2 the gate of each multiplexing transistor 21 is electrically connected to one of the multiplexing driving lines 64, and the The first electrodes are respectively electrically connected to one of the plurality of data lines 12 , and the second electrodes of the m multiplexing transistors 21 are all electrically connected to one of the plurality of data driving lines 63 .
  • the turn-on signal can be provided to each multiplexing drive line 64 in a time-divisional manner, so that each multiplexing unit can be provided with a turn-on signal.
  • Each multiplexing transistor 21 in 2 is turned on in a time division; and when any multiplexing transistor 21 is turned on, the data signal required by the data line 12 electrically connected to the multiplexing transistor 21 is provided through the corresponding data driving line 63, to write the data signal into the corresponding sub-pixel 1.
  • each multiplexing unit 2 can control 3 data lines 12 (one for three).
  • the number of data lines 12 can be equal to “m*the number of multiplexing units 2”; and the number of multiplexing driving lines 64 cannot be less than m, for example, referring to FIG. 12 and FIG. 22, when each When two multiplexing units 2 are electrically connected to one data driving line 63 , the number of the multiplexing driving lines 64 may be m (for example).
  • the distribution modes of the layers where each structure of the multiplexing unit 2 is specifically located may be various.
  • each multiplexing transistor 21 can be disposed in the same layer as the first active layer 111 and arranged at intervals, and is covered by the gate insulating layer 190; and the gate of each multiplexing transistor 21 can be the same as the first gate. 112 is arranged in the same layer, and at the same time, there is also a structure for electrically connecting the first electrode of the partial multiplexing transistor 21 with the corresponding data line 12 (or a part of the data line 12); and the first source electrode 113 and the same layer as the first drain 114, the first and second poles of the multiplexing transistors 21 may be provided, wherein the second poles of the multiplexing transistors 21 in the same multiplexing unit 2 are connected as a whole. ; And through the via hole in the second insulating layer 192, the electrical connection of the corresponding structure can be realized.
  • a plurality of gate driving lines 61 , a plurality of multiplexing driving lines 64 , and a plurality of data driving lines 63 are located on the side of the gate driving circuit A41 and the multiplexing circuit A2 away from the display area 91 .
  • a plurality of multiplexing driving lines 64 are located on a side of the plurality of gate driving lines 61 away from the display area 91;
  • the plurality of data driving lines 63 are located on a side of the plurality of multiplexing driving lines 64 away from the display area 91 .
  • the above gate drive lines 61, multiplexing drive lines 64, and data drive lines 63 may be provided in the gate drive circuit A41 (there may also be a gate drive circuit A42), multiplexing circuit A2 " so that these circuits are closer to the display area 91 to supply power to the data lines 12 and gate lines 13 in the display area 91 .
  • the gate drive line 61 (and also the gate drive line 62 ) may be the "most inner", because the shift register (gate shift register, gate shift register, control electrode shift The driving of the bit register) is relatively important, so the corresponding line is preferably as close to the shift register as possible; and the number of data driving lines 63 is the largest, occupying a larger area, so it can be at the outermost side.
  • the specific positions of the units in various driving circuits can be set as required.
  • each gate driving unit 41 of the gate driving circuit A41 can be along the circumferential direction of the peripheral area 92 with each multiplexing unit 2 of the multiplexing circuit A2 "Mixed".
  • the gate driving units 42 of the gate driving circuit A42 can be “shuffled” with the multiplexing units 2 of the multiplexing circuit A2 along the circumferential direction of the peripheral area 92 . .
  • the gate driving units 41 of the gate driving circuit A41 can be “shuffled” with the test units 3 of the test circuit A3 described later along the circumferential direction of the peripheral area 92 .
  • the gate driving units 41 of the gate driver circuit A42 and the test units 3 of the test circuit A3 described later can be “shuffled” along the circumferential direction of the peripheral area 92 .
  • the electrostatic discharge unit 5 of the electrostatic discharge circuit A5 described later is small in number, so it can only be provided in some other structures in the gap position.
  • the first power drive line 68 and the initialization drive line 67 described later may be located “inside” the gate drive unit 41 , the multiplexing unit 2 and other units (the first power drive line 68 may be the most reliable inside, initialization drive line 67 outside).
  • the second power drive line 69 described later is located “outside” the data drive line 63, and of course also “outside” the gate driving unit 41, the multiplexing unit 2 and other units.
  • test drive line 65 described later can be arranged on a different gate drive line 61 (or control between the pole driving lines 62), wherein the specific arrangement order is various (the driving lines of the same type are not necessarily consecutively arranged together).
  • the display substrate further includes:
  • the test circuit A3 is located in the peripheral area 92 and is electrically connected to the plurality of data lines 12;
  • test drive lines 65 located in the peripheral area 92 and at least partially surrounding the display area 91, the plurality of test drive lines 65 are electrically connected to the test circuit A3;
  • a plurality of test leads 75 are located in the peripheral area 92 and extend along the first direction 991.
  • the plurality of test leads 75 are electrically connected to the plurality of test drive lines 65 and the plurality of pads 8; the plurality of test leads 75 are located in the first group of data leads 738 and the second set of data leads 739.
  • test circuit A3 in the display substrate, and the test circuit A3 is also connected to each data line 12, so that each sub-pixel 1 can be tested under the control of a plurality of test drive lines 65, for example, when the display substrate leaves the factory Before lighting test.
  • test drive lines 65 also need to be connected to the corresponding pads 8 through the test leads 75 extending along the first direction 991, and the test leads 75 are also located in the first group of data leads 738 and the second group of data leads between 739.
  • the plurality of test drive lines 65 include test data signal lines 651 and test control signal lines 652 .
  • test circuit A3 may include a plurality of test cells 3 (CT).
  • each test unit 3 is electrically connected to at least one test data signal line 651, at least one test control signal line 652, and at least one of the plurality of data lines 12, and is configured to control according to the at least one test control signal line 652.
  • the signal provided by the signal line 652 provides the signal provided by the at least one test data signal line 651 to the at least one data line 12 .
  • the total number of at least one test data signal line 651 is n (at least 2, for example, 3), and the total number of at least one test control signal line 652 is One, n is an integer greater than or equal to 2;
  • At least one of the plurality of test units 3 includes n test transistors 31;
  • the gates 311 of the n test transistors 31 are electrically connected to a test control signal line 652, and the first poles 313 of each test transistor 31 are electrically connected to the plurality of data lines 12 respectively.
  • One of the n test data signal lines 651 is electrically connected to the second pole 314 of each test transistor 31 respectively.
  • the number of test data signal lines 651 is n, and there is only one test control signal line 652; and each test unit 3 also includes n test transistors 31, the n test transistors 31
  • the gates 311 of the n test transistors 31 are all electrically connected to the test control signal line 652
  • the first electrodes 313 are electrically connected to different data lines 12 respectively
  • the second electrodes 314 eg sources of the n test transistors 31 are respectively
  • the n test data signal lines 651 are electrically connected (ie, the second electrodes of different test transistors 31 are electrically connected to different test data signal lines 651 ).
  • test transistor 31 in each test unit 3 can be controlled through the test control signal line 652, and the signal of each test data signal line 651 can be controlled to be written into different data lines 12, that is, "whether to test";
  • a conduction signal can be provided to the test control signal line 652, and a required signal can be provided to the n test data signal lines 651 respectively, so that each data line 12 can obtain the required signal to realize detection.
  • the number of data lines 12 may be equal to n*the number of test cells 3 .
  • n 3.
  • the sub-pixels 1 electrically connected to each data line 12 have the same color, for example, the sub-pixels 1 in the same column have the same color, for example, the columns of red, green, and blue sub-pixels are arranged along the second direction 992 .
  • the red sub-pixel, the green sub-pixel, and the blue sub-pixel are represented by R, G, and B, respectively.
  • the same signal can be provided to the data lines 12 corresponding to the sub-pixels 1 of the same color, so that these sub-pixels 1 perform the same display (such as lighting or not lighting), so as to pass the display screen.
  • the color determines whether there is a defective sub-pixel 1, and locates the defective sub-pixel 1.
  • the arrangement of the colors of the sub-pixels 1 and the specific form of the test unit 3 are not limited to this.
  • the display substrate further includes:
  • the multiplexing circuit A2 is located in the peripheral area 92 and is electrically connected to the plurality of data lines 12;
  • test circuit A3 and the multiplexing circuit A2 are located on two opposite sides of the display area 91 along the first direction 991;
  • the plurality of pads 8 are located on the side of the multiplexing circuit A2 away from the display area 91 .
  • test circuit A3 and the multiplexing circuit A2 since the test circuit A3 and the multiplexing circuit A2 must be connected to the data line 12, and the data line 12 extends along the first direction 991, the test circuit A3 (multiple The test unit 3) and the multiplexing circuit A2 (a plurality of multiplexing units 2) can be arranged opposite to each other along the first direction 991; and since the multiplexing circuit A2 requires the largest number of data driving lines 63, so The pad 8 can be provided on the side where the multiplexing circuit A2 is located, so that the data driving line 63 can be connected to the multiplexing circuit A2 "nearly" without going around a half circle and connecting again.
  • the display substrate further includes:
  • Electrostatic discharge circuit A5 located in the peripheral area 92;
  • the electrostatic discharge drive line 66 is located in the peripheral area 92 and at least partially surrounds the display area 91, and the electrostatic discharge drive line 66 is electrically connected to the electrostatic discharge circuit A5;
  • the electrostatic discharge lead is located in the peripheral area 92 and extends along the first direction 991.
  • the electrostatic discharge lead is electrically connected to the electrostatic discharge drive line 66 and the pad 8; the electrostatic discharge lead is located between the first group of data leads 738 and the second group of data leads 739. between.
  • the display substrate further includes an electrostatic discharge circuit A5 for discharging other lines (eg, gate driving line 61 , gate driving line 62 , multiplexing driving line 64 , test driving line 65 ) etc.) in order to avoid the electrostatic breakdown caused by the excessive accumulation of static electricity in the line; and the electrostatic discharge circuit A5 can work under the control of the electrostatic discharge drive line 66, and the electrostatic discharge drive line 66 is connected to the electrostatic discharge lead. , and the electrostatic discharge leads are also located between the first group of data leads 738 and the second group of data leads 739 .
  • other lines eg, gate driving line 61 , gate driving line 62 , multiplexing driving line 64 , test driving line 65 .
  • the electrostatic discharge circuit A5 may include an electrostatic discharge unit 5 (ESD).
  • ESD electrostatic discharge unit 5
  • Each electrostatic discharge unit 5 is used to discharge the static electricity in the lines that need to be protected (such as the gate driving line 61, the gate driving line 62, the multiplexing driving line 64, the test driving line 65, etc.) to the electrostatic discharge driving line on line 66.
  • the electrostatic discharge drive line 66 may include an electrostatic high level line 661 and an electrostatic low level line 662; each electrostatic discharge unit 5 includes a first discharge transistor 51 and a second discharge transistor 51 Transistor 52: the gate and the first electrode of the first discharge transistor 51 are connected to the electrostatic high-level line 661, and the second electrode is connected to the line that needs to be protected by the electrostatic discharge unit 5 (the upper vertical line in FIG. 14); the second discharge transistor The gate and the first electrode of 52 are connected to the line to be protected by the electrostatic discharge unit 5 , and the second electrode is connected to the electrostatic low-level line 662 .
  • the high-level signal VGH and the low-level signal VGL are continuously loaded on the electrostatic high-level line 661 and the electrostatic low-level line 662 above, respectively.
  • the above electrostatic discharge unit 5 includes a first discharge transistor 51 and a second discharge transistor 52, wherein one pole of each discharge transistor is connected to its own gate, thereby forming an equivalent "diode". Therefore, when an instantaneous high voltage (such as 100V) occurs in the line that needs to be protected by the electrostatic discharge unit 5 due to the accumulation of positive charges, the "diode" of the first discharge transistor 51 is turned on to discharge the positive charge in the signal line; When an instantaneous low voltage (eg -100V) occurs due to the accumulation of negative charges, the "diode” of the second discharge transistor 52 is turned on to discharge the negative charges in the signal line.
  • an instantaneous high voltage such as 100V
  • an instantaneous low voltage eg -100V
  • the display substrate further includes:
  • the initialization drive line 67 is located in the peripheral area 92 and at least partially surrounds the display area 91, and the initialization drive line 67 is electrically connected to the plurality of sub-pixels 1;
  • the initialization lead 77 is located in the peripheral area 92 and extends along the first direction 991.
  • the initialization lead 77 is electrically connected to the initialization drive line 67 and the pad 8; the initialization lead 77 is located between the first group of data leads 738 and the second group of data leads 739 .
  • the peripheral area 92 may also be provided with an initialization drive line 67, and
  • the initialization drive line 67 is connected to the initialization line 77 , which is also located between the first group of data lines 738 and the second group of data lines 739 .
  • the display substrate further includes:
  • the first power driving line 68 is located in the peripheral region 92 and at least partially surrounds the display region 91, and the first power driving line 68 is electrically connected to the plurality of sub-pixels 1;
  • the first power lead 78 is located in the peripheral area 92 and extends along the first direction 991.
  • the first power lead 78 is electrically connected to the first power drive line 68 and the pad 8; the first power lead 78 is located between the first group of data leads 738 and the between the second group of data leads 739;
  • the second power drive line 69 is located in the peripheral area 92 and at least partially surrounds the display area 91, and the second power drive line 69 is electrically connected to the plurality of sub-pixels 1;
  • the second power lead 79 is located in the peripheral area 92 and extends along the first direction 991.
  • the second power lead 79 is electrically connected to the second power drive line 69 and the pad 8; the second power lead 79 is located in the first group of data leads 738 away from
  • the second group of data leads 739 is on the side, or on the side of the second group of data leads 739 away from the first group of data leads 738 .
  • the peripheral area 92 can also be provided with a first power drive line 68 and a second power drive line 69, and the first power drive line 68 and the second power drive line 69 pass along the first direction 991 respectively.
  • the extended first power supply lead 78 and the second power supply lead 79 are connected to the pad 8 .
  • the first power lead 78 is also located between the above first group of data leads 738 and the second group of data leads 739; while the second power lead 79 is different, located between the above first group of data leads 738 and the second group Data lead 739 "outside".
  • the first power lead 78 is in the middle, the initialization lead 77 is on both sides, and then goes out
  • the two sides are the test lead 75 and the multiplexing lead 74 at the same time, and the two outer sides are the gate lead 71 and the control electrode lead 72 respectively (in the figure, the gate lead 71 is on the left, and the control electrode lead 72 is on the left side. right as an example).
  • the test drive line 65 , the multiplexed drive line 64 , the high-level signal line 615 , the low-level signal line 616 , etc. can form a closed loop, so it is different from any of them.
  • the plurality of pads 8 are located in the access area 921 and are arranged along the second direction 992; the access area 921 is located on one side of the display area 91 along the first direction 991;
  • the plurality of gate leads 71 and the plurality of data leads 73 are located in the lead-out area 922; the lead-out area 922 is located between the access area 921 and the display area 91 along the first direction 991;
  • the plurality of gate leads 71 are located between the first set of data leads 738 and the second set of data leads 739 .
  • the above plurality of pads 8 can be arranged in a row along the second direction 992 , and are located in the access area 921 on one side of the display area 91 along the first direction 991 ; In between, the lead-out regions 922 for the above leads are provided.
  • the leads extend in the lead-out area 922 along the first direction 991, and different leads should be arranged along the second direction 992, that is, most of the other leads (except the second power lead 79) should be in the first
  • the two directions 992 are located between the first group of data leads 738 and the second group of data leads 739 , or the first group of data leads 738 and the second group of data leads 739 are respectively located on both sides of the other majority leads in the second direction 992 .
  • the plurality of pads 8 electrically connected to the plurality of gate leads 71 are located at the plurality of pads 8 electrically connected to the first set of data leads 738 and to the second set of data
  • the leads 739 are electrically connected between the plurality of pads 8 .
  • the pads 8 corresponding to the data leads 73 should also be divided into two groups, and they should be located on most of the other leads (except the first power lead 78 , the second power lead 78 , the second power lead The lead 79) corresponds to the outside of the pad 8.
  • the display substrate further includes:
  • control electrode lines 14 at least located in the display area 91 and extending along the second direction 992, and the plurality of control electrode lines 14 are electrically connected to the plurality of sub-pixels 1;
  • the gate driving circuit A42 is located in the peripheral area 92 and is electrically connected to the plurality of gate lines 14;
  • a plurality of gate driving lines 62 located in the peripheral region 92 and at least partially surrounding the display region 91, the plurality of gate driving lines 62 are electrically connected to the gate driving circuit A42;
  • a plurality of gate leads 72 are located in the peripheral region 92 and extend along the first direction 991.
  • the plurality of gate leads 72 are electrically connected to the plurality of gate drive lines 62 and the plurality of pads 8; the plurality of gate leads 72 are located in the first direction. between a group of data leads 738 and a second group of data leads 739;
  • the plurality of pads 8 electrically connected to the plurality of data leads 73 are located on the plurality of pads 8 that are electrically connected to the plurality of gate leads 71 and the plurality of pads 8 that are electrically connected to the plurality of gate leads 72 Between pads 8;
  • At least part of the data leads 73 are electrically connected to the plurality of pads 8 through the plurality of data auxiliary leads 731
  • the plurality of gate leads 71 are electrically connected to the plurality of pads 8 through the plurality of gate auxiliary leads 711
  • the plurality of control electrode leads 72 The plurality of pads 8 are electrically connected through a plurality of gate auxiliary leads 721 .
  • the gate lead 71 , the gate lead 72 (and the multiplexed lead 74 and the test lead 75 may also be used) , the initialization lead 77, the first power lead 78) are still located between the first group of data leads 738 and the second group of data leads 739 in the second direction 992;
  • the two directions 992 are located in the middle of the pads 8 corresponding to the gate lead 71, the gate lead 72 (and the multiplex lead 74, the test lead 75, the initialization lead 77, and the first power lead 78).
  • the data lead 73 needs to be connected to the pad 8 through the data auxiliary lead 731, that is, the data auxiliary lead 731 extends at least partially along the second direction 992, so that in the second direction 992, the signal from the pad 8 is routed from the middle. to both sides into the data leads 73 .
  • the gate lead 71 and the gate lead 72 are respectively connected to the corresponding pads 8 through the gate auxiliary lead 711 and the gate auxiliary lead 721 (while the multiplexing lead 74, the test lead 75, the initialization lead 77,
  • the first power supply lead 78 is also connected to the corresponding pad 8 through the multiplexing auxiliary lead 741, the test auxiliary lead 751, the initialization auxiliary lead 771, and the first power supply auxiliary lead 781 respectively).
  • the display substrate further includes:
  • the first power driving line 68 is located in the peripheral region 92 and at least partially surrounds the display region 91, and the first power driving line 68 is electrically connected to the plurality of sub-pixels 1;
  • the first power lead 78 is located in the peripheral area 92 and extends along the first direction 991.
  • the first power lead 78 is electrically connected to the first power drive line 68 and the pad 8; the first power lead 78 is located between the first group of data leads 738 and the between the second group of data leads 739;
  • the second power drive line 69 is located in the peripheral area 92 and at least partially surrounds the display area 91, and the second power drive line 69 is electrically connected to the plurality of sub-pixels 1;
  • the second power lead 79 is located on the side of the first group of data leads 738 away from the second group of data leads 739, or on the side of the second group of data leads 739 away from the first group of data leads 738;
  • the pads 8 electrically connected to the first power supply leads 78 are located on the side of the pads 8 electrically connected to the first set of data leads 738 away from the pads 8 electrically connected to the second set of data leads 739, Or located on the side of the pad 8 electrically connected to the second group of data leads 739 away from the pad 8 electrically connected to the first group of data leads 738;
  • the pads 8 electrically connected to the second power supply leads 79 are located on the side of the pads 8 electrically connected to the first group of data leads 738 away from the pads 8 electrically connected to the second group of data leads 739, Or located on the side of the pad 8 electrically connected to the second group of data leads 739 away from the pad 8 electrically connected to the first group of data leads 738;
  • the first power supply lead 78 is electrically connected to the pad 8 through the first power supply auxiliary lead 781 .
  • the pads 8 corresponding to the first power supply lead 78 and the second power supply lead 79 are usually located on both sides of the other pads 8, or The other pads 8 are located between the two pads 8 connected to the first power supply lead 78 and also between the two pads 8 connected to the second power supply lead 79 .
  • the first power lead 78 since the first power lead 78 is located between the first set of data leads 738 and the second set of data leads 739 , the first power lead 78 needs to be connected through the first power auxiliary lead 781 extending at least partially along the second direction 992 Corresponding pad 8.
  • the second power lead 79 is located outside the first group of data leads 738 and the second group of data leads 739 , it can be directly connected to the corresponding pad 8 .
  • an embodiment of the present disclosure provides a display device, which includes:
  • the above display substrates can be combined with other devices (eg, cell cover plates, flexible circuit boards, driving chips, power supply components, etc.) to form a display device with a display function.
  • other devices eg, cell cover plates, flexible circuit boards, driving chips, power supply components, etc.
  • the display device is a wearable display device.
  • the above display device is particularly suitable as a wearable display device that can be worn on the human body.
  • the display device can be a smart watch worn on a human wrist.
  • the wearable display device may also include devices such as a watch strap that are worn on the human body.
  • the above display devices are not limited to wearable display devices, but can also be any products or components with display functions, such as electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, and navigators.

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Abstract

一种显示基板，包括：基底（9），包括显示区（91）和围绕显示区（91）的周边区（92）；多个子像素（1），位于显示区（91）；多条数据线（12），至少位于显示区（91）且沿第一方向（991）延伸，多条数据线（12）与多个子像素（1）电连接；多条栅极线（13），至少位于显示区（91）且沿第二方向（992）延伸，多条栅极线（13）与多个子像素（1）电连接；第一方向（991）和第二方向（992）交叉；多个焊盘（8），位于周边区（92）；多条数据引线（73），位于周边区（92），与多条数据线（12）、多个焊盘（8）电连接；多条数据引线（73）包括第一组数据引线（738）和第二组数据引线（739）；栅极驱动电路（A41），位于周边区(92)，且与多条栅极线(13)电连接；多条栅极驱动线(61)，位于周边区(92)且至少部分围绕显示区(91)，多条栅极驱动线(61)与栅极驱动电路（A41）电连接；多条栅极引线(71)，位于周边区(92)且沿第一方向(991)延伸，多条栅极引线(71)与多条栅极驱动线(61)、多个焊盘(8)电连接；多条栅极引线(71)位于第一组数据引线(738)与第二组数据引线(739)之间。

Description

显示基板、显示装置 技术领域
本公开实施例涉及显示技术领域，特别涉及一种显示基板、显示装置。
背景技术
为了简化驱动芯片、检测装置等的结构，可将部分用于驱动显示的单元或电路直接设于显示基板上。
发明内容
本公开实施例提供一种显示基板，其包括：
基底，包括显示区和围绕所述显示区的周边区；
多个子像素，位于所述显示区；
多条数据线，至少位于所述显示区且沿第一方向延伸，所述多条数据线与所述多个子像素电连接；
多条栅极线，至少位于所述显示区且沿第二方向延伸，所述多条栅极线与所述多个子像素电连接；所述第一方向和所述第二方向交叉；
多个焊盘，位于所述周边区；
多条数据引线，位于所述周边区，与所述多条数据线、所述多个焊盘电连接；所述多条数据引线包括第一组数据引线和第二组数据引线；
栅极驱动电路，位于所述周边区，且与所述多条栅极线电连接；
多条栅极驱动线，位于所述周边区且至少部分围绕所述显示区，所述多条栅极驱动线与所述栅极驱动电路电连接；
多条栅极引线，位于所述周边区且沿所述第一方向延伸，所述多条栅极引线与所述多条栅极驱动线、所述多个焊盘电连接；所述多条 栅极引线位于所述第一组数据引线与所述第二组数据引线之间。
在一些实施例中，所述多条栅极驱动线包括栅极启动信号线、第一栅极时钟信号线、第二栅极时钟信号线、栅极驱动测试线、高电平信号线、低电平信号线。
在一些实施例中，所述显示基板还包括：
多条控制极线，至少位于所述显示区且沿第二方向延伸，所述多条控制极线与所述多个子像素电连接；
控制极驱动电路，位于所述周边区，且与所述多条控制极线电连接；
多条控制极驱动线，位于所述周边区且至少部分围绕所述显示区，所述多条控制极驱动线与所述控制极驱动电路电连接；
多条控制极引线，位于所述周边区且沿所述第一方向延伸，所述多条控制极引线与所述多条控制极驱动线、所述多个焊盘电连接；所述多条控制极引线位于所述第一组数据引线与所述第二组数据引线之间。
在一些实施例中，所述多条控制极驱动线包括控制极启动信号线、第一控制极时钟信号线、第二控制极时钟信号线、控制极驱动测试线、高电平信号线、低电平信号线。
在一些实施例中，所述栅极驱动电路与所述控制极驱动电路沿所述第二方向位于所述显示区的两个相对侧。
在一些实施例中，所述显示基板还包括：
多路复用电路，位于所述周边区，且与所述多条数据线电连接；
多条数据驱动线，位于所述周边区且至少部分围绕所述显示区，所述多路复用电路与所述多条数据驱动线与所述多条数据引线电连接；
多条多路复用驱动线，位于所述周边区且至少部分围绕所述显示区，所述多条多路复用驱动线与所述多路复用电路电连接；
多条多路复用引线，位于所述周边区且沿所述第一方向延伸，所述多条多路复用引线与所述多条多路复用驱动线、所述多个焊盘电连 接；所述多条多路复用引线位于所述第一组数据引线与所述第二组数据引线之间。
在一些实施例中，所述多条栅极驱动线、所述多条多路复用驱动线、所述多条数据驱动线位于所述栅极驱动电路、所述多路复用电路远离所述显示区一侧。
在一些实施例中，所述多条多路复用驱动线位于所述多条栅极驱动线远离所述显示区的一侧；
所述多条数据驱动线位于所述多条多路复用驱动线远离所述显示区的一侧。
在一些实施例中，所述显示基板还包括：
测试电路，位于所述周边区，且与所述多条数据线电连接；
多条测试驱动线，位于所述周边区且至少部分围绕所述显示区，所述多条测试驱动线与所述测试电路电连接；
多条测试引线，位于所述周边区且沿所述第一方向延伸，所述多条测试引线与所述多条测试驱动线、所述多个焊盘电连接；所述多条测试引线位于所述第一组数据引线与所述第二组数据引线之间。
在一些实施例中，所述多条测试驱动线包括测试数据信号线、测试控制信号线。
在一些实施例中，所述显示基板还包括：
多路复用电路，位于所述周边区，且与所述多条数据线电连接；
所述测试电路与所述多路复用电路沿所述第一方向位于所述显示区的两个相对侧；
所述多个焊盘位于所述多路复用电路远离所述显示区的一侧。
在一些实施例中，所述显示基板还包括：
静电释放电路，位于所述周边区；
静电释放驱动线，位于所述周边区且至少部分围绕所述显示区，所述静电释放驱动线与所述静电释放电路电连接；
静电释放引线，位于所述周边区且沿所述第一方向延伸，所述静电释放引线与所述静电释放驱动线、所述焊盘电连接；所述静电释放引线位于所述第一组数据引线与所述第二组数据引线之间。
在一些实施例中，所述显示基板还包括：
初始化驱动线，位于所述周边区且至少部分围绕所述显示区，所述初始化驱动线与所述多个子像素电连接；
初始化引线，位于所述周边区且沿所述第一方向延伸，所述初始化引线与所述初始化驱动线、所述焊盘电连接；所述初始化引线位于所述第一组数据引线与所述第二组数据引线之间。
在一些实施例中，所述显示基板还包括：
第一电源驱动线，位于所述周边区且至少部分围绕所述显示区，所述第一电源驱动线与所述多个子像素电连接；
第一电源引线，位于所述周边区且沿所述第一方向延伸，所述第一电源引线与所述第一电源驱动线、所述焊盘电连接；所述第一电源引线位于所述第一组数据引线与所述第二组数据引线之间；
第二电源驱动线，位于所述周边区且至少部分围绕所述显示区，所述第二电源驱动线与所述多个子像素电连接；
第二电源引线，位于所述周边区且沿所述第一方向延伸，所述第二电源引线与所述第二电源驱动线、所述焊盘电连接；所述第二电源引线位于所述第一组数据引线背离所述第二组数据引线一侧，或位于所述第二组数据引线背离所述第一组数据引线一侧。
在一些实施例中，所述多个焊盘位于接入区，且沿所述第二方向排列；所述接入区沿所述第一方向位于所述显示区一侧；
所述多条栅极引线、所述多条数据引线位于引出区；所述引出区沿所述第一方向位于所述接入区与所述显示区之间；
所述沿所述第二方向，所述多条栅极引线位于所述第一组数据引线与所述第二组数据引线之间。
在一些实施例中，沿所述第二方向，与所述多条栅极引线电连接 的多个所述焊盘，位于与所述第一组数据引线电连接的多个所述焊盘以及与所述第二组数据引线电连接的多个所述焊盘之间。
在一些实施例中，所述显示基板还包括：
多条控制极线，至少位于所述显示区且沿第二方向延伸，所述多条控制极线与所述多个子像素电连接；
控制极驱动电路，位于所述周边区，且与所述多条控制极线电连接；
多条控制极驱动线，位于所述周边区且至少部分围绕所述显示区，所述多条控制极驱动线与所述控制极驱动电路电连接；
多条控制极引线，位于所述周边区且沿所述第一方向延伸，所述多条控制极引线与所述多条控制极驱动线、所述多个焊盘电连接；所述多条控制极引线位于所述第一组数据引线与所述第二组数据引线之间。
在一些实施例中，所述显示基板还包括：
第一电源驱动线，位于所述周边区且至少部分围绕所述显示区，所述第一电源驱动线与所述多个子像素电连接；
第一电源引线，位于所述周边区且沿所述第一方向延伸，所述第一电源引线与所述第一电源驱动线、所述焊盘电连接；所述第一电源引线位于所述第一组数据引线与所述第二组数据引线之间；
第二电源驱动线，位于所述周边区且至少部分围绕所述显示区，所述第二电源驱动线与所述多个子像素电连接；
第二电源引线，位于所述周边区且沿所述第一方向延伸，所述第二电源引线与所述第二电源驱动线、所述焊盘电连接；所述第二电源引线位于所述第一组数据引线背离所述第二组数据引线一侧，或位于所述第二组数据引线背离所述第一组数据引线一侧；
沿所述第二方向，与所述第一电源引线电连接的所述焊盘位于与所述第一组数据引线电连接的所述焊盘背离于与所述第二组数据引线电连接的所述焊盘一侧，或位于与所述第二组数据引线电连接的所述 焊盘背离于与所述第一组数据引线电连接的所述焊盘一侧；
沿所述第二方向，与所述第二电源引线电连接的所述焊盘位于与所述第一组数据引线电连接的所述焊盘背离于与所述第二组数据引线电连接的所述焊盘一侧，或位于与所述第二组数据引线电连接的所述焊盘背离于与所述第一组数据引线电连接的所述焊盘一侧。
在一些实施例中，所述显示区基本为圆形；
所述显示基板基本为圆形。
第二方面，本公开实施例提供一种显示装置，其包括：
上述的任意一种显示基板。
附图说明
附图用来提供对本公开实施例的进一步理解，并且构成说明书的一部分，与本公开实施例一起用于解释本公开，并不构成对本公开的限制。通过参考附图对详细示例实施例进行描述，以上和其它特征和优点对本领域技术人员将变得更加显而易见，在附图中：
图1为本公开实施例提供的一种显示基板的俯视结构示意图；
图2为本公开实施例提供的一种显示基板中部分引线分布的俯视结构示意图；
图3为本公开实施例提供的一种显示基板中接入区和引出区的局部结构示意图；
图4为本公开实施例提供的另一种显示基板中接入区和引出区的局部结构示意图；
图5为本公开实施例提供的一种显示基板中部分结构所占位置的示意图；
图6为本公开实施例提供的一种显示基板中的一种子像素的电路图；
图7为本公开实施例提供的一种显示基板中的一种子像素的局部剖面结构示意图；
图8为本公开实施例提供的一种显示基板中的一种栅极移位寄存器的电路图；
图9为图8的栅极移位寄存器的驱动时序图；
图10为本公开实施例提供的一种显示基板中的一种控制极移位寄存器的电路图；
图11为图10的控制极移位寄存器的驱动时序图；
图12为本公开实施例提供的一种显示基板中的一种多路复用单元的电路图
图13为本公开实施例提供的一种显示基板中的一种测试单元的电路图；
图14为本公开实施例提供的一种显示基板中的一种静电释放单元的电路图；
图15为图3的显示基板的A位置的局部放大结构设计布图；
图16为图4的显示基板的B位置的局部放大结构设计布图；
图17为图4的显示基板的C位置的局部放大结构设计布图；
图18为图4的显示基板的D位置的局部放大结构设计布图；
图19为本公开实施例提供的一种显示基板的周边区的一个位置的局部放大结构设计布图；
图20为本公开实施例提供的一种显示基板中的一种栅极移位寄存器的结构设计布图；
图21为本公开实施例提供的一种显示基板中的一种控制极移位寄存器的结构设计布图；
图22为本公开实施例提供的一种显示基板中的一种多路复用单元的结构设计布图
图23为本公开实施例提供的一种显示基板中的一种测试单元的 结构设计布图
图24为本公开实施例提供的一种显示基板中的一种静电释放单元的结构设计布图。
具体实施方式
为使本领域的技术人员更好地理解本公开实施例的技术方案，下面结合附图对本公开实施例提供的显示基板、显示装置进行更详细的描述。
在下文中将参考附图更充分地描述本公开实施例，但是所示的实施例可以以不同形式来体现，且不应当被解释为限于本公开阐述的实施例。反之，提供这些实施例的目的在于使本公开透彻和完整，并将使本领域技术人员充分理解本公开的范围。
本公开实施例可借助本公开的理想示意图而参考平面图和/或截面图进行描述。因此，可根据制造技术和/或容限来修改示例图示。
在不冲突的情况下，本公开各实施例及实施例中的各特征可相互组合。
本公开所使用的术语仅用于描述特定实施例，且不意欲限制本公开。如本公开所使用的术语“和/或”包括一个或多个相关列举条目的任何和所有组合。如本公开所使用的单数形式“一个”和“该”也意欲包括复数形式，除非上下文另外清楚指出。如本公开所使用的术语“包括”、“由……制成”，指定存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或添加一个或多个其它特征、整体、步骤、操作、元件、组件和/或其群组。
除非另外限定，否则本公开所用的所有术语(包括技术和科学术语)的含义与本领域普通技术人员通常理解的含义相同。还将理解，诸如那些在常用字典中限定的那些术语应当被解释为具有与其在相关技术以及本公开的背景下的含义一致的含义，且将不解释为具有理想化或过度形式上的含义，除非本公开明确如此限定。
本公开实施例不限于附图中所示的实施例，而是包括基于制造工艺而形成的配置的修改。因此，附图中例示的区具有示意性属性，并且图中所示区的形状例示了元件的区的具体形状，但并不是旨在限制性的。
本公开实施例中，在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本公开实施例中，“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
本公开实施例中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
本公开实施例中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
本公开实施例，“A基本为B”是指，在A整体的尺度上，其符合特征B，但在从明显比A整体更小的尺度上看，A可以不是完全符合特征B的。例如，“A基本为圆形”表示A可以是完美的圆形或椭圆形，也可以是A的形状整体上是圆形或椭圆形，但其部分细节结构 不是严格的圆形：例如，A的边界可有少部分为直线、折线等；再如，A的边界可有部分位置具有凸出、凹陷等；再如，A的边界可有少部分为近似于圆弧但不是严格的圆弧的弧形；再如，A的不同位置的边界可为直径不同的圆弧形等。
本公开实施例中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
本公开实施例中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
本公开实施例中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
本公开实施例中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开实施例中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开实施例中，“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
第一方面，参照图1至图24，本公开实施例提供一种显示基板。
在本公开实施例的部分附图中，基于空间的限制，为清楚的表明主要结构，故其中均有部分结构没有示出，且有部分同类型的结构合并表示为一个结构，故各附图中示出的结构的数量、具体位置、具体尺寸关系等都只是示意性的，而不是对本公开实施例的限定。
例如，对应一种电路的驱动线、引线、辅助引线中的每种均为“一组线”，而“一组线”实际可能实际有多条线，而部分附图中，可能用一条或两条线代表同组的多条线。
本公开实施例的显示基板是用于显示装置中的基板，例如是设有薄膜晶体管(TFT)阵列的阵列基板，且还可设有用于进行显示的发光器件(如有机发光二极管)。
本公开实施例的显示基板包括：
基底9，包括显示区91和围绕显示区91的周边区92；
多个子像素1，位于显示区91；
多条数据线12，至少位于显示区91且沿第一方向991延伸，多条数据线12与多个子像素1电连接；
多条栅极线13，至少位于显示区91且沿第二方向992延伸，多条栅极线13与多个子像素1电连接；第一方向991和第二方向992交叉；
多个焊盘8，位于周边区92；
多条数据引线73，位于周边区92，与多条数据线12、多个焊盘8电连接；多条数据引线73包括第一组数据引线738和第二组数据引线739；
栅极驱动电路A41，位于周边区92，且与多条栅极线13电连接；
多条栅极驱动线61，位于周边区92且至少部分围绕显示区91，多条栅极驱动线61与栅极驱动电路A41电连接；
多条栅极引线71，位于周边区92且沿第一方向991延伸，多条栅极引线71与多条栅极驱动线61、多个焊盘8电连接；多条栅极引 线71位于第一组数据引线738与第二组数据引线739之间。
参照图1、图7，本公开实施例的显示基板中的各种结构设于“基底9”上。
其中，基底9是用于承载显示基板上的其它结构的基础，其是由玻璃、硅(如单晶硅)、聚合物材料(如聚酰亚胺)等材料构成的基本为片状的结构，可为刚性，也可为柔性，厚度可在毫米量级。
以上基底9包括位于中部的显示区91，以及围绕显示区91的周边区92。
以上显示区91中设有多个用于进行显示的子像素1。
其中，每个子像素1是指可用于独立显示所需内容的最小的结构，即是显示装置中可独立的控制的最小的“点”。
其中，不同的子像素1可具有不同的颜色，从而通过不同子像素1的混光可实现彩色显示。当要实现彩色显示时，可以是多个排在一起的不同颜色的子像素1组成一个“像素(或像素单元)”，即这些子像素1发出的光混在一起成为视觉上的一个“点”；例如，可以是红色、绿色、蓝色三种颜色的三个子像素1组成一个像素。或者，也可不存在明确的像素(或像素单元)，而是通过邻近子像素1间的“公用”实现彩色显示。
参照图1，显示区91中，还设有沿第一方向991延伸的数据线12，以及沿第二方向992延伸的栅极线13，其中，第一方向991是与第二方向992交叉(即不相互平行)的，从而数据线12与栅极线13的每个交叉处可限定出一个子像素1，而通过栅极线13与数据线12的共同控制，可使二者交叉处的子像素1进行显示；另外，显示区91中还可设有沿第二方向992延伸的控制极线14，也起到控制子像素1的作用。
在一些实施例中，第一方向991垂直于第二方向992，即第一方向991可为列方向(各附图中为纵向，或列方向)，第二方向992可为与列方向垂直的行方向(各附图中为横向，或行方向)。
应当理解，第一方向991、第二方向992实际只是对应数据线12和栅极线13(或控制极线14)的两个相对方向，二者不一定是列方向、行方向，且与显示基板(或显示装置)的形状、所处位置、放置方式等没有必然的关系。
在一些实施例中，显示区91中的子像素1可排成阵列，即子像素1可排成多行、多列，其中每行子像素1连接一条栅极线13和一条控制极线14，每列子像素1连接一条数据线12。
应当理解，子像素1不一定排成阵列，每条数据线12、栅极线13、控制极线14也不一定连接同一列、同一行的子像素1。
示例性的，子像素1可包括像素电路，该像素电路可在相应的栅极线13、数据线12等的控制下发出所需亮度的光。例如，像素电路可为7T1C结构(即包括7个晶体管和1个电容)，参照图6，以上7T1C的像素电路可包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、存储电容Cst、有机发光二极管OLED、第一重置端Reset、第二重置端Reset’、初始化信号端Vinit、栅极线13端Gate、数据线12端Data、控制端EM、第一电源信号端VDD、第二电源信号端VSS等结构；其中，各晶体管可均为P型晶体管(如PMOS)。
也就是说，本公开实施例的显示基板的各子像素1中，可用有机发光二极管OLED作为发光器件，其具体是有机发光二极管显示基板，也是设有薄膜晶体管(TFT)阵列的阵列基板。
参照图7，在一些实施例中，每个子像素1中的第三晶体管T3为驱动晶体管，其中部分器件的具体结构和层叠关系可如下：
驱动晶体管(第三晶体管T3)包括：
位于基底9一侧的第一有源层111；
位于第一有源层111远离基底9一侧的栅绝缘层190；
位于栅绝缘层190远离基底9一侧的第一栅极112；
位于第一栅极112远离基底9一侧的第一绝缘层191；
位于第一绝缘层191远离基底9一侧的第二绝缘层192(层间绝缘层ILD)；
位于第二绝缘层192远离基底9一侧的，电连接第一有源层111的第一源极113和第一漏极114；
存储电容Cst包括：
第一极片121，与第一栅极112同层设置；
第二极片122，位于第一绝缘层191与第二绝缘层192之间。
当然，子像素1中还可包括其它的结构。
当然，子像素1和像素电路的具体结构并不限于以上方式。
其中，数据线12端Data可连接数据线12，栅极线13端Gate可连接栅极线13，控制极线14端EM可连接控制极线14，第一重置端Reset和第二重置端Reset’可同时连接上一行的栅极线13，第二重置端Reset’也可连接本行的栅极线13，其它各端(如初始化信号端Vinit、第一电源信号端VDD、第二电源信号端VSS)也可连接相应的信号源，这些信号源可以是“线”，也可以是连成一体的导电结构。
以上数据线12、栅极线13、控制极线14，以及用于为初始化信号端Vinit、第一电源信号端VDD、第二电源信号端VSS供电的信号源的信号，本质上是通过设于周边区92的、围绕或部分围绕显示区91的多种驱动线直接(如驱动线直接连接显示区91中的线或信号源)或间接(如驱动线通过某些单元连接显示区91中的线或信号源)提供。
各种驱动线则连接位于周边区92的、沿第一方向991延伸的“引线”；各“引线”再直接或间接(如通过辅助引线)连接对应的焊盘8，即驱动子像素1的信号本质上来自“焊盘8”。
其中，焊盘8(Pad或Pin)是指显示基板周边区92的、可获取其它信号并将信号最终引入到子像素1的结构。
具体的，焊盘8可用于与柔性线路板(FPC)或驱动芯片绑定(Bonding)连接，从而获取来自柔性线路板或驱动芯片的信号；或者，焊盘8也可用于与测试装置的测试探针接触，从而获得来自测试探针 的信号(或向测试探针反馈信号)。
其中，最终与数据线12电连接(通过位于周边区92的数据驱动线63)的数据引线73包括两组，即第一组数据引线738与第二组数据引线739，而其它多数引线(至少包括最终与栅极线13电连接的栅极引线71)则位于第一组数据引线738与第二组数据引线739“之间”。
即，本公开实施例中，数据引线73是相对其它测试引线75处于“外侧”(如沿第二方向992的外侧)的。
其中，相对其它引线，数据引线73的数量通常是最多的，故其要从沿第一方向991(纵向)延伸转变为沿围绕显示区91延伸(即数据驱动线63)所需占据的扇出线(Fanout)的区域也较大。
本公开实施例中，数据引线73设于其它引线的两侧(或者说比较靠边)，从而与周边区92的两侧更接近，便于实现扇出，可减小布线面积，压缩显示装置的边框宽度，实现窄边框设计。
例如，参照图5，当数据引线73沿第一方向991的长度相同时，则相当于扇出线(数据引线73与数据驱动线63之间的连接线)的起点“靠向侧边”，从而相对数据引线73设于中部的方式，可在第二方向992上节省尺寸d1，或者是在第一方向991上节约尺寸h1，降低周边区92的尺寸，实现窄边框设计。
在一些实施例中，显示区91基本为圆形；显示基板基本为圆形。
参照图1、图2，作为本公开实施例的一种方式，以上显示区91和显示基板可以基本都是圆形的，从而显示区91外的周边区92基本是“圆环形”的，且该显示基板对应的显示装置整体也是基本圆形的，例如圆形的“智能手表”。
当然，以上形状也不是对显示基板及其中各区的具体形式的限定，显示基板以及其中各区也可为其它的形状。
在一些实施例中，多条栅极驱动线61包括栅极启动信号线611、 第一栅极时钟信号线612、第二栅极时钟信号线613、栅极驱动测试线614、高电平信号线615、低电平信号线616。
参照图18，以上栅极驱动线61具体可包括栅极启动信号线611、第一栅极时钟信号线612、第二栅极时钟信号线613、栅极驱动测试线614、高电平信号线615、低电平信号线616。
其中，参照图1，栅极驱动电路A41可由多个栅极驱动单元41构成，而每个栅极驱动单元41向一条栅极线13提供栅极驱动信号；其中，各栅极驱动单元41可沿第二方向992(各附图中行方向)分别位于显示区91的两侧，从而分别为不同行的栅极线13提供栅极驱动信号，或者是从两侧同时为栅极线13提供栅极驱动信号(双侧驱动)。
具体的，每个栅极驱动单元41可为一个栅极移位寄存器(GOA)，而多个栅极移位寄存器级联，从而多个栅极移位寄存器可分别向多条栅极线13提供驱动信号。
栅极移位寄存器的具体形式是多样的。示例性的，栅极移位寄存器的电路结构和驱动时序可参照图8、图20、图9。其中，以下各信号的低电平具体可等于低电平信号VGL，而各信号的高电平具体可等于高电平信号VGH。
在输入阶段t1，第一栅极时钟信号CK为低电平，第二栅极时钟信号CB为高电平，栅极启动信号GSTV为低电平。由于第一栅极时钟信号CK为低电平，第二栅极晶体管K2导通，栅极启动信号GSTV经由第二栅极晶体管K2传输至第三栅极节点N3。由于第二栅极晶体管K2具有阈值损失，从而第三栅极节点N3的电平为GSTV-Vth2，即VGL-Vth2，其中，Vth2表示第二栅极晶体管K2的阈值电平。由于第六栅极晶体管K6的栅极接收低电平信号VGL，从而第六栅极晶体管K6处于开启状态，由此，电平VGL-Vth2经由第六栅极晶体管K6传输至第一栅极节点N1。例如，第六栅极晶体管K6的阈值电平表示为Vth6，同理，由于第六栅极晶体管K6具有阈值损失，第一栅极节点N1的电平为VGL-VthN1，其中，VthN1为Vth2和Vth6中较小的一个。第一栅极节点N1的电平可以控制第八栅极晶体管K8导通，第二栅极 时钟信号CB经由第八栅极晶体管K8被作为栅极输出信号GOUT，即在输入阶段t1，栅极输出信号GOUT为高电平的第二栅极时钟信号CB，即等于VGH。
在输入阶段t1，由于第一栅极时钟信号CK为低电平，第一栅极晶体管K1导通，低电平信号VGL经由第一栅极晶体管K1传输至第二栅极节点N2，由于第三栅极节点N3的电平为VGL-Vth2，第七栅极晶体管K7导通，低电平的第一栅极时钟信号CK经由第七栅极晶体管K7传输至第二栅极节点N2。例如，第七栅极晶体管K7的阈值电平表示为Vth7，第一栅极晶体管K1的阈值电平表示为Vth1，当Vth1<Vth7+Vth2时，则第二栅极节点N2的电平为VGL-Vth7-Vth2；而当Vth1>Vth7+Vth2时，则第二栅极节点N2的电平为VGL-Vth1。此时，第三栅极晶体管K3和第四栅极晶体管K4均导通。由于第二栅极时钟信号CB为高电平，第五栅极晶体管K5截止。
在输出阶段t2，第一栅极时钟信号CK为高电平，第二栅极时钟信号CB为低电平，栅极启动信号GSTV为高电平。第八栅极晶体管K8导通，第二栅极时钟信号CB经由第八栅极晶体管K8作为栅极输出信号GOUT。在输入阶段t1，第二栅极电容C2的连接第一栅极节点N1的一端的电平为VGL-VthN1，另一端的电平为高电平；而在输出阶段t2，第二栅极电容C2的连接输出端GOUT的一端的电平变为VGL，由于第二栅极电容C2的自举作用，第二栅极电容C2的连接第一栅极节点N1的一端的电平变为2VGL-VthN1-VGH，即第一栅极节点N1的电平变为2VGL-VthN1-VGH，此时，第六栅极晶体管K6截止，第八栅极晶体管K8可以更好地打开，栅极输出信号GOUT为低电平信号VGL。
在输出阶段t2，第一栅极时钟信号CK为高电平，从而第二栅极晶体管K2和第一栅极晶体管K1均截止。第三栅极节点N3的电平仍为VGL-VthN1，第七栅极晶体管K7导通，高电平的第一栅极时钟信号CK经由第七栅极晶体管K7传输至第二栅极节点N2，即第二栅极节点N2的电平为VGH，由此，第三栅极晶体管K3和第四栅极晶体 管K4均截止。由于第二栅极时钟信号CB为低电平，第五栅极晶体管K5导通。
在缓冲阶段t3，第一栅极时钟信号CK和第二栅极时钟信号CB均为高电平，栅极启动信号GSTV为高电平。第八栅极晶体管K8导通，第二栅极时钟信号CB经由第八栅极晶体管K8作为栅极输出信号GOUT，此时，栅极输出信号GOUT为高电平的第二栅极时钟信号CB，即VGH。由于第二栅极电容C2的自举作用，第一栅极节点N1的电平变为VGL-VthN1。
在缓冲阶段t3，第一栅极时钟信号CK为高电平，从而第二栅极晶体管K2和第一栅极晶体管K1均截止。第一栅极节点N1的电平变为VGL-VthN1，此时，第六栅极晶体管K6导通，第三栅极节点N3的电平也为VGL-VthN1，第七栅极晶体管K7导通，高电平的第一栅极时钟信号CK经由第七栅极晶体管K7传输至第二栅极节点N2，即第二栅极节点N2的电平为VGH，由此，第三栅极晶体管K3和第四栅极晶体管K4均截止。由于第二栅极时钟信号CB为高电平，第五栅极晶体管K5截止。
在稳定阶段t4的第一子阶段t41中，第一栅极时钟信号CK为低电平，第二栅极时钟信号CB为高电平，栅极启动信号GSTV为高电平。由于第一栅极时钟信号CK为低电平，第二栅极晶体管K2导通，栅极启动信号GSTV经由第二栅极晶体管K2传输至第三栅极节点N3，由于第二栅极晶体管K2传递高电平无阈值损失，第三栅极节点N3的电平为VGH，第七栅极晶体管K7截止。由于第六栅极晶体管K6处于开启状态，第一栅极节点N1的电平与第三栅极节点N3相同，也就是说，第一栅极节点N1的电平为VGH，第八栅极晶体管K8截止。由于第一栅极时钟信号CK为低电平，第一栅极晶体管K1导通，第二栅极节点N2的电平为VGL-Vth1，第三栅极晶体管K3和第四栅极晶体管K4均导通，高电平信号VGH经由第三栅极晶体管K3传输作为栅极输出信号GOUT，即栅极输出信号为高电平信号VGH。
在稳定阶段t4的第二子阶段t42中，第一栅极时钟信号为高电平， 第二栅极时钟信号为低电平，栅极启动信号GSTV为高电平。第一栅极节点N1和第三栅极节点N3的电平为VGH，第八栅极晶体管K8和第七栅极晶体管K7均截止。第一栅极时钟信号CK为高电平，从而第二栅极晶体管K2和第一栅极晶体管K1均截止，由于第一栅极电容C1的保持作用，第二栅极节点N2的电平仍为VGL-Vth1，第三栅极晶体管K3和第四栅极晶体管K4均导通，高电平信号VGH经由第三栅极晶体管K3作为栅极输出信号GOUT，即栅极输出信号为高电平信号VGH。
在第二子阶段t42中，由于第二栅极时钟信号CB为低电平，第五栅极晶体管K5导通，从而高电平信号VGH经由第四栅极晶体管K4和第五栅极晶体管K5被传输至第三栅极节点N3和第一栅极节点N1，以使第一栅极节点N1的电平和第三栅极节点N3的电平保持为高电平。
在稳定阶段t4的第三子阶段t43中，第一栅极时钟信号CK和第二栅极时钟信号CB均为高电平，栅极启动信号GSTV为高电平。第一栅极节点N1和第三栅极节点N3的电平为VGH，第八栅极晶体管K8和第七栅极晶体管K7截止。第一栅极时钟信号CK为高电平，从而第二栅极晶体管K2和第一栅极晶体管K1均截止，第二栅极节点N2的电平仍为VGL-Vth1，第三栅极晶体管K3和第四栅极晶体管K4均导通。高电平信号VGH经由第三栅极晶体管K3作为栅极输出信号GOUT，即栅极输出信号为高电平信号VGH。
其中，以上第一栅极时钟信号CK可通过以上第一栅极时钟信号线612提供，而第二栅极时钟信号CB可通过以上第二栅极时钟信号线613提供，高电平信号VGH、低电平信号VGL分别通过高电平信号线615、低电平信号线616提供。
而栅极启动信号GSTV通过上一级栅极移位寄存器的栅极输出信号GOUT提供，第一级栅极移位寄存器的栅极启动信号GSTV通过栅极启动信号线611提供，最后一级栅极移位寄存器产生的栅极输出信号GOUT还连接栅极驱动测试线614，以检测栅极驱动电路A41是否正常工作。
在一些实施例中，显示基板还包括：
多条控制极线14，至少位于显示区91且沿第二方向992延伸，多条控制极线14与多个子像素1电连接；
控制极驱动电路A42，位于周边区92，且与多条控制极线14电连接；
多条控制极驱动线62，位于周边区92且至少部分围绕显示区91，多条控制极驱动线62与控制极驱动电路A42电连接；
多条控制极引线72，位于周边区92且沿第一方向991延伸，多条控制极引线72与多条控制极驱动线62、多个焊盘8电连接；多条控制极引线72位于第一组数据引线738与第二组数据引线739之间。
参照图1，以上控制极线14的信号可通过控制极驱动电路A42提供，而控制极驱动电路A42由控制极驱动线62驱动，控制极驱动线62则连接沿第一方向991延伸的控制极引线72，该控制极引线72也是位于以上第一组数据引线738与第二组数据引线739之间的。
在一些实施例中，参照图18，多条控制极驱动线62包括控制极启动信号线621、第一控制极时钟信号线、第二控制极时钟信号线623、控制极驱动测试线624、高电平信号线615、低电平信号线616。
其中，参照图1，控制极驱动电路A42可由多个控制极驱动单元42构成，而每个控制极驱动单元42向一条控制极线14提供控制极驱动信号；其中，各控制极驱动单元42可沿第二方向992(各附图中行方向)分别位于显示区91的两侧，从而分别为不同行的控制极线14提供控制极驱动信号，或者是从两侧同时为控制极线14提供控制极驱动信号(双侧驱动)。
具体的，每个控制极驱动单元42可为一个控制极移位寄存器(EM GOA)，而多个控制极移位寄存器级联，从而多个控制极移位寄存器可分别向多条控制极线14提供驱动信号。
控制极移位寄存器的具体形式是多样的。示例性的，控制极移位 寄存器的电路结构和驱动时序可参照图10、图21、图11。其中，以下各信号的低电平具体可等于低电平信号VGL，而各信号的高电平具体可等于高电平信号VGH。
其中，在第一阶段P1，第一控制极时钟信号CK’为低电平，所以第一控制极晶体管M1和第三控制极晶体管M3被导通，导通的第一控制极晶体管M1将高电平的控制极启动信号ESTV传输至第一控制极节点N1’，从而使得第一控制极节点N1’的电平变为高电平，所以第二控制极晶体管M2、第八控制极晶体管M8以及第十控制极晶体管M10被截止。另外，导通的第三控制极晶体管M3将低电平的低电平信号VGL传输至第二控制极节点N2’，从而使得第二控制极节点N2’的电平变为低电平，所以第五控制极晶体管M5和第六控制极晶体管M6被导通。由于第二控制极时钟信号CB’为高电平，所以第七控制极晶体管M7被截止。另外，由于第三控制极电容C3’的存储作用，第四控制极节点N4的电平可以保持高电平，从而使得第九控制极晶体管M9被截止。在第一阶段P1中，由于第九控制极晶体管M9以及第十控制极晶体管M10均被截止，控制极输出信号EMOUT保持之前的低电平。
在第二阶段P2，第二控制极时钟信号CB’为低电平，所以第四控制极晶体管M4、第七控制极晶体管M7被导通。由于第一控制极时钟信号CK’为高电平，所以第一控制极晶体管M1和第三控制极晶体管M3被截止。由于第一控制极电容C1’的存储作用，所以第二控制极节点N2’可以继续保持上一阶段的低电平，所以第五控制极晶体管M5以及第六控制极晶体管M6被导通。高电平信号VGH通过导通的第五控制极晶体管M5以及第四控制极晶体管M4传输至第一控制极节点N1’，从而使得第一控制极节点N1’的电平继续保持上一阶段的高电平，所以第二控制极晶体管M2、第八控制极晶体管M8以及第十控制极晶体管M10被截止。另外，低电平的第二控制极时钟信号CB’通过导通的第六控制极晶体管M6以及第七控制极晶体管M7被传输至第四控制极节点N4’，从而使得第四控制极节点N4’的电平变为低电平，所以第九控制极晶体管M9被导通，导通的第九控制极晶体管 M9将高电平信号VGH输出，所以控制极输出信号EMOUT为高电平。
在第三阶段P3，第一控制极时钟信号CK’为低电平，所以第一控制极晶体管M1以及第三控制极晶体管M3被导通。第二控制极时钟信号CB’为高电平，所以第四控制极晶体管M4以及第七控制极晶体管M7被截止。由于第三控制极电容C3’的存储作用，所以第四控制极节点N4’的电平可以保持上一阶段的低电平，从而使得第九控制极晶体管M9保持导通状态，导通的第九控制极晶体管M9将高电平信号VGH输出，所以控制极输出信号EMOUT仍然为高电平。
在第四阶段P4，第一控制极时钟信号CK’为高电平，所以第一控制极晶体管M1以及第三控制极晶体管M3被截止。第二控制极时钟信号CB’为低电平，所以第四控制极晶体管M4以及第七控制极晶体管M7被导通。由于第二控制极电容C2’的存储作用，所以第一控制极节点N1’的电平保持上一阶段的高电平，从而使得第二控制极晶体管M2、第八控制极晶体管M8以及第十控制极晶体管M10被截止。由于第一控制极电容C1’的存储作用，第二控制极节点N2继续保持上一阶段的低电平，从而使得第五控制极晶体管M5以及第六控制极晶体管M6被导通。另外，低电平的第二控制极时钟信号CB’通过导通的第六控制极晶体管M6以及第七控制极晶体管M7被传输至第四控制极节点N4’，从而使得第四控制极节点N4’的电平变为低电平，所以第九控制极晶体管M9被导通，导通的第九控制极晶体管M9将高电平信号VGH输出，所以控制极输出信号EMOUT仍然为高电平。
在第五阶段P5，第一控制极时钟信号CK’为低电平，所以第一控制极晶体管M1以及第三控制极晶体管M3被导通。第二控制极时钟信号CB’为高电平，所以第四控制极晶体管M4以及第七控制极晶体管M7被截止。导通的第一控制极晶体管M1将低电平的控制极启动信号ESTV传输至第一控制极节点N1’，从而使得第一控制极节点N1’的电平变为低电平，所以第二控制极晶体管M2、第八控制极晶体管M8以及第十控制极晶体管M10被导通。导通的第二控制极晶体管M2将低电平的第一控制极时钟信号CK’传输至第二控制极节点N2’， 从而可以进一步拉低第二控制极节点N2’的电平，所以第二控制极节点N2’继续保持上一阶段的低电平，从而使得第五控制极晶体管M5以及第六控制极晶体管M6被导通。另外，导通的第八控制极晶体管M8将高电平信号VGH传输至第四控制极节点N4’，从而使得第四控制极节点N4的电平变为高电平，所以第九控制极晶体管M9被截止。导通的第十控制极晶体管M10将低电平信号VGL输出，所以控制极输出信号EMOUT变为低电平。
其中，以上第一控制极时钟信号CK’可通过以上第一控制极时钟信号线622提供，而第二控制极时钟信号CB’可通过以上第二控制极时钟信号线623提供,高电平信号VGH、低电平信号VGL分别通过高电平信号线615、低电平信号线616提供。
而控制极启动信号ESTV通过上一级控制极移位寄存器的控制极输出信号EOUT提供，第一级控制极移位寄存器的控制极启动信号ESTV通过控制极启动信号线621提供，最后一级控制极移位寄存器产生的控制极输出信号EOUT还连接控制极驱动测试线624，以检测控制极驱动电路A42是否正常工作。
其中，参照图9、图11，由于以上栅极驱动电路A41和控制极驱动电路A42中用的高电平信号VGH、低电平信号VGL是一样的，故参照图18，栅极驱动线61、控制极驱动线62中的高电平信号线615可以实际是同一条线，而栅极驱动线61、控制极驱动线62中的低电平信号线616也可以实际是同一条线。
在一些实施例中，栅极驱动电路A41与控制极驱动电路A42沿第二方向992位于显示区91的两个相对侧。
参照图1，由于栅极驱动电路A41、控制极驱动电路A42分别对应栅极线13、控制极线14，而栅极线13、控制极线14均沿第二方向992延伸，故从走线简便的角度考虑，栅极驱动电路A41(多个栅极驱动单元41)、控制极驱动电路A42(多个控制极驱动单元42)可沿第二方向992相对设置。
在一些实施例中，显示基板还包括：
多路复用电路A2，位于周边区92，且与多条数据线12电连接；
多条数据驱动线63，位于周边区92且至少部分围绕显示区91，多路复用电路A2与多条数据驱动线63与多条数据引线73电连接；
多条多路复用驱动线64，位于周边区92且至少部分围绕显示区91，多条多路复用驱动线64与多路复用电路电连接；
多条多路复用引线74，位于周边区92且沿第一方向991延伸，多条多路复用引线74与多条多路复用驱动线64、多个焊盘8电连接；多条多路复用引线74位于第一组数据引线738与第二组数据引线739之间。
参照图1，在一些实施例中，显示基板可包括多路复用电路A2，多路复用电路A2用于在多条多路复用驱动线64的控制下，使每条数据驱动线63可分时的与不同数据线12导通。由此，每条数据驱动线63(或者说每条数据引线73)可对应多条数据线12，从而减少数据驱动线63、数据引线73(以及相应焊盘8、芯片)的数量，简化产品结构，并易于实现显示装置的窄边框设计。
其中，参照图1、图2，以上多路复用驱动线64也需要通过沿第一方向991延伸的多路复用引线74连接焊盘8，而该多路复用引线74也是位于以上第一组数据引线738与第二组数据引线739之间的。
其中，多路复用电路A2可包括多个多路复用单元2(MUX)。
参照图12、图22，在一些实施例中，多个多路复用单元2包括m个(m至少为2)复用晶体管21；
在每个多路复用单元2的m个复用晶体管21中，每个复用晶体管21的栅极分别电连接多条多路复用驱动线64中的一条，每个复用晶体管21的第一极分别电连接多条数据线12中的一条，m个复用晶体管21的第二极均电连接多条数据驱动线63中的一条。
可见，在显示过程中，当向任意一条栅极线13提供导通信号的过程中，可向各多路复用驱动线64分时的提供导通信号，以使每个多路 复用单元2中的各复用晶体管21分时导通；并在任意复用晶体管21导通时，通过相应的数据驱动线63提供与该复用晶体管21电连接的数据线12所需的数据信号，以将数据信号写入相应的子像素1。
示例性的，参照图12、图22，m为3，即每个多路复用单元2可控制3条数据线12(一拖三)。
显然，根据以上方式，数据线12数量可等于“m*多路复用单元2的数量”；而多路复用驱动线64的数量不能少于m，例如参照图12、图22，当每两个多路复用单元2电连接一条数据驱动线63时，多路复用驱动线64数量的数量可为m(如为)。
其中，多路复用单元2的各结构具体所处层的分布方式可以是多样的。
例如，各复用晶体管21的有源层可与第一有源层111同层设置并间隔排布，且被栅绝缘层190覆盖；而各复用晶体管21的栅极可与第一栅极112同层设置，且同时该层中还设有用于使部分复用晶体管21的第一极与相应数据线12电连接的结构(或者说是数据线12的一部分)；与第一源极113和第一漏极114同层，则可设有复用晶体管21的第一极和第二极，其中同一个多路复用单元2中的各复用晶体管21的第二极一端连为一体；而通过中第二绝缘层192中的过孔，即可实现相应结构的电连接。
在一些实施例中，多条栅极驱动线61、多条多路复用驱动线64、多条数据驱动线63位于栅极驱动电路A41、多路复用电路A2远离显示区91一侧。
在一些实施例中，多条多路复用驱动线64位于多条栅极驱动线61远离显示区91的一侧；
多条数据驱动线63位于多条多路复用驱动线64远离显示区91的一侧。
参照图19，以上栅极驱动线61、多路复用驱动线64、数据驱动 线63可以是设于栅极驱动电路A41(还可有控制极驱动电路A42)、多路复用电路A2“之外”的，以便这些电路更靠近显示区91而为其显示区91中的数据线12、栅极线13供电。
进一步的，在以上的各驱动线中，栅极驱动线61(还可有控制极驱动线62)可以是“最靠内”的，因为对移位寄存器(栅极移位寄存器、控制极移位寄存器)的驱动是相对比较重要的，故对应的线最好尽量接近移位寄存器；而数据驱动线63的数量是最多的，占据的面积较大，故可在最外侧。
其中，各种驱动电路中单元的具体位置可根据需要设置。
例如，参照图19，在周边区92的左下半区，栅极驱动电路A41的各栅极驱动单元41可与多路复用电路A2的各多路复用单元2沿周边区92的周向“混排”。
而在周边区92的右下半区，控制极驱动电路A42的各控制极驱动单元42可与多路复用电路A2的各多路复用单元2沿周边区92的周向“混排”。
而在周边区92的左上半区，栅极驱动电路A41的各栅极驱动单元41可与后续描述的测试电路A3的各测试单元3沿周边区92的周向“混排”。
而在周边区92的右上半区，控制极驱动电路A42的各栅极驱动单元41可与后续描述的测试电路A3的各测试单元3沿周边区92的周向“混排”。
而后续描述的静电释放电路A5的静电释放单元5数量较少，故可仅设于一些其它结构的空隙位置。
其中，其它各种驱动线与的具体位置可根据需要设置。
例如，参照图18，后续描述的第一电源驱动线68、初始化驱动线67可位于栅极驱动单元41、多路复用单元2等单元的“内侧”(第一电源驱动线68可最靠内，初始化驱动线67在外)。
例如，后续描述的第二电源驱动线69则位于数据驱动线63的“外 侧”，当然也位于栅极驱动单元41、多路复用单元2等单元的“外侧”。
例如，参照图18，后续描述的测试驱动线65则可与以上栅极驱动线61(还包括控制极驱动线62)、多路复用驱动线64排列在不同栅极驱动线61(或控制极驱动线62)之间，其中具体的排列顺序是多样的(同类驱动线不一定连续排在一起)。
在一些实施例中，显示基板还包括：
测试电路A3，位于周边区92，且与多条数据线12电连接；
多条测试驱动线65，位于周边区92且至少部分围绕显示区91，多条测试驱动线65与测试电路A3电连接；
多条测试引线75，位于周边区92且沿第一方向991延伸，多条测试引线75与多条测试驱动线65、多个焊盘8电连接；多条测试引线75位于第一组数据引线738与第二组数据引线739之间。
参照图1，显示基板中还有测试电路A3，测试电路A3也与各数据线12相连，从而可在多条测试驱动线65的控制下，对各子像素1进行测试，例如在显示基板出厂前进行点灯测试。
其中，参照图1、图2，测试驱动线65也需要通过沿第一方向991延伸的测试引线75连接相应焊盘8，而测试引线75也是位于第一组数据引线738与第二组数据引线739之间的。
在一些实施例中，多条测试驱动线65包括测试数据信号线651、测试控制信号线652。
其中，测试电路A3可包括多个测试单元3(CT)。
参照图13、图23，每个测试单元3与至少一条测试数据信号线651、至少一条测试控制信号线652、多条数据线12中的至少一条电连接，并被配置为根据至少一条测试控制信号线652提供的信号将至少一条测试数据信号线651提供的信号提供给至少一条数据线12。
参照图13，作为本公开实施例的一种方式，至少一条测试数据信号线651的总数量为n个(至少为2个，例如为3个)，至少一条测 试控制信号线652的总数量为一条，n为大于或等于2的整数；
多个测试单元3中的至少一个包括n个测试晶体管31；
同一个测试单元3的n个测试晶体管31中，n个测试晶体管31的栅极311电连接一条测试控制信号线652，每个测试晶体管31的第一极313分别电连接多条数据线12中的一条，每个测试晶体管31的第二极314分别电连接n条测试数据信号线651中的一条。
作为本公开实施例的一种形式，测试数据信号线651的数量为n个，而测试控制信号线652只有一条；而每个测试单元3也包括n个测试晶体管31，该n个测试晶体管31的栅极311均电连接该测试控制信号线652，第一极313(如漏极)则分别电连接不同的数据线12；n个测试晶体管31的第二极314(如源极)则分别电连接n个测试数据信号线651(即不同测试晶体管31的第二极电连接不同的测试数据信号线651)。
可见，通过测试控制信号线652可控制各测试单元3中的测试晶体管31是否导通，可控制各测试数据信号线651的信号写入不同的数据线12，也就是控制“是否进行测试”；当要进行测试时，可向测试控制信号线652提供导通信号，并向n个测试数据信号线651分别提供所需的信号，以使各数据线12获得所需的信号实现检测。
由此，在一些实施例中，数据线12数量可等于n*测试单元3的数量。
在一些实施例中，n为3。
在一些实施例中，每条数据线12电连接的子像素1颜色相同，例如是同一列子像素1颜色相同，例如是红色、绿色、蓝色子像素的列沿第二方向992排列。在图13中，红色子像素、绿色子像素、蓝色子像素分别用R、G、B表示。
由此，进行测试时，可向同一种颜色的子像素1对应的数据线12提供相同的信号，以使这些子像素1进行相同的显示(如点亮或不亮)，以便通过显示画面的颜色确定是否有发生不良的子像素1，以及定位发生不良的子像素1。
当然，子像素1颜色的排布以及测试单元3的具体形式并不限于此。
在一些实施例中，显示基板还包括：
多路复用电路A2，位于周边区92，且与多条数据线12电连接；
测试电路A3与多路复用电路A2沿第一方向991位于显示区91的两个相对侧；
多个焊盘8位于多路复用电路A2远离显示区91的一侧。
参照图1，由于测试电路A3、多路复用电路A2都要连接数据线12，而数据线12是沿第一方向991延伸的，故从走线简便的角度考虑，测试电路A3(多个测试单元3)、多路复用电路A2(多个多路复用单元2)可沿第一方向991相对设置；且其中由于多路复用电路A2所需的数据驱动线63数量最多，故焊盘8可设于多路复用电路A2所在侧，以便数据驱动线63能“就近”连接多路复用电路A2，而不用绕过半圈再连接。
在一些实施例中，显示基板还包括：
静电释放电路A5，位于周边区92；
静电释放驱动线66，位于周边区92且至少部分围绕显示区91，静电释放驱动线66与静电释放电路A5电连接；
静电释放引线，位于周边区92且沿第一方向991延伸，静电释放引线与静电释放驱动线66、焊盘8电连接；静电释放引线位于第一组数据引线738与第二组数据引线739之间。
参照图1，在一些实施例中，显示基板还包括静电释放电路A5，用于释放其它线(如栅极驱动线61、控制极驱动线62、多路复用驱动线64、测试驱动线65等)中积累的静电，以避免线中静电积累过量而造成造成静电击穿等不良；而静电释放电路A5可在静电释放驱动线66的控制下工作，静电释放驱动线66则连接静电释放引线，而静电释放引线也是位于以上第一组数据引线738与第二组数据引线739之 间的。
具体的，静电释放电路A5可包括静电释放单元5(ESD)。每个静电释放单元5用于将其需要保护的线(如栅极驱动线61、控制极驱动线62、多路复用驱动线64、测试驱动线65等)中的静电释放到静电释放驱动线66上。
参照图14、图24，在一些实施例中，静电释放驱动线66可包括静电高电平线661、静电低电平线662；每个静电释放单元5包括第一释放晶体管51和第二释放晶体管52：第一释放晶体管51的栅极和第一极连接静电高电平线661，第二极连接该静电释放单元5需要保护的线(图14中上方纵向的线)；第二释放晶体管52的栅极和第一极连接该静电释放单元5需要保护的线，第二极连接静电低电平线662。
其中，以上静电高电平线661和静电低电平线662中分别持续加载高电平信号VGH和低电平信号VGL。
参照图14，以上静电释放单元5包括第一释放晶体管51和第二释放晶体管52，其中，每个释放晶体管的一极都和自身的栅极连接，从而形成一个等效的“二极管”。由此，当静电释放单元5需要保护的线中因积累正电荷出现瞬时高压(如100V)时，第一释放晶体管51的“二极管”导通，释放信号线中的正电荷；而当信号线中因积累负电荷出现瞬时低压(如-100V)时，第二释放晶体管52的“二极管”导通，释放信号线中的负电荷。
在一些实施例中，显示基板还包括：
初始化驱动线67，位于周边区92且至少部分围绕显示区91，初始化驱动线67与多个子像素1电连接；
初始化引线77，位于周边区92且沿第一方向991延伸，初始化引线77与初始化驱动线67、焊盘8电连接；初始化引线77位于第一组数据引线738与第二组数据引线739之间。
参照图1、图2、图17、图18，如前，为了给显示区91的各子像 素1的初始化信号端Vinit提供初始化信号，故周边区92中还可设有初始化驱动线67，而初始化驱动线67连接初始化引线77，该初始化引线77也是位于以上第一组数据引线738与第二组数据引线739之间的。
在一些实施例中，显示基板还包括：
第一电源驱动线68，位于周边区92且至少部分围绕显示区91，第一电源驱动线68与多个子像素1电连接；
第一电源引线78，位于周边区92且沿第一方向991延伸，第一电源引线78与第一电源驱动线68、焊盘8电连接；第一电源引线78位于第一组数据引线738与第二组数据引线739之间；
第二电源驱动线69，位于周边区92且至少部分围绕显示区91，第二电源驱动线69与多个子像素1电连接；
第二电源引线79，位于周边区92且沿第一方向991延伸，第二电源引线79与第二电源驱动线69、焊盘8电连接；第二电源引线79位于第一组数据引线738背离第二组数据引线739一侧，或位于第二组数据引线739背离第一组数据引线738一侧。
参照图1、图2、图17、如前，为了给显示区91的各子像素1的第一电源信号端VDD、第二电源信号端VSS提供第一电源信号(对应阳极)、第二电源信号(对应阴极)，故周边区92中还可设有第一电源驱动线68、第二电源驱动线69，而第一电源驱动线68、第二电源驱动线69分别通过沿第一方向991延伸的第一电源引线78、第二电源引线79连接焊盘8。
其中，第一电源引线78也是位于以上第一组数据引线738与第二组数据引线739之间的；而第二电源引线79则有所不同，位于以上第一组数据引线738与第二组数据引线739“之外”。
其中，在符合以上位置要求的情况下，各种引线的具体位置关系可以是多样的。
例如，可参照图17、图18，在第一组数据引线738与第二组数据 引线739之间的其它引线中，第一电源引线78在最中间，初始化引线77在其两侧，再往外的两侧同时为测试引线75、多路复用引线74，而再往外的两侧则分别是栅极引线71、控制极引线72(图中以栅极引线71在左、控制极引线72再右为例)。
其中，参照图2、图17、图18，测试驱动线65、多路复用驱动线64、高电平信号线615、低电平信号线616等是可以形成封闭环形的，故与它们中的每者对应的引线也可有两条，同时从两侧连接；而栅极驱动线61、控制极驱动线62中的每者则只对应周边区92的“半圈”，故与它们对应的其它引线(除去高电平信号线615、低电平信号线616对应的引线)可分别单独的从一侧进入的。
在一些实施例中，多个焊盘8位于接入区921，且沿第二方向992排列；接入区921沿第一方向991位于显示区91一侧；
多条栅极引线71、多条数据引线73位于引出区922；引出区922沿第一方向991位于接入区921与显示区91之间；
沿第二方向992，多条栅极引线71位于第一组数据引线738与第二组数据引线739之间。
参照图2，以上多个焊盘8可沿第二方向992排成一排，且沿第一方向991位于显示区91一侧的接入区921中；而接入区921与显示区91之间，则是设置以上各引线用的引出区922。
由此，参照图2，引线沿第一方向991在引出区922中延伸，而不同的引线应当是沿第二方向992排列的，即其它多数引线(除第二电源引线79)应当是在第二方向992上位于第一组数据引线738与第二组数据引线739之间，或者说第一组数据引线738与第二组数据引线739在第二方向992分别位于其它多数引线的两侧。
在一些实施例中，沿第二方向992，与多条栅极引线71电连接的多个焊盘8，位于与第一组数据引线738电连接的多个焊盘8以及与第二组数据引线739电连接的多个焊盘8之间。
参照图3、图15，作为本公开实施例的一种形式，与数据引线73对应的焊盘8也应分为两组，且分别位于其它多数引线(除第一电源引线78、第二电源引线79)对应的焊盘8外侧。
由此，多数焊盘8都可直接与其对应的引线连接。
在一些实施例中，显示基板还包括：
多条控制极线14，至少位于显示区91且沿第二方向992延伸，多条控制极线14与多个子像素1电连接；
控制极驱动电路A42，位于周边区92，且与多条控制极线14电连接；
多条控制极驱动线62，位于周边区92且至少部分围绕显示区91，多条控制极驱动线62与控制极驱动电路A42电连接；
多条控制极引线72，位于周边区92且沿第一方向991延伸，多条控制极引线72与多条控制极驱动线62、多个焊盘8电连接；多条控制极引线72位于第一组数据引线738与第二组数据引线739之间；
沿第二方向992，与多条数据引线73电连接的多个焊盘8，位于与多条栅极引线71电连接的多个焊盘8以及与多条控制极引线72电连接的多个焊盘8之间；
至少部分数据引线73通过多条数据辅助引线731与多个焊盘8电连接，多条栅极引线71通过多条栅极辅助引线711与多个焊盘8电连接，多条控制极引线72通过多条控制极辅助引线721与多个焊盘8电连接。
参照图4、图16、图17、图18，作为本公开实施例的另一种形式，也可以是栅极引线71、控制极引线72(还可有多路复用引线74、测试引线75、初始化引线77、第一电源引线78)仍然是在第二方向992上位于第一组数据引线738与第二组数据引线739之间；但各数据引线73对应的焊盘8，却在第二方向992上位于在栅极引线71、控制极引线72(还可有多路复用引线74、测试引线75、初始化引线77、第一电源引线78)对应的焊盘8中间。
由此，数据引线73需要通过数据辅助引线731连接焊盘8，即，数据辅助引线731至少部分沿第二方向992延伸，从而在第二方向992上，将来自焊盘8的信号从中间引到两侧而进入数据引线73。
类似的，栅极引线71、控制极引线72分别要通过栅极辅助引线711、控制极辅助引线721与相应的焊盘8连接(而多路复用引线74、测试引线75、初始化引线77、第一电源引线78，也要分别通过多路复用辅助引线741、测试辅助引线751、初始化辅助引线771、第一电源辅助引线781与相应的焊盘8连接)。
在一些实施例中，显示基板还包括：
第一电源驱动线68，位于周边区92且至少部分围绕显示区91，第一电源驱动线68与多个子像素1电连接；
第一电源引线78，位于周边区92且沿第一方向991延伸，第一电源引线78与第一电源驱动线68、焊盘8电连接；第一电源引线78位于第一组数据引线738与第二组数据引线739之间；
第二电源驱动线69，位于周边区92且至少部分围绕显示区91，第二电源驱动线69与多个子像素1电连接；
第二电源引线79，第二电源引线79位于第一组数据引线738背离第二组数据引线739一侧，或位于第二组数据引线739背离第一组数据引线738一侧；
沿第二方向992，与第一电源引线78电连接的焊盘8位于与第一组数据引线738电连接的焊盘8背离于与第二组数据引线739电连接的焊盘8一侧，或位于与第二组数据引线739电连接的焊盘8背离于与第一组数据引线738电连接的焊盘8一侧；
沿第二方向992，与第二电源引线79电连接的焊盘8位于与第一组数据引线738电连接的焊盘8背离于与第二组数据引线739电连接的焊盘8一侧，或位于与第二组数据引线739电连接的焊盘8背离于与第一组数据引线738电连接的焊盘8一侧；
第一电源引线78通过第一电源辅助引线781与焊盘8电连接。
参照图2、图4、图5、图16，在第二方向992上，第一电源引线78和第二电源引线79对应的焊盘8，通常是位于其它焊盘8两侧的，或者说其它焊盘8位于与第一电源引线78连接的两个焊盘8之间，也位于与第二电源引线79连接的两个焊盘8之间。
如前，由于第一电源引线78位于第一组数据引线738与第二组数据引线739之间，故第一电源引线78需要通过至少部分沿第二方向992延伸的第一电源辅助引线781连接对应的焊盘8。
而由于第二电源引线79位于第一组数据引线738与第二组数据引线739之外，故其可直接连接对应的焊盘8。
第二方面，本公开实施例提供一种显示装置，其包括：
上述的任意一种显示基板。
可将以上显示基板与其它器件(例如对盒盖板、柔性线路板、驱动芯片、电源组件等)组合形成具有显示功能的显示装置。
在一些实施例中，显示装置为佩戴式显示装置。
具体的，以上显示装置特别适用于作为可佩戴在人体上的佩戴式显示装置，例如显示装置可为佩戴在人的手腕上的智能手表等。
当然，对佩戴式显示装置，其中还可包括表带等用于戴在人体上的器件。
当然，以上显示装置不限于佩戴式显示装置，其也可为电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开已经公开了示例实施例，并且虽然采用了具体术语，但它们仅用于并仅应当被解释为一般说明性含义，并且不用于限制的目的。在一些实例中，对本领域技术人员显而易见的是，除非另外明确指出，否则可单独使用与特定实施例相结合描述的特征、特性和/或元素，或可与其它实施例相结合描述的特征、特性和/或元件组合使用。因此， 本领域技术人员将理解，在不脱离由所附的权利要求阐明的本公开的范围的情况下，可进行各种形式和细节上的改变。

Claims (20)

  1. 一种显示基板，其中，包括：
    基底，包括显示区和围绕所述显示区的周边区；
    多个子像素，位于所述显示区；
    多条数据线，至少位于所述显示区且沿第一方向延伸，所述多条数据线与所述多个子像素电连接；
    多条栅极线，至少位于所述显示区且沿第二方向延伸，所述多条栅极线与所述多个子像素电连接；所述第一方向和所述第二方向交叉；
    多个焊盘，位于所述周边区；
    多条数据引线，位于所述周边区，与所述多条数据线、所述多个焊盘电连接；所述多条数据引线包括第一组数据引线和第二组数据引线；
    栅极驱动电路，位于所述周边区，且与所述多条栅极线电连接；
    多条栅极驱动线，位于所述周边区且至少部分围绕所述显示区，所述多条栅极驱动线与所述栅极驱动电路电连接；
    多条栅极引线，位于所述周边区且沿所述第一方向延伸，所述多条栅极引线与所述多条栅极驱动线、所述多个焊盘电连接；所述多条栅极引线位于所述第一组数据引线与所述第二组数据引线之间。
  2. 根据权利要求1所述的显示基板，其中，
    所述多条栅极驱动线包括栅极启动信号线、第一栅极时钟信号线、第二栅极时钟信号线、栅极驱动测试线、高电平信号线、低电平信号线。
  3. 根据权利要求1所述的显示基板，其中，还包括：
    多条控制极线，至少位于所述显示区且沿第二方向延伸，所述多 条控制极线与所述多个子像素电连接；
    控制极驱动电路，位于所述周边区，且与所述多条控制极线电连接；
    多条控制极驱动线，位于所述周边区且至少部分围绕所述显示区，所述多条控制极驱动线与所述控制极驱动电路电连接；
    多条控制极引线，位于所述周边区且沿所述第一方向延伸，所述多条控制极引线与所述多条控制极驱动线、所述多个焊盘电连接；所述多条控制极引线位于所述第一组数据引线与所述第二组数据引线之间。
  4. 根据权利要求3所述的显示基板，其中，
    所述多条控制极驱动线包括控制极启动信号线、第一控制极时钟信号线、第二控制极时钟信号线、控制极驱动测试线、高电平信号线、低电平信号线。
  5. 根据权利要求3所述的显示基板，其中，
    所述栅极驱动电路与所述控制极驱动电路沿所述第二方向位于所述显示区的两个相对侧。
  6. 根据权利要求1所述的显示基板，其中，还包括：
    多路复用电路，位于所述周边区，且与所述多条数据线电连接；
    多条数据驱动线，位于所述周边区且至少部分围绕所述显示区，所述多路复用电路与所述多条数据驱动线与所述多条数据引线电连接；
    多条多路复用驱动线，位于所述周边区且至少部分围绕所述显示区，所述多条多路复用驱动线与所述多路复用电路电连接；
    多条多路复用引线，位于所述周边区且沿所述第一方向延伸，所述多条多路复用引线与所述多条多路复用驱动线、所述多个焊盘电连 接；
    所述多条多路复用引线位于所述第一组数据引线与所述第二组数据引线之间。
  7. 根据权利要求6所述的显示基板，其中，
    所述多条栅极驱动线、所述多条多路复用驱动线、所述多条数据驱动线位于所述栅极驱动电路、所述多路复用电路远离所述显示区一侧。
  8. 根据权利要求7所述的显示基板，其中，
    所述多条多路复用驱动线位于所述多条栅极驱动线远离所述显示区的一侧；
    所述多条数据驱动线位于所述多条多路复用驱动线远离所述显示区的一侧。
  9. 根据权利要求1所述的显示基板，其中，还包括：
    测试电路，位于所述周边区，且与所述多条数据线电连接；
    多条测试驱动线，位于所述周边区且至少部分围绕所述显示区，所述多条测试驱动线与所述测试电路电连接；
    多条测试引线，位于所述周边区且沿所述第一方向延伸，所述多条测试引线与所述多条测试驱动线、所述多个焊盘电连接；所述多条测试引线位于所述第一组数据引线与所述第二组数据引线之间。
  10. 根据权利要求9所述的显示基板，其中，
    所述多条测试驱动线包括测试数据信号线、测试控制信号线。
  11. 根据权利要求9所述的显示基板，其中，还包括：
    多路复用电路，位于所述周边区，且与所述多条数据线电连接；
    所述测试电路与所述多路复用电路沿所述第一方向位于所述显示区的两个相对侧；
    所述多个焊盘位于所述多路复用电路远离所述显示区的一侧。
  12. 根据权利要求1所述的显示基板，其中，还包括：
    静电释放电路，位于所述周边区；
    静电释放驱动线，位于所述周边区且至少部分围绕所述显示区，所述静电释放驱动线与所述静电释放电路电连接；
    静电释放引线，位于所述周边区且沿所述第一方向延伸，所述静电释放引线与所述静电释放驱动线、所述焊盘电连接；所述静电释放引线位于所述第一组数据引线与所述第二组数据引线之间。
  13. 根据权利要求1所述的显示基板，其中，还包括：
    初始化驱动线，位于所述周边区且至少部分围绕所述显示区，所述初始化驱动线与所述多个子像素电连接；
    初始化引线，位于所述周边区且沿所述第一方向延伸，所述初始化引线与所述初始化驱动线、所述焊盘电连接；所述初始化引线位于所述第一组数据引线与所述第二组数据引线之间。
  14. 根据权利要求1所述的显示基板，其中，还包括：
    第一电源驱动线，位于所述周边区且至少部分围绕所述显示区，所述第一电源驱动线与所述多个子像素电连接；
    第一电源引线，位于所述周边区且沿所述第一方向延伸，所述第一电源引线与所述第一电源驱动线、所述焊盘电连接；所述第一电源引线位于所述第一组数据引线与所述第二组数据引线之间；
    第二电源驱动线，位于所述周边区且至少部分围绕所述显示区， 所述第二电源驱动线与所述多个子像素电连接；
    第二电源引线，位于所述周边区且沿所述第一方向延伸，所述第二电源引线与所述第二电源驱动线、所述焊盘电连接；所述第二电源引线位于所述第一组数据引线背离所述第二组数据引线一侧，或位于所述第二组数据引线背离所述第一组数据引线一侧。
  15. 根据权利要求1所述的显示基板，其中，所述周边区包括接入区和引出区，所述接入区沿所述第一方向位于所述显示区一侧，所述引出区沿所述第一方向位于所述接入区与所述显示区之间；所述多个焊盘位于接入区，且沿所述第二方向排列；所述多条栅极引线、所述多条数据引线位于引出区；所述沿所述第二方向，所述多条栅极引线位于所述第一组数据引线与所述第二组数据引线之间。
  16. 根据权利要求15所述的显示基板，其中，
    沿所述第二方向，与所述多条栅极引线电连接的多个所述焊盘，位于与所述第一组数据引线电连接的多个所述焊盘以及与所述第二组数据引线电连接的多个所述焊盘之间。
  17. 根据权利要求15所述的显示基板，其中，还包括：
    多条控制极线，至少位于所述显示区且沿第二方向延伸，所述多条控制极线与所述多个子像素电连接；
    控制极驱动电路，位于所述周边区，且与所述多条控制极线电连接；
    多条控制极驱动线，位于所述周边区且至少部分围绕所述显示区，所述多条控制极驱动线与所述控制极驱动电路电连接；
    多条控制极引线，位于所述周边区且沿所述第一方向延伸，所述多条控制极引线与所述多条控制极驱动线、所述多个焊盘电连接；所述多条控制极引线位于所述第一组数据引线与所述第二组数据引线之 间；
    沿所述第二方向，与所述多条数据引线电连接的多个所述焊盘，位于与所述多条栅极引线电连接的多个所述焊盘以及与所述多条控制极引线电连接的多个所述焊盘之间。
  18. 根据权利要求15所述的显示基板，其中，还包括：
    第一电源驱动线，位于所述周边区且至少部分围绕所述显示区，所述第一电源驱动线与所述多个子像素电连接；
    第一电源引线，位于所述周边区且沿所述第一方向延伸，所述第一电源引线与所述第一电源驱动线、所述焊盘电连接；所述第一电源引线位于所述第一组数据引线与所述第二组数据引线之间；
    第二电源驱动线，位于所述周边区且至少部分围绕所述显示区，所述第二电源驱动线与所述多个子像素电连接；
    第二电源引线，位于所述周边区且沿所述第一方向延伸，所述第二电源引线与所述第二电源驱动线、所述焊盘电连接；所述第二电源引线位于所述第一组数据引线背离所述第二组数据引线一侧，或位于所述第二组数据引线背离所述第一组数据引线一侧；
    沿所述第二方向，与所述第一电源引线电连接的所述焊盘位于与所述第一组数据引线电连接的所述焊盘背离于与所述第二组数据引线电连接的所述焊盘一侧，或位于与所述第二组数据引线电连接的所述焊盘背离于与所述第一组数据引线电连接的所述焊盘一侧；
    沿所述第二方向，与所述第二电源引线电连接的所述焊盘位于与所述第一组数据引线电连接的所述焊盘背离于与所述第二组数据引线电连接的所述焊盘一侧，或位于与所述第二组数据引线电连接的所述焊盘背离于与所述第一组数据引线电连接的所述焊盘一侧。
  19. 根据权利要求1至18中任意一项所述的显示基板，其中，
    所述显示区基本为圆形；
    所述显示基板基本为圆形。
  20. 一种显示装置，其包括：
    权利要求1至19中任意一项所述的显示基板。
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