WO2024046054A1 - 显示基板、显示面板及显示装置 - Google Patents

显示基板、显示面板及显示装置 Download PDF

Info

Publication number
WO2024046054A1
WO2024046054A1 PCT/CN2023/111733 CN2023111733W WO2024046054A1 WO 2024046054 A1 WO2024046054 A1 WO 2024046054A1 CN 2023111733 W CN2023111733 W CN 2023111733W WO 2024046054 A1 WO2024046054 A1 WO 2024046054A1
Authority
WO
WIPO (PCT)
Prior art keywords
area
display
electrostatic discharge
sub
power line
Prior art date
Application number
PCT/CN2023/111733
Other languages
English (en)
French (fr)
Inventor
卢彦伟
闫卓然
石佺
程羽雕
嵇凤丽
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2024046054A1 publication Critical patent/WO2024046054A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G09F9/335—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes being organic light emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
    • H05K9/0067—Devices for protecting against damage from electrostatic discharge

Definitions

  • This article relates to but is not limited to the field of display technology, and specifically refers to a display substrate, a display panel and a display device.
  • OLED Organic light-emitting diodes
  • QLED Quantum-dot Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • At least one embodiment of the present disclosure provides a display substrate, a display panel and a display device.
  • a display substrate including: a display area and a frame area located around the display area.
  • the display substrate includes a substrate, a plurality of data lines located in the display area, a plurality of multiplexing circuits located in the frame area, a plurality of multiplexed data lines, a plurality of first electrostatic discharge circuits, a plurality of second electrostatic discharge circuits, and multiple first signal lines.
  • a plurality of multiplexing circuits are arranged sequentially along the edge of the display area.
  • a plurality of multiplexing circuits are electrically connected to a plurality of multiplexed data lines and a plurality of data lines.
  • a plurality of first electrostatic discharge circuits are electrically connected to a plurality of multiplexed data lines, and a plurality of second electrostatic discharge circuits are electrically connected to a plurality of first signal lines.
  • a plurality of first electrostatic discharge circuits and a plurality of second electrostatic discharge circuits are located on a side of the multiplexing circuits away from the display area, and a plurality of second electrostatic discharge circuits are interspersed and arranged among the plurality of first electrostatic discharge circuits. .
  • At least one of the plurality of second electrostatic discharge circuits is located on a side of the plurality of first electrostatic discharge circuits away from the display area.
  • the frame area includes: a first frame area located on one side of the display area along the second direction; the multiplexing circuits are located in the first frame area and along the second direction.
  • the first directions are arranged side by side, and the first direction intersects the second direction.
  • the multiplexing circuit is electrically connected to multiple data lines of the display area through multiple data fan-out lines, and the multiple data fan-out lines are of the same layer structure.
  • the display substrate has a first center line parallel to the second direction; the plurality of second electrostatic discharge circuits are located in the first frame area close to the The area of the first center line and the edge area in the first frame area away from the first center line.
  • the frame area further includes: a second frame area located on a side of the display area away from the first frame area along the second direction.
  • the display substrate further includes: a plurality of test circuits located in the second frame area, and the plurality of test circuits are arranged side by side along the first direction.
  • the frame area further includes: located in the display area along the first direction.
  • the third frame area and the fourth frame area on opposite sides, the first corner area connecting the first frame area and the third frame area, the third frame area connecting the third frame area and the second frame area. two corner areas, a third corner area connecting the second frame area and the fourth frame area, and a fourth corner area connecting the fourth frame area and the first frame area.
  • the display substrate further includes: a gate drive circuit located in the third frame area, the fourth frame area, the first corner area, the second corner area, and the third corner area. area and the fourth corner area.
  • the multiplexing circuit near the first corner area and the fourth corner area is electrically connected to the plurality of data lines of the display area through arc-shaped data fan-out lines.
  • a test circuit close to the second corner area and the third corner area is electrically connected to a plurality of data lines of the display area through arc-shaped data connection lines.
  • the display substrate further includes: a first power line located in the frame area, and the first power line at least includes: a first sub-power line located in the first frame area, The second sub-power line and the third sub-power line, the first sub-power line, the second sub-power line and the third sub-power line all extend along the second direction; the plurality of multi-channel The multiplexing circuit is separated by the second sub-power line in the first direction.
  • the first power line further includes: a fourth sub-power line and a fifth sub-power line located in the first frame area, the fourth sub-power line and the fifth sub-power line The lines all extend along the first direction, and the fourth sub-power line is located on a side of the fifth sub-power line close to the display area.
  • the fourth sub-power line and the fifth sub-power line All are electrically connected to the first sub-power line, the second sub-power line and the third sub-power line; the plurality of multiplexing circuits, the plurality of first electrostatic discharge circuits and the plurality of second electrostatic discharge circuits The circuit is located between the fourth sub-power line and the fifth sub-power line.
  • At least one of the multiplexed data lines is electrically connected to a compensation resistor, and the compensation resistor is located on a side of the first electrostatic discharge circuit away from the display area.
  • the first frame area at least includes: a peripheral circuit area, a signal access area located on the side of the peripheral circuit area away from the display area, and a packaging area located between the peripheral circuit area and the signal access area, and the compensation resistor It is located in the packaging area and serves as the packaging base.
  • the arrangement direction of the plurality of discharge transistors included in the first electrostatic discharge circuit and the arrangement direction of the plurality of discharge transistors included in the second electrostatic discharge circuit are opposite to each other.
  • the plurality of first signal lines include: a plurality of multiplexed control lines and a plurality of driving signal lines.
  • embodiments of the present disclosure provide a display panel, including a display substrate as described above, and light-emitting elements disposed in a display area of the display substrate, where the light-emitting elements are arranged in an array.
  • embodiments of the present disclosure provide a display device, including the display panel as described above.
  • Figure 1 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure
  • Figure 2 is a partial cross-sectional structural diagram of a display area according to at least one embodiment of the present disclosure
  • Figure 3 is a partial schematic diagram of the frame area of at least one embodiment of the present disclosure.
  • Figure 4 is a partial enlarged schematic diagram of area A1 in Figure 3;
  • Figure 5 is an equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure.
  • Figure 6A is a schematic structural diagram of a multiplexing circuit according to at least one embodiment of the present disclosure.
  • Figure 6B is a schematic diagram of the multiplexing circuit after forming the second gate metal layer in Figure 6A;
  • Figure 6C is a schematic diagram of the multiplexing circuit after forming the third insulating layer in Figure 6A;
  • Figure 7 is an equivalent circuit diagram of an electrostatic discharge circuit according to at least one embodiment of the present disclosure.
  • Figure 8A is a schematic structural diagram of an electrostatic discharge circuit according to at least one embodiment of the present disclosure.
  • Figure 8B is a schematic diagram of the electrostatic discharge circuit after forming the second gate metal layer in Figure 8A;
  • Figure 8C is a schematic diagram of the electrostatic discharge circuit after forming the third insulating layer in Figure 8A;
  • Figure 9A is another structural schematic diagram of an electrostatic discharge circuit according to at least one embodiment of the present disclosure.
  • Figure 9B is a schematic diagram of the electrostatic discharge circuit after forming the second gate metal layer in Figure 9A;
  • Figure 10 is a partial schematic diagram of the first corner area of at least one embodiment of the present disclosure.
  • Figure 11 is a partial schematic diagram of the package wiring in the first corner area of at least one embodiment of the present disclosure.
  • Figure 12 is a partial cross-sectional schematic diagram along the Q-Q’ direction in Figure 11;
  • Figure 13 is an equivalent circuit diagram of a test circuit according to at least one embodiment of the present disclosure.
  • Figure 14A is a schematic structural diagram of a test circuit according to at least one embodiment of the present disclosure.
  • Figure 14B is a schematic diagram of the test circuit after forming the second gate metal layer in Figure 14A;
  • Figure 14C is a schematic diagram of the test circuit after forming the third insulating layer in Figure 14A;
  • Figure 15 is a partial schematic diagram of the second corner area of at least one embodiment of the present disclosure.
  • Figure 16 is a partial enlarged schematic diagram of area A2 in Figure 3;
  • Figure 17 is another schematic diagram of a display panel according to at least one embodiment of the present disclosure.
  • Figure 18 is a partial enlarged schematic diagram of area A3 in Figure 17;
  • FIG. 19 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • a transistor refers to an element including at least three terminals: a gate (gate electrode), a drain, and a source.
  • a transistor has a channel region between a drain (drain electrode terminal, drain region, or drain electrode) and a source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the gate can also be called the control electrode.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • element having some electrical function There is no particular limitation on the "element having some electrical function” as long as it can transmit electrical signals between connected components.
  • elements with some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with multiple functions.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • circles, ovals, triangles, rectangles, trapezoids, pentagons or hexagons are not strictly defined, and may be approximately circles, approximately ellipses, approximately triangles, approximately rectangles, approximately trapezoids, Approximate pentagons or approximate hexagons may have some small deformations caused by tolerances, such as leading corners, arc edges, and deformations.
  • a extending along direction B means that A may include a main part and a secondary part connected to the main part.
  • the main part is a line, line segment or bar-shaped body, the main part extends along direction B, and the main part
  • the length of the portion extending along direction B is greater than the length of the minor portion extending along the other directions.
  • “A extends along direction B” means "the main part of A extends along direction B".
  • a and B have the same layer structure means that A and B are formed simultaneously through the same patterning process.
  • “Same layer” does not always mean that the thickness of the layer or the height of the layer is the same in the cross-sectional view.
  • the orthographic projection of A contains the orthographic projection of B means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.
  • narrow-framed display designs have gradually become the mainstream form of display devices.
  • the layout of some signal lines and circuits in the display panel makes it impossible for the display panel to achieve a narrow bezel.
  • An embodiment of the present disclosure provides a display substrate, including: a display area and a frame area located around the display area.
  • the display substrate includes: a substrate, multiple data lines located on the substrate, multiple multiplexing circuits, multiple multiplexed data lines, A plurality of first electrostatic discharge circuits, a plurality of second electrostatic discharge circuits, and a plurality of first signal lines.
  • a plurality of data lines are located in the display area and configured to provide data signals to pixels in the display area.
  • a plurality of multiplexing circuits, a plurality of multiplexing data lines, a plurality of first electrostatic discharge circuits, a plurality of second electrostatic discharge circuits, and a plurality of first signal lines are located in the frame area.
  • a plurality of multiplexing circuits are arranged sequentially along the edge of the display area.
  • a plurality of multiplexing circuits are electrically connected to a plurality of multiplexed data lines and a plurality of data lines.
  • a plurality of first electrostatic discharge circuits are electrically connected to a plurality of multiplexed data lines, and a plurality of second electrostatic discharge circuits are electrically connected to a plurality of first signal lines.
  • a plurality of first electrostatic discharge circuits and a plurality of second electrostatic discharge circuits are located on a side of the multiplexing circuits away from the display area, and a plurality of second electrostatic discharge circuits are interspersed and arranged among the plurality of first electrostatic discharge circuits. .
  • the display substrate provided in this embodiment can reduce the arrangement space occupied by the second electrostatic discharge circuit by optimizing the arrangement position of the second electrostatic discharge circuit, thereby facilitating the realization of a narrow frame of the display substrate.
  • the frame area may include: a first frame area located on one side of the display area along the second direction.
  • a plurality of multiplexing circuits are located in the first frame area and are arranged side by side along the first direction, and the first direction intersects the second direction.
  • the arrangement space occupied by the multiplexed circuits can be reduced, thereby facilitating the realization of a narrow frame of the display substrate.
  • the display substrate may have a first center line, and the first center line may be parallel to the second direction.
  • the plurality of second electrostatic discharge circuits may be located in an area of the first frame area close to the first center line and an edge area of the first frame area away from the first center line.
  • the substrates are shown to be symmetrically distributed about the first center line as the axis of symmetry. The arrangement of the second electrostatic discharge circuit in this example is conducive to the electrostatic discharge of the corresponding wiring.
  • the frame area may further include: a second frame area located on a side of the display area away from the first frame area along the second direction.
  • the display substrate may further include: multiple test circuits located in the second frame area, and the multiple test circuits may be arranged side by side along the first direction. In this example, by arranging the test circuits side by side in the second frame area along the first direction, the arrangement space occupied by the test circuits can be reduced, thereby facilitating the realization of a narrow frame of the display substrate.
  • the frame area may further include: a third frame area and a fourth frame area located on opposite sides of the display area along the first direction, and a first corner area connecting the first frame area and the third frame area. , a second corner area connecting the third frame area and the second frame area, a third corner area connecting the second frame area and the fourth frame area, and a fourth corner area connecting the fourth frame area and the first frame area.
  • the display substrate may further include: a gate driving circuit, and the gate driving circuit may be located in the third frame area, the fourth frame area, the first corner area, the second corner area, the third corner area and the fourth corner area.
  • the gate drive circuit can be arranged in multiple corner areas, and the test circuit and the multiplexing circuit are not arranged in the corner area, which can be beneficial to reducing the size of the corner area and narrowing the corner area.
  • FIG. 1 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure.
  • the display panel may be a closed polygon including linear sides, such as a rectangular rounded shape.
  • the display panel has linear edges, at least some corners of the display panel may be curved.
  • a portion where adjacent linear sides meet each other may be replaced with a curve having a predetermined curvature.
  • the curvature can be set according to the different positions of the curve.
  • the curvature can be changed based on where the curve starts, the length of the curve, etc.
  • this embodiment is not limited to this.
  • the display panel may be circular or elliptical including curved sides, or semicircular or semi-elliptical including linear sides and curved sides, or the like.
  • the display panel may include a display substrate.
  • the display substrate may include: a display area AA and a frame area located around the display area AA.
  • the display area AA may include: a first edge (lower edge) and a second edge (upper edge) oppositely arranged in the second direction Y, and an opposite edge in the first direction X.
  • the first edge and the second edge may be linear sides parallel to each other, and the third edge and the fourth edge may be linear sides parallel to each other. Adjacent linear edges can be connected by curved edges.
  • the frame area may include: a first frame area (lower frame) B1 and a second frame area (upper frame) B2 arranged oppositely in the second direction Y.
  • the third frame area (left frame) B3 and the fourth frame area (right frame) B4 are arranged opposite to each other.
  • the first frame area B1 is adjacent to the first edge of the display area AA
  • the second frame area B2 is adjacent to the second edge of the display area AA
  • the third frame area B3 is adjacent to the third edge of the display area AA
  • the fourth The frame area B4 is adjacent to the fourth edge of the display area AA.
  • the first frame area B1 may be connected to the third frame area B3 through the first corner area C1, and may also be connected to the fourth corner area C4 and the fourth frame area B4.
  • the second frame area B2 may be connected to the third frame area B3 through the second corner area C2, and may also be connected to the fourth frame area B4 through the third corner area C3.
  • the first to fourth corner areas C1 to C4 each correspond to the arc-shaped edge of the display area AA.
  • the edges on the side away from the display area AA of the first to fourth corner areas C1 to C4 may all be curved edges.
  • the display area AA of the display substrate may at least include a plurality of pixel circuits, a plurality of gate lines, and a plurality of data lines.
  • the display panel may further include: a light-emitting element (ie, a sub-pixel) Px located in the display area AA of the display substrate.
  • the light-emitting elements Px can be arranged in an array.
  • the plurality of gate lines may extend along the first direction X, and the plurality of data lines may extend along the second direction Y. Orthographic projections of multiple gate lines and multiple data lines on the substrate can intersect to form multiple circuit areas, and a pixel circuit can be provided in each circuit area.
  • the plurality of data lines are electrically connected to the plurality of pixel circuits, and the plurality of data lines may be configured to provide data signals to the plurality of pixel circuits.
  • the plurality of gate lines are electrically connected to the plurality of pixel circuits, and the plurality of gate lines may be configured to provide gate control signals to the plurality of pixel circuits.
  • the gate control signal may include a scan signal, or may include a scan signal and a light emitting control signal.
  • the first direction sub-pixel column direction may be perpendicular to each other.
  • one pixel unit of the display area AA may include three sub-pixels, and the three sub-pixels are red sub-pixels, green sub-pixels and blue sub-pixels respectively.
  • this embodiment is not limited to this.
  • one pixel unit may include four sub-pixels, which are red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels.
  • the shape of the subpixel may be a rectangle, a diamond, a pentagon, or a hexagon.
  • a pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically or squarely.
  • the four sub-pixels can be arranged horizontally, vertically or squarely. ) arrangement.
  • this embodiment is not limited to this.
  • the pixel circuit may be configured to drive connected light emitting elements.
  • the pixel circuit may include a plurality of transistors and at least one capacitor.
  • the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • T in the above circuit structure refers to the thin film transistor
  • C refers to the capacitor
  • the number in front of T represents the number of thin film transistors in the circuit
  • the number in front of C represents the number of capacitors in the circuit.
  • the plurality of transistors in the pixel circuit may be P-type transistors, or may be N-type transistors. Using the same type of transistors in pixel circuits can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield.
  • the plurality of transistors in the pixel circuit may include P-type transistors and N-type transistors.
  • the plurality of transistors in the pixel circuit may employ low-temperature polysilicon thin film transistors, or may employ oxide thin film transistors, or may employ low-temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor uses low temperature polysilicon (LTPS, Low Temperature Poly-Silicon).
  • the active layer of the chemical thin film transistor uses oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • Low-temperature polysilicon thin film transistors and oxide thin film transistors are integrated on a display panel, that is, LTPS+Oxide (LTPO for short) Display panels can take advantage of both to achieve low-frequency driving, reduce power consumption, and improve display quality.
  • LTPS+Oxide LTPO for short
  • the light-emitting element may be a light-emitting diode (LED, Light Emitting Diode), an organic light-emitting diode (OLED, Organic Light Emitting Diode), a quantum dot light-emitting diode (QLED, Quantum Dot Light Emitting Diodes), or a micro-LED (including: Any of mini-LED or micro-LED), etc.
  • the light-emitting element can be an OLED, and the light-emitting element can emit red light, green light, blue light, or white light, etc., driven by its corresponding pixel circuit.
  • the color of the light-emitting element can be determined according to needs.
  • the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.
  • the anode of the light-emitting element may be electrically connected to the corresponding pixel circuit.
  • this embodiment is not limited to this.
  • FIG. 2 is a partial cross-sectional structural diagram of a display area according to at least one embodiment of the present disclosure.
  • Figure 2 illustrates the structure of three sub-pixels of the display panel.
  • the display panel may include: a substrate 101 , and a circuit structure layer 102 , a light-emitting structure layer 103 , and a packaging structure sequentially disposed on the substrate 101 layer 104 and encapsulation cover 200 .
  • the package cover 200 may be a glass cover, for example.
  • the display panel may include other film layers, such as spacer pillars, etc., which are not limited by this disclosure.
  • substrate 101 may be a rigid substrate, such as a glass substrate.
  • the substrate may be a flexible substrate, for example, made of an insulating material such as resin.
  • the substrate may have a single-layer structure or a multi-layer structure.
  • inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride may be disposed between multiple layers in a single layer or in multiple layers.
  • the circuit structure layer 102 may include multiple transistors and storage capacitors that constitute a pixel circuit.
  • each pixel circuit includes one transistor and one storage capacitor as an example.
  • the circuit structure layer 102 may include: an active layer disposed on the substrate 101; a first insulating layer 11 covering the active layer; and a first gate metal disposed on the first insulating layer 11.
  • the third insulating layer 13 of the second gate metal layer, the first insulating layer 11, the second insulating layer 12 and the third insulating layer 13 are provided with via holes, and the via holes expose the active layer; provided in the third insulating layer 13
  • the first source and drain metal layer (for example, including the source and drain electrodes of a transistor) on the There is a via hole on 14, and the via hole exposes the drain electrode.
  • the active layer, gate electrode, source electrode and drain electrode may form the transistor 105, and the first capacitor electrode and the second capacitor electrode may form the storage capacitor 106.
  • the light emitting structure layer 103 may include an anode layer, a pixel definition layer, an organic light emitting layer, and a cathode.
  • the anode layer may include the anode of the light-emitting element, and the anode may be disposed on the flat layer and connected to the drain electrode of the transistor of the pixel circuit through a via hole opened on the flat layer;
  • the pixel definition layer is disposed on the anode layer and the flat layer, and the pixel definition layer A pixel opening is provided on the top, and the pixel opening exposes the anode;
  • the organic light-emitting layer is at least partially set in the pixel opening, and the organic light-emitting layer is connected to the anode;
  • the cathode is set on the organic light-emitting layer, and the cathode is connected to the organic light-emitting layer;
  • the organic light-emitting layer is on the anode Driven by the cathode, light of corresponding colors is
  • the packaging structure layer 104 may include a stacked first packaging layer, a second packaging layer, and a third packaging layer.
  • the first packaging layer and the third packaging layer may be made of inorganic materials.
  • the second encapsulation layer can be made of organic materials.
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.
  • the organic light-emitting layer may include at least a hole injection layer, a hole transport layer stacked on the anode, light emitting layer and hole blocking layer.
  • the hole injection layers of all sub-pixels may be a common layer connected together
  • the hole transport layers of all sub-pixels may be a common layer connected together
  • the light-emitting layers of adjacent sub-pixels may have a small amount of Overlapping, or may be separate
  • hole blocking layers may be a common layer connected together.
  • this embodiment is not limited to this.
  • FIG. 3 is a partial schematic diagram of the frame area of at least one embodiment of the present disclosure.
  • the first frame area (lower frame) B1 of the display substrate may include at least: a signal access area B13 located on one side of the display area AA, and a signal access area B13 located on one side of the display area AA. and the first area between display area AA.
  • the first area may include: a peripheral circuit area B11 and a packaging area B12 that are sequentially arranged in the second direction Y along a direction away from the display area AA.
  • the encapsulation area B12 may be an area where encapsulation glue is applied or printed.
  • the packaging area B12 may be an annular area surrounding the display area AA, which is beneficial to improving the packaging effect.
  • the peripheral circuit area B11 of the first frame area B1 may be provided with multiple multiplexing circuits 41 , multiple first electrostatic discharge (ESD) circuits 31 , and multiple a second electrostatic discharge circuit 32.
  • a plurality of multiplexing circuits 41 may be arranged side by side along the first direction X.
  • the first electrostatic discharge circuit 31 and the second electrostatic discharge circuit 32 may be located on a side of the multiplexing circuit 41 away from the display area AA.
  • Each multiplexing circuit 41 may be electrically connected to a plurality of data lines within the display area AA, and may be configured to enable one signal source to provide data signals for the plurality of data lines.
  • each multiplexing circuit 41 may be electrically connected to a multiplexed data line, and a signal source providing a data signal may be electrically connected through the multiplexed data line.
  • a plurality of multiplexed data lines and a plurality of first electrostatic discharge circuits 31 can be electrically connected in a one-to-one correspondence to discharge static electricity.
  • the peripheral circuit area B11 may also be provided with multiple data fan-out lines.
  • the plurality of data fan-out lines may be electrically connected to the plurality of data lines in the display area AA and to the multiplexing circuit 41 of the peripheral circuit area B11.
  • multiple data fan-out lines may be electrically connected to multiple data lines in one-to-one correspondence.
  • the data lines may be electrically connected to the multiplexing circuit 41 through data fanout lines.
  • the plurality of multiplexed data lines can extend to the signal access area B13 and be electrically connected to the plurality of first signal access pins in the signal access area B13.
  • the multiple data fan-out lines may be in the same layer structure, for example, may be located on the first gate metal layer.
  • the peripheral circuit area B11 may also be provided with multiple first signal lines, and the multiple first signal lines may extend to the signal access area B13 and be connected to multiple second signals in the signal access area B13.
  • the input pins correspond to the electrical connections.
  • the plurality of first signal lines may also extend to the third frame area B3 and the second corner area C2 through the first corner area C1, and extend to the fourth frame area B4 and the third corner area C3 through the fourth corner area C4.
  • the first signal line may be electrically connected to the second static electricity discharge circuit 32 to discharge static electricity.
  • the first signal line may include: a plurality of reset control lines, a plurality of drive signal lines, a test control line and a test data line.
  • a gate driving circuit 43 may be provided in the third frame area B3, the fourth frame area B4, and the first to fourth corner areas C1 to C4.
  • the gate driving circuit 43 may include a plurality of driving units.
  • each driving unit may be configured to provide a scan signal to a row of sub-pixels within the display area AA.
  • the plurality of driving units may be arranged sequentially along the edge extending direction of the display area AA.
  • the drive signal line may be electrically connected to the gate drive circuit 43 to provide drive signals (eg, clock signal, start signal, power signal, etc.) to the gate drive circuit.
  • test circuits 42 may be provided in the second frame area B2.
  • the plurality of test circuits 42 may be arranged sequentially along the first direction X.
  • Each test circuit 42 may be electrically connected to a plurality of data lines within the display area AA, and may be configured to provide test data signals to the plurality of data lines.
  • the frame area may also be provided with first power lines 51 and second power lines 52 .
  • the second power line 52 may be located on a side of the first power line 51 away from the display area AA.
  • the first power line 51 and the second power line 52 may surround the display area AA.
  • the second power line 52 is within the first frame area B1 The end can extend to the signal access area B13 and be electrically connected to the second power signal access pin in the signal access area B13.
  • the first power line 51 in the first frame area B1 may include: a first sub-power line 511 , a second sub-power line 512 , a third sub-power line 513 , and a fourth sub-power line. Line 514 and the fifth sub-power line 515.
  • the first power line 51 in the first frame area B1 may have an integrated structure.
  • the first sub-power line 511 , the second sub-power line 512 and the third sub-power line 513 may all extend along the second direction Y.
  • the fourth sub-power line 514 may extend along the first direction X and be electrically connected to the first sub-power line 511, the second sub-power line 512 and the third sub-power line 513 respectively.
  • the fifth sub-power line 515 is located on the side of the fourth sub-power line 514 away from the display area.
  • the fifth sub-power line 515 may have a main body portion extending in the first direction X, and first and second extending portions extending in the second direction Y.
  • the first sub-power line 511, the second sub-power line 512, the third sub-power line 513 and the fourth sub-power line 514 may be located in the peripheral circuit area B11, and the fifth sub-power line 515 may be partially located in the peripheral circuit area B11 and partially located in the peripheral circuit area B11.
  • the first extension part and the second extension part may extend from both sides of the first center line OO' to the signal access area B13, and be electrically connected to the first power signal access pin in the signal access area B13.
  • the fourth sub-power line 514 may be electrically connected to a plurality of first power connection lines in the display area to provide first power signals to sub-pixels in the display area.
  • the second sub-power line 512 may be located at the first center line OO'
  • the first sub-power line 511 and the third sub-power line 513 may be located at opposite sides of the first center line OO'
  • the first sub-power line 511 may be close to the first center line OO'.
  • the third sub-power line 513 may be close to the fourth corner area C4.
  • the first sub-circuit line 511 to the fifth sub-power line 515 are connected to form a first area and a second area, and the first area and the second area are located on opposite sides of the first center line OO'.
  • the multiplexing circuit 41, the first electrostatic discharge circuit 31 and the second electrostatic discharge circuit 32 may be located in the first area and the second area.
  • One end of the fourth sub-power line 514 can extend to the first corner area C1 and the third frame area B3 along the edge extension direction of the display area, and the other end can extend to the fourth corner area C4 and the fourth corner area C4 along the edge extension direction of the display area. Border area B4.
  • the portion of the fifth sub-power line 515 located in the packaging area B12 and the portion of the second power line 52 located in the packaging area B12 may serve as the first encapsulant base.
  • a plurality of openings may be provided on the first encapsulating glue base.
  • the first power signal can be transmitted to the side close to the display area AA through the first sub-power line 511, the second sub-power line 512 and the third sub-power line 513.
  • a design of three-way transmission to the display area can be used. Effectively reducing the attenuation of the first power signal can improve the current attenuation caused by the signal attenuation from bottom to top and from the middle to both sides of the first power signal transmitted to the display area, which can improve the brightness uniformity of the display area and improve display effect.
  • the design of the first power line is conducive to supporting the multiplexing circuits to be arranged sequentially along the first direction in the first frame area.
  • FIG. 4 is a partially enlarged schematic diagram of area A1 in FIG. 3 .
  • a plurality of multiplexing circuits 41 , a plurality of first electrostatic discharge circuits 31 and a plurality of second electrostatic discharge circuits 32 may be located on the first power line. in the area between the fourth sub-power line 514 and the fifth sub-power line 515 .
  • the front projection of the fourth sub-power line 514 and the fifth sub-power line 515 on the substrate may not overlap with the front projection of the multiplexing circuit 41, the first electrostatic discharge circuit 31 and the second electrostatic discharge circuit 32 on the substrate. .
  • the first electrostatic discharge circuit 31 and the second electrostatic discharge circuit 32 may be located on a side of the multiplexing circuit 41 away from the display area.
  • the multiplexing circuit 41 and the first electrostatic discharge circuit 31 may be electrically connected through a multiplexing data line.
  • the second electrostatic discharge circuit 32 may be interposed between the plurality of first electrostatic discharge circuits 31 .
  • a second electrostatic discharge circuit 32 may be provided between two adjacent first electrostatic discharge circuits 31 .
  • the second electrostatic discharge circuit 32 may be located on a side of the first electrostatic discharge circuit 31 away from the display area.
  • the first frame area may also be provided with multiple multiplexing control lines (for example, the first multiplexing control line 611 to the sixth multiplexing control line 616), the test control line 620, the Test data lines (for example, the first test data line 621), a plurality of drive signal lines (for example, including: the start signal line 631, the first clock signal line 632, the second clock signal line 633, the drive output line 634, the third power supply line line VGH and the fourth power line VGL).
  • the first test data line 621 and the test control line 620 may extend through the first corner area, the third frame area, and the second corner area to be electrically connected to the test circuit in the second frame area.
  • the start signal line 631, the first clock signal line 632, the second clock signal line 633, the driving output line 634, the third power supply line VGH and the fourth power supply line VGL may be electrically connected to the gate driving circuit.
  • the start signal line 631 may be configured to provide a start signal to the gate driving circuit
  • the first clock signal line 632 may be configured to provide a first clock signal to the gate driving circuit
  • the second clock signal line 633 may be configured to provide a starting signal to the gate driving circuit.
  • the second clock signal and the third power line VGH may be configured to provide a third power signal to the gate driving circuit
  • the fourth power line VGL may be configured to provide a fourth power signal to the gate driving circuit.
  • the voltage value of the third power signal may be greater than the voltage value of the fourth power signal.
  • the gate drive circuit may include a plurality of cascaded drive units, the start signal line 631 may be electrically connected to the first-level drive unit, and the drive output line 634 may be electrically connected to the last-level drive unit, configured to drive the last-level drive unit.
  • the output signal of the unit is transmitted to the control device to detect whether the gate drive circuit is working properly. At least part of the line segments of the multiplexed control line may extend along the first direction X, and at least part of the line segments of the driving signal line may extend along the first direction X.
  • the plurality of multiplexed control lines, the first test data line 621, the test control line 620, and the plurality of driving signal lines may be arranged sequentially along the second direction Y.
  • the multiplexing control lines may be located on a side of the multiplexing circuit away from the display area, and the multiple driving signal lines may be located between the first electrostatic discharge circuit and the multiplexing control lines.
  • a plurality of second electrostatic discharge circuits 32 close to the first neutral line may be electrically connected to a plurality of multiplexed control lines respectively to release static electricity from the multiplexed control lines.
  • the plurality of second electrostatic discharge circuits 32 located at the edge of the first frame area away from the first center line may be electrically connected to the plurality of driving signal lines respectively to discharge the static electricity of the plurality of driving signal lines.
  • FIG. 5 is an equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure.
  • a multiplexing circuit may be electrically connected to a multiplexed control line and a multiplexed data line, and a may be a positive integer greater than or equal to 2.
  • Two multiplexing circuits are illustrated in Figure 5, each multiplexing circuit is electrically connected to six multiplexing control lines.
  • the multiplexing circuit 41 may include six multiplexing transistors MT.
  • the gates of the multiplexing transistors MT are respectively connected to different multiplexing control lines, that is, the gate of the first multiplexing transistor is connected to the first multiplexing control line 611, and the gate of the second multiplexing transistor is connected to the second multiplexing control line 611.
  • the gate of the third multiplexing transistor is connected to the third multiplexing control line 613
  • the gate of the fourth multiplexing transistor is connected to the fourth multiplexing control line 614
  • the gate of the fifth multiplexing transistor is connected to the control line 612.
  • the fifth multiplexing control line 615 is connected
  • the gate of the sixth multiplexing transistor is connected to the sixth multiplexing control line 616 .
  • the first poles of the six multiplexing transistors MT are all connected to the same multiplexed data line (for example, the multiplexed data line 610).
  • the second poles of the six multiplexing transistors MT are respectively connected to different data lines DL in the display area. That is, the second electrode of the first multiplexing transistor is connected to a data line DL in the display area, and the second electrode of the second multiplexing transistor is connected to a data line DL in the display area.
  • the two poles are connected to another data signal line DL... in the display area.
  • the control device provides turn-on signals to the six multiplexing control lines in a time-sharing manner, so that the six multiplexing transistors MT in each multiplexing circuit 41 are turned on in a time-sharing manner.
  • the multiplexed data line provides the data signal required by the data line connected to the turned-on multiplexing transistor MT, and the data line writes the data signal into the corresponding sub-pixel.
  • one signal source (such as a pin of a driver chip) can provide data signals for multiple data lines, which can greatly reduce the number of actual signal sources and simplify the product structure.
  • one multiplexing circuit 41 may include three multiplexing transistors to control three data lines (ie, one for three).
  • FIG. 6A is a schematic structural diagram of a multiplexing circuit according to at least one embodiment of the present disclosure.
  • Figure 6B is a diagram formed in Figure 6A Schematic of the multiplexing circuit behind the second gate metal layer.
  • FIG. 6C is a schematic diagram of the multiplexing circuit after forming the third insulating layer in FIG. 6A.
  • FIG. 6A is a schematic diagram of the multiplexing circuit after forming the first source-drain metal layer.
  • one multiplexing circuit may include six multiplexing transistors (eg, first to sixth multiplexing transistors MT1 to MT6 ) arranged sequentially along the first direction X.
  • the first active layer 401 of the first multiplexing transistor MT1 , the second active layer 402 of the second multiplexing transistor MT2 , and the third active layer of the third multiplexing transistor MT3 Orthographic projection of layer 403, the fourth active layer 404 of the fourth multiplexing transistor MT4, the fifth active layer 405 of the fifth multiplexing transistor MT5, and the sixth active layer 406 of the sixth multiplexing transistor MT6 on the substrate They may be rectangular and may be arranged sequentially along the first direction X.
  • the first gate metal layer of the multiplexing circuit may include: gates of multiple multiplexing transistors and multiple data fan-out lines 21 .
  • the fifth gate 415 of the fifth multiplexing transistor MT5 and the sixth gate 416 of the sixth multiplexing transistor MT6 may be arranged sequentially along the first direction X, and the length along the second direction Y may gradually increase.
  • the plurality of data fan-out lines 21 may be arranged sequentially along the first direction X.
  • the data fan-out line 21 may extend toward one side of the display area so as to be electrically connected to the data lines of the display area.
  • the plurality of data fan-out lines 21 may be electrically connected to the plurality of data lines in the display area in a one-to-one correspondence.
  • the second gate metal layer of the multiplexing circuit may include: multiplexed data line 610 .
  • the multiplexing data line 610 may be located on a side of the active layer of the multiplexing transistor away from the display area. In other examples, the multiplexed data line 610 may be located on the first gate metal layer.
  • the third insulating layer in the first frame region may be provided with a plurality of via holes, which may include, for example, the first via hole V1 to the twenty-fifth via hole V25.
  • the third insulating layer and the second insulating layer in the first to twelfth via holes V1 to V12 may be removed, exposing the surface of the first gate metal layer of the multiplexing circuit.
  • the third insulating layer, the second insulating layer and the first insulating layer in the thirteenth via hole V13 to the twenty-fourth via hole V24 can be removed, exposing the active components of the multiplexing transistors of the multiplexing circuit. layer surface.
  • the third insulating layer in the twenty-fifth via hole V25 can be removed to expose the surface of the second gate metal layer.
  • the first source-drain metal layer of the multiplexing circuit may include: first and second poles of six multiplexing transistors, first multiplexing control lines 611 to sixth Multiplex control line 616.
  • the first pole of the transistor MT6 and the first pole of the sixth multiplexing transistor MT6 may have an integrated structure. For example, as shown in FIGS.
  • the first pole 451 of the first multiplexing transistor MT1 can be electrically connected to the first active layer 401 through six thirteenth vias V13 arranged vertically, or can also be connected through vertically arranged thirteenth vias V13 .
  • the six fifteenth via holes V15 arranged in a row are electrically connected to the second active layer 402, and can also be electrically connected to the third active layer 403 through the six seventeenth via holes V17 arranged in a vertical row.
  • the six 19th via holes V19 arranged in a row are electrically connected to the fourth active layer 404, and can also be electrically connected to the fifth active layer 405 through the six 21st via holes V21 arranged in a vertical row.
  • the six twenty-third via holes V23 arranged in vertical rows are electrically connected to the sixth active layer 406, and can also be electrically connected to the multiplexed data line 610 through the two twenty-fifth via holes V25 arranged in horizontal rows.
  • the second pole 452 of the first multiplexing transistor MT1 may be electrically connected to the first active layer 401 through six fourteenth vias V14 arranged vertically, and also It can be electrically connected to the first data fan-out line 21 through the seventh via V7.
  • the second pole 453 of the second multiplexing transistor MT2 can be electrically connected to the second active layer 402 through the six sixteenth vias V16 arranged vertically, and can also be connected to the second data fan-out line through the eighth via V8 21 electrical connections.
  • the second pole 454 of the third multiplexing transistor MT3 can be electrically connected to the third active layer 403 through the six eighteenth vias V18 arranged vertically, and can also be connected to the third data fan-out line through the ninth via V9 21 electrical connections.
  • the second pole 455 of the fourth multiplexing transistor MT4 can be connected to the fourth active layer through the six twentieth vias V20 arranged vertically. 404 electrical connection, and can also be electrically connected to the fourth data fan-out line 21 through the tenth via V10.
  • the second pole 456 of the fifth multiplexing transistor MT5 can be electrically connected to the fifth active layer 405 through the six twenty-second vias V22 arranged vertically, and can also be connected to the fifth piece of data through the eleventh via V11.
  • the fan-out line 21 is electrically connected.
  • the second pole 457 of the sixth multiplexing transistor MT6 can be electrically connected to the sixth active layer 406 through the six twenty-fourth vias V24 arranged vertically, and can also be connected to the sixth piece of data through the twelfth via V12.
  • the fan-out line 21 is electrically connected.
  • the first gate 411 of the first multiplexing transistor MT1 may be electrically connected to the first reset control line 611 through two first vias V1 arranged in a row.
  • the second gate 412 of the second multiplexing transistor MT2 may be electrically connected to the second reset control line 612 through two second vias V2 arranged in a horizontal row.
  • the third gate 413 of the third multiplexing transistor MT3 may be electrically connected to the third reset control line 613 through two third vias V3 arranged in a horizontal row.
  • the fourth gate 414 of the fourth multiplexing transistor MT4 may be electrically connected to the fourth reset control line 614 through two fourth vias V4 arranged in a horizontal row.
  • the fifth gate 415 of the fifth multiplexing transistor MT5 may be electrically connected to the fifth reset control line 615 through two fifth vias V5 arranged in a horizontal row.
  • the sixth gate 416 of the sixth multiplexing transistor MT6 may be electrically connected to the sixth reset control line 616 through two sixth vias V6 arranged in a horizontal row.
  • the multiplexing transistors of the multiplexing circuit may be electrically connected to the plurality of data lines in the display area through the data fan-out lines 21 located on the first gate metal layer. Since the parasitic capacitance generated per unit area where the first gate metal layer and the first source-drain metal layer overlap is smaller than the parasitic capacitance generated per unit area where the second gate metal layer overlaps the first source-drain metal layer, by fanning out the data line Setting it on the first gate metal layer can effectively reduce parasitic capacitance, thereby reducing the load and optimizing the display effect.
  • no multiplexing circuit is provided in the first corner area and the fourth corner area, and all multiplexing circuits are provided in the first frame area.
  • the plurality of multiplexing circuits can be divided into two groups and arranged on opposite sides of the second sub-power line. By arranging multiple multiplexing circuits side by side in the first frame area, and the intervals between adjacent multiplexing circuits can be reduced, the space occupied by the multiplexing circuits can be reduced. Not arranging multiplexing circuits in the first corner area and the fourth corner area can facilitate the driving unit of the gate driving circuit to be arranged closer to the display area side, thereby greatly reducing the power consumption of the first corner area and the fourth corner area.
  • the outer edge arc size allows the outer edge position of the first corner area and the fourth corner area to be closer to the display area, reducing the frame size of the first corner area and the fourth corner area, which is beneficial to realizing a narrow frame design of the display substrate .
  • FIG. 7 is an equivalent circuit diagram of an electrostatic discharge circuit according to at least one embodiment of the present disclosure.
  • at least one electrostatic discharge circuit is connected to a second signal line 22 and is configured to release static electricity in the second signal line 22 to which it is connected.
  • the second signal line connected to the first electrostatic discharge circuit may be a multiplexed data line
  • the second signal line connected to the second electrostatic discharge circuit may be a driving signal line.
  • An electrostatic discharge circuit may include first to fourth discharge transistors ST1 to ST4.
  • the first electrode of the first release transistor ST1 is electrically connected to the fourth power supply line VGL.
  • the gate electrode and the second electrode of the first release transistor ST1 are electrically connected to the first electrode of the second release transistor ST2.
  • the gate electrode of the second release transistor ST2 The first pole and the second pole of the third release transistor ST3 are electrically connected to the second signal line 22 corresponding to the electrostatic discharge circuit.
  • the first pole of the third release transistor ST3 is electrically connected to the second signal line 22 corresponding to the electrostatic discharge circuit.
  • the gate of the third release transistor ST3 The gate electrode and the second electrode of the fourth release transistor ST4 are electrically connected to the third power supply line VGH.
  • providing an electrostatic discharge circuit can prevent static electricity accumulation in the second signal line from causing discharge breakdown and damage, so as to release the static electricity accumulated in the second signal line to protect the second signal line.
  • the electrostatic discharge circuit may include two discharge transistors, wherein one electrode of each discharge transistor is connected to its own gate, thereby forming an equivalent diode connection; and between the two "diodes” Connect the signal line to be protected, and the other two ends of the two “diodes” are connected to the third power line VGH and the fourth power line VGL respectively.
  • FIG. 8A is a schematic structural diagram of an electrostatic discharge circuit according to at least one embodiment of the present disclosure.
  • FIG. 8B is a schematic diagram of the electrostatic discharge circuit after forming the second gate metal layer in FIG. 8A.
  • FIG. 8C is a schematic diagram of the electrostatic discharge circuit after forming the third insulating layer in FIG. 8A.
  • FIG. 8A is a schematic diagram of the electrostatic discharge circuit after forming the first source-drain metal layer.
  • two first electrostatic discharge circuits and one second electrostatic discharge circuit are used as examples for schematic illustration.
  • the equivalent circuit diagrams of the first electrostatic discharge circuit and the second electrostatic discharge circuit are both shown in Figure 7.
  • the first electrostatic discharge circuit may include first to fourth discharge transistors ST1a to ST4a
  • the second electrostatic discharge circuit may include first to fourth discharge transistors ST1b to ST4b.
  • the first active layer 301 of the first discharge transistor ST1a, the second active layer 302 of the second discharge transistor ST2a, and the third discharge transistor of the first electrostatic discharge circuit The orthographic projection of the third active layer 303 of ST3a and the fourth active layer 304 of the fourth release transistor ST4a on the substrate may be a rectangle, and may be arranged sequentially along the first direction X.
  • the first active layer 301 of the first release transistor ST1a and the second active layer 302 of the second release transistor ST2a may be an integrated structure
  • the fourth active layer 304 may be an integral structure.
  • the first active layer 305 of the first discharge transistor ST1b, the second active layer 306 of the second discharge transistor ST2b, the third active layer 307 of the third discharge transistor ST3b and the fourth discharge transistor ST4b of the second electrostatic discharge circuit may be rectangular, and may be arranged sequentially along the first direction X.
  • the arrangement direction of the four discharge transistors of the second electrostatic discharge circuit and the arrangement direction of the four discharge transistors of the first electrostatic discharge circuit may be opposite to each other.
  • the first active layer 305 of the first release transistor ST1b and the second active layer 306 of the second release transistor ST2b may be an integrated structure
  • the fourth active layer 308 may be an integral structure.
  • the first gate metal layer of the electrostatic discharge circuit may further include: gates of a plurality of discharge transistors of the first electrostatic discharge circuit (for example, the gates of the first discharge transistor ST1a 311, the gate 312 of the second discharge transistor ST2a, the gate 313 of the third discharge transistor ST3a, and the gate 314 of the fourth discharge transistor ST4a), the gates of the plurality of discharge transistors of the second electrostatic discharge circuit (for example, The gate electrode 321 of the first release transistor ST1b, the gate electrode 322 of the second release transistor ST2b, the gate electrode 323 of the third release transistor ST3b and the gate electrode 324 of the fourth release transistor ST4b), the second connection line 342 and the third connection Line 343.
  • a plurality of discharge transistors of the first electrostatic discharge circuit for example, the gates of the first discharge transistor ST1a 311, the gate 312 of the second discharge transistor ST2a, the gate 313 of the third discharge transistor ST3a, and the gate 314 of the fourth discharge transistor ST4a
  • the first electrostatic discharge circuit can be electrically connected to the multiplexed data line through the second connection line 342.
  • the second connection line 342 can be located on the first gate metal layer and be integrated with the multiplexed data line located on the first gate metal layer. structure, or the second connection line 342 may be located on the first gate metal layer and electrically connected to the multiplexed data line located on the second gate metal layer.
  • the second electrostatic discharge circuit may be electrically connected to a driving signal line through a third connection line 343.
  • the third connection line 343 may be electrically connected to the driving output line 634.
  • the second gate metal layer of the electrostatic discharge circuit may further include: a first connection line 341 .
  • the first connection line 341 may extend along the second direction Y.
  • this embodiment is not limited to this.
  • the third insulating layer in the first frame region may be provided with multiple via holes, which may include, for example, the thirty-first via hole V31 to the fifty-sixth via hole V56.
  • the third insulating layer, the second insulating layer and the first insulating layer in the thirty-first to forty-second via holes V31 to V42 may be removed to expose the surface of the active layer of the electrostatic discharge circuit.
  • the third insulating layer and the second insulating layer in the forty-third via hole V43 to the fifty-second via hole V52 can be removed to expose the surface of the first gate metal layer.
  • the third insulating layer in the fifty-fifth via hole V55 and the fifty-sixth via hole V56 can be removed to expose the surface of the second gate metal layer.
  • the first source-drain metal layer of the electrostatic discharge circuit may include: a plurality of connection electrodes (for example, the first connection electrode 331 to the ninth connection electrode 339).
  • the first connection electrode 331 may pass through a third
  • the eleventh via V31 is electrically connected to the first active layer 301 of the first discharge transistor ST1a of the first electrostatic discharge circuit, and can also be electrically connected to the first connection line 341 through the fifty-fifth via V55.
  • the first connection line 341 may be electrically connected to the fourth power line VGL through the fifty-sixth via hole V56.
  • the second connection electrode 332 can be electrically connected to the gate electrode 311 of the first release transistor ST1a through the 43rd via hole V43, and can also be electrically connected to the second active layer 302 of the second release transistor ST2a through the 32nd via hole V32. Electrical connection.
  • the third connection electrode 333 can be electrically connected to the gate electrode 312 of the second release transistor ST2a through the 44th via hole V44, and can also be electrically connected to the second active layer 302 of the second release transistor ST2a through the 33rd via hole V33.
  • the electrical connection can also be electrically connected to the second connection line 342 through the forty-fifth via hole V45, and can also be electrically connected to the third active layer 303 of the third release transistor ST3a through the thirty-fourth via hole V34.
  • the fourth connection electrode 334 can be electrically connected to the gate electrode 313 of the third release transistor ST3a through the 46th via hole V46, and can also be electrically connected to the third active layer 303 of the third release transistor ST3a through the 35th via hole V35. Electrical connection.
  • the fifth connection electrode 335 can be electrically connected to the fourth active layer 304 of the fourth release transistor ST4a through the thirty-sixth via hole V36, and can also be electrically connected to the gate electrode 314 of the fourth release transistor ST4a through the forty-seventh via hole V47.
  • the electrical connection can also be electrically connected to the fourth active layer 308 of the fourth release transistor ST4b of the second electrostatic discharge circuit through the thirty-seventh via V37, and can also be electrically connected to the fourth release transistor through the forty-eighth via V48.
  • Gate 324 of ST4b is electrically connected.
  • the gate 314 of the fourth release transistor ST4a may be electrically connected to the third power line VGH through the fifty-third via hole V53.
  • the sixth connection electrode 336 can be electrically connected to the fourth active layer 308 of the fourth discharge transistor ST4b of the second electrostatic discharge circuit through the thirty-eighth via V38, and can also be electrically connected to the third discharge transistor ST4b through the forty-ninth via V49.
  • the gate 323 of the transistor ST3b is electrically connected.
  • the seventh connection electrode 337 can be electrically connected to the third active layer 307 of the third release transistor ST3b through the thirty-ninth via hole V39, and can also be electrically connected to the third connection line 343 through the fiftieth via hole V50.
  • the fortieth via hole V40 is electrically connected to the second active layer 306 of the second release transistor ST2b, and the fifty-first via hole V51 is also electrically connected to the gate electrode 322 of the second release transistor ST2b.
  • the eighth connection electrode 338 can be electrically connected to the second active layer 306 of the second release transistor ST2b through the 41st via hole V41, and can also be electrically connected to the gate electrode 321 of the first release transistor ST1b through the 52nd via hole V52. Electrical connection.
  • the ninth connection electrode 339 may be electrically connected to the first active layer 305 of the first release transistor ST1b through the 42nd via hole V42, and may also be electrically connected to the first electrode of the first release transistor of another first electrostatic discharge circuit. connect.
  • the third connection line 343 can be electrically connected to the driving output line 634 through the fifty-fourth via hole V54 to release static electricity on the driving output line 634 .
  • FIG. 9A is another structural schematic diagram of an electrostatic discharge circuit according to at least one embodiment of the present disclosure.
  • FIG. 9B is a schematic diagram of the electrostatic discharge circuit after forming the second gate metal layer in FIG. 9A.
  • FIG. 9A is a schematic diagram of the electrostatic discharge circuit after forming the first source-drain metal layer.
  • the first electrostatic discharge circuit and the second electrostatic discharge circuit may be arranged sequentially along the first direction X and aligned.
  • the second electrostatic discharge circuit may be located between two adjacent first electrostatic discharge circuits.
  • the fourth active layer 308 of the fourth discharge transistor ST4b of the second electrostatic discharge circuit and the fourth active layer 304 of the adjacent fourth discharge transistor ST4a of the first electrostatic discharge circuit may have an integrated structure.
  • the first active layer 305 of the first discharge transistor ST1b of the circuit and the first active layer 301 of the first discharge transistor ST1a of another adjacent first electrostatic discharge circuit may have an integrated structure.
  • other structures of the electrostatic discharge circuit of this embodiment reference can be made to the description of the previous embodiment, and therefore no further description is given here.
  • arranging the second electrostatic discharge circuit between the first electrostatic discharge circuits can reduce the space occupied by the second electrostatic discharge circuit and simplify the wiring arrangement, which can greatly save space and benefit the first frame. Narrowing of the area (i.e. lower border).
  • FIG. 10 is a partial schematic diagram of a first corner area according to at least one embodiment of the present disclosure.
  • the gate driving circuit may include a plurality of cascaded driving units 431 .
  • the driving units 431 may be disposed in the third frame area and the first corner area, and are sequentially arranged along the edge extension direction of the display area.
  • the multiplexing circuit 41, the first electrostatic discharge circuit 31 and the second electrostatic discharge circuit 32 may be located in the first frame area.
  • the multiplexing circuit 41 near the junction of the first frame area and the first corner area may be electrically connected to a column of pixel circuits in the left edge area of the display area through the arc-shaped data fan-out line 21 .
  • the plurality of drive signal lines in the first frame area can extend to the first corner area domain, and use the transfer line located on the first gate metal layer for transfer to avoid conflict with the first sub-power line 511.
  • An initial signal line 641 may also be provided on the side of the fourth sub-power line 514 close to the multiplexing circuit 41 .
  • a third electrostatic discharge circuit 33 may also be provided in the first corner area.
  • the third electrostatic discharge circuit 33 may be located on a side of the driving unit 431 close to the junction of the first corner area and the first frame area.
  • the third electrostatic discharge circuit 33 may be electrically connected to the driving signal line extending to the first corner area to discharge static electricity from the driving signal line.
  • this embodiment is not limited to this.
  • the electrostatic discharge circuit may not be provided in the first corner area to save space and facilitate narrowing of the first corner area.
  • a second power line 52 and a package trace 53 located on the side of the second power line 52 away from the display area are also provided in the first corner area and the third frame area.
  • the package trace 53 and the second power line 52 may be electrically connected.
  • the second power line 52 may be arranged in a different layer from the package trace 53 .
  • the package trace 53 may be located on a side of the second power line 52 close to the substrate.
  • FIG. 11 is a partial schematic diagram of the package traces in the first corner area according to at least one embodiment of the present disclosure.
  • Figure 12 is a partial cross-sectional view along the Q-Q’ direction in Figure 11.
  • the package trace 53 may be provided with a plurality of openings 530 .
  • the orthographic projection of the opening 530 on the substrate may be, for example, a rectangle.
  • the package trace 53 may be located on the first gate metal layer, and the second power line 52 may be located on the first source-drain metal layer.
  • the edge of the package trace 53 close to the second power line 52 has a plurality of protrusions, and the plurality of protrusions can be electrically connected to the second power line 52 through the sixty-first via hole V61.
  • the second insulating layer 12 and the third insulating layer 13 in the sixty-first via hole V61 may be removed, exposing the surface of the protruding portion of the second power line 52 .
  • a plurality of via arrays V62 may also be provided on the second insulating layer 12 and the third insulating layer 13 .
  • the orthographic projection of the opening 530 provided on the package trace 53 on the substrate 101 may cover the orthographic projection of the via array V62 on the substrate 101 .
  • the via array V62 can be filled with encapsulating glue 201 so that the packaging cover 200 can be fixed through the encapsulating glue 201 .
  • FIG. 13 is an equivalent circuit diagram of a test circuit according to at least one embodiment of the present disclosure.
  • the test circuit may include b test transistors and may be electrically connected to at least one test control line and b test data lines, where b may be a positive integer greater than or equal to 2.
  • FIG. 13 takes one test control line, three test data lines and two test circuits 42 (each test circuit 42 includes three test transistors CT) as an example. As shown in FIG. 13 , the gates of the three test transistors CT in the same test circuit 42 are all connected to the same test control line 620 .
  • the first poles of the three test transistors CT are respectively connected to different test data lines, that is, the first pole of the first test transistor is connected to the first test data line 621, and the first pole of the second test transistor is connected to the second test data line. 622.
  • the first electrode of the third test transistor is connected to the third test data line 623.
  • the second poles of the three test transistors CT are respectively connected to different data lines DL in the display area, that is, the second pole of the first test transistor is connected to one data line DL, and the second pole of the second test transistor is connected to another data line. DL, the second electrode of the third test transistor is connected to another data line DL.
  • the conduction of the three test transistors CT in the test circuit 42 can be controlled through the test control line 620, and the signals of different test data lines can be controlled to be written into different data lines DL.
  • the control device provides a conduction signal to the test control line 620 and provides required test data signals to multiple test data lines respectively, so that multiple data lines in the display area obtain test data signals to implement detection.
  • the test control line 620 and the first test data line 621 may extend from the first frame area through the first corner area, the third frame area, and the second corner area to the second frame area, and the second test data line 622
  • the third test data line 623 may extend from the first frame area to the second frame area through the fourth corner area, the fourth frame area and the third corner area.
  • the sub-pixels connected to each data line are of the same color.
  • the same test data signal is provided to the data lines corresponding to the sub-pixels of the same color, so that these sub-pixels perform the same display, which is determined by the color of the display screen. Whether there are any defective sub-pixels, and the positioning of the defective sub-pixels.
  • FIG. 14A is a schematic structural diagram of a test circuit according to at least one embodiment of the present disclosure.
  • FIG. 14B is a schematic diagram of the test circuit after forming the second gate metal layer in FIG. 14A.
  • Figure 14C is a view of the test circuit after forming the third insulating layer in Figure 14A Schematic diagram.
  • FIG. 14A is a schematic diagram of the test circuit after forming the first source-drain metal layer.
  • Figures 14A to 14C take a test circuit as an example, and the equivalent circuit diagram of the test circuit is shown in Figure 13.
  • the test circuit may include a first test transistor CT1, a second test transistor CT2, and a third test transistor CT3.
  • the three test transistors are arranged sequentially along the second direction Y, and are dislocated in the first direction X.
  • the first to third test transistors CT1 to CT3 may be arranged in a ladder shape.
  • the first active layer 421 of the first test transistor CT1 , the second active layer 422 of the second test transistor CT2 , and the third active layer 422 of the third test transistor CT3 may all be rectangular.
  • the first active layer 421, the second active layer 422 and the third active layer 423 may be arranged in a ladder shape.
  • the first gate 424 of the first test transistor CT1 , the second gate of the second test transistor CT2 , and the third gate of the third test transistor CT3 may be integrated. structure.
  • the first gate metal layer of the test circuit may include: first data connection lines 23a and 23c
  • the second gate metal layer of the test circuit may include: the first data connection line 23b, and the second data connection lines 461, 462, and 463.
  • the first data connection lines 23a, 23b and 23c may be located on a side of the active layer of the three test transistors close to the display area, and at least part of the line segments may extend toward the display area side along the second direction Y to communicate with the data in the display area. Wire connection.
  • the second data connection lines 461, 462 and 463 may be located on a side of the active layer of the three test transistors away from the display area, and may extend along the second direction Y to a side away from the display area so as to be electrically connected to the test data lines.
  • the first data connection lines 23a, 23b, and 23c may be arranged in sequence along the first direction X
  • the second data connection lines 461, 462, and 463 may be arranged in sequence along the first direction X.
  • the third insulation layer in the second frame region may be provided with a plurality of via holes, which may include, for example, the seventy-first via hole V71 to the eighty-sixth via hole V86.
  • the third insulating layer, the second insulating layer and the first insulating layer in the seventy-first via hole V71 to the seventy-sixth via hole V76 can be removed, exposing the surface of the active layer of the three test transistors.
  • the third insulating layer and the second insulating layer in the seventy-seventh via hole V77 to the seventy-ninth via hole V79 can be removed, exposing the surface of the first gate metal layer of the test circuit.
  • the third insulating layer in the eighty-sixth via hole V80 to the eighty-sixth via hole V86 can be removed, exposing the surface of the second gate metal layer of the test circuit.
  • the first source and drain metal layer of the test circuit may include: a test control line 620 , a first test data line 621 , a second test data line 622 , and a third test data line. 623, and the first and second poles of the three test transistors.
  • a third power line VGH and a fourth power line VGL may be provided on a side of the third test data line 623 close to the active layer of the three test transistors.
  • the test control line 620 may be electrically connected to the gate 424 of the first test transistor CT1 through the seventy-seventh via V77.
  • the first pole 471 of the first test transistor CT1 can be electrically connected to the first active layer 421 through the 71st via hole V71, and can also be electrically connected to the first data connection line 23a through the 78th via hole V78.
  • the second electrode 472 of the first test transistor CT1 can be electrically connected to the first active layer 421 through the seventy-fourth via hole V74, and can also be electrically connected to the second data connection line 461 through the eighty-first via hole V81.
  • the second data connection line 461 may be electrically connected to the first test data line 621 through the 82nd via V82.
  • the first pole 473 of the second test transistor CT2 can be electrically connected to the second active layer 422 through the seventy-second via hole V72, and can also be electrically connected to the first data connection line 23b through the eightieth via hole V80.
  • the second pole 474 of the second test transistor CT2 can be electrically connected to the second active layer 422 through the seventy-fifth via hole V75, and can also be electrically connected to the second data connection line 462 through the eighty-third via hole V83.
  • the second data connection line 462 may be electrically connected to the second test data line 622 through the eighty-fourth via hole V84.
  • the first pole 475 of the third test transistor CT3 can be electrically connected to the third active layer 423 through the seventy-third via hole V73, and can also be electrically connected to the first data connection line 23c through the seventy-ninth via hole V79.
  • the second electrode 476 of the third test transistor CT3 can be electrically connected to the third active layer 423 through the seventy-sixth via hole V76, and can also be electrically connected to the second data connection line 463 through the eighty-fifth via hole V85.
  • the second data connection line 463 may be electrically connected to the third test data line 623 through the eighty-sixth via V86.
  • the plurality of first data connection lines can be divided into two groups, respectively located on the first gate metal layer and the second gate metal layer, and the two groups of first data connection lines can be spaced apart along the first direction, so that The gap between adjacent first data connection lines can be reduced and the transmission effect can be ensured.
  • the plurality of first data connection lines may all be located on the first gate metal layer, because the parasitic capacitance generated by the overlap of the first gate metal layer and the first source-drain metal layer per unit area is smaller than that of the second gate metal layer. By arranging the first data connection line on the first gate metal layer, the parasitic capacitance generated by the unit area overlapping with the first source-drain metal layer can be effectively reduced, thereby reducing the load and optimizing the test effect.
  • FIG. 15 is a partial schematic diagram of a second corner area according to at least one embodiment of the present disclosure.
  • the driving units 431 of the gate driving circuit may be disposed in the third frame area and the second corner area, and are sequentially arranged along the edge extension direction of the display area.
  • the test circuits 42 may be located in the second frame area and arranged sequentially along the first direction X.
  • the test circuit 42 near the junction of the second frame area and the second corner area may be electrically connected to a column of pixel circuits in the left edge area of the display area through the arc-shaped first data connection line 23 .
  • a third electrostatic discharge circuit 33 may also be provided in the second corner area.
  • the third electrostatic discharge circuit 33 may be located on a side of the driving unit 431 close to the junction of the second corner area and the second frame area.
  • the third electrostatic discharge circuit 33 may be electrically connected to the driving signal line extending to the second corner area to discharge static electricity from the driving signal line.
  • test circuit is not arranged in the second corner area and the third corner area, which can increase the arrangement space of the driving unit 431 in the corner area, and can make the driving unit move closer to the display area side, thereby achieving a narrow frame design.
  • FIG. 16 is a partially enlarged schematic diagram of area A2 in FIG. 3 .
  • the multiplexed data line 610 electrically connected to the first electrostatic discharge circuit may extend toward the signal access area side. Since the number of sub-pixels connected to the data lines in the middle area and the left and right edge areas of the display area is different, compensation for the corresponding data lines can be achieved by connecting compensation resistors in series to the partial multiplexed data lines 342 .
  • the compensation resistor may be traced in a snake shape. Among them, the serpentine trace is a bending curve.
  • the multiplexed data line 342 may also be electrically connected to the compensation resistor through the second connection line 342 .
  • the compensation resistor electrically connected to the multiplexed data line 610 may be located in the packaging area as the second packaging glue base.
  • the first encapsulating glue base and the second encapsulating glue base may be arranged sequentially along the first direction X.
  • the compensation resistor as the second encapsulant base, the contact area between the encapsulant and the encapsulant base can be increased, thereby improving the encapsulation capability and achieving better water and oxygen barrier properties and sealing effects, making the encapsulant (for example, Frit glue ) will have better curing and encapsulating effects.
  • FIG. 17 is another schematic diagram of a display panel according to at least one embodiment of the present disclosure.
  • the display panel may include a display substrate.
  • the display substrate may include: a display area AA, and a frame area located around the display area AA.
  • the frame area may include a first frame area B1 located on one side of the display area AA and remaining frame areas B20 located on other sides.
  • the display substrate may be circular or oval.
  • FIG. 18 is a partially enlarged schematic diagram of area A3 in FIG. 17 .
  • the multiplexing circuit 41 , the first electrostatic discharge circuit 31 and the second electrostatic discharge circuit 32 may be located in the frame area.
  • the second electrostatic discharge circuit 32 may extend along the second direction Y.
  • multiple multiplexing circuits 41 may be arranged side by side along the first direction X.
  • the multiplexing circuits may be arranged in a ladder shape along the edge extension direction of the display area AA.
  • the gate driving circuit may include a plurality of cascaded driving units 431.
  • the plurality of driving units 431 may be arranged in a ladder shape along the edge extension direction of the display area.
  • a plurality of first electrostatic discharge circuits 31 may be arranged side by side along the first direction X.
  • a plurality of first electrostatic discharge circuits 31 may be arranged along the edge extension direction of the display area AA. Step-like arrangement.
  • the second electrostatic discharge circuit 32 may be located in the first frame area B1 or the remaining frame area B20, and the second electrostatic discharge circuit 32 may be interspersed between the first electrostatic discharge circuits 31.
  • a plurality of discharge transistors of the first electrostatic discharge circuit 31 may be arranged side by side along the first direction X, and a plurality of discharge transistors of the second electrostatic discharge circuit 32 may be arranged sequentially along the second direction Y.
  • this embodiment is not limited to this.
  • the circuit arrangement can be optimized, which is beneficial to realizing a narrow frame design.
  • the structure of the display substrate of this exemplary embodiment is only an exemplary illustration. In some exemplary embodiments, the corresponding structure may be changed and the patterning process may be increased or decreased according to actual needs.
  • the display area may be provided with a first source-drain metal layer and a second source-drain metal layer.
  • the first source-drain metal layer may include a source electrode and a drain electrode of a transistor
  • the second source-drain metal layer may include a light-emitting element and a leakage current of the transistor. connecting electrodes between poles.
  • this embodiment is not limited to this.
  • An embodiment of the present disclosure also provides a display device, including the display panel of the foregoing embodiment.
  • FIG. 19 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • the display panel 910 may be an OLED display panel.
  • the display device 91 may be: an OLED display device, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator, or any other product or component with a display function.
  • this embodiment is not limited to this.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示基板，包括：衬底、位于衬底上的多条数据线、多个多路复用电路、多条复用数据线、多个第一静电释放电路、多个第二静电释放电路、以及多条第一信号线。多个多路复用电路沿显示区域的边缘依次排布。多个多路复用电路与多条复用数据线和多条数据线电连接。多个第一静电释放电路与多条复用数据线电连接，多个第二静电释放电路与多条第一信号线电连接。多个第一静电释放电路和多个第二静电释放电路位于多个多路复用电路远离显示区域的一侧，且多个第二静电释放电路穿插排布在多个第一静电释放电路中。

Description

显示基板、显示面板及显示装置
本申请要求于2022年8月30日提交中国专利局、申请号为202211048005.2、发明名称为“显示基板、显示面板及显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板、显示面板及显示装置。
背景技术
有机发光二极管(OLED，Organic Light Emitting Diode)和量子点发光二极管(QLED，Quantum-dot Light Emitting Diode)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开至少一实施例提供一种显示基板、显示面板及显示装置。
一方面，本公开实施例提供一种显示基板，包括：显示区域以及位于所述显示区域周围的边框区域。显示基板包括衬底、位于显示区域的多条数据线、位于边框区域的多个多路复用电路、多条复用数据线、多个第一静电释放电路、多个第二静电释放电路、以及多条第一信号线。多个多路复用电路沿显示区域的边缘依次排布。多个多路复用电路与多条复用数据线和多条数据线电连接。多个第一静电释放电路与多条复用数据线电连接，多个第二静电释放电路与多条第一信号线电连接。多个第一静电释放电路和多个第二静电释放电路位于多个多路复用电路远离显示区域的一侧，且多个第二静电释放电路穿插排布在多个第一静电释放电路中。
在一些示例性实施方式中，所述多个第二静电释放电路中的至少一个位于所述多个第一静电释放电路远离所述显示区域的一侧。
在一些示例性实施方式中，所述边框区域包括：沿第二方向位于所述显示区域一侧的第一边框区域；所述多个多路复用电路位于所述第一边框区域，且沿第一方向并排排布，所述第一方向与所述第二方向交叉。
在一些示例性实施方式中，所述多路复用电路通过多条数据扇出线与所述显示区域的多条数据线电连接，所述多条数据扇出线为同层结构。
在一些示例性实施方式中，所述显示基板具有第一中线，所述第一中线平行于所述第二方向；所述多个第二静电释放电路位于所述第一边框区域内靠近所述第一中线的区域以及所述第一边框区域内远离所述第一中线的边缘区域。
在一些示例性实施方式中，所述边框区域还包括：沿所述第二方向位于所述显示区域远离所述第一边框区域一侧的第二边框区域。所述显示基板还包括：位于所述第二边框区域的多个测试电路，所述多个测试电路沿所述第一方向并排排布。
在一些示例性实施方式中，所述边框区域还包括：沿所述第一方向位于所述显示区域 相对两侧的第三边框区域和第四边框区域、连接所述第一边框区域和所述第三边框区域的第一拐角区域、连接所述第三边框区域和所述第二边框区域的第二拐角区域、连接所述第二边框区域和第四边框区域的第三拐角区域、以及连接所述第四边框区域和第一边框区域的第四拐角区域。所述显示基板还包括：栅驱动电路，所述栅驱动电路位于所述第三边框区域、所述第四边框区域、所述第一拐角区域、所述第二拐角区域、所述第三拐角区域以及所述第四拐角区域。
在一些示例性实施方式中，靠近所述第一拐角区域和所述第四拐角区域的多路复用电路通过弧形的数据扇出线与所述显示区域的多条数据线电连接。
在一些示例性实施方式中，靠近所述第二拐角区域和所述第三拐角区域的测试电路通过弧形的数据连接线与所述显示区域的多条数据线电连接。
在一些示例性实施方式中，所述显示基板还包括：位于所述边框区域的第一电源线，所述第一电源线至少包括：位于所述第一边框区域内的第一子电源线、第二子电源线和第三子电源线，所述第一子电源线、所述第二子电源线和所述第三子电源线均沿所述第二方向延伸；所述多个多路复用电路在所述第一方向上被所述第二子电源线隔开。
在一些示例性实施方式中，所述第一电源线还包括：位于所述第一边框区域内的第四子电源线和第五子电源线，所述第四子电源线和第五子电源线均沿所述第一方向延伸，且所述第四子电源线位于所述第五子电源线靠近所述显示区域的一侧，所述第四子电源线和所述第五子电源线均与所述第一子电源线、第二子电源线和第三子电源线电连接；所述多个多路复用电路、所述多个第一静电释放电路和多个第二静电释放电路位于所述第四子电源线和第五子电源线之间。
在一些示例性实施方式中，所述多条复用数据线中的至少一条与补偿电阻电连接，所述补偿电阻位于所述第一静电释放电路远离所述显示区域的一侧。所述第一边框区域至少包括：周边电路区、位于周边电路区远离显示区域一侧的信号接入区、以及位于所述周边电路区和信号接入区之间的封装区，所述补偿电阻位于所述封装区，并作为封装基底。
在一些示例性实施方式中，所述第一静电释放电路包括的多个释放晶体管的排布方向与所述第二静电释放电路包括的多个释放晶体管的排布方向互为反方向。
在一些示例性实施方式中，所述多条第一信号线包括：多条复用控制线以及多条驱动信号线。
另一方面，本公开实施例提供一种显示面板，包括如上所述的显示基板，以及设置于显示基板的显示区域的发光元件，所述发光元件阵列排布。
另一方面，本公开实施例提供一种显示装置，包括如上所述的显示面板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开至少一实施例的显示面板的示意图；
图2为本公开至少一实施例的显示区域的局部剖面结构示意图；
图3为本公开至少一实施例的边框区域的局部示意图；
图4为图3中区域A1的局部放大示意图；
图5为本公开至少一实施例的多路复用电路的等效电路图；
图6A为本公开至少一实施例的多路复用电路的结构示意图；
图6B为图6A中形成第二栅金属层后的多路复用电路的示意图；
图6C为图6A中形成第三绝缘层后的多路复用电路的示意图；
图7为本公开至少一实施例的静电释放电路的等效电路图；
图8A为本公开至少一实施例的静电释放电路的结构示意图；
图8B为图8A中形成第二栅金属层后的静电释放电路的示意图；
图8C为图8A中形成第三绝缘层后的静电释放电路的示意图；
图9A为本公开至少一实施例的静电释放电路的另一结构示意图；
图9B为图9A中形成第二栅金属层后的静电释放电路的示意图；
图10为本公开至少一实施例的第一拐角区域的局部示意图；
图11为本公开至少一实施例的第一拐角区域的封装走线的局部示意图；
图12为图11中沿Q-Q’方向的局部剖面示意图；
图13为本公开至少一实施例的测试电路的等效电路图；
图14A为本公开至少一实施例的测试电路的结构示意图；
图14B为图14A中形成第二栅金属层后的测试电路的示意图；
图14C为图14A中形成第三绝缘层后的测试电路的示意图；
图15为本公开至少一实施例的第二拐角区域的局部示意图；
图16为图3中区域A2的局部放大示意图；
图17为本公开至少一实施例的显示面板的另一示意图；
图18为图17中区域A3的局部放大示意图；
图19为本公开至少一实施例的显示装置的示意图。
详述
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水 平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，晶体管是指至少包括栅极(栅电极)、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。另外，栅极还可以称为控制极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，圆形、椭圆形、三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似圆形、近似椭圆形、近似三角形、近似矩形、近似梯形、近似五边形或近似六边形等，可以存在公差导致的一些小变形，例如可以存在导角、弧边以及变形等。
本说明书中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本公开中，“大致相同”是指数值相差10％以内的情况。
在本说明书中，A沿着B方向延伸是指，A可以包括主体部分和与主体部分连接的次要部分，主体部分是线、线段或条形状体，主体部分沿着B方向伸展，且主体部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。本说明书中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。
本说明书中所说的“A和B为同层结构”是指，A和B通过同一次构图工艺同时形成。“相同层”不总是意味着层的厚度或层的高度在截面图中是相同的。“A的正投影包含B的正投影”是指，B的正投影落入A的正投影范围内，或者A的正投影覆盖B的正投影。
为了更好地满足人们对于各种功能的需求及更好的屏幕体验(比如，具有超高屏占比的显示屏)，窄边框的显示屏设计逐渐成为显示设备的主流形态。然而，在一些实现方式中的显示面板内的部分信号线和电路的布局方式使得显示面板无法实现窄边框。
本公开实施例提供一种显示基板，包括：显示区域以及位于显示区域周围的边框区域。显示基板包括：衬底、位于衬底上的多条数据线、多个多路复用电路、多条复用数据线、 多个第一静电释放电路、多个第二静电释放电路、以及多条第一信号线。多条数据线位于显示区域，配置为所述显示区域的像素提供数据信号。多个多路复用电路、多条复用数据线、多个第一静电释放电路、多个第二静电释放电路、以及多条第一信号线位于所述边框区域。多个多路复用电路沿显示区域的边缘依次排布。多个多路复用电路与多条复用数据线和多条数据线电连接。多个第一静电释放电路与多条复用数据线电连接，多个第二静电释放电路与多条第一信号线电连接。多个第一静电释放电路和多个第二静电释放电路位于多个多路复用电路远离显示区域的一侧，且多个第二静电释放电路穿插排布在多个第一静电释放电路中。
本实施例提供的显示基板，通过优化第二静电释放电路的设置位置，可以减小第二静电释放电路占用的排布空间，从而有利于实现显示基板的窄边框。
在一些示例性实施方式中，边框区域可以包括：沿第二方向位于显示区域一侧的第一边框区域。多个多路复用电路位于第一边框区域，且沿第一方向并排排布，第一方向与第二方向交叉。在本示例中，通过将多路复用电路沿第一方向并排排布在第一边框区域，可以减少多路复用电路占用的排布空间，从而有利于实现显示基板的窄边框。
在一些示例性实施方式中，显示基板可以具有第一中线，第一中线可以平行于第二方向。多个第二静电释放电路可以位于第一边框区域内靠近第一中线的区域以及第一边框区域内远离第一中线的边缘区域。在一些示例中，显示基板以第一中线为对称轴对称分布。本示例的第二静电释放电路的排布方式有利于对应走线的静电释放。
在一些示例性实施方式中，边框区域还可以包括：沿第二方向位于显示区域远离第一边框区域一侧的第二边框区域。显示基板还可以包括：位于第二边框区域的多个测试电路，多个测试电路可以沿第一方向并排排布。在本示例中，通过将测试电路沿第一方向并排排布在第二边框区域，可以减少测试电路占用的排布空间，从而有利于实现显示基板的窄边框。
在一些示例性实施方式中，边框区域还可以包括：沿第一方向位于显示区域相对两侧的第三边框区域和第四边框区域、连接第一边框区域和第三边框区域的第一拐角区域、连接第三边框区域和第二边框区域的第二拐角区域、连接第二边框区域和第四边框区域的第三拐角区域、以及连接第四边框区域和第一边框区域的第四拐角区域。显示基板还可以包括：栅驱动电路，栅驱动电路可以位于第三边框区域、第四边框区域、第一拐角区域、第二拐角区域、第三拐角区域以及第四拐角区域。在本示例中，栅驱动电路可以设置在多个拐角区域，测试电路和多路复用电路没有设置在拐角区域，可以有利于减小拐角区域的尺寸，有利于拐角区域窄化。
下面通过一些示例对本实施例的方案进行举例说明。
图1为本公开至少一实施例的显示面板的示意图。在一些示例中，显示面板可以为包括线性边的闭合多边形，比如可以为矩形倒圆角形状。例如，当显示面板具有线性边时，显示面板的至少一些拐角可以为曲线。当显示面板具有矩形形状时，在相邻的线性边彼此交汇处的部分可以采用具有预定曲率的曲线代替。其中，可以根据曲线的位置不同来设定曲率。例如，可以根据曲线开始的位置、曲线的长度等来改变曲率。然而，本实施例对此并不限定。例如，显示面板可以为包括弯曲边的圆形或椭圆形、或者包括线性边和弯曲边的半圆形或半椭圆形等。
在一些示例中，如图1所示，显示面板可以包括显示基板。显示基板可以包括：显示区域AA和位于显示区域AA周边的边框区域。例如，显示区域AA可以包括：在第二方向Y上相对设置的第一边缘(下边缘)和第二边缘(上边缘)，以及在第一方向X上相 对设置的第三边缘(左边缘)和第四边缘(右边缘)。第一边缘和第二边缘可以为相互平行的线性边，第三边缘和第四边缘可以为相互平行的线性边。相邻线性边之间可以通过弯曲边缘连接。
在一些示例中，如图1所示，边框区域可以包括：在第二方向Y上相对设置的第一边框区域(下边框)B1和第二边框区域(上边框)B2，在第一方向X上相对设置的第三边框区域(左边框)B3和第四边框区域(右边框)B4。第一边框区域B1与显示区域AA的第一边缘相邻，第二边框区域B2与显示区域AA的第二边缘相邻，第三边框区域B3与显示区域AA的第三边缘相邻，第四边框区域B4与显示区域AA的第四边缘相邻。第一边框区域B1可以通过第一拐角区域C1和第三边框区域B3连通，还可以通过第四拐角区域C4和第四边框区域B4连通。第二边框区域B2可以通过第二拐角区域C2和第三边框区域B3连通，还可以通过第三拐角区域C3和第四边框区域B4连通。第一拐角区域C1至第四拐角区域C4各自与显示区域AA的弧形边缘对应。第一拐角区域C1至第四拐角区域C4的远离显示区域AA一侧的边缘可以均为弯曲边缘。
在一些示例中，如图1所示，显示基板的显示区域AA至少可以包括多个像素电路、多条栅线以及多条数据线。显示面板还可以包括：位于显示基板的显示区域AA的发光元件(即子像素)Px。发光元件Px可以阵列排布。多条栅线可以沿第一方向X延伸，多条数据线可以沿第二方向Y延伸。多条栅线和多条数据线在衬底上的正投影可以交叉形成多个电路区域，每个电路区域内可以设置一个像素电路。多条数据线与多个像素电路电连接，多条数据线可以被配置为向多个像素电路提供数据信号。多条栅线与多个像素电路电连接，多条栅线可以被配置为向多个像素电路提供栅极控制信号。在一些示例中，栅极控制信号可以包括扫描信号，或者可以包括扫描信号和发光控制信号。
在一些示例中，如图1所示，第一方向X可以是显示区域AA中栅线的延伸方向(子像素的行方向)，第二方向Y可以是显示区域AA中数据线的延伸方向(子像素的列方向)。第一方向X和第二方向Y可以相互垂直。
在一些示例中，显示区域AA的一个像素单元可以包括三个子像素，三个子像素分别为红色子像素、绿色子像素和蓝色子像素。然而，本实施例对此并不限定。在一些示例中，一个像素单元可以包括四个子像素，四个子像素分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。
在一些示例中，子像素的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列；一个像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形(Square)方式排列。然而，本实施例对此并不限定。
在一些示例中，像素电路可以配置为驱动所连接的发光元件。像素电路可以包括多个晶体管和至少一个电容。例如，像素电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。其中，上述电路结构中的T指的是薄膜晶体管，C指的是电容，T前面的数字代表电路中薄膜晶体管的数量，C前面的数字代表电路中电容的数量。在一些示例中，像素电路中的多个晶体管可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在另一些示例中，像素电路中的多个晶体管可以包括P型晶体管和N型晶体管。
在一些示例中，像素电路中的多个晶体管可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧 化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示面板上，即LTPS+Oxide(简称LTPO)显示面板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在一些示例中，发光元件可以是发光二极管(LED，Light Emitting Diode)、有机发光二极管(OLED，Organic Light Emitting Diode)、量子点发光二极管(QLED，Quantum Dot Light Emitting Diodes)、微LED(包括：mini-LED或micro-LED)等中的任一者。例如，发光元件可以为OLED，发光元件在其对应的像素电路的驱动下可以发出红光、绿光、蓝光、或者白光等。发光元件发光的颜色可根据需要而定。在一些示例中，发光元件可以包括：阳极、阴极以及位于阳极和阴极之间的有机发光层。发光元件的阳极可以与对应的像素电路电连接。然而，本实施例对此并不限定。
图2为本公开至少一实施例的显示区域的局部剖面结构示意图。图2中示意了显示面板的三个子像素的结构。在一些示例中，如图2所示，在垂直于显示基板的方向上，显示面板可以包括：衬底101、以及依次设置在衬底101上的电路结构层102、发光结构层103、封装结构层104以及封装盖板200。封装盖板200例如可以为玻璃盖板。在一些可能的实现方式中，显示面板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在一些示例中，衬底101可以为刚性基底，例如玻璃基底。然而，本实施例对此并不限定。例如，衬底可以为柔性基底，例如由树脂等绝缘材料制备。另外，衬底可以为单层结构或多层结构。当衬底为多层结构时，例如氮化硅、氧化硅和氮氧化硅的无机材料可以以单层或多层置于多个层之间。
在一些示例中，电路结构层102可以包括构成像素电路的多个晶体管和存储电容，图2中以每个像素电路包括的一个晶体管和一个存储电容为例进行示意。在一些可能的实现方式中，电路结构层102可以包括：设置在衬底101上的有源层；覆盖有源层的第一绝缘层11；设置在第一绝缘层11上的第一栅金属层(例如包括栅电极和第一电容电极)；覆盖第一栅金属层的第二绝缘层12；设置在第二绝缘层12上的第二栅金属层(例如包括第二电容电极)；覆盖第二栅金属层的第三绝缘层13，第一绝缘层11、第二绝缘层12和第三绝缘层13上开设有过孔，过孔暴露出有源层；设置在第三绝缘层13上的第一源漏金属层(例如包括晶体管的源电极和漏电极)，源电极和漏电极可以分别通过过孔与有源层连接；覆盖前述结构的第一平坦层14，第一平坦层14上开设有过孔，过孔暴露出漏电极。有源层、栅电极、源电极和漏电极可以组成晶体管105，第一电容电极和第二电容电极可以组成存储电容106。
在一些示例中，如图2所示，发光结构层103可以包括阳极层、像素定义层、有机发光层和阴极。阳极层可以包括发光元件的阳极，阳极可以设置在平坦层上，通过平坦层上开设的过孔与像素电路的晶体管的漏电极连接；像素定义层设置在阳极层和平坦层上，像素定义层上设置有像素开口，像素开口暴露出阳极；有机发光层至少部分设置在像素开口内，有机发光层与阳极连接；阴极设置在有机发光层上，阴极与有机发光层连接；有机发光层在阳极和阴极驱动下出射相应颜色的光线。
在一些示例中，如图2所示，封装结构层104可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可采用无机材料，第二封装层可采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层103。
在一些示例中，有机发光层可以至少包括在阳极上叠设的空穴注入层、空穴传输层、 发光层和空穴阻挡层。在一些示例中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，空穴阻挡层可以是连接在一起的共通层。然而，本实施例对此并不限定。
图3为本公开至少一实施例的边框区域的局部示意图。在一些示例中，如图1和图3所示，显示基板的第一边框区域(下边框)B1可以至少包括：位于显示区域AA一侧的信号接入区B13、以及位于信号接入区B13和显示区域AA之间的第一区域。第一区域可以包括：在第二方向Y上沿着远离显示区域AA的方向依次设置的周边电路区B11和封装区B12。封装区B12可以为涂覆或印刷封装胶的区域。在一些示例中，封装区B12可以为围绕显示区域AA的环形区域，从而有利于提高封装效果。
在一些示例中，如图1和图3所示，第一边框区域B1的周边电路区B11可以设置有多个多路复用电路41、多个第一静电释放(ESD)电路31、以及多个第二静电释放电路32。多个多路复用电路41可以沿第一方向X并排排布。第一静电释放电路31和第二静电释放电路32可以位于多路复用电路41远离显示区域AA的一侧。每个多路复用电路41可以与显示区域AA内的多条数据线电连接，可以被配置为使一个信号源为所述多条数据线提供数据信号。例如，每个多路复用电路41可以电连接一条复用数据线，通过复用数据线可以电连接提供数据信号的信号源。多条复用数据线与多个第一静电释放电路31可以一一对应电连接，以便释放静电。
在一些示例中，周边电路区B11还可以设置有多条数据扇出线。多条数据扇出线可以与显示区域AA的多条数据线电连接，并与周边电路区B11的多路复用电路41电连接。例如，多条数据扇出线可以与多条数据线一一对应电连接。数据线可以通过数据扇出线与多路复用电路41电连接。多条复用数据线可以延伸至信号接入区B13，并与信号接入区B13内的多个第一信号接入引脚对应电连接。在一些示例中，多条数据扇出线可以为同层结构，例如可以位于第一栅金属层。
在一些示例中，周边电路区B11还可以设置有多条第一信号线，多条第一信号线可以延伸至信号接入区B13，并与信号接入区B13内的多个第二信号接入引脚对应电连接。多条第一信号线还可以经过第一拐角区域C1延伸至第三边框区域B3和第二拐角区域C2，经过第四拐角区域C4延伸至第四边框区域B4和第三拐角区域C3。第一信号线可以与第二静电释放电路32电连接，以便释放静电。例如，第一信号线可以包括：多条复位控制线、多条驱动信号线、测试控制线以及测试数据线。
在一些示例中，如图1和图3所示，第三边框区域B3、第四边框区域B4、第一拐角区域C1至第四拐角区域C4可以设置栅驱动电路43。栅驱动电路43可以包括多个驱动单元。例如，每个驱动单元可以配置为给显示区域AA内的一行子像素提供扫描信号。多个驱动单元可以沿着显示区域AA的边缘延伸方向依次排布。驱动信号线可以与栅驱动电路43电连接，以便向栅驱动电路提供驱动信号(例如，时钟信号、起始信号、电源信号等)。
在一些示例中，如图1所示，第二边框区域B2可以设置多个测试电路42。多个测试电路42可以沿第一方向X依次排布。每个测试电路42可以与显示区域AA内的多条数据线电连接，可以被配置为向所述多条数据线提供测试数据信号。
在一些示例中，如图1和图3所示，边框区域还可以设置有第一电源线51和第二电源线52。第二电源线52可以位于第一电源线51远离显示区域AA的一侧。例如，第一电源线51和第二电源线52可以围绕显示区域AA。第二电源线52在第一边框区域B1内 的端部可以延伸至信号接入区B13，并与信号接入区B13内的第二电源信号接入引脚电连接。
在一些示例中，如图3所示，第一电源线51在第一边框区域B1可以包括：第一子电源线511、第二子电源线512、第三子电源线513、第四子电源线514和第五子电源线515。第一边框区域B1内的第一电源线51可以为一体结构。第一子电源线511、第二子电源线512和第三子电源线513可以均沿第二方向Y延伸。第四子电源线514可以沿第一方向X延伸，并分别与第一子电源线511、第二子电源线512和第三子电源线513电连接。第五子电源线515位于第四子电源线514远离显示区域的一侧。第五子电源线515可以具有沿第一方向X延伸的主体部、以及沿第二方向Y延伸的第一延伸部和第二延伸部。第一子电源线511、第二子电源线512、第三子电源线513和第四子电源线514可以位于周边电路区B11，第五子电源线515可以部分位于周边电路区B11，部分位于封装区B12。第一延伸部和第二延伸部可以从第一中线OO’的两侧延伸至信号接入区B13，并与信号接入区B13内的第一电源信号接入引脚对应电连接。
在一些示例中，如图1和图3所示，第四子电源线514可以与显示区域的多条第一电源连接线电连接，以便给显示区域的子像素提供第一电源信号。第二子电源线512可以位于第一中线OO’处，第一子电源线511和第三子电源线513可以位于第一中线OO’的相对两侧，第一子电源线511可以靠近第一拐角区域C1，第三子电源线513可以靠近第四拐角区域C4。第一子电路线511至第五子电源线515连接后围绕形成第一区域和第二区域，第一区域和第二区域位于第一中线OO’的相对两侧。多路复用电路41、第一静电释放电路31和第二静电释放电路32可以位于第一区域和第二区域内。第四子电源线514的一端可以沿显示区域的边缘延伸方向延伸至第一拐角区域C1和第三边框区域B3，另一端可以沿显示区域的边缘延伸方向延伸至第四拐角区域C4和第四边框区域B4。
在一些示例中，第五子电源线515的位于封装区B12内的部分、第二电源线52的位于封装区B12内的部分可以作为第一封装胶基底。第一封装胶基底上可以开设有多个开孔。通过在封装胶基底设置多个开孔，使得在封装胶基底上涂覆封装胶时，封装胶会漏入开孔内，相当于在封装胶基底的上面和内部都有封装胶，在通过激光进行封装胶熔融时，可以进一步提高封装胶的粘合强度，增强衬底基板和封装盖板的结合力，从而提高产品良率。
在本示例中，第一电源信号可以通过第一子电源线511、第二子电源线512和第三子电源线513向靠近显示区域AA一侧传输，采用分三路向显示区域传输的设计可以有效减小第一电源信号的衰减，可以改善传输至显示区域的第一电源信号存在从下到上以及从中间到两边的信号衰减而导致的电流衰减，可以提高显示区域的亮度均一性，改善显示效果。而且，第一电源线的设计方式有利于支持多路复用电路在第一边框区域沿第一方向依次排布。
图4为图3中区域A1的局部放大示意图。在一些示例中，如图4所示，在第一边框区域内，多个多路复用电路41、多个第一静电释放电路31和多个第二静电释放电路32可以位于第一电源线的第四子电源线514和第五子电源线515之间的区域内。第四子电源线514和第五子电源线515在衬底的正投影与多路复用电路41、第一静电释放电路31和第二静电释放电路32在衬底的正投影可以没有交叠。第一静电释放电路31和第二静电释放电路32可以位于多路复用电路41远离显示区域的一侧。多路复用电路41和第一静电释放电路31可以通过复用数据线电连接。第二静电释放电路32可以插设在多个第一静电释放电路31之间。例如，相邻两个第一静电释放电路31之间可以设置一个第二静电释放电路32。第二静电释放电路32可以位于第一静电释放电路31远离显示区域的一侧。
在一些示例中，如图4所示，第一边框区域还可以设置有多条复用控制线(例如第一复用控制线611至第六复用控制线616)、测试控制线620、第测试数据线(例如第一测试数据线621)、多条驱动信号线(例如包括：起始信号线631、第一时钟信号线632、第二时钟信号线633、驱动输出线634、第三电源线VGH和第四电源线VGL)。例如，第一测试数据线621和测试控制线620可以经过第一拐角区域、第三边框区域和第二拐角区域延伸至与第二边框区域内的测试电路电连接。起始信号线631、第一时钟信号线632、第二时钟信号线633、驱动输出线634、第三电源线VGH和第四电源线VGL可以与栅驱动电路电连接。起始信号线631可以配置为给栅驱动电路提供起始信号，第一时钟信号线632可以配置为给栅驱动电路提供第一时钟信号，第二时钟信号线633可以配置为给栅驱动电路提供第二时钟信号，第三电源线VGH可以配置为给栅驱动电路提供第三电源信号，第四电源线VGL可以配置为给栅驱动电路提供第四电源信号。例如，第三电源信号的电压值可以大于第四电源信号的电压值。栅驱动电路例如可以包括多个级联的驱动单元，起始信号线631可以与第一级驱动单元电连接，驱动输出线634可以与最后一级驱动单元电连接，配置为将最后一级驱动单元的输出信号传输给控制装置，以便检测栅驱动电路是否正常工作。复用控制线的至少部分线段可以沿第一方向X延伸，驱动信号线的至少部分线段可以沿第一方向X延伸。多条复用控制线、第一测试数据线621、测试控制线620、以及多条驱动信号线可以沿第二方向Y依次排布。多条复用控制线可以位于多路复用电路远离显示区域的一侧，多条驱动信号线可以位于第一静电释放电路和多条复用控制线之间。
在一些示例中，如图3和图4所示，靠近第一中线的多个第二静电释放电路32可以分别与多条复用控制线电连接，以释放多条复用控制线的静电。远离第一中线位于第一边框区域的边缘的多个第二静电释放电路32可以分别与多条驱动信号线电连接，以释放多条驱动信号线的静电。
图5为本公开至少一实施例的多路复用电路的等效电路图。在一些示例中，一个多路复用电路可以与a条复用控制线和一条复用数据线电连接，a可以为大于或等于2的正整数。图5中示意了两个多路复用电路，每个多路复用电路与六条复用控制线电连接。以图5中的一个多路复用电路为例，多路复用电路41可以包括六个复用晶体管MT。多个复用晶体管MT的栅极分别连接不同的复用控制线，即第一个复用晶体管的栅极连接第一复用控制线611，第二个复用晶体管的栅极连接第二复用控制线612，第三个复用晶体管的栅极连接第三复用控制线613，第四个复用晶体管的栅极连接第四复用控制线614，第五个复用晶体管的栅极连接第五复用控制线615，第六个复用晶体管的栅极连接第六复用控制线616。六个复用晶体管MT的第一极均连接同一个复用数据线(例如复用数据线610)。六个复用晶体管MT的第二极分别连接显示区域中不同的数据线DL，即第一个复用晶体管的第二极连接显示区域中的一个数据线DL，第二个复用晶体管的第二极连接显示区域中的另一个数据信号线DL……。在显示过程中，通过控制装置分时向六条复用控制线提供导通信号，使每个多路复用电路41中的六个复用晶体管MT分时导通，在任一复用晶体管MT导通时，复用数据线提供与导通的复用晶体管MT连接的数据线所需的数据信号，数据线将数据信号写入相应的子像素。
在一些示例中，通过设置多路复用电路，可以使一个信号源(例如驱动芯片的一个引脚)为多个数据线提供数据信号，可以大大降低实际的信号源数量，简化产品结构。在另一些示例中，一个多路复用电路41可以包括三个复用晶体管，控制三条数据线(即一拖三)。
图6A为本公开至少一实施例的多路复用电路的结构示意图。图6B为图6A中形成 第二栅金属层后的多路复用电路的示意图。图6C为图6A中形成第三绝缘层后的多路复用电路的示意图。图6A为形成第一源漏金属层后的多路复用电路的示意图。在本示例中，一个多路复用电路可以包括沿第一方向X依次排布的六个复用晶体管(例如，第一复用晶体管MT1至第六复用晶体管MT6)。
在一些示例中，如图6B所示，第一复用晶体管MT1的第一有源层401、第二复用晶体管MT2的第二有源层402、第三复用晶体管MT3的第三有源层403、第四复用晶体管MT4的第四有源层404、第五复用晶体管MT5的第五有源层405和第六复用晶体管MT6的第六有源层406在衬底的正投影可以为矩形，且可以沿第一方向X依次排布。
在一些示例中，如图6B所示，多路复用电路的第一栅金属层可以包括：多个复用晶体管的栅极以及多条数据扇出线21。第一复用晶体管MT1的第一栅极411、第二复用晶体管MT2的第二栅极412、第三复用晶体管MT3的第三栅极413、第四复用晶体管MT4的第四栅极414、第五复用晶体管MT5的第五栅极415和第六复用晶体管MT6的第六栅极416可以沿第一方向X依次排布，且沿第二方向Y的长度可以逐渐增加。多条数据扇出线21可以沿第一方向X依次排布。数据扇出线21可以向显示区域一侧延伸，以便与显示区域的数据线电连接。多条数据扇出线21可以与显示区域的多条数据线一一对应电连接。
在一些示例中，如图6B所示，多路复用电路的第二栅金属层可以包括：复用数据线610。复用数据线610可以位于复用晶体管的有源层远离显示区域的一侧。在另一些示例中，复用数据线610可以位于第一栅金属层。
在一些示例中，如图6C所示，第一边框区域的第三绝缘层可以开设有多个过孔，例如可以包括第一过孔V1至第二十五过孔V25。第一过孔V1至第十二过孔V12内的第三绝缘层和第二绝缘层可以被去掉，暴露出多路复用电路的第一栅金属层的表面。第十三过孔V13至第二十四过孔V24内的第三绝缘层、第二绝缘层和第一绝缘层可以被去掉，暴露出多路复用电路的多个复用晶体管的有源层的表面。第二十五过孔V25内的第三绝缘层可以被去掉，暴露出第二栅金属层的表面。
在一些示例中，如图6A所示，多路复用电路的第一源漏金属层可以包括：六个复用晶体管的第一极和第二极、第一复用控制线611至第六复用控制线616。第一复用晶体管MT1的第一极、第二复用晶体管MT2的第一极、第三复用晶体管MT3的第一极、第四复用晶体管MT4的第一极、第五复用晶体管MT5的第一极以及第六复用晶体管MT6的第一极可以为一体结构。例如，如图6A至图6C所示，第一复用晶体管MT1的第一极451可以通过竖排设置的六个第十三过孔V13与第一有源层401电连接，还可以通过竖排设置的六个第十五过孔V15与第二有源层402电连接，还可以通过竖排设置的六个第十七过孔V17与第三有源层403电连接，还可以通过竖排设置的六个第十九过孔V19与第四有源层404电连接，还可以通过竖排设置的六个第二十一过孔V21与第五有源层405电连接，还可以通过竖排设置的六个第二十三过孔V23与第六有源层406电连接，还可以通过横排设置的两个第二十五过孔V25与复用数据线610电连接。
在一些示例中，如图6A至图6C所示，第一复用晶体管MT1的第二极452可以通过竖排设置的六个第十四过孔V14与第一有源层401电连接，还可以通过第七过孔V7与第一条数据扇出线21电连接。第二复用晶体管MT2的第二极453可以通过竖排设置的六个第十六过孔V16与第二有源层402电连接，还可以通过第八过孔V8与第二条数据扇出线21电连接。第三复用晶体管MT3的第二极454可以通过竖排设置的六个第十八过孔V18与第三有源层403电连接，还可以通过第九过孔V9与第三条数据扇出线21电连接。第四复用晶体管MT4的第二极455可以通过竖排设置的六个第二十过孔V20与第四有源层 404电连接，还可以通过第十过孔V10与第四条数据扇出线21电连接。第五复用晶体管MT5的第二极456可以通过竖排设置的六个第二十二过孔V22与第五有源层405电连接，还可以通过第十一过孔V11与第五条数据扇出线21电连接。第六复用晶体管MT6的第二极457可以通过竖排设置的六个第二十四过孔V24与第六有源层406电连接，还可以通过第十二过孔V12与第六条数据扇出线21电连接。
在一些示例中，如图6A至图6C所示，第一复用晶体管MT1的第一栅极411可以通过横排设置的两个第一过孔V1与第一复位控制线611电连接。第二复用晶体管MT2的第二栅极412可以通过横排设置的两个第二过孔V2与第二复位控制线612电连接。第三复用晶体管MT3的第三栅极413可以通过横排设置的两个第三过孔V3与第三复位控制线613电连接。第四复用晶体管MT4的第四栅极414可以通过横排设置的两个第四过孔V4与第四复位控制线614电连接。第五复用晶体管MT5的第五栅极415可以通过横排设置的两个第五过孔V5与第五复位控制线615电连接。第六复用晶体管MT6的第六栅极416可以通过横排设置的两个第六过孔V6与第六复位控制线616电连接。
在本示例中，多路复用电路的复用晶体管可以通过位于第一栅金属层的数据扇出线21与显示区域的多条数据线电连接。由于第一栅金属层和第一源漏金属层交叠的单位面积产生的寄生电容小于第二栅金属层和第一源漏金属层交叠的单位面积产生的寄生电容，通过将数据扇出线设置在第一栅金属层，可以有效降低寄生电容，从而达到降低负载的作用，优化显示效果。
本示例中，第一拐角区域和第四拐角区域内不设置多路复用电路，多路复用电路全部设置在第一边框区域内。多个多路复用电路可以分成两组，设置在第二子电源线的相对两侧。通过将多个多路复用电路并排排布在第一边框区域，且相邻多路复用电路之间的间隔可以减少，可以减少多路复用电路的占用空间。在第一拐角区域和第四拐角区域内不设置多路复用电路，可以有利于栅驱动电路的驱动单元向显示区域一侧靠近设置，从而大大减小第一拐角区域和第四拐角区域的外边缘圆弧尺寸，使得第一拐角区域和第四拐角区域的外边缘位置可以更靠近显示区域，减小第一拐角区域和第四拐角区域的边框尺寸，有利于实现显示基板的窄边框设计。
图7为本公开至少一实施例的静电释放电路的等效电路图。在一些示例中，如图7所示，至少一个静电释放电路与一条第二信号线22连接，且配置为释放其连接的第二信号线22中的静电。例如，第一静电释放电路所连接的第二信号线可以为复用数据线，第二静电释放电路所连接的第二信号线可以为驱动信号线。一个静电释放电路可以包括：第一释放晶体管ST1至第四释放晶体管ST4。第一释放晶体管ST1的第一极与第四电源线VGL电连接，第一释放晶体管ST1的栅极和第二极与第二释放晶体管ST2的第一极电连接，第二释放晶体管ST2的栅极和第二极与静电释放电路对应的第二信号线22电连接，第三释放晶体管ST3的第一极与静电释放电路对应的第二信号线22电连接，第三释放晶体管ST3的栅极和第二极与第四释放晶体管ST4的第一极电连接，第四释放晶体管ST4的栅极和第二极与第三电源线VGH电连接。
在一种示例中，设置静电释放电路可以防止第二信号线中的静电积累而引起放电击穿导致损坏，以释放第二信号线中积累的静电，实现对第二信号线的保护。
在另一种示例中，静电释放电路可以包括两个释放晶体管，其中，每个释放晶体管的一极都和自身的栅极连接，从而形成等效的二极管连接；而两个“二极管”之间连接要保护的信号线，两个“二极管”的另外两端分别连接第三电源线VGH和第四电源线VGL。由此，当信号线中因积累正电荷出现瞬时高压(如100V)时，其中一个“二极管”导通，释放信号线中的正电荷；而当信号线中因积累负电荷出现瞬时低压(如-100V)时，另一个“二极 管”导通，释放信号线中的负电荷。
图8A为本公开至少一实施例的静电释放电路的结构示意图。图8B为图8A中形成第二栅金属层后的静电释放电路的示意图。图8C为图8A中形成第三绝缘层后的静电释放电路的示意图。图8A为形成第一源漏金属层后的静电释放电路的示意图。图8A至图8C中以两个第一静电释放电路和一个第二静电释放电路为例进行示意。第一静电释放电路和第二静电释放电路的等效电路图均如图7所示。例如，第一静电释放电路可以包括第一释放晶体管ST1a至第四释放晶体管ST4a，第二静电释放电路可以包括第一释放晶体管ST1b至第四释放晶体管ST4b。
在一些示例中，如图8A至图8B所示，第一静电释放电路的第一释放晶体管ST1a的第一有源层301、第二释放晶体管ST2a的第二有源层302、第三释放晶体管ST3a的第三有源层303和第四释放晶体管ST4a的第四有源层304在衬底的正投影可以为矩形，且可以沿第一方向X依次排布。其中，第一释放晶体管ST1a的第一有源层301、第二释放晶体管ST2a的第二有源层302可以为一体结构，第三释放晶体管ST3a的第三有源层303和第四释放晶体管ST4a的第四有源层304可以为一体结构。第二静电释放电路的第一释放晶体管ST1b的第一有源层305、第二释放晶体管ST2b的第二有源层306、第三释放晶体管ST3b的第三有源层307和第四释放晶体管ST4b的第四有源层308在衬底的正投影可以为矩形，且可以沿第一方向X依次排布。第二静电释放电路的四个释放晶体管的排布方向与第一静电释放电路的四个释放晶体管的排布方向可以互为反方向。其中，第一释放晶体管ST1b的第一有源层305、第二释放晶体管ST2b的第二有源层306可以为一体结构，第三释放晶体管ST3b的第三有源层307和第四释放晶体管ST4b的第四有源层308可以为一体结构。
在一些示例中，如图8A和图8B所示，静电释放电路的第一栅金属层还可以包括：第一静电释放电路的多个释放晶体管的栅极(例如，第一释放晶体管ST1a的栅极311、第二释放晶体管ST2a的栅极312、第三释放晶体管ST3a的栅极313和第四释放晶体管ST4a的栅极314)、第二静电释放电路的多个释放晶体管的栅极(例如，第一释放晶体管ST1b的栅极321、第二释放晶体管ST2b的栅极322、第三释放晶体管ST3b的栅极323和第四释放晶体管ST4b的栅极324)、第二连接线342和第三连接线343。第二连接线342的至少部分可以沿第二方向Y延伸，第三连接线343可以沿第二方向Y延伸。第一静电释放电路可以通过第二连接线342与复用数据线电连接，例如，第二连接线342可以位于第一栅金属层，并与位于第一栅金属层的复用数据线为一体结构，或者，第二连接线342可以位于第一栅金属层，并与位于第二栅金属层的复用数据线电连接。第二静电释放电路可以通过第三连接线343与一条驱动信号线电连接，例如，第三连接线343可以与驱动输出线634电连接。
在一些示例中，如图8A和图8B所示，静电释放电路的第二栅金属层还可以包括：第一连接线341。第一连接线341可以沿第二方向Y延伸。然而，本实施例对此并不限定。
在一些示例中，如图8C所示，第一边框区域的第三绝缘层可以开设有多个过孔，例如可以包括第三十一过孔V31至第五十六过孔V56。第三十一过孔V31至第四十二过孔V42内的第三绝缘层、第二绝缘层和第一绝缘层可以被去掉，暴露出静电释放电路的有源层的表面。第四十三过孔V43至第五十二过孔V52内的第三绝缘层和第二绝缘层可以被去掉，暴露出第一栅金属层的表面。第五十五过孔V55和第五十六过孔V56内的第三绝缘层可以被去掉，暴露出第二栅金属层的表面。
在一些示例中，如图8A所示，静电释放电路的第一源漏金属层可以包括：多个连接电极(例如，第一连接电极331至第九连接电极339)。第一连接电极331可以通过第三 十一过孔V31与第一静电释放电路的第一释放晶体管ST1a的第一有源层301，还可以通过第五十五过孔V55与第一连接线341电连接。第一连接线341可以通过第五十六过孔V56与第四电源线VGL电连接。第二连接电极332可以通过第四十三过孔V43与第一释放晶体管ST1a的栅极311电连接，还可以通过第三十二过孔V32与第二释放晶体管ST2a的第二有源层302电连接。第三连接电极333可以通过第四十四过孔V44与第二释放晶体管ST2a的栅极312电连接，还可以通过第三十三过孔V33与第二释放晶体管ST2a的第二有源层302电连接，还可以通过第四十五过孔V45与第二连接线342电连接，还可以通过第三十四过孔V34与第三释放晶体管ST3a的第三有源层303电连接。第四连接电极334可以通过第四十六过孔V46与第三释放晶体管ST3a的栅极313电连接，还可以通过第三十五过孔V35与第三释放晶体管ST3a的第三有源层303电连接。第五连接电极335可以通过第三十六过孔V36与第四释放晶体管ST4a的第四有源层304电连接，还可以通过第四十七过孔V47与第四释放晶体管ST4a的栅极314电连接，还可以通过第三十七过孔V37与第二静电释放电路的第四释放晶体管ST4b的第四有源层308电连接，还可以通过第四十八过孔V48与第四释放晶体管ST4b的栅极324电连接。第四释放晶体管ST4a的栅极314可以通过第五十三过孔V53与第三电源线VGH电连接。第六连接电极336可以通过第三十八过孔V38与第二静电释放电路的第四释放晶体管ST4b的第四有源层308电连接，还可以通过第四十九过孔V49与第三释放晶体管ST3b的栅极323电连接。第七连接电极337可以通过第三十九过孔V39与第三释放晶体管ST3b的第三有源层307电连接，还可以通过第五十过孔V50与第三连接线343电连接，还可以通过第四十过孔V40与第二释放晶体管ST2b的第二有源层306电连接，还可以通过第五十一过孔V51与第二释放晶体管ST2b的栅极322电连接。第八连接电极338可以通过第四十一过孔V41与第二释放晶体管ST2b的第二有源层306电连接，还可以通过第五十二过孔V52与第一释放晶体管ST1b的栅极321电连接。第九连接电极339可以通过第四十二过孔V42与第一释放晶体管ST1b的第一有源层305电连接，还可以与另一个第一静电释放电路的第一释放晶体管的第一极电连接。第三连接线343可以通过第五十四过孔V54与驱动输出线634电连接，以释放驱动输出线634上的静电。
图9A为本公开至少一实施例的静电释放电路的另一结构示意图。图9B为图9A中形成第二栅金属层后的静电释放电路的示意图。图9A为形成第一源漏金属层后的静电释放电路的示意图。本示例中，第一静电释放电路和第二静电释放电路可以沿第一方向X依次排布，并对齐。第二静电释放电路可以位于相邻两个第一静电释放电路之间。第二静电释放电路的第四释放晶体管ST4b的第四有源层308与相邻的一个第一静电释放电路的第四释放晶体管ST4a的第四有源层304可以为一体结构，第二静电释放电路的第一释放晶体管ST1b的第一有源层305与相邻的另一个第一静电释放电路的第一释放晶体管ST1a的第一有源层301可以为一体结构。关于本实施例的静电释放电路的其它结构可以参照前述实施例的说明，故于此不再赘述。
本示例中，将第二静电释放电路设置在第一静电释放电路之间，可以减少第二静电释放电路的占用空间，而且可以简化走线排布，可以极大地节省空间，有利于第一边框区域(即下边框)的窄化。
图10为本公开至少一实施例的第一拐角区域的局部示意图。在一些示例中，如图1所示，栅驱动电路可以包括多个级联的驱动单元431。驱动单元431可以设置在第三边框区域和第一拐角区域内，并沿着显示区域的边缘延伸方向依次排布。多路复用电路41、第一静电释放电路31和第二静电释放电路32可以位于第一边框区域。靠近第一边框区域与第一拐角区域交界处的多路复用电路41可以通过弧形的数据扇出线21与显示区域左侧边缘区域的一列像素电路电连接。第一边框区域的多条驱动信号线可以延伸至第一拐角区 域，并利用位于第一栅金属层的转接线进行转接，避免与第一子电源线511冲突。第四子电源线514靠近多路复用电路41一侧还可以设置初始信号线641。
在一些示例中，如图10所示，在第一拐角区域还可以设置第三静电释放电路33。第三静电释放电路33可以位于驱动单元431靠近第一拐角区域和第一边框区域的交界处的一侧。第三静电释放电路33可以与延伸至第一拐角区域的驱动信号线电连接，以释放所述驱动信号线的静电。然而，本实施例对此并不限定。例如，第一拐角区域可以不设置静电释放电路，以节省空间，有利于实现第一拐角区域的窄化。
在一些示例中，如图10所示，在第一拐角区域和第三边框区域还设置有第二电源线52和位于第二电源线52远离显示区域一侧的封装走线53。封装走线53和第二电源线52可以电连接。第二电源线52可以与封装走线53异层设置。例如，封装走线53可以位于第二电源线52靠近衬底的一侧。
图11为本公开至少一实施例的第一拐角区域的封装走线的局部示意图。图12为图11中沿Q-Q’方向的局部剖面示意图。在一些示例中，如图11所示，封装走线53可以开设有多个开孔530。开孔530在衬底的正投影例如可以为矩形。如图12所示，封装走线53可以位于第一栅金属层，第二电源线52可以位于第一源漏金属层。封装走线53靠近第二电源线52的边缘具有多个凸出部，所述多个凸出部可以通过第六十一过孔V61与第二电源线52电连接。第六十一过孔V61内的第二绝缘层12和第三绝缘层13可以被去除，暴露出第二电源线52的凸出部的表面。第二绝缘层12和第三绝缘层13上还可以设置有多个过孔阵列V62。设置在封装走线53上的开孔530在衬底101上的正投影可以覆盖过孔阵列V62在衬底101上的正投影。过孔阵列V62内可以填充封装胶201，以便于通过封装胶201实现封装盖板200的固定。
图13为本公开至少一实施例的测试电路的等效电路图。在一些示例中，测试电路可以包括b个测试晶体管，并可以与至少一个测试控制线和b条测试数据线电连接，b可以为大于或等于2的正整数。图13以一个测试控制线、三条测试数据线以及两个测试电路42(每个测试电路42包括三个测试晶体管CT)为例进行了示意。如图13所示，在同一个测试电路42的三个测试晶体管CT的栅极均连接同一个测试控制线620。三个测试晶体管CT的第一极分别连接不同的测试数据线，即第一个测试晶体管的第一极连接第一测试数据线621，第二个测试晶体管的第一极连接第二测试数据线622，第三个测试晶体管的第一极连接第三测试数据线623。三个测试晶体管CT的第二极分别连接显示区域中不同的数据线DL，即第一个测试晶体管的第二极连接一个数据线DL，第二个测试晶体管的第二极连接另一个数据线DL，第三个测试晶体管的第二极连接又一个数据线DL。这样，通过测试控制线620可以控制测试电路42中的三个测试晶体管CT的导通，可以控制不同的测试数据线的信号写入不同的数据线DL。在进行测试时，通过控制装置向测试控制线620提供导通信号，向多个测试数据线分别提供所需的测试数据信号，使显示区域中多个数据线获得测试数据信号，实现检测。在一些示例中，测试控制线620和第一测试数据线621可以从第一边框区域经过第一拐角区域、第三边框区域和第二拐角区域延伸至第二边框区域，第二测试数据线622和第三测试数据线623可以从第一边框区域经过第四拐角区域、第四边框区域和第三拐角区域延伸至第二边框区域。
在一些示例中，每条数据线连接的子像素颜色相同，测试时向同一颜色的子像素对应的数据线提供相同的测试数据信号，使这些子像素进行相同的显示，通过显示画面的颜色确定是否有发生不良的子像素，以及定位发生不良的子像素。
图14A为本公开至少一实施例的测试电路的结构示意图。图14B为图14A中形成第二栅金属层后的测试电路的示意图。图14C为图14A中形成第三绝缘层后的测试电路的 示意图。图14A为形成第一源漏金属层后的测试电路的示意图。图14A至图14C中以一个测试电路为例进行示意，测试电路的等效电路图如图13所示。例如，测试电路可以包括第一测试晶体管CT1、第二测试晶体管CT2和第三测试晶体管CT3。三个测试晶体管沿第二方向Y依次排布，且在第一方向X上存在错位。例如，第一测试晶体管CT1至第三测试晶体管CT3可以呈阶梯形排布。
在一些示例中，如图14A至图14B所示，第一测试晶体管CT1的第一有源层421、第二测试晶体管CT2的第二有源层422和第三测试晶体管CT3的第三有源层423在衬底的正投影可以均为矩形。第一有源层421、第二有源层422和第三有源层423可以呈阶梯形排布。
在一些示例中，如图14A和图14B所示，第一测试晶体管CT1的第一栅极424、第二测试晶体管CT2的第二栅极和第三测试晶体管CT3的第三栅极可以为一体结构。测试电路的第一栅金属层可以包括：第一数据连接线23a和23c，测试电路的第二栅金属层可以包括：第一数据连接线23b、以及第二数据连接线461、462和463。第一数据连接线23a、23b和23c可以位于三个测试晶体管的有源层靠近显示区域的一侧，且至少部分线段可以沿第二方向Y向显示区域一侧延伸，以便与显示区域的数据线电连接。第二数据连接线461、462和463可以位于三个测试晶体管的有源层远离显示区域的一侧，且可以沿第二方向Y向远离显示区域一侧延伸，以便与测试数据线电连接。第一数据连接线23a、23b和23c可以沿第一方向X依次排布，第二数据连接线461、462和463可以沿第一方向X依次排布。
在一些示例中，如图14C所示，第二边框区域的第三绝缘层可以开设有多个过孔，例如可以包括第七十一过孔V71至第八十六过孔V86。其中，第七十一过孔V71至第七十六过孔V76内的第三绝缘层、第二绝缘层和第一绝缘层可以被去掉，暴露出三个测试晶体管的有源层的表面。第七十七过孔V77至第七十九过孔V79内的第三绝缘层和第二绝缘层可以被去掉，暴露出测试电路的第一栅金属层的表面。第八十过孔V80至第八十六过孔V86内的第三绝缘层可以被去掉，暴露出测试电路的第二栅金属层的表面。
在一些示例中，如图14A至图14C所示，测试电路的第一源漏金属层可以包括：测试控制线620、第一测试数据线621、第二测试数据线622、第三测试数据线623、以及三个测试晶体管的第一极和第二极。第三测试数据线623靠近三个测试晶体管的有源层的一侧可以设置第三电源线VGH和第四电源线VGL。测试控制线620可以通过第七十七过孔V77与第一测试晶体管CT1的栅极424电连接。第一测试晶体管CT1的第一极471可以通过第七十一过孔V71与第一有源层421电连接，还可以通过第七十八过孔V78与第一数据连接线23a电连接。第一测试晶体管CT1的第二极472可以通过第七十四过孔V74与第一有源层421电连接，还可以通过第八十一过孔V81与第二数据连接线461电连接。第二数据连接线461可以通过第八十二过孔V82与第一测试数据线621电连接。第二测试晶体管CT2的第一极473可以通过第七十二过孔V72与第二有源层422电连接，还可以通过第八十过孔V80与第一数据连接线23b电连接。第二测试晶体管CT2的第二极474可以通过第七十五过孔V75与第二有源层422电连接，还可以通过第八十三过孔V83与第二数据连接线462电连接。第二数据连接线462可以通过第八十四过孔V84与第二测试数据线622电连接。第三测试晶体管CT3的第一极475可以通过第七十三过孔V73与第三有源层423电连接，还可以通过第七十九过孔V79与第一数据连接线23c电连接。第三测试晶体管CT3的第二极476可以通过第七十六过孔V76与第三有源层423电连接，还可以通过第八十五过孔V85与第二数据连接线463电连接。第二数据连接线463可以通过第八十六过孔V86与第三测试数据线623电连接。
在本示例中，多条第一数据连接线可以分为两组，分别位于第一栅金属层和第二栅金属层，且两组第一数据连接线可以沿第一方向间隔排布，从而可以减小相邻第一数据连接线之间的间隙，并确保传输效果。在另一些示例中，多条第一数据连接线可以均位于第一栅金属层，由于第一栅金属层和第一源漏金属层交叠的单位面积产生的寄生电容小于第二栅金属层和第一源漏金属层交叠的单位面积产生的寄生电容，通过将第一数据连接线设置在第一栅金属层，可以有效降低寄生电容，从而达到降低负载的作用，优化测试效果。
图15为本公开至少一实施例的第二拐角区域的局部示意图。在一些示例中，如图15所示，栅驱动电路的驱动单元431可以设置在第三边框区域和第二拐角区域，并沿着显示区域的边缘延伸方向依次排布。测试电路42可以位于第二边框区域，并沿第一方向X依次排布。靠近第二边框区域与第二拐角区域交界处的测试电路42可以通过弧形的第一数据连接线23与显示区域左侧边缘区域的一列像素电路电连接。
在一些示例中，如图15所示，在第二拐角区域还可以设置第三静电释放电路33。第三静电释放电路33可以位于驱动单元431靠近第二拐角区域和第二边框区域的交界处的一侧。第三静电释放电路33可以与延伸至第二拐角区域的驱动信号线电连接，以释放所述驱动信号线的静电。
本示例中，测试电路不设置在第二拐角区域和第三拐角区域，可以增大驱动单元431在拐角区域的排布空间，可以使得驱动单元向显示区域一侧靠近，从而实现窄边框设计。
图16为图3中区域A2的局部放大示意图。在一些示例中，如图16所示，与第一静电释放电路电连接的复用数据线610可以向信号接入区一侧延伸。由于显示区域内中间区域和左右边缘区域的数据线连接的子像素数目不同，可以通过给部分复用数据线342串联补偿电阻来实现给对应的数据线进行补偿。在一些示例中，补偿电阻可以为蛇形走线。其中，蛇形走线是一种弯折曲线。例如，走线一端沿一个方向延伸一段距离后，弯折迂回并向与该方向的相反方向延伸一段距离，再次弯折迂回而向该方向延伸，如此反复弯折迂回若干次，形成蛇形走线。在一些示例中，复用数据线342还可以通过第二连接线342与补偿电阻电连接。
在本示例中，复用数据线610电连接的补偿电阻可以位于封装区，作为第二封装胶基底。第一封装胶基底和第二封装胶基底可以沿第一方向X依次排布。本示例通过将补偿电阻作为第二封装胶基底，可以增加封装胶与封装胶基底的接触面积，从而提高封装能力，达到更好的水氧阻隔性和密封效果，使得封装胶(例如，Frit胶)的固化效果和封装效果会更好。
图17为本公开至少一实施例的显示面板的另一示意图。在一些示例中，如图17所示，显示面板可以包括显示基板。显示基板可以包括：显示区域AA、以及位于显示区域AA四周的边框区域。边框区域可以包括位于显示区域AA一侧的第一边框区域B1以及位于其余侧的其余边框区域B20。在本示例中，显示基板可以为圆形或椭圆形。
图18为图17中区域A3的局部放大示意图。在一些示例中，如图18所示，多路复用电路41、第一静电释放电路31和第二静电释放电路32可以位于边框区域。第二静电释放电路32可以沿第二方向Y延伸。在第一边框区域B1内，多个多路复用电路41可以沿第一方向X并排排布。在其余边框区域B20内，多路复用电路可以沿着显示区域AA的边缘延伸方向呈阶梯状排布。栅驱动电路可以包括多个级联的驱动单元431，在其余边框区域B20内，多个驱动单元431可以沿着显示区域的边缘延伸方向呈阶梯状排布。在第一边框区域B1内，多个第一静电释放电路31可以沿第一方向X并排排布，在其余边框区域B20内，多个第一静电释放电路31可以沿显示区域AA的边缘延伸方向呈阶梯状 排布。第二静电释放电路32可以位于第一边框区域B1或其余边框区域B20内，第二静电释放电路32可以穿插设置在第一静电释放电路31之间。例如，第一静电释放电路31的多个释放晶体管可以沿第一方向X并排排布，第二静电释放电路32的多个释放晶体可以沿第二方向Y依次排布。然而，本实施例对此并不限定。本示例通过将第二静电释放电路排布在第一静电释放电路之间，可以优化电路排布，有利于实现窄边框设计。
关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
本示例性实施例的显示基板的结构仅仅是一种示例性说明。在一些示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，显示区域可以设置第一源漏金属层和第二源漏金属层，第一源漏金属层可以包括晶体管的源电极和漏电极，第二源漏金属层可以包括发光元件和晶体管的漏电极之间的连接电极。然而，本实施例对此并不限定。
本公开实施例还提供一种显示装置，包括前述实施例的显示面板。
图19为本公开至少一实施例的显示装置的示意图。在一些示例中，如图19所示，显示面板910可以为OLED显示面板。显示装置91可以为：OLED显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。然而，本实施例对此并不限定。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (16)

  1. 一种显示基板，包括显示区域以及位于所述显示区域周围的边框区域，所述显示基板包括：
    衬底；
    位于所述衬底上的多条数据线，位于所述显示区域，所述多条数据线配置为给所述显示区域的像素提供数据信号；
    多个多路复用电路、多条复用数据线、多个第一静电释放电路、多个第二静电释放电路、以及多条第一信号线，位于所述边框区域；
    所述多个多路复用电路沿所述显示区域的边缘依次排布；所述多个多路复用电路与所述多条复用数据线和所述多条数据线电连接；所述多个第一静电释放电路与所述多条复用数据线电连接，所述多个第二静电释放电路与所述多条第一信号线电连接；
    所述多个第一静电释放电路和多个第二静电释放电路位于所述多个多路复用电路远离所述显示区域的一侧，且所述多个第二静电释放电路穿插排布在所述多个第一静电释放电路中。
  2. 根据权利要求1所述的显示基板，其中，所述多个第二静电释放电路中的至少一个位于所述多个第一静电释放电路远离所述显示区域的一侧。
  3. 根据权利要求1或2所述的显示基板，其中，所述边框区域包括：沿第二方向位于所述显示区域一侧的第一边框区域；所述多个多路复用电路位于所述第一边框区域，且沿第一方向并排排布，所述第一方向与所述第二方向交叉。
  4. 根据权利要求3所述的显示基板，其中，所述多路复用电路通过多条数据扇出线与所述显示区域的多条数据线电连接，所述多条数据扇出线为同层结构。
  5. 根据权利要求3或4所述的显示基板，其中，所述显示基板具有第一中线，所述第一中线平行于所述第二方向；所述多个第二静电释放电路位于所述第一边框区域内靠近所述第一中线的区域以及所述第一边框区域内远离所述第一中线的边缘区域。
  6. 根据权利要求3至5中任一项所述的显示基板，其中，所述边框区域还包括：沿所述第二方向位于所述显示区域远离所述第一边框区域一侧的第二边框区域；
    所述显示基板还包括：位于所述第二边框区域的多个测试电路，所述多个测试电路沿所述第一方向并排排布。
  7. 根据权利要求6所述的显示基板，其中，所述边框区域还包括：沿所述第一方向位于所述显示区域相对两侧的第三边框区域和第四边框区域、连接所述第一边框区域和所述第三边框区域的第一拐角区域、连接所述第三边框区域和所述第二边框区域的第二拐角区域、连接所述第二边框区域和第四边框区域的第三拐角区域、以及连接所述第四边框区域和第一边框区域的第四拐角区域；
    所述显示基板还包括：栅驱动电路，所述栅驱动电路位于所述第三边框区域、所述第四边框区域、所述第一拐角区域、所述第二拐角区域、所述第三拐角区域以及所述第四拐角区域。
  8. 根据权利要求7所述的显示基板，其中，靠近所述第一拐角区域和所述第四拐角区域的多路复用电路通过弧形的数据扇出线与所述显示区域的多条数据线电连接。
  9. 根据权利要求7所述的显示基板，其中，靠近所述第二拐角区域和所述第三拐角 区域的测试电路通过弧形的数据连接线与所述显示区域的多条数据线电连接。
  10. 根据权利要求3至9中任一项所述的显示基板，其中，所述显示基板还包括：位于所述边框区域的第一电源线，所述第一电源线至少包括：位于所述第一边框区域内的第一子电源线、第二子电源线和第三子电源线，所述第一子电源线、所述第二子电源线和所述第三子电源线均沿所述第二方向延伸；所述多个多路复用电路在所述第一方向上被所述第二子电源线隔开。
  11. 根据权利要求10所述的显示基板，其中，所述第一电源线还包括：位于所述第一边框区域内的第四子电源线和第五子电源线，所述第四子电源线和第五子电源线均沿所述第一方向延伸，且所述第四子电源线位于所述第五子电源线靠近所述显示区域的一侧，所述第四子电源线和所述第五子电源线均与所述第一子电源线、第二子电源线和第三子电源线电连接；所述多个多路复用电路、所述多个第一静电释放电路和多个第二静电释放电路位于所述第四子电源线和第五子电源线之间。
  12. 根据权利要求3至11中任一项所述的显示基板，其中，所述多条复用数据线中的至少一条与补偿电阻电连接，所述补偿电阻位于所述第一静电释放电路远离所述显示区域的一侧；
    所述第一边框区域至少包括：周边电路区、位于周边电路区远离显示区域一侧的信号接入区、以及位于所述周边电路区和信号接入区之间的封装区，所述补偿电阻位于所述封装区，并作为封装基底。
  13. 根据权利要求1至12中任一项所述的显示基板，其中，所述第一静电释放电路包括的多个释放晶体管的排布方向与所述第二静电释放电路包括的多个释放晶体管的排布方向互为反方向。
  14. 根据权利要求1至13中任一项所述的显示基板，其中，所述多条第一信号线包括：多条复用控制线以及多条驱动信号线。
  15. 一种显示面板，包括如权利要求1至14中任一项所述的显示基板，及设置于显示基板的显示区域的发光元件，所述发光元件阵列排布。
  16. 一种显示装置，包括如权利要求15所述的显示面板。
PCT/CN2023/111733 2022-08-30 2023-08-08 显示基板、显示面板及显示装置 WO2024046054A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211048005.2 2022-08-30
CN202211048005.2A CN115294889B (zh) 2022-08-30 2022-08-30 显示基板、显示面板及显示装置

Publications (1)

Publication Number Publication Date
WO2024046054A1 true WO2024046054A1 (zh) 2024-03-07

Family

ID=83831767

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/111733 WO2024046054A1 (zh) 2022-08-30 2023-08-08 显示基板、显示面板及显示装置

Country Status (2)

Country Link
CN (1) CN115294889B (zh)
WO (1) WO2024046054A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115294889B (zh) * 2022-08-30 2023-11-21 京东方科技集团股份有限公司 显示基板、显示面板及显示装置
CN115835723A (zh) * 2022-12-08 2023-03-21 京东方科技集团股份有限公司 显示基板、显示装置
CN115802834A (zh) * 2022-12-23 2023-03-14 京东方科技集团股份有限公司 显示基板及显示装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108470522A (zh) * 2018-05-14 2018-08-31 昆山国显光电有限公司 显示面板及其显示装置
CN111223436A (zh) * 2020-02-26 2020-06-02 上海中航光电子有限公司 阵列基板、显示面板及显示装置
CN111681554A (zh) * 2020-06-30 2020-09-18 上海中航光电子有限公司 显示面板及显示装置
WO2022028132A1 (zh) * 2020-08-07 2022-02-10 京东方科技集团股份有限公司 显示基板、显示装置
CN114447068A (zh) * 2021-12-30 2022-05-06 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN114464644A (zh) * 2020-11-09 2022-05-10 京东方科技集团股份有限公司 显示基板和显示装置
CN114937420A (zh) * 2022-05-27 2022-08-23 武汉天马微电子有限公司 显示面板和显示装置
CN115294889A (zh) * 2022-08-30 2022-11-04 京东方科技集团股份有限公司 显示基板、显示面板及显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102013673B (zh) * 2009-09-07 2014-02-05 上海宏力半导体制造有限公司 一种静电放电保护装置
CN109935571B (zh) * 2019-04-02 2020-06-02 京东方科技集团股份有限公司 显示基板及其制作方法、裂纹检测方法、显示装置
KR20200124798A (ko) * 2019-04-24 2020-11-04 삼성디스플레이 주식회사 표시 장치
CN110277386B (zh) * 2019-06-24 2021-05-14 京东方科技集团股份有限公司 静电释放电路、显示面板、显示装置以及静电释放方法
CN112838106A (zh) * 2019-11-22 2021-05-25 京东方科技集团股份有限公司 显示基板及显示装置
EP4148786A4 (en) * 2020-05-06 2023-06-14 BOE Technology Group Co., Ltd. DISPLAY SUBSTRATE AND DISPLAY DEVICE
CN114784082B (zh) * 2022-06-15 2022-09-30 京东方科技集团股份有限公司 显示基板和显示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108470522A (zh) * 2018-05-14 2018-08-31 昆山国显光电有限公司 显示面板及其显示装置
CN111223436A (zh) * 2020-02-26 2020-06-02 上海中航光电子有限公司 阵列基板、显示面板及显示装置
CN111681554A (zh) * 2020-06-30 2020-09-18 上海中航光电子有限公司 显示面板及显示装置
WO2022028132A1 (zh) * 2020-08-07 2022-02-10 京东方科技集团股份有限公司 显示基板、显示装置
CN114464644A (zh) * 2020-11-09 2022-05-10 京东方科技集团股份有限公司 显示基板和显示装置
CN114447068A (zh) * 2021-12-30 2022-05-06 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN114937420A (zh) * 2022-05-27 2022-08-23 武汉天马微电子有限公司 显示面板和显示装置
CN115294889A (zh) * 2022-08-30 2022-11-04 京东方科技集团股份有限公司 显示基板、显示面板及显示装置

Also Published As

Publication number Publication date
CN115294889A (zh) 2022-11-04
CN115294889B (zh) 2023-11-21

Similar Documents

Publication Publication Date Title
WO2024046054A1 (zh) 显示基板、显示面板及显示装置
US11139317B2 (en) Array substrate, touch panel and manufacturing method of array substrate
WO2024046068A1 (zh) 显示基板及显示装置
WO2022056901A1 (zh) 显示基板、显示装置
WO2023246338A1 (zh) 显示基板及显示装置
WO2023000832A1 (zh) 显示模组和显示设备
WO2024109358A1 (zh) 显示面板及其制备方法、显示装置
WO2023231737A1 (zh) 显示基板及显示装置
CN114730543B (zh) 显示基板及其检测方法、制备方法、显示装置
WO2023246388A1 (zh) 发光二极管器件及其制备方法、显示基板和显示装置
WO2023066104A1 (zh) 显示基板及显示装置
EP4053907A1 (en) Display substrate and display device
CN115802834A (zh) 显示基板及显示装置
US20230351970A1 (en) Display Substrate and Preparation Method thereof, and Display Apparatus
WO2024036511A1 (zh) 显示基板及显示装置
WO2023216200A1 (zh) 显示基板及显示装置
WO2023201537A1 (zh) 显示基板及显示装置
WO2024000287A1 (zh) 显示基板及显示装置
WO2024168468A1 (zh) 显示基板及显示装置
WO2024000292A1 (zh) 显示基板及显示装置
WO2024113181A1 (zh) 显示基板及其制备方法、显示装置
WO2023159509A1 (zh) 显示基板、显示面板及显示装置
WO2022067584A1 (zh) 显示基板及显示装置
WO2023184163A1 (zh) 显示基板及显示装置
WO2023206218A1 (zh) 显示基板及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23859089

Country of ref document: EP

Kind code of ref document: A1