WO2023077269A1 - 显示基板、显示装置 - Google Patents

显示基板、显示装置 Download PDF

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Publication number
WO2023077269A1
WO2023077269A1 PCT/CN2021/128196 CN2021128196W WO2023077269A1 WO 2023077269 A1 WO2023077269 A1 WO 2023077269A1 CN 2021128196 W CN2021128196 W CN 2021128196W WO 2023077269 A1 WO2023077269 A1 WO 2023077269A1
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Prior art keywords
stretching
hole
area
holes
display substrate
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PCT/CN2021/128196
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English (en)
French (fr)
Inventor
赵佳
王品凡
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180003214.2A priority Critical patent/CN116584177A/zh
Priority to PCT/CN2021/128196 priority patent/WO2023077269A1/zh
Publication of WO2023077269A1 publication Critical patent/WO2023077269A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements

Definitions

  • the present disclosure relates to but not limited to the field of display technology, especially a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • TFT Thin Film Transistor
  • an embodiment of the present disclosure provides a display substrate, including a base substrate and a circuit structure layer disposed on the base substrate, the circuit structure layer includes a planar region and at least one layer disposed on the planar region
  • the bendable area on the side, the bendable area includes at least one stretched area, the stretched area includes a first pixel circuit area and a first power line area, and the first power line area is located in the The first pixel circuit area is away from the side of the flat area, the first power line area is provided with a first stretching hole, and the first pixel circuit area is provided with a second stretching hole.
  • the first power trace region includes first power traces, and the first power traces extend along a direction parallel to an edge of the stretching region.
  • the first power trace includes a first conductive layer, a connecting conductive layer, and a second conductive layer that are sequentially stacked along the thickness direction of the base substrate, and the first conductive layer and the The second conductive layer is bridged by the connecting conductive layer.
  • a first insulating layer is disposed between the first conductive layer and the connecting conductive layer, a first via hole is disposed in the first insulating layer, and the connecting conductive layer passes through the The first via hole is connected to the first conductive layer, a second insulating layer is provided between the second conductive layer and the connecting conductive layer, a second via hole is provided in the second insulating layer, and the second via hole is provided in the second insulating layer.
  • the connecting conductive layer is connected to the first conductive layer through the second via hole.
  • the first stretching hole includes a stretching hole in a first direction and a stretching hole in a second direction
  • the stretching hole in the first direction is a strip-shaped hole extending along the first direction
  • the stretching hole in the second direction is a strip-shaped hole extending along the second direction
  • the vertical projection of the stretching hole in the first direction on the substrate is the same as the stretching hole in the second direction on the substrate.
  • the vertical projections of the substrates do not overlap, the number of the stretching holes in the first direction is multiple, and the stretching holes in the first direction are arranged at intervals along the first direction to form a row of stretching holes in the first direction, one Second direction stretching holes are arranged between adjacent first direction stretching holes in the row of first direction stretching holes; and/or, the number of the second direction stretching holes is multiple, and multiple second The direction stretching holes are arranged at intervals along the second direction to form rows of second direction stretching holes, and first direction stretching holes are arranged between adjacent second direction stretching holes in a row of second direction stretching holes. holes, the first direction intersects with the second direction.
  • the first stretching hole includes a stretching hole in a first direction and a stretching hole in a second direction
  • the stretching hole in the first direction is an I-shaped hole extending along the first direction
  • the stretching hole in the second direction is an I-shaped hole extending along the second direction
  • the vertical projection of the stretching hole in the first direction on the substrate is the same as that of the stretching hole in the second direction on the substrate.
  • the vertical projections of the substrates do not overlap, the number of the stretching holes in the first direction is multiple, and the stretching holes in the first direction are arranged at intervals along the first direction to form a row of stretching holes in the first direction, one Second direction stretching holes are arranged between adjacent first direction stretching holes in the row of first direction stretching holes; and/or, the number of the second direction stretching holes is multiple, and multiple second The direction stretching holes are arranged at intervals along the second direction to form rows of second direction stretching holes, and first direction stretching holes are arranged between adjacent second direction stretching holes in a row of second direction stretching holes. holes, the first direction intersects with the second direction.
  • the stretching holes in the first direction and the stretching holes in the second direction each include two first side portions disposed opposite to each other and a second side portion connecting the two first side portions,
  • the two first sides and the second side form the I-shaped hole, and in a row of stretching holes in the first direction, between the edges of the first sides of adjacent stretching holes in the first direction The distance is greater than the length of the first side of the stretching hole in the second direction; and/or, in a row of stretching holes in the second direction, between the edges of the first sides of adjacent stretching holes in the second direction The distance between them is greater than the length of the first side of the stretching hole in the first direction.
  • the stretching holes in the first direction and the stretching holes in the second direction each include two first side portions disposed opposite to each other and a second side portion connecting the two first side portions,
  • the two first sides and the second side form the I-shaped hole, and in a row of stretching holes in the first direction, between the edges of the first sides of adjacent stretching holes in the first direction The distance is less than or equal to the length of the first side of the stretching hole in the second direction; and/or, in a row of stretching holes in the second direction, the edges of the first sides of adjacent stretching holes in the second direction The distance between them is less than or equal to the length of the first side of the stretching hole in the first direction.
  • the stretch zone is located at a corner region of the bendable zone.
  • the first power trace area is an edge area of the stretched area away from the flat area.
  • the planar region includes a gate driving circuit region and a second pixel circuit region located on at least one side of the gate driving circuit region, and a third stretcher is provided in the gate driving circuit region. hole.
  • the shape of the third stretching hole is the same as or different from that of the first stretching hole, and the stretching ratio of the third stretching hole is the same as that of the first stretching hole.
  • the stretch ratio is different.
  • the gate driving circuit area includes at least one sub-gate driving circuit area, and the sub-gate driving circuit includes a plurality of cascaded gate driving units.
  • the gate drive unit Arranged sequentially in the first direction, the gate drive unit includes a plurality of cascaded gate drive islands, the third stretching hole located between adjacent gate drive islands, and the adjacent gate drive A wiring region in which the island regions are connected to each other, a plurality of gate driving island regions are sequentially arranged along a second direction, and the first direction intersects with the second direction.
  • the sub-gate driving circuit further includes an output signal line, the first end of the output signal line is connected to the gate driving unit, and the second end of the output signal line extends to the The second pixel circuit area.
  • the gate driving circuit region and the planar region have the same central axis in the first direction.
  • the planar area further includes a plurality of second power supply lines and a plurality of second power supply fan-out lines, and the plurality of second power supply lines and the plurality of second power supply fan-out lines are connected on the base substrate
  • the orthographic projections of are at least partially overlapped; the plurality of second power supply fan-out lines are correspondingly connected to at least part of the plurality of second power supply lines.
  • the circuit structure layer further includes a binding area disposed on one side of the flat area, the binding area includes at least a lead area, the lead area includes a plurality of lead lines, and the at least A first end of a second power fan-out line is connected to the lead-out line, and a second end of the at least one second power fan-out line is connected to the second power fan-out line.
  • the plurality of second power supply traces extend along the first direction and are arranged at intervals along the second direction, and the distance between adjacent second power supply traces is along the The central axis in the first direction gradually becomes smaller; the first direction and the second direction are intersected.
  • the shape of the second stretching hole is the same as or different from that of the first stretching hole, and the stretching ratio of the second stretching hole is the same as that of the first stretching hole.
  • the stretch ratio is different.
  • an embodiment of the present disclosure further provides a display device, including the aforementioned display substrate.
  • Fig. 1 is a kind of schematic diagram showing the structure of the circuit structure layer in the substrate
  • FIG. 2 is an enlarged view showing a circuit structure layer in a substrate
  • FIG. 3 is a schematic diagram showing the structure of the circuit structure layer in the substrate according to the embodiment of the present application.
  • FIG. 4 is an enlarged view showing the circuit structure layer in the substrate according to the embodiment of the present application.
  • FIG. 5 is an enlarged view showing the first power supply wiring in the substrate according to the embodiment of the present application.
  • FIG. 6 is a schematic diagram showing the structure of the first stretching hole in the substrate according to the embodiment of the present application.
  • Fig. 7 is a schematic diagram showing the second structure of the first stretching hole in the substrate according to the embodiment of the present application.
  • Fig. 8 is a schematic diagram showing the third structure of the first stretching hole in the substrate according to the embodiment of the present application.
  • FIG. 9 is a schematic structural diagram showing a flat region of a circuit structure layer in a substrate according to an embodiment of the present application.
  • FIG. 10 is an enlarged view showing a gate driving unit in a substrate according to an embodiment of the present application.
  • FIG. 11 is a distribution diagram showing the distribution of the second power traces and the second power fan-out lines of the circuit structure layer in the substrate according to the embodiment of the present application.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged with each other.
  • electrically connected includes the case where constituent elements are connected together through an element having some kind of electrical effect.
  • the "element having some kind of electrical action” is not particularly limited as long as it can transmit and receive electrical signals between connected components.
  • Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
  • perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
  • film and “layer” are interchangeable.
  • conductive layer may sometimes be replaced with “conductive film”.
  • insulating film may sometimes be replaced with “insulating layer”.
  • FIG. 1 is a schematic structural view of a circuit structure layer in a display substrate
  • FIG. 2 is an enlarged view of a circuit structure layer in a display substrate. Take Figure 2 as an example of the enlarged view at a in Figure 1.
  • the display substrate includes a base substrate and a circuit structure layer arranged on the base substrate.
  • the circuit structure layer includes a planar region 100 and a bendable region 200 located on at least one side of the planar region 100 .
  • the bendable region 200 may be in a curled state formed by bending.
  • the bendable zone 200 includes at least one stretch zone 300 .
  • the flat area 100 is a rectangular structure, one side of the flat area 100 is provided with a binding area, and the bendable area 200 is arranged around the other sides of the flat area 100 .
  • the stretch zone 300 is located at the corner area of the bendable zone 200 .
  • the stretching area 300 includes a first pixel circuit area 400 and a wiring circuit area 500 , and the wiring circuit area 500 is located on a side of the first pixel circuit area 400 away from the flat area 100 .
  • the first pixel circuit area 400 includes a pixel driving circuit and at least one stretch hole, and the pixel driving circuit is used to drive the light emitting unit to emit light.
  • the stretch holes can be used to provide deformation space during stretching, improve the flexibility of the stretching zone 300, and realize stretchability.
  • the routing circuit area 500 includes a gate driving circuit area, a first power routing area (eg, VSS routing area) and a second power routing area (eg, VDD routing area).
  • the first power wiring area, the second power wiring area and the gate driving circuit area are sequentially arranged along a direction close to the flat area 100 . Since stretching holes cannot be set on the gate drive circuit area, the first power supply wiring area and the second power supply wiring area, the wiring circuit area 500 is a planar structure, that is, the wiring circuit area 500 is not provided with stretching holes, and then When the stretching area 300 is stretched, there is a risk of wrinkles and disconnection at the wiring circuit area 500 , resulting in failure of the display substrate as a whole.
  • An embodiment of the present application provides a display substrate, including a base substrate and a circuit structure layer disposed on the base substrate, the circuit structure layer including a planar region and a bendable substrate disposed on at least one side of the planar region.
  • the bending area, the bendable area includes at least one stretching area, the stretching area includes a first pixel circuit area and a first power wiring area, and the first power wiring area is located in the first pixel circuit The region is far away from the flat region, and a first stretching hole is set in the first power line region.
  • the embodiment of the present application shows that the substrate is provided with a first stretching hole in the first power wiring area in the stretching area, and a second stretching hole is provided in the first pixel circuit area in the stretching area, so that the stretching
  • the entire area of the stretch zone has an open structure, which avoids the risk of wrinkles and broken lines when the stretch zone is stretched.
  • FIG. 3 is a schematic diagram showing the structure of a circuit structure layer in a substrate according to an embodiment of the present application.
  • the substrate includes: a base substrate and a circuit structure layer disposed on the base substrate.
  • the circuit structure layer includes a planar region 100 , a binding region 500 located on one side of the planar region 100 opposite to the first direction D1 , and a bendable region 200 located on the other side of the planar region 100 .
  • the bendable zone 200 includes at least one stretch zone 300 .
  • the flat area 100 is rectangular, and the bendable area 200 surrounds the peripheral sides of the flat area 100 on other sides except the side where the binding area 500 is located.
  • the bendable region 200 includes four stretching regions 300 , and the four stretching regions 300 are respectively located at four corner regions of the bendable region 200 .
  • FIG. 4 is an enlarged view showing a circuit structure layer in a substrate according to an embodiment of the present application.
  • the stretching area 300 includes a first pixel circuit area 400 and a first power wiring area 600 , and the first power wiring area 600 is located on a side of the first pixel circuit area 400 away from the flat area 100 .
  • the first power trace area 600 is an edge area of the stretching area 300 away from the flat area 100 .
  • the first pixel circuit region 400 may include a plurality of transistors and storage capacitors.
  • the first pixel circuit area 400 may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure. Embodiments of the present disclosure will not be repeated here.
  • the first power supply wiring area 600 includes a plurality of first power supply wirings configured to output first level signals to the first pixel circuit area 400 and the second pixel circuit area in the flat area 100 .
  • the first level signal may be a low level signal (VSS).
  • VSS low level signal
  • the substrate is provided with a first stretching hole through the first power wiring region 600 in the stretching region 300
  • the first pixel circuit region 400 in the stretching region 300 is provided with a second stretching hole , so that the entire area of the stretching zone 300 has an open structure, that is, the first stretching hole and the second stretching hole, so as to avoid the risk of wrinkles and broken lines when the stretching zone 300 is stretched.
  • the display substrate of this embodiment may be an organic light emitting diode (OLED, Organic Light Emitting Diode) display substrate or a quantum dot light emitting diode (QLED, Quantum-dot Light Emitting Diode) display substrate.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • this embodiment does not limit it.
  • FIG. 5 is an enlarged view showing the first power trace in the substrate according to the embodiment of the present application.
  • the first power trace 1 may extend along a direction parallel to the edge of the tensile region 300 .
  • the first power trace 1 includes a first conductive layer 101, a connecting conductive layer 102, and a second conductive layer 103 that are sequentially stacked along the thickness direction of the substrate.
  • the first conductive layer 101 and the second conductive layer 103 are connected through the connecting conductive layer 102 bridging.
  • a first insulating layer is disposed between the first conductive layer 101 and the connecting conductive layer 102
  • a second insulating layer is disposed between the second conductive layer 103 and the connecting conductive layer 102 .
  • At least part of the vertical projection of the connecting conductive layer 102 on the substrate overlaps with the vertical projection of the first conductive layer 101 on the substrate
  • at least part of the vertical projection of the connecting conductive layer 102 on the substrate overlaps with the vertical projection of the second conductive layer 103 on the substrate.
  • a plurality of first stretch holes 2 are disposed in the first power trace area 600 , at least part of the first stretch holes 2 are located in the first power trace 1 . At least part of the first stretching hole 2 is located in at least one of the first conductive layer 101 , the connecting conductive layer 102 and the second conductive layer 103 .
  • the first stretching hole 2 is only set on the first conductive layer; and/or, the first stretching hole 2 is only set on the connecting conductive layer; and/or, the first stretching hole 2 is only set on the second On the conductive layer; and/or, a part of the first stretching hole 2 is arranged on the first conductive layer, a part of the first stretching hole 2 is arranged on the connecting conductive layer, and a part of the first stretching hole 2 is arranged on the second conductive layer and/or, a part of the first stretching hole 2 is set on the first conductive layer, and another part of the first stretching hole 2 is set on the connecting conductive layer; and/or, a part of the first stretching hole 2 is set on the second On the second conductive layer, another part of the first stretching hole 2 is arranged on the connecting conductive layer.
  • FIG. 6 is a first structural schematic diagram showing a first stretching hole in a substrate according to an embodiment of the present application.
  • the first stretching hole 2 includes a stretching hole 21 in a first direction and a stretching hole 22 in a second direction, and the stretching hole 21 in the first direction is along the first direction D1.
  • the second-direction stretching hole 22 is a strip-shaped hole extending along the second direction D2, the vertical projection of the first-direction stretching hole 21 on the base substrate and the second-direction stretching hole 22 on the lining
  • the vertical projections of the base substrate do not overlap
  • the number of first-direction stretching holes 21 is multiple
  • the plurality of first-direction stretching holes 21 are arranged at intervals along the first direction D1 to form rows of first-direction stretching holes
  • one Second direction stretching holes 22 are arranged between adjacent first direction stretching holes 21 in the row of first direction stretching holes; and/or, the number of second direction stretching holes 22 is plural
  • the plurality of The two-direction stretching holes 22 are arranged at intervals along the second direction D2 to form a second-direction stretching hole row
  • a first-direction stretching hole 22 is arranged between adjacent second-direction stretching holes 22 in a second-direction stretching hole row. Stretch hole 21.
  • the first direction D1 and the second direction D2 are intersected.
  • FIG. 7 is a second schematic diagram showing the structure of the first stretching hole in the substrate according to the embodiment of the present application.
  • the first stretching hole 2 includes a stretching hole 21 in a first direction and a stretching hole 22 in a second direction, and the stretching hole 21 in the first direction is along the first direction D1.
  • the second direction stretching hole 22 is an I-shaped hole extending along the second direction D2, the vertical projection of the first direction stretching hole 21 on the base substrate and the second direction stretching hole 22 on the lining
  • the vertical projections of the base substrate do not overlap
  • the number of first-direction stretching holes 21 is multiple
  • the plurality of first-direction stretching holes 21 are arranged at intervals along the first direction D1 to form rows of first-direction stretching holes
  • one Second direction stretching holes 22 are arranged between adjacent first direction stretching holes 21 in the row of first direction stretching holes; and/or, the number of second direction stretching holes 22 is plural
  • the plurality of The two-direction stretching holes 22 are arranged at intervals along the second direction D2 to form a second-direction stretching hole row
  • a first-direction stretching hole 22 is arranged between adjacent second-direction stretching holes 22 in a second-direction stretching hole row.
  • the first direction D1 and the second direction D2 are intersected.
  • the first direction D1 is perpen
  • the stretching holes 21 in the first direction and the stretching holes 22 in the second direction each include two first side portions 23 oppositely arranged and connect the two first side portions 23
  • the second edge portion 24, the two first edge portions 23 and the second edge portion 21 form an I-shaped hole.
  • the distance between the edges of the first side portions 23 of adjacent stretching holes 21 in the first direction is greater than the length of the first side portions 23 of the stretching holes 22 in the second direction; and /or, in a row of stretching holes in the second direction, the distance between the edges of the first side portions 23 of adjacent stretching holes 22 in the second direction is greater than that of the first side portions 23 of the stretching holes 21 in the first direction. length.
  • FIG. 8 is a schematic diagram showing the third structure of the first stretching hole in the substrate according to the embodiment of the present application.
  • the stretching holes 21 in the first direction and the stretching holes 22 in the second direction each include two first side portions 23 oppositely arranged and connect the two first side portions 23
  • the second edge portion 24, the two first edge portions 23 and the second edge portion 21 form an I-shaped hole.
  • the distance between the edges of the first side portions 23 of adjacent stretching holes 21 in the first direction is less than or equal to the length of the first side portion 23 of the stretching holes 22 in the second direction; And/or, in a second-direction stretching hole row, the distance between the edges of the first side portions 23 of adjacent second-direction stretching holes 22 is less than or equal to the first side portion of the first-direction stretching holes 21 23 in length.
  • the shape and distribution of the second stretching holes may be the same as or different from those of the first stretching holes, and the stretching ratio of the second stretching holes is the same as that of the first stretching holes. Different, the embodiment of the present application will not be repeated here.
  • the flat area of this embodiment is further provided with a plurality of data lines.
  • the first conductive layer can be arranged on the same layer as the data line, and can be prepared by using the same material through the same preparation process.
  • the display substrate of this embodiment further includes a light-emitting structure layer disposed on the circuit structure layer, and the light-emitting structure layer includes an anode, a light-emitting layer, and a cathode.
  • the connecting conductive layer 102 can be arranged on the same layer as the anode, and can be prepared by using the same material through the same manufacturing process.
  • the second conductive layer 103 can be arranged on the same layer as the cathode, and can be prepared by using the same material through the same preparation process.
  • FIG. 9 is a schematic structural diagram showing a planar region of a circuit structure layer in a substrate according to an embodiment of the present application.
  • the planar region 100 includes a gate driver on array (Gate Driver on Array, GOA for short) 700 and a second pixel circuit region 800 located on at least one side of the gate driver on array 700 , the second pixel circuit region 800 may include a plurality of transistors and storage capacitors.
  • the second pixel circuit region 800 may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure. Embodiments of the present disclosure will not be repeated here.
  • a third stretching hole is disposed in the gate driving circuit region 700 .
  • the gate driving circuit area 2 can be used to transmit scanning signals and light emitting signals to the first pixel circuit area of the stretching area 300 and the second pixel circuit area 800 of the flat area 100 .
  • the gate driving circuit region 700 by removing the gate driving circuit region 700 from the bendable region 200, the gate driving circuit region 700 is arranged in the planar region 100, so as to reduce the area of the wiring circuit region in the stretching region 300 , to reduce the risk of wrinkles and disconnection in the wiring circuit area when the stretching area 300 is stretched.
  • the gate driving circuit region 700 by setting the third stretching hole in the gate driving circuit region 700 , the gate driving circuit region 700 can be stretched, and the influence of the gate driving circuit region 700 on the planar region 300 is reduced.
  • the gate driving circuit region 700 includes at least one sub-gate driving circuit region 3 .
  • the gate driving circuit region 700 includes two first sub-gate driving circuit regions and a second sub-gate driving circuit region extending along the first direction D1, the first sub-gate driving circuit region is configured to stretch The first pixel circuit area in the area 300 and the second pixel circuit area 800 in the flat area 100 transmit scan signals; The second pixel circuit area 800 transmits a light emitting signal.
  • FIG. 10 is an enlarged view showing a gate driving unit in a substrate according to an embodiment of the present application.
  • the sub-gate driving circuit includes a plurality of cascaded gate driving units, and the plurality of gate driving units are sequentially arranged along the first direction D1.
  • a gate driving unit 31 includes a plurality of cascaded gate driving island regions 301 , a third stretch hole 302 located between adjacent gate driving island regions 301 , and the adjacent gate driving The wiring regions 303 where the island regions 301 are connected to each other, and a plurality of gate driving island regions 301 are arranged sequentially along the second direction.
  • the gate driving island region 301 includes sub-gate driving circuits, and all the sub-gate driving circuits in the gate driving island region 301 in one gate driving unit 31 form a gate driving circuit.
  • the wiring area 303 includes a plurality of connection leads, and the plurality of connection leads connect the sub-gate drive circuits in adjacent gate drive island areas 301 to each other.
  • the third stretching hole 302 is used to provide deformation space during stretching.
  • the gate driving unit 31 may have a structure of 8T2C (ie, eight transistors and two capacitors), or a structure of 12T4C (ie, twelve transistors and four capacitors). Take the 8T2C structure of the gate driving unit 31 as an example.
  • the gate drive unit 31 includes three cascaded gate drive island regions 301, the 8T2C circuit is split into three sub-gate drive circuits, and the three sub-gate drive circuits are respectively arranged in the three gate drive island regions 301, namely The three sub-gate driving circuits in the three gate driving island regions 301 form an 8T2C circuit.
  • the first direction D1 and the second direction D2 are intersected.
  • the first direction D1 is perpendicular to the second direction D2.
  • the shape and distribution of the third stretching holes may be the same as or different from those of the first stretching holes, and the stretching ratio of the third stretching holes is the same as that of the first stretching holes. Different, the embodiment of the present application will not be repeated here.
  • the stretching ratios of the first stretching hole, the second stretching hole, and the third stretching hole can be adjusted according to requirements, and can be the same or different.
  • the gate driving unit may include at least one output signal line, a first end of the output signal line is connected to the gate driving unit, and a second end of the output signal line may extend to a flat surface along the second direction D2.
  • the second pixel circuit area in the area. After the output signal line extends to the second pixel circuit area, it can be connected to the scanning signal line or the light emitting signal line in the second pixel circuit area, and the gate driving unit can output the scanning signal or the light emitting signal to the second pixel circuit area.
  • the gate driving circuit area and the flat area have the same central axis in the first direction, that is, the gate driving circuit area is located in the middle area of the flat area in the second direction, so that the gate driving Routing in the circuit area.
  • FIG. 11 is a distribution diagram showing the distribution of the second power traces and the second power fan-out lines of the circuit structure layer in the substrate according to the embodiment of the present application.
  • the planar region 100 further includes a plurality of second power supply lines 4 and a plurality of second power supply fan-out lines 5 .
  • the bonding area 500 includes a lead area 900 , and the lead area 900 may include a plurality of lead wires 6 .
  • the plurality of second power supply wires 4 are configured to output second level signals to the first pixel circuit area 400 and the second pixel circuit area in the flat area 100 .
  • the second level signal may be a high level signal (VDD).
  • a plurality of second power supply fan-out lines 5 are correspondingly connected to a part of the second power supply lines 4 , and are configured such that a part of the second power supply lines 4 are correspondingly connected to a plurality of lead-out lines 6 in the bonding area 500 .
  • a plurality of second power supply wires 4 extend along the first direction D1 and are arranged at intervals along the second direction D2.
  • the distance between adjacent second power supply traces 4 gradually becomes smaller along the central axis in the first direction near the flat region 100 . That is, the density of the plurality of second power supply wires 4 gradually increases along the central axis in the first direction near the flat area 100 .
  • the first direction D1 and the second direction D2 are intersected.
  • the first direction D1 is perpendicular to the second direction D2.
  • the pixel circuits on the circuit structure layer form a plurality of pixel circuit rows and a plurality of pixel circuit columns.
  • a plurality of second power supply lines 4 extend along the first direction D1 and are sequentially arranged at set intervals along the second direction D2, each second power supply line is connected to all pixels in a pixel circuit column in the circuit structure layer circuit connection.
  • each second power supply fan-out line 5 is correspondingly connected to a part of the lead-out lines 6 of the wiring area 501, and the second end of each second power supply fan-out line 5 is connected to a part of the second power supply wiring 4 corresponds to the connection.
  • a part of the lead-out lines 6 in the lead-out area 900 is connected to the second power supply fan-out line 5 , and another part of the lead-out lines 6 is correspondingly connected to another part of the second power supply wiring 4 .
  • the orthographic projection of any lead-out line 6 on the base substrate has no overlapping area with the orthographic projections of other lead-out lines 6 on the base substrate, and the orthographic projection of any second power fan-out line 5 on the base substrate There is no overlapping area between the projection and the orthographic projection of other second power supply fan-out lines 5 on the base substrate.
  • An embodiment of the present disclosure also provides a display device, including the display substrate of the foregoing embodiments.
  • the display device can be: mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, navigator, advertising panel, watch phone, e-book portable multimedia player or display screen of various products of the Internet of Things, etc. products or components.
  • the display device may be a wearable display device that can be worn on the human body in some ways, such as a smart watch, a smart bracelet, and the like.

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Abstract

一种显示基板、显示装置，显示基板包括衬底基板和设置在所述衬底基板上的电路结构层，所述电路结构层包括平坦区以及设置在所述平坦区至少一侧的可弯折区，所述可弯折区包括至少一个拉伸区，所述拉伸区包括第一像素电路区以及第一电源走线区，所述第一电源走线区位于所述第一像素电路区远离所述平坦区一侧，所述第一电源走线区中设置有第一拉伸孔，所述第一像素电路区中设置有第二拉伸孔。

Description

显示基板、显示装置 技术领域
本公开涉及但不限于显示技术领域，尤指一种显示基板、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度等优点。随着显示技术的不断发展，以OLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的显示装置已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开实施例提供了一种显示基板，包括衬底基板和设置在所述衬底基板上的电路结构层，所述电路结构层包括平坦区以及设置在所述平坦区至少一侧的可弯折区，所述可弯折区包括至少一个拉伸区，所述拉伸区包括第一像素电路区以及第一电源走线区，所述第一电源走线区位于所述第一像素电路区远离所述平坦区一侧，所述第一电源走线区中设置有第一拉伸孔，所述第一像素电路区中设置有第二拉伸孔。
在示例性实施方式中，所述第一电源走线区包括第一电源走线，所述第一电源走线沿着平行于所述拉伸区边缘的方向延伸。
在示例性实施方式中，所述第一电源走线包括沿所述衬底基板厚度方向依次层叠设置的第一导电层、连接导电层以及第二导电层，所述第一导电层和所述第二导电层通过所述连接导电层桥接。
在示例性实施方式中，所述第一导电层与所述连接导电层之间设置有第 一绝缘层，所述第一绝缘层中设置有第一过孔，所述连接导电层通过所述第一过孔与所述第一导电层连接，所述第二导电层与所述连接导电层之间设置有第二绝缘层，所述第二绝缘层中设置有第二过孔，所述连接导电层通过所述第二过孔与所述第一导电层连接。
在示例性实施方式中，所述第一拉伸孔包括第一方向拉伸孔和第二方向拉伸孔，所述第一方向拉伸孔是沿着第一方向延伸的条形状孔，所述第二方向拉伸孔是沿着第二方向延伸的条形状孔，所述第一方向拉伸孔在所述衬底基板的垂直投影与所述第二方向拉伸孔在所述衬底基板的垂直投影不交叠，所述第一方向拉伸孔的数目为多个，多个第一方向拉伸孔沿着所述第一方向间隔排布形成第一方向拉伸孔行，一个第一方向拉伸孔行中相邻的第一方向拉伸孔之间设置有第二方向拉伸孔；和/或，所述第二方向拉伸孔的数目为多个，多个第二方向拉伸孔沿着所述第二方向间隔排布形成第二方向拉伸孔行，一个第二方向拉伸孔行中相邻的第二方向拉伸孔之间设置有第一方向拉伸孔，所述第一方向与所述第二方向交叉设置。
在示例性实施方式中，所述第一拉伸孔包括第一方向拉伸孔和第二方向拉伸孔，所述第一方向拉伸孔是沿着第一方向延伸的工字形孔，所述第二方向拉伸孔是沿着第二方向延伸的工字形孔，所述第一方向拉伸孔在所述衬底基板的垂直投影与所述第二方向拉伸孔在所述衬底基板的垂直投影不交叠，所述第一方向拉伸孔的数目为多个，多个第一方向拉伸孔沿着所述第一方向间隔排布形成第一方向拉伸孔行，一个第一方向拉伸孔行中相邻的第一方向拉伸孔之间设置有第二方向拉伸孔；和/或，所述第二方向拉伸孔的数目为多个，多个第二方向拉伸孔沿着所述第二方向间隔排布形成第二方向拉伸孔行，一个第二方向拉伸孔行中相邻的第二方向拉伸孔之间设置有第一方向拉伸孔，所述第一方向与所述第二方向交叉设置。
在示例性实施方式中，所述第一方向拉伸孔和第二方向拉伸孔均包括相对设置的两个第一边部以及将所述两个第一边部连接的第二边部，所述两个第一边部与所述第二边部组成所述工字形孔，在一个第一方向拉伸孔行中，相邻的第一方向拉伸孔的第一边部边缘之间的距离大于所述第二方向拉伸孔的第一边部的长度；和/或，在一个第二方向拉伸孔行中，相邻的第二方向拉 伸孔的第一边部边缘之间的距离大于所述第一方向拉伸孔的第一边部的长度。
在示例性实施方式中，所述第一方向拉伸孔和第二方向拉伸孔均包括相对设置的两个第一边部以及将所述两个第一边部连接的第二边部，所述两个第一边部与所述第二边部组成所述工字形孔，在一个第一方向拉伸孔行中，相邻的第一方向拉伸孔的第一边部边缘之间的距离小于等于所述第二方向拉伸孔的第一边部的长度；和/或，在一个第二方向拉伸孔行中，相邻的第二方向拉伸孔的第一边部边缘之间的距离小于等于所述第一方向拉伸孔的第一边部的长度。
在示例性实施方式中，所述拉伸区位于所述可弯折区的边角区域。
在示例性实施方式中，所述第一电源走线区为所述拉伸区远离所述平坦区一侧的边缘区域。
在示例性实施方式中，所述平坦区包括栅极驱动电路区以及位于所述栅极驱动电路区至少一侧的第二像素电路区，所述栅极驱动电路区中设置有第三拉伸孔。
在示例性实施方式中，所述第三拉伸孔的形状与所述第一拉伸孔的形状相同或不同，所述第三拉伸孔的拉伸倍率与所述第一拉伸孔的拉伸倍率不同。
在示例性实施方式中，所述栅极驱动电路区包括至少一个子栅极驱动电路区，所述子栅极驱动电路包括级联的多个栅极驱动单元，多个栅极驱动单元沿着第一方向依次排布，所述栅极驱动单元包括级联的多个栅极驱动岛区、位于相邻栅极驱动岛区之间的所述第三拉伸孔以及使相邻栅极驱动岛区彼此连接的布线区，多个栅极驱动岛区沿着第二方向依次排布，所述第一方向与所述第二方向交叉。
在示例性实施方式中，所述子栅极驱动电路还包括输出信号线，所述输出信号线的第一端与所述栅极驱动单元连接，所述输出信号线的第二端延伸至所述第二像素电路区。
在示例性实施方式中，所述栅极驱动电路区与所述平坦区在所述第一方向上具有相同的中心轴线。
在示例性实施方式中，所述平坦区还包括多条第二电源走线以及多条第二电源扇出线，多条第二电源走线和多条第二电源扇出线在所述衬底基板的正投影至少部分重叠；所述多条第二电源扇出线与至少部分所述多条第二电源走线对应连接。
在示例性实施方式中，所述电路结构层还包括设置在所述平坦区一侧的绑定区域，所述绑定区域至少包括引线区，所述引线区包括多条引出线，所述至少一条第二电源扇出线的第一端与所述引出线连接，所述至少一条第二电源扇出线的第二端与所述第二电源扇出线连接。
在示例性实施方式中，所述多条第二电源走线沿着第一方向延伸，并沿着第二方向间隔设置，相邻第二电源走线之间的间距沿着靠近所述平坦区在所述第一方向上的中心轴线逐渐变小；所述第一方向与所述第二方向交叉设置。
在示例性实施方式中，所述第二拉伸孔的形状与所述第一拉伸孔的形状相同或不同，所述第二拉伸孔的拉伸倍率与所述第一拉伸孔的拉伸倍率不同。
第二方面，本公开实施例还提供了一种显示装置，包括前述的显示基板。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示基板中电路结构层的结构示意图；
图2为一种显示基板中电路结构层的放大图；
图3为本申请实施例显示基板中电路结构层的结构示意图；
图4为本申请实施例显示基板中电路结构层的放大图；
图5为本申请实施例显示基板中第一电源走线的放大图；
图6为本申请实施例显示基板中第一拉伸孔的结构示意图一；
图7为本申请实施例显示基板中第一拉伸孔的结构示意图二；
图8为本申请实施例显示基板中第一拉伸孔的结构示意图三；
图9为本申请实施例显示基板中电路结构层的平坦区的结构示意图；
图10为本申请实施例显示基板中一个栅极驱动单元的放大图；
图11为本申请实施例显示基板中电路结构层的第二电源走线和第二电源扇出线的分布图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述， 而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层” 换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示基板中电路结构层的结构示意图；图2为一种显示基板中电路结构层的放大图。以图2为图1中a处放大图为例。该显示基板包括衬底基板和设置在衬底基板上的电路结构层。如图1和图2所示，电路结构层包括平坦区100、位于平坦区100至少一侧的可弯折区200。可弯折区200可以是通过弯折形成的卷曲状态。可弯折区200包括至少一个拉伸区300。示例的，平坦区100为矩形结构，平坦区100的一侧设置有绑定区，可弯折区200围绕平坦区100其他侧的四周设置。拉伸区300位于可弯折区200的边角区域。
如图2所示，拉伸区300包括第一像素电路区400以及走线电路区500，走线电路区500位于第一像素电路区400远离平坦区100一侧。第一像素电路区400包括像素驱动电路以及至少一个拉伸孔，像素驱动电路用于驱动发光单元发光。拉伸孔可以用于在拉伸时提供变形空间，提高拉伸区300的柔性，实现可拉伸。走线电路区500包括栅极驱动电路区、第一电源走线区(例如，VSS走线区)和第二电源走线区(例如，VDD走线区)。第一电源走线区、第二电源走线区以及栅极驱动电路区沿着靠近平坦区100方向依次排布。由于栅极驱动电路区、第一电源走线区和第二电源走线区上无法设置拉伸孔，导致走线电路区500为平面结构，即走线电路区500没有设置拉伸孔，进而在拉伸区300拉伸时，在走线电路区500处容易出现了褶皱、断线的风险，导致显示基板整体失效。
本申请实施例提供了一种显示基板，包括衬底基板和设置在所述衬底基板上的电路结构层，所述电路结构层包括平坦区以及设置在所述平坦区至少一侧的可弯折区，所述可弯折区包括至少一个拉伸区，所述拉伸区包括第一像素电路区以及第一电源走线区，所述第一电源走线区位于所述第一像素电路区远离所述平坦区一侧，所述第一电源走线区中设置有第一拉伸孔。
本申请实施例显示基板通过在拉伸区中的第一电源走线区设置有第一拉 伸孔，以及在拉伸区中的第一像素电路区设置有第二拉伸孔，使拉伸区整个区域均具有开孔结构，避免拉伸区拉伸时，出现褶皱、断线的风险的问题。
下面通过一些示例对本实施例的方案进行举例说明。
图3为本申请实施例显示基板中电路结构层的结构示意图。本申请实施例显示基板包括：衬底基板和设置在衬底基板上的电路结构层。如图3所示，电路结构层包括平坦区100、位于平坦区100第一方向D1的反方向一侧的绑定区域500以及位于平坦区100其它侧的可弯折区200。可弯折区200包括至少一个拉伸区300。示例的，平坦区100为矩形，可弯折区200围绕平坦区100除绑定区域500所在侧以外的其他侧的周侧。可弯折区200包括四个拉伸区300，四个拉伸区300分别位于可弯折区200的四个边角区域。
图4为本申请实施例显示基板中电路结构层的放大图。在示例性实施方式中，以图4为图3中b处放大图为例。如图3和图4所示，拉伸区300包括第一像素电路区400以及第一电源走线区600，第一电源走线区600位于第一像素电路区400远离平坦区100一侧。第一电源走线区600为拉伸区300远离平坦区100一侧的边缘区域。第一像素电路区400可以包括多个晶体管和存储电容。第一像素电路区400可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C结构。本公开实施例在此不再赘述。第一电源走线区600包括多条第一电源走线，第一电源走线被配置为向第一像素电路区400以及平坦区100中的第二像素电路区输出第一电平信号。第一电平信号可以为低电平信号(VSS)。其中，第一像素电路区400中设置有第一拉伸孔，第一像素电路区中设置有第二拉伸孔。
在本公开实施例显示基板的电路结构层中，拉伸区300除第一像素电路区400和第一电源走线区600以外，没有设置其他电路区。本公开实施例显示基板通过在拉伸区300中的第一电源走线区600设置有第一拉伸孔，以及在拉伸区300中的第一像素电路区400设置有第二拉伸孔，使拉伸区300整个区域均具有开孔结构，即第一拉伸孔和第二拉伸孔，避免拉伸区300拉伸时，出现褶皱、断线的风险的问题。
在一些示例性实施方式中，本实施例的显示基板可以为有机发光二极管(OLED，Organic Light Emitting Diode)显示基板或者量子点发光二极管 (QLED，Quantum-dot Light Emitting Diode)显示基板。然而，本实施例对此并不下限定。
图5为本申请实施例显示基板中第一电源走线的放大图。在示例性实施方式中，如图5所示，第一电源走线1可以沿着平行于拉伸区300边缘的方向延伸。第一电源走线1包括沿着衬底基板厚度方向依次层叠设置的第一导电层101、连接导电层102以及第二导电层103，第一导电层101和第二导电层103通过连接导电层102桥接。示例的，第一导电层101与连接导电层102之间设置有第一绝缘层，第二导电层103与连接导电层102之间设置有第二绝缘层。至少部分连接导电层102在衬底基板的垂直投影与第一导电层101在衬底基板的垂直投影交叠，至少部分连接导电层102在衬底基板的垂直投影与第二导电层103在衬底基板的垂直投影交叠，第一绝缘层中设置有第一过孔，第二绝缘层中设置有第二过孔，连接导电层102通过第一过孔与第一导电层101连接，连接导电层102通过第二过孔与第二导电层103连接。
在示例性实施方式中，第一电源走线区600中设置有多个第一拉伸孔2，至少部分第一拉伸孔2位于第一电源走线1中。至少部分第一拉伸孔2位于第一导电层101、连接导电层102以及第二导电层103中的至少一个。例如，第一拉伸孔2仅设置在第一导电层上；和/或，第一拉伸孔2仅设置在连接导电层上；和/或，第一拉伸孔2仅设置在第二导电层上；和/或，第一拉伸孔2一部分设置在第一导电层上，第一拉伸孔2一部分设置在连接导电层上，第一拉伸孔2一部分设置在第二导电层上；和/或，第一拉伸孔2一部分设置在第一导电层上，第一拉伸孔2另一部分设置在连接导电层上；和/或，第一拉伸孔2一部分设置在第二导电层上，第一拉伸孔2另一部分设置在连接导电层上。
图6为本申请实施例显示基板中第一拉伸孔的结构示意图一。在示例性实施方式中，如图6所示，第一拉伸孔2包括第一方向拉伸孔21和第二方向拉伸孔22，第一方向拉伸孔21是沿着第一方向D1延伸的条形状孔，第二方向拉伸孔22是沿着第二方向D2延伸的条形状孔，第一方向拉伸孔21在衬底基板的垂直投影与第二方向拉伸孔22在衬底基板的垂直投影不交叠，第一方向拉伸孔21的数目为多个，多个第一方向拉伸孔21沿着第一方向D1间 隔排布形成第一方向拉伸孔行，一个第一方向拉伸孔行中相邻的第一方向拉伸孔21之间设置有第二方向拉伸孔22；和/或，第二方向拉伸孔22的数目为多个，多个第二方向拉伸孔22沿着第二方向D2间隔排布形成第二方向拉伸孔行，一个第二方向拉伸孔行中相邻的第二方向拉伸孔22之间设置有第一方向拉伸孔21。其中，第一方向D1与第二方向D2交叉设置。例如，第一方向D1与第二方向D2垂直设置。
图7为本申请实施例显示基板中第一拉伸孔的结构示意图二。在示例性实施方式中，如图7所示，第一拉伸孔2包括第一方向拉伸孔21和第二方向拉伸孔22，第一方向拉伸孔21是沿着第一方向D1延伸的工字形孔，第二方向拉伸孔22是沿着第二方向D2延伸的工字形孔，第一方向拉伸孔21在衬底基板的垂直投影与第二方向拉伸孔22在衬底基板的垂直投影不交叠，第一方向拉伸孔21的数目为多个，多个第一方向拉伸孔21沿着第一方向D1间隔排布形成第一方向拉伸孔行，一个第一方向拉伸孔行中相邻的第一方向拉伸孔21之间设置有第二方向拉伸孔22；和/或，第二方向拉伸孔22的数目为多个，多个第二方向拉伸孔22沿着第二方向D2间隔排布形成第二方向拉伸孔行，一个第二方向拉伸孔行中相邻的第二方向拉伸孔22之间设置有第一方向拉伸孔21。其中，第一方向D1与第二方向D2交叉设置。例如，第一方向D1与第二方向D2垂直设置。
在示例性实施方式中，如图7所示，第一方向拉伸孔21和第二方向拉伸孔22均包括相对设置的两个第一边部23以及将两个第一边部23连接的第二边部24，两个第一边部23与第二边部21组成工字形孔。在一个第一方向拉伸孔行中，相邻的第一方向拉伸孔21的第一边部23边缘之间的距离大于第二方向拉伸孔22的第一边部23的长度；和/或，在一个第二方向拉伸孔行中，相邻的第二方向拉伸孔22的第一边部23边缘之间的距离大于第一方向拉伸孔21的第一边部23的长度。
图8为本申请实施例显示基板中第一拉伸孔的结构示意图三。在示例性实施方式中，如图8所示，第一方向拉伸孔21和第二方向拉伸孔22均包括相对设置的两个第一边部23以及将两个第一边部23连接的第二边部24，两个第一边部23与第二边部21组成工字形孔。在一个第一方向拉伸孔行中， 相邻的第一方向拉伸孔21的第一边部23边缘之间的距离小于等于第二方向拉伸孔22的第一边部23的长度；和/或，在一个第二方向拉伸孔行中，相邻的第二方向拉伸孔22的第一边部23边缘之间的距离小于等于第一方向拉伸孔21的第一边部23的长度。
在示例性实施方式中，第二拉伸孔的形状和分布可以与第一拉伸孔的形状和分布相同或不同，第二拉伸孔的拉伸倍率与第一拉伸孔的拉伸倍率不同，本申请实施例在此不再赘述。
在示例性实施方式中，本实施例的平坦区还设置有多条数据线。第一导电层可以与数据线同层设置，采用相同的材料通过同一制备工艺制备而成。本实施例的显示基板还包括设置在电路结构层上的发光结构层，发光结构层包括阳极、发光层以及阴极等。连接导电层102可以与阳极同层设置，采用相同的材料通过同一制备工艺制备而成。第二导电层103可以与阴极同层设置，采用相同的材料通过同一制备工艺制备而成。
图9为本申请实施例显示基板中电路结构层的平坦区的结构示意图。在示例性实施方式中，如图9所示，平坦区100包括栅极驱动电路区(Gate Driver on Array，简称GOA)700以及位于栅极驱动电路区700至少一侧的第二像素电路区800，第二像素电路区800可以包括多个晶体管和存储电容。第二像素电路区800可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C结构。本公开实施例在此不再赘述。栅极驱动电路区700中设置有第三拉伸孔。栅极驱动电路区2可以用于向拉伸区300的第一像素电路区以及平坦区100的第二像素电路区800传输扫描信号和发光信号。
本申请实施例通过将栅极驱动电路区700从可弯折区200中移除，将栅极驱动电路区700设置在平坦区100中，以减小拉伸区300中走线电路区的面积，降低拉伸区300拉伸时，走线电路区域出现褶皱、断线的风险。本申请实施例通过在栅极驱动电路区700中设置第三拉伸孔，使栅极驱动电路区700可拉伸，将栅极驱动电路区700对平坦区300的影响。
在示例性实施方式中，如图9所示，栅极驱动电路区700包括至少一个子栅极驱动电路区3。例如，栅极驱动电路区700包括两个沿第一方向D1延伸的第一子栅极驱动电路区和第二子栅极驱动电路区，第一子栅极驱动电 路区被配置为向拉伸区300的第一像素电路区以及平坦区100的第二像素电路区800传输扫描信号；第二子栅极驱动电路区被配置为向拉伸区300的第一像素电路区以及平坦区100的第二像素电路区800传输发光信号。
图10为本申请实施例显示基板中一个栅极驱动单元的放大图。在示例性实施方式中，子栅极驱动电路包括级联的多个栅极驱动单元，多个栅极驱动单元沿着第一方向D1依次排布。如图10所示，一个栅极驱动单元31包括级联的多个栅极驱动岛区301、位于相邻栅极驱动岛区301之间的第三拉伸孔302以及使相邻栅极驱动岛区301彼此连接的布线区303，多个栅极驱动岛区301沿着第二方向依次排布。栅极驱动岛区301包括子栅极驱动电路，一个栅极驱动单元31中的所有栅极驱动岛区301中的子栅极驱动电路组成一个栅极驱动电路。布线区303包括多条连接引线，多条连接引线将相邻栅极驱动岛区301中的子栅极驱动电路彼此连接。第三拉伸孔302用于在拉伸时提供变形空间。例如，栅极驱动单元31可以为8T2C(即八个晶体管和两个电容)结构、或者12T4C(即十二个晶体管和四个电容)结构等。以栅极驱动单元31为8T2C结构为例。栅极驱动单元31包括级联的三个栅极驱动岛区301，8T2C电路拆分成三个子栅极驱动电路，三个子栅极驱动电路分别设置在三个栅极驱动岛区301中，即三个栅极驱动岛区301中的三个子栅极驱动电路形成8T2C电路。其中，第一方向D1与第二方向D2交叉设置。示例的，第一方向D1与第二方向D2垂直设置。
在示例性实施方式中，第三拉伸孔的形状和分布可以与第一拉伸孔的形状和分布相同或不同，第三拉伸孔的拉伸倍率与第一拉伸孔的拉伸倍率不同，本申请实施例在此不再赘述。
在示例性实施方式中，第一拉伸孔、第二拉伸孔和第三拉伸孔的拉伸倍率可以根据需求进行调解，可以相同或不同。
在示例性实施方式中，栅极驱动单元可以包括至少一条输出信号线，输出信号线的第一端与栅极驱动单元连接，输出信号线的第二端可以沿着第二方向D2延伸到平坦区中的第二像素电路区。输出信号线延伸到第二像素电路区后，可以与第二像素电路区中的扫描信号线或发光信号线连接，栅极驱动单元可以向第二像素电路区输出扫描信号或发光信号。
在示例性实施方式中，栅极驱动电路区与平坦区在第一方向上具有相同的中心轴线，即栅极驱动电路区在第二方向上位于平坦区的中部区域，从而方便的栅极驱动电路区的走线。
图11为本申请实施例显示基板中电路结构层的第二电源走线和第二电源扇出线的分布图。在示例性实施方式中，如图11所示，平坦区100还包括多条第二电源走线4以及多条第二电源扇出线5。多条第二电源走线4和多条第二电源扇出线5在所述衬底基板的正投影至少部分重叠。绑定区域500包括引线区900，引线区900可以包括多条引出线6。多条第二电源走线4配置为向第一像素电路区400以及平坦区100中的第二像素电路区输出第二电平信号。其中第二电平信号可以为高电平信号(VDD)。多条第二电源扇出线5与一部分第二电源走线4对应连接，配置为使一部分第二电源走线4与绑定区域500中的多条引出线6对应连接。
在示例性实施方式中，图11所示，多条第二电源走线4沿着第一方向D1延伸，并沿着第二方向D2间隔设置。相邻第二电源走线4之间的间距沿着靠近平坦区100在第一方向上的中心轴线逐渐变小。即多条第二电源走线4的密度沿着靠近平坦区100在第一方向上的中心轴线逐渐变大。其中，第一方向D1与第二方向D2交叉设置。示例的，第一方向D1与第二方向D2垂直设置。
电路结构层上的像素电路形成多个像素电路行和多个像素电路列。多条第二电源走线4沿着第一方向D1延伸，并沿着第二方向D2以设定的间隔顺序设置，每条第二电源走线与电路结构层中一个像素电路列的所有像素电路连接。
在示例性实施方式中，每条第二电源扇出线5的第一端与引线区501的一部分引出线6对应连接，每条第二电源扇出线5的第二端与一部分第二电源走线4对应连接。引线区900中的一部分引出线6与第二电源扇出线5连接，另一部分引出线6与另一部分第二电源走线4对应连接。
在示例性实施方式中，任意一条引出线6在衬底基板的正投影与其它引出线6在衬底基板的正投影没有重叠区域，任意一条第二电源扇出线5在衬底基板上的正投影与其它第二电源扇出线5在衬底基板上的正投影没有重叠 区域。
本公开实施例还提供了一种显示装置，包括前述实施例的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、广告面板、手表电话、电子书便携式多媒体播放器或物联网各种产品的显示屏等任何具有显示功能的产品或部件。在示例性实施方式中，显示装置可以为穿戴式显示装置，能通过某些方式佩戴在人体上，如智能手表、智能手环等。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (20)

  1. 一种显示基板，包括衬底基板和设置在所述衬底基板上的电路结构层，所述电路结构层包括平坦区以及设置在所述平坦区至少一侧的可弯折区，所述可弯折区包括至少一个拉伸区，所述拉伸区包括第一像素电路区以及第一电源走线区，所述第一电源走线区位于所述第一像素电路区远离所述平坦区一侧，所述第一电源走线区中设置有第一拉伸孔，所述第一像素电路区中设置有第二拉伸孔。
  2. 根据权利要求1所述的显示基板，其中，所述第一电源走线区包括第一电源走线，所述第一电源走线沿着平行于所述拉伸区边缘的方向延伸。
  3. 根据权利要求2所述的显示基板，其中，所述第一电源走线包括沿所述衬底基板厚度方向依次层叠设置的第一导电层、连接导电层以及第二导电层，所述第一导电层和所述第二导电层通过所述连接导电层桥接。
  4. 根据权利要求3所述的显示基板，其中，所述第一导电层与所述连接导电层之间设置有第一绝缘层，所述第一绝缘层中设置有第一过孔，所述连接导电层通过所述第一过孔与所述第一导电层连接，所述第二导电层与所述连接导电层之间设置有第二绝缘层，所述第二绝缘层中设置有第二过孔，所述连接导电层通过所述第二过孔与所述第一导电层连接。
  5. 根据权利要求1所述的显示基板，其中，所述第一拉伸孔包括第一方向拉伸孔和第二方向拉伸孔，所述第一方向拉伸孔是沿着第一方向延伸的条形状孔，所述第二方向拉伸孔是沿着第二方向延伸的条形状孔，所述第一方向拉伸孔在所述衬底基板的垂直投影与所述第二方向拉伸孔在所述衬底基板的垂直投影不交叠，所述第一方向拉伸孔的数目为多个，多个第一方向拉伸孔沿着所述第一方向间隔排布形成第一方向拉伸孔行，一个第一方向拉伸孔行中相邻的第一方向拉伸孔之间设置有第二方向拉伸孔；和/或，所述第二方向拉伸孔的数目为多个，多个第二方向拉伸孔沿着所述第二方向间隔排布形成第二方向拉伸孔行，一个第二方向拉伸孔行中相邻的第二方向拉伸孔之间设置有第一方向拉伸孔，所述第一方向与所述第二方向交叉设置。
  6. 根据权利要求1所述的显示基板，其中，所述第一拉伸孔包括第一 方向拉伸孔和第二方向拉伸孔，所述第一方向拉伸孔是沿着第一方向延伸的工字形孔，所述第二方向拉伸孔是沿着第二方向延伸的工字形孔，所述第一方向拉伸孔在所述衬底基板的垂直投影与所述第二方向拉伸孔在所述衬底基板的垂直投影不交叠，所述第一方向拉伸孔的数目为多个，多个第一方向拉伸孔沿着所述第一方向间隔排布形成第一方向拉伸孔行，一个第一方向拉伸孔行中相邻的第一方向拉伸孔之间设置有第二方向拉伸孔；和/或，所述第二方向拉伸孔的数目为多个，多个第二方向拉伸孔沿着所述第二方向间隔排布形成第二方向拉伸孔行，一个第二方向拉伸孔行中相邻的第二方向拉伸孔之间设置有第一方向拉伸孔，所述第一方向与所述第二方向交叉设置。
  7. 根据权利要求8所述的显示基板，其中，所述第一方向拉伸孔和第二方向拉伸孔均包括相对设置的两个第一边部以及将所述两个第一边部连接的第二边部，所述两个第一边部与所述第二边部组成所述工字形孔，在一个第一方向拉伸孔行中，相邻的第一方向拉伸孔的第一边部边缘之间的距离大于所述第二方向拉伸孔的第一边部的长度；和/或，在一个第二方向拉伸孔行中，相邻的第二方向拉伸孔的第一边部边缘之间的距离大于所述第一方向拉伸孔的第一边部的长度。
  8. 根据权利要求8所述的显示基板，其中，所述第一方向拉伸孔和第二方向拉伸孔均包括相对设置的两个第一边部以及将所述两个第一边部连接的第二边部，所述两个第一边部与所述第二边部组成所述工字形孔，在一个第一方向拉伸孔行中，相邻的第一方向拉伸孔的第一边部边缘之间的距离小于等于所述第二方向拉伸孔的第一边部的长度；和/或，在一个第二方向拉伸孔行中，相邻的第二方向拉伸孔的第一边部边缘之间的距离小于等于所述第一方向拉伸孔的第一边部的长度。
  9. 根据权利要求1所述的显示基板，其中，所述拉伸区位于所述可弯折区的边角区域。
  10. 根据权利要求1所述的显示基板，其中，所述第一电源走线区为所述拉伸区远离所述平坦区一侧的边缘区域。
  11. 根据权利要求1所述的显示基板，其中，所述平坦区包括栅极驱动 电路区以及位于所述栅极驱动电路区至少一侧的第二像素电路区，所述栅极驱动电路区中设置有第三拉伸孔。
  12. 根据权利要求11所述的显示基板，其中，所述第三拉伸孔的形状与所述第一拉伸孔的形状相同或不同，所述第三拉伸孔的拉伸倍率与所述第一拉伸孔的拉伸倍率不同。
  13. 根据权利要求11所述的显示基板，其中，所述栅极驱动电路区包括至少一个子栅极驱动电路区，所述子栅极驱动电路包括级联的多个栅极驱动单元，多个栅极驱动单元沿着第一方向依次排布，所述栅极驱动单元包括级联的多个栅极驱动岛区、位于相邻栅极驱动岛区之间的所述第三拉伸孔以及使相邻栅极驱动岛区彼此连接的布线区，多个栅极驱动岛区沿着第二方向依次排布，所述第一方向与所述第二方向交叉。
  14. 根据权利要求13所述的显示基板，其中，所述子栅极驱动电路还包括输出信号线，所述输出信号线的第一端与所述栅极驱动单元连接，所述输出信号线的第二端延伸至所述第二像素电路区。
  15. 根据权利要求13所述的显示基板，其中，所述栅极驱动电路区与所述平坦区在所述第一方向上具有相同的中心轴线。
  16. 根据权利要求1所述的显示基板，其中，所述平坦区还包括多条第二电源走线以及多条第二电源扇出线，多条第二电源走线和多条第二电源扇出线在所述衬底基板的正投影至少部分重叠；所述多条第二电源扇出线与至少部分所述多条第二电源走线对应连接。
  17. 根据权利要求16所述的显示基板，其中，所述电路结构层还包括设置在所述平坦区一侧的绑定区域，所述绑定区域至少包括引线区，所述引线区包括多条引出线，所述至少一条第二电源扇出线的第一端与所述引出线连接，所述至少一条第二电源扇出线的第二端与所述第二电源扇出线连接。
  18. 根据权利要求16所述的显示基板，其中，所述多条第二电源走线沿着第一方向延伸，并沿着第二方向间隔设置，相邻第二电源走线之间的间距沿着靠近所述平坦区在所述第一方向上的中心轴线逐渐变小；所述第一方向与所述第二方向交叉设置。
  19. 根据权利要求1-18任一项所述的显示基板，其中，所述第二拉伸孔的形状与所述第一拉伸孔的形状相同或不同，所述第二拉伸孔的拉伸倍率与所述第一拉伸孔的拉伸倍率不同。
  20. 一种显示装置，包括如权利要求1至19任一项所述的显示基板。
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CN112992995A (zh) * 2021-02-08 2021-06-18 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN113193028A (zh) * 2021-04-28 2021-07-30 京东方科技集团股份有限公司 显示装置及其显示面板
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