WO2021102791A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

Info

Publication number
WO2021102791A1
WO2021102791A1 PCT/CN2019/121570 CN2019121570W WO2021102791A1 WO 2021102791 A1 WO2021102791 A1 WO 2021102791A1 CN 2019121570 W CN2019121570 W CN 2019121570W WO 2021102791 A1 WO2021102791 A1 WO 2021102791A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
electrode
light
signal line
line
Prior art date
Application number
PCT/CN2019/121570
Other languages
English (en)
French (fr)
Inventor
魏玉龙
董向丹
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2019/121570 priority Critical patent/WO2021102791A1/zh
Priority to CN201980002688.8A priority patent/CN113261106B/zh
Priority to US16/977,273 priority patent/US11721282B2/en
Publication of WO2021102791A1 publication Critical patent/WO2021102791A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/813—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors

Definitions

  • At least one embodiment of the present disclosure relates to a display substrate and a display device.
  • At least one embodiment of the present disclosure relates to a display substrate and a display device.
  • the display substrate includes: a base substrate including a display area; a plurality of pixel units located in the display area, the pixel units including a pixel circuit structure and a light emitting
  • the light-emitting element includes a first electrode, the first electrode is located on a side of the pixel circuit structure away from the base substrate, and the plurality of pixel units include first pixels adjacent to each other in a first direction Unit and second pixel unit; first initialization signal line, extending along the first direction; light emission control signal line, extending along the first direction; first power line, extending along the second direction, the second direction Crosses the first direction; a first data line extends along the second direction, and the first data line is connected to the pixel circuit structure of the first pixel unit; a second data line extends along the second Extending in the direction, the second data line is connected to the pixel circuit structure of the second pixel unit; the first data line and the second data line are separately provided on both sides
  • the distance from the second data line to the first power line is greater than the distance from the first data line to the first power line.
  • the pixel circuit structure further includes a first light-emission control transistor and a second light-emission control transistor, the first light-emission control transistor includes a first electrode and a second electrode, and the first electrode and the second electrode of the first light-emission control transistor The two poles are respectively located on the first side and the second side of the light emission control line; the second light emission control transistor includes a first electrode and a second electrode, and the second electrode and the first electrode of the second light emission control transistor are respectively Located at the first side and the second side of the light-emitting control line; the first side and the second side are opposite sides of the light-emitting control signal line; the light-transmitting hole is located at the Between the first pole of the first light-emitting control transistor and the second pole of the second light-emitting control transistor.
  • the gate of the first light emission control transistor and the gate of the second light emission control transistor are both connected to the light emission control signal line.
  • the first light emission control transistor, the light transmission hole, and the second light emission control transistor are arranged along the first direction.
  • the pixel circuit structure further includes a driving transistor located on the second side of the light emission control signal line; the first electrode and the second electrode of the first light emission control transistor are connected to the first power line and The first electrode of the driving transistor is electrically connected; the first electrode and the second electrode of the second light-emitting control transistor are electrically connected to the second electrode of the driving transistor and the first electrode of the light-emitting element, respectively.
  • a driving transistor located on the second side of the light emission control signal line; the first electrode and the second electrode of the first light emission control transistor are connected to the first power line and The first electrode of the driving transistor is electrically connected; the first electrode and the second electrode of the second light-emitting control transistor are electrically connected to the second electrode of the driving transistor and the first electrode of the light-emitting element, respectively.
  • the display substrate further includes a second initialization signal line, a first reset control signal line, and a second reset control signal line
  • the pixel circuit structure further includes a first reset transistor and a second reset transistor;
  • the gate is electrically connected to the first reset control signal line, the first electrode of the first reset transistor is electrically connected to the second initialization signal line through the first connection electrode, and the second electrode of the first reset transistor
  • the gate of the second reset transistor is electrically connected to the second reset control signal line through the second connecting electrode; the first electrode of the second reset transistor passes through the third
  • the connecting electrode is electrically connected to the first initialization signal line, and the second electrode of the second reset transistor is electrically connected to the first electrode of the light-emitting element.
  • the second initialization signal line extends in the first direction
  • the first reset control signal line extends in the first direction
  • the second reset control signal line extends in the first direction
  • the light-transmitting hole is also located between the driving transistor and the second reset transistor.
  • the driving transistor and the second reset transistor are respectively disposed on two sides of the light transmission hole opposite to each other in the second direction.
  • the second reset control signal line, the first initialization signal line, the light emission control signal line, the first reset control signal line, and the second initialization signal line are sequentially arranged along the second direction.
  • first initialization signal line and the second initialization signal line are electrically connected, or the first initialization signal line and the second initialization signal line are configured to apply the same signal.
  • the display substrate further includes a gate line and a second power line
  • the pixel circuit structure further includes a storage capacitor, a data writing transistor, and a threshold compensation transistor;
  • the first electrode of the storage capacitor is electrically connected to the first power line
  • the second electrode of the storage capacitor is electrically connected to the second electrode of the threshold compensation transistor through the second connecting electrode;
  • the gate of the data writing transistor is electrically connected to the gate line, and the first The first electrode and the second electrode of the data writing transistor of the pixel unit are respectively electrically connected to the first data line and the first electrode of the driving transistor of the first pixel unit;
  • the gate is electrically connected to the gate line, the first electrode of the threshold compensation transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the threshold compensation transistor is electrically connected to the second electrode through the second connection electrode.
  • the gate of the driving transistor is electrically connected;
  • the second electrode of the light-emitting element is electrically connected to the second power line.
  • the edge of the first power line close to the first data line has the same distance from the first data line at each position.
  • the gate line extends in a first direction, and the gate line is located between the light emission control signal line and the first reset control signal line.
  • the second reset control signal line and the gate line are electrically connected, or the second reset control signal line and the gate line are configured to apply the same signal.
  • first connection electrode, the second connection electrode, the third connection electrode, the first data line, the second data line, and the first power line are located on the same layer.
  • the size of the light-transmitting hole in the first direction is 5-15 ⁇ m
  • the size of the light-transmitting hole in the second direction is 5-15 ⁇ m.
  • At least one embodiment of the present disclosure further provides a display device including any of the above-mentioned display substrates.
  • the display substrate includes: a pixel circuit structure, the pixel circuit structure includes a first light-emission control transistor and a second light-emission control transistor; a light-emission control signal line, the The gate of the first light-emitting control transistor and the gate of the second light-emitting control transistor are both connected to the light-emitting control signal line; the light-emitting element includes a first electrode, and the first electrode is located far away from the pixel circuit structure One side of the base substrate; and a light-transmitting hole, located between the first light-emitting control transistor and the second light-emitting control transistor, the light-transmitting hole in the orthographic projection of the base substrate and the first The orthographic projections of the electrodes on the base substrate do not overlap.
  • the distance between the first data line and the first power line is smaller than the distance between the second data line and the first power line.
  • the light emission control signal line extends in a first direction, and the first light emission control transistor, the light transmission hole, and the second light emission control transistor are arranged in the first direction.
  • the display substrate further includes a first power line
  • the light transmission hole is located on the first side of the light emission control signal line
  • the pixel circuit structure further includes a drive transistor located on the second side of the light emission control signal line, The first side and the second side are opposite sides of the light emission control signal line; the first electrode and the second electrode of the first light emission control transistor are connected to the first power line and the The first electrode of the driving transistor is electrically connected; the first electrode and the second electrode of the second light-emitting control transistor are electrically connected to the second electrode of the driving transistor and the first electrode of the light-emitting element, respectively;
  • the power line extends in a second direction, and the second direction intersects the first direction.
  • the display substrate further includes a first initialization signal line, a second initialization signal line, a first reset control signal line, and a second reset control signal line
  • the pixel circuit structure further includes a first reset transistor and a second reset transistor
  • the gate of the first reset transistor is electrically connected to the first reset control signal line
  • the first electrode of the first reset transistor is electrically connected to the second initialization signal line through a first connection electrode
  • the The second electrode of the first reset transistor is electrically connected to the gate of the driving transistor through a second connection electrode
  • the gate of the second reset transistor is electrically connected to the second reset control signal line
  • the second reset The first electrode of the transistor is electrically connected to the first initialization signal line through a third connection electrode
  • the second electrode of the second reset transistor is electrically connected to the first electrode of the light-emitting element.
  • the first initialization signal line extends in the first direction
  • the second initialization signal line extends in the first direction
  • the first reset control signal line extends in the first direction
  • the second reset control signal line extends along the first direction
  • the light-transmitting hole is also located between the driving transistor and the second reset transistor.
  • the driving transistor and the second reset transistor are respectively disposed on two sides of the light transmission hole opposite to each other in the second direction.
  • the light-transmitting hole is also located between the first initialization signal line and the light-emitting control signal line.
  • the second reset control signal line, the first initialization signal line, the light emission control signal line, the first reset control signal line, and the second initialization signal line are sequentially arranged along the second direction.
  • first initialization signal line and the second initialization signal line are electrically connected, or the first initialization signal line and the second initialization signal line are configured to apply the same signal.
  • the display substrate further includes a gate line, a data line, and a second power line
  • the pixel circuit structure further includes a storage capacitor, a data writing transistor, and a threshold compensation transistor
  • the first electrode of the storage capacitor and the first power supply The second electrode of the storage capacitor is electrically connected to the second electrode of the threshold compensation transistor through the second connection electrode
  • the gate of the data writing transistor is electrically connected to the gate line, so The first electrode and the second electrode of the data writing transistor are respectively electrically connected to the data line and the first electrode of the driving transistor
  • the gate of the threshold compensation transistor is electrically connected to the gate line
  • the threshold The first electrode of the compensation transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the threshold value compensation transistor is electrically connected to the gate of the driving transistor through the second connecting electrode
  • the second electrode is electrically connected with the second power line.
  • the edge of the first power line close to the data line has the same distance from the data line at each position.
  • the gate line extends in a first direction, and the gate line is located between the light emission control signal line and the first reset control signal line.
  • the data line extends in the second direction
  • the first power line extends in the second direction
  • the second reset control signal line and the gate line are electrically connected, or the second reset control signal line and the gate line are configured to apply the same signal.
  • first connection electrode, the second connection electrode, the third connection electrode, the data line, and the first power line are located on the same layer.
  • the size of the light-transmitting hole in the first direction is 5-15 ⁇ m
  • the size of the light-transmitting hole in the second direction is 5-15 ⁇ m.
  • At least one embodiment of the present disclosure further provides a display device including any of the above-mentioned display substrates.
  • FIG. 1 is a schematic diagram of a pixel circuit structure of a display panel provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure
  • 3A is a schematic partial top view of a display substrate provided by an embodiment of the present disclosure.
  • 3B is a schematic partial top view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 4A is a schematic diagram of a semiconductor pattern layer formed in a manufacturing method of a display substrate provided by an embodiment of the present disclosure
  • 4B is a schematic diagram of the first conductive pattern layer formed on the first insulating layer in the manufacturing method of the display substrate provided by an embodiment of the present disclosure
  • 4C is a schematic structural diagram of a semiconductor pattern layer after conducting a conductorization treatment by a self-alignment process in a manufacturing method of a display substrate provided by an embodiment of the present disclosure
  • 4D is a schematic diagram of a second conductive pattern layer formed on an intermediate layer of a second insulating film in a manufacturing method of a display substrate provided by an embodiment of the present disclosure
  • 4E is a schematic diagram of forming a third insulating film layer on the second conductive pattern layer and forming a via hole in the third insulating film layer in the manufacturing method of the display substrate provided by an embodiment of the present disclosure
  • 4F is a schematic diagram of a third conductive pattern layer formed on the third insulating layer in the manufacturing method of the display substrate provided by an embodiment of the present disclosure
  • Figure 5A is a cross-sectional view at A-B in Figure 3A;
  • FIG. 5B is a cross-sectional view at A-B of the display substrate shown in FIG. 3A according to another embodiment of the present disclosure
  • Figure 6 is a cross-sectional view at E-F in Figure 3A;
  • Figure 7A is a cross-sectional view at M-N in Figure 3A;
  • Figure 7B is a cross-sectional view at J-K in Figure 3A;
  • Figure 7C is a cross-sectional view at X-Y in Figure 3A;
  • FIG. 8A is a schematic diagram of electrical connection between a first initialization signal line and a second initialization signal line in a display substrate provided by an embodiment of the present disclosure
  • FIG. 8B is a schematic diagram of the electrical connection between the second reset control signal line and the gate line in the display substrate provided by an embodiment of the present disclosure.
  • FIG. 9 is a timing signal diagram of a pixel unit in a display panel provided by an embodiment of the disclosure.
  • the usual under-screen fingerprint recognition scheme designed by the principle of small hole imaging is as follows.
  • An imaging hole is designed in the pixel unit in the display area of the display panel.
  • fingerprint identification the light emitted by the light-emitting element in the display panel is reflected by the fingerprint, passes through the hole, and reaches the sensor, thereby realizing the fingerprint identification function.
  • the design space of a single pixel unit is getting smaller and smaller.
  • the pixel circuit structure of a single pixel unit includes multiple transistors, such as 7 or more transistors, the wiring design in the pixel unit is already close to the current process limit. Therefore, it is necessary to find a Design the best position of the imaging hole.
  • the pixel circuit structure includes a 7T1C pixel circuit structure, but is not limited to this.
  • the embodiment of the present disclosure takes the pixel circuit structure of 7T1C as an example for description.
  • FIG. 1 is a schematic diagram of a pixel circuit structure of a display panel provided by an embodiment of the disclosure.
  • FIG. 2 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure.
  • the display panel 100 includes a plurality of pixel units 101 arranged in a matrix.
  • Each pixel unit 101 includes a pixel circuit structure 10, a light emitting element 20, a gate line 113, a data line 311, and a voltage signal line.
  • the light-emitting element 20 is an organic light-emitting diode (OLED), and the light-emitting element 20 emits red light, green light, blue light, or white light under the driving of its corresponding pixel circuit structure 10.
  • OLED organic light-emitting diode
  • the voltage signal line may be one or more than one.
  • the voltage signal line includes a first power line 312, a second power line 14, a light-emitting control signal line 110, a first initialization signal line 212, a second initialization signal line 211, and a first reset control signal. At least one of the line 111 and the second reset control signal line 112 and the like.
  • the gate line 113 is configured to provide the scan signal SCAN to the pixel circuit structure 10.
  • the data line 311 is configured to provide a data signal DATA to the pixel circuit structure 10.
  • one pixel includes a plurality of pixel units.
  • One pixel may include a plurality of pixel units that emit light of different colors.
  • a pixel includes a pixel unit that emits red light, a pixel unit that emits green light, and a pixel unit that emits blue light, but it is not limited to this.
  • the number of pixel units included in a pixel and the light output of each pixel unit can be determined according to needs.
  • the first power line 312 is configured to provide a constant first voltage signal ELVDD to the pixel circuit structure 10
  • the second power line 14 is configured to provide a constant second voltage signal ELVSS to the pixel circuit structure 10
  • the first voltage signal ELVDD It is greater than the second voltage signal ELVSS.
  • the emission control signal line 110 is configured to provide an emission control signal EM to the pixel circuit structure 10.
  • the first initialization signal line 212 and the second initialization signal line 211 are configured to provide an initialization signal Vint to the pixel circuit structure 10
  • the first reset control signal line 111 is configured to provide a reset control signal RESET to the pixel circuit structure 10
  • the line 112 is configured to provide the scan signal SCAN to the pixel circuit structure 10.
  • the initialization signal Vint is a constant voltage signal, and its magnitude may be between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited thereto.
  • the initialization signal Vint may be less than or equal to the second voltage signal ELVSS.
  • the pixel circuit structure 10 includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a first reset transistor T6, and a second reset transistor.
  • the driving transistor T1 is electrically connected to the light-emitting element 20, and outputs a driving current to drive the light-emitting element 20 under the control of the scan signal SCAN, data signal DATA, first voltage signal ELVDD, and second voltage signal ELVSS provided by the gate line 113. Glow.
  • a driving transistor is connected to an organic light emitting element, and under the control of a data signal, a scan signal, and other signals, a driving current is output to the organic light emitting element to drive the organic light emitting element to emit light.
  • the display panel 100 provided by the embodiment of the present disclosure further includes: a data driving circuit 102 and a scan driving circuit 103.
  • the data driving circuit 102 is configured to provide a data signal DATA to the pixel unit 101 according to an instruction of the control circuit;
  • the scan driving circuit 103 is configured to provide a light emission control signal EM, a scan signal SCAN, and a reset control signal to the pixel unit 101 according to an instruction of the control circuit RESET and other signals.
  • the control circuit includes an external integrated circuit (IC), but is not limited thereto.
  • the scan driving circuit 103 is a GOA (Gate On Array) structure mounted on the display panel, or a driver chip (IC) structure that is bonded to the display panel.
  • GOA Gate On Array
  • the display panel 100 further includes a power source (not shown in the figure) to provide the above-mentioned voltage signal, which can be a voltage source or a current source as required, and the power source is configured to pass through the first power line 312 and the second power line 14 respectively.
  • the initialization signal lines (the second initialization signal line 211 and the first initialization signal line 212) provide the pixel unit 101 with the first power supply voltage ELVDD, the second power supply voltage ELVSS, and the initialization signal Vint, etc.
  • the display substrate includes a display area R1 and a peripheral area R2.
  • the peripheral area R2 surrounds the display area R1, but is not limited thereto.
  • FIG. 3A is a schematic partial top view of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate includes: a pixel circuit structure 10 and a light-transmitting hole 01.
  • the pixel circuit structure 10 includes a first light emission control transistor T4 and a second light emission control transistor T5.
  • the light-transmitting hole 01 is located between the first light-emitting control transistor T4 and the second light-emitting control transistor T5.
  • the display substrate further includes a light emission control signal line 110, and the gate T40 of the first light emission control transistor T4 and the gate T50 of the second light emission control transistor T5 are both connected to the light emission control signal line 110 .
  • a part of the light emission control signal line 110 serves as the gate T40 of the first light emission control transistor T4.
  • a part of the light emission control signal line 110 serves as the gate T50 of the second light emission control transistor T5.
  • the light emission control signal line 110 extends along the first direction X. Since the light-transmitting hole 01 is located between the first light-emitting control transistor T4 and the second light-emitting control transistor T5, the position of the light-transmitting hole in the first direction X is limited.
  • the first light emission control transistor T4, the light transmission hole 01, and the second light emission control transistor T5 are arranged along the first direction X.
  • the first electrode T41 of the first light emission control transistor T4 and the second electrode T52 of the second light emission control transistor T5 are located on the same side of the light emission control signal line 110, and the center of the first electrode T41 of the first light emission control transistor T4 and the second electrode T52 The line connecting the center of the second electrode T52 of the two light-emitting control transistors T5 passes through the light-transmitting hole 01.
  • the center of a certain element may refer to the center of its geometric shape, or the center of a certain element may refer to the center of gravity of its geometric shape, but is not limited to this.
  • the connection line between the center of the first pole T41 of the first light emission control transistor T4 and the center of the second pole T52 of the second light emission control transistor T5 is a dummy line.
  • the light-transmitting hole 01 is located on the first side of the light-emitting control signal line 110.
  • the first pole T41 of the first light emission control transistor T4 and the second pole T52 of the second light emission control transistor T5 are also located on the first side of the light emission control signal line 110.
  • the display substrate further includes a first power line 312 and a light emitting element 20.
  • the pixel circuit structure 10 further includes a driving transistor T1 located on the second side of the light emission control signal line 110, and the first side and the second side are opposite sides of the light emission control signal line 110.
  • the first side is the upper side of the light-emitting control signal line 110
  • the second side is the lower side of the light-emitting control signal line 110.
  • the first pole T41 and the second pole T42 of the first light emission control transistor T4 are electrically connected to the first power line 312 and the first pole T11 of the driving transistor T1, respectively.
  • the first electrode T51 and the second electrode T52 of the second light-emitting control transistor T5 are respectively electrically connected to the second electrode T12 of the driving transistor T1 and the first electrode 201 of the light-emitting element 20 (not shown in FIG. 3A, please refer to FIG. 1) .
  • the first power line 312 extends along the second direction Y, and the second direction Y intersects the first direction X.
  • the second direction Y is perpendicular to the first direction X, but it is not limited thereto.
  • the display substrate further includes a first initialization signal line 212, a second initialization signal line 211, a first reset control signal line 111, and a second reset control signal line 112
  • the pixel circuit structure 10 further includes a first The reset transistor T6 and the second reset transistor T7.
  • the gate T60 of the first reset transistor T6 is electrically connected to the first reset control signal line 111
  • the first electrode T61 of the first reset transistor T6 is electrically connected to the second initialization signal line 211 through the first connection electrode 31a
  • the second electrode T62 of T6 is electrically connected to the gate T10 of the driving transistor T1 through the second connecting electrode 31b.
  • the gate T70 of the second reset transistor T7 is electrically connected to the second reset control signal line 112
  • the first electrode T71 of the second reset transistor T7 is electrically connected to the first initialization signal line 212 through the third connection electrode 31c
  • the second reset transistor The second electrode T72 of T7 is electrically connected to the first electrode 201 (see FIG. 1) of the light-emitting element 20.
  • the gate T40 of the first light-emission control transistor T4 is electrically connected to the light-emission control signal line 110, and the first electrode T41 and the second electrode T42 of the first light-emission control transistor T4 are respectively connected to the first power line 312 is electrically connected to the first electrode T11 of the driving transistor T1.
  • the gate T50 of the second light emission control transistor T5 is electrically connected to the light emission control signal line 110, and the first electrode T51 and the second electrode T52 of the second light emission control transistor T5 are respectively connected to the second electrode T12 of the driving transistor T1 and the light emitting element 20
  • the first electrode 201 (see FIG. 1) is electrically connected.
  • the second electrode (which may be a common electrode of the OLED, such as a cathode) of the light-emitting element 20 is electrically connected to the second power line 14.
  • the transistors used in an embodiment of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain of the transistor can be structurally indistinguishable.
  • one pole is directly described as the first pole and the other pole is the second pole. Therefore, all or part of the first pole of the transistor in the embodiment of the present disclosure
  • the second pole is interchangeable according to needs.
  • the first electrode of the transistor described in the embodiment of the present disclosure may be a source and the second electrode may be a drain; or, the first electrode of the transistor may be a drain and the second electrode may be a source.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the transistors all adopt P-type transistors as an example for description. Based on the description and teaching of the implementation in the present disclosure, those of ordinary skill in the art can easily think of using N-type transistors in at least part of the transistors in the pixel circuit structure of the embodiments of the present disclosure without creative work, that is, using N-type transistors.
  • Type transistors or implementations of a combination of N-type transistors and P-type transistors therefore, these implementations are also within the protection scope of the present disclosure.
  • the second initialization signal line 211 extends along the first direction X
  • the first initialization signal line 212 extends along the first direction X
  • the first reset control signal line 111 extends along the first direction X
  • the second The reset control signal line 112 extends in the first direction X.
  • the light-transmitting hole 01 is also located between the driving transistor T1 and the second reset transistor T7.
  • the position of the light-transmitting hole is limited.
  • the driving transistor T1 and the second reset transistor T7 are respectively disposed on two sides of the light transmission hole 01 opposite to each other in the second direction Y.
  • the light transmission hole 01 is provided with a driving transistor T1 and a second reset transistor T7 on both sides in the second direction Y, respectively.
  • the light-transmitting hole 01 is also located between the first initialization signal line 212 and the light-emitting control signal line 110, so that the position of the light-transmitting hole in the second direction Y is limited.
  • the second reset control signal line 112 the first initialization signal line 212, the light emission control signal line 110, the first reset control signal line 111, and the second initialization signal line 211 are sequentially arranged along the second direction Y .
  • the display substrate further includes a gate line 113, a data line 311, and a second power line 14 (as shown in FIG. 1)
  • the pixel circuit structure 10 further includes a storage capacitor C1, a data writing transistor T2, and Threshold compensation transistor T3.
  • the first electrode C11 of the storage capacitor C1 is electrically connected to the first power line 312, and the second electrode C12 of the storage capacitor C1 is electrically connected to the second electrode T32 of the threshold compensation transistor T3 through the second connection electrode 31b.
  • the gate T20 of the data writing transistor T2 is electrically connected to the gate line 113, and the first electrode T21 and the second electrode T22 of the data writing transistor T2 are electrically connected to the data line 311 and the first electrode T11 of the driving transistor T1, respectively.
  • the gate T30 of the threshold compensation transistor T3 is electrically connected to the gate line 113, the first electrode T31 of the threshold compensation transistor T3 is electrically connected to the second electrode T12 of the driving transistor T1, and the second electrode T32 of the threshold compensation transistor T3 is electrically connected through the second connecting electrode.
  • 31b is electrically connected to the gate T10 of the driving transistor T1; the second electrode 202 (see FIG. 1) of the light-emitting element 20 is electrically connected to the second power line 14 (shown in FIG. 1).
  • the edge of the first power line 312 close to the data line 311 has the same distance from the data line 311 at each position.
  • the gate line 113 extends in the first direction X, and the gate line 113 is located between the light emission control signal line 110 and the first reset control signal line 111.
  • the gate line 113 is located between the storage capacitor C1 and the first reset control signal line 111.
  • the data line 311 extends in the second direction Y
  • the first power line 312 extends in the second direction Y.
  • the first power line 312 is electrically connected to the first electrode T41 of the first light emission control transistor T4 through the via hole VH2.
  • the second connection electrode 31b is connected to the second electrode T32 of the threshold compensation transistor T3 through a via hole VH21, and the second connection electrode 31b is connected to the gate T10 of the driving transistor T1 through a via hole VH22.
  • the size of the light-transmitting hole 01 in the first direction X is 5-15 ⁇ m
  • the size of the light-transmitting hole 01 in the second direction Y is 5-15 ⁇ m.
  • the size of the pixel unit in the first direction X is about 30 ⁇ m.
  • the size of the pixel unit in the second direction Y is about 60 ⁇ m.
  • the display substrate further includes a fourth connecting electrode 31d, and the fourth connecting electrode 31d is electrically connected to the second electrode T52 of the second light-emitting control transistor T5.
  • the fourth connecting electrode 31d can be used to electrically connect with the first electrode 201 (not shown in FIG. 3A, please refer to FIG. 1) of the light-emitting element 20 formed later.
  • the gate T40 of the first light emission control transistor T4 is a part of the light emission control signal line 110
  • the gate T50 of the second light emission control transistor T5 is a part of the light emission control signal line 110
  • the gate T20 of the data writing transistor T2 is a part of the gate line 113
  • the gate T30 of the threshold compensation transistor T3 is a part of the gate line 113
  • the gate T60 of the first reset transistor T6 is a part of the first reset control signal line 111.
  • the gate T70 of the second reset transistor T7 is a part of the second reset control signal line 112.
  • FIG. 3B is a schematic partial top view of a display substrate provided by an embodiment of the present disclosure. Compared with the display substrate shown in FIG. 3A, the display substrate shown in FIG. 3B is different in that: FIG. 3B shows two pixel units, namely: a first pixel unit P1 and a second pixel unit P2. FIG. 3A shows only one pixel unit. For example, the first pixel unit P1 and the second pixel unit P2 have the same structure. The second pixel unit P2 and the first pixel unit P1 are adjacent to each other along the first direction.
  • the data line 311 includes a first data line 3111 and a second data line 3112.
  • the first data line 3111 extends along the second direction Y, and the first data line 3111 is connected to the pixel circuit structure of the first pixel unit P1.
  • the second data line 3112 extends along the second direction, and the second data line 3112 is connected to the pixel circuit structure of the second pixel unit P2; the first data line 3111 and the second data line 3112 are separately arranged on both sides of the first power line 312.
  • the distance D1 between the first data line 3111 and the first power line 312 is smaller than the distance D2 between the second data line 3112 and the first power line 312.
  • the light-transmitting hole 01 is located in the area enclosed by the first initialization signal line 212, the light-emitting control signal line 110, the first power line 312, and the second data line 3112.
  • the orthographic projection of the light-transmitting hole 01 on the base substrate and the orthographic projection of the first electrode on the base substrate do not overlap.
  • FIG. 4A is a schematic diagram of a semiconductor pattern layer formed in a manufacturing method of a display substrate provided by an embodiment of the present disclosure.
  • the semiconductor pattern layer SCP is formed of a semiconductor material.
  • the manufacturing method of the display substrate provided by an embodiment of the present disclosure further includes forming a first insulating film layer on the semiconductor pattern layer SCP.
  • the first conductive pattern layer L1 includes a light emission control signal line 110, a first reset control signal line 111, a second reset control signal line 112, a gate line 113, and a gate T10 of the driving transistor T1.
  • the gate T10 of the driving transistor T1 also serves as the second electrode C12 of the storage capacitor C1.
  • FIG. 4C is a schematic structural diagram of a semiconductor pattern layer after a self-alignment process is used to conduct a conductive process in a manufacturing method of a display substrate provided by an embodiment of the present disclosure.
  • a self-aligned process is used to conduct a conductive process on the semiconductor pattern layer SCP using the first conductive pattern layer L1 as a mask, for example, the semiconductor pattern layer SCP is heavily doped by ion implantation , So that the portion of the semiconductor pattern layer SCP that is not covered by the first conductive pattern layer L1 is made conductive, forming the source region (first electrode T11) and drain region (second electrode T12) of the driving transistor T1, and data writing The source area (first electrode T21) and drain area (second electrode T22) of the transistor T2, the source area (first electrode T31) and the drain area (second electrode T32) of the threshold compensation transistor T3, the first The source region (first electrode T41) and drain region (second electrode T42) of the light emission
  • the portion of the semiconductor pattern layer SCP covered by the first conductive pattern layer L1 retains semiconductor characteristics, forming the channel region T14 of the driving transistor T1, the channel region T24 of the data writing transistor T2, the channel region T34 of the threshold compensation transistor T3, and the second A channel region T44 of the light emission control transistor T4, a channel region T54 of the second light emission control transistor T5, a channel region T64 of the first reset transistor T6, and a channel region T74 of the second reset transistor T7.
  • the second electrode T72 of the second reset transistor T7 and the second electrode T52 of the second light emission control transistor T5 are integrally formed; the first electrode T51 of the second light emission control transistor T5 and the first electrode T51 of the drive transistor T1 are formed integrally.
  • the two poles T12 and the first pole T31 of the threshold compensation transistor T3 are integrally formed; the first pole T11 of the driving transistor T1, the second pole T22 of the data writing transistor T2, and the second pole T42 of the first light-emitting control transistor T4 are integrally formed;
  • the second pole T32 of the threshold compensation transistor T3 and the second pole T62 of the first reset transistor T6 are integrally formed.
  • the first pole T71 of the second reset transistor T7 and the first pole T61 of the first reset transistor T6 may be integrally formed.
  • the channel region (active layer) of the transistor used in the embodiments of the present disclosure may be monocrystalline silicon, polycrystalline silicon (such as low-temperature polycrystalline silicon), or metal oxide semiconductor materials (such as IGZO, AZO, etc.).
  • the transistors are all P-type low temperature polysilicon (LTPS) thin film transistors.
  • the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are metal oxide semiconductor thin film transistors, that is, the channel material of the transistor is a metal oxide semiconductor material (such as IGZO). , AZO, etc.), the metal oxide semiconductor thin film transistor has a lower leakage current, which can help reduce the gate leakage current of the driving transistor T1.
  • the transistor used in the embodiments of the present disclosure may include various structures, such as a top gate type, a bottom gate type, or a double gate structure.
  • the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are double-gate thin film transistors, which can help reduce the gate leakage current of the driving transistor T1.
  • a second insulating film layer is formed on the structure after conducting the conductive treatment.
  • the second insulating film layer is not shown in the figure.
  • the second insulating film layer may cover the base substrate in a planar shape.
  • the second conductive pattern layer L2 includes a first initialization signal line 212, a first pole C11 of the storage capacitor C1, a second initialization signal line 211, and a connection element 214.
  • the first electrode C11 of the storage capacitor C1 has an opening 02 to facilitate the second connection electrode 31b to pass through the opening 02 to be electrically connected to the second electrode C12 of the storage capacitor C1.
  • the second connection electrode 31b and the first electrode C11 of the storage capacitor C1 are insulated from each other.
  • a third insulating film layer is formed on the second conductive pattern layer, and at least the first insulating film layer, the second insulating film layer, and the third insulating film layer are formed on the second conductive pattern layer.
  • the third insulating film layer may cover the base substrate in a planar shape.
  • the first insulating layer is a structure after a via hole is formed in the first insulating film layer.
  • the second insulating layer is a structure after a via hole is formed in the second insulating film layer.
  • the third insulating layer is a structure after a via hole is formed in the third insulating film layer.
  • the third insulating layer includes vias VH40, vias VH0, vias VH1, vias VH2, vias VH3, vias VH11, vias VH12, vias VH21, vias VH22, and vias VH31 And via VH32.
  • the third conductive pattern layer L3 includes a first connection electrode 31a, a second connection electrode 31b, a third connection electrode 31c, a fourth connection electrode 31d, a data line 311, and a first power supply line 312.
  • the dashed boxes in Figure 4F indicate the corresponding vias VH40, vias VH0, vias VH1, vias VH2, vias VH3, vias VH11, vias VH12, vias VH21, vias VH22, vias VH31 and vias Location of hole VH32.
  • FIG. 4F is a schematic diagram of the third conductive pattern layer formed on the third insulating layer in the manufacturing method of the display substrate provided by an embodiment of the present disclosure.
  • the third conductive pattern layer L3 includes a first connection electrode 31a, a second connection electrode 31b, a third connection electrode 31c, a fourth connection electrode 31d, a data line 311, and a first power supply line 312.
  • the dashed boxes in Figure 4F indicate the corresponding via
  • the first connection electrode 31a, the second connection electrode 31b, the third connection electrode 31c, the fourth connection electrode 31d, the data line 311, and the first power supply line 312 are located in the same layer.
  • the data line 311 is electrically connected to the first pole T21 of the data writing transistor T2 through the via hole VH1
  • the first power line 312 is electrically connected to the first pole T41 of the first light emitting control transistor T4 through the via hole VH2
  • the first power source The line 312 is electrically connected to the first pole C11 of the storage capacitor C1 through the via hole VH3
  • the first power line 312 is electrically connected to the connecting element 214 through the via hole VH0
  • the connecting element 214 is connected in parallel with the first power line 312 to reduce The role of small resistance.
  • One end of the first connection electrode 31a is electrically connected to the second initialization signal line 211 through the via hole VH11, and the other end of the first connection electrode 31a is connected to the first electrode T61 of the first reset transistor T6 through the via hole VH12, so that the first The first pole T61 of the reset transistor T6 is electrically connected to the second initialization signal line 211.
  • One end of the second connection electrode 31b is electrically connected to the second electrode T62 of the first reset transistor T6 through the via hole VH21, and the other end of the second connection electrode 31b is connected to the gate T10 of the driving transistor T1 (that is, the storage capacitor) through the via hole VH22.
  • the second electrode C12 of C1 is electrically connected, so that the second electrode T62 of the first reset transistor T6 is electrically connected to the gate T10 of the driving transistor T1 (that is, the second electrode C12 of the storage capacitor C1).
  • One end of the third connection electrode 31c is electrically connected to the first initialization signal line 212 through the via hole VH31, and the other end of the third connection electrode 31c is electrically connected to the first electrode T71 of the second reset transistor T7 through the via hole VH32, so that the The first pole T71 of the second reset transistor T7 is electrically connected to the first initialization signal line 212.
  • the control transistor T5 constitutes the 7 transistors shown in FIG. 1, that is, constitutes the 7 transistors in the pixel circuit structure in a pixel unit.
  • the first conductive pattern layer L1, the second conductive pattern layer L2, and the third conductive pattern layer L3 are all made of metal materials.
  • the first conductive pattern layer L1 is formed of the same metal material using the same patterning process
  • the second conductive pattern layer L2 is formed of the same metal material using the same patterning process
  • the third conductive pattern layer L3 is formed of the same metal material using the same patterning process.
  • metal materials include aluminum metal and titanium metal, but are not limited thereto.
  • the first conductive pattern layer L1, the second conductive pattern layer L2, and the third conductive pattern layer L3 may adopt a three-layer metal structure of titanium-aluminum-titanium, but is not limited thereto.
  • Fig. 5A is a cross-sectional view at A-B in Fig. 3A.
  • a buffer layer BL is provided on the base substrate BS, and the second electrode T52 of the second light emission control transistor T5 and the first electrode T41 of the first light emission control transistor T4 are provided on the buffer layer BL.
  • the second electrode T52 of the light emission control transistor T5 and the first electrode T41 of the first light emission control transistor T4 are provided with a first insulating layer IS1, a second insulating layer IS2, and a third insulating layer IS3.
  • a via hole VH2 is formed in the first insulating layer IS1, the second insulating layer IS2, and the third insulating layer IS3, and the first power line 312 is electrically connected to the first electrode T41 of the first light emitting control transistor T4 through the via hole VH2.
  • a data line 311 is also provided on the third insulating layer IS3.
  • a fourth connecting electrode 31d is also provided on the third insulating layer IS3. As shown in FIGS. 3A and 5A, the fourth connection electrode 31d is electrically connected to the second electrode T52 of the second light emission control transistor T5 through the via hole VH40.
  • FIG. 5B is a cross-sectional view at A-B of the display substrate shown in FIG. 3A according to another embodiment of the present disclosure.
  • the embodiment shown in FIG. 5B shows the first electrode 201, the second electrode 202, and the organic layer 2012 located between the first electrode 201 and the second electrode 202.
  • the organic layer 2012 includes a light-emitting layer.
  • the organic layer 2012 further includes at least one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer, but is not limited thereto.
  • the first electrode 201, the second electrode 202, and the organic layer 2012 constitute the light-emitting element 20.
  • the light emitted by the light-emitting element 20 is reflected by the finger FG, and then passes through the light-transmitting hole 01 to reach the sensor, thereby realizing the fingerprint recognition function.
  • Finger FG includes ridges and valleys.
  • the sensor may be located between the base substrate and the thin film transistor.
  • the sensor can also be located on the side of the base substrate away from the thin film transistor.
  • the first electrode 201 is the anode of the light-emitting element 20 and the second electrode 202 is the cathode of the light-emitting element 20.
  • the first electrode 201 can be made of a transparent conductive material and a metal material
  • the second electrode 202 can be made of a transparent or semi-transparent conductive material.
  • the first electrode 201 may use at least one of transparent conductive metal oxide and silver, but is not limited thereto.
  • the transparent conductive metal oxide includes indium tin oxide (ITO), but is not limited thereto.
  • the first electrode 201 may adopt a structure in which three sub-layers of ITO-Ag-ITO are arranged.
  • the second electrode may be a low work function metal, and at least one of magnesium and silver may be used, but is not limited thereto.
  • the material of the second electrode includes magnesium aluminum alloy (MgAl), lithium aluminum alloy (LiAl), or magnesium, aluminum, lithium metal, or the like.
  • the first electrode 201 in order to avoid stray light from affecting fingerprint recognition, is an opaque electrode, but it is not limited thereto.
  • the first electrode 201 is hollowed out at a position corresponding to the light-transmitting hole 01.
  • the orthographic projection of the light-transmitting hole 01 on the base substrate BS and the orthographic projection of the first electrode 201 on the base substrate BS do not overlap.
  • Fig. 6 is a cross-sectional view at E-F in Fig. 3A.
  • a buffer layer BL is provided on the base substrate BS, and the channel region T14 of the driving transistor T1, the first electrode T11 of the driving transistor T1, and the second electrode T12 of the driving transistor T1 are provided on the buffer layer BL.
  • a first insulating layer IS1 is provided on the channel region T14 of the driving transistor T1, the first electrode T11 of the driving transistor T1, and the second electrode T12 of the driving transistor T1, and the second insulating layer IS1 is provided with the second electrode of the storage capacitor C1.
  • the electrode C12 (that is, the gate T10 of the driving transistor T1), a second insulating layer IS2 is provided on the second electrode C12 of the storage capacitor C1, and the first electrode C11 of the storage capacitor C1 is provided on the second insulating layer IS2, A third insulating layer IS3 is provided on the first pole C11 of the storage capacitor C1.
  • the second connection electrode 31b, the first power line 312 and the data line 311 are provided on the third insulating layer IS3.
  • a via hole VH22 is provided in the second insulating layer IS2 and the third insulating layer IS3, and the second connection electrode 31b is electrically connected to the second electrode C12 of the storage capacitor C1 through the via hole VH22.
  • the second connection electrode 31b and the first pole C11 of the storage capacitor C1 are insulated from each other, and the second pole C12 of the storage capacitor C1 and the first pole C11 of the storage capacitor C1 are insulated from each other.
  • a via hole VH3 is provided in the third insulating layer IS3, and the first power line 312 is electrically connected to the first pole C11 of the storage capacitor C1 through the via hole VH3.
  • the base substrate BS is a transparent substrate.
  • the first insulating layer IS1, the second insulating layer IS2 and the third insulating layer IS3 are respectively made of insulating materials. Insulating materials include inorganic insulating materials and organic insulating materials. Inorganic insulating materials include, but are not limited to, silicon oxide, silicon nitride, and silicon oxynitride, and organic insulating materials include, but are not limited to, polyimide (PI).
  • Fig. 7A is a cross-sectional view at M-N in Fig. 3A.
  • a buffer layer BL is provided on the base substrate BS
  • a first electrode T71 of the second reset transistor T7 is provided on the buffer layer BL
  • a first electrode T71 is provided on the first electrode T71 of the second reset transistor T7.
  • the insulating layer IS1 is provided with a second reset control signal 112 on the first insulating layer IS1, a second insulating layer IS2 is provided on the second reset control signal 112, and a first initialization signal line 212 is provided on the second insulating layer IS2
  • a third insulating layer IS3 is provided on the first initialization signal line 212.
  • a via hole VH32 is provided in the first insulating layer IS1, the second insulating layer IS2, and the third insulating layer IS3, a via hole VH31 is provided in the third insulating layer IS3, and the third connecting electrode 31c passes through the via hole VH32 and the second The first pole T71 of the reset transistor T7 is electrically connected.
  • the third connection electrode 31c is electrically connected to the first initialization signal line 212 through the via hole VH31.
  • Fig. 7B is a cross-sectional view at J-K in Fig. 3A.
  • a buffer layer BL is provided on the base substrate BS
  • the first electrode T71 of the second reset transistor T7 is provided on the buffer layer BL
  • the first electrode T71 of the second reset transistor T7 is provided on the first electrode T71.
  • the insulating layer IS1 is provided with a first reset control signal 111 on the first insulating layer IS1, a second insulating layer IS2 is provided on the first reset control signal 111, and a second initialization signal line 211 is provided on the second insulating layer IS2 ,
  • a third insulating layer IS3 is provided on the second initialization signal line 211.
  • a via hole VH12 is provided in the first insulating layer IS1, the second insulating layer IS2, and the third insulating layer IS3, a via hole VH11 is provided in the third insulating layer IS3, and the first connecting electrode 31a passes through the via hole VH12 and the second The first pole T71 of the reset transistor T7 is electrically connected.
  • the first connection electrode 31a is electrically connected to the second initialization signal line 211 through the via hole VH11.
  • Fig. 7C is a cross-sectional view at X-Y in Fig. 3A.
  • the first power line 312 is electrically connected to the connecting element 214 through the via hole VH0.
  • the data line 311 is electrically connected to the first electrode T21 of the data writing transistor T2 through the via hole VH1.
  • One end of the second connection electrode 31b is electrically connected to the second electrode T62 of the first reset transistor T6 through the via hole VH21, and the other end of the second connection electrode 31b is connected to the gate T10 of the driving transistor T1 (that is, the storage capacitor) through the via hole VH22.
  • the second pole of C1 (C12) is electrically connected.
  • FIG. 8A is a schematic diagram of the electrical connection between the first initialization signal line and the second initialization signal line in the display substrate provided by an embodiment of the present disclosure.
  • the second initialization signal line 211 and the first initialization signal line 212 are electrically connected.
  • the display substrate includes a display area R1 and a peripheral area R2, and the second initialization signal line 211 and the first initialization signal line 212 are electrically connected through the first connection structure 81 located in the peripheral area R2.
  • the second initialization signal line 211 and the first initialization signal line 212 may be located on the same layer, and an insulating layer is provided between the first connection structure 81, and both ends of the first connection structure 81 pass through the via hole and the second initialization signal line.
  • the signal line 211 is connected to the first initialization signal line 212.
  • the second initialization signal line 211 and the first initialization signal line 212 may not be connected, but are configured to apply the same signal.
  • the first connection structure 81 may be located on the third conductive pattern layer L3, but it is not limited thereto.
  • FIG. 8B is a schematic diagram of the electrical connection between the second reset control signal line and the gate line in the display substrate provided by an embodiment of the present disclosure.
  • the second reset control signal line 112 and the gate line 113 are electrically connected.
  • the display substrate includes a display area R1 and a peripheral area R2, and the second reset control signal line 112 and the gate line 113 are electrically connected through a second connection structure 82 located in the peripheral area R2.
  • the second reset control signal line 112 and the gate line 113 may be located on the same layer, and an insulating layer is provided between the second connection structure 82, and both ends of the second connection structure 82 are connected to the second reset control signal through via holes respectively.
  • the line 112 and the gate line 113 are connected.
  • the second reset control signal line 112 and the gate line may not be connected, but are configured to apply the same signal.
  • the second connection structure 82 may be located on the third conductive pattern layer L3, but it is not limited thereto.
  • FIG. 9 is a timing signal diagram of a pixel unit in a display panel provided by an embodiment of the disclosure. The driving method of one pixel unit in the display panel provided by the embodiment of the present disclosure will be described below in conjunction with FIG. 1 and FIG. 9.
  • the driving method of the pixel unit includes a first reset stage t1, data writing and threshold compensation, a second reset stage t2, and a light-emitting stage t3.
  • the light-emitting control signal EM is set to the off voltage
  • the reset control signal RESET is set to the on voltage
  • the scan signal SCAN is set to the off voltage.
  • the light-emitting control signal EM is set to the off voltage
  • the reset control signal RESET is set to the off voltage
  • the scan signal SCAN is set to the on voltage.
  • the light-emitting control signal EM is set to the on voltage
  • the reset control signal RESET is set to the off voltage
  • the scan signal SCAN is set to the off voltage.
  • the first voltage signal ELVDD, the second voltage signal ELVSS, and the initialization signal Vint are all constant voltage signals, and the initialization signal Vint is between the first voltage signal ELVDD and the second voltage signal ELVSS.
  • the turn-on voltage in the embodiments of the present disclosure refers to the voltage that can turn on the first pole and the second stage of the corresponding transistor
  • the turn-off voltage refers to the voltage that can turn off the first pole and the second stage of the corresponding transistor.
  • the turn-on voltage is a low voltage (for example, 0V) and the turn-off voltage is a high voltage (for example, 5V);
  • the turn-on voltage is a high voltage (for example, 5V)
  • the turn-on voltage is a high voltage (for example, 5V).
  • the voltage is a low voltage (for example, 0V).
  • the driving waveforms shown in FIG. 9 are all explained by taking a P-type transistor as an example, that is, the turn-on voltage is a low voltage (for example, 0V), and the turn-off voltage is a high voltage (for example, 5V).
  • the first reset transistor T6 transmits the initialization signal (initialization voltage) Vint to the gate of the driving transistor T1 and is stored by the storage capacitor C1, resets the driving transistor T1 and eliminates the data stored during the last (previous frame) light emission.
  • the light emission control signal EM is the off voltage
  • the reset control signal RESET is the off voltage
  • the scan signal SCAN is the on voltage.
  • the data writing transistor T2 and the threshold compensation transistor T3 are in the on state
  • the second reset transistor T7 is in the on state
  • the second reset transistor T7 transmits the initialization signal Vint to the first electrode of the light emitting element 20 to emit light.
  • the element 20 is reset; and the first light-emission control transistor T4, the second light-emission control transistor T5, the first reset transistor T6, and the second reset transistor T7 are in an off state.
  • the data writing transistor T2 transmits the data signal voltage VDATA to the first pole of the driving transistor T1, that is, the data writing transistor T2 receives the scan signal SCAN and the data signal DATA and sends it to the first pole of the driving transistor T1 according to the scan signal SCAN. Write the data signal DATA.
  • the threshold compensation transistor T3 is turned on to connect the driving transistor T1 into a diode structure, thereby charging the gate of the driving transistor T1.
  • the gate voltage of the driving transistor T1 is VDATA+Vth, where VDATA is the data signal voltage, and Vth is the threshold voltage of the driving transistor T1, that is, the threshold compensation transistor T3 receives the scan signal SCAN and drives it according to the scan signal SCAN The gate voltage of the transistor T1 performs threshold voltage compensation.
  • the voltage difference across the storage capacitor C1 is ELVDD-VDATA-Vth.
  • the light-emitting control signal EM is the turn-on voltage
  • the reset control signal RESET is the turn-off voltage
  • the scan signal SCAN is the turn-off voltage.
  • the first light emission control transistor T4 and the second light emission control transistor T5 are in an on state
  • the data writing transistor T2, the threshold compensation transistor T3, the first reset transistor T6 and the second reset transistor T7 are in an off state.
  • the first power signal ELVDD is transmitted to the first pole of the driving transistor T1 through the first light-emitting control transistor T4, the gate voltage of the driving transistor T1 is maintained at VDATA+Vth, and the light-emitting current I passes through the first light-emitting control transistor T4, the driving transistor T1, and
  • the second light emission control transistor T5 flows into the light emitting element 20, and the light emitting element 20 emits light. That is, the first light-emission control transistor T4 and the second light-emission control transistor T5 receive the light-emission control signal EM, and control the light-emitting element 20 to emit light according to the light-emission control signal EM.
  • the luminous current I satisfies the following saturation current formula:
  • ⁇ n is the channel mobility of the drive transistor
  • Cox is the channel capacitance per unit area of the drive transistor T1
  • W and L are the channel width and channel length of the drive transistor T1, respectively
  • Vgs is the gate and source of the drive transistor T1 The voltage difference between the two poles (that is, the first pole of the driving transistor T1 in this embodiment).
  • the pixel circuit structure compensates the threshold voltage of the driving transistor T1 very well.
  • the ratio of the duration of the light-emitting phase t3 to the display period of one frame can be adjusted.
  • the luminous brightness can be controlled by adjusting the ratio of the duration of the luminous phase t3 to the display period of one frame.
  • the scan driving circuit 103 in the display panel or an additional driving circuit the ratio of the duration of the light-emitting phase t3 to the display time period of one frame can be adjusted.
  • the first reset transistor T6 or the second reset transistor T7 may not be provided, that is, the embodiments of the present disclosure are not limited to the specific pixel circuit shown in FIG. Compensated pixel circuit. Based on the description and teaching of the implementation manner in the present disclosure, other setting manners that a person of ordinary skill in the art can easily think of without creative work fall within the protection scope of the present disclosure.
  • the light-transmitting hole 01 in the direction perpendicular to the base substrate, the light-transmitting hole 01 has a certain size, so it is called a hole.
  • the light-transmitting hole 01 is an imaging hole, and the position of the light-transmitting hole 01 is not provided. Line to avoid affecting the light transmittance of the light-transmitting hole 01.
  • the first conductive pattern layer, the second conductive pattern layer, and the third conductive pattern layer are not provided with metal traces at the position of the light transmission hole 01 to form the light transmission hole 01.
  • the display device may include an OLED display and any product or component with a display function such as a TV, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, a navigator, and the like including an OLED display.
  • each element is only a schematic description, and is not limited to what is shown in the figure, and can be determined according to needs.
  • the patterning or patterning process may include only a photolithography process, or include a photolithography process and an etching step, or may include other processes for forming predetermined patterns such as printing and inkjet.
  • the photolithography process refers to the process including film formation, exposure, development, etc., using photoresist, mask, exposure machine, etc. to form patterns.
  • the corresponding patterning process can be selected according to the structure formed in the embodiment of the present disclosure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

提供一种显示基板和显示装置。该显示基板包括：衬底基板，包括显示区；多个像素单元，位于显示区中，像素单元包括像素电路结构和发光元件，发光元件包括第一电极，第一电极位于像素电路结构的远离衬底基板的一侧，多个像素单元包括沿第一方向相邻的第一像素单元和第二像素单元；第一初始化信号线，沿第一方向延伸；发光控制信号线，沿第一方向延伸；第一电源线，沿第二方向延伸，第二方向与第一方向交叉；第一数据线，沿第二方向延伸，第一数据线与第一像素单元的像素电路结构相连；第二数据线，沿第二方向延伸，第二数据线与第二像素单元的像素电路结构相连；第一数据线和第二数据线分设在第一电源线的两侧；透光孔，透光孔在衬底基板的正投影和第一电极在衬底基板的正投影不交叠；透光孔位于第一初始化信号线、发光控制信号线、第一电源线和第二数据线围成的区域内。

Description

显示基板和显示装置 技术领域
本公开至少一实施例涉及一种显示基板和显示装置。
背景技术
随着显示装置例如手机全面屏时代的到来，屏下指纹识别得到广泛的研究。
发明内容
本公开的至少一实施例涉及一种显示基板和显示装置。
一方面，本公开的至少一实施例提供一种显示基板，显示基板包括：衬底基板，包括显示区；多个像素单元，位于所述显示区中，所述像素单元包括像素电路结构和发光元件，所述发光元件包括第一电极，所述第一电极位于所述像素电路结构的远离所述衬底基板的一侧，所述多个像素单元包括沿第一方向相邻的第一像素单元和第二像素单元；第一初始化信号线，沿所述第一方向延伸；发光控制信号线，沿所述第一方向延伸；第一电源线，沿第二方向延伸，所述第二方向与所述第一方向交叉；第一数据线，沿所述第二方向延伸，所述第一数据线与所述第一像素单元的像素电路结构相连；第二数据线，沿所述第二方向延伸，所述第二数据线与所述第二像素单元的像素电路结构相连；所述第一数据线和所述第二数据线分设在所述第一电源线的两侧；透光孔，所述透光孔在所述衬底基板的正投影和所述第一电极在所述衬底基板的正投影不交叠；所述透光孔位于所述第一初始化信号线、所述发光控制信号线、所述第一电源线和所述第二数据线围成的区域内。
例如，所述第二数据线到所述第一电源线的距离大于所述第一数据线到所述第一电源线的距离。
例如，所述像素电路结构还包括第一发光控制晶体管和第二发光控制晶体管，所述第一发光控制晶体管包括第一极和第二极，所述第一发光控制晶体管的第一极和第二极分别位于所述发光控制线的第一侧和第二侧；所述第二发光控制晶体管包括第一极和第二极，所述第二发光控制晶体管的第二极 和第一极分别位于所述发光控制线的所述第一侧和所述第二侧；所述第一侧和所述第二侧为所述发光控制信号线的相对的两侧；所述透光孔位于所述第一发光控制晶体管的第一极和所述第二发光控制晶体管的第二极之间。
例如，所述第一发光控制晶体管的栅极和所述第二发光控制晶体管的栅极均与所述发光控制信号线相连。
例如，所述第一发光控制晶体管、所述透光孔和所述第二发光控制晶体管沿所述第一方向排列。
例如，所述像素电路结构还包括位于所述发光控制信号线的所述第二侧的驱动晶体管；所述第一发光控制晶体管的第一极与第二极分别与所述第一电源线和所述驱动晶体管的第一极电连接；所述第二发光控制晶体管的第一极与第二极分别与所述驱动晶体管的第二极、所述发光元件的第一电极电连接。
例如，显示基板还包括第二初始化信号线、第一复位控制信号线和第二复位控制信号线，所述像素电路结构还包括第一复位晶体管以及第二复位晶体管；所述第一复位晶体管的栅极与所述第一复位控制信号线电连接，所述第一复位晶体管的第一极通过第一连接电极与所述第二初始化信号线电连接，所述第一复位晶体管的第二极通过第二连接电极与所述驱动晶体管的栅极电连接；所述第二复位晶体管的栅极与所述第二复位控制信号线电连接，所述第二复位晶体管的第一极通过第三连接电极与所述第一初始化信号线电连接，所述第二复位晶体管的第二极与所述发光元件的第一电极电连接。
例如，所述第二初始化信号线沿所述第一方向延伸，所述第一复位控制信号线沿所述第一方向延伸，所述第二复位控制信号线沿所述第一方向延伸。
例如，所述透光孔还位于所述驱动晶体管和所述第二复位晶体管之间。
例如，所述驱动晶体管和所述第二复位晶体管分别设置在所述透光孔在所述第二方向上彼此相对的两侧。
例如，所述第二复位控制信号线、所述第一初始化信号线、所述发光控制信号线、所述第一复位控制信号线和所述第二初始化信号线沿第二方向依次排列。
例如，所述第一初始化信号线和所述第二初始化信号线电连接，或者，所述第一初始化信号线和所述第二初始化信号线被配置为施加同一信号。
例如，显示基板还包括栅线以及第二电源线，所述像素电路结构还包括存储电容、数据写入晶体管和阈值补偿晶体管；所述存储电容的第一极与所述第一电源线电连接，所述存储电容的第二极通过所述第二连接电极与所述阈值补偿晶体管的第二极电连接；所述数据写入晶体管的栅极与所述栅线电连接，所述第一像素单元的所述数据写入晶体管的第一极与第二极分别与所述第一数据线、所述第一像素单元的所述驱动晶体管的第一极电连接；所述阈值补偿晶体管的栅极与所述栅线电连接，所述阈值补偿晶体管的第一极与所述驱动晶体管的第二极电连接，所述阈值补偿晶体管的第二极通过所述第二连接电极与所述驱动晶体管的栅极电连接；所述发光元件的第二电极与所述第二电源线电连接。
例如，所述第一电源线的靠近所述第一数据线的边缘在各位置处与所述第一数据线之间的距离相等。
例如，所述栅线沿第一方向延伸，所述栅线位于所述发光控制信号线和所述第一复位控制信号线之间。
例如，所述第二复位控制信号线和所述栅线电连接，或者，所述第二复位控制信号线和所述栅线被配置为施加同一信号。
例如，所述第一连接电极、所述第二连接电极、所述第三连接电极、所述第一数据线、所述第二数据线和所述第一电源线位于同一层。
例如，所述透光孔在所述第一方向上的尺寸为5-15μm，所述透光孔在所述第二方向上的尺寸为5-15μm。
本公开的至少一实施例还提供一种显示装置，包括上述任一显示基板。
另一方面，本公开的至少一实施例提供一种显示基板，显示基板包括：像素电路结构，所述像素电路结构包括第一发光控制晶体管和第二发光控制晶体管；发光控制信号线，所述第一发光控制晶体管的栅极和所述第二发光控制晶体管的栅极均与所述发光控制信号线相连；发光元件，包括第一电极，所述第一电极位于所述像素电路结构的远离衬底基板的一侧；以及透光孔，位于所述第一发光控制晶体管和所述第二发光控制晶体管之间，所述透光孔在所述衬底基板的正投影和所述第一电极在所述衬底基板的正投影不交叠。
例如，所述第一数据线和所述第一电源线之间的距离小于所述第二数据线和所述第一电源线之间的距离。
例如，所述发光控制信号线沿第一方向延伸，所述第一发光控制晶体管、所述透光孔和所述第二发光控制晶体管沿所述第一方向排列。
例如，显示基板还包括第一电源线，所述透光孔位于所述发光控制信号线的第一侧，所述像素电路结构还包括位于所述发光控制信号线的第二侧的驱动晶体管，所述第一侧和所述第二侧为所述发光控制信号线的相对的两侧；所述第一发光控制晶体管的第一极与第二极分别与所述第一电源线和所述驱动晶体管的第一极电连接；所述第二发光控制晶体管的第一极与第二极分别与所述驱动晶体管的第二极、所述发光元件的第一电极电连接；所述第一电源线沿第二方向延伸，所述第二方向与所述第一方向相交。
例如，显示基板还包括第一初始化信号线、第二初始化信号线、第一复位控制信号线和第二复位控制信号线，其中，所述像素电路结构还包括第一复位晶体管以及第二复位晶体管；所述第一复位晶体管的栅极与所述第一复位控制信号线电连接，所述第一复位晶体管的第一极通过第一连接电极与所述第二初始化信号线电连接，所述第一复位晶体管的第二极通过第二连接电极与所述驱动晶体管的栅极电连接；所述第二复位晶体管的栅极与所述第二复位控制信号线电连接，所述第二复位晶体管的第一极通过第三连接电极与所述第一初始化信号线电连接，所述第二复位晶体管的第二极与所述发光元件的第一电极电连接。
例如，所述第一初始化信号线沿所述第一方向延伸，所述第二初始化信号线沿所述第一方向延伸，所述第一复位控制信号线沿所述第一方向延伸，所述第二复位控制信号线沿所述第一方向延伸。
例如，所述透光孔还位于所述驱动晶体管和所述第二复位晶体管之间。
例如，所述驱动晶体管和所述第二复位晶体管分别设置在所述透光孔在所述第二方向上彼此相对的两侧。
例如，所述透光孔还位于所述第一初始化信号线和所述发光控制信号线之间。
例如，所述第二复位控制信号线、所述第一初始化信号线、所述发光控制信号线、所述第一复位控制信号线和所述第二初始化信号线沿第二方向依次排列。
例如，所述第一初始化信号线和所述第二初始化信号线电连接，或者， 所述第一初始化信号线和所述第二初始化信号线被配置为施加同一信号。
例如，显示基板还包括栅线、数据线以及第二电源线；所述像素电路结构还包括存储电容、数据写入晶体管和阈值补偿晶体管；所述存储电容的第一极与所述第一电源线电连接，所述存储电容的第二极通过所述第二连接电极与所述阈值补偿晶体管的第二极电连接；所述数据写入晶体管的栅极与所述栅线电连接，所述数据写入晶体管的第一极与第二极分别与所述数据线、所述驱动晶体管的第一极电连接；所述阈值补偿晶体管的栅极与所述栅线电连接，所述阈值补偿晶体管的第一极与所述驱动晶体管的第二极电连接，所述阈值补偿晶体管的第二极通过所述第二连接电极与所述驱动晶体管的栅极电连接；所述发光元件的第二电极与所述第二电源线电连接。
例如，所述第一电源线的靠近所述数据线的边缘在各位置处与所述数据线之间的距离相等。
例如，所述栅线沿第一方向延伸，所述栅线位于所述发光控制信号线和所述第一复位控制信号线之间。
例如，所述数据线沿第二方向延伸，所述第一电源线沿第二方向延伸。
例如，所述第二复位控制信号线和所述栅线电连接，或者，所述第二复位控制信号线和所述栅线被配置为施加同一信号。
例如，所述第一连接电极、所述第二连接电极、所述第三连接电极、所述数据线和所述第一电源线位于同一层。
例如，所述透光孔在所述第一方向上的尺寸为5-15μm，所述透光孔在所述第二方向上的尺寸为5-15μm。
本公开的至少一实施例还提供一种显示装置，包括上述任一显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一实施例提供的一种显示面板的像素电路结构的原理图；
图2为本公开一实施例提供的一种显示面板的平面结构示意图；
图3A为本公开一实施例提供的一种显示基板的局部俯视示意图；
图3B为本公开一实施例提供的一种显示基板的局部俯视示意图；
图4A为本公开一实施例提供的显示基板的制作方法中形成的半导体图案层的示意图；
图4B为本公开一实施例提供的显示基板的制作方法中在第一绝缘层上形成的第一导电图案层的示意图；
图4C为本公开一实施例提供的显示基板的制作方法中对半导体图案层采用自对准工艺进行导体化处理后的结构示意图；
图4D为本公开一实施例提供的显示基板的制作方法中在第二绝缘薄膜中间层上形成的第二导电图案层的示意图；
图4E为本公开一实施例提供的显示基板的制作方法中在第二导电图案层上形成第三绝缘薄膜层，并在第三绝缘薄膜层中形成过孔的示意图；
图4F为本公开一实施例提供的显示基板的制作方法中在第三绝缘层上形成的第三导电图案层的示意图；
图5A为图3A中A-B处的剖视图；
图5B为本公开另一实施例提供的图3A所示的显示基板的A-B处的剖视图；
图6为图3A中E-F处的剖视图；
图7A为图3A中M-N处的剖视图；
图7B为图3A中J-K处的剖视图；
图7C为图3A中X-Y处的剖视图；
图8A为本公开一实施例提供的显示基板中的第一初始化信号线和第二初始化信号线电连接的示意图；
图8B为本公开一实施例提供的显示基板中的第二复位控制信号线和栅线电连接的示意图；以及
图9为本公开实施例提供的显示面板中一个像素单元的时序信号图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描 述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
通常的利用小孔成像原理设计的屏下指纹识别方案如下。在显示面板的显示区内的像素单元内设计成像小孔，指纹识别时，由显示面板中的发光元件发出的光经指纹反射经过小孔，到达传感器(sensor)上，从而实现指纹识别功能。为确保指纹功能效果，该小孔范围内不能有金属走线。
随着屏幕像素密度(Pixels Per Inch，PPI)的提升，单个像素单元的设计空间越来越小。例如，在有机发光二极管显示面板中，单个像素单元的像素电路结构包括多个晶体管例如7个或7个以上的晶体管时，像素单元内走线设计已经接近目前的工艺极限，从而，需要寻找一个设计成像小孔的最佳位置。例如，像素电路结构包括7T1C的像素电路结构，但不限于此。本公开的实施例以7T1C的像素电路结构为例进行说明。
图1为本公开一实施例提供的一种显示面板的像素电路结构的原理图。图2为本公开一实施例提供的一种显示面板的平面结构示意图。请一并参阅图1和图2，显示面板100包括呈矩阵排布的多个像素单元101，每个像素单元101包括像素电路结构10、发光元件20以及栅线113、数据线311及电压信号线。例如，发光元件20为有机发光二极管(OLED)，发光元件20在其对应的像素电路结构10的驱动下发出红光、绿光、蓝光，或者白光等。该电压信号线可以是一条也可以包括多条。例如，如图1所示，该电压信号线包括第一电源线312、第二电源线14、发光控制信号线110、第一初始化信号线212、第二初始化信号线211、第一复位控制信号线111和第二复位控制 信号线112等中的至少之一。栅线113配置为向像素电路结构10提供扫描信号SCAN。数据线311配置为向像素电路结构10提供数据信号DATA。例如，一个像素包括多个像素单元。一个像素可包括出射不同颜色光的多个像素单元。例如，一个像素包括出射红光的像素单元，出射绿光的像素单元和出射蓝光的像素单元，但不限于此。一个像素包括的像素单元的个数以及每个像素单元的出光情况可根据需要而定。
例如，第一电源线312配置为向像素电路结构10提供恒定的第一电压信号ELVDD，第二电源线14配置为向像素电路结构10提供恒定的第二电压信号ELVSS，并且第一电压信号ELVDD大于第二电压信号ELVSS。发光控制信号线110配置为向像素电路结构10提供发光控制信号EM。第一初始化信号线212和第二初始化信号线211配置为向像素电路结构10提供初始化信号Vint，第一复位控制信号线111配置为向像素电路结构10提供复位控制信号RESET，第二复位控制信号线112配置为向像素电路结构10提供扫描信号SCAN。初始化信号Vint为恒定的电压信号，其大小例如可以介于第一电压信号ELVDD和第二电压信号ELVSS之间，但不限于此，例如，初始化信号Vint可小于或等于第二电压信号ELVSS。
如图1所示，该像素电路结构10包括驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6、第二复位晶体管T7以及存储电容C1。驱动晶体管T1与发光元件20电连接，并在由栅线113提供的扫描信号SCAN、数据信号DATA、第一电压信号ELVDD、第二电压信号ELVSS等信号的控制下输出驱动电流以驱动发光元件20发光。
在有机发光二极管显示面板的像素单元中，驱动晶体管与有机发光元件连接，在数据信号、扫描信号等信号的控制下向有机发光元件输出驱动电流，从而驱动有机发光元件发光。
例如，如图2所示，本公开实施例提供的显示面板100还包括：数据驱动电路102和扫描驱动电路103。数据驱动电路102被配置为根据控制电路的指令向像素单元101提供数据信号DATA；扫描驱动电路103被配置为根据控制电路的指令向像素单元101提供发光控制信号EM、扫描信号SCAN以及复位控制信号RESET等信号。例如，控制电路包括外部集成电路(IC)， 但不限于此。例如，扫描驱动电路103为安装于该显示面板上的GOA(Gate On Array)结构，或者为与该显示面板进行绑定(Bonding)的驱动芯片(IC)结构。例如，还可以采用不同的驱动电路分别提供发光控制信号EM和扫描信号SCAN。例如，显示面板100还包括电源(图中未示出)以提供上述电压信号，根据需要可以为电压源或电流源，所述电源被配置为分别通过第一电源线312、第二电源线14、以及初始化信号线(第二初始化信号线211和第一初始化信号线212)向像素单元101提供第一电源电压ELVDD、第二电源电压ELVSS、以及初始化信号Vint等。
例如，如图2所示，显示基板包括显示区R1和周边区R2。例如，周边区R2围绕显示区R1，但不限于此。
图3A为本公开一实施例提供的一种显示基板的局部俯视示意图。如图1和图3A所示，显示基板包括：像素电路结构10以及透光孔01。像素电路结构10包括第一发光控制晶体管T4和第二发光控制晶体管T5。如图3A所示，透光孔01位于第一发光控制晶体管T4和第二发光控制晶体管T5之间。
本公开的实施例提供的显示基板，在保证工艺余量(margin)和像素电路结构功能的情况下，通过整体优化、调整像素单元内的图形(pattern)，得到一种较合理的透光孔01(成像小孔)的放置方案。
例如，如图1和图3A所示，显示基板还包括发光控制信号线110，第一发光控制晶体管T4的栅极T40和第二发光控制晶体管T5的栅极T50均与发光控制信号线110相连。例如，如图3A所示，发光控制信号线110的一部分作为第一发光控制晶体管T4的栅极T40。例如，如图3A所示，发光控制信号线110的一部分作为第二发光控制晶体管T5的栅极T50。如图3A所示，发光控制信号线110沿第一方向X延伸。因透光孔01位于第一发光控制晶体管T4和第二发光控制晶体管T5之间，则使得在第一方向X上，透光孔的位置得以限定。
例如，如图3A所示，第一发光控制晶体管T4、透光孔01和第二发光控制晶体管T5沿第一方向X排列。例如，第一发光控制晶体管T4的第一极T41和第二发光控制晶体管T5的第二极T52位于发光控制信号线110的同一侧，第一发光控制晶体管T4的第一极T41的中心和第二发光控制晶体管T5的第二极T52的中心的连线通过透光孔01。本公开的实施例中，某一元 件的中心可指其几何形状的中心，或者，某一元件的中心可指其几何形状的重心，但不限于此。第一发光控制晶体管T4的第一极T41的中心和第二发光控制晶体管T5的第二极T52的中心的连线为虚设的线。
例如，如图3A所示，透光孔01位于发光控制信号线110的第一侧。第一发光控制晶体管T4的第一极T41和第二发光控制晶体管T5的第二极T52也位于发光控制信号线110的第一侧。
例如，如图1和图3A所示，显示基板还包括第一电源线312和发光元件20。如图3A所示，像素电路结构10还包括位于发光控制信号线110的第二侧的驱动晶体管T1，第一侧和第二侧为发光控制信号线110的相对的两侧。如图3A所示，第一侧为发光控制信号线110的上侧，第二侧为发光控制信号线110的下侧。第一发光控制晶体管T4的第一极T41与第二极T42分别与第一电源线312和驱动晶体管T1的第一极T11电连接。第二发光控制晶体管T5的第一极T51与第二极T52分别与驱动晶体管T1的第二极T12、发光元件20的第一电极201(图3A中未示出，请参照图1)电连接。
例如，如图3A所示，第一电源线312沿第二方向Y延伸，第二方向Y与第一方向X相交。例如，第二方向Y与第一方向X垂直，但不限于此。
例如，如图3A所示，显示基板还包括第一初始化信号线212、第二初始化信号线211、第一复位控制信号线111和第二复位控制信号线112，像素电路结构10还包括第一复位晶体管T6以及第二复位晶体管T7。第一复位晶体管T6的栅极T60与第一复位控制信号线111电连接，第一复位晶体管T6的第一极T61通过第一连接电极31a与第二初始化信号线211电连接，第一复位晶体管T6的第二极T62通过第二连接电极31b与驱动晶体管T1的栅极T10电连接。第二复位晶体管T7的栅极T70与第二复位控制信号线112电连接，第二复位晶体管T7的第一极T71通过第三连接电极31c与第一初始化信号线212电连接，第二复位晶体管T7的第二极T72与发光元件20的第一电极201(参见图1)电连接。
如图1和图3A所示，第一发光控制晶体管T4的栅极T40与发光控制信号线110电连接，第一发光控制晶体管T4的第一极T41与第二极T42分别与第一电源线312和驱动晶体管T1的第一极T11电连接。第二发光控制晶体管T5的栅极T50与发光控制信号线110电连接，第二发光控制晶体管T5 的第一极T51与第二极T52分别与驱动晶体管T1的第二极T12、发光元件20的第一电极201(参见图1)电连接。发光元件20的第二电极(可为OLED的公共电极，例如阴极)与第二电源线14电连接。
需要说明的是，本公开一实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开一实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极，所以本公开实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。例如，本公开实施例所述的晶体管的第一极可以为源极，第二极可以为漏极；或者，晶体管的第一极为漏极，第二极为源极。
此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。本公开实施例以晶体管均采用P型晶体管为例进行说明。基于本公开对该实现方式的描述和教导，本领域普通技术人员在无需做出创造性劳动前提下，能够容易想到将本公开实施例的像素电路结构中至少部分晶体管采用N型晶体管，即采用N型晶体管或N型晶体管和P型晶体管组合的实现方式，因此，这些实现方式也是在本公开的保护范围内的。
例如，如图3A所示，第二初始化信号线211沿第一方向X延伸，第一初始化信号线212沿第一方向X延伸，第一复位控制信号线111沿第一方向X延伸，第二复位控制信号线112沿第一方向X延伸。
例如，如图3A所示，透光孔01还位于驱动晶体管T1和第二复位晶体管T7之间。从而，在第二方向Y上，透光孔的位置得以限定。
例如，驱动晶体管T1和第二复位晶体管T7分别设置在透光孔01在第二方向Y上彼此相对的两侧。例如，透光孔01在第二方向Y上的两侧分别设置驱动晶体管T1和第二复位晶体管T7。
例如，透光孔01还位于第一初始化信号线212和发光控制信号线110之间，使得在第二方向Y上，透光孔的位置得以限定。
例如，如图3A所示，第二复位控制信号线112、第一初始化信号线212、发光控制信号线110、第一复位控制信号线111和第二初始化信号线211沿第二方向Y依次排列。
如图1和图3A所示，显示基板还包括栅线113、数据线311以及第二电源线14(如图1所示)，像素电路结构10还包括存储电容C1、数据写入晶体管T2和阈值补偿晶体管T3。存储电容C1的第一极C11与第一电源线312电连接，存储电容C1的第二极C12通过第二连接电极31b与阈值补偿晶体管T3的第二极T32电连接。数据写入晶体管T2的栅极T20与栅线113电连接，数据写入晶体管T2的第一极T21与第二极T22分别与数据线311、驱动晶体管T1的第一极T11电连接。阈值补偿晶体管T3的栅极T30与栅线113电连接，阈值补偿晶体管T3的第一极T31与驱动晶体管T1的第二极T12电连接，阈值补偿晶体管T3的第二极T32通过第二连接电极31b与驱动晶体管T1的栅极T10电连接；发光元件20的第二电极202(参见图1)与第二电源线14(如图1所示)电连接。
例如，如图3A所示，为了利于形成透光孔01，第一电源线312的靠近数据线311的边缘在各位置处与数据线311之间的距离相等。
例如，如图3A所示，栅线113沿第一方向X延伸，栅线113位于发光控制信号线110和第一复位控制信号线111之间。例如，如图3A所示，栅线113位于存储电容C1和第一复位控制信号线111之间。
例如，如图3A所示，数据线311沿第二方向Y延伸，第一电源线312沿第二方向Y延伸。
例如，如图3A所示，第一电源线312通过过孔VH2与第一发光控制晶体管T4的第一极T41电连接。例如，如图3A所示，第二连接电极31b通过过孔VH21与阈值补偿晶体管T3的第二极T32相连，第二连接电极31b通过过孔VH22与驱动晶体管T1的栅极T10相连。
例如，如图3A所示，透光孔01在第一方向X上的尺寸为5-15μm，透光孔在第二方向Y上的尺寸为5-15μm。例如，像素单元在第一方向X上的尺寸约为30μm。例如，像素单元在第二方向Y上的尺寸约为60μm。
如图3A所示，显示基板还包括第四连接电极31d，第四连接电极31d与第二发光控制晶体管T5的第二极T52电连接。第四连接电极31d可用来与后续形成的发光元件20的第一电极201(图3A中未示出，请参照图1)电连接。
本公开的实施例中，如图3A所示，第一发光控制晶体管T4的栅极T40 为发光控制信号线110的一部分，第二发光控制晶体管T5的栅极T50为发光控制信号线110的一部分，数据写入晶体管T2的栅极T20为栅线113的一部分，阈值补偿晶体管T3的栅极T30为栅线113的一部分，第一复位晶体管T6的栅极T60为第一复位控制信号线111的一部分，第二复位晶体管T7的栅极T70为第二复位控制信号线112的一部分。
图3B为本公开一实施例提供的一种显示基板的局部俯视示意图。图3B所示的显示基板与图3A所示的显示基板相比，区别在于：图3B示出了两个像素单元，即：第一像素单元P1和第二像素单元P2。图3A仅示出了一个像素单元。例如，第一像素单元P1和第二像素单元P2的结构相同。第二像素单元P2和第一像素单元P1沿第一方向相邻。
如图3B所示，数据线311包括第一数据线3111和第二数据线3112。第一数据线3111沿第二方向Y延伸，第一数据线3111与第一像素单元P1的像素电路结构相连。第二数据线3112沿第二方向延伸，第二数据线3112与第二像素单元P2的像素电路结构相连；第一数据线3111和第二数据线3112分设在第一电源线312的两侧。如图3B所示，第一数据线3111和第一电源线312之间的距离D1小于第二数据线3112和第一电源线312之间的距离D2。
如图3B和图5B所示，透光孔01位于第一初始化信号线212、发光控制信号线110、第一电源线312和第二数据线3112围成的区域内。如图3B和图5B所示，透光孔01在衬底基板的正投影和第一电极在衬底基板的正投影不交叠。
以下给出图3A或图3B所示的显示基板的制作方法。
图4A为本公开一实施例提供的显示基板的制作方法中形成的半导体图案层的示意图。半导体图案层SCP由半导体材料形成。本公开一实施例提供的显示基板的制作方法还包括在半导体图案层SCP上形成第一绝缘薄膜层。
图4B为本公开一实施例提供的显示基板的制作方法中在第一绝缘薄膜层上形成的第一导电图案层的示意图。第一导电图案层L1包括发光控制信号线110、第一复位控制信号线111、第二复位控制信号线112、栅线113、驱动晶体管T1的栅极T10。驱动晶体管T1的栅极T10同时作为存储电容C1的第二极C12。
图4C为本公开一实施例提供的显示基板的制作方法中对半导体图案层采用自对准工艺进行导体化处理后的结构示意图。例如，在显示基板的制作过程中，采用自对准工艺，以第一导电图案层L1为掩模对半导体图案层SCP进行导体化处理，例如，采用离子注入对半导体图案层SCP进行重掺杂，从而使得半导体图案层SCP未被第一导电图案层L1覆盖的部分被导体化，形成驱动晶体管T1的源极区(第一极T11)和漏极区(第二极T12)、数据写入晶体管T2的源极区(第一极T21)和漏极区(第二极T22)、阈值补偿晶体管T3的源极区(第一极T31)和漏极区(第二极T32)、第一发光控制晶体管T4的源极区(第一极T41)和漏极区(第二极T42)、第二发光控制晶体管T5的源极区(第一极T51)和漏极区(第二极T52)、第一复位晶体管T6的源极区(第一极T61)和漏极区(第二极T62)、以及第二复位晶体管T7的源极区(第一极T71)和漏极区(第二极T72)。半导体图案层SCP被第一导电图案层L1覆盖的部分保留半导体特性，形成驱动晶体管T1的沟道区T14、数据写入晶体管T2的沟道区T24、阈值补偿晶体管T3的沟道区T34、第一发光控制晶体管T4的沟道区T44、第二发光控制晶体管T5的沟道区T54、第一复位晶体管T6的沟道区T64、以及第二复位晶体管T7的沟道区T74。例如，如图4C所示，第二复位晶体管T7的第二极T72和第二发光控制晶体管T5的第二极T52一体形成；第二发光控制晶体管T5的第一极T51、驱动晶体管T1的第二极T12和阈值补偿晶体管T3的第一极T31一体形成；驱动晶体管T1的第一极T11、数据写入晶体管T2的第二极T22、第一发光控制晶体管T4的第二极T42一体形成；阈值补偿晶体管T3的第二极T32和第一复位晶体管T6的第二极T62一体形成。在一些实施例中，如图4C所示，第二复位晶体管T7的第一极T71和第一复位晶体管T6的第一极T61可一体形成。
例如，本公开实施例采用的晶体管的沟道区(有源层)可以为单晶硅、多晶硅(例如低温多晶硅)或金属氧化物半导体材料(如IGZO、AZO等)。在一个实施例中，该晶体管均为P型低温多晶硅(LTPS)薄膜晶体管。在另一个实施例中，与驱动晶体管T1的栅极直接连接的阈值补偿晶体管T3和第一复位晶体管T6为金属氧化物半导体薄膜晶体管，即晶体管的沟道材料为金属氧化物半导体材料(如IGZO、AZO等)，金属氧化物半导体薄膜晶体 管具有较低的漏电流，可以有助于降低驱动晶体管T1的栅极漏电流。
例如，本公开实施例采用的晶体管可以包括多种结构，如顶栅型、底栅型或者双栅结构。在一个实施例中，与驱动晶体管T1的栅极直接连接的阈值补偿晶体管T3和第一复位晶体管T6为双栅型薄膜晶体管，可以有助于降低驱动晶体管T1的栅极漏电流。
本公开一实施例提供的显示基板的制作方法，在进行导体化处理后的结构上形成第二绝缘薄膜层。图中未示出第二绝缘薄膜层。例如，第二绝缘薄膜层可呈面状覆盖衬底基板。
图4D为本公开一实施例提供的显示基板的制作方法中在第二绝缘薄膜层上形成的第二导电图案层的示意图。第二导电图案层L2包括第一初始化信号线212、存储电容C1的第一极C11、第二初始化信号线211和连接元件214。存储电容C1的第一极C11具有开口02，以利于第二连接电极31b穿过开口02与存储电容C1的第二极C12电连接。第二连接电极31b与存储电容C1的第一极C11彼此绝缘。
图4E为本公开一实施例提供的显示基板的制作方法中在第二导电图案层上形成第三绝缘薄膜层，并在第一绝缘薄膜层、第二绝缘薄膜层和第三绝缘薄膜层至少之一中形成过孔的示意图。如图4E所示，在形成过孔后，形成第一绝缘层、第二绝缘层和第三绝缘层，图4E中未示出第一绝缘层、第二绝缘层和第三绝缘层，可参照后续的剖视图。第三绝缘薄膜层可呈面状覆盖衬底基板。第一绝缘层为在第一绝缘薄膜层中形成过孔后的结构。第二绝缘层为在第二绝缘薄膜层中形成过孔后的结构。第三绝缘层为在第三绝缘薄膜层中形成过孔后的结构。如图4E所示，第三绝缘层包括过孔VH40、过孔VH0、过孔VH1、过孔VH2、过孔VH3、过孔VH11、过孔VH12、过孔VH21、过孔VH22、过孔VH31和过孔VH32。
图4F为本公开一实施例提供的显示基板的制作方法中在第三绝缘层上形成的第三导电图案层的示意图。如图4F所示，第三导电图案层L3包括第一连接电极31a、第二连接电极31b、第三连接电极31c、第四连接电极31d、数据线311和第一电源线312。图4F中的虚线框分别表示对应过孔VH40、过孔VH0、过孔VH1、过孔VH2、过孔VH3、过孔VH11、过孔VH12、过孔VH21、过孔VH22、过孔VH31和过孔VH32的位置。例如，如图4F所 示，第一连接电极31a、第二连接电极31b、第三连接电极31c、第四连接电极31d、数据线311和第一电源线312位于同一层。从而，数据线311通过过孔VH1与数据写入晶体管T2的第一极T21电连接，第一电源线312通过过孔VH2与第一发光控制晶体管T4的第一极T41电连接，第一电源线312通过过孔VH3与存储电容C1的第一极C11电连接，第一电源线312通过过孔VH0与连接元件214电连接，连接元件214与第一电源线312并联，从而可起到减小电阻的作用。第一连接电极31a的一端通过过孔VH11与第二初始化信号线211电连接，第一连接电极31a的另一端通过过孔VH12与第一复位晶体管T6的第一极T61相连，进而使得第一复位晶体管T6的第一极T61与第二初始化信号线211电连接。第二连接电极31b的一端通过过孔VH21与第一复位晶体管T6的第二极T62电连接，第二连接电极31b的另一端通过过孔VH22与驱动晶体管T1的栅极T10(也即存储电容C1的第二极C12)电连接，从而使得第一复位晶体管T6的第二极T62与驱动晶体管T1的栅极T10(也即存储电容C1的第二极C12)电连接。第三连接电极31c的一端通过过孔VH31与第一初始化信号线212电连接，第三连接电极31c的另一端通过过孔VH32与第二复位晶体管T7的第一极T71电连接，从而使得第二复位晶体管T7的第一极T71与第一初始化信号线212电连接。形成第三导电图案层后，即可得到如图3A或图3B所示的显示基板。
例如，图3A中，左上角的第二复位晶体管T7、右下角的第一复位晶体管T6、驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、以及第二发光控制晶体管T5构成图1所示的7个晶体管，即构成一个像素单元内的像素电路结构中的7个晶体管。
例如，第一导电图案层L1、第二导电图案层L2和第三导电图案层L3均采用金属材料制作。例如，第一导电图案层L1由同一金属材料采用同一构图工艺形成，第二导电图案层L2由同一金属材料采用同一构图工艺形成，第三导电图案层L3由同一金属材料采用同一构图工艺形成。例如，金属材料采包括铝金属、钛金属，但不限于此。例如，第一导电图案层L1、第二导电图案层L2和第三导电图案层L3可以采用钛-铝-钛的三层金属结构，但不限于此。
图5A为图3A中A-B处的剖视图。如图5A所示，衬底基板BS上设有 缓冲层BL，缓冲层BL上设有第二发光控制晶体管T5的第二极T52和第一发光控制晶体管T4的第一极T41，在第二发光控制晶体管T5的第二极T52和第一发光控制晶体管T4的第一极T41上设有第一绝缘层IS1、第二绝缘层IS2和第三绝缘层IS3。在第一绝缘层IS1、第二绝缘层IS2和第三绝缘层IS3中形成有过孔VH2，第一电源线312通过过孔VH2与第一发光控制晶体管T4的第一极T41电连接。第三绝缘层IS3上还设有数据线311。第三绝缘层IS3上还设有第四连接电极31d。如图3A和图5A所示，第四连接电极31d通过过孔VH40与第二发光控制晶体管T5的第二极T52电连接。
图5B为本公开另一实施例提供的图3A所示的显示基板的A-B处的剖视图。与图5A所示的实施例相比，图5B所示的实施例示出了第一电极201、第二电极202和位于第一电极201和第二电极202之间的有机层2012。例如，有机层2012包括发光层。例如，有机层2012还包括空穴注入层、空穴传输层、电子传输层、电子注入层中至少之一，但不限于此。例如，第一电极201、第二电极202和有机层2012构成发光元件20。发光元件20发出的光经过手指FG反射，再通过透光孔01，可到达传感器(sensor)上，从而实现指纹识别功能。手指FG包括脊和谷。例如，传感器可位于衬底基板和薄膜晶体管之间。例如，传感器还可位于衬底基板的远离薄膜晶体管的一侧。
例如，第一电极201为发光元件20的阳极，第二电极202为发光元件20的阴极。例如，第一电极201可采用透明导电材料和金属材料制作，第二电极202可采用透明或半透明的导电材料。一些实施例中，第一电极201可采用透明导电金属氧化物和银至少之一，但不限于此。例如，透明导电金属氧化物包括氧化铟锡(ITO)，但不限于此。例如，第一电极201可采用ITO-Ag-ITO三个子层叠层设置的结构。一些实施例中，第二电极可以为低功函的金属，可采用镁和银至少之一，但不限于此。例如，另一些实施例中，第二电极的材料包括镁铝合金(MgAl)、锂铝合金(LiAl)或者镁、铝、锂金属等。例如，在本公开的一些实施例中，为了避免杂散光影响指纹识别，第一电极201为不透明电极，但不限于此。
如图5B所示，第一电极201在对应透光孔01的位置处镂空。例如，如图5B所示，透光孔01在衬底基板BS上的正投影与第一电极201在衬底基板BS上的正投影不交叠。
图6为图3A中E-F处的剖视图。如图6所示，衬底基板BS上设有缓冲层BL，缓冲层BL上设有驱动晶体管T1的沟道区T14、驱动晶体管T1的第一极T11、驱动晶体管T1的第二极T12，在驱动晶体管T1的沟道区T14、驱动晶体管T1的第一极T11和驱动晶体管T1的第二极T12上设有第一绝缘层IS1，在第一绝缘层IS1设有存储电容C1的第二极C12(也即驱动晶体管T1的栅极T10)，在存储电容C1的第二极C12上设有第二绝缘层IS2，在第二绝缘层IS2上设有存储电容C1的第一极C11，在存储电容C1的第一极C11上设有第三绝缘层IS3。在第三绝缘层IS3上设有第二连接电极31b、第一电源线312和数据线311。在第二绝缘层IS2和第三绝缘层IS3中设有过孔VH22，第二连接电极31b通过过孔VH22与存储电容C1的第二极C12电连接。第二连接电极31b与存储电容C1的第一极C11彼此绝缘，存储电容C1的第二极C12和存储电容C1的第一极C11彼此绝缘。在第三绝缘层IS3中设有过孔VH3，第一电源线312通过过孔VH3与存储电容C1的第一极C11电连接。例如，衬底基板BS为透明基板。第一绝缘层IS1、第二绝缘层IS2和第三绝缘层IS3分别采用绝缘材料制成。绝缘材料包括无机绝缘材料和有机绝缘材料。无机绝缘材料包括氧化硅、氮化硅和氮氧化硅，但不限于此，有机绝缘材料包括聚酰亚胺(PI)，但不限于此。
图7A为图3A中M-N处的剖视图。如图7A所示，衬底基板BS上设有缓冲层BL，缓冲层BL上设有第二复位晶体管T7的第一极T71，在第二复位晶体管T7的第一极T71上设有第一绝缘层IS1，在第一绝缘层IS1设有第二复位控制信号112，在第二复位控制信号112上设有第二绝缘层IS2，在第二绝缘层IS2上设有第一初始化信号线212，在第一初始化信号线212上设有第三绝缘层IS3。在第一绝缘层IS1、第二绝缘层IS2和第三绝缘层IS3中设有过孔VH32，在第三绝缘层IS3中设有过孔VH31，第三连接电极31c通过过孔VH32与第二复位晶体管T7的第一极T71电连接。第三连接电极31c通过过孔VH31与第一初始化信号线212电连接。
图7B为图3A中J-K处的剖视图。如图7B所示，衬底基板BS上设有缓冲层BL，缓冲层BL上设有第二复位晶体管T7的第一极T71，在第二复位晶体管T7的第一极T71上设有第一绝缘层IS1，在第一绝缘层IS1设有第一复位控制信号111，在第一复位控制信号111上设有第二绝缘层IS2，在第 二绝缘层IS2上设有第二初始化信号线211，在第二初始化信号线211上设有第三绝缘层IS3。在第一绝缘层IS1、第二绝缘层IS2和第三绝缘层IS3中设有过孔VH12，在第三绝缘层IS3中设有过孔VH11，第一连接电极31a通过过孔VH12与第二复位晶体管T7的第一极T71电连接。第一连接电极31a通过过孔VH11与第二初始化信号线211电连接。
图7C为图3A中X-Y处的剖视图。如图7C所示，第一电源线312通过过孔VH0与连接元件214电连接。数据线311通过过孔VH1与数据写入晶体管T2的第一极T21电连接。第二连接电极31b的一端通过过孔VH21与第一复位晶体管T6的第二极T62电连接，第二连接电极31b的另一端通过过孔VH22与驱动晶体管T1的栅极T10(也即存储电容C1的第二极C12)电连接。
图8A为本公开一实施例提供的显示基板中的第一初始化信号线和第二初始化信号线电连接的示意图。例如，如图8A所示，第二初始化信号线211和第一初始化信号线212电连接。例如，如图8A所示，显示基板包括显示区R1和周边区R2，第二初始化信号线211和第一初始化信号线212通过位于周边区R2的第一连接结构81电连接。例如，第二初始化信号线211和第一初始化信号线212可位于同一层，且与第一连接结构81之间设有绝缘层，第一连接结构81的两端分别通过过孔与第二初始化信号线211和第一初始化信号线212相连。在其他的实施例中，第二初始化信号线211和第一初始化信号线212也可不相连，但被配置为施加同一信号。例如，本公开的实施例中，第一连接结构81可位于第三导电图案层L3，但不限于此。
图8B为本公开一实施例提供的显示基板中的第二复位控制信号线和栅线电连接的示意图。例如，第二复位控制信号线112和栅线113电连接。例如，如图8B所示，显示基板包括显示区R1和周边区R2，第二复位控制信号线112和栅线113通过位于周边区R2的第二连接结构82电连接。例如，第二复位控制信号线112和栅线113可位于同一层，且与第二连接结构82之间设有绝缘层，第二连接结构82的两端分别通过过孔与第二复位控制信号线112和栅线113相连。在其他的实施例中，第二复位控制信号线112和栅线也可不相连，但被配置为施加同一信号。例如，本公开的实施例中，第二连接结构82可位于第三导电图案层L3，但不限于此。
图9为本公开实施例提供的显示面板中一个像素单元的时序信号图。以下将结合图1和图9对本公开实施例提供的显示面板中一个像素单元的驱动方法进行说明。
如图9所示，在一帧显示时间段内，像素单元的驱动方法包括第一复位阶段t1、数据写入及阈值补偿和第二复位阶段t2和发光阶段t3。
在第一复位阶段t1，设置发光控制信号EM为关闭电压，设置复位控制信号RESET为开启电压，设置扫描信号SCAN为关闭电压。
在数据写入及阈值补偿和第二复位阶段t2，设置发光控制信号EM为关闭电压，设置复位控制信号RESET为关闭电压，设置扫描信号SCAN为开启电压。
在发光阶段t3，设置发光控制信号EM为开启电压，设置复位控制信号RESET为关闭电压，设置扫描信号SCAN为关闭电压。
如图9所示，第一电压信号ELVDD、第二电压信号ELVSS、以及初始化信号Vint均为恒定的电压信号，初始化信号Vint介于第一电压信号ELVDD和第二电压信号ELVSS之间。
例如，本公开实施例中的开启电压是指能使相应晶体管的第一极和第二级导通的电压，关闭电压是指能使相应晶体管的第一极和第二级断开的电压。当晶体管为P型晶体管时，开启电压为低电压(例如，0V)，关闭电压为高电压(例如，5V)；当晶体管为N型晶体管时，开启电压为高电压(例如，5V)，关闭电压为低电压(例如，0V)。图9所示的驱动波形均以P型晶体管为例进行说明，即开启电压为低电压(例如，0V)，关闭电压为高电压(例如，5V)。
请一并参阅图1和图9，在第一复位阶段t1，发光控制信号EM为关闭电压，复位控制信号RESET为开启电压，扫描信号SCAN为关闭电压。此时，第一复位晶体管T6处于导通状态，而数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4和第二发光控制晶体管T5处于关闭状态。第一复位晶体管T6将初始化信号(初始化电压)Vint传输到驱动晶体管T1的栅极并被存储电容C1存储，将驱动晶体管T1复位并消除上一次(上一帧)发光时存储的数据。
在数据写入及阈值补偿和第二复位阶段t2，发光控制信号EM为关闭电 压，复位控制信号RESET为关闭电压，扫描信号SCAN为开启电压。此时，数据写入晶体管T2和阈值补偿晶体管T3处于导通状态，第二复位晶体管T7处于导通状态，第二复位晶体管T7将初始化信号Vint传输到发光元件20的第一电极，以将发光元件20复位；而第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7处于关闭状态。此时，数据写入晶体管T2将数据信号电压VDATA传输到驱动晶体管T1的第一极，即，数据写入晶体管T2接收扫描信号SCAN和数据信号DATA并根据扫描信号SCAN向驱动晶体管T1的第一极写入数据信号DATA。阈值补偿晶体管T3导通将驱动晶体管T1连接成二极管结构，由此可对于驱动晶体管T1的栅极进行充电。充电完成之后，驱动晶体管T1的栅极电压为VDATA+Vth，其中，VDATA为数据信号电压，Vth为驱动晶体管T1的阈值电压，即，阈值补偿晶体管T3接收扫描信号SCAN并根据扫描信号SCAN对驱动晶体管T1的栅极电压进行阈值电压补偿。在此阶段，存储电容C1两端的电压差为ELVDD-VDATA-Vth。
在发光阶段t3，发光控制信号EM为开启电压，复位控制信号RESET为关闭电压，扫描信号SCAN为关闭电压。第一发光控制晶体管T4和第二发光控制晶体管T5处于导通状态，而数据写入晶体管T2、阈值补偿晶体管T3、第一复位晶体管T6和第二复位晶体管T7处于关闭状态。第一电源信号ELVDD通过第一发光控制晶体管T4传输到驱动晶体管T1的第一极，驱动晶体管T1的栅极电压保持为VDATA+Vth，发光电流I通过第一发光控制晶体管T4、驱动晶体管T1和第二发光控制晶体管T5流入发光元件20，发光元件20发光。即，第一发光控制晶体管T4和第二发光控制晶体管T5接收发光控制信号EM，并根据发光控制信号EM控制有发光元件20发光。发光电流I满足如下饱和电流公式：
K(Vgs-Vth) 2＝K(VDATA+Vth-ELVDD-Vth) 2＝K(VDATA-ELVDD) 2
其中，
Figure PCTCN2019121570-appb-000001
μ n为驱动晶体管的沟道迁移率，Cox为驱动晶体管T1单位面积的沟道电容，W和L分别为驱动晶体管T1的沟道宽度和沟道长度，Vgs为驱动晶体管T1的栅极与源极(也即本实施例中驱动晶体管T1的第一极)之间的电压差。
由上式中可以看到流经发光元件20的电流与驱动晶体管T1的阈值电压无关。因此，本像素电路结构非常好的补偿了驱动晶体管T1的阈值电压。
例如，发光阶段t3的时长占一帧显示时间段的比例可被调节。这样，可以通过调节发光阶段t3的时长占一帧显示时间段的比例控制发光亮度。例如，通过控制显示面板中的扫描驱动电路103或者额外设置的驱动电路实现调节发光阶段t3的时长占一帧显示时间段的比例。
例如，在其他实施例中，可以不提供第一复位晶体管T6或第二复位晶体管T7等，也即本公开实施例不限于图1所示出的具体像素电路，可以采用其他能实现对于驱动晶体管补偿的像素电路。基于本公开对该实现方式的描述和教导，本领域普通技术人员在没有做出创造性劳动前提下能够容易想到的其它设置方式，都属于本公开的保护范围之内。
本公开的实施例中，在垂直于衬底基板的方向上，透光孔01具有一定的尺寸，故而称作孔，透光孔01为成像小孔，透光孔01所在位置处不设置走线，以避免影响透光孔01的透光性。例如，前述第一导电图案层、第二导电图案层和第三导电图案层在透光孔01位置处均不设置金属走线，以形成透光孔01。
本公开的另一实施例还提供一种显示装置，包括上述任一显示基板。显示装置可包括OLED显示器以及包括OLED显示器的电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产品或者部件。
需要说明的是，为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在本公开的实施例中，各个元件的形状只是示意性的描述，不限于图中所示，可根据需要而定。
在本公开的实施例中，构图或构图工艺可只包括光刻工艺，或包括光刻工艺以及刻蚀步骤，或者可以包括打印、喷墨等其他用于形成预定图形的工艺。光刻工艺是指包括成膜、曝光、显影等工艺过程，利用光刻胶、掩模板、曝光机等形成图形。可根据本公开的实施例中所形成的结构选择相应的构图工艺。
在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (38)

  1. 一种显示基板，包括：
    衬底基板，包括显示区；
    多个像素单元，位于所述显示区中，所述像素单元包括像素电路结构和发光元件，所述发光元件包括第一电极，所述第一电极位于所述像素电路结构的远离所述衬底基板的一侧，所述多个像素单元包括沿第一方向相邻的第一像素单元和第二像素单元；
    第一初始化信号线，沿所述第一方向延伸；
    发光控制信号线，沿所述第一方向延伸；
    第一电源线，沿第二方向延伸，所述第二方向与所述第一方向交叉；
    第一数据线，沿所述第二方向延伸，所述第一数据线与所述第一像素单元的像素电路结构相连；
    第二数据线，沿所述第二方向延伸，所述第二数据线与所述第二像素单元的像素电路结构相连；所述第一数据线和所述第二数据线分设在所述第一电源线的两侧；
    透光孔，所述透光孔在所述衬底基板的正投影和所述第一电极在所述衬底基板的正投影不交叠，
    其中，所述透光孔位于所述第一初始化信号线、所述发光控制信号线、所述第一电源线和所述第二数据线围成的区域内。
  2. 根据权利要求1所述的显示基板，其中，所述第二数据线到所述第一电源线的距离大于所述第一数据线到所述第一电源线的距离。
  3. 根据权利要求1所述的显示基板，其中，所述像素电路结构还包括第一发光控制晶体管和第二发光控制晶体管，
    所述第一发光控制晶体管包括第一极和第二极，所述第一发光控制晶体管的第一极和第二极分别位于所述发光控制线的第一侧和第二侧；
    所述第二发光控制晶体管包括第一极和第二极，所述第二发光控制晶体管的第二极和第一极分别位于所述发光控制线的所述第一侧和所述第二侧；
    所述第一侧和所述第二侧为所述发光控制信号线的相对的两侧；
    所述透光孔位于所述第一发光控制晶体管的第一极和所述第二发光控制 晶体管的第二极之间。
  4. 根据权利要求3所述的显示基板，其中，所述第一发光控制晶体管的栅极和所述第二发光控制晶体管的栅极均与所述发光控制信号线相连。
  5. 根据权利要求3或4所述的显示基板，其中，所述第一发光控制晶体管、所述透光孔和所述第二发光控制晶体管沿所述第一方向排列。
  6. 根据权利要求3-5任一项所述的显示基板，其中，所述像素电路结构还包括位于所述发光控制信号线的所述第二侧的驱动晶体管；
    所述第一发光控制晶体管的第一极与第二极分别与所述第一电源线和所述驱动晶体管的第一极电连接；
    所述第二发光控制晶体管的第一极与第二极分别与所述驱动晶体管的第二极、所述发光元件的第一电极电连接。
  7. 根据权利要求6所述的显示基板，还包括第二初始化信号线、第一复位控制信号线和第二复位控制信号线，其中，所述像素电路结构还包括第一复位晶体管以及第二复位晶体管；
    所述第一复位晶体管的栅极与所述第一复位控制信号线电连接，所述第一复位晶体管的第一极通过第一连接电极与所述第二初始化信号线电连接，所述第一复位晶体管的第二极通过第二连接电极与所述驱动晶体管的栅极电连接；
    所述第二复位晶体管的栅极与所述第二复位控制信号线电连接，所述第二复位晶体管的第一极通过第三连接电极与所述第一初始化信号线电连接，所述第二复位晶体管的第二极与所述发光元件的第一电极电连接。
  8. 根据权利要求7所述的显示基板，其中，所述第二初始化信号线沿所述第一方向延伸，所述第一复位控制信号线沿所述第一方向延伸，所述第二复位控制信号线沿所述第一方向延伸。
  9. 根据权利要求7或8所述的显示基板，其中，所述透光孔还位于所述驱动晶体管和所述第二复位晶体管之间。
  10. 根据权利要求6-9任一项所述的显示基板，其中，所述驱动晶体管和所述第二复位晶体管分别设置在所述透光孔在所述第二方向上彼此相对的两侧。
  11. 根据权利要求6-10任一项所述的显示基板，其中，所述第二复位控 制信号线、所述第一初始化信号线、所述发光控制信号线、所述第一复位控制信号线和所述第二初始化信号线沿第二方向依次排列。
  12. 根据权利要求6-11任一项所述的显示基板，其中，所述第一初始化信号线和所述第二初始化信号线电连接，或者，所述第一初始化信号线和所述第二初始化信号线被配置为施加同一信号。
  13. 根据权利要求6-12任一项所述的显示基板，还包括栅线以及第二电源线，其中，所述像素电路结构还包括存储电容、数据写入晶体管和阈值补偿晶体管，其中，
    所述存储电容的第一极与所述第一电源线电连接，所述存储电容的第二极通过所述第二连接电极与所述阈值补偿晶体管的第二极电连接；
    所述数据写入晶体管的栅极与所述栅线电连接，所述第一像素单元的所述数据写入晶体管的第一极与第二极分别与所述第一数据线、所述第一像素单元的所述驱动晶体管的第一极电连接；
    所述阈值补偿晶体管的栅极与所述栅线电连接，所述阈值补偿晶体管的第一极与所述驱动晶体管的第二极电连接，所述阈值补偿晶体管的第二极通过所述第二连接电极与所述驱动晶体管的栅极电连接；
    所述发光元件的第二电极与所述第二电源线电连接。
  14. 根据权利要求13所述的显示基板，其中，所述第一电源线的靠近所述第一数据线的边缘在各位置处与所述第一数据线之间的距离相等。
  15. 根据权利要求13或14所述的显示基板，其中，所述栅线沿第一方向延伸，所述栅线位于所述发光控制信号线和所述第一复位控制信号线之间。
  16. 根据权利要求13-15任一项所述的显示基板，其中，所述第二复位控制信号线和所述栅线电连接，或者，所述第二复位控制信号线和所述栅线被配置为施加同一信号。
  17. 根据权利要求13-16任一项所述的显示基板，其中，所述第一连接电极、所述第二连接电极、所述第三连接电极、所述第一数据线、所述第二数据线和所述第一电源线位于同一层。
  18. 根据权利要求1-17任一项所述的显示基板，其中，所述透光孔在所述第一方向上的尺寸为5-15μm，所述透光孔在所述第二方向上的尺寸为5-15μm。
  19. 一种显示装置，包括权利要求1-18任一项所述的显示基板。
  20. 一种显示基板，包括：
    像素电路结构，所述像素电路结构包括第一发光控制晶体管和第二发光控制晶体管；
    发光控制信号线，所述第一发光控制晶体管的栅极和所述第二发光控制晶体管的栅极均与所述发光控制信号线相连；
    发光元件，包括第一电极，所述第一电极位于所述像素电路结构的远离衬底基板的一侧；以及
    透光孔，位于所述第一发光控制晶体管和所述第二发光控制晶体管之间，所述透光孔在所述衬底基板的正投影和所述第一电极在所述衬底基板的正投影不交叠。
  21. 根据权利要求20所述的显示基板，其中，所述第一数据线和所述第一电源线之间的距离小于所述第二数据线和所述第一电源线之间的距离。
  22. 根据权利要求20或21所述的显示基板，所述发光控制信号线沿第一方向延伸，所述第一发光控制晶体管、所述透光孔和所述第二发光控制晶体管沿所述第一方向排列。
  23. 根据权利要求22所述的显示基板，还包括第一电源线，其中，所述透光孔位于所述发光控制信号线的第一侧，所述像素电路结构还包括位于所述发光控制信号线的第二侧的驱动晶体管，所述第一侧和所述第二侧为所述发光控制信号线的相对的两侧；
    所述第一发光控制晶体管的第一极与第二极分别与所述第一电源线和所述驱动晶体管的第一极电连接；
    所述第二发光控制晶体管的第一极与第二极分别与所述驱动晶体管的第二极、所述发光元件的第一电极电连接；
    所述第一电源线沿第二方向延伸，所述第二方向与所述第一方向相交。
  24. 根据权利要求23所述的显示基板，还包括第一初始化信号线、第二初始化信号线、第一复位控制信号线和第二复位控制信号线，其中，所述像素电路结构还包括第一复位晶体管以及第二复位晶体管；
    所述第一复位晶体管的栅极与所述第一复位控制信号线电连接，所述第一复位晶体管的第一极通过第一连接电极与所述第二初始化信号线电连接， 所述第一复位晶体管的第二极通过第二连接电极与所述驱动晶体管的栅极电连接；
    所述第二复位晶体管的栅极与所述第二复位控制信号线电连接，所述第二复位晶体管的第一极通过第三连接电极与所述第一初始化信号线电连接，所述第二复位晶体管的第二极与所述发光元件的第一电极电连接。
  25. 根据权利要求24所述的显示基板，其中，所述第一初始化信号线沿所述第一方向延伸，所述第二初始化信号线沿所述第一方向延伸，所述第一复位控制信号线沿所述第一方向延伸，所述第二复位控制信号线沿所述第一方向延伸。
  26. 根据权利要求24或25所述的显示基板，其中，所述透光孔还位于所述驱动晶体管和所述第二复位晶体管之间。
  27. 根据权利要求24-26任一项所述的显示基板，其中，所述驱动晶体管和所述第二复位晶体管分别设置在所述透光孔在所述第二方向上彼此相对的两侧。
  28. 根据权利要求24-27任一项所述的显示基板，其中，所述透光孔还位于所述第一初始化信号线和所述发光控制信号线之间。
  29. 根据权利要求24-28任一项所述的显示基板，其中，所述第二复位控制信号线、所述第一初始化信号线、所述发光控制信号线、所述第一复位控制信号线和所述第二初始化信号线沿第二方向依次排列。
  30. 根据权利要求24-29任一项所述的显示基板，其中，所述第一初始化信号线和所述第二初始化信号线电连接，或者，所述第一初始化信号线和所述第二初始化信号线被配置为施加同一信号。
  31. 根据权利要求24-30任一项所述的显示基板，还包括栅线、数据线以及第二电源线，其中，所述像素电路结构还包括存储电容、数据写入晶体管和阈值补偿晶体管，其中，
    所述存储电容的第一极与所述第一电源线电连接，所述存储电容的第二极通过所述第二连接电极与所述阈值补偿晶体管的第二极电连接；
    所述数据写入晶体管的栅极与所述栅线电连接，所述数据写入晶体管的第一极与第二极分别与所述数据线、所述驱动晶体管的第一极电连接；
    所述阈值补偿晶体管的栅极与所述栅线电连接，所述阈值补偿晶体管的 第一极与所述驱动晶体管的第二极电连接，所述阈值补偿晶体管的第二极通过所述第二连接电极与所述驱动晶体管的栅极电连接；
    所述发光元件的第二电极与所述第二电源线电连接。
  32. 根据权利要求31所述的显示基板，其中，所述第一电源线的靠近所述数据线的边缘在各位置处与所述数据线之间的距离相等。
  33. 根据权利要求31或32所述的显示基板，其中，所述栅线沿第一方向延伸，所述栅线位于所述发光控制信号线和所述第一复位控制信号线之间。
  34. 根据权利要求31-33任一项所述的显示基板，其中，所述数据线沿第二方向延伸，所述第一电源线沿第二方向延伸。
  35. 根据权利要求31-34任一项所述的显示基板，其中，所述第二复位控制信号线和所述栅线电连接，或者，所述第二复位控制信号线和所述栅线被配置为施加同一信号。
  36. 根据权利要求24-35任一项所述的显示基板，其中，所述第一连接电极、所述第二连接电极、所述第三连接电极、所述数据线和所述第一电源线位于同一层。
  37. 根据权利要求23-36任一项所述的显示基板，其中，所述透光孔在所述第一方向上的尺寸为5-15μm，所述透光孔在所述第二方向上的尺寸为5-15μm。
  38. 一种显示装置，包括权利要求20-37任一项所述的显示基板。
PCT/CN2019/121570 2019-11-28 2019-11-28 显示基板和显示装置 WO2021102791A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/CN2019/121570 WO2021102791A1 (zh) 2019-11-28 2019-11-28 显示基板和显示装置
CN201980002688.8A CN113261106B (zh) 2019-11-28 2019-11-28 显示基板和显示装置
US16/977,273 US11721282B2 (en) 2019-11-28 2019-11-28 Display substrate and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/121570 WO2021102791A1 (zh) 2019-11-28 2019-11-28 显示基板和显示装置

Publications (1)

Publication Number Publication Date
WO2021102791A1 true WO2021102791A1 (zh) 2021-06-03

Family

ID=76128616

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/121570 WO2021102791A1 (zh) 2019-11-28 2019-11-28 显示基板和显示装置

Country Status (3)

Country Link
US (1) US11721282B2 (zh)
CN (1) CN113261106B (zh)
WO (1) WO2021102791A1 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113809098A (zh) * 2021-08-24 2021-12-17 武汉天马微电子有限公司 显示基板、显示面板和显示装置
WO2022160839A1 (zh) * 2021-01-26 2022-08-04 京东方科技集团股份有限公司 显示基板以及显示装置
WO2023039721A1 (zh) * 2021-09-14 2023-03-23 京东方科技集团股份有限公司 显示面板和显示装置
EP4207301A4 (en) * 2021-06-10 2023-12-27 BOE Technology Group Co., Ltd. DISPLAY SUBSTRATE AND DISPLAY DEVICE

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116097925A (zh) * 2021-09-02 2023-05-09 京东方科技集团股份有限公司 显示基板及显示装置
CN116686414B (zh) * 2021-12-23 2024-04-12 京东方科技集团股份有限公司 显示基板及其驱动方法、显示装置
CN115410523A (zh) * 2022-08-30 2022-11-29 武汉华星光电半导体显示技术有限公司 像素电路及显示面板
CN115377165A (zh) * 2022-08-30 2022-11-22 京东方科技集团股份有限公司 显示基板及显示装置
CN118251770A (zh) * 2022-10-24 2024-06-25 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140098078A1 (en) * 2012-10-08 2014-04-10 Samsung Display Co., Ltd. Organic light emitting diode display
CN108242453A (zh) * 2016-12-23 2018-07-03 京东方科技集团股份有限公司 一种oled显示面板及显示装置
CN108550602A (zh) * 2018-04-20 2018-09-18 上海天马有机发光显示技术有限公司 显示面板和显示装置
US20190081090A1 (en) * 2017-09-08 2019-03-14 Samsung Display Co., Ltd. Display device
CN110265458A (zh) * 2019-06-27 2019-09-20 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板及显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105789266A (zh) * 2016-05-30 2016-07-20 京东方科技集团股份有限公司 一种oled阵列基板及其制备方法、显示装置
CN108878488B (zh) 2018-06-26 2020-12-04 上海天马有机发光显示技术有限公司 一种显示面板和显示装置及显示面板的制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140098078A1 (en) * 2012-10-08 2014-04-10 Samsung Display Co., Ltd. Organic light emitting diode display
CN108242453A (zh) * 2016-12-23 2018-07-03 京东方科技集团股份有限公司 一种oled显示面板及显示装置
US20190081090A1 (en) * 2017-09-08 2019-03-14 Samsung Display Co., Ltd. Display device
CN108550602A (zh) * 2018-04-20 2018-09-18 上海天马有机发光显示技术有限公司 显示面板和显示装置
CN110265458A (zh) * 2019-06-27 2019-09-20 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板及显示装置

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022160839A1 (zh) * 2021-01-26 2022-08-04 京东方科技集团股份有限公司 显示基板以及显示装置
US11869268B2 (en) 2021-01-26 2024-01-09 Chengdu Boe Optoelectronics Technology Co., Ltd. Display panel and display device
EP4207301A4 (en) * 2021-06-10 2023-12-27 BOE Technology Group Co., Ltd. DISPLAY SUBSTRATE AND DISPLAY DEVICE
CN113809098A (zh) * 2021-08-24 2021-12-17 武汉天马微电子有限公司 显示基板、显示面板和显示装置
CN113809098B (zh) * 2021-08-24 2024-04-09 武汉天马微电子有限公司 显示基板、显示面板和显示装置
WO2023039721A1 (zh) * 2021-09-14 2023-03-23 京东方科技集团股份有限公司 显示面板和显示装置

Also Published As

Publication number Publication date
CN113261106A (zh) 2021-08-13
CN113261106B (zh) 2022-11-25
US20230038017A1 (en) 2023-02-09
US11721282B2 (en) 2023-08-08

Similar Documents

Publication Publication Date Title
WO2021102791A1 (zh) 显示基板和显示装置
JP7402053B2 (ja) 表示パネル及び表示装置
US11631728B2 (en) Array substrate structure and display device
WO2019227943A1 (zh) 显示面板及显示装置
WO2021227553A1 (zh) 显示基板和显示装置
WO2022068152A1 (zh) 显示面板和显示装置
US11594587B2 (en) Display device
WO2021189335A1 (zh) 显示面板和显示装置
WO2022226967A1 (zh) 显示面板和显示装置
US20220293640A1 (en) Display device
WO2021203358A1 (zh) 显示面板和显示装置
WO2022174420A1 (zh) 显示面板和显示装置
WO2022226994A1 (zh) 显示面板和显示装置
US20220208923A1 (en) Display device and method of providing the same
WO2022141681A1 (zh) 显示面板和显示装置
WO2021189334A9 (zh) 显示面板和显示装置
WO2023202586A1 (zh) 像素驱动电路、显示模组及显示装置、智能手表
WO2023039721A1 (zh) 显示面板和显示装置
WO2023016335A1 (zh) 显示基板及显示装置
WO2023035138A1 (zh) 显示面板和显示装置
WO2023092473A1 (zh) 显示基板及其制备方法、显示装置
WO2024113224A1 (zh) 显示面板和显示装置
US20240038151A1 (en) Display panel and display device
US20240206269A1 (en) Display Panel and Display Apparatus

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19954679

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19954679

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 19954679

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 07.02.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 19954679

Country of ref document: EP

Kind code of ref document: A1