WO2023202586A1 - 像素驱动电路、显示模组及显示装置、智能手表 - Google Patents

像素驱动电路、显示模组及显示装置、智能手表 Download PDF

Info

Publication number
WO2023202586A1
WO2023202586A1 PCT/CN2023/089030 CN2023089030W WO2023202586A1 WO 2023202586 A1 WO2023202586 A1 WO 2023202586A1 CN 2023089030 W CN2023089030 W CN 2023089030W WO 2023202586 A1 WO2023202586 A1 WO 2023202586A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
electrically connected
node
light
electrode
Prior art date
Application number
PCT/CN2023/089030
Other languages
English (en)
French (fr)
Other versions
WO2023202586A9 (zh
Inventor
李盛义
程海涛
刘乾乾
陈晶
毕鑫
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2023202586A1 publication Critical patent/WO2023202586A1/zh
Publication of WO2023202586A9 publication Critical patent/WO2023202586A9/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present invention relates to the field of display technology, and in particular, to a pixel driving circuit, a display module, a display device, and a smart watch.
  • a display device includes a display panel and at least one flexible circuit board on which an ALS and a plurality of peripheral devices are disposed, and the flexible circuit board is configured to electrically connect the ALS to the display panel.
  • a pixel driving circuit includes a photosensitive device and a dimming subcircuit.
  • the first end of the photosensitive device is configured to receive a control signal, and the second end of the photosensitive device is electrically connected to the first node; the resistance of the photosensitive device changes with the intensity of light irradiating on the photosensitive device. Change, the photosensitive device is configured to adjust the voltage of the first node based on the control signal.
  • the light-adjusting sub-circuit is connected between the first voltage terminal and the light-emitting device, and is electrically connected to the first node; the conduction state of the light-adjusting sub-circuit changes with the change of the voltage of the first node.
  • the dimming sub-circuit is configured to adjust the brightness of the light-emitting device based on the first voltage signal from the first voltage terminal under the control of the voltage of the first node.
  • the pixel driving circuit further includes a driving transistor.
  • the control electrode of the driving transistor is electrically connected to the second node
  • the first electrode of the driving transistor is electrically connected to the third node
  • the second electrode of the driving transistor is electrically connected to the fourth node.
  • the dimming sub-circuit includes a first transistor connected between the fourth node and the light-emitting device, and a control electrode of the first transistor is electrically connected to the first node.
  • the first terminal of the photosensitive device is electrically connected to the enable signal terminal.
  • the dimming sub-circuit further includes a second transistor, a control electrode of the second transistor is electrically connected to the first node or the enable signal terminal, and a first electrode of the second transistor is connected to the first The voltage terminal is electrically connected, and the second pole of the second transistor is electrically connected to the third node.
  • the first end of the photosensitive device is electrically connected to the scanning signal end.
  • the dimming sub-circuit further includes a second transistor, the control electrode of the second transistor is electrically connected to the enable signal terminal, the first electrode of the second transistor is electrically connected to the first voltage terminal, and the third transistor is electrically connected to the enable signal terminal.
  • the second pole of the two transistors is electrically connected to the third node.
  • the first terminal of the photosensitive device is connected with the enable signal terminal, the scan signal terminal, the reset signal terminal, the initialization signal terminal, the first voltage terminal, the second voltage terminal, and the second node.
  • the third node or the fourth Any one of the nodes is electrically connected; wherein the light-emitting device is electrically connected to the second voltage terminal.
  • the dimming sub-circuit also includes a second transistor and a third transistor.
  • the control electrode of the second transistor is electrically connected to the enable signal terminal, the first electrode of the second transistor is electrically connected to the first voltage terminal, and the second electrode of the second transistor is electrically connected to the third node. Electrical connection.
  • the control electrode of the third transistor is electrically connected to the enable signal terminal, the third transistor is connected between the fourth node and the light-emitting device, and the third transistor is connected to the first transistor in series.
  • the pixel driving circuit further includes a driving transistor, a control electrode of the driving transistor is electrically connected to the second node, and a first electrode of the driving transistor is electrically connected to the third node.
  • the driving transistor The second pole is electrically connected to the fourth node.
  • the dimming sub-circuit includes a first transistor, a control electrode of the first transistor is electrically connected to the first node, a first electrode of the first transistor is electrically connected to the first voltage terminal, and the control electrode of the first transistor is electrically connected to the first voltage terminal.
  • a second terminal of a transistor is electrically connected to the third node.
  • the first end of the photosensitive device is electrically connected to the enable signal end or the scan signal end.
  • the dimming sub-circuit further includes a second transistor, a control electrode of the second transistor is electrically connected to the enable signal terminal, a first electrode of the second transistor is electrically connected to the fourth node, and the The second electrode of the second transistor is electrically connected to the light emitting device.
  • the pixel driving circuit further includes a capacitor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor.
  • the first plate of the capacitor is electrically connected to the first voltage terminal, and the second plate of the capacitor is electrically connected to the second node.
  • the control electrode of the fourth transistor is electrically connected to the scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the third node.
  • the control electrode of the fifth transistor is electrically connected to the scan signal terminal, the first electrode of the fifth transistor is electrically connected to the fourth node, and the second electrode of the fifth transistor is electrically connected to the second node. Electrical connection.
  • the control electrode of the sixth transistor is electrically connected to the reset signal terminal, the first electrode of the sixth transistor is electrically connected to the initialization signal terminal, and the second electrode of the sixth transistor is electrically connected to the second node.
  • the control electrode of the seventh transistor is electrically connected to the scanning signal terminal, the first electrode of the seventh transistor is electrically connected to the initialization signal terminal, and the second electrode of the seventh transistor is electrically connected to the light-emitting device. connect.
  • the light modulation sub-circuit when the first terminal of the photosensitive device is electrically connected to any one of the first voltage terminal, the scan signal terminal, the third node and the fourth node , the polarity of the first transistor is opposite to the polarity of the driving transistor, the second transistor, the fourth transistor to the seventh transistor; the light modulation sub-circuit also includes a third transistor. In this case, the polarity of the first transistor is also opposite to the polarity of the third transistor.
  • the The polarity of the first transistor is the same as the polarity of the driving transistor, the second transistor, and the fourth to seventh transistors; in the case where the dimming sub-circuit also includes a third transistor
  • the polarity of the first transistor is also the same as the polarity of the third transistor. same.
  • the display module includes a substrate, a plurality of pixel driving circuits as provided in any of the above embodiments, and a plurality of light-emitting devices.
  • the plurality of pixel driving circuits are disposed on the substrate.
  • the plurality of light-emitting devices are disposed on a side of the plurality of pixel driving circuits away from the substrate, and the light-emitting devices are electrically connected to the pixel driving circuit.
  • the display module has a light-transmitting area, and at least one of the photosensitive devices is provided in the light-transmitting area, and each of the photosensitive devices is electrically connected to a plurality of the pixel driving circuits.
  • the display module further includes a photosensitive layer, the photosensitive layer is disposed on a side of the plurality of pixel driving circuits away from the substrate, the photosensitive layer includes a plurality of the photosensitive devices, Each of the photosensitive devices is electrically connected to one or more of the pixel driving circuits.
  • the display module further includes a flip-chip film and a flexible circuit board.
  • the chip-on-chip film is electrically connected to a plurality of pixel driving circuits.
  • the flexible circuit board is electrically connected to the chip-on-chip film; one side surface of the flexible circuit board is provided with at least one of the photosensitive devices, and the flexible circuit board is bent to the backlight side of the substrate.
  • the photosensitive device is close to the substrate relative to the flexible circuit board.
  • each of the photosensitive devices is electrically connected to a plurality of the pixel driving circuits.
  • a display device which includes the display module provided in any of the above embodiments, and a housing.
  • a smart watch which includes the display module provided in any of the above embodiments, and a supporting component.
  • Figure 1A is a structural diagram of a display module in the prior art
  • Figure 1B is a structural diagram of another display module in the prior art
  • Figure 1C is a partial cross-sectional view of the flip-chip film of the display module provided in Figure 1B after being bent;
  • Figure 2 is a structural diagram of a display device according to some embodiments.
  • Figure 3A is a structural diagram of a display module in the display device provided in Figure 2;
  • Figure 3B is a structural diagram of another display module in the display device provided in Figure 2;
  • Figure 4 is a pixel layout diagram of a display device according to some embodiments.
  • Figure 5 is a pixel architecture diagram of a display device according to some embodiments.
  • Figure 6A is a cross-sectional view along section line CC of a display panel in the display device provided in Figure 4;
  • FIG. 6B is a cross-sectional view along section line CC of another display panel in the display device provided in FIG. 4;
  • Figure 7 is a schematic diagram of a pixel driving circuit according to some embodiments.
  • Figure 8A is a schematic diagram of another pixel driving circuit provided according to some embodiments.
  • Figure 8B is a schematic diagram of yet another pixel driving circuit provided according to some embodiments.
  • Figure 9A is a schematic diagram of yet another pixel driving circuit provided according to some embodiments.
  • Figure 9B is a schematic diagram of a pixel driving circuit provided according to other embodiments.
  • Figure 10 is a schematic diagram of another pixel driving circuit provided according to some embodiments.
  • Figure 11 is a schematic diagram of yet another pixel driving circuit provided according to some embodiments.
  • Figure 12 is a schematic diagram of another pixel driving circuit provided according to other embodiments.
  • Figure 13 is a schematic diagram of yet another pixel driving circuit provided according to other embodiments.
  • Figure 14 is a schematic diagram of a pixel driving circuit according to some embodiments.
  • Figure 15 is a schematic diagram of another pixel driving circuit according to some embodiments.
  • Figure 16 is a schematic diagram of yet another pixel driving circuit provided according to some embodiments.
  • Figure 17 is a schematic diagram of yet another pixel driving circuit provided according to some embodiments.
  • Figure 18 is a schematic diagram of yet another pixel driving circuit provided according to some embodiments.
  • Figure 19 is a schematic diagram of yet another pixel driving circuit provided according to some embodiments.
  • Figure 20 is a schematic diagram of yet another pixel driving circuit provided according to some embodiments.
  • Figure 21 is a schematic diagram of yet another pixel driving circuit provided according to some embodiments.
  • Figure 22 is a timing diagram of a pixel driving circuit provided in accordance with some embodiments.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • “Plural” means two or more.
  • connection and its derivatives may be used.
  • some embodiments may be described using the term “connected” to indicate that two or more components are in direct physical or electrical contact with each other.
  • the embodiments disclosed herein are not necessarily limited by the content herein.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and includes the following combinations of A, B and C: A only, B only, C only, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • ALS is used to sense light intensity, and the display brightness of the display device is adjusted according to the sensed light intensity. For example, if the light intensity sensed by the ALS is strong, a signal is output to adjust the display brightness to increase so that the user can clearly see the display screen of the display device. If the light intensity sensed by the ALS is weak, it outputs a signal to adjust the display brightness, so that the user can clearly see the display screen of the display device, reducing the adverse stimulation to the human eye caused by excessive display brightness, and at the same time reducing the display brightness. Brightness reduces battery consumption.
  • the ALS processes information according to the sensed light intensity and interacts with the processor in the display device, so that the processor controls the display brightness of the display device. In this way, the operation of the ALS and processor generates greater power consumption.
  • Display devices such as smart watches are often powered by batteries. Due to the limited energy storage capacity of the battery, the use of ALS is obviously not conducive to the battery life of the display device.
  • the display device 1000 includes at least two flexible circuit boards 1100 and a display panel 1200 . When the ALS 1300 is installed on the flexible circuit board 1100 and the flexible circuit board 1100 is bent to the non-display side of the display panel 1200, as shown in FIG.
  • the flexible circuit board 1100 has a certain hardness and is prone to warping, resulting in There is a gap between the ALS 1300 and the display panel 1200 and they cannot be in close contact. Then, the light-transmitting area H on the display panel 1200 where the ALS 1300 is exposed is misaligned with the ALS 1300. The light-transmitting area H cannot completely expose the ALS 1300, affecting the light sensitivity of the ALS 1300. Effect.
  • each film layer stack is a light-transmitting film layer to allow external ambient light to illuminate the ALS 1300.
  • peripheral components that operate with the ALS 1300 (such as two filter capacitors There are many devices, adjustable resistors, etc.), which occupies a large space, which is not conducive to making the display device 1000 thin and light.
  • some embodiments of the present application provide a display device that can automatically adjust the light according to the current ambient light intensity without adding an ALS, and can reduce the number of ALS attachment process steps and improve the process. efficiency and yield.
  • the above-mentioned display device can be a tablet computer, a monitor, a mobile phone, a billboard, a digital photo frame or a personal digital assistant (Personal Digital Assistant, PDA) or any other device with a display function.
  • the display device 2000 provided by some embodiments of the present application is a smart watch 2001.
  • the display device 2000 may also be an organic electroluminescent diode (Organic Light-Emitting Diode, OLED for short) display device, a quantum dot electroluminescent diode (Quantum Dot Light Emitting Diodes, QLED for short) display device, or an active matrix.
  • Organic light emitting diode Active-matrix organic light emitting diode, referred to as AMOLED
  • AMOLED Active-matrix organic light emitting diode
  • the following embodiments take an OLED display device as an example for detailed description.
  • the display device 2000 includes a display module 2200 and a housing 2100 .
  • the case 2100 includes components such as a frame 2101 and a back case (not shown in the figure), and is configured to provide protection and support for the display module 2200 .
  • the display device 2000 is a smart watch 2001.
  • the smart watch 2001 includes a display module 2200, a housing 2100 and a supporting component 2300.
  • the supporting component 2300 is configured to be connected to the housing 2100 to facilitate wearing the display device.
  • support member 2300 includes watch band 2301.
  • the display module 2200 includes a motherboard 2210 , a flexible circuit board 2220 , a chip-on-chip film 2230 and a display panel 2240 .
  • a central processing unit (Central Processing Unit, CPU for short) 2211 is provided on the main board 2210.
  • the main board 2210 is electrically connected to the flexible circuit board 2220, and is configured to control a timing controller (Timing Controller, TCON for short) 2222 to output timing control signals.
  • Timing Controller, TCON for short timing controller 2222 to output timing control signals.
  • the flexible circuit board 2220 and the chip-on-chip film 2230 are electrically connected through the second pin S2.
  • the flexible circuit board 2220 is provided with drive circuits such as a power manager 2221 and a TCON 2222.
  • the power manager 2221 is configured to process the processed power voltage signal. Transmitted to TCON 2222, chip-on-chip film 2230, and processor 2211 to power on TCON 2222, chip-on-chip film 2230, and processor 2211.
  • the chip on film 2230 (Chip On Film, COF for short) is electrically connected to the display panel 2240 through the first pin S1, and the driver chip 2231 is provided on the chip on film 2230.
  • the driver chip 2231 is a source driver IC.
  • the source driver chip is electrically connected to the plurality of pixel driver circuits 100 on the display panel 2240 and is configured to transmit data signals to the pixel driver circuits 100 .
  • TCON 2222 is electrically connected to the source driver chip and is configured to transmit timing control signals to the source driver chip to control the source driver chip to output the required data signals.
  • the display panel 2240 includes a display area AA (Active Area) and a peripheral area BB located on at least one side of the display area AA.
  • the peripheral area BB surrounds the display area AA for illustration.
  • the shapes of the peripheral area BB and the display area AA are not limited.
  • the display area AA includes a plurality of sub-pixel units (sub pixels) P arranged in an array.
  • the sub-pixels P arranged in a row along the horizontal direction X are called sub-pixels in the same row
  • the sub-pixel units P arranged in a row along the vertical direction Y are called sub-pixels in the same column.
  • the sub-pixel units P in the same row may be connected to at least one gate line GL and one light-emitting control signal line EM.
  • the sub-pixel units P in the same column can be connected to one data line DL.
  • the sub-pixel unit P is provided with a pixel driving circuit 100 and a light-emitting device 200 for controlling the sub-pixel unit P to perform display.
  • the gate line GL connected to the sub-pixel unit P is used to transmit the gate scanning signal gate to the pixel driving circuit 100 of the sub-pixel unit P.
  • the light emission control signal line EM connected to the sub-pixel unit P is used to transmit the enable signal em to the pixel driving circuit 100 of the sub-pixel unit P.
  • the reset scan signal line RS connected to the sub-pixel unit P is used to transmit the reset signal to the pixel driving circuit 100 of the sub-pixel unit P (the reset scan signal line RS is another gate line, that is, the gate line GL of the Nth row transmits The gate scanning signal gate is used as the reset signal reset of the N+1th row).
  • the data line DL connected to the sub-pixel unit P is used to transmit the data signal vdata to the pixel driving circuit 100 of the sub-pixel unit P.
  • the data signal Data comes from the source driving chip electrically connected to each data line DL.
  • the signal line electrically connected to the scan signal terminal Gate mentioned in subsequent embodiments is the gate line GL
  • the signal line electrically connected to the reset signal terminal Reset is the reset signal line RS
  • the signal line electrically connected to the enable signal terminal EM It is the light-emitting control signal line EM (not distinguished here).
  • the pixel driving circuit 100 and the light-emitting device 200 are illustrated below based on the specific film layer structure of the display panel 2240.
  • the display panel 2240 includes a stacked substrate 2241 , a driving circuit stack 2242 , a plurality of light emitting devices 200 and an encapsulation layer 2243 .
  • the substrate 2241 may be flexible, including polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate One of glycol ester (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC) and cellulose acetate propionate (CAP) or more.
  • PES polyethersulfone
  • PAR polyarylate
  • PEI polyetherimide
  • PEN polyethylene naphthalate
  • PEN polyethylene terephthalate
  • PET glycol ester
  • PPS polyphenylene sulfide
  • PI polyimide
  • PC polycarbonate
  • TAC cellulose triacetate
  • CAP cellulose acetate propionate
  • the material of the substrate 2241 includes polyimide (PI).
  • the driving circuit stack 2242 refers to the film layer where the arrays of multiple pixel driving circuits 100 are disposed, including a plurality of patterned conductive layers and insulating layers.
  • the pixel driving circuit 100 is disposed on the substrate 2241.
  • Each pixel driving circuit 100 includes a plurality of thin film transistors (Thin Film Transistor, TFT for short) and at least one capacitor Cst.
  • the driving circuit stack 2242 Perpendicular to the direction of the driving circuit stack 2242, the driving circuit stack 2242 includes a semiconductor layer 1, a gate insulating layer 2, a first gate metal layer 3, a first insulating layer 4, a second gate metal layer 5, and a second insulating layer 6 , conductive layer 7, third insulating layer 8 and flat layer 9.
  • the first gate metal layer 3 includes gate electrodes 31 of a plurality of TFTs, first plates 32 of a plurality of capacitors Cst, and a plurality of first gate scanning lines 33 (ie, gate lines GL).
  • the second gate metal layer 5 includes a plurality of second plates 51 of capacitors Cst and a plurality of second gate scanning lines 52 (ie, one gate line GL multiplexed as a reset signal line RS).
  • the conductive layer 7 includes source electrodes 71 and drain electrodes 72 of a plurality of TFTs, and a plurality of signal lines 73 (for example, including data signal lines DL, first voltage signal line VDD and the second voltage signal line VSS, etc.).
  • the plurality of light-emitting devices 200 are disposed on a side of the plurality of pixel driving circuits 100 away from the substrate 2241, and the light-emitting devices 200 are electrically connected to the pixel driving circuit 100.
  • the film layer in which the plurality of light-emitting devices 200 is located includes a plurality of pixel anodes 10 , a pixel defining layer 11 , a light-emitting functional layer 12 and a cathode layer 13 .
  • a light-emitting device 200 can be formed by overlapping orthographic projections of a pixel anode 10 (used to provide holes), a light-emitting functional layer 12 and a cathode layer 13 on the substrate 2241.
  • the pixel anode 10 and the cathode layer 13 inject holes and electrons into the light-emitting functional layer 12 respectively, and when the excitons (exciton) generated by the combination of holes and electrons transition from an excited state to a ground state, they emit light.
  • the encapsulation layer 2243 is disposed on the side of the cathode layer 13 away from the substrate 2241.
  • the encapsulation layer 2243 may be an encapsulation film.
  • the number of layers of packaging films included in the packaging layer 2243 is not limited.
  • the encapsulation layer 2243 may include one layer of encapsulation film, or may include two or more layers of encapsulation films that are stacked.
  • the encapsulation layer 2243 includes a three-layer material film of inorganic/organic/inorganic layered in sequence.
  • the inorganic material may be any one or more of silicon nitride (SiNx), silicon oxynitride (SiON), or silicon oxide (SiOx).
  • the transistors used in the pixel driving circuit 100 provided by the embodiments of the present disclosure may be thin film transistors (Thin Film Transistor, TFT for short), field effect transistors (Metal Oxide Semiconductor, MOS for short) or other transistors with the same characteristics. Switching devices, in the embodiments of the present disclosure, thin film transistors are used as examples for description.
  • the control electrode of each thin film transistor used in the pixel driving circuit 100 is the gate electrode of the transistor, the first electrode is one of the source electrode and the drain electrode of the thin film transistor, and the second electrode is the other of the source electrode and the drain electrode of the thin film transistor. Since the source and drain of the thin film transistor may be symmetrical in structure, the source and drain of the thin film transistor may be structurally indistinguishable. That is to say, the first electrode of the thin film transistor in the embodiment of the present disclosure There may be no difference in structure from the second pole.
  • the first electrode of the thin film transistor is a source electrode
  • the second electrode is a drain electrode
  • the first electrode of the transistor is a drain electrode
  • the drain, the second pole is the source.
  • the above-mentioned chip-on-chip film 2230 and the display panel 2240 are electrically connected through a plurality of first pins S1.
  • the chip-on-chip film 2230 is provided with a plurality of first pins S1, and the plurality of first pins are electrically connected to the driver chip 2231.
  • the peripheral area BB of the display panel 2240 is provided with a plurality of extension sections of the signal lines 73 (not shown in the figure).
  • the plurality of signal lines 73 are electrically connected to the plurality of pixel driving circuits 100 , and the extended sections of the plurality of signal lines 73 are electrically connected to the plurality of first pins S1 to realize the connection between the driving chip 2231 on the flip-chip film 2230 and the plurality of first pins S1 .
  • the pixel driving circuit 100 is electrically connected.
  • the above-mentioned encapsulation layer 2243 located in the peripheral area BB will expose the extension sections of the multiple signal lines 73 , that is, no encapsulation layer 2243 is provided on the extension sections of the multiple signal lines 73 to facilitate passage.
  • the conductive adhesive 14 is pasted on the extension sections of the plurality of signal lines 73 to achieve electrical connection between the extension sections of the plurality of signal lines 73 and the plurality of first pins S1 on the chip-on-chip film 2230 .
  • the display module 2200 further includes at least one photosensitive device 110 , and at least one pixel driving circuit 100 in the display panel 2240 includes the photosensitive device 110 .
  • At least one photosensitive device 110 is provided on one side surface of the flexible circuit board 2220 , and when the flexible circuit board 2220 is bent to the backlight side of the substrate 2241 , the photosensitive device 110 is Flexible circuit board 2220 is adjacent to substrate 2241.
  • the display panel 2240 is not provided with a film layer where the photosensitive device 110 is located.
  • a chip photoresistor RG is provided on the flexible circuit board 2220.
  • At least one pixel driving circuit 100 in the display panel 2240 is electrically connected to the chip photoresistor RG.
  • At least one photosensitive device 110 is provided on the display panel 2240 .
  • the film layer where the photosensitive device 110 is located ie, the photosensitive layer 17
  • the photosensitive layer 17 is disposed on a side of the plurality of pixel driving circuits 100 away from the substrate 2241.
  • the photosensitive layer 17 includes at least one photosensitive device 110 (not shown in the figure). Each photosensitive device 110 is electrically connected to the plurality of pixel driving circuits 100. connect.
  • the display panel 2240 may also include a touch layer 15 and a circular polarizer 16
  • the photosensitive layer 17 is disposed on the side of the circular polarizer 16 away from the substrate 2241 . In this way, the external ambient light shines on the photosensitive layer 17 through the glass cover 18, reducing the loss of light flux shining on the photosensitive device 110, and improving the sensing efficiency and sensitivity of the photosensitive device 110.
  • the display module 2200 has a light-transmitting area (not shown in the figure).
  • the light-transmitting area is provided with at least one photosensitive device 110 .
  • the light-transmitting area can transmit external ambient light to the photosensitive device 110 .
  • a pixel driving circuit 100 adjusts the brightness of the light-emitting device 200 in response to the photosensitive device 110
  • the processor 2211 can obtain the potential flowing through the photosensitive device 110 and perform information processing to adjust the brightness of the entire display area AA.
  • the brightness of the light emitting device 200 is adjusted.
  • This disclosure does not specifically limit the information interaction method between the processor 2211 and the pixel driving circuit 100 having the photosensitive device 110 .
  • the light-transmitting area is an opening (not shown in the figure) on the frame 2101, which exposes the photosensitive device 110 so that the photosensitive device 110 can sense light.
  • the light-transmitting area is located in the peripheral area BB of the display panel 2240.
  • the light-transmitting area is located close to the camera (not shown in the figure) of the display device 2000 to avoid the influence of the photosensitive device 110 on the aperture ratio of the display area AA.
  • the light-transmitting area is located in the display area AA of the display panel 2240 .
  • the light-transmitting area is the entire display area AA.
  • the photosensitive layer 17 includes multiple photosensitive devices 110, and each pixel driving circuit 100 is set to be electrically connected to one photosensitive device 110 to improve the photosensitive response efficiency.
  • Some embodiments of the present disclosure provide a pixel driving circuit 100 .
  • the pixel driving circuit 100 includes a photosensitive device 110 and a dimming subcircuit 120 .
  • the first end of the photosensitive device 110 is configured to receive the control signal Ctl, and the second end of the photosensitive device 110 is electrically connected to the first node N1.
  • the control signal Ctl is various types of signals output by the control terminal OP. For example, as shown in FIGS.
  • the control signal Ctl can be some original signals in the multiplexed pixel driving circuit 100, such as em signal, vinit signal, vdd signal, gate signal, reset signal; it may also be the voltage signal of some nodes in the multiplexed pixel driving circuit 100, such as the voltage signal of the second node N2, the voltage signal of the third node N3 and the voltage signal of the fourth node N4. voltage signal.
  • the control The control signal Ctl does not affect the driving process of the pixel driving circuit 100, and only allows the light-emitting device 200 to emit light normally while the pixel driving circuit 100 drives the light-emitting device 200 to emit light.
  • the second node N2, the third node N3, and the fourth node N4 are equivalent circuit nodes in the pixel driving circuit 100.
  • the resistance of the photosensitive device 110 changes as the intensity of light shining on the photosensitive device 110 changes, and the photosensitive device 110 is configured to adjust the voltage of the first node N1 based on the control signal Ctl.
  • the resistance of the photosensitive device 110 increases as the intensity of light shining on the photosensitive device 110 increases, and the voltage and current flowing through the photosensitive device 110 decrease, that is, the voltage and current of the first node N1 decrease.
  • the potential decreases as the intensity of light irradiated on the photosensitive device 110 increases to control the conduction state of the dimming sub-circuit 120 .
  • FIG. 8A the resistance of the photosensitive device 110 increases as the intensity of light shining on the photosensitive device 110 increases, and the voltage and current flowing through the photosensitive device 110 decrease, that is, the voltage and current of the first node N1 decrease.
  • the potential decreases as the intensity of light irradiated on the photosensitive device 110 increases to control the conduction state of the dimming sub-circuit 120 .
  • the resistance of the photosensitive device 110 decreases as the intensity of light shining on the photosensitive device 110 increases, and the voltage and current flowing through the photosensitive device 110 increase, that is, the potential of the first node N1 increases with The intensity of light irradiated on the photosensitive device 110 increases to control the conduction state of the dimming sub-circuit 120 .
  • the characteristics of the photosensitive device 110 are related to the material used to make the photosensitive device 110, and the limit potential of the first node N1 (that is, the potential at which the control signal Ctl is transmitted to the first node N1 when the resistance of the photosensitive device 110 is maximum and minimum) can
  • the dimming sub-circuit 120 is controlled to be turned on, and at least part of the first voltage signal vdd of the first voltage terminal VDD is transmitted to the light-emitting device 200, so that the light-emitting device 200 emits light.
  • the photosensitive device 110 includes one or more of a photoresistor RG, a photodiode, and a phototransistor, and the settings are selected according to the need to adjust the voltage of the first node N1.
  • the photosensitive device 110 is a photoresistor RG as an example for explanation.
  • the first node N1 is electrically connected to the light-adjusting sub-circuit 120 , and the light-adjusting sub-circuit 120 is connected between the first voltage terminal VDD and the light-emitting device 200 .
  • the conduction state of the dimming sub-circuit 120 changes with the change of the voltage of the first node N1, so that under the control of the voltage of the first node N1, based on the voltage from the first node N1
  • the first voltage signal vdd at the voltage terminal VDD adjusts the brightness of the light-emitting device 200 .
  • the voltage (and current) transmitted from the first voltage signal vdd to the light-emitting device 200 increases, and the brightness of the light-emitting device 200 increases.
  • the potential of the first node N1 decreases and the conduction degree of the dimming sub-circuit 120 decreases. Then the voltage (and current) transmitted from the first voltage signal vdd to the light-emitting device 200 decreases, and the brightness of the light-emitting device 200 decreases. weaken.
  • the pixel driving circuit 100 automatically adjusts the brightness of the light-emitting device 200 through the photosensitive device 110 and the dimming sub-circuit 120 electrically connected thereto, without the need to interact with additional dimming components, thereby reducing the complexity of the circuit structure.
  • the above-mentioned light-emitting device 200 may be a diode with self-luminous properties such as OLED, QLED, and LED. Those skilled in the art can select settings according to actual needs.
  • the pixel driving circuit 100 further includes a driving transistor TD.
  • the control electrode of the driving transistor TD is electrically connected to the second node N2
  • the first electrode of the driving transistor TD is electrically connected to the third node N3
  • the second electrode of the driving transistor TD is electrically connected to the fourth node N4.
  • the dimming sub-circuit 120 includes a first transistor T1 , and the first transistor T1 is connected between the fourth node N4 and the light-emitting device 200 time, and the control electrode of the first transistor T1 is electrically connected to the first node N1.
  • the dimming sub-circuit 120 includes a first transistor T1, the first transistor T1 is connected between the first voltage terminal VDD and the third node N3, and The control electrode of the first transistor T1 is electrically connected to the first node N1.
  • the pixel driving circuit 100 includes a driving transistor TD and a dimming sub-circuit 120 connected in series between the first voltage terminal VDD and the light-emitting device 200 .
  • the driving transistor TD and the dimming subcircuit 120 work together to control the light emitting device 200 to emit light.
  • the relative positional relationship between the light-adjusting sub-circuit 120 and the driving transistor TD does not affect the control of the conduction state of the light-adjusting sub-circuit 120 by the potential of the first node N1 and can be adjusted according to the actual situation.
  • the pixel driving circuit 100 further includes a capacitor Cst, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.
  • the first plate of the capacitor Cst is electrically connected to the first voltage terminal VDD, and the second plate of the capacitor Cst is electrically connected to the second node N2.
  • the control electrode of the fourth transistor T4 is electrically connected to the scan signal terminal Gate, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3.
  • the control electrode of the fifth transistor T5 is electrically connected to the scan signal terminal Gate, the first electrode of the fifth transistor T5 is electrically connected to the fourth node N4, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2.
  • the control electrode of the sixth transistor T6 is electrically connected to the reset signal terminal Reset, the first electrode of the sixth transistor T6 is electrically connected to the initialization signal terminal Vinit, and the second electrode of the sixth transistor T6 is connected to the second node N2.
  • the control electrode of the seventh transistor T7 is electrically connected to the scanning signal terminal Gate, the first electrode of the seventh transistor T7 is electrically connected to the initialization signal terminal Vinit, and the second electrode of the seventh transistor T7 is electrically connected to the light-emitting device 200 .
  • the working process of the pixel driving circuit 100 will be exemplified below with reference to the timing of the output signals of the enable signal terminal EM, the scanning signal terminal Gate, and the reset signal terminal Reset shown in FIG. 22 .
  • the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 in the pixel driving circuit 100 are P-type transistors, and the first voltage signal vdd transmitted by the first voltage terminal VDD is a high level signal, The second voltage signal vss transmitted by the second voltage terminal VSS is a low-level signal and will be explained as an example.
  • the photosensitive device 110 only affects the conduction state of the light-adjusting sub-circuit 120, that is, the potential of the first voltage signal vdd transmitted by the light-adjusting sub-circuit 120 to the light-emitting device 200 changes with the intensity of light irradiating on the photosensitive device 110. And change.
  • the driving process of the pixel driving circuit 100 may include a first phase P1, a second phase P2, and a third phase P3.
  • first phase P1 a first phase
  • second phase P2 a second phase
  • third phase P3 a third phase
  • the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are all turned off.
  • Sixth transistor T6 is turned on, and the initialization signal vinit from the initialization signal terminal Vinit is transmitted to the second node N2 to initialize the storage capacitor Cst and the control electrode of the drive transistor TD.
  • the light-adjusting sub-circuit 120 is turned off, the line between the first voltage terminal VDD and the second voltage terminal VSS is open circuit, and the light-emitting device 200 does not emit light.
  • the fourth transistor T4 and the fifth transistor T5 are turned on, and the sixth transistor T6 is turned off.
  • the data signal vdata from the data signal terminal Vdata is written in the capacitor Cst, and the threshold voltage of the driving transistor TD is written in the capacitor Cst.
  • the potential of the second node N2 is vdata+Vth.
  • the seventh transistor T7 is turned on, and the initialization signal vinit from the initialization signal terminal Vinit is transmitted to the anode of the light-emitting device 200 to initialize the light-emitting device 200 .
  • the light-adjusting sub-circuit 120 is turned off, the line between the first voltage terminal VDD and the second voltage terminal VSS is open circuit, and the light-emitting device 200 does not emit light.
  • the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all turned off, the capacitor Cst is discharged, the second node N2 maintains a low potential (vdata+Vth), and the driving transistor TD is turned on.
  • the dimming sub-circuit 120 is turned on, the line between the first voltage terminal VDD and the second voltage terminal VSS is a path, and the light-emitting device 200 emits light.
  • the potential of the third node N3 is vdd.
  • the driving transistor TD is turned on, that is, when Vdata+Vth-Vdd>Vth, the potential of the fourth node N4 is a high potential.
  • Vth when the driving transistor TD is a P-type transistor, Vth ⁇ 0.
  • Vth When the drive transistor TD is an N-type transistor, Vth>0.
  • the pixel driving circuit 100 controls the light-emitting device 200 to emit light, and the enable signal terminal EM and the scanning signal terminal Gate in the pixel driving circuit 100 , the reset signal terminal Reset, the initialization signal terminal Vinit, the first voltage terminal VDD, the second voltage terminal VSS, the second node N2, the third node N3 and the fourth node N4 all have potential signal outputs.
  • the number and type of transistors in the dimming sub-circuit 120 are set so that the pixel driving circuit 100 realizes initialization of the capacitor Cst in the first stage P1, realizes data writing into the capacitor Cst in the second stage P2, and realizes light emission in the third stage P3.
  • the normal driving process of the device 200 emitting light is set so that the pixel driving circuit 100 realizes initialization of the capacitor Cst in the first stage P1, realizes data writing into the capacitor Cst in the second stage P2, and realizes light emission in the third stage P3.
  • the normal driving process of the device 200 emitting light.
  • the description will be made by taking the light-adjusting sub-circuit 120 including two transistors as an example.
  • the light modulation sub-circuit 120 includes a first transistor T1 and a second transistor T2.
  • the connection relationship between the first transistor T1 and the second transistor T2 is as shown in Figure 9A, Figure 10, and Figure 11
  • the control electrode of the first transistor T1 is electrically connected to the first node N1
  • the first electrode of the first transistor T1 is electrically connected to the fourth node N4
  • the second electrode of the first transistor T1 is electrically connected to the light-emitting device 200.
  • the control electrode of the second transistor T2 is electrically connected to the first node N1 or the enable signal terminal EM.
  • the first electrode of the second transistor T2 is electrically connected to the first voltage terminal VDD.
  • the second electrode of the second transistor T2 is electrically connected to the third node. N3 electrical connection.
  • the first end of the photosensitive device 110 is electrically connected to the enable signal terminal EM, and the control signal Ctl received by the first end of the photosensitive device 110 is the enable signal em.
  • the control electrodes of the first transistor T1 and the second transistor T2 are both electrically connected to the first node N1;
  • the first pole of the first transistor T1 is electrically connected to the first voltage terminal VDD, the second pole of the second transistor T2 is electrically connected to the third node N3; the first pole of the first transistor T1 is electrically connected to the fourth node N4, and the second pole of the first transistor T1 electrically connected to the light emitting device 200 .
  • the enable signal em output by the enable signal terminal EM flows to the first node N1 through the photosensitive device 110.
  • the first transistor T1 and the second transistor T2 of the light-adjusting sub-circuit 120 The conduction degree of the first voltage terminal VDD changes, thereby controlling the size of the first voltage signal vdd transmitted from the first voltage terminal VDD to the light-emitting device 200, and adjusting the brightness of the light-emitting device 200.
  • the control electrode of the first transistor T1 of the light-adjusting subcircuit 120 is electrically connected to the first node N1 , and the first electrode of the first transistor T1 is electrically connected to the fourth node N4 .
  • the second electrode of the first transistor T1 is electrically connected to the light emitting device 200 .
  • the control electrode of the second transistor T2 is electrically connected to the enable signal terminal EM, the first electrode of the second transistor T2 is electrically connected to the first voltage terminal VDD, and the second electrode of the second transistor T2 is electrically connected to the third node N3.
  • the enable signal em output by the enable signal terminal EM flows to the first node N1 through the photosensitive device 110.
  • the conduction degree of the first transistor T1 of the light modulating sub-circuit 120 is uniform. Changes occur, thereby controlling the magnitude of the first voltage signal vdd from the first voltage terminal VDD transmitted to the light-emitting device 200 , that is, controlling the magnitude of the potential of the fourth node N4 transmitted to the light-emitting device 200 to adjust the brightness of the light-emitting device 200 .
  • the first end of the photosensitive device 110 is electrically connected to the scanning signal terminal Gate
  • the control signal Ctl received by the first end of the photosensitive device 110 is the scanning signal gate
  • the second end of the photosensitive device 110 The terminal is electrically connected to the first node N1.
  • the control electrode of the first transistor T1 of the light-adjusting sub-circuit 120 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fourth node N4, and the second electrode of the first transistor T1 is electrically connected to the light-emitting device 200. connect.
  • the control electrode of the second transistor T2 is electrically connected to the enable signal terminal EM, the first electrode of the second transistor T2 is electrically connected to the first voltage terminal VDD, and the second electrode of the second transistor T2 is electrically connected to the third node N3.
  • the scanning signal gate output by the scanning signal terminal Gate flows to the first node N1 through the photoresistor RG.
  • the conduction degree of the first transistor T1 of the dimming sub-circuit 120 changes, thereby controlling the size of the first voltage signal vdd transmitted from the first voltage terminal VDD to the light-emitting device 200 , that is, controlling the fourth
  • the potential of the node N4 is transmitted to the size of the light-emitting device 200 to adjust the brightness of the light-emitting device 200 .
  • the dimming sub-circuit 120 includes a first transistor T1 and a second transistor T2.
  • the connection relationship between the first transistor T1 and the second transistor T2 is as shown in FIG. 9B, FIG. 12 and FIG. 13.
  • the first transistor The control electrode of T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the first voltage terminal VDD, and the second electrode of the first transistor T1 is electrically connected to the third node N3.
  • the control electrode of the second transistor T2 is electrically connected to the enable signal terminal EM, the first electrode of the second transistor T2 is electrically connected to the fourth node N4, and the second electrode of the second transistor T2 is electrically connected to the light-emitting device 200 .
  • the first end of the photosensitive device 110 is electrically connected to the enable signal terminal EM or the scan signal terminal Gate.
  • the first end of the photosensitive device 110 is electrically connected to the enable signal terminal EM
  • the control signal Ctl received by the first end of the photosensitive device 110 is the enable signal em
  • the second end of the photosensitive device 110 The terminal is electrically connected to the first node N1.
  • the control electrode of the first transistor T1 of the dimming sub-circuit 120 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the first voltage terminal VDD, and the second electrode of the first transistor T1 is electrically connected to the third node. N3 electrical connection.
  • the control electrode of the second transistor T2 is electrically connected to the enable signal terminal EM, the first electrode of the second transistor T2 is electrically connected to the fourth node N4, and the second electrode of the second transistor T2 is electrically connected to the light-emitting device 200 .
  • the enable signal em output by the enable signal terminal EM flows to the first node N1 through the photosensitive device 110.
  • the conduction degree of the first transistor T1 of the light-adjusting sub-circuit 120 is changed. change, thereby controlling the magnitude of the first voltage signal vdd transmitted from the first voltage terminal VDD to the third node N3 to adjust the brightness of the light emitting device 200 .
  • the first end of the photoresistor RG is electrically connected to the scanning signal terminal Gate
  • the control signal Ctl received by the first end of the photoresistor RG is the scanning signal gate
  • the second end of the photoresistor RG is connected to the scanning signal terminal Gate.
  • the first node N1 is electrically connected.
  • the control electrode of the first transistor T1 of the dimming sub-circuit 120 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the first voltage terminal VDD, and the second electrode of the first transistor T1 is electrically connected to the third node. N3 electrical connection.
  • the control electrode of the second transistor T2 is electrically connected to the enable signal terminal EM, the first electrode of the second transistor T2 is electrically connected to the fourth node N4, and the second electrode of the second transistor T2 is electrically connected to the light-emitting device 200 .
  • the scanning signal gate output by the scanning signal terminal Gate flows to the first node N1 through the photoresistor RG.
  • the conduction degree of the first transistor T1 of the photomodulation sub-circuit 120 changes. Therefore, the magnitude of the first voltage signal vdd transmitted from the first voltage terminal VDD to the third node N3 is controlled to adjust the brightness of the light-emitting device 200 by adjusting the potential magnitude of the third node N3.
  • the description takes the light-adjusting sub-circuit 120 including three transistors as an example. As shown in FIGS. 14 to 21 , the light modulation sub-circuit 120 includes a first transistor T1 , a second transistor T2 and a third transistor T3 .
  • connection relationship between the first transistor T1, the second transistor T2 and the third transistor T3 is as shown in Figures 14 to 21.
  • the control electrode of the second transistor T2 is electrically connected to the enable signal terminal EM.
  • the first electrode of the transistor T2 is electrically connected to the first voltage terminal VDD, and the second electrode of the second transistor T2 is electrically connected to the third node N3.
  • the third transistor T3 and the first transistor T1 are connected in series between the fourth node N4 and the light emitting device 200 , and the control electrode of the third transistor T3 is electrically connected to the enable signal terminal EM.
  • the control electrode of the third transistor T3 is electrically connected to the enable signal terminal EM
  • the first electrode of the third transistor T3 is electrically connected to the fourth node N4
  • the third node of the third transistor T3 is electrically connected to the enable signal terminal EM.
  • the two poles are electrically connected to the first pole of the first transistor T1.
  • the control electrode of the first transistor T1 is electrically connected to the first node N1
  • the second electrode of the first transistor T1 is electrically connected to the light emitting device 200.
  • the light-emitting device 200 is electrically connected to the second voltage terminal VSS.
  • the normal driving process of the pixel driving circuit 100 is implemented by considering the connection relationship between the second transistor T2 and the third transistor T3. In this way, the first end of the photoresistor RG electrically connected to the control electrode of the first transistor T1 can be connected to the enable signal end. Any one of EM, scanning signal terminal Gate, reset signal terminal Reset, initialization signal terminal Vinit, first voltage terminal VDD, second voltage terminal VSS, second node N2, third node N3 or fourth node N4 is electrically connected .
  • the first end of the photoresistor RG is electrically connected to the scanning signal terminal Gate, and the control signal Ctl received by the first end of the photoresistor RG is the scanning signal gate.
  • the scanning signal gate output by the scanning signal terminal Gate outputs a high-level signal in the light-emitting phase P3.
  • the scanning signal gate output by the scanning signal terminal Gate flows to the first node N1 through the photoresistor RG.
  • the conduction degree of the first transistor T1 of the photomodulation sub-circuit 120 changes. Therefore, the magnitude of the first voltage signal vdd from the first voltage terminal VDD transmitted to the light-emitting device 200 is controlled, that is, the magnitude of the potential transmitted from the second pole of the third transistor T3 to the light-emitting device 200 is controlled, so as to adjust the intensity of the light-emitting device 200 .
  • brightness the magnitude of the first voltage signal vdd from the first voltage terminal VDD transmitted to the light-emitting device 200
  • the first end of the photoresistor RG is electrically connected to the reset signal terminal Reset, and the control signal Ctl received by the first end of the photoresistor RG is the reset signal reset.
  • the reset signal reset output by the reset signal terminal Reset outputs a low-level signal during the light-emitting phase P3.
  • the reset signal reset output by the reset signal terminal Reset flows to the first node N1 through the photoresistor RG.
  • the conduction degree of the first transistor T1 of the dimming sub-circuit 120 changes. Therefore, the magnitude of the first voltage signal vdd from the first voltage terminal VDD transmitted to the light-emitting device 200 is controlled, that is, the magnitude of the potential transmitted from the second pole of the third transistor T3 to the light-emitting device 200 is controlled, so as to adjust the intensity of the light-emitting device 200 . brightness.
  • the first terminal of the photoresistor RG is connected to the initialization signal terminal Vinit, and the control signal Ctl received by the first terminal of the photoresistor RG is the initial signal vinit.
  • the initial signal vinit is a constant low level signal.
  • the initial signal vinit output by the initialization signal terminal Vinit flows to the first node N1 through the photoresistor RG.
  • the conduction degree of the first transistor T1 of the dimming sub-circuit 120 changes. Therefore, the magnitude of the first voltage signal vdd from the first voltage terminal VDD transmitted to the light-emitting device 200 is controlled, that is, the magnitude of the potential transmitted from the second pole of the third transistor T3 to the light-emitting device 200 is controlled, so as to adjust the intensity of the light-emitting device 200 . brightness.
  • the first end of the photoresistor RG is electrically connected to the first voltage terminal VDD, and the control signal Ctl received by the first end of the photoresistor RG is the first voltage signal vdd.
  • the first voltage signal vdd is a constant high level signal.
  • the first voltage signal vdd output by the first voltage terminal VDD flows to the first node N1 through the photoresistor RG.
  • the conduction degree of the first transistor T1 of the light sub-circuit 120 is adjusted. changes, thereby controlling the transmission of the first voltage signal vdd from the first voltage terminal VDD to the size of the light-emitting device 200, that is, controlling the transmission of the potential from the second pole of the third transistor T3 to the size of the light-emitting device 200, to adjust the light emission.
  • the brightness of the device 200 is adjusted.
  • the first end of the photoresistor RG is electrically connected to the second voltage terminal VSS, and the control signal Ctl received by the first end of the photoresistor RG is the second voltage signal vss.
  • the second voltage signal vss is a constant low level signal.
  • the second voltage signal vss output by the second voltage terminal VSS flows to the first node N1 through the photoresistor RG.
  • the conduction degree of the first transistor T1 of the light sub-circuit 120 is adjusted. changes, thereby controlling the transmission of the first voltage signal vdd from the first voltage terminal VDD to the size of the light-emitting device 200, that is, controlling the transmission of the potential from the second pole of the third transistor T3 to the size of the light-emitting device 200, to adjust the light emission.
  • the brightness of the device 200 is adjusted.
  • the first end of the photoresistor RG is electrically connected to the second node N2, and the control signal Ctl received by the first end of the photoresistor RG is the potential of the second node N2, that is, vdata+Vth .
  • the second node N2 is a low level signal.
  • the potential of the second node N2 flows to the first node N1 through the photoresistor RG.
  • the conduction degree of the first transistor T1 of the light modulation sub-circuit 120 changes, thereby controlling
  • the first voltage signal vdd from the first voltage terminal VDD is transmitted to the magnitude of the light-emitting device 200 , that is, the potential from the second pole of the third transistor T3 is transmitted to the magnitude of the light-emitting device 200 to adjust the brightness of the light-emitting device 200 .
  • the first end of the photoresistor RG is electrically connected to the third node N3, and the control signal Ctl received by the first end of the photoresistor RG is the potential of the third node N3, that is, at the third In stage P3, the first voltage terminal VDD transmits the first voltage signal vdd to the third node N3.
  • the potential of the third node N3 is a high-level signal.
  • the potential of the third node N3 flows to the first node N1 through the photoresistor RG.
  • the conduction degree of the first transistor T1 of the light modulating sub-circuit 120 changes, thereby controlling
  • the first voltage signal vdd from the first voltage terminal VDD is transmitted to the magnitude of the light-emitting device 200 , that is, the potential from the second pole of the third transistor T3 is transmitted to the magnitude of the light-emitting device 200 to adjust the brightness of the light-emitting device 200 .
  • the first end of the photoresistor RG is electrically connected to the fourth node N4, and the control signal Ctl received by the first end of the photoresistor RG is the potential of the fourth node N4, that is, at the third Stage P3, fourth node
  • the potential of N4 is a high level signal.
  • the potential of the fourth node N4 flows to the first node N1 through the photoresistor RG.
  • the conduction degree of the first transistor T1 of the light modulation sub-circuit 120 changes, thereby controlling
  • the first voltage signal vdd from the first voltage terminal VDD is transmitted to the magnitude of the light-emitting device 200 , that is, the potential from the second pole of the third transistor T3 is transmitted to the magnitude of the light-emitting device 200 to adjust the brightness of the light-emitting device 200 .
  • the dimming subcircuit 120 includes a first transistor T1 and a second transistor T2
  • the sixth transistor T6 and the seventh transistor T7 are both P-type transistors
  • the first transistor T1 is an N-type transistor.
  • the dimming sub-circuit 120 when the dimming sub-circuit 120 also includes a third transistor T3 , the driving transistor TD, the second transistor T2 , the third transistor T3 and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all P-type transistors, and the first transistor T1 is an N-type transistor.
  • the first end of the photosensitive device 110 is connected to the enable signal end EM and the reset signal end.
  • the polarity of the first transistor T1 is consistent with the driving transistor TD, the second transistor T2 and the fourth transistor T4.
  • the polarity of the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 is the same; in the case where the dimming sub-circuit 120 also includes a third transistor T3, the polarity of the first transistor T1 is also the same as that of the third transistor T3. The polarity is the same.
  • the dimming subcircuit 120 includes a first transistor T1 and a second transistor T2
  • the driving transistor TD, the second transistor T2, and the fourth transistor T4 are all P-type transistors, so the first transistor T1 is a P-type transistor.
  • the fifth transistor T5 is a P-type transistor.
  • the dimming sub-circuit 120 when the dimming sub-circuit 120 also includes a third transistor T3 , the driving transistor TD, the second transistor T2 , the third transistor T3 and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all P-type transistors, so the first transistor T1 is a P-type transistor.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种像素驱动电路（100），包括光敏器件（110）和调光子电路（120）。光敏器件（110）的第一端被配置为接收控制信号，光敏器件（110）的第二端与第一节点（N1）电连接；光敏器件（110）被配置为基于控制信号，调节第一节点（N1）的电压。调光子电路（120）连接在第一电压端（VDD）和发光器件（200）之间，且与第一节点（N1）电连接。调光子电路（120）的导通状态随第一节点（N1）的电压的变化而变化，调光子电路（120）被配置为在第一节点（N1）的电压的控制下，基于来自第一电压端（VDD）的第一电压信号，调节发光器件（200）的亮度。

Description

像素驱动电路、显示模组及显示装置、智能手表
本申请要求于2022年04月22日提交的、申请号为202210427079.0的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示技术领域，尤其涉及一种像素驱动电路、显示模组及显示装置、智能手表。
背景技术
目前，大多显示装置能够实现随着环境亮度进行显示亮度的自动调节的效果。其中，实现亮度自动调节功能的是环境光传感器(Ambient Light Sensor，简称ALS)。通常，显示装置包括显示面板和至少一个柔性电路板，柔性电路板上设置ALS和多个外围器件，柔性电路板被配置为将ALS与显示面板电连接。
发明内容
一方面，提供了一种像素驱动电路。像素驱动电路包括光敏器件和调光子电路。所述光敏器件的第一端被配置为接收控制信号，所述光敏器件的第二端与第一节点电连接；所述光敏器件的电阻随照射在所述光敏器件上的光照强度的变化而变化，所述光敏器件被配置为基于所述控制信号，调节所述第一节点的电压。所述调光子电路连接在第一电压端和发光器件之间，且与所述第一节点电连接；所述调光子电路的导通状态随所述第一节点的电压的变化而变化，所述调光子电路被配置为在所述第一节点的电压的控制下，基于来自所述第一电压端的第一电压信号，调节所述发光器件的亮度。
在一些实施例中，所述像素驱动电路还包括驱动晶体管。所述驱动晶体管的控制极与第二节点电连接，所述驱动晶体管的第一极与第三节点电连接，所述驱动晶体管的第二极与第四节点电连接。所述调光子电路包括第一晶体管，连接在所述第四节点与所述发光器件之间，且所述第一晶体管的控制极与所述第一节点电连接。
在一些实施例中，所述光敏器件的第一端与使能信号端电连接。所述调光子电路还包括第二晶体管，所述第二晶体管的控制极与所述第一节点或所述使能信号端电连接，所述第二晶体管的第一极与所述第一电压端电连接，所述第二晶体管的第二极与所述第三节点电连接。
在一些实施例中，所述光敏器件的第一端与扫描信号端电连接。所述调光子电路还包括第二晶体管，所述第二晶体管的控制极与使能信号端电连接，所述第二晶体管的第一极与所述第一电压端电连接，所述第二晶体管的第二极与所述第三节点电连接。
在另一些实施例中，所述光敏器件的第一端与使能信号端、扫描信号端、复位信号端、初始化信号端、所述第一电压端、第二电压端、所述第二节点、所述第三节点或所述第四 节点中的任一者电连接；其中，所述发光器件与所述第二电压端电连接。
所述调光子电路还包括第二晶体管和第三晶体管。所述第二晶体管的控制极与使能信号端电连接，所述第二晶体管的第一极与所述第一电压端电连接，所述第二晶体管的第二极与所述第三节点电连接。所述第三晶体管的控制极与所述使能信号端电连接，所述第三晶体管连接在所述第四节点和所述发光器件之间，且所述第三晶体管与所述第一晶体管串联。
在又一些实施例中，所述像素驱动电路还包括驱动晶体管，所述驱动晶体管的控制极与第二节点电连接，所述驱动晶体管的第一极与第三节点电连接，所述驱动晶体管的第二极与第四节点电连接。所述调光子电路包括第一晶体管，所述第一晶体管的控制极与所述第一节点电连接，所述第一晶体管的第一极与所述第一电压端电连接，所述第一晶体管的第二极与所述第三节点电连接。
在一些实施例中，所述光敏器件的第一端与使能信号端或扫描信号端电连接。所述调光子电路还包括第二晶体管，所述第二晶体管的控制极与所述使能信号端电连接，所述第二晶体管的第一极与所述第四节点电连接，所述第二晶体管的第二极与所述发光器件电连接。
在一些实施例中，所述像素驱动电路还包括电容器、第四晶体管、第五晶体管、第六晶体管和第七晶体管。所述电容器的第一极板与所述第一电压端电连接，所述电容器的第二极板与所述第二节点电连接。所述第四晶体管的控制极与扫描信号端电连接，所述第四晶体管的第一极与数据信号端电连接，所述第四晶体管的第二极与所述第三节点电连接。所述第五晶体管的控制极与所述扫描信号端电连接，所述第五晶体管的第一极与所述第四节点电连接，所述第五晶体管的第二极与所述第二节点电连接。所述第六晶体管的控制极与复位信号端电连接，所述第六晶体管的第一极与初始化信号端电连接，所述第六晶体管的第二极与所述第二节点电连接。所述第七晶体管的控制极与所述扫描信号端电连接，所述第七晶体管的第一极与所述初始化信号端电连接，所述第七晶体管的第二极与所述发光器件电连接。
在一些实施例中，在所述光敏器件的第一端与所述第一电压端、所述扫描信号端、所述第三节点和所述第四节点中的任一者电连接的情况下，所述第一晶体管的极性，与所述驱动晶体管、所述第二晶体管、所述第四晶体管～所述七晶体管的极性相反；在所述调光子电路还包括第三晶体管的情况下，所述第一晶体管的极性还与所述第三晶体管的极性相反。所述光敏器件的第一端与所述使能信号端、所述复位信号端、所述初始化信号端、第二电压端和所述第二节点中的任一者电连接的情况下，所述第一晶体管的极性，与所述驱动晶体管、所述第二晶体管、及所述第四晶体管～所述七晶体管的极性相同；在所述调光子电路还包括第三晶体管的情况下，所述第一晶体管的极性还与所述第三晶体管的极性相 同。
另一方面，提供了一种显示模组。所述显示模组包括衬底、多个如上述任一实施例提供的像素驱动电路和多个发光器件。所述多个像素驱动电路设置于所述衬底上。所述多个发光器件设置于多个所述像素驱动电路远离所述衬底的一侧，所述发光器件与所述像素驱动电路电连接。
在一些实施例中，所述显示模组具有透光区域，所述透光区域设置有至少一个所述光敏器件，每个所述光敏器件与多个所述像素驱动电路电连接。
在一些实施例中，所述显示模组还包括光敏层，所述光敏层设置于所述多个像素驱动电路远离所述衬底的一侧，所述光敏层包括多个所述光敏器件，每个所述光敏器件与一个或多个所述像素驱动电路电连接。
在一些实施例中，所述显示模组还包括覆晶薄膜和柔性电路板。所述覆晶薄膜与多个所述像素驱动电路电连接。所述柔性电路板与所述覆晶薄膜电连接；所述柔性电路板的一侧表面设有至少一个所述光敏器件，且在所述柔性电路板弯折至所述衬底的背光侧的情况下，所述光敏器件相对于所述柔性电路板靠近所述衬底。其中，每个所述光敏器件与多个所述像素驱动电路电连接。
又一方面，提供了一种显示装置，所述显示装置包括如上述任一实施例提供的显示模组，以及壳体。
又一方面，提供了一种智能手表，所述智能手表包括如上述任一实施例提供的显示模组，以及支撑部件。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。此外，以下描述中的附图可以视作示意图，并非对本申请实施例所涉及的产品的实际尺寸的限制。
图1A为现有技术中的一种显示模组的结构图；
图1B为现有技术中的另一种显示模组的结构图；
图1C为图1B提供的显示模组的覆晶薄膜弯折后的局部剖视图；
图2为根据一些实施例提供的一种显示装置的结构图；
图3A为图2提供的显示装置中一种显示模组的结构图；
图3B为图2提供的显示装置中另一种显示模组的结构图；
图4为根据一些实施例提供的一种显示装置的像素布置图；
图5为根据一些实施例提供的一种显示装置的像素架构图；
图6A为图4提供的显示装置中的一种显示面板沿剖面线CC的剖视图；
图6B为图4提供的显示装置中的另一种显示面板沿剖面线CC的剖视图；
图7为根据一些实施例提供的一种像素驱动电路原理图；
图8A为根据一些实施例提供的另一种像素驱动电路原理图；
图8B为根据一些实施例提供的又一种像素驱动电路原理图；
图9A为根据一些实施例提供的又一种像素驱动电路原理图；
图9B为根据另一些实施例提供的一种像素驱动电路原理图；
图10为根据一些实施例提供的另一种像素驱动电路原理图；
图11为根据一些实施例提供的又一种像素驱动电路原理图；
图12为根据另一些实施例提供的另一种像素驱动电路原理图；
图13为根据另一些实施例提供的又一种像素驱动电路原理图；
图14为根据又一些实施例提供的一种像素驱动电路原理图；
图15为根据又一些实施例提供的另一种像素驱动电路原理图；
图16为根据又一些实施例提供的又一种像素驱动电路原理图；
图17为根据又一些实施例提供的又一种像素驱动电路原理图；
图18为根据又一些实施例提供的又一种像素驱动电路原理图；
图19为根据又一些实施例提供的又一种像素驱动电路原理图；
图20为根据又一些实施例提供的又一种像素驱动电路原理图；
图21为根据又一些实施例提供的又一种像素驱动电路原理图；
图22为根据一些实施例提供的像素驱动电路的时序图。
具体实施方式
下面将结合附图，对本申请一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本申请保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例”、“特定示例”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本申请的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请实施例的描述中，除非另有说明， “多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
目前，采用ALS进行光照强度感应，并根据感应的光照强度进行显示装置的显示亮度调节。例如，若ALS感应的光照强度较强，输出调节显示亮度增加的信号，以使用户可清楚看到显示装置的显示画面。若ALS感应的光照强度较弱，输出调节显示亮度降低的信号，以使用户可清楚看到显示装置的显示画面的情况下，降低由于显示亮度过高对人眼造成的不良刺激，同时降低显示亮度能够降低电池能耗。
然而，在应用ALS进行显示亮度调节的过程中，ALS根据感应的光照强度进行信息处理，并与显示装置内的处理器进行信息交互，从而，由处理器控制显示装置的显示亮度。这样，ALS和处理器的运行产生较大功耗。智能手表等显示装置往往通过电池供电，由于电池的储能容量有限，采用ALS明显不利于显示装置的续航。示例性地，如图1A～图1C所示，显示装置1000包括至少两个柔性电路板1100和显示面板1200。在柔性电路板1100上设置ALS 1300，并将柔性电路板1100弯折至显示面板1200的非显示侧的情况下，如图1C所示，柔性电路板1100具有一定硬度，容易发生翘曲，导致ALS 1300与显示面板1200之间存在缝隙而无法紧靠，进而显示面板1200上暴露ALS 1300的透光区H与ALS 1300发生错位，透光区H无法完整的暴露ALS 1300，影响ALS 1300的感光效果。可以理解的是，若透光区H位于周边区，在与透光区H正投影重叠的壳体上设置开口；若透光区H位于显示区，透光区H的位于ALS 1300朝向显示侧的各膜层叠层均为透光膜层，以使外界环境光照射到ALS 1300。此外，与ALS 1300共同运作的外围器件(例如两个滤波电容 器，可调电阻等)较多，占用的空间较大，不利于实现显示装置1000的轻薄化。
为了解决上述问题，本申请的一些实施例提供了一种显示装置，该显示装置在无增设ALS的情况下，能够根据当前环境光强度进行自动调光，且减少ALS贴附工艺步骤，提高工艺效率和良率。
上述显示装置可以是平板电脑，显示器，手机，广告牌，数码相框或个人数字助理(Personal Digital Assistant，PDA)等任何具有显示功能的装置。示例的，如图2所示，本申请的一些实施例提供的显示装置2000为智能手表2001。
本申请实施例对显示装置2000的具体类型不做特殊限制。示例性地，显示装置2000也可以为有机电致发光二极管(Organic Light-Emitting Diode，简称OLED)显示装置、量子点电致发光二极管(Quantum Dot Light Emitting Diodes，简称QLED)显示装置或有源矩阵有机发光二极管(Active-matrix organic light emitting diode，简称AMOLED)显示装置。以下实施例以OLED显示装置为例进行详细说明。
在一些实施例中，如图2所示，显示装置2000包括显示模组2200和壳体2100。其中，壳体2100包括边框2101和后壳(图中未示出)等部件，被配置为给显示模组2200提供保护和支撑作用。示例的，如图2所示，显示装置2000为智能手表2001，智能手表2001包括显示模组2200、壳体2100和支撑部件2300，支撑部件2300被配置为与壳体2100连接以便于穿戴显示装置2000，例如，支撑部件2300包括表带2301。
在一些示例中，如图3A和图3B所示，显示模组2200包括主板2210、柔性电路板2220、覆晶薄膜2230和显示面板2240。
主板2210上设有中央处理器(Central Processing Unit，简称CPU)2211，主板2210与柔性电路板2220电连接，被配置为控制时序控制器(Timing Controller，简称TCON)2222输出时序控制信号。
柔性电路板2220与覆晶薄膜2230通过第二引脚S2电连接，柔性电路板2220上设有电源管理器2221和TCON 2222等驱动电路，电源管理器2221被配置为将处理过的电源电压信号传输至TCON 2222、覆晶薄膜2230和处理器2211，以给TCON 2222、覆晶薄膜2230和处理器2211上电。
覆晶薄膜2230(Chip On Film，简称COF)与显示面板2240通过第一引脚S1电连接，覆晶薄膜2230上设置驱动芯片2231。示例的，驱动芯片2231为源极驱动芯片(Source Driver IC)。该源极驱动芯片与显示面板2240上的多个像素驱动电路100电连接，被配置为传输数据信号至像素驱动电路100。其中，TCON 2222与源极驱动芯片电连接，被配置为将时序控制信号传输至源极驱动芯片，以控制源极驱动芯片输出所需的数据信号。
如图3A、图3B和图4所示，显示面板2240包括显示区AA(Active Area)和位于显示区AA的至少一侧的周边区BB。图4中以周边区BB围绕显示区AA一圈进行示意，对 周边区BB和显示区AA的形状并不做限制。其中，显示区AA包括多个阵列排布的子像素单元(sub pixel)P。示例的，沿水平方向X排列成一排的子像素P称为同一行子像素，沿竖直方向Y排列成一排的子像素单元P称为同一列子像素。示例的，如图5所示，同一行子像素单元P可以与至少一根栅线GL连接，以及与一根发光控制信号线EM连接。同一列子像素单元P可以与一根数据线DL连接。
请继续参阅图5，子像素单元P内设置有用于控制子像素单元P进行显示的像素驱动电路100和发光器件200。与子像素单元P连接的栅线GL用于向子像素单元P的像素驱动电路100传输栅扫描信号gate。与子像素单元P连接的发光控制信号线EM用于向子像素单元P的像素驱动电路100传输使能信号em。与子像素单元P连接的复位扫描信号线RS用于向子像素单元P的像素驱动电路100传输复位信号reset(该复位扫描信号线RS为另一条栅线，即第N行的栅线GL传输的栅扫描信号gate作为第N+1行的复位信号reset)。与子像素单元P连接的数据线DL用于向子像素单元P的像素驱动电路100传输数据信号vdata，数据信号Data来自与各条数据线DL电连接的源极驱动芯片。
需要说明的是，后续实施例提到的扫描信号端Gate电连接的信号线为栅线GL，复位信号端Reset电连接的信号线为复位信号线RS，使能信号端EM电连接的信号线为发光控制信号线EM(此处不做区分)。
以下根据显示面板2240的具体膜层结构对像素驱动电路100和发光器件200进行举例说明。如图6A和图6B所示，显示面板2240包括层叠设置的衬底2241、驱动电路叠层2242、多个发光器件200和封装层2243。
衬底2241可以是柔性的，包括聚醚砜(PES)、聚芳酯(PAR)、聚醚酰亚胺(PEI)、聚萘二甲酸乙二醇酯(PEN)、聚对苯二甲酸乙二醇酯(PET)、聚苯硫醚(PPS)、聚酰亚胺(PI)、聚碳酸酯(PC)、三乙酸纤维素(TAC)和乙酸丙酸纤维素(CAP)中的一种或多种。示例的，衬底2241的材料包括聚酰亚胺(PI)。
在一些示例中，如图6A和图6B所示，驱动电路叠层2242是指多个像素驱动电路100阵列设置所在的膜层，包括多个图案化的导电层和绝缘层。像素驱动电路100设置于衬底2241上。每个像素驱动电路100包括多个薄膜晶体管(Thin Film Transistor，简称TFT)和至少一个电容器Cst。垂直于驱动电路叠层2242的方向，驱动电路叠层2242包括半导体层1、栅绝缘层2、第一栅金属层3、第一绝缘层4、第二栅金属层5、第二绝缘层6、导电层7、第三绝缘层8和平坦层9。
其中，第一栅金属层3包括多个TFT的栅极31、多个电容器Cst的第一极板32、多条第一栅扫描线33(即栅线GL)。第二栅金属层5包括多个电容器Cst的第二极板51和多条第二栅扫描线52(即复用为复位信号线RS的一条栅线GL)。导电层7包括多个TFT的源极71和漏极72，以及多条信号线73(例如包括数据信号线DL、第一电压 信号线VDD和第二电压信号线VSS等)。
多个发光器件200设置于多个像素驱动电路100远离衬底2241的一侧，发光器件200与像素驱动电路100电连接。多个发光器件200所在膜层包括多个像素阳极10、像素界定层11、发光功能层12和阴极层13。一个像素阳极10(用于提供空穴)、一个发光功能层12和阴极层13三者在衬底2241上的正投影重叠的部分可构成一个发光器件200。像素阳极10和阴极层13分别向发光功能层12注入空穴和电子，当空穴和电子结合产生的激子(exciton)从激发态跃迁到基态时构成发光。
封装层2243设置在阴极层13远离衬底2241的一侧。封装层2243可以为封装薄膜。对于封装层2243包括的封装薄膜的层数不进行限定。在一些实施例中，封装层2243可以包括一层封装薄膜，也可以包括层叠设置的两层或两层以上封装薄膜。示例的，封装层2243包括依次层叠设置的无机/有机/无机三层材料薄膜。其中，无机材料可以为氮化硅(SiNx)、氮氧化硅(SiON)或氧化硅(SiOx)中的任意一种或多种。
需要说明的是，本公开的实施例提供的像素驱动电路100中所采用的晶体管可以为薄膜晶体管(Thin Film Transistor，简称TFT)、场效应晶体管(Metal Oxide Semiconductor，简称MOS)或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。
像素驱动电路100所采用的各薄膜晶体管的控制极为晶体管的栅极，第一极为薄膜晶体管的源极和漏极中一者，第二极为薄膜晶体管的源极和漏极中另一者。由于薄膜晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的薄膜晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在薄膜晶体管为P型晶体管的情况下，薄膜晶体管的第一极为源极，第二极为漏极；示例性的，在薄膜晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
如图3A和图3B所示，上述覆晶薄膜2230与显示面板2240通过多个第一引脚S1电连接。覆晶薄膜2230上设有多个第一引脚S1，多个第一引脚与驱动芯片2231电连接。显示面板2240的周边区BB设有多条信号线73的延伸段(图中未示出)。这样，多条信号线73与多个像素驱动电路100电连接，多条信号线73的延伸段与多个第一引脚S1电连接，以实现覆晶薄膜2230上的驱动芯片2231与多个像素驱动电路100电连接。并且，如图6A和图6B所示，上述位于周边区BB的封装层2243会暴露多条信号线73的延伸段，即多条信号线73的延伸段上不设置封装层2243，以便于通过在多条信号线73的延伸段上贴合导电胶14，实现多条信号线73的延伸段与覆晶薄膜2230上的多个第一引脚S1电连接。
在一些示例中，如图3A和图3B所示，显示模组2200还包括至少一个光敏器件110，且显示面板2240中至少一个像素驱动电路100包括光敏器件110。
示例的，如图3A所示，在柔性电路板2220的一侧表面设有至少一个光敏器件110，且在柔性电路板2220弯折至衬底2241的背光侧的情况下，光敏器件110相对于柔性电路板2220靠近衬底2241。结合图6A，显示面板2240未设置光敏器件110所在的膜层。例如，在柔性电路板2220上设置一个贴片光敏电阻RG。显示面板2240中至少一个像素驱动电路100与这个贴片光敏电阻RG电连接。
又示例的，如图3B所示，在显示面板2240上设置至少一个光敏器件110。如图6B所示，在显示面板2240上设置光敏器件110所在的膜层(即光敏层17)。该光敏层17设置于多个像素驱动电路100远离衬底2241的一侧，光敏层17包括至少一个光敏器件110(图中未示出)，每个光敏器件110与多个像素驱动电路100电连接。考虑到显示面板2240还可以包括触控层15和圆偏光片16的情况，为提高光敏器件110的光感应灵敏度，将光敏层17设置于圆偏光片16远离衬底2241的一侧。这样，外界环境光透过玻璃盖板18照射在光敏层17上，减小照射在光敏器件110上的光通量损失，提高光敏器件110的感应效率和灵敏度。
在一些示例中，显示模组2200具有透光区域(图中未示出)，透光区域设置有至少一个光敏器件110，透光区域能够将外界环境光透射至光敏器件110。
可以理解的是，在一个像素驱动电路100响应于光敏器件110进行发光器件200亮度调节的情况下，处理器2211可以获取流经光敏器件110的电位并进行信息处理，以对整个显示区AA的发光器件200的亮度进行调节。本公开对处理器2211与具有光敏器件110的像素驱动电路100的信息交互方式不作具体限定。
示例的，透光区域为边框2101上的一个开口(图中未示出)，暴露光敏器件110，以便于光敏器件110进行感光。
或者，透光区域位于显示面板2240的周边区BB，例如，透光区域位于靠近显示装置2000摄像头(图中未示出)的位置，避免光敏器件110对显示区AA的开口率的影响。
又或者，透光区域位于显示面板2240的显示区AA。例如，透光区域为整个显示区AA，这样，光敏层17包括多个光敏器件110，设置每个像素驱动电路100与一个光敏器件110电连接，提高光敏感应效率。
基于此，请参阅图7～图21所示，本公开的一些实施例提供了一种像素驱动电路100。
如图7所示，像素驱动电路100包括光敏器件110和调光子电路120。光敏器件110的第一端被配置为接收控制信号Ctl，光敏器件110的第二端与第一节点N1电连接。其中，控制信号Ctl是由控制端OP输出的各类信号，示例的，如图9A～图21所示，控制信号Ctl可以是复用像素驱动电路100中原本的一些信号，例如em信号、vinit信号、vdd信号、gate信号、reset信号；也可以是复用像素驱动电路100中的一些节点的电压信号，例如第二节点N2的电压信号、第三节点N3的电压信号和第四节点N4的电压信号。该控 制信号Ctl不影响像素驱动电路100的驱动过程，且在像素驱动电路100驱动发光器件200发光的过程中使发光器件200正常发光即可。其中第二节点N2、第三节点N3、第四节点N4为像素驱动电路100中的等效电路节点。
光敏器件110的电阻随照射在光敏器件110上的光照强度的变化而变化，光敏器件110被配置为基于控制信号Ctl，调节第一节点N1的电压。示例性地，如图8A所示，光敏器件110的电阻随照射在光敏器件110上的光照强度的增大而增大，流经光敏器件110的电压和电流减小，即第一节点N1的电位随照射在光敏器件110上的光照强度的增大而减小，以控制调光子电路120的导通状态。或者，如图8B所示，光敏器件110的电阻随照射在光敏器件110上的光照强度的增大而减小，流经光敏器件110的电压和电流增大，即第一节点N1的电位随照射在光敏器件110上的光照强度的增大而增大，以控制调光子电路120的导通状态。该光敏器件110的特性与制作光敏器件110的材料有关，且第一节点N1的极限电位(即光敏器件110的阻值最大和最小情况下，控制信号Ctl传输至第一节点N1的电位)可控制调光子电路120导通，将第一电压端VDD的第一电压信号vdd的至少部分传输至发光器件200，使发光器件200发光。
示例的，该光敏器件110包括光敏电阻RG、光敏二极管和光敏三极管中的一种或多种，根据调节第一节点N1的电压的需求选择设置。如图9A～图21所示，以光敏器件110为光敏电阻RG为例进行说明。
上述第一节点N1与调光子电路120电连接，且调光子电路120连接在第一电压端VDD和发光器件200之间。这样，在第一节点N1的电位的控制下，调光子电路120的导通状态随第一节点N1的电压的变化而变化，以在第一节点N1的电压的控制下，基于来自第一电压端VDD的第一电压信号vdd，调节发光器件200的亮度。
示例的，第一节点N1的电位增大，调光子电路120的导通程度增大，则第一电压信号vdd传输至发光器件200的电压(和电流)增大，发光器件200的亮度增加。
又示例的，第一节点N1的电位减小，调光子电路120的导通程度减小，则第一电压信号vdd传输至发光器件200的电压(和电流)减小，发光器件200的亮度减弱。
这样，像素驱动电路100通过光敏器件110和与其电连接的调光子电路120来实现自动调节发光器件200的亮度，无需与额外增设的调光元件进行信息交互，降低电路结构的复杂度。
上述发光器件200可以为OLED、QLED和LED等具有自发光特性的二极管。本领域技术人员可以根据实际需求选择设置。
如图9A～图21所示，像素驱动电路100还包括驱动晶体管TD。驱动晶体管TD的控制极与第二节点N2电连接，驱动晶体管TD的第一极与第三节点N3电连接，驱动晶体管TD的第二极与第四节点N4电连接。
在一些实施例中，如图9A、图10、图11和图14～图21所示，调光子电路120包括第一晶体管T1，第一晶体管T1连接在第四节点N4与发光器件200之间，且第一晶体管T1的控制极与第一节点N1电连接。
在另一些实施例中，如图9B、图12和图13所示，调光子电路120包括第一晶体管T1，第一晶体管T1连接在第一电压端VDD与第三节点N3之间，且第一晶体管T1的控制极与第一节点N1电连接。
在上述两种实施例中，像素驱动电路100包括串接于第一电压端VDD和发光器件200之间的驱动晶体管TD和调光子电路120。驱动晶体管TD和调光子电路120共同作用以控制发光器件200发光。其中，调光子电路120与驱动晶体管TD的相对位置关系，并不影响第一节点N1的电位对调光子电路120的导通状态的控制，可根据实际情况调整。
在一些实施例中，如图9A～图21所示，像素驱动电路100还包括电容器Cst、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7。电容器Cst的第一极板与第一电压端VDD电连接，电容器Cst的第二极板与第二节点N2电连接。第四晶体管T4的控制极与扫描信号端Gate电连接，第四晶体管T4的第一极与数据信号端电连接，第四晶体管T4的第二极与第三节点N3电连接。第五晶体管T5的控制极与扫描信号端Gate电连接，第五晶体管T5的第一极与第四节点N4电连接，第五晶体管T5的第二极与第二节点N2电连接。第六晶体管T6的控制极与复位信号端Reset电连接，第六晶体管T6的第一极与初始化信号端Vinit电连接，第六晶体管T6的第二极与第二节点电N2连接。第七晶体管T7的控制极与扫描信号端Gate电连接，第七晶体管T7的第一极与初始化信号端Vinit电连接，第七晶体管T7的第二极与发光器件200电连接。
示例性地，以下结合图22所示使能信号端EM、扫描信号端Gate和复位信号端Reset输出信号的时序，对像素驱动电路100的工作过程进行示例性说明。在下面的描述中，像素驱动电路100中的第四晶体管T4、第五晶体管T5和第七晶体管T7为P型晶体管，第一电压端VDD所传输的第一电压信号vdd为高电平信号，第二电压端VSS所传输的第二电压信号vss为低电平信号为例进行说明。本领域技术人员应当了解，在上述像素驱动电路100中，第一电压信号端VDD与第二电压信号端VSS之间的线路导通，则发光器件200发光。其中，光敏器件110仅影响调光子电路120的导通状态，即调光子电路120将第一电压信号vdd传输至发光器件200的电位大小，随照射在光敏器件110上的光照强度的变化而变化。
在一个帧周期内，像素驱动电路100的驱动过程可以包括第一阶段P1、第二阶段P2和第三阶段P3。示例性的，在下面的描述中，“0”表示低电平，“1”表示高电平。
在第一阶段P1，EM＝1，Reset＝0，Gate＝1。
在此情况下，第四晶体管T4、第五晶体管T5和第七晶体管T7均关闭。第六晶体管 T6打开，来自初始化信号端Vinit的初始化信号vinit传输至第二节点N2，对存储电容Cst和驱动晶体管TD的控制极进行初始化。
以及，调光子电路120关闭，第一电压端VDD与第二电压端VSS之间的线路为断路，发光器件200不发光。
在第二阶段P2，EM＝1，Reset＝1，Gate＝0。
在此情况下，第四晶体管T4和第五晶体管T5打开，第六晶体管T6关闭。来自数据信号端Vdata的数据信号vdata写入电容器Cst中，并且，驱动晶体管TD的阈值电压写入电容器Cst中。此时，第二节点N2的电位为vdata+Vth。
第七晶体管T7打开，来自初始化信号端Vinit的初始化信号vinit传输至发光器件200的阳极，对发光器件200进行初始化。
以及，调光子电路120关闭，第一电压端VDD与第二电压端VSS之间的线路为断路，发光器件200不发光。
在第三阶段P3，EM＝0，Reset＝1，Gate＝1。
在此情况下，第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7均关闭，电容器Cst放电，第二节点N2保持低电位(vdata+Vth)，驱动晶体管TD打开。
以及，调光子电路120打开，第一电压端VDD与第二电压端VSS之间的线路为通路，发光器件200发光。其中，第三节点N3的电位为vdd。在驱动晶体管TD打开，即Vdata+Vth-Vdd＞Vth的情况下，第四节点N4的电位为高电位。
可以理解的是，驱动晶体管TD为P型晶体管的情况下，Vth＜0。驱动晶体管TD为N型晶体管的情况下，Vth＞0。
由上面关于像素驱动电路100的描述可知，在一个帧周期内的第三阶段P3，像素驱动电路100控制发光器件200发光，且该像素驱动电路100中的使能信号端EM、扫描信号端Gate、复位信号端Reset、初始化信号端Vinit、第一电压端VDD、第二电压端VSS、第二节点N2、第三节点N3和第四节点N4均有电位信号输出。基于此，设置调光子电路120中的晶体管数量和类型，以实现像素驱动电路100在第一阶段P1实现电容器Cst初始化、第二阶段P2实现数据写入电容器Cst，和第三阶段P3实现发光器件200发光的正常驱动过程。
在以下实施例中，如图9A～图21所示，根据光敏器件110的第一端接收不同的控制信号Ctl(即光敏器件110的第一端与不同的信号端或节点电连接)，对调光子电路120的具体结构进行详细说明。
以调光子电路120包括两个晶体管为例进行说明。如图9A～图13所示，调光子电路120包括第一晶体管T1和第二晶体管T2。
在一些实施例中，第一晶体管T1和第二晶体管T2的连接关系如图9A、图10、图11 所示，第一晶体管T1的控制极与第一节点N1电连接，第一晶体管T1的第一极与第四节点N4电连接，第一晶体管T1的第二极与发光器件200电连接。第二晶体管T2的控制极与第一节点N1或使能信号端EM电连接，第二晶体管T2的第一极与第一电压端VDD电连接，第二晶体管T2的第二极与第三节点N3电连接。
在一些示例中，如图9A和图10所示，光敏器件110的第一端与使能信号端EM电连接，光敏器件110的第一端接收的控制信号Ctl为使能信号em。
示例性地，如图9A所示，在此情况下，调光子电路120中，第一晶体管T1和第二晶体管T2的控制极均与第一节点N1电连接；第二晶体管T2的第一极与第一电压端VDD电连接，第二晶体管T2的第二极与第三节点N3电连接；第一晶体管T1的第一极与第四节点N4电连接，第一晶体管T1的第二极与发光器件200电连接。
这样，使能信号端EM输出的使能信号em经光敏器件110流至第一节点N1，在第一节点N1的电位的控制下，调光子电路120的第一晶体管T1和第二晶体管T2的导通程度均发生变化，从而，控制来自第一电压端VDD的第一电压信号vdd传输至发光器件200的大小，调节发光器件200的亮度。
示例性地，如图10所示，在此情况下，调光子电路120的第一晶体管T1的控制极与第一节点N1电连接，第一晶体管T1的第一极与第四节点N4电连接，第一晶体管T1的第二极与发光器件200电连接。第二晶体管T2的控制极与使能信号端EM电连接，第二晶体管T2的第一极与第一电压端VDD电连接，第二晶体管T2的第二极与第三节点N3电连接。
这样，使能信号端EM输出的使能信号em经光敏器件110流至第一节点N1，在第一节点N1的电位的控制下，调光子电路120的第一晶体管T1的导通程度均发生变化，从而，控制来自第一电压端VDD的第一电压信号vdd传输至发光器件200的大小，即控制第四节点N4的电位传输至发光器件200的大小，以调节发光器件200的亮度。
在另一些示例中，如图11所示，光敏器件110的第一端与扫描信号端Gate电连接，光敏器件110的第一端接收的控制信号Ctl为扫描信号gate，光敏器件110的第二端与第一节点N1电连接。
调光子电路120的第一晶体管T1的控制极与第一节点N1电连接，第一晶体管T1的第一极与第四节点N4电连接，第一晶体管T1的第二极与发光器件200电连接。第二晶体管T2的控制极与使能信号端EM电连接，第二晶体管T2的第一极与第一电压端VDD电连接，第二晶体管T2的第二极与第三节点N3电连接。
这样，扫描信号端Gate输出的扫描信号gate经光敏电阻RG流至第一节点N1。在第一节点N1的电位的控制下，调光子电路120的第一晶体管T1的导通程度发生变化，从而，控制来自第一电压端VDD的第一电压信号vdd传输至发光器件200的大小，即控制第四 节点N4的电位传输至发光器件200的大小，以调节发光器件200的亮度。
在另一些实施例中，调光子电路120包括第一晶体管T1和第二晶体管T2，第一晶体管T1和第二晶体管T2的连接关系如图9B、图12和图13所示，第一晶体管T1的控制极与第一节点N1电连接，第一晶体管T1的第一极与第一电压端VDD电连接，第一晶体管T1的第二极与第三节点N3电连接。第二晶体管T2的控制极与使能信号端EM电连接，第二晶体管T2的第一极与第四节点N4电连接，第二晶体管T2的第二极与发光器件200电连接。
在一些示例中，请继续参阅图9B、图12和图13，光敏器件110的第一端与使能信号端EM或扫描信号端Gate电连接。
示例性地，如图12所示，光敏器件110的第一端与使能信号端EM电连接，光敏器件110的第一端接收的控制信号Ctl为使能信号em，光敏器件110的第二端与第一节点N1电连接。
调光子电路120的第一晶体管T1的控制极与第一节点N1电连接，第一晶体管T1的第一极与第一电压端VDD电连接，第一晶体管T1的第二极与第三节点N3电连接。第二晶体管T2的控制极与使能信号端EM电连接，第二晶体管T2的第一极与第四节点N4电连接，第二晶体管T2的第二极与发光器件200电连接。
这样，使能信号端EM输出的使能信号em经光敏器件110流至第一节点N1，在第一节点N1的电位的控制下，调光子电路120的第一晶体管T1的导通程度发生变化，从而，控制来自第一电压端VDD的第一电压信号vdd传输至第三节点N3的大小，以调节发光器件200的亮度。
示例性地，如图13所示，光敏电阻RG的第一端与扫描信号端Gate电连接，光敏电阻RG的第一端接收的控制信号Ctl为扫描信号gate，光敏电阻RG的第二端与第一节点N1电连接。
调光子电路120的第一晶体管T1的控制极与第一节点N1电连接，第一晶体管T1的第一极与第一电压端VDD电连接，第一晶体管T1的第二极与第三节点N3电连接。第二晶体管T2的控制极与使能信号端EM电连接，第二晶体管T2的第一极与第四节点N4电连接，第二晶体管T2的第二极与发光器件200电连接。
这样，扫描信号端Gate输出的扫描信号gate经光敏电阻RG流至第一节点N1，在第一节点N1的电位的控制下，调光子电路120的第一晶体管T1的导通程度发生变化，从而，控制来自第一电压端VDD的第一电压信号vdd传输至第三节点N3的大小，以通过调节第三节点N3的电位大小来调节发光器件200的亮度。
以调光子电路120包括三个晶体管为例进行说明。如图14～图21所示，调光子电路120包括第一晶体管T1、第二晶体管T2和第三晶体管T3。
在一些实施例中，第一晶体管T1、第二晶体管T2和第三晶体管T3的连接关系如图14～图21所示，第二晶体管T2的控制极与使能信号端EM电连接，第二晶体管T2的第一极与第一电压端VDD电连接，第二晶体管T2的第二极与第三节点N3电连接。第三晶体管T3与第一晶体管T1串联在第四节点N4和发光器件200之间，第三晶体管T3的控制极与使能信号端EM电连接。
示例的，如图14～图21所示，第三晶体管T3的控制极与使能信号端EM电连接，第三晶体管T3的第一极与第四节点N4电连接，第三晶体管T3的第二极与第一晶体管T1的第一极电连接。第一晶体管T1的控制极与第一节点N1电连接，第一晶体管T1的第二极与发光器件200电连接。其中，发光器件200与第二电压端VSS电连接。
考虑第二晶体管T2和第三晶体管T3的连接关系实现像素驱动电路100的正常驱动过程，这样，与第一晶体管T1的控制极电连接的光敏电阻RG，其第一端可以与使能信号端EM、扫描信号端Gate、复位信号端Reset、初始化信号端Vinit、第一电压端VDD、第二电压端VSS、第二节点N2、第三节点N3或第四节点N4中的任一者电连接。
在一些示例中，如图14所示，光敏电阻RG的第一端与扫描信号端Gate电连接，光敏电阻RG的第一端接收的控制信号Ctl为扫描信号gate。如图22所示，扫描信号端Gate输出的扫描信号gate在发光阶段P3输出高电平信号。
这样，扫描信号端Gate输出的扫描信号gate经光敏电阻RG流至第一节点N1，在第一节点N1的电位的控制下，调光子电路120的第一晶体管T1的导通程度发生变化，从而，控制来自第一电压端VDD的第一电压信号vdd传输至发光器件200的大小，即控制来自第三晶体管T3的第二极的电位传输至发光器件200的大小，以调节发光器件200的亮度。
在一些示例中，如图15所示，光敏电阻RG的第一端与复位信号端Reset电连接，光敏电阻RG的第一端接收的控制信号Ctl为复位信号reset。如图22所示，复位信号端Reset输出的复位信号reset在发光阶段P3输出低电平信号。
这样，复位信号端Reset输出的复位信号reset经光敏电阻RG流至第一节点N1，在第一节点N1的电位的控制下，调光子电路120的第一晶体管T1的导通程度发生变化，从而，控制来自第一电压端VDD的第一电压信号vdd传输至发光器件200的大小，即控制来自第三晶体管T3的第二极的电位传输至发光器件200的大小，以调节发光器件200的亮度。
在一些示例中，如图16所示，光敏电阻RG的第一端与初始化信号端Vinit，光敏电阻RG的第一端接收的控制信号Ctl为初始信号vinit。初始信号vinit为恒定的低电平信号。
这样，初始化信号端Vinit输出的初始信号vinit经光敏电阻RG流至第一节点N1，在第一节点N1的电位的控制下，调光子电路120的第一晶体管T1的导通程度发生变化，从而，控制来自第一电压端VDD的第一电压信号vdd传输至发光器件200的大小，即控制来自第三晶体管T3的第二极的电位传输至发光器件200的大小，以调节发光器件200的 亮度。
在一些示例中，如图17所示，光敏电阻RG的第一端与第一电压端VDD电连接，光敏电阻RG的第一端接收的控制信号Ctl为第一电压信号vdd。第一电压信号vdd为恒定的高电平信号。
这样，第一电压端VDD输出的第一电压信号vdd经光敏电阻RG流至第一节点N1，在第一节点N1的电位的控制下，调光子电路120的第一晶体管T1的导通程度发生变化，从而，控制来自第一电压端VDD的第一电压信号vdd传输至发光器件200的大小，即控制来自第三晶体管T3的第二极的电位传输至发光器件200的大小，以调节发光器件200的亮度。
在一些示例中，如图18所示，光敏电阻RG的第一端与第二电压端VSS电连接，光敏电阻RG的第一端接收的控制信号Ctl为第二电压信号vss。第二电压信号vss为恒定的低电平信号。
这样，第二电压端VSS输出的第二电压信号vss经光敏电阻RG流至第一节点N1，在第一节点N1的电位的控制下，调光子电路120的第一晶体管T1的导通程度发生变化，从而，控制来自第一电压端VDD的第一电压信号vdd传输至发光器件200的大小，即控制来自第三晶体管T3的第二极的电位传输至发光器件200的大小，以调节发光器件200的亮度。
在一些示例中，如图19所示，光敏电阻RG的第一端与第二节点N2电连接，光敏电阻RG的第一端接收的控制信号Ctl为第二节点N2的电位，即vdata+Vth。第二节点N2为低电平信号。
这样，第二节点N2的电位经光敏电阻RG流至第一节点N1，在第一节点N1的电位的控制下，调光子电路120的第一晶体管T1的导通程度发生变化，从而，控制来自第一电压端VDD的第一电压信号vdd传输至发光器件200的大小，即控制来自第三晶体管T3的第二极的电位传输至发光器件200的大小，以调节发光器件200的亮度。
在一些示例中，如图20所示，光敏电阻RG的第一端与第三节点N3电连接，光敏电阻RG的第一端接收的控制信号Ctl为第三节点N3的电位，即在第三阶段P3，第一电压端VDD传输至第三节点N3的第一电压信号vdd。第三节点N3的电位为高电平信号。
这样，第三节点N3的电位经光敏电阻RG流至第一节点N1，在第一节点N1的电位的控制下，调光子电路120的第一晶体管T1的导通程度发生变化，从而，控制来自第一电压端VDD的第一电压信号vdd传输至发光器件200的大小，即控制来自第三晶体管T3的第二极的电位传输至发光器件200的大小，以调节发光器件200的亮度。
在一些示例中，如图21所示，光敏电阻RG的第一端与第四节点N4电连接，光敏电阻RG的第一端接收的控制信号Ctl为第四节点N4的电位，即在第三阶段P3，第四节点 N4的电位为高电平信号。
这样，第四节点N4的电位经光敏电阻RG流至第一节点N1，在第一节点N1的电位的控制下，调光子电路120的第一晶体管T1的导通程度发生变化，从而，控制来自第一电压端VDD的第一电压信号vdd传输至发光器件200的大小，即控制来自第三晶体管T3的第二极的电位传输至发光器件200的大小，以调节发光器件200的亮度。
由上述实施例中光敏电阻RG的第一端连接的不同的信号端或节点，来设置第一晶体管T1的类型可知，在一些示例中，如图11、图13、图14、图17、图20和图21所示，在光敏电阻RG的第一端与第一电压端VDD、扫描信号端Gate、第三节点N3和第四节点N4中的任一者电连接的情况下，第一晶体管T1的极性，与驱动晶体管TD、第二晶体管T2、及第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7的极性相反。其中，在调光子电路120还包括第三晶体管T3的情况下，第一晶体管T1的极性还与第三晶体管T3的极性相反。
示例的，如图11和图13所示，在调光子电路120包括第一晶体管T1和第二晶体管T2的情况下，驱动晶体管TD、第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7均为P型晶体管，则第一晶体管T1为N型晶体管。以及，如图14、图17、图20和图21所示，在调光子电路120还包括第三晶体管T3的情况下，驱动晶体管TD、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7均为P型晶体管，则第一晶体管T1为N型晶体管。
在另一些示例中，如图9A、图9B、图10、图12、图15、图16、图18和图19所示，光敏器件110的第一端与使能信号端EM、复位信号端Reset、初始化信号端Vinit、第二电压端VSS和第二节点N2中的任一者电连接的情况下，第一晶体管T1的极性，与驱动晶体管TD、第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7的极性相同；在调光子电路120还包括第三晶体管T3的情况下，第一晶体管T1的极性还与第三晶体管T3的极性相同。
示例的，如图9A、图9B、图10、图12所示，在调光子电路120包括第一晶体管T1和第二晶体管T2的情况下，驱动晶体管TD、第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7均为P型晶体管，则第一晶体管T1为P型晶体管。以及，如图15、图16、图18和图19所示，在调光子电路120还包括第三晶体管T3的情况下，驱动晶体管TD、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7均为P型晶体管，则第一晶体管T1为P型晶体管。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此， 任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种像素驱动电路，包括：
    光敏器件，所述光敏器件的第一端被配置为接收控制信号，所述光敏器件的第二端与第一节点电连接；所述光敏器件的电阻随照射在所述光敏器件上的光照强度的变化而变化，所述光敏器件被配置为基于所述控制信号，调节所述第一节点的电压；
    调光子电路，连接在第一电压端和发光器件之间，且与所述第一节点电连接；所述调光子电路的导通状态随所述第一节点的电压的变化而变化，所述调光子电路被配置为在所述第一节点的电压的控制下，基于来自所述第一电压端的第一电压信号，调节所述发光器件的亮度。
  2. 根据权利要求1所述的像素驱动电路，还包括：
    驱动晶体管，所述驱动晶体管的控制极与第二节点电连接，所述驱动晶体管的第一极与第三节点电连接，所述驱动晶体管的第二极与第四节点电连接；
    所述调光子电路包括第一晶体管，连接在所述第四节点与所述发光器件之间，且所述第一晶体管的控制极与所述第一节点电连接。
  3. 根据权利要求2所述的像素驱动电路，其中，所述光敏器件的第一端与使能信号端电连接；
    所述调光子电路还包括第二晶体管，所述第二晶体管的控制极与所述第一节点或所述使能信号端电连接，所述第二晶体管的第一极与所述第一电压端电连接，所述第二晶体管的第二极与所述第三节点电连接。
  4. 根据权利要求2所述的像素驱动电路，其中，所述光敏器件的第一端与扫描信号端电连接；
    所述调光子电路还包括第二晶体管，所述第二晶体管的控制极与使能信号端电连接，所述第二晶体管的第一极与所述第一电压端电连接，所述第二晶体管的第二极与所述第三节点电连接。
  5. 根据权利要求2所述的像素驱动电路，其中，所述光敏器件的第一端与使能信号端、扫描信号端、复位信号端、初始化信号端、所述第一电压端、第二电压端、所述第二节点、所述第三节点或所述第四节点中的任一者电连接；其中，所述发光器件与所述第二电压端电连接；
    所述调光子电路还包括第二晶体管和第三晶体管；
    所述第二晶体管的控制极与使能信号端电连接，所述第二晶体管的第一极与所述第一电压端电连接，所述第二晶体管的第二极与所述第三节点电连接；
    所述第三晶体管的控制极与所述使能信号端电连接，所述第三晶体管连接在所述第四节点和所述发光器件之间，且所述第三晶体管与所述第一晶体管串联。
  6. 根据权利要求1所述的像素驱动电路，还包括：
    驱动晶体管，所述驱动晶体管的控制极与第二节点电连接，所述驱动晶体管的第一极与第三节点电连接，所述驱动晶体管的第二极与第四节点电连接；
    所述调光子电路包括第一晶体管，所述第一晶体管的控制极与所述第一节点电连接，所述第一晶体管的第一极与所述第一电压端电连接，所述第一晶体管的第二极与所述第三节点电连接。
  7. 根据权利要求6所述的像素驱动电路，其中，所述光敏器件的第一端与使能信号端或扫描信号端电连接；
    所述调光子电路还包括第二晶体管，所述第二晶体管的控制极与所述使能信号端电连接，所述第二晶体管的第一极与所述第四节点电连接，所述第二晶体管的第二极与所述发光器件电连接。
  8. 根据权利要求3、4、5和7中任一项所述的像素驱动电路，还包括：
    电容器，所述电容器的第一极板与所述第一电压端电连接，所述电容器的第二极板与所述第二节点电连接；
    第四晶体管，所述第四晶体管的控制极与扫描信号端电连接，所述第四晶体管的第一极与数据信号端电连接，所述第四晶体管的第二极与所述第三节点电连接；
    第五晶体管，所述第五晶体管的控制极与所述扫描信号端电连接，所述第五晶体管的第一极与所述第四节点电连接，所述第五晶体管的第二极与所述第二节点电连接；
    第六晶体管，所述第六晶体管的控制极与复位信号端电连接，所述第六晶体管的第一极与初始化信号端电连接，所述第六晶体管的第二极与所述第二节点电连接；
    第七晶体管，所述第七晶体管的控制极与所述扫描信号端电连接，所述第七晶体管的第一极与所述初始化信号端电连接，所述第七晶体管的第二极与所述发光器件电连接。
  9. 根据权利要求8所述的像素驱动电路，其中，
    在所述光敏器件的第一端与所述第一电压端、所述扫描信号端、所述第三节点和所述第四节点中的任一者电连接的情况下，所述第一晶体管的极性，与所述驱动晶体管、所述第二晶体管、及所述第四晶体管～所述七晶体管的极性相反；在所述调光子电路还包括第三晶体管的情况下，所述第一晶体管的极性还与所述第三晶体管的极性相反；
    所述光敏器件的第一端与所述使能信号端、所述复位信号端、所述初始化信号端、第二电压端和所述第二节点中的任一者电连接的情况下，所述第一晶体管的极性，与所述驱动晶体管、所述第二晶体管、所述第四晶体管～所述七晶体管的极性相同；在所述调光子电路还包括第三晶体管的情况下，所述第一晶体管的极性还与所述第三晶体管的极性相同。
  10. 一种显示模组，包括：
    衬底；
    多个如权利要求1～9中任一项所述的像素驱动电路，设置于所述衬底上；
    多个发光器件，设置于多个所述像素驱动电路远离所述衬底的一侧，所述发光器件与所述像素驱动电路电连接。
  11. 根据权利要求10所述的显示模组，其中，所述显示模组具有透光区域，所述透光区域设置有至少一个所述光敏器件，每个所述光敏器件与多个所述像素驱动电路电连接。
  12. 根据权利要求10所述的显示模组，还包括：
    光敏层，设置于所述多个像素驱动电路远离所述衬底的一侧，所述光敏层包括多个所述光敏器件，每个所述光敏器件与一个或多个所述像素驱动电路电连接。
  13. 根据权利要求10所述的显示模组，还包括：
    覆晶薄膜，与多个所述像素驱动电路电连接；
    柔性电路板，与所述覆晶薄膜电连接；所述柔性电路板的一侧表面设有至少一个所述光敏器件，且在所述柔性电路板弯折至所述衬底的背光侧的情况下，所述光敏器件相对于所述柔性电路板靠近所述衬底；
    其中，每个所述光敏器件与多个所述像素驱动电路电连接。
  14. 一种显示装置，包括如权利要求10～13中任一项所述的显示模组，以及壳体。
  15. 一种智能手表，包括如权利要求10～13中任一项所述的显示模组，以及支撑部件。
PCT/CN2023/089030 2022-04-22 2023-04-18 像素驱动电路、显示模组及显示装置、智能手表 WO2023202586A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210427079.0A CN114783345A (zh) 2022-04-22 2022-04-22 像素驱动电路、显示模组及显示装置、智能手表
CN202210427079.0 2022-04-22

Publications (2)

Publication Number Publication Date
WO2023202586A1 true WO2023202586A1 (zh) 2023-10-26
WO2023202586A9 WO2023202586A9 (zh) 2023-12-14

Family

ID=82431834

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/089030 WO2023202586A1 (zh) 2022-04-22 2023-04-18 像素驱动电路、显示模组及显示装置、智能手表

Country Status (2)

Country Link
CN (1) CN114783345A (zh)
WO (1) WO2023202586A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114783345A (zh) * 2022-04-22 2022-07-22 京东方科技集团股份有限公司 像素驱动电路、显示模组及显示装置、智能手表

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1609938A (zh) * 2004-11-25 2005-04-27 友达光电股份有限公司 自动调整自发光亮度的电路与方法
US20060250330A1 (en) * 2003-04-04 2006-11-09 Koninklijke Philips Electronics N. V. Electroluminescent display devices
US20110248973A1 (en) * 2010-04-09 2011-10-13 Delphi Technologies, Inc. Brightness control drive circuit for a current-driven display device
CN103956142A (zh) * 2014-05-15 2014-07-30 深圳市华星光电技术有限公司 面板驱动电路及面板驱动方法
JP2016109912A (ja) * 2014-12-08 2016-06-20 三星ディスプレイ株式會社Ｓａｍｓｕｎｇ Ｄｉｓｐｌａｙ Ｃｏ．，Ｌｔｄ． 表示装置、表示方法、及びプログラム
CN106875892A (zh) * 2017-02-28 2017-06-20 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN106935190A (zh) * 2017-02-22 2017-07-07 上海天马有机发光显示技术有限公司 一种有机发光显示面板、有机发光显示装置、有机发光显示面板的驱动方法
CN108154844A (zh) * 2018-03-09 2018-06-12 京东方科技集团股份有限公司 一种像素电路、其驱动方法及显示面板
CN109891487A (zh) * 2019-01-29 2019-06-14 京东方科技集团股份有限公司 显示基板、显示面板、显示基板的制备方法及驱动方法
CN110189692A (zh) * 2019-05-31 2019-08-30 京东方科技集团股份有限公司 像素电路、像素驱动方法、显示面板和显示装置
CN111696484A (zh) * 2020-07-10 2020-09-22 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、阵列基板及显示装置
CN112951153A (zh) * 2021-02-26 2021-06-11 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板和显示装置
CN114783345A (zh) * 2022-04-22 2022-07-22 京东方科技集团股份有限公司 像素驱动电路、显示模组及显示装置、智能手表

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060250330A1 (en) * 2003-04-04 2006-11-09 Koninklijke Philips Electronics N. V. Electroluminescent display devices
CN1609938A (zh) * 2004-11-25 2005-04-27 友达光电股份有限公司 自动调整自发光亮度的电路与方法
US20110248973A1 (en) * 2010-04-09 2011-10-13 Delphi Technologies, Inc. Brightness control drive circuit for a current-driven display device
CN103956142A (zh) * 2014-05-15 2014-07-30 深圳市华星光电技术有限公司 面板驱动电路及面板驱动方法
JP2016109912A (ja) * 2014-12-08 2016-06-20 三星ディスプレイ株式會社Ｓａｍｓｕｎｇ Ｄｉｓｐｌａｙ Ｃｏ．，Ｌｔｄ． 表示装置、表示方法、及びプログラム
CN106935190A (zh) * 2017-02-22 2017-07-07 上海天马有机发光显示技术有限公司 一种有机发光显示面板、有机发光显示装置、有机发光显示面板的驱动方法
CN106875892A (zh) * 2017-02-28 2017-06-20 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN108154844A (zh) * 2018-03-09 2018-06-12 京东方科技集团股份有限公司 一种像素电路、其驱动方法及显示面板
CN109891487A (zh) * 2019-01-29 2019-06-14 京东方科技集团股份有限公司 显示基板、显示面板、显示基板的制备方法及驱动方法
CN110189692A (zh) * 2019-05-31 2019-08-30 京东方科技集团股份有限公司 像素电路、像素驱动方法、显示面板和显示装置
CN111696484A (zh) * 2020-07-10 2020-09-22 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、阵列基板及显示装置
CN112951153A (zh) * 2021-02-26 2021-06-11 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板和显示装置
CN114783345A (zh) * 2022-04-22 2022-07-22 京东方科技集团股份有限公司 像素驱动电路、显示模组及显示装置、智能手表

Also Published As

Publication number Publication date
CN114783345A (zh) 2022-07-22
WO2023202586A9 (zh) 2023-12-14

Similar Documents

Publication Publication Date Title
US11968865B2 (en) Display substrate and display device
CN112117320B (zh) 一种显示面板和显示装置
JP5288656B2 (ja) 発光装置及びその駆動方法
WO2019214286A1 (zh) 像素电路和电致发光显示面板、其驱动方法及显示装置
WO2021213062A1 (zh) 显示基板和显示装置
KR102642869B1 (ko) 표시 장치
WO2021102791A1 (zh) 显示基板和显示装置
WO2020186396A1 (zh) 像素阵列基板及其驱动方法、显示面板、显示装置
US11374067B2 (en) Display device
US11985874B2 (en) Display substrate and display device
US11963400B2 (en) Display panel and display device
WO2022222453A1 (zh) 像素驱动电路、驱动背板及其制备方法、显示装置
EP4040430A1 (en) Display substrate and display apparatus
TW202133137A (zh) 顯示裝置及其驅動方法
WO2023202586A1 (zh) 像素驱动电路、显示模组及显示装置、智能手表
CN113035134A (zh) 显示面板和显示装置
US11682348B2 (en) Display panel, display device and display method
JP2006091860A (ja) 表示装置及びその駆動方法並びに電子機器
CN115000092A (zh) 显示基板及其制备方法、显示装置
US20220208923A1 (en) Display device and method of providing the same
US11605684B2 (en) Array substrate, control method thereof, manufacturing method thereof, display panel and display device
TWI829365B (zh) 顯示裝置、電源供應裝置以及像素
KR20210030542A (ko) 표시 장치
KR20220135278A (ko) 표시 장치
US11367768B2 (en) Display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23791241

Country of ref document: EP

Kind code of ref document: A1