WO2019214286A1 - 像素电路和电致发光显示面板、其驱动方法及显示装置 - Google Patents

像素电路和电致发光显示面板、其驱动方法及显示装置 Download PDF

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WO2019214286A1
WO2019214286A1 PCT/CN2019/071599 CN2019071599W WO2019214286A1 WO 2019214286 A1 WO2019214286 A1 WO 2019214286A1 CN 2019071599 W CN2019071599 W CN 2019071599W WO 2019214286 A1 WO2019214286 A1 WO 2019214286A1
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Prior art keywords
thin film
film transistor
circuit
node
photosensitive
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PCT/CN2019/071599
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English (en)
French (fr)
Inventor
杨盛际
董学
陈小川
王辉
卢鹏程
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京东方科技集团股份有限公司
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Priority to US16/487,376 priority Critical patent/US11227544B2/en
Publication of WO2019214286A1 publication Critical patent/WO2019214286A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
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    • G09G2300/00—Aspects of the constitution of display devices
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    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
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    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/066—Adjustment of display parameters for control of contrast
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/14—Detecting light within display terminals, e.g. using a single or a plurality of photosensors
    • G09G2360/144—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light being ambient light
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/14—Detecting light within display terminals, e.g. using a single or a plurality of photosensors
    • G09G2360/145—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light originating from the display screen

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel circuit and an electroluminescence display panel, a driving method thereof, and a display device.
  • AMOLED Active Matrix OLED
  • pixel circuits which is an active display type with high luminous efficiency, high contrast, wide viewing angle, etc., and is usually used for high-definition large-size display.
  • the commonly used AMOLED pixel circuit is a current-type driving circuit. When a current passes through the organic light-emitting diode, the organic light-emitting diode emits light, and the gray-scale brightness of the pixel can realize the change of the brightness by controlling the current flowing through the organic light-emitting diode itself.
  • Embodiments of the present disclosure provide a pixel circuit, including: a photosensitive circuit and a driving circuit for driving pixel illumination, the photosensitive circuit comprising: an initialization circuit, a photosensitive driving circuit, a photosensitive output circuit, and a photosensitive device;
  • the initialization circuit is configured to transmit, by the second control signal end, an initialization signal provided by the initialization signal end to the third node;
  • the photosensitive device is configured to control a potential of the third node according to the received illumination intensity
  • the photosensitive driving circuit is configured to output a corresponding electrical signal under the potential control of the third node
  • the photosensitive output circuit is configured to transmit an electrical signal output by the photosensitive driving circuit to the read signal end under the control of the first gate signal terminal.
  • an input end of the initialization circuit is connected to the initialization signal end, a control end is connected to the second control signal end, and an output end is The third node is connected;
  • One end of the photosensitive device is connected to the third node, and the other end is grounded;
  • An input end of the photosensitive driving circuit is connected to the first reference signal end, a control end is connected to the third node, and an output end is connected to an input end of the photosensitive output circuit;
  • the control end of the photosensitive output circuit is connected to the first gate signal end, and the output end is connected to the read signal end.
  • the driving circuit includes: a data writing circuit, a light emitting driving circuit, and a light emitting device;
  • An input end of the data writing circuit is connected to the data signal end, a control end is connected to the first gate signal end, and an output end is connected to the first node;
  • the data writing circuit is used in the first gate Transmitting, by the signal terminal, the data signal provided by the data signal end to the first node;
  • the input end of the illumination driving circuit is connected to the first reference signal end, the first control end is connected to the first node, the second control end is connected to the first control signal end, and the output end is connected to the second node;
  • the light emitting device is connected between the second node and the second reference signal end; the light emitting driving circuit is configured to drive the light emitting under the control of the potential of the first node and the first control signal end The device emits light.
  • the data writing circuit includes: a first thin film transistor
  • the gate of the first thin film transistor is connected to the first gate signal terminal, the source is connected to the data signal end, and the drain is connected to the first node.
  • the data writing circuit further includes: a second thin film transistor
  • a gate of the second thin film transistor is connected to the second gate signal terminal, a source is connected to the data signal end, and a drain is connected to the first node;
  • the first thin film transistor is an N-type transistor, and the second thin film transistor is a P-type transistor; or the second thin film transistor is an N-type transistor, and the first thin film transistor is a P-type transistor;
  • the second gate signal terminal and the first gate signal terminal provide opposite electrical signals.
  • the photosensitive output circuit includes: a third thin film transistor
  • a gate of the third thin film transistor is connected to the signal terminal of the first gate, a source is connected to an output end of the photosensitive driving circuit, and a drain is connected to the read signal end;
  • the first thin film transistor is an N-type transistor, and the third thin film transistor is an N-type transistor; or the first thin film transistor is a P-type transistor, and the third thin film transistor is a P-type transistor.
  • the light emitting driving circuit includes: a fourth thin film transistor, a first driving transistor, and a first capacitor; wherein
  • a gate of the fourth thin film transistor is connected to the first control signal end, a source is connected to the first reference signal end, and a drain is connected to a source of the first driving transistor;
  • a gate of the first driving transistor is connected to the first node, and a drain is connected to the second node;
  • the first capacitor is connected to the first node.
  • the initialization circuit includes: a fifth thin film transistor
  • the gate of the fifth thin film transistor is connected to the initialization signal end, the source is connected to the second control signal end, and the drain is connected to the third node.
  • the first control signal end and the second control signal end are the same signal end;
  • the fourth thin film transistor is an N-type transistor, and the fifth thin film transistor is a P-type transistor; or the fifth thin film transistor is an N-type transistor, and the fourth thin film transistor is a P-type transistor.
  • the method further includes: a sixth thin film transistor of the same type as the fifth thin film transistor;
  • the gate of the sixth thin film transistor is connected to the second control signal end, the source is connected to the common signal end, and the drain is connected to the second node.
  • the photosensitive driving circuit includes: a second driving transistor and a second capacitor; wherein
  • a gate of the second driving transistor is connected to the third node, a source is connected to the first reference signal end, and a drain is connected to an input end of the photosensitive output circuit;
  • the second capacitor is connected to the third node.
  • an embodiment of the present disclosure further provides a driving method of a pixel circuit, including:
  • the initialization circuit transmits the initialization signal provided by the initialization signal terminal to the third node under the control of the second control signal end;
  • the photosensitive device controls the potential of the third node according to the received illumination intensity, and the photosensitive driving circuit outputs a corresponding electrical signal under the potential control of the third node, and the photosensitive output circuit is in the The electrical signal output by the photosensitive driving circuit is transmitted to the read signal terminal under the control of a gate signal terminal.
  • the method further includes:
  • the data writing circuit transmits the data signal provided by the data signal end to the first node under the control of the first gate signal end;
  • the illumination driving circuit drives the light emitting device to emit light under the control of the potential of the first node and the first control signal end;
  • the first time period, the second time period, and the third time period are time periods that are sequentially connected.
  • the method further includes: in the first time period, the sixth thin film transistor controls a common potential of the common signal terminal under the control of the second control signal end The signal is provided to the second node.
  • an embodiment of the present disclosure further provides an electroluminescent display panel including a plurality of illuminating pixels, wherein at least a portion of the illuminating pixels include the pixel circuit.
  • the substrate of the electroluminescent display panel is a silicon wafer.
  • an embodiment of the present disclosure further provides a driving method of an electroluminescent display panel, including:
  • embodiments of the present disclosure also provide a display device including the electroluminescent display panel.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2a is a schematic diagram of a specific structure of a pixel circuit according to an embodiment of the present disclosure
  • Figure 2b is a timing diagram of the input and output signals corresponding to Figure 2a;
  • FIG. 3 is a schematic diagram of another specific structure of a pixel circuit according to an embodiment of the present disclosure.
  • Figure 3b is a timing diagram of the input and output signals corresponding to Figure 3a;
  • 4a is another schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • Figure 4b is a timing diagram of the input and output signals corresponding to Figure 4a;
  • 5a and 5b are schematic structural views of an electroluminescent display panel according to an embodiment of the present disclosure.
  • a pixel circuit includes: a photosensitive circuit and a driving circuit for driving pixel illumination, the photosensitive circuit comprising: an initialization circuit 4, a photosensitive driving circuit 5, and a photosensitive output circuit 6 And photosensitive device 7; wherein
  • the initialization circuit 4 is used to transmit the initialization signal provided by the initialization signal terminal Vint to the third node A under the control of the second control signal terminal EM2;
  • the photosensitive device 7 is configured to control the potential of the third node C according to the received light intensity
  • the photosensitive driving circuit 5 is configured to output a corresponding electrical signal under the potential control of the third node C;
  • the photosensitive output circuit 6 is for transmitting the electrical signal output from the photosensitive drive circuit 5 to the read signal terminal R under the control of the first gate signal terminal G1.
  • the initialization circuit 4 the photosensitive driving circuit 5, the photosensitive output circuit 6, and the photosensitive device 7 are added, and under the control of the second control signal terminal EM2, the initialization circuit 4 The initialization signal provided by the initialization signal terminal Vint is transmitted to the third node A.
  • the photosensitive driving circuit 5 Under the potential control of the third node C, the photosensitive driving circuit 5 outputs a corresponding electrical signal, and under the control of the first gate signal terminal G1, the photosensitive output circuit 6 The electrical signal outputted by the photosensitive driving circuit 5 is transmitted to the reading signal terminal R, and the external environment brightness detection in the pixel circuit can be completed while controlling the pixel circuit to emit light, thereby realizing the optical detection function in the on-screen, and facilitating the display screen.
  • the display mode is adjusted according to the detected brightness of the external environment.
  • the optical detection function inside the pixel circuit does not occupy the panel area, which is advantageous for the narrow bezel or the full screen design; and, without separately providing the external detector device, the cost can be saved.
  • the input end of the initialization circuit 4 is connected to the initialization signal terminal Vint, the control terminal is connected to the second control signal terminal EM2, and the output terminal and the third terminal are connected. Node C is connected;
  • One end of the photosensitive device 7 is connected to the third node C, and the other end is grounded;
  • the input end of the photosensitive driving circuit 5 is connected to the first reference signal terminal VDD, the control terminal is connected to the third node C, and the output end is connected to the input end of the photosensitive output circuit 6;
  • the control terminal of the photosensitive output circuit 6 is connected to the first gate signal terminal G1, and the output terminal is connected to the read signal terminal R.
  • the driving circuit includes: a data writing circuit 1, a light emitting driving circuit 2, and a light emitting device 3;
  • the input end of the data writing circuit 1 is connected to the data signal terminal D, the control terminal is connected to the first gate signal terminal G1, the output terminal is connected to the first node A, and the data writing circuit 1 is used at the first gate signal terminal. Under the control of G1, the data signal provided by the data signal terminal D is transmitted to the first node A;
  • the input end of the illumination driving circuit 2 is connected to the first reference signal terminal VDD, the first control end is connected to the first node A, the second control end is connected to the first control signal end EM1, and the output end is connected to the second node B;
  • the device 3 is connected between the second node B and the second reference signal terminal VSS; the light-emitting driving circuit 2 is configured to drive the light-emitting device 3 to emit light under the control of the potential of the first node A and the first control signal terminal EM1.
  • the data writing circuit 1 may include: a first thin film transistor T1;
  • the gate of the first thin film transistor T1 is connected to the first gate signal terminal G1, the source is connected to the data signal terminal D, and the drain is connected to the first node A.
  • the first thin film transistor T1 when the first thin film transistor T1 is in an on state under the control of the first gate signal terminal G1, the data signal of the data signal terminal D is supplied to the first node A. .
  • the first thin film transistor T1 may be a P-type transistor.
  • the first gate signal terminal G1 When the first gate signal terminal G1 is loaded with a low-level effective pulse signal, the first thin film transistor T1 is in an on state.
  • the first thin film transistor T1 may also be an N-type transistor, which is not limited herein.
  • the first gate signal terminal G1 When the first gate signal terminal G1 is loaded with a high-level effective pulse signal, the first thin film transistor T1 is used. It is in the on state.
  • the data writing circuit 1 may further include: a second thin film transistor T2;
  • the gate of the second thin film transistor T2 is connected to the second gate signal terminal G2, the source is connected to the data signal terminal D, and the drain is connected to the first node A;
  • the first thin film transistor T1 is an N-type transistor, and the second thin film transistor T2 is a P-type transistor; or the second thin film transistor T2 is an N-type transistor, and the first thin film transistor T1 is a P-type transistor;
  • the second gate signal terminal G2 and the first gate signal terminal G1 provide opposite electrical signals.
  • the second thin film transistor T2 when the second thin film transistor T2 is in an on state under the control of the second gate signal terminal G2, the data signal of the data signal terminal D is supplied to the first node A. .
  • the second thin film transistor T2 may be a P-type transistor.
  • the second gate signal terminal G2 When the second gate signal terminal G2 is loaded with a low-level effective pulse signal, the second thin film transistor T2 is in an on state.
  • the second thin film transistor T2 may also be an N-type transistor, which is not limited herein.
  • the second gate signal terminal G2 is loaded with a high-level effective pulse signal, the second thin film transistor T2 is used. It is in the on state.
  • the first thin film transistor T1 and the second thin film transistor T2 are used in the data writing circuit 1 to form a CMOS (Complementary Metal-Oxide Semiconductor).
  • CMOS is composed of PMOS and NMOS transistors. Since NMOS and PMOS are complementary, they are called complementary MOS, ie CMOS. Since the gate circuit composed of a pair of MOSs in CMOS is turned on at the moment or the PMOS is turned on, or the NMOS is turned on or is turned off, it is much more efficient than the transistor, and thus the power consumption is low. Therefore, the data writing circuit 1 adopts a CMOS structure composed of the first thin film transistor T1 and the second thin film transistor T2, which can reduce power consumption and improve data signal writing efficiency.
  • the photosensitive output circuit 6, as shown in FIG. 2a and FIG. 3a may include: a third thin film transistor T3;
  • the gate of the third thin film transistor T3 is connected to the first gate signal terminal G1, the source is connected to the output end of the photosensitive driving circuit 5, and the drain is connected to the read signal terminal R;
  • the first thin film transistor T1 is an N-type transistor
  • the third thin film transistor T3 is an N-type transistor
  • the first thin film transistor T1 is a P-type transistor
  • the third thin film transistor T3 is P-type transistor.
  • the third thin film transistor T3 when the third thin film transistor T3 is in an on state under the control of the first gate signal terminal G1, the electrical signal output from the photosensitive driving circuit 5 is transmitted to the read signal. End R.
  • the third thin film transistor T3 may be a P-type transistor.
  • the third thin film transistor T3 When the first gate signal terminal G1 is loaded with a low-level effective pulse signal, the third thin film transistor T3 is in an on state.
  • the third thin film transistor T3 may also be an N-type transistor, which is not limited herein.
  • the third film transistor T3 When the first gate signal terminal G1 is loaded with a high-level effective pulse signal, the third film transistor T3 is used. It is in the on state.
  • the light-emitting driving circuit 2 may include: a fourth thin film transistor T4, a first driving transistor DTFT1, and a first capacitor C1; ,
  • the gate of the fourth thin film transistor T4 is connected to the first control signal terminal EM1, the source is connected to the first reference signal terminal VDD, and the drain is connected to the source of the first driving transistor DTFT1;
  • a gate of the first driving transistor DTFT1 is connected to the first node A, and a drain is connected to the second node B;
  • the first capacitor C1 is connected to the first node A.
  • the fourth thin film transistor T4 when the fourth thin film transistor T4 is in an on state under the control of the first control signal terminal EM1, the first reference signal of the first reference signal terminal VDD is supplied to the first A source of the driving transistor DTFT1.
  • the fourth thin film transistor T4 may be a P-type transistor.
  • the fourth thin film transistor T4 When the first control signal terminal EM1 is loaded with a low-level effective pulse signal, the fourth thin film transistor T4 is in an on state.
  • the fourth thin film transistor T4 may also be an N-type transistor, which is not limited herein.
  • the fourth thin film transistor T4 When the first control signal terminal EM1 is loaded with a high-level effective pulse signal, the fourth thin film transistor T4 is at On state.
  • the first driving transistor DTFT1 controls the drain output current amount of the first driving transistor DTFT1 under the potential control of the first node A.
  • the first driving transistor DTFT1 may be a P-type transistor. When the first node A is at a low potential, the first driving transistor DTFT1 is in an on state.
  • the first driving transistor DTFT1 may be an N-type transistor, which is not limited herein. When the first node A is at a high potential, the first driving transistor DTFT1 is in an on state.
  • the first capacitor C1 is used to maintain the potential of the first node A to ensure that the first driving transistor DTFT1 is continuously turned on.
  • the photosensitive driving circuit 5 may include: a second driving transistor DTFT2 and a second capacitor C2;
  • the gate of the second driving transistor DTFT2 is connected to the third node C, the source is connected to the first reference signal terminal VDD, and the drain is connected to the input end of the photosensitive output circuit 6;
  • the second capacitor C2 is connected to the third node C.
  • the second driving transistor DTFT2 controls the amount of drain output current of the second driving transistor DTFT2 under the potential control of the third node C.
  • the second driving transistor DTFT2 may be a P-type transistor. When the third node C is at a low potential, the second driving transistor DTFT2 is in an on state.
  • the second driving transistor DTFT2 may be an N-type transistor, which is not limited herein. When the third node C is at a high potential, the second driving transistor DTFT2 is in an on state.
  • the second capacitor C2 is used to maintain the potential of the third node C to ensure that the second driving transistor DTFT2 is continuously turned on.
  • the first driving transistor DTFT1 in the light emitting driving circuit 2 and the second driving transistor DTFT2 in the photosensitive driving circuit 5 may constitute a CMOS structure to reduce power consumption and improve illumination driving. And sensitization drive efficiency.
  • the initialization circuit 4 may include: a fifth thin film transistor T5;
  • the gate of the fifth thin film transistor T5 is connected to the initialization signal terminal Vint, the source is connected to the second control signal terminal EM2, and the drain is connected to the third node C.
  • the fifth thin film transistor T5 when the fifth thin film transistor T5 is in an on state under the control of the second control signal terminal EM2, the initialization signal of the initialization signal terminal Vint is supplied to the third node C. .
  • the fifth thin film transistor T5 may be a P-type transistor.
  • the fifth thin film transistor T5 When the second control signal terminal EM2 is loaded with a low-level effective pulse signal, the fifth thin film transistor T5 is in an on state.
  • the fifth thin film transistor T5 may also be an N-type transistor, which is not limited herein.
  • the fifth thin film transistor T5 When the second control signal terminal EM2 is loaded with a high-level effective pulse signal, the fifth thin film transistor T5 is at On state.
  • the first control signal terminal EM1 and the second control signal terminal EM2 may be the same signal terminal, so as to save wiring complexity;
  • the fourth thin film transistor T4 may be an N-type transistor, and the fifth thin film transistor T5 may be a P-type transistor; when the first control signal terminal EM1 and the second control signal terminal EM2 are loaded with a high-level effective pulse signal, the fourth thin film transistor T4 is in an on state, and the fifth thin film transistor T5 is in an off state; when the first control signal terminal EM1 and the second control signal terminal EM2 are loaded with a low level effective pulse signal, the fourth thin film transistor T4 is in an off state, and the fifth The thin film transistor T5 is in an on state;
  • the fifth thin film transistor T5 may be an N-type transistor, and the fourth thin film transistor T4 may be a P-type transistor; as shown in FIG. 4b, at the first control signal terminal EM1 and the second control signal terminal EM2 When the low-level effective pulse signal is loaded, the fourth thin film transistor T4 is in an on state, and the fifth thin film transistor T5 is in an off state; the first control signal terminal EM1 and the second control signal terminal EM2 are loaded with a high level effective pulse. At the time of the signal, the fourth thin film transistor T4 is in an off state, and the fifth thin film transistor T5 is in an on state.
  • the fourth thin film transistor T4 in the light emitting driving circuit 2 and the fifth thin film transistor T5 in the initializing circuit 4 may constitute a CMOS structure to reduce power consumption and improve illumination driving and Photosensitive initialization efficiency.
  • the first control signal terminal EM1 and the second control signal terminal EM2 may also be different signal terminals, load the same control signal or load as shown in FIG. 2a and FIG. 3b. Different control signals are not limited herein.
  • the first control signal terminal EM1 and the second control signal terminal EM2 are loaded with different control signals, it can be ensured that the light-emitting device 3 does not emit light during the period in which the photosensitive signal is read, so that the external light brightness detected by the photosensitive device 7 at this time is The information is more accurate.
  • the sixth thin film transistor T6 of the same type as the fifth thin film transistor T5 may be further included;
  • the gate of the sixth thin film transistor T6 is connected to the second control signal terminal EM2, the source is connected to the common signal terminal Vcom, and the drain is connected to the second node B.
  • the sixth thin film transistor T6 when the sixth thin film transistor T6 is in an on state under the control of the second control signal terminal EM2, the common potential signal of the common signal terminal Vcom is supplied to the second node B. In order to reset the anode potential of the light-emitting device 3, the potential of the second node B before the light-emitting is fixed, thereby improving the motion blur problem.
  • the sixth thin film transistor T6 may be a P-type transistor.
  • the sixth thin film transistor T6 When the second control signal terminal EM2 is loaded with a low-level effective pulse signal, the sixth thin film transistor T6 is in an on state.
  • the sixth thin film transistor T6 may also be an N-type transistor, which is not limited herein.
  • the second control signal terminal EM2 When the second control signal terminal EM2 is loaded with a high-level effective pulse signal, the sixth thin film transistor T6 is at On state.
  • the third thin film transistor T3 and the sixth thin film transistor T6 in the photosensitive output circuit 6 may constitute a CMOS structure to reduce power consumption and improve power consumption.
  • each module in the pixel circuit provided by the embodiment of the present disclosure.
  • the specific structure of each module is not limited to the foregoing structure provided by the embodiment of the present disclosure, and may be known to those skilled in the art. Other structures are not limited here.
  • the first reference signal terminal VDD is at a high potential
  • the second reference signal terminal VSS is at a low potential.
  • the corresponding input/output timing diagram is as shown in FIG. 2b.
  • the main selection is as follows. The continuous first time period, the second time period, and the third time period in the input-output timing chart shown in FIG. 2b are described.
  • the turned-on first thin film transistor T1 and the second thin film transistor T2 write the data signal of the data signal terminal D to the first node A, and the first capacitor C1 ensures continuous light emission within one frame time.
  • the photosensitive device 7 is irradiated with incident light from the external environment, the photon-excited electron-hole pair is generated on the PN junction of the photosensitive device 7, and the charge on the PN junction capacitance is recombined, causing the potential of the third node C to drop and stored in the first
  • the potential change of the third node C causes the gate voltage of the second driving transistor DTFT2 to change, causing the drain current of the second driving transistor DTFT2 to change, and the third thin film transistor T3 that is turned on at the same time.
  • the drain current of the second driving transistor DTFT2 is supplied to the read signal terminal R to be derived. According to the derived current signal, after the optical signal is converted into an electrical signal, the external light intensity information can be finally detected at this time. According to the external light intensity information obtained at this time, it can be confirmed whether the environment in which the display device is located is a high-bright environment or a low-brightness environment, and according to the detection mode, real-time adjustment conversion of the display device is realized. Moreover, since the fourth thin film transistor T4 is in an off state, it can be ensured that the light emitting device 3 does not emit light, so that the detected external light intensity information is more accurate.
  • the first reference signal terminal VDD is at a high potential
  • the second reference signal terminal VSS is at a low potential.
  • the corresponding input and output timing diagram is as shown in FIG. 4b.
  • the main selection is as follows. The continuous first time period, the second time period, and the third time period in the input-output timing chart shown in FIG. 4b are described.
  • the anode potential of the light-emitting device 3 is reset by supplying the common potential signal of the common signal terminal Vcom to the second node B.
  • the turned-on first thin film transistor T1 and the second thin film transistor T2 write the data signal of the data signal terminal D to the first node A, and the first capacitor C1 ensures continuous light emission within one frame time.
  • the photosensitive device 7 is irradiated with incident light from the external environment, the photon-excited electron-hole pair is generated on the PN junction of the photosensitive device 7, and the charge on the PN junction capacitance is recombined, causing the potential of the third node C to drop and stored in the first
  • the potential change of the third node C causes the gate voltage of the second driving transistor DTFT2 to change, causing the drain current of the second driving transistor DTFT2 to change, and the third thin film transistor T3 that is turned on at the same time.
  • the drain current of the second driving transistor DTFT2 is supplied to the read signal terminal R to be derived. According to the derived current signal, after the optical signal is converted into an electrical signal, the external light intensity information can be finally detected at this time. According to the external light intensity information obtained at this time, it can be confirmed whether the environment in which the display device is located is a high-bright environment or a low-brightness environment, and according to the detection mode, real-time adjustment conversion of the display device is realized.
  • the potential of the second node B is controlled to form a voltage across the cathode and the anode of the light-emitting device 3 to control the brightness of the light-emitting device 3; the fifth thin film transistor T5 and the sixth thin film transistor T6 are in an off state.
  • an embodiment of the present disclosure further provides a driving method of a pixel circuit, including:
  • the initialization circuit transmits the initialization signal provided by the initialization signal terminal to the third node under the control of the second control signal end;
  • the photosensitive device controls the potential of the third node according to the received illumination intensity, and the photosensitive driving circuit outputs a corresponding electrical signal under the potential control of the third node, and the photosensitive output circuit controls at the signal end of the first gate.
  • the electrical signal output by the photosensitive driving circuit is transmitted to the reading signal terminal.
  • the method further includes:
  • the data writing circuit transmits the data signal provided by the data signal end to the first node under the control of the first gate signal end;
  • the illumination driving circuit drives the light emitting device to emit light under the control of the potential of the first node and the first control signal end;
  • the first time period, the second time period, and the third time period are time periods that are sequentially connected.
  • the method further includes: in a first time period, the sixth thin film transistor provides the common potential signal of the common signal end to the second node under the control of the second control signal end, to Reset the anode of the illuminator to avoid motion blur.
  • an embodiment of the present disclosure further provides an electroluminescent display panel, including a plurality of illuminating pixels, and at least part of the illuminating pixels includes a pixel circuit provided by an embodiment of the present disclosure.
  • the illuminating pixel including the pixel circuit provided by the embodiment of the present disclosure may be located at the side of the display area (AA), for example, the illuminating pixel may be disposed according to the pixel arrangement manner as shown in FIG. 5a, or may be as shown in FIG. 5b.
  • the illuminating pixel is disposed in the manner of dividing the surrounding area, which is not limited herein.
  • the filling area shown in FIG. 5a and FIG. 5b is the illuminating pixel, and may of course be disposed at other positions of the display area, which is not limited herein.
  • the base substrate of the electroluminescent display panel may be a silicon wafer. That is, the electroluminescent display panel may be a silicon-based OLED.
  • Silicon-based OLEDs are at the intersection of microelectronics and optoelectronics and cover a wide range of topics, including optoelectronics, microelectronics, electronic informatics and optics. They are related to physics, chemistry, materials science and electronics. Multidisciplinary research areas.
  • the combination of OLED technology and CMOS technology is the cross-integration of the optoelectronics industry and the microelectronics industry, promoting the development of a new generation of microdisplays, and promoting the research and development of organic electrons on silicon and even molecular electrons on silicon. Compared to DMD and LCOS microdisplays, silicon-based OLED microdisplays have excellent display characteristics.
  • OLED has high brightness, rich color, low driving voltage, fast response, low power consumption and excellent user experience.
  • OLED is an all-solid-state device with good seismic performance and wide operating temperature range (-40°C ⁇ 85). °C), suitable for military and special applications; it is also a self-illuminating device, does not require a backlight, has a wide viewing angle range, and is thin in thickness, which is beneficial to reduce the system volume, and is especially suitable for a near-eye display system.
  • the display screen requires that the core product indicator is brightness, because AR products need to adjust the brightness of their screens in different working environments and scenes to achieve a sensory experience suitable for the human eye, especially outdoors. In this mode of direct sunlight, we need to adjust the brightness of the device according to the change of external light intensity.
  • the conventional OLED module is composed of a TFT backplane and a light-emitting device (EL).
  • the TFT backplane implements a compensation circuit and a peripheral GOA function, and the EL portion realizes a light-emitting function.
  • the traditional glass-based LTPS process is difficult to achieve high-end high-brightness PPI solutions (1500+ or higher), so it can only be realized by high-speed and high-mobility silicon-based OLED displays.
  • the silicon-based OLED is fabricated on the IC Wafer, including the pixel driver and the GOA and the previous IC driver (all integrated into the wafer). After the wafer is finished, the anode and the subsequent EL are formed, and finally the color film is protected. Film cover (CF cover) and the like.
  • an embodiment of the present disclosure further provides a driving method of an electroluminescent display panel, including:
  • the driving method of the electroluminescent display panel realizes the silicon-based OLED display device by detecting the ambient light brightness in real time during the normal display process and reasonably selecting the Gamma Code in the specific mode. Automatically switch display mode in real time.
  • an embodiment of the present disclosure further provides a display device, including the above-mentioned electroluminescent display panel provided by the embodiment of the present disclosure, which may be: a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame. , navigation, etc. Any product or component that has a display function.
  • a display device including the above-mentioned electroluminescent display panel provided by the embodiment of the present disclosure, which may be: a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame. , navigation, etc. Any product or component that has a display function.
  • the display device reference may be made to the embodiment of the electroluminescent display panel described above, and the repeated description is omitted.
  • the pixel circuit and the electroluminescence display panel, the driving method thereof and the display device provided by the embodiments of the present disclosure add an initialization circuit, a photosensitive driving circuit, a photosensitive output circuit and a photosensitive device to the pixel circuit, under the control of the second control signal end
  • the initialization signal provided by the initialization signal terminal is transmitted to the third node through the initialization circuit, and under the potential control of the third node, the photosensitive driving circuit outputs a corresponding electrical signal, and under the control of the first gate signal terminal, the photosensitive output circuit will
  • the electrical signal outputted by the photosensitive driving circuit is transmitted to the reading signal end, and the external environment brightness detection in the pixel circuit can be completed while controlling the pixel circuit to emit light, thereby realizing the optical detection function in the on-screen, and the display screen is convenient according to the detected The external environment brightness adjustment display mode.
  • the optical detection function inside the pixel circuit does not occupy the panel area, which is advantageous for narrow bezel or full screen design; and, without separately providing an external detector

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Abstract

一种像素电路和电致发光显示面板、其驱动方法及显示装置，在像素电路中增加初始化电路（4）、感光驱动电路（5）、感光输出电路（6）和感光器件（7），在第二控制信号端（EM2）的控制下通过初始化电路（4）将初始化信号端（Vint）提供的初始化信号传输至第三节点（C），在第三节点（C）的电位控制下感光驱动电路（5）输出对应的电信号，在第一栅极信号端（G1）的控制下感光输出电路（6）将感光驱动电路（5）输出的电信号传输至读取信号端（R），可以在控制像素电路发光时，完成在像素电路内的外部环境亮度探测，实现自带屏内光学检测功能，便于显示屏根据检测到的外部环境亮度调整显示模式，在像素电路内部实现光学检测功能，不会占用面板面积，有利于窄边框或全面屏设计，且不用单独设置外部探测器件以节省成本。

Description

像素电路和电致发光显示面板、其驱动方法及显示装置
本公开要求在2018年05月09日提交中国专利局、公开号为201810436464.5，公开名称为“像素电路和电致发光显示面板、其驱动方法及显示装置”的中国专利公开的优先权，其全部内容以引入的方式并入本公开中。
技术领域
本公开涉及显示技术领域，尤其涉及像素电路和电致发光显示面板、其驱动方法及显示装置。
背景技术
有源矩阵型OLED(Active Matrix OLED,AMOLED)具有呈阵列式排布的像素电路，属于主动显示类型，具有发光效能高、对比度高、视角宽等优点，通常被用于高清晰的大尺寸显示装置。目前，常用的AMOLED像素电路为电流型驱动电路，当有电流经过有机发光二极管时，有机发光二极管发光，且像素灰阶亮度可以通过控制流经有机发光二极管自身的电流大小来实现亮度的变化。
发明内容
本公开实施例提供了像素电路，包括：感光电路以及用于驱动像素发光的驱动电路，所述感光电路包括：初始化电路、感光驱动电路、感光输出电路和感光器件；
所述初始化电路用于在第二控制信号端的控制下，将初始化信号端提供的初始化信号传输至第三节点；
所述感光器件用于根据接收到的光照强度，控制所述第三节点的电位；
所述感光驱动电路用于在所述第三节点的电位控制下，输出对应的电信 号；
所述感光输出电路用于在第一栅极信号端的控制下，将所述感光驱动电路输出的电信号传输至读取信号端。
在一种可能的实现方式中，在本公开实施例提供的像素电路中，所述初始化电路的输入端与所述初始化信号端相连，控制端与所述第二控制信号端相连，输出端与所述第三节点相连；
所述感光器件的一端与所述第三节点相连，另一端接地；
所述感光驱动电路的输入端与所述第一参考信号端相连，控制端与所述第三节点相连，输出端与所述感光输出电路的输入端相连；
所述感光输出电路的控制端与所述第一栅极信号端相连，输出端与所述读取信号端相连。
在一种可能的实现方式中，在本公开实施例提供的像素电路中，所述驱动电路包括：数据写入电路、发光驱动电路和发光器件；
所述数据写入电路的输入端与数据信号端相连，控制端与所述第一栅极信号端相连，输出端与第一节点相连；所述数据写入电路用于在所述第一栅极信号端的控制下，将所述数据信号端提供的数据信号传输至第一节点；
所述发光驱动电路的输入端与所述第一参考信号端相连，第一控制端与所述第一节点相连，第二控制端与第一控制信号端相连，输出端与第二节点相连；所述发光器件连接于所述第二节点与第二参考信号端之间；所述发光驱动电路用于在所述第一节点的电位和所述第一控制信号端的控制下，驱动所述发光器件发光。
在一种可能的实现方式中，在本公开实施例提供的像素电路中，所述数据写入电路，包括：第一薄膜晶体管；
所述第一薄膜晶体管的栅极与所述第一栅极信号端相连，源极与所述数据信号端相连，漏极与所述第一节点相连。
在一种可能的实现方式中，在本公开实施例提供的像素电路中，所述数据写入电路，还包括：第二薄膜晶体管；
所述第二薄膜晶体管的栅极与第二栅极信号端相连，源极与所述数据信号端相连，漏极与所述第一节点相连；
所述第一薄膜晶体管为N型晶体管，所述第二薄膜晶体管为P型晶体管；或，所述第二薄膜晶体管为N型晶体管，所述第一薄膜晶体管为P型晶体管；
所述第二栅极信号端和所述第一栅极信号端提供相反的电信号。
在一种可能的实现方式中，在本公开实施例提供的像素电路中，所述感光输出电路包括：第三薄膜晶体管；
所述第三薄膜晶体管的栅极与所述第一栅极信号端相连，源极与所述感光驱动电路的输出端相连，漏极与所述读取信号端相连；
所述第一薄膜晶体管为N型晶体管，所述第三薄膜晶体管为N型晶体管；或，所述第一薄膜晶体管为P型晶体管，所述第三薄膜晶体管为P型晶体管。
在一种可能的实现方式中，在本公开实施例提供的像素电路中，所述发光驱动电路包括：第四薄膜晶体管、第一驱动晶体管和第一电容；其中，
所述第四薄膜晶体管的栅极与所述第一控制信号端相连，源极与所述第一参考信号端相连，漏极与所述第一驱动晶体管的源极相连；
所述第一驱动晶体管的栅极与所述第一节点相连，漏极与所述第二节点相连；
所述第一电容与所述第一节点相连。
在一种可能的实现方式中，在本公开实施例提供的像素电路中，所述初始化电路包括：第五薄膜晶体管；
所述第五薄膜晶体管的栅极与所述初始化信号端相连，源极与所述第二控制信号端相连，漏极与所述第三节点相连。
在一种可能的实现方式中，在本公开实施例提供的像素电路中，所述第一控制信号端和所述第二控制信号端为同一信号端；
所述第四薄膜晶体管为N型晶体管，所述第五薄膜晶体管为P型晶体管；或，所述第五薄膜晶体管为N型晶体管，所述第四薄膜晶体管为P型晶体管。
在一种可能的实现方式中，在本公开实施例提供的像素电路中，还包括： 与所述第五薄膜晶体管类型相同的第六薄膜晶体管；
所述第六薄膜晶体管的栅极与所述第二控制信号端相连，源极与公共信号端相连，漏极与所述第二节点相连。
在一种可能的实现方式中，在本公开实施例提供的像素电路中，所述感光驱动电路包括：第二驱动晶体管和第二电容；其中，
所述第二驱动晶体管的栅极与所述第三节点相连，源极与所述第一参考信号端相连，漏极与所述感光输出电路的输入端相连；
所述第二电容与所述第三节点相连。
另一方面，本公开实施例还提供了像素电路的驱动方法，包括：
在第一时段，初始化电路在第二控制信号端的控制下，将初始化信号端提供的初始化信号传输至第三节点；
在第二时段，感光器件根据接收到的光照强度，控制所述第三节点的电位，感光驱动电路在所述第三节点的电位控制下，输出对应的电信号，感光输出电路在所述第一栅极信号端的控制下，将所述感光驱动电路输出的电信号传输至读取信号端。
在一种可能的实现方式中，在本公开实施例提供的驱动方法中，还包括：
在第二时段，数据写入电路在第一栅极信号端的控制下，将数据信号端提供的数据信号传输至第一节点；
在第三时段，发光驱动电路在所述第一节点的电位和所述第一控制信号端的控制下，驱动所述发光器件发光；
所述第一时段、第二时段和第三时段为顺序连接的时段。
在一种可能的实现方式中，在本公开实施例提供的驱动方法中，还包括：所述第一时段，第六薄膜晶体管在所述第二控制信号端的控制下，将公共信号端的公共电位信号提供至第二节点。
另一方面，本公开实施例还提供了电致发光显示面板，包括多个发光像素，至少部分所述发光像素中包括上述像素电路。
在一种可能的实现方式中，在本公开实施例提供的电致发光显示面板中， 所述电致发光显示面板的衬底基板为硅晶片。
另一方面，本公开实施例还提供了电致发光显示面板的驱动方法，包括：
通过读取感光驱动电路输出的电信号强度，确定感光器件接收到的外部光照强度；
根据所述外部光照强度，在高亮度和高对比度之间各发光像素的工作模式。
另一方面，本公开实施例还提供了显示装置，包括所述电致发光显示面板。
附图说明
图1为本公开实施例提供的像素电路的结构示意图；
图2a为本公开实施例提供的像素电路的一种具体结构示意图；
图2b为图2a对应的输入输出信号时序图；
图3a为本公开实施例提供的像素电路的另一种具体结构示意图；
图3b为图3a对应的输入输出信号时序图；
图4a为本公开实施例提供的像素电路的另一种具体结构示意图；
图4b为图4a对应的输入输出信号时序图；
图5a和图5b分别为本公开实施例提供的电致发光显示面板的结构示意图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开作进一步地详细描述，显然，所描述的实施例仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本公开保护的范围。
附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
本公开实施例提供的一种像素电路，如图1所示，包括：感光电路以及用于驱动像素发光的驱动电路，所述感光电路包括：初始化电路4、感光驱动电路5、感光输出电路6和感光器件7；其中，
初始化电路4用于在第二控制信号端EM2的控制下，将初始化信号端Vint提供的初始化信号传输至第三节点A；
感光器件7用于根据接收到的光照强度，控制第三节点C的电位；
感光驱动电路5用于在第三节点C的电位控制下，输出对应的电信号；
感光输出电路6用于在第一栅极信号端G1的控制下，将感光驱动电路5输出的电信号传输至读取信号端R。
具体地，在本公开实施例提供的像素电路中，增加了初始化电路4、感光驱动电路5、感光输出电路6和感光器件7，在第二控制信号端EM2的控制下，通过初始化电路4将初始化信号端Vint提供的初始化信号传输至第三节点A，在第三节点C的电位控制下，感光驱动电路5输出对应的电信号，在第一栅极信号端G1的控制下，感光输出电路6将感光驱动电路5输出的电信号传输至读取信号端R，可以在控制像素电路发光的同时，完成在像素电路内的外部环境亮度探测，实现自带屏内光学检测功能，便于显示屏根据检测到的外部环境亮度调整显示模式。在像素电路内部实现光学检测功能，不会占用面板面积，有利于窄边框或全面屏设计；并且，不用单独设置外部探测器件，可以节省成本。
可选地，在本公开实施例提供的像素电路中，如图1所示，初始化电路4的输入端与初始化信号端Vint相连，控制端与第二控制信号端EM2相连，输出端与第三节点C相连；
感光器件7的一端与第三节点C相连，另一端接地；
感光驱动电路5的输入端与第一参考信号端VDD相连，控制端与第三节点C相连，输出端与感光输出电路6的输入端相连；
感光输出电路6的控制端与第一栅极信号端G1相连，输出端与读取信号端R相连。
可选地，在本公开实施例提供的像素电路中，如图1所示，驱动电路包括：数据写入电路1、发光驱动电路2和发光器件3；
数据写入电路1的输入端与数据信号端D相连，控制端与第一栅极信号端G1相连，输出端与第一节点A相连；数据写入电路1用于在第一栅极信号端G1的控制下，将数据信号端D提供的数据信号传输至第一节点A；
发光驱动电路2的输入端与第一参考信号端VDD相连，第一控制端与第一节点A相连，第二控制端与第一控制信号端EM1相连，输出端与第二节点B相连；发光器件3连接于第二节点B与第二参考信号端VSS之间；发光驱动电路2用于在第一节点A的电位和第一控制信号端EM1的控制下，驱动发光器件3发光。
可选地，在本公开实施例提供的像素电路中，如图2a和图3a所示，数据写入电路1，可以包括：第一薄膜晶体管T1；
第一薄膜晶体管T1的栅极与第一栅极信号端G1相连，源极与数据信号端D相连，漏极与第一节点A相连。
具体地，在本公开实施例提供的像素电路中，第一薄膜晶体管T1在第一栅极信号端G1的控制下处于导通状态时，将数据信号端D的数据信号提供给第一节点A。并且，如图2a所示，第一薄膜晶体管T1可以为P型晶体管，此时第一栅极信号端G1加载低电平的有效脉冲信号时，第一薄膜晶体管T1处于导通状态。或者，如图3a所示，第一薄膜晶体管T1也可以为N型晶体管，在此不做限定，此时第一栅极信号端G1加载高电平的有效脉冲信号时，第一薄膜晶体管T1处于导通状态。
可选地，在本公开实施例提供的像素电路中，数据写入电路1，还可以包括：第二薄膜晶体管T2；
第二薄膜晶体管T2的栅极与第二栅极信号端G2相连，源极与数据信号端D相连，漏极与第一节点A相连；
第一薄膜晶体管T1为N型晶体管，第二薄膜晶体管T2为P型晶体管；或，第二薄膜晶体管T2为N型晶体管，第一薄膜晶体管T1为P型晶体管；
第二栅极信号端G2和第一栅极信号端G1提供相反的电信号。
具体地，在本公开实施例提供的像素电路中，第二薄膜晶体管T2在第二栅极信号端G2的控制下处于导通状态时，将数据信号端D的数据信号提供给第一节点A。并且，如图3a所示，第二薄膜晶体管T2可以为P型晶体管，此时第二栅极信号端G2加载低电平的有效脉冲信号时，第二薄膜晶体管T2处于导通状态。或者，如图2a所示，第二薄膜晶体管T2也可以为N型晶体管，在此不做限定，此时第二栅极信号端G2加载高电平的有效脉冲信号时，第二薄膜晶体管T2处于导通状态。
具体地，在本公开实施例提供的像素电路中，在数据写入电路1中采用第一薄膜晶体管T1和第二薄膜晶体管T2可以构成CMOS(Complementary Metal-Oxide Semiconductor，互补性金属氧化物半导体)。CMOS由PMOS和NMOS管共同构成，由于NMOS和PMOS是互补的，因此叫互补型MOS，即CMOS。由于CMOS中一对MOS组成的门电路在瞬间要么PMOS导通，要么NMOS导通，要么都截止，所以比晶体管效率高得多，因此功耗很低。因此，数据写入电路1采用第一薄膜晶体管T1和第二薄膜晶体管T2构成的CMOS结构，可以降低功耗，提高数据信号写入效率。
可选地，在本公开实施例提供的像素电路中，感光输出电路6，如图2a和图3a所示，可以包括：第三薄膜晶体管T3；
第三薄膜晶体管T3的栅极与第一栅极信号端G1相连，源极与感光驱动电路5的输出端相连，漏极与读取信号端R相连；
如图3a所示，第一薄膜晶体管T1为N型晶体管，第三薄膜晶体管T3为N型晶体管；或，如图2a所示，第一薄膜晶体管T1为P型晶体管，第三薄膜晶体管T3为P型晶体管。
具体地，在本公开实施例提供的像素电路中，第三薄膜晶体管T3在第一栅极信号端G1的控制下处于导通状态时，将感光驱动电路5输出的电信号传输至读取信号端R。并且，如图2a所示，第三薄膜晶体管T3可以为P型晶体管，此时第一栅极信号端G1加载低电平的有效脉冲信号时，第三薄膜晶体 管T3处于导通状态。或者，如图3a所示，第三薄膜晶体管T3也可以为N型晶体管，在此不做限定，此时第一栅极信号端G1加载高电平的有效脉冲信号时，第三膜晶体管T3处于导通状态。
可选地，在本公开实施例提供的像素电路中，发光驱动电路2，如图2a和图3a所示，可以包括：第四薄膜晶体管T4、第一驱动晶体管DTFT1和第一电容C1；其中，
第四薄膜晶体管T4的栅极与第一控制信号端EM1相连，源极与第一参考信号端VDD相连，漏极与第一驱动晶体管DTFT1的源极相连；
第一驱动晶体管DTFT1的栅极与第一节点A相连，漏极与第二节点B相连；
第一电容C1与第一节点A相连。
具体地，在本公开实施例提供的像素电路中，第四薄膜晶体管T4在第一控制信号端EM1的控制下处于导通状态时，将第一参考信号端VDD的第一参考信号提供给第一驱动晶体管DTFT1的源极。并且，如图2a所示，第四薄膜晶体管T4可以为P型晶体管，此时第一控制信号端EM1加载低电平的有效脉冲信号时，第四薄膜晶体管T4处于导通状态。或者，如图3a所示，第四薄膜晶体管T4也可以为N型晶体管，在此不做限定，此时第一控制信号端EM1加载高电平的有效脉冲信号时，第四薄膜晶体管T4处于导通状态。
具体地，在本公开实施例提供的像素电路中，第一驱动晶体管DTFT1在第一节点A的电位控制下，控制第一驱动晶体管DTFT1的漏极输出电流量。并且，第一驱动晶体管DTFT1可以为P型晶体管，此时第一节点A为低电位时，第一驱动晶体管DTFT1处于导通状态。或者，如图2a至图3a所示，第一驱动晶体管DTFT1也可以为N型晶体管，在此不做限定，此时第一节点A为高电位时，第一驱动晶体管DTFT1处于导通状态。
具体地，在本公开实施例提供的像素电路中，第一电容C1用于保持第一节点A的电位，以保证第一驱动晶体管DTFT1持续导通。
可选地，在本公开实施例提供的像素电路中，感光驱动电路5，如图2a 和图3a所示，可以包括：第二驱动晶体管DTFT2和第二电容C2；其中，
第二驱动晶体管DTFT2的栅极与第三节点C相连，源极与第一参考信号端VDD相连，漏极与感光输出电路6的输入端相连；
第二电容C2与第三节点C相连。
具体地，在本公开实施例提供的像素电路中，第二驱动晶体管DTFT2在第三节点C的电位控制下，控制第二驱动晶体管DTFT2的漏极输出电流量。并且，如图2a至图3a所示，第二驱动晶体管DTFT2可以为P型晶体管，此时第三节点C为低电位时，第二驱动晶体管DTFT2处于导通状态。或者，第二驱动晶体管DTFT2也可以为N型晶体管，在此不做限定，此时第三节点C为高电位时，第二驱动晶体管DTFT2处于导通状态。
具体地，在本公开实施例提供的像素电路中，第二电容C2用于保持第三节点C的电位，以保证第二驱动晶体管DTFT2持续导通。
具体地，在本公开实施例提供的像素电路中，发光驱动电路2中的第一驱动晶体管DTFT1和感光驱动电路5中的第二驱动晶体管DTFT2可以构成CMOS结构，以降低功耗，提高发光驱动和感光驱动效率。
可选地，在本公开实施例提供的像素电路中，初始化电路4，如图2a和图3a所示，可以包括：第五薄膜晶体管T5；
第五薄膜晶体管T5的栅极与初始化信号端Vint相连，源极与第二控制信号端EM2相连，漏极与第三节点C相连。
具体地，在本公开实施例提供的像素电路中，第五薄膜晶体管T5在第二控制信号端EM2的控制下处于导通状态时，将始化信号端Vint的初始化信号提供给第三节点C。并且，如图3a所示，第五薄膜晶体管T5可以为P型晶体管，此时第二控制信号端EM2加载低电平的有效脉冲信号时，第五薄膜晶体管T5处于导通状态。或者，如图2a所示，第五薄膜晶体管T5也可以为N型晶体管，在此不做限定，此时第二控制信号端EM2加载高电平的有效脉冲信号时，第五薄膜晶体管T5处于导通状态。
可选地，在本公开实施例提供的像素电路中，如图4a所示，第一控制信 号端EM1和第二控制信号端EM2可以为同一信号端，以便节省布线复杂程度；
第四薄膜晶体管T4可以为N型晶体管，第五薄膜晶体管T5可以为P型晶体管；在第一控制信号端EM1和第二控制信号端EM2加载高电平的有效脉冲信号时，第四薄膜晶体管T4处于导通状态，第五薄膜晶体管T5处于截止状态；在第一控制信号端EM1和第二控制信号端EM2加载低电平的有效脉冲信号时，第四薄膜晶体管T4处于截止状态，第五薄膜晶体管T5处于导通状态；
或者，如图4a所示，第五薄膜晶体管T5可以为N型晶体管，第四薄膜晶体管T4可以为P型晶体管；如图4b所示，在第一控制信号端EM1和第二控制信号端EM2加载低电平的有效脉冲信号时，第四薄膜晶体管T4处于导通状态，第五薄膜晶体管T5处于截止状态；在第一控制信号端EM1和第二控制信号端EM2加载高电平的有效脉冲信号时，第四薄膜晶体管T4处于截止状态，第五薄膜晶体管T5处于导通状态。
具体地，在本公开实施例提供的像素电路中，发光驱动电路2中的第四薄膜晶体管T4和初始化电路4中的第五薄膜晶体管T5可以构成CMOS结构，以降低功耗，提高发光驱动和感光初始化效率。
或者，在本公开实施例提供的像素电路中，第一控制信号端EM1和第二控制信号端EM2也可以为不同的信号端，加载相同的控制信号或如图2a和图3b所示，加载不同的控制信号，在此不做限定。在第一控制信号端EM1和第二控制信号端EM2加载不同的控制信号时，可以保证在感光信号读取的时段，发光器件3不发光，以使此时感光器件7检测到的外部光亮度信息更加准确。
可选地，在本公开实施例提供的像素电路中，如图2a至图4a所示，还可以包括：与第五薄膜晶体管T5类型相同的第六薄膜晶体管T6；
第六薄膜晶体管T6的栅极与第二控制信号端EM2相连，源极与公共信号端Vcom相连，漏极与第二节点B相连。
具体地，在本公开实施例提供的像素电路中，第六薄膜晶体管T6在第二控制信号端EM2的控制下处于导通状态时，将公共信号端Vcom的公共电位信号提供给第二节点B，以对发光器件3的阳极电位进行重置，保证发光前第二节点B的电位固定，从而改善动态模糊(Motion Blur)问题。并且，如图3a所示，第六薄膜晶体管T6可以为P型晶体管，此时第二控制信号端EM2加载低电平的有效脉冲信号时，第六薄膜晶体管T6处于导通状态。或者，如图2a所示，第六薄膜晶体管T6也可以为N型晶体管，在此不做限定，此时第二控制信号端EM2加载高电平的有效脉冲信号时，第六薄膜晶体管T6处于导通状态。
具体地，在本公开实施例提供的像素电路中，感光输出电路6中的第三薄膜晶体管T3和第六薄膜晶体管T6可以构成CMOS结构，以降低功耗，提高减小功耗。
以上仅是举例说明本公开实施例提供的像素电路中各模块的具体结构，在具体实施时，上述各模块的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
下面分别以图2a和图4a所示的像素电路的结构为例，结合电路时序图对本公开实施例提供的上述像素电路的工作过程进行描述。下述描述中以1表示高电位信号，以0表示低电位信号，其中，1和0代表逻辑电位，仅是为了更好的解释本公开实施例提供的上述像素电路的工作过程，而不是在具体实施时施加在各晶体管的栅极的电位。
实施例一
以图2a所示的像素电路的结构为例，第一参考信号端VDD为高电位，第二参考信号端VSS为低电位，对应的输入输出时序图如图2b所示，具体地，主要选取图2b所示的输入输出时序图中的连续的第一时段、第二时段和第三时段进行描述。
在第一时段t1，即初始化时段，G1＝1，G2＝0，EM1＝1，EM2＝1。
由于G1＝1，因此第一薄膜晶体管T1和第三薄膜晶体管T3处于截止状态， 由于G2＝0，因此第二薄膜晶体管T2处于截止状态，由于EM1＝1，因此，第四薄膜晶体管T4处于截止状态。由于EM2＝1，因此，第五薄膜晶体管T5处于导通状态，以将初始化信号端Vint的初始化信号提供给第三节点C，对第三节点C的电位进行初始化；第六薄膜晶体管T6处于导通状态，以将公共信号端Vcom的公共电位信号提供给第二节点B，重置发光器件3的阳极电位。
在第二时段t2，即数据写入和感光读取时段，G1＝0，G2＝1，EM1＝1，EM2＝0。
由于G1＝0，因此第一薄膜晶体管T1和第三薄膜晶体管T3处于导通状态，由于G2＝1，因此第二薄膜晶体管T2处于导通状态。由于EM1＝1，因此，第四薄膜晶体管T4处于截止状态。由于EM2＝0，因此，第五薄膜晶体管T5和第六薄膜晶体管T6处于截止状态。
导通的第一薄膜晶体管T1和第二薄膜晶体管T2将数据信号端D的数据信号写入第一节点A，由第一电容C1，保证一帧时间内的持续发光。当感光器件7被外部环境入射光照射时，光量子激发感光器件7的PN结上产生电子空穴对，使PN结电容上的电荷发生复合，导致第三节点C的电势下降，并存储在第二电容C2的两端，此时第三节点C的电位变化导致第二驱动晶体管DTFT2的栅极电压变化，导致第二驱动晶体管DTFT2的漏极电流发生变化，同时导通的第三薄膜晶体管T3将第二驱动晶体管DTFT2的漏极电流提供至读取信号端R导出。根据导出的电流信号，将光信号转变为电信号后，可以最终实现此时检测外部光强度信息。根据此时得到的外部光强度信息，可以确认此时显示器件所在环境为高亮环境，还是低亮度环境，根据这种探测方式，实现显示器件实时调节转换。并且，由于第四薄膜晶体管T4处于截止状态，可以保证发光器件3不发光，使探测到的外部光强度信息更准确。
在第三时段t3，即发光时段，G1＝1，G2＝0，EM1＝0，EM2＝0。
由于G1＝1，因此第一薄膜晶体管T1和第三薄膜晶体管T3处于截止状态，由于G2＝0，因此第二薄膜晶体管T2处于截止状态，由于EM1＝0，因此，第四薄膜晶体管T4处于导通状态，将第一参考信号端VDD的高电位第一参考 信号提供至第一驱动晶体管DTFT1的源极，第一驱动晶体管DTFT1由源跟随器原理，在第一节点A的电位控制下，控制第二节点B的电位，以在发光器件3的阴极和阳极之间形成跨压，控制发光器件3的亮度。由于EM2＝0，因此，第五薄膜晶体管T5和第六薄膜晶体管T6处于截止状态。
实施例二
以图4a所示的像素电路的结构为例，第一参考信号端VDD为高电位，第二参考信号端VSS为低电位，对应的输入输出时序图如图4b所示，具体地，主要选取图4b所示的输入输出时序图中的连续的第一时段、第二时段和第三时段进行描述。
在第一时段t1，即初始化时段，G1＝1，G2＝0，EM1＝EM2＝1。
由于G1＝1，因此第一薄膜晶体管T1和第三薄膜晶体管T3处于截止状态，由于G2＝0，因此第二薄膜晶体管T2处于截止状态，由于EM1＝EM2＝1，因此，第四薄膜晶体管T4处于截止状态，第五薄膜晶体管T5处于导通状态，以将初始化信号端Vint的初始化信号提供给第三节点C，对第三节点C的电位进行初始化；第六薄膜晶体管T6处于导通状态，以将公共信号端Vcom的公共电位信号提供给第二节点B，重置发光器件3的阳极电位。
在第二时段t2，即数据写入和感光读取时段，G1＝0，G2＝1，EM1＝EM2＝0。
由于G1＝0，因此第一薄膜晶体管T1和第三薄膜晶体管T3处于导通状态，由于G2＝1，因此第二薄膜晶体管T2处于导通状态。由于EM1＝EM2＝0，因此，第四薄膜晶体管T4处于导通状态，第五薄膜晶体管T5和第六薄膜晶体管T6处于截止状态。
导通的第一薄膜晶体管T1和第二薄膜晶体管T2将数据信号端D的数据信号写入第一节点A，由第一电容C1，保证一帧时间内的持续发光。当感光器件7被外部环境入射光照射时，光量子激发感光器件7的PN结上产生电子空穴对，使PN结电容上的电荷发生复合，导致第三节点C的电势下降，并存储在第二电容C2的两端，此时第三节点C的电位变化导致第二驱动晶体管DTFT2的栅极电压变化，导致第二驱动晶体管DTFT2的漏极电流发生变化， 同时导通的第三薄膜晶体管T3将第二驱动晶体管DTFT2的漏极电流提供至读取信号端R导出。根据导出的电流信号，将光信号转变为电信号后，可以最终实现此时检测外部光强度信息。根据此时得到的外部光强度信息，可以确认此时显示器件所在环境为高亮环境，还是低亮度环境，根据这种探测方式，实现显示器件实时调节转换。
在第三时段t3，即发光时段，G1＝1，G2＝0，EM1＝EM2＝0。
由于G1＝1，因此第一薄膜晶体管T1和第三薄膜晶体管T3处于截止状态，由于G2＝0，因此第二薄膜晶体管T2处于截止状态，由于EM1＝EM2＝0，因此，第四薄膜晶体管T4处于导通状态，将第一参考信号端VDD的高电位第一参考信号提供至第一驱动晶体管DTFT1的源极，第一驱动晶体管DTFT1由源跟随器原理，在第一节点A的电位控制下，控制第二节点B的电位，以在发光器件3的阴极和阳极之间形成跨压，控制发光器件3的亮度；第五薄膜晶体管T5和第六薄膜晶体管T6处于截止状态。
基于同一发明构思，本公开实施例还提供了像素电路的驱动方法，包括：
在第一时段，初始化电路在第二控制信号端的控制下，将初始化信号端提供的初始化信号传输至第三节点；
在第二时段，感光器件根据接收到的光照强度，控制第三节点的电位，感光驱动电路在第三节点的电位控制下，输出对应的电信号，感光输出电路在第一栅极信号端的控制下，将感光驱动电路输出的电信号传输至读取信号端。
可选地，在本公开实施例提供的驱动方法中，其中，还包括：
在第二时段，数据写入电路在第一栅极信号端的控制下，将数据信号端提供的数据信号传输至第一节点；
在第三时段，发光驱动电路在第一节点的电位和第一控制信号端的控制下，驱动发光器件发光；
第一时段、第二时段和第三时段为顺序连接的时段。
可选地，在本公开实施例提供的驱动方法中，还可以包括：第一时段， 第六薄膜晶体管在第二控制信号端的控制下，将公共信号端的公共电位信号提供至第二节点，以对发光器件的阳极进行重置，避免动态模糊。
基于同一发明构思，本公开实施例还提供了电致发光显示面板，包括多个发光像素，至少部分发光像素中包括本公开实施例提供的像素电路。具体地，包括本公开实施例提供的像素电路的发光像素可以位于显示区域(AA)的侧边，例如可以按照如图5a所示的像素排布方式设置该发光像素，也可以按照如图5b所示的周边区域分割方式设置该发光像素，在此不做限定。如图5a和图5b所示的填充区域为该发光像素，当然也可以设置在显示区域的其他位置，在此不做限定。
可选地，在本公开实施例提供的电致发光显示面板中，电致发光显示面板的衬底基板可以为硅晶片(Wafer)。即电致发光显示面板可以为硅基OLED。
硅基OLED处于微电子技术和光电子技术的交叉点上，涉及的内容非常广泛，包括光电子学、微电子学、电子信息学和光学等领域，是一个涉及物理学、化学、材料学和电子学等多学科的研究领域。OLED技术和CMOS技术的结合，是光电子产业和微电子产业的交叉集成，促进了新一代的微型显示的发展，也推进了硅上有机电子，甚至是硅上分子电子的研究和发展。相比于DMD和LCOS微显示器，硅基OLED微显示器拥有非常优秀的显示特性。OLED亮度高、色彩丰富、驱动电压低、响应速度快、功耗低，具有非常优秀的用户体验；且OLED是一种全固态型器件，抗震性能好，工作温度范围宽(-40℃～85℃)，适合于军事和特殊应用；其亦属于自发光器件，不需要背光源，视角范围大，厚度薄，有利于减小系统体积，尤其适用于近眼显示系统。那么对应未来AR显示技术，其显示屏幕要求最核心的产品指标就是亮度，因为AR产品在不同的工作环境和场景下需要调节自身屏体亮度，来实现适宜人眼的感官体验，尤其是在户外直对太阳这种模式下，需要我们根据外界光强的变化，从而调节器件亮度。
传统OLED模组是由TFT背板和发光器件(EL)两部分组成，其中TFT背板实现的是补偿电路以及周边GOA功能，EL部分实现发光功能。传统的 玻璃基LTPS工艺想做高端的高亮高PPI方案很难(1500+以上)，所以只能够通过高速高迁移率的硅基OLED显示器来实现。硅基OLED是在IC Wafer上制作驱动部分，包括像素驱动和GOA以及之前的IC驱动部分(全部集成到wafer上)，wafer制作完毕后，在形成阳极及后续的EL部分，最后制作彩膜保护膜(CF cover)等。
基于同一发明构思，本公开实施例还提供了电致发光显示面板的驱动方法，包括：
通过读取感光驱动电路输出的电信号强度，确定感光器件接收到的外部光照强度；
根据外部光照强度，在高亮度和高对比度之间各发光像素的工作模式。
具体地，本公开实施例提供的电致发光显示面板的驱动方法，通过在正常显示过程中，实时的检测外界环境光亮度，合理选择特定模式下的Gamma Code，从而实现了硅基OLED显示器件实时自动切换显示模式。
基于同一发明构思，本公开实施例还提供了显示装置，包括本公开实施例提供的上述电致发光显示面板，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述电致发光显示面板的实施例，重复之处不再赘述。
本公开实施例提供的像素电路和电致发光显示面板、其驱动方法及显示装置，在像素电路中增加了初始化电路、感光驱动电路、感光输出电路和感光器件，在第二控制信号端的控制下，通过初始化电路将初始化信号端提供的初始化信号传输至第三节点，在第三节点的电位控制下，感光驱动电路输出对应的电信号，在第一栅极信号端的控制下，感光输出电路将感光驱动电路输出的电信号传输至读取信号端，可以在控制像素电路发光的同时，完成在像素电路内的外部环境亮度探测，实现自带屏内光学检测功能，便于显示屏根据检测到的外部环境亮度调整显示模式。在像素电路内部实现光学检测功能，不会占用面板面积，有利于窄边框或全面屏设计；并且，不用单独设 置外部探测器件，可以节省成本。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (18)

  1. 一种像素电路，其中，包括：感光电路以及用于驱动像素发光的驱动电路，所述感光电路包括：初始化电路、感光驱动电路、感光输出电路和感光器件；
    所述初始化电路用于在第二控制信号端的控制下，将初始化信号端提供的初始化信号传输至第三节点；
    所述感光器件用于根据接收到的光照强度，控制所述第三节点的电位；
    所述感光驱动电路用于在所述第三节点的电位控制下，输出对应的电信号；
    所述感光输出电路用于在第一栅极信号端的控制下，将所述感光驱动电路输出的电信号传输至读取信号端。
  2. 如权利要求1所述的像素电路，其中，所述初始化电路的输入端与所述初始化信号端相连，控制端与所述第二控制信号端相连，输出端与所述第三节点相连；
    所述感光器件的一端与所述第三节点相连，另一端接地；
    所述感光驱动电路的输入端与所述第一参考信号端相连，控制端与所述第三节点相连，输出端与所述感光输出电路的输入端相连；
    所述感光输出电路的控制端与所述第一栅极信号端相连，输出端与所述读取信号端相连。
  3. 如权利要求1所述的像素电路，其中，所述驱动电路包括：数据写入电路、发光驱动电路和发光器件；
    所述数据写入电路的输入端与数据信号端相连，控制端与所述第一栅极信号端相连，输出端与第一节点相连；所述数据写入电路用于在所述第一栅极信号端的控制下，将所述数据信号端提供的数据信号传输至第一节点；
    所述发光驱动电路的输入端与所述第一参考信号端相连，第一控制端与所述第一节点相连，第二控制端与第一控制信号端相连，输出端与第二节点 相连；所述发光器件连接于所述第二节点与第二参考信号端之间；所述发光驱动电路用于在所述第一节点的电位和所述第一控制信号端的控制下，驱动所述发光器件发光。
  4. 如权利要求3所述的像素电路，其中，所述数据写入电路，包括：第一薄膜晶体管；
    所述第一薄膜晶体管的栅极与所述第一栅极信号端相连，源极与所述数据信号端相连，漏极与所述第一节点相连。
  5. 如权利要求4所述的像素电路，其中，所述数据写入电路，还包括：第二薄膜晶体管；
    所述第二薄膜晶体管的栅极与第二栅极信号端相连，源极与所述数据信号端相连，漏极与所述第一节点相连；
    所述第一薄膜晶体管为N型晶体管，所述第二薄膜晶体管为P型晶体管；或，所述第二薄膜晶体管为N型晶体管，所述第一薄膜晶体管为P型晶体管；
    所述第二栅极信号端和所述第一栅极信号端提供相反的电信号。
  6. 如权利要求4所述的像素电路，其中，所述感光输出电路包括：第三薄膜晶体管；
    所述第三薄膜晶体管的栅极与所述第一栅极信号端相连，源极与所述感光驱动电路的输出端相连，漏极与所述读取信号端相连；
    所述第一薄膜晶体管为N型晶体管，所述第三薄膜晶体管为N型晶体管；或，所述第一薄膜晶体管为P型晶体管，所述第三薄膜晶体管为P型晶体管。
  7. 如权利要求3所述的像素电路，其中，所述发光驱动电路包括：第四薄膜晶体管、第一驱动晶体管和第一电容；其中，
    所述第四薄膜晶体管的栅极与所述第一控制信号端相连，源极与所述第一参考信号端相连，漏极与所述第一驱动晶体管的源极相连；
    所述第一驱动晶体管的栅极与所述第一节点相连，漏极与所述第二节点相连；
    所述第一电容与所述第一节点相连。
  8. 如权利要求7所述的像素电路，其中，所述初始化电路包括：第五薄膜晶体管；
    所述第五薄膜晶体管的栅极与所述初始化信号端相连，源极与所述第二控制信号端相连，漏极与所述第三节点相连。
  9. 如权利要求8所述的像素电路，其中，所述第一控制信号端和所述第二控制信号端为同一信号端；
    所述第四薄膜晶体管为N型晶体管，所述第五薄膜晶体管为P型晶体管；或，所述第五薄膜晶体管为N型晶体管，所述第四薄膜晶体管为P型晶体管。
  10. 如权利要求8所述的像素电路，其中，还包括：与所述第五薄膜晶体管类型相同的第六薄膜晶体管；
    所述第六薄膜晶体管的栅极与所述第二控制信号端相连，源极与公共信号端相连，漏极与所述第二节点相连。
  11. 如权利要求1-10任一项所述的像素电路，其中，所述感光驱动电路包括：第二驱动晶体管和第二电容；其中，
    所述第二驱动晶体管的栅极与所述第三节点相连，源极与所述第一参考信号端相连，漏极与所述感光输出电路的输入端相连；
    所述第二电容与所述第三节点相连。
  12. 一种如权利要求1-11任一项所述的像素电路的驱动方法，其中，包括：
    在第一时段，初始化电路在第二控制信号端的控制下，将初始化信号端提供的初始化信号传输至第三节点；
    在第二时段，感光器件根据接收到的光照强度，控制所述第三节点的电位，感光驱动电路在所述第三节点的电位控制下，输出对应的电信号，感光输出电路在所述第一栅极信号端的控制下，将所述感光驱动电路输出的电信号传输至读取信号端。
  13. 如权利要求12所述的驱动方法，其中，还包括：
    在第二时段，数据写入电路在第一栅极信号端的控制下，将数据信号端 提供的数据信号传输至第一节点；
    在第三时段，发光驱动电路在所述第一节点的电位和所述第一控制信号端的控制下，驱动所述发光器件发光；
    所述第一时段、第二时段和第三时段为顺序连接的时段。
  14. 如权利要求13所述的驱动方法，其中，还包括：所述第一时段，第六薄膜晶体管在所述第二控制信号端的控制下，将公共信号端的公共电位信号提供至第二节点。
  15. 一种电致发光显示面板，其中，包括多个发光像素，至少部分所述发光像素中包括如权利要求1-11任一项所述的像素电路。
  16. 如权利要求15所述的电致发光显示面板，其中，所述电致发光显示面板的衬底基板为硅晶片。
  17. 一种如权利要求15或16所述的电致发光显示面板的驱动方法，其中，包括：
    通过读取感光驱动电路输出的电信号强度，确定感光器件接收到的外部光照强度；
    根据所述外部光照强度，在高亮度和高对比度之间各发光像素的工作模式。
  18. 一种显示装置，其中，包括如权利要求15或16所述的电致发光显示面板。
PCT/CN2019/071599 2018-05-09 2019-01-14 像素电路和电致发光显示面板、其驱动方法及显示装置 WO2019214286A1 (zh)

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