WO2021164641A1 - 指纹识别模组及其制作方法、显示基板和显示装置 - Google Patents

指纹识别模组及其制作方法、显示基板和显示装置 Download PDF

Info

Publication number
WO2021164641A1
WO2021164641A1 PCT/CN2021/076187 CN2021076187W WO2021164641A1 WO 2021164641 A1 WO2021164641 A1 WO 2021164641A1 CN 2021076187 W CN2021076187 W CN 2021076187W WO 2021164641 A1 WO2021164641 A1 WO 2021164641A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
layer
photosensitive sensor
thin film
film transistor
Prior art date
Application number
PCT/CN2021/076187
Other languages
English (en)
French (fr)
Inventor
姚念琦
史鲁斌
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/431,636 priority Critical patent/US20220100982A1/en
Publication of WO2021164641A1 publication Critical patent/WO2021164641A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
    • G06F21/31—User authentication
    • G06F21/32—User authentication using biometric data, e.g. fingerprints, iris scans or voiceprints

Definitions

  • the embodiments of the present disclosure relate to the field of display technology, and in particular to a fingerprint identification module and a manufacturing method thereof, a display substrate and a display device.
  • the embodiments of the present disclosure provide a fingerprint identification module and a manufacturing method thereof, a display substrate and a display device.
  • a fingerprint identification module including:
  • the thin film transistor includes an active layer
  • the active layer and the connecting electrode are formed by the same semiconductor layer pattern, the semiconductor layer pattern includes a first semiconductor pattern and a second semiconductor pattern, and the first semiconductor pattern serves as the active layer through a conductor
  • the second semiconductor pattern after chemical treatment is used as the connection electrode.
  • the photosensitive sensor includes: a first electrode, a PIN layer, and a second electrode stacked on a substrate in sequence, wherein the connecting electrode is overlapped on the second electrode.
  • the fingerprint identification module further includes:
  • a gate insulating layer wherein a part of the gate insulating layer covers the surface of the second electrode away from the first electrode
  • the connecting electrode is in contact with the second electrode through the through hole.
  • the connecting electrode is a transparent electrode.
  • the photosensitive sensor includes a first electrode and a PIN layer sequentially stacked on a substrate, and the connecting electrode is a transparent electrode, which is multiplexed as a second electrode of the photosensitive sensor.
  • a part of the connecting electrode is located on a surface of the PIN layer away from the first electrode.
  • the connecting electrode is multiplexed as the second electrode of the photosensitive sensor.
  • the thin film transistor includes a gate, and the gate and the first electrode of the photosensitive sensor are provided in the same layer and the same material.
  • the connecting electrode is connected to the active layer and multiplexed as the drain of the thin film transistor;
  • connection electrode is respectively connected to the active layer and the drain electrode of the thin film transistor.
  • connection electrode is separated from the active layer, and the drain of the thin film transistor is connected to the connection electrode.
  • embodiments of the present disclosure provide a display substrate including the above-mentioned fingerprint identification module.
  • embodiments of the present disclosure provide a display device including the above-mentioned display substrate.
  • embodiments of the present disclosure provide a method for manufacturing a fingerprint recognition module, the fingerprint recognition module including a thin film transistor and a photosensitive sensor, and the manufacturing method includes:
  • the semiconductor layer pattern including a first semiconductor pattern and a second semiconductor pattern, the first semiconductor pattern serving as an active layer of the thin film transistor;
  • the manufacturing method further includes: before the forming the semiconductor layer pattern,
  • the first electrode, the PIN layer and the second electrode of the photosensitive sensor are sequentially formed on the substrate, wherein the connecting electrode is overlapped on the second electrode.
  • the manufacturing method further includes: after sequentially forming the first electrode, the PIN layer, and the second electrode of the photosensitive sensor on the substrate,
  • a through hole penetrating the gate insulating layer is opened on the part of the gate insulating layer
  • the connecting electrode is in contact with the second electrode through the through hole.
  • the connecting electrode is a transparent electrode.
  • the manufacturing method further includes: before forming the semiconductor layer pattern,
  • the first electrode and the PIN layer of the photosensitive sensor are sequentially formed on the substrate, wherein the connecting electrode is a transparent electrode, which is multiplexed as the second electrode of the photosensitive sensor.
  • a part of the connecting electrode is located on a surface of the PIN layer away from the first electrode.
  • the connecting electrode is multiplexed as the first electrode of the photosensitive sensor.
  • the manufacturing method further includes: before forming the semiconductor layer pattern,
  • a gate metal layer pattern is formed, and the gate metal layer pattern includes the gate of the thin film transistor and the first electrode of the photosensitive sensor.
  • the manufacturing method further includes: after forming the semiconductor layer pattern,
  • the source-drain metal layer pattern includes only a source electrode, and the connecting electrode is connected to the active layer and is multiplexed as the drain electrode of the thin film transistor;
  • the source-drain metal layer pattern includes a source electrode and a drain electrode, and the connection electrode is connected to the active layer and the drain electrode respectively;
  • a source-drain metal layer pattern is formed, the source-drain metal layer pattern includes a source electrode and a drain electrode, the connection electrode is separated from the active layer, and the drain electrode is connected to the connection electrode.
  • Figure 1 is a schematic diagram of an equivalent circuit of a fingerprint recognition module in the related art
  • FIG. 2 is a schematic flowchart of a method for manufacturing a fingerprint identification module according to an embodiment of the disclosure
  • FIG. 3 is a schematic structural diagram of a fingerprint recognition module in some embodiments of the disclosure.
  • FIG. 4 is a schematic structural diagram of another fingerprint identification module in some embodiments of the disclosure.
  • FIG. 5 is a schematic structural diagram of yet another fingerprint identification module in some embodiments of the present disclosure.
  • FIG. 6 is a schematic structural diagram of yet another fingerprint identification module in some embodiments of the present disclosure.
  • FIGS. 7A-7G are schematic flowcharts of a manufacturing method of a fingerprint recognition module in some embodiments of the present disclosure.
  • FIGS. 8A-8B are schematic flowcharts of another method for manufacturing a fingerprint recognition module in some embodiments of the present disclosure.
  • FIG. 9 is a schematic structural diagram of yet another fingerprint identification module in some embodiments of the present disclosure.
  • the fingerprint recognition module generally includes a thin film transistor (TFT) and a photosensitive sensor.
  • TFT thin film transistor
  • Figure 1 is a schematic diagram of the equivalent circuit of the fingerprint identification module.
  • the fingerprint identification module includes a thin film transistor 11 and a photosensitive sensor 12.
  • the gate of the thin film transistor 11 is connected to a control line.
  • the control line is used to control the thin film transistor
  • the thin film transistor 11 is turned on, the source of the thin film transistor 11 is connected to the data line, the drain is connected to the upper electrode of the photosensitive sensor 12, and the lower electrode of the photosensitive sensor 12 is connected to the reference voltage REF.
  • the reading line reads the current generated by the photosensitive sensor 12, and recognizes the fingerprint according to the magnitude of the current.
  • the photosensitive sensor 12 may be a PIN diode.
  • the thin film transistor and the photosensitive sensor need to be connected by a connecting electrode, and the manufacturing of the connecting electrode usually requires a separate masking process, resulting in an excessive number of masks used, which is not conducive to reducing the manufacturing cost of the fingerprint recognition module.
  • An embodiment of the present disclosure provides a method for manufacturing a fingerprint recognition module, the fingerprint recognition module including a thin film transistor and a photosensitive sensor, and the manufacturing method includes:
  • Step S11 forming a semiconductor layer pattern, the semiconductor layer pattern includes a first semiconductor pattern and a second semiconductor pattern, and the first semiconductor pattern serves as an active layer of the thin film transistor;
  • Step S12 Conducting a conductive process on the second semiconductor pattern to form a connecting electrode, where the connecting electrode is used to connect the thin film transistor and the photosensitive sensor.
  • the first semiconductor pattern as the active layer of the thin film transistor and the second semiconductor pattern for forming the connection electrode are formed at the same time through one patterning process, thereby reducing the number of masks of the fingerprint recognition module ,reduce manufacturing cost.
  • the method includes:
  • Step S0a forming the lower electrode, the PIN layer and the upper electrode of the photosensitive sensor, wherein the connecting electrode is overlapped on the upper electrode.
  • the bottom electrode 102a, the PIN layer 103, and the top electrode 104 of the photosensitive sensor are formed first, and then the active layer 106a and the connecting electrode 106b of the thin film transistor are formed, and the connecting electrode 106b overlaps Connected to the upper electrode 104 for connecting the thin film transistor and the photosensitive sensor.
  • the thin film transistor is usually formed first, and then the photosensitive sensor is formed.
  • the photosensitive sensor In the process of forming the photosensitive sensor, it is likely to cause damage to the active layer of the thin film transistor, thereby causing damage to the thin film transistor. The characteristics have an impact.
  • the photosensitive sensor when the fingerprint recognition module is manufactured, the photosensitive sensor is formed first, and then the active layer of the thin film transistor is formed, so as to avoid damage to the active layer and the like caused by the formation of the photosensitive sensor.
  • the shielding metal layer shields the thin film transistor, it also shields part of the photosensitive sensor, so that the photosensitive sensor is The light-receiving area is reduced, so that the current of the photosensitive sensor is reduced, which affects the sensitivity of the fingerprint recognition module.
  • the semiconductor layer pattern is formed of a transparent semiconductor material, so that the formed connecting electrode is a transparent electrode. Even if the connecting electrode overlaps the upper electrode of the photosensitive sensor, it will not affect the photosensitive sensor. The light-receiving area.
  • the transparent semiconductor material is a metal oxide semiconductor material, and the metal oxide semiconductor is used as an active layer, which can effectively improve the characteristics of the thin film transistor.
  • the connecting electrode is a transparent electrode, which is multiplexed as the upper electrode of the photosensitive sensor, that is, before the formation of the semiconductor layer pattern, the method includes:
  • Step S0b forming the lower electrode and the PIN layer of the photosensitive sensor, wherein the connecting electrode is a transparent electrode, which is multiplexed as the upper electrode of the photosensitive sensor.
  • the bottom electrode 202a and the PIN layer 203 of the photosensitive sensor are formed first, and then the active layer 205a and the connection electrode 205b of the thin film transistor are formed.
  • the connection electrode 205b is multiplexed as the The upper electrode of the photosensitive sensor.
  • the semiconductor layer pattern adopts a transparent metal oxide semiconductor material, and the metal oxide semiconductor is used as the active layer, which can effectively improve the characteristics of the thin film transistor.
  • the bottom electrode and the PIN layer of the photosensitive sensor are formed first, and then the active layer of the thin film transistor and the connecting electrode multiplexed as the upper electrode of the photosensitive sensor are formed.
  • the formation process of the sensor causes damage to the active layer, etc., while reducing the masking process of separately fabricating the upper electrode of the photosensitive sensor, thereby reducing the number of masks of the fingerprint identification module, reducing the production cost, and also reducing fingerprint identification The thickness of the module.
  • the connecting electrode is overlapped on the upper electrode of the photosensitive sensor, or multiplexed as the upper electrode of the photosensitive sensor.
  • the connecting electrode may also be connected to the lower electrode of the photosensitive sensor. Or, it can be multiplexed as the lower electrode of the photosensitive sensor, which will be described separately below.
  • the connecting electrode is multiplexed as the lower electrode of the photosensitive sensor.
  • the connecting electrode 303b is multiplexed as the lower electrode of the photosensitive sensor.
  • the connecting electrode is multiplexed as the bottom electrode of the photosensitive sensor, which reduces the masking process of separately manufacturing the bottom electrode of the photosensitive sensor, reduces the number of masks of the fingerprint recognition module, and can also reduce the fingerprint recognition module.
  • the thickness of the group is multiplexed as the bottom electrode of the photosensitive sensor, which reduces the masking process of separately manufacturing the bottom electrode of the photosensitive sensor, reduces the number of masks of the fingerprint recognition module, and can also reduce the fingerprint recognition module.
  • the connecting electrode may not be multiplexed as the lower electrode of the photosensitive sensor, but is arranged and connected to the lower electrode of the photosensitive sensor in the same layer. Under this structure, the thickness of the fingerprint identification module can also be reduced.
  • the method includes:
  • Step S0c forming a gate metal layer pattern, the gate metal layer pattern including the gate of the thin film transistor and the bottom electrode of the photosensitive sensor.
  • the gate 102b of the thin film transistor and the bottom electrode 102a of the photosensitive sensor are arranged in the same layer and the same material, and are formed by a patterning process.
  • the gate 202b of the thin film transistor and the lower electrode 202a of the photosensitive sensor are arranged in the same layer and the same material, and are formed by one patterning process.
  • the gate 502b of the thin film transistor and the bottom electrode 502a of the photosensitive sensor are arranged in the same layer and the same material, and are formed by a patterning process.
  • the gate of the thin film transistor and the bottom electrode of the photosensitive sensor are formed by a patterning process, thereby further reducing the number of masks used in making the fingerprint recognition module and helping to reduce the thickness of the fingerprint recognition module.
  • the method further includes:
  • Step S13a forming a source-drain metal layer pattern, the source-drain metal layer pattern includes only a source electrode, and the connecting electrode is connected to the active layer and is multiplexed as the drain electrode of the thin film transistor.
  • connection electrode 106b is multiplexed as the drain of the thin film transistor.
  • the connecting electrode 205b is simultaneously multiplexed as the drain electrode of the thin film transistor and the upper electrode of the photosensitive sensor.
  • the connecting electrode 303b is simultaneously multiplexed as the drain electrode of the thin film transistor and the lower electrode of the photosensitive sensor.
  • the method further includes:
  • Step S13b forming a source-drain metal layer pattern, the source-drain metal layer pattern includes a source electrode and a drain electrode, and the connecting electrode is connected to the active layer and the drain electrode, respectively.
  • the source-drain metal layer pattern includes a source electrode 507a and a drain electrode 507b, and the connecting electrode 506b is connected to the active layer 506a and the drain electrode 507b, respectively.
  • the resistance of the drain can be reduced.
  • the active layer of the thin film transistor may not be connected to the connection electrode, and the connection electrode is connected to the drain.
  • the method further includes:
  • Step S13c forming a source-drain metal layer pattern, the source-drain metal layer pattern includes a source electrode and a drain electrode, the connection electrode is separated from the active layer, and the drain electrode is connected to the connection electrode.
  • the connection electrode can be separated from the active layer by an insulating structure 509.
  • the semiconductor layer pattern adopts a metal oxide semiconductor, such as IGZO (Indium Gallium Zinc Oxide), ITZO (Indium Tin Zinc Oxide, Indium Tin Zinc Oxide), IZO (Indium Zinc Oxide, indium zinc oxide), etc., to improve the performance of thin film transistors.
  • IGZO Indium Gallium Zinc Oxide
  • ITZO Indium Tin Zinc Oxide, Indium Tin Zinc Oxide
  • IZO Indium Zinc Oxide, indium zinc oxide
  • the conductorization method may use NH3, H2, etc. to perform plasma (Plasma) treatment on the semiconductor pattern, or perform ion doping on the semiconductor pattern.
  • the manufacturing method of the fingerprint identification module in the embodiment of the present disclosure is described below with an example.
  • a method for manufacturing a fingerprint recognition module includes the following steps:
  • Step S21 forming a gate metal layer on the substrate 101 and patterning it to form the gate 102b of the thin film transistor and the lower electrode 102a of the photosensitive sensor, as shown in FIG. 7A.
  • the substrate may be a glass substrate or a flexible PI (Polyimide, polyimide) substrate
  • the gate metal may be Al, Mo, AlNd, Cu, MoNb, etc.
  • This step uses a mask (Mask 1).
  • Step S22 a PIN process is prepared and patterned on the lower electrode 102a to form the PIN layer 103 and the upper electrode 104 of the photosensitive sensor, as shown in FIG. 7B.
  • the PIN layer 103 may include an intrinsic amorphous silicon layer and a P-doped amorphous silicon layer, where the thickness of the intrinsic amorphous silicon layer may be 600-1200 nm, and the thickness of the P-doped amorphous silicon layer may be 10- 100nm.
  • the upper electrode 104 may be a transparent metal oxide such as ITO (Indium Tin Oxide), and the thickness may be 20-80 nm.
  • This step uses 2 masks (mask 2-3).
  • Step S23 deposit a gate insulating layer (GI layer) and punch holes above the upper electrode 104, as shown in FIG. 7C.
  • GI layer gate insulating layer
  • the gate insulating layer may be SiO2, or a combined film layer of SiNx and SiO2, and the thickness may be 200-400 nm.
  • This step uses a mask (mask 4).
  • Step S24 forming a semiconductor layer pattern 106, the semiconductor layer pattern 106 includes: a first semiconductor pattern 106a and a second semiconductor pattern 106b', wherein the first semiconductor pattern 106a serves as the active layer of the thin film transistor, as shown in FIG. 7D .
  • the semiconductor layer pattern 106 can be formed of IGZO, ITZO, IZO and other metal oxide semiconductor materials.
  • IGZO can be used, which can be in an amorphous state or a crystalline state or a laminated structure of the two, and the thickness can be 30-70nm .
  • This step uses a mask (Mask 5).
  • Step S25 Conduct a conductive process on the second semiconductor pattern 1062 to form a connecting electrode 106b, as shown in FIG. 7E.
  • the conductive method can use NH3, H2, etc. to perform plasma (Plasma) treatment on the semiconductor pattern, or perform ion doping on the semiconductor pattern.
  • Plasma plasma
  • This step uses a mask (mask 6).
  • Step S26 forming a source-drain metal layer pattern, the source-drain metal layer pattern includes only the source electrode 107, and the source-drain metal layer pattern is not formed on the connection electrode 106b, as shown in FIG. 7F.
  • the source and drain metal may be Al, Mo, AlNd, Cu, MoNb, etc., or a combination of any two or more of the foregoing metals, and the thickness of the source and drain metal layer may be 300-500 nm.
  • This step uses a mask (mask 7).
  • Step S27 forming a passivation protection (PVX) layer 108, as shown in FIG. 7G.
  • PVX passivation protection
  • the PVX layer can use SiO2, or SiON, or a combination of SiO2 and SiON, and the thickness can be
  • another method for manufacturing a fingerprint recognition module includes the following steps:
  • Step S31-Step S35 The same as the steps S21-S25 in the first implementation, and will not be described one by one.
  • Step S36 forming a source-drain metal layer pattern, where the source-drain metal layer pattern only includes the source electrode 507a and the drain electrode 507b, as shown in FIG. 8A.
  • the source and drain metal may be Al, Mo, AlNd, Cu, MoNb, etc., or a combination of any two or more of the foregoing metals, and the thickness of the source and drain metal layer may be 300-500 nm.
  • the drain electrode 507b is formed on the connecting electrode 506b to reduce its resistance.
  • Step S37 forming a passivation protection (PVX) layer 508, as shown in FIG. 8B.
  • PVX passivation protection
  • the PVX layer can be made of SiO2, or SiON, or a combination of SiO2 and SiON, with a thickness of
  • the first semiconductor pattern as the active layer of the thin film transistor and the second semiconductor pattern for forming the connection electrode are formed simultaneously through one patterning process, thereby reducing the masking of the fingerprint recognition module.
  • the number of films is reduced, and the production cost is reduced; and the photosensitive sensor is made first, and then the gate insulating layer, active layer, source and drain metal pattern, and PVX process related to the thin film transistor are carried out to reduce the influence of the photosensitive sensor process on the characteristics of the thin film transistor.
  • the embodiment of the present disclosure also provides a fingerprint identification module, including:
  • the thin film transistor includes an active layer
  • the active layer and the connecting electrode are formed by the same semiconductor layer pattern, the semiconductor layer pattern includes a first semiconductor pattern and a second semiconductor pattern, the first semiconductor pattern serves as the active layer, the The connecting electrode is obtained by conducting a conductive process on the second semiconductor pattern.
  • the active layer as the thin film transistor and the semiconductor pattern used to form the connecting electrode can be formed at the same time through a patterning process, thereby reducing the number of masks used in making the fingerprint recognition module and reducing the production cost .
  • the photosensitive sensor includes: a lower electrode, a PIN layer and an upper electrode, wherein the connecting electrode is overlapped on the upper electrode.
  • the semiconductor layer pattern is formed of a transparent semiconductor material, so that the formed connecting electrode is a transparent electrode. Even if the connecting electrode overlaps the upper electrode of the photosensitive sensor, it will not affect the light-receiving area of the photosensitive sensor.
  • the transparent semiconductor material is a metal oxide semiconductor material, and the metal oxide semiconductor is used as an active layer, which can effectively improve the characteristics of the thin film transistor.
  • the fingerprint identification module includes:
  • Substrate 101 the substrate can use a glass substrate or a flexible PI (polyimide) substrate;
  • the gate metal layer pattern, the gate metal layer pattern includes the gate 102b of the thin film transistor and the lower electrode 102a of the photosensitive sensor; the gate metal can be Al, Mo, AlNd, Cu, MoNb, etc.;
  • PIN layer 103 can include an intrinsic amorphous silicon layer and a P-doped amorphous silicon layer, where the thickness of the intrinsic amorphous silicon layer can be 600-1200 nm, and the thickness of the P-doped amorphous silicon layer can be 10 ⁇ 100nm;
  • the upper electrode 104; the upper electrode 104 can be a transparent metal oxide such as ITO, and the thickness can be 20 to 80 nm;
  • the gate insulating layer 105 is provided with a through hole on the gate insulating layer 105, and the through hole is located above the upper electrode 104;
  • the gate insulating layer may be SiO2, or a combined film of SiNx and SiO2, and the thickness may be 200-400nm;
  • the active layer 106a and the connecting electrode 106b, the active layer 106a and the connecting electrode 106b are formed by the same semiconductor layer pattern, the semiconductor layer pattern includes a first semiconductor pattern and a second semiconductor pattern, the first A semiconductor pattern is used as the active layer 106a, the connecting electrode 106b is obtained by conducting a conductive process on the second semiconductor pattern, and the connecting electrode 106b is connected to the photosensitive sensor through the through hole on the gate insulating layer 105
  • the connecting electrode 106 is a transparent electrode;
  • the semiconductor layer pattern can be formed of metal oxide semiconductor materials such as IGZO, ITZO, IZO, etc.
  • IGZO can be used, which can be in an amorphous state or a crystalline state Or a laminated structure of the two, the thickness can be 30-70nm;
  • the source-drain metal layer pattern, the source-drain metal layer pattern includes the source electrode 107;
  • the source-drain metal can be Al, Mo, AlNd, Cu, MoNb, etc., or a combination of any two or more of the above metals, the source and drain
  • the thickness of the metal layer can be 300-500nm;
  • PVX layer 108 can use SiO2, or SiON, or a combination of SiO2 and SiON, and the thickness can be
  • the connecting electrode is a transparent electrode, which is multiplexed as the upper electrode of the photosensitive sensor.
  • the semiconductor layer pattern adopts a transparent metal oxide semiconductor material, and the metal oxide semiconductor is used as the active layer, which can effectively improve the characteristics of the thin film transistor.
  • the fingerprint identification module includes:
  • Substrate 201 the substrate can use a glass substrate or a flexible PI (polyimide) substrate;
  • Gate metal layer pattern includes the gate 202b of the thin film transistor and the lower electrode 202a of the photosensitive sensor; the gate metal can be Al, Mo, AlNd, Cu, MoNb, etc.;
  • PIN layer 203 can include an intrinsic amorphous silicon layer and a P-doped amorphous silicon layer, where the thickness of the intrinsic amorphous silicon layer can be 600-1200 nm, and the thickness of the P-doped amorphous silicon layer can be 10 ⁇ 100nm;
  • the gate insulating layer 204 is provided with a through hole on the gate insulating layer 204, and the through hole is located above the PIN layer 203;
  • the gate insulating layer 204 can be made of SiO2, or a combined film of SiNx and SiO2, and the thickness can be 200-400nm;
  • the active layer 205a and the connection electrode 205b, the active layer 205a and the connection electrode 205b are formed by the same semiconductor layer pattern, the semiconductor layer pattern includes a first semiconductor pattern and a second semiconductor pattern, the first The semiconductor pattern is used as the active layer 205a, the connecting electrode 205b is obtained by conducting a conductive process on the second semiconductor pattern, and the connecting electrode 205b is a transparent electrode, which is multiplexed as the upper electrode of the photosensitive sensor;
  • the semiconductor layer pattern It can be formed of metal oxide semiconductor materials such as IGZO, ITZO, IZO, etc., optionally, IGZO can be used in an amorphous or crystalline state or a laminated structure of the two, and the thickness can be 30-70 nm;
  • the source-drain metal layer pattern, the source-drain metal layer pattern includes the source electrode 206;
  • the source-drain metal can be Al, Mo, AlNd, Cu, MoNb, etc., or a combination of any two or more of the above metals, the source and drain
  • the thickness of the metal layer can be 300-500nm;
  • PVX layer 207 can use SiO2, or SiON, or a combination of SiO2 and SiON, and the thickness can be
  • the connecting electrode is overlapped on the upper electrode of the photosensitive sensor, or multiplexed as the upper electrode of the photosensitive sensor.
  • the connecting electrode may also be connected to the lower electrode of the photosensitive sensor. Or, it can be multiplexed as the lower electrode of the photosensitive sensor, which will be described separately below.
  • the connecting electrode is multiplexed as the lower electrode of the photosensitive sensor.
  • the fingerprint identification module includes:
  • the substrate 301 can use a glass substrate or a flexible PI (polyimide) substrate;
  • the active layer 303a, the connection electrode 303b, and the source connection region 303c are formed by the same semiconductor layer pattern, and the semiconductor layer pattern includes the first semiconductor pattern , A second semiconductor pattern and a third semiconductor pattern, the first semiconductor pattern is used as the active layer 303a, the connecting electrode 303b is obtained by conducting a conductive process on the second semiconductor pattern, and the source connecting region 303c is The third semiconductor pattern is obtained by conducting a conductive process.
  • the connecting electrode 303b is multiplexed as the drain electrode of the thin film transistor and the lower electrode of the photosensitive sensor;
  • the semiconductor layer pattern can be formed of metal oxide semiconductor materials such as IGZO, ITZO, IZO, etc., optionally, IGZO can be used, which can be in an amorphous state It can also be in a crystalline state or a laminated structure of the two, and the thickness can be 30-70nm;
  • PIN layer 304 may include an intrinsic amorphous silicon layer and a P-doped amorphous silicon layer, where the thickness of the intrinsic amorphous silicon layer may be 600-1200 nm, and the thickness of the P-doped amorphous silicon layer may 10 ⁇ 100nm;
  • the upper electrode 305; the upper electrode 305 can be a transparent metal oxide such as ITO, and the thickness can be 20 to 80 nm;
  • the gate insulating layer 306 is provided with a through hole on the gate insulating layer 306, and the through hole is located above the upper electrode 305;
  • the gate insulating layer may be SiO2, or a combined film of SiNx and SiO2, and the thickness may be 200-400nm;
  • the gate metal layer pattern, the gate metal layer pattern includes the gate 307 of the thin film transistor; the gate metal can be Al, Mo, AlNd, Cu, MoNb, etc.;
  • Interlayer dielectric layer (ILD) 308 the interlayer dielectric layer 308 is provided with a through hole, the through hole is located above the through hole of the gate insulating layer 306, and is connected to the through hole on the gate insulating layer 306;
  • the first connecting portion 309 is connected to the upper electrode 305 through the through holes on the interlayer dielectric layer 308 and the gate insulating layer 306;
  • the source-drain metal layer pattern includes a source electrode 310a and a second connecting portion 310b; the source-drain metal layer may be Al, Mo, AlNd, Cu, MoNb, etc., or any two or more of the above metals
  • the thickness of the source and drain metal layers can be 300-500nm; in some embodiments of the present disclosure, the first connection portion 309 may not be included, and the second connection portion 310b is directly insulated by the interlayer dielectric layer 308 and the gate.
  • the through hole on the layer 306 is connected to the upper electrode 305;
  • PVX layer 311 can use SiO2, or SiON, or a combination of SiO2 and SiON, and the thickness can be
  • the connecting electrode is multiplexed as the bottom electrode of the photosensitive sensor, which reduces the masking process of separately manufacturing the bottom electrode of the photosensitive sensor, reduces the number of masks of the fingerprint recognition module, and can also reduce the fingerprint recognition module.
  • the thickness of the group is multiplexed as the bottom electrode of the photosensitive sensor, which reduces the masking process of separately manufacturing the bottom electrode of the photosensitive sensor, reduces the number of masks of the fingerprint recognition module, and can also reduce the fingerprint recognition module.
  • the connecting electrode may not be multiplexed as the lower electrode of the photosensitive sensor, but is arranged and connected to the lower electrode of the photosensitive sensor in the same layer. Under this structure, the thickness of the fingerprint identification module can also be reduced.
  • the thin film transistor includes a gate, and the gate and the bottom electrode of the photosensitive sensor are arranged in the same layer and the same material.
  • the gate 102b of the thin film transistor and the lower electrode 102a of the photosensitive sensor are arranged in the same layer and the same material, and are formed by one patterning process.
  • the gate 202b of the thin film transistor and the lower electrode 202a of the photosensitive sensor are arranged in the same layer and the same material, and are formed by one patterning process.
  • the gate 502b of the thin film transistor and the bottom electrode 502a of the photosensitive sensor are arranged in the same layer and the same material, and are formed by a patterning process.
  • the gate of the thin film transistor and the bottom electrode of the photosensitive sensor are formed by a patterning process, thereby further reducing the number of masks used in making the fingerprint recognition module and helping to reduce the thickness of the fingerprint recognition module.
  • connection electrode is connected to the active layer and is multiplexed as the drain of the thin film transistor. Please refer to FIG. 3, FIG. 4 and FIG. 5.
  • the connection electrode 106b is multiplexed as the drain of the thin film transistor.
  • the connecting electrode 205b is simultaneously multiplexed as the drain electrode of the thin film transistor and the upper electrode of the photosensitive sensor.
  • the connecting electrode 303b is simultaneously multiplexed as the drain electrode of the thin film transistor and the lower electrode of the photosensitive sensor.
  • connection electrode is respectively connected to the active layer and the drain electrode of the thin film transistor.
  • the source-drain metal layer pattern includes a source electrode 507a and a drain electrode 507b, and the connecting electrode 506b is connected to the active layer 506a and the drain electrode 507b, respectively. This structure can reduce the resistance of the drain.
  • connection electrode is separated from the active layer, and the drain electrode of the thin film transistor is connected to the connection electrode.
  • the semiconductor layer pattern adopts a metal oxide semiconductor, such as IGZO (Indium Gallium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), IZO (Indium Zinc Oxide), etc., to improve The performance of thin film transistors.
  • IGZO Indium Gallium Zinc Oxide
  • ITZO Indium Tin Zinc Oxide
  • IZO Indium Zinc Oxide
  • the embodiments of the present disclosure also provide a display substrate, which includes the fingerprint identification module in any of the above embodiments.
  • the embodiment of the present disclosure also provides a display device, including the above-mentioned display substrate.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Multimedia (AREA)
  • Human Computer Interaction (AREA)
  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Thin Film Transistor (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

一种指纹识别模组及其制作方法、显示基板和显示装置。所述指纹识别模组，包括薄膜晶体管（11）、光敏传感器（12）和连接电极（106b），所述连接电极（106b）用于连接所述薄膜晶体管（11）和所述光敏传感器（12）；所述薄膜晶体管（11）包括有源层（106a）；所述有源层（106a）和所述连接电极（106b）是由同一层半导体层图形（106）形成，所述半导体层图形（106）包括第一半导体图形（106a）和第二半导体图形（106b'），所述第一半导体图形（106a）作为所述有源层（106a），经导体化处理后的所述第二半导体图形（106b'）作为所述连接电极（106b）。

Description

指纹识别模组及其制作方法、显示基板和显示装置
相关申请的交叉引用
本公开主张在2020年2月18日在中国提交的中国专利申请No.202010098804.5的优先权，其全部内容通过引用包含于此。
技术领域
本公开实施例涉及显示技术领域，尤其涉及一种指纹识别模组及其制作方法、显示基板和显示装置。
背景技术
随着全面屏逐渐进入市场，相应的全屏指纹识别及触控技术需求也非常迫切。
相关技术中，在制作相关的指纹识别模组时，使用了的掩膜(mask)数量超过10个，制作流程较为复杂，制作成本较高。
发明内容
本公开实施例提供一种指纹识别模组及其制作方法、显示基板和显示装置。
第一方面，本公开实施例提供了一种指纹识别模组，包括：
薄膜晶体管、光敏传感器和连接电极，所述连接电极用于连接所述薄膜晶体管和所述光敏传感器；
所述薄膜晶体管包括有源层；
所述有源层和所述连接电极是由同一层半导体层图形形成，所述半导体层图形包括第一半导体图形和第二半导体图形，所述第一半导体图形作为所述有源层，经导体化处理后的所述第二半导体图形作为所述连接电极。
可选地，所述光敏传感器包括：在基板上依次层叠设置的第一电极、PIN层和第二电极，其中，所述连接电极搭接在所述第二电极上。
可选地，所述的指纹识别模组还包括：
栅绝缘层，其中所述栅绝缘层的一部分覆盖在所述第二电极的远离所述第一电极的表面上；以及
在所述栅绝缘层的该一部分上开设的通孔，其中所述通孔贯穿所述栅绝缘层，
其中，所述连接电极通过所述通孔与所述第二电极相接触。
可选地，所述连接电极为透明电极。
可选地，所述光敏传感器包括在基板上依次层叠设置的第一电极和PIN层，所述连接电极为透明电极，复用为所述光敏传感器的第二电极。
可选地，所述连接电极的一部分位于所述PIN层的远离第一电极的表面上。
可选地，所述连接电极复用为所述光敏传感器的第二电极。
可选地，所述薄膜晶体管包括栅极，所述栅极和所述光敏传感器的第一电极同层同材料设置。
可选地，所述连接电极与所述有源层连接，复用为所述薄膜晶体管的漏极；或者
所述连接电极分别与所述有源层和所述薄膜晶体管的漏极连接；或者
所述连接电极与所述有源层分离，所述薄膜晶体管的漏极与所述连接电极连接。
第二方面，本公开实施例提供了一种显示基板，包括上述的指纹识别模组。
第三方面，本公开实施例提供了一种显示装置，包括上述的显示基板。
第四方面，本公开实施例提供了一种指纹识别模组的制作方法，所述指纹识别模组包括薄膜晶体管和光敏传感器，所述制作方法包括：
通过一次构图工艺形成半导体层图形，所述半导体层图形包括第一半导体图形和第二半导体图形，所述第一半导体图形作为所述薄膜晶体管的有源层；
对所述第二半导体图形进行导体化处理形成连接电极，所述连接电极用于连接所述薄膜晶体管和所述光敏传感器。
可选地，所述制作方法还包括：在所述形成半导体层图形之前，
在基板上依次形成所述光敏传感器的第一电极、PIN层和第二电极，其中，所述连接电极搭接在所述第二电极上。
可选地，所述的制作方法还包括：在基板上依次形成所述光敏传感器的第一电极、PIN层和第二电极之后，
形成栅绝缘层，其中，所述栅绝缘层的一部分覆盖在所述第二电极的远离所述第一电极的表面上；
在所述栅绝缘层的该一部分上开设贯穿所述栅绝缘层的通孔，
其中，所述连接电极通过所述通孔与所述第二电极相接触。
可选地，所述连接电极为透明电极。
可选地，所述的制作方法还包括：所述形成半导体层图形之前，
在基板上依次形成所述光敏传感器的第一电极和PIN层，其中，所述连接电极为透明电极，复用为所述光敏传感器的第二电极。
可选地，所述连接电极的一部分位于所述PIN层的远离第一电极的表面上。
可选地，所述连接电极复用为所述光敏传感器的第一电极。
可选地，所述制作方法还包括：所述形成半导体层图形之前，
形成栅金属层图形，所述栅金属层图形包括所述薄膜晶体管的栅极和所述光敏传感器的第一电极。
可选地，所述制作方法还包括：所述形成半导体层图形之后，
形成源漏金属层图形，所述源漏金属层图形仅包括源极，所述连接电极与所述有源层连接，复用为所述薄膜晶体管的漏极；
或者
形成源漏金属层图形，所述源漏金属层图形包括源极和漏极，所述连接电极分别与所述有源层和所述漏极连接；
或者
形成源漏金属层图形，所述源漏金属层图形包括源极和漏极，所述连接电极与所述有源层分离，所述漏极与所述连接电极连接。
附图说明
通过阅读下文可选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出可选实施方式的目的，而并不认为是对本公开的限制。而且在整个附图中，用相同的参考符号表示相同的部件。在附图中：
图1为相关技术中的指纹识别模组的等效电路示意图；
图2为本公开实施例的指纹识别模组的制作方法的流程示意图；
图3为本公开一些实施例中的一种指纹识别模组的结构示意图；
图4为本公开一些实施例中的另一种指纹识别模组的结构示意图；
图5为本公开一些实施例中的又一种指纹识别模组的结构示意图；
图6为本公开一些实施例中的又一种指纹识别模组的结构示意图；
图7A-图7G为本公开一些实施例中的一种指纹识别模组的制作方法的流程示意图；
图8A-图8B为本公开一些实施例中的另一种指纹识别模组的制作方法的流程示意图；
图9为本公开一些实施例中的又一种指纹识别模组的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
相关技术中，指纹识别模组一般包含薄膜晶体管(TFT)和光敏传感器。请参考图1，图1为指纹识别模组的等效电路示意图，指纹识别模组包括薄膜晶体管11和光敏传感器12，薄膜晶体管11的栅极与控制线连接，控制线用于控制薄膜晶体管的开启，薄膜晶体管11的源极与数据线连接，漏极与光敏传感器12的上电极连接，光敏传感器12的下电极与参考电压REF连接，当控制线输出的信号控制薄膜晶体管开启时，通过数据读取线读取光敏传感器12产生的电流，根据电流的大小识别指纹。可选地，所述光敏传感器12可以为PIN二极管。
相关技术中，薄膜晶体管和光敏传感器之间需要采用连接电极进行连接，而制作连接电极通常需要单独的掩膜工艺，造成使用的掩膜数量过多，不利于减少指纹识别模组的制作成本。
为解决上述问题，请参考图2，本公开实施例提供了一种指纹识别模组的制作方法，所述指纹识别模组包括薄膜晶体管和光敏传感器，所述制作方法包括：
步骤S11：形成半导体层图形，所述半导体层图形包括第一半导体图形和第二半导体图形，所述第一半导体图形作为所述薄膜晶体管的有源层；
步骤S12：对所述第二半导体图形进行导体化处理形成连接电极，所述连接电极用于连接所述薄膜晶体管和所述光敏传感器。
本公开实施例中，通过一次构图工艺，同时形成作为薄膜晶体管的有源层的第一半导体图形，以及，用于形成连接电极的第二半导体图形，从而减少了指纹识别模组的掩膜数量，降低生产成本。
在本公开的一些实施例中，可选地，所述形成半导体层图形之前包括：
步骤S0a：形成所述光敏传感器的下电极、PIN层和上电极，其中，所述连接电极搭接在所述上电极上。
请参考图3，图3所示的实施例中，先形成光敏传感器的下电极102a、PIN层103和上电极104，然后再形成薄膜晶体管的有源层106a和连接电极106b，连接电极106b搭接在上电极104上，用于连接薄膜晶体管和光敏传感器。
相关技术中的指纹识别模组的制作过程中，通常是先形成薄膜晶体管，然后形成光敏传感器，在形成光敏传感器的过程中，很可能对薄膜晶体管的有源层等造成损伤，从而对薄膜晶体管的特性产生影响。
本公开实施例中，在制作指纹识别模组时，首先形成光敏传感器，然后再形成薄膜晶体管的有源层等膜层，从而避免光敏传感器的形成过程对有源层等造成损伤。
相关技术中，有通过薄膜晶体管的遮蔽金属(Shield Metal)层作为搭接电极连接光敏传感器与薄膜晶体管的方案，遮蔽金属层在遮蔽薄膜晶体管的同时，也会遮蔽部分光敏传感器，使得光敏传感器的受光面积减少，从而使 得光敏传感器的电流减小，影响指纹识别模组的敏感度。
上述实施例中，可选地，所述半导体层图形采用透明的半导体材料形成，从而使得形成的连接电极为透明电极，即使连接电极搭接在光敏传感器的上电极上，也不会影响光敏传感器的受光面积。
进一步可选地，所述透明的半导体材料为金属氧化物半导体材料，金属氧化物半导体作为有源层，可以有效提高薄膜晶体管的特性。
在本公开的另外一些实施例中，可选地，所述连接电极为透明电极，复用为所述光敏传感器的上电极，即所述形成半导体层图形之前包括：
步骤S0b：形成所述光敏传感器的下电极和PIN层，其中，所述连接电极为透明电极，复用为所述光敏传感器的上电极。
请参考图4，图4所示的实施例中，先形成光敏传感器的下电极202a和PIN层203，然后再形成薄膜晶体管的有源层205a和连接电极205b，连接电极205b复用为所述光敏传感器的上电极。
可选地，所述半导体层图形采用透明的金属氧化物半导体材料，金属氧化物半导体作为有源层，可以有效提高薄膜晶体管的特性。
本公开实施例中，在制作指纹识别模组时，首先形成光敏传感器的下电极和PIN层，然后再形成薄膜晶体管的有源层和复用为光敏传感器的上电极的连接电极，在避免光敏传感器的形成过程对有源层等造成损伤的同时，减少单独制作光敏传感器的上电极的掩膜工艺，从而减少了指纹识别模组的掩膜数量，降低了生产成本，并且还可以减少指纹识别模组的厚度。
上述实施例中，连接电极搭接在光敏传感器的上电极上，或者，复用为光敏传感器的上电极，在本公开的其他一些实施例中，连接电极也可以与光敏传感器的下电极连接，或者，复用为光敏传感器的下电极，下面分别进行说明。
在本公开的其他一些实施例中，可选地，所述连接电极复用为所述光敏传感器的下电极。
请参考图5，图5所示的实施例中，连接电极303b复用为光敏传感器的下电极。
本公开实施例中，连接电极复用为光敏传感器的下电极，减少了单独制 作光敏传感器的下电极的掩膜工艺，减少了指纹识别模组的掩膜数量，同时，还可以减少指纹识别模组的厚度。
在本公开的其他一些实施例中，所述连接电极也可以不复用为光敏传感器的下电极，而是与所述光敏传感器的下电极同层设置并连接。该种结构下，同样可以减少指纹识别模组的厚度。
在本公开的一些实施例中，可选地，所述形成半导体层图形之前包括：
步骤S0c：形成栅金属层图形，所述栅金属层图形包括所述薄膜晶体管的栅极和所述光敏传感器的下电极。
请参考图3、图4和图6，图3所示的实施例中，薄膜晶体管的栅极102b和光敏传感器的下电极102a同层同材料设置，通过一次构图工艺形成。图4所示的实施例中，薄膜晶体管的栅极202b和光敏传感器的下电极202a同层同材料设置，通过一次构图工艺形成。图6所示的实施例中，薄膜晶体管的栅极502b和光敏传感器的下电极502a同层同材料设置，通过一次构图工艺形成。
本公开实施例中，薄膜晶体管的栅极和光敏传感器的下电极通过一次构图工艺形成，从而进一步减少了制作指纹识别模组使用的掩膜数量，且有助于减少指纹识别模组的厚度。
在本公开的一些实施例中，所述形成半导体层图形之后还包括：
步骤S13a：形成源漏金属层图形，所述源漏金属层图形仅包括源极，所述连接电极与所述有源层连接，复用为所述薄膜晶体管的漏极。
请参考图3、图4和图5，图3所示的实施例中，连接电极106b复用为薄膜晶体管的漏极。图4所示的实施例中，连接电极205b同时复用为薄膜晶体管的漏极以及光敏传感器的上电极。图5所示的实施例中，连接电极303b同时复用为薄膜晶体管的漏极以及光敏传感器的下电极。
在本公开的一些实施例中，所述形成半导体层图形之后还包括：
步骤S13b：形成源漏金属层图形，所述源漏金属层图形包括源极和漏极，所述连接电极分别与所述有源层和所述漏极连接。
请参考图6，图6所示的实施例中，所述源漏金属层图形包括源极507a和漏极507b，连接电极506b分别与所述有源层506a和所述漏极507b连接。
本公开实施例中，可以减少漏极的电阻。
在本公开的其他一些实施例中，所述薄膜晶体管的有源层也可以不与所述连接电极连接，连接电极与漏极连接。
即，所述形成半导体层图形之后还包括：
步骤S13c：形成源漏金属层图形，所述源漏金属层图形包括源极和漏极，所述连接电极与所述有源层分离，所述漏极与所述连接电极连接。如图9所示，例如可以通过绝缘结构509将所述连接电极与所述有源层相分离。
本公开的上述实施例中，可选地，半导体层图形采用金属氧化物半导体，例如IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)，ITZO(Indium Tin Zinc Oxide，铟锡锌氧化物)，IZO(Indium Zinc Oxide，氧化铟锌)等，以提高薄膜晶体管的性能。
本公开的上述实施例中，导体化方法可以采用NH3、H2等对半导体图形进行等离子体(Plasma)处理，或者对半导体图形进行离子掺杂。
下面举例对本公开实施例中的指纹识别模组的制作方法进行说明。
在一些实施例中，一种指纹识别模组的制作方法包括以下步骤：
步骤S21：在基板101上制作栅金属层并图形化，形成薄膜晶体管的栅极102b和光敏传感器的下电极102a，如图7A所示。
本公开实施例中，基板可使用玻璃基板或者柔性PI(Polyimide，聚酰亚胺)基板，栅金属可以是Al，Mo，AlNd，Cu，MoNb等。
该步骤使用一张掩膜(掩膜1)。
步骤S22：在下电极102a上制备PIN工序并图形化，形成光敏传感器的PIN层103和上电极104，如图7B所示。
其中PIN层103可以包括本征非晶硅层和P掺杂非晶硅层，其中，本征非晶硅层的厚度可以为600～1200nm，P掺杂非晶硅层的厚度可以为10～100nm。上电极104可以采用透明金属氧化物例如ITO(氧化铟锡，Indium Tin Oxide)，厚度可以为20～80nm。
该步骤使用2张掩膜(掩膜2-3)。
步骤S23：进行栅绝缘层(GI层)的沉积并打孔至上电极104上方，如图7C所示。
栅绝缘层可以采用SiO2，或者，SiNx和SiO2组合膜层，厚度可以为200-400nm。
该步骤使用一张掩膜(掩膜4)。
步骤S24：形成半导体层图形106，所述半导体层图形106包括：第一半导体图形106a和第二半导体图形106b’，其中，第一半导体图形106a作为薄膜晶体管的有源层，如图7D所示。
半导体层图形106可以采用IGZO，ITZO，IZO等金属氧化物半导体材料形成，可选地，采用IGZO，可以为非晶状态也可以为结晶状态或是二者叠层结构，厚度可以为30-70nm。
该步骤使用一张掩膜(掩膜5)。
步骤S25：对第二半导体图形1062进行导体化处理，形成连接电极106b，如图7E所示。
导体化方法可以采用NH3、H2等对半导体图形进行等离子体(Plasma)处理，或者对半导体图形进行离子掺杂。
该步骤使用一张掩膜(掩膜6)。
步骤S26：形成源漏金属层图形，所述源漏金属层图形仅包括源极107，连接电极106b上不形成源漏金属层图形，如图7F所示。
源漏金属可以为Al，Mo，AlNd，Cu，MoNb等，或者上述金属中的任意两个或多个的组合，源漏金属层的厚度可以为300-500nm。
该步骤使用一张掩膜(掩膜7)。
步骤S27：形成钝化保护(PVX)层108，如图7G所示。
PVX层可以采用SiO2，或SiON，或SiO2和SiON的组合，厚度可以为
Figure PCTCN2021076187-appb-000001
在一些实施例中，另一种指纹识别模组的制作方法包括以下步骤：
步骤S31-步骤S35：与实施一中的步骤S21-S25相同，不再一一描述。
步骤S36：形成源漏金属层图形，所述源漏金属层图形仅包括源极507a和漏极507b，如图8A所示。
源漏金属可以为Al，Mo，AlNd，Cu，MoNb等，或者上述金属中的任意两个或多个的组合，源漏金属层的厚度可以为300-500nm。
本公开实施例中，在连接电极506b上制作漏极507b，可以降低其电阻。
步骤S37：形成钝化保护(PVX)层508，如图8B所示。
PVX层可以采用SiO2，或SiON，或SiO2和SiON的组合，厚度为
Figure PCTCN2021076187-appb-000002
本公开的上述实施例中，通过一次构图工艺，同时形成作为薄膜晶体管的有源层的第一半导体图形，以及，用于形成连接电极的第二半导体图形，从而减少了指纹识别模组的掩膜数量，降低生产成本；且，且先进行光敏传感器的制作，后进行与薄膜晶体管相关的栅绝缘层、有源层、源漏金属图形、PVX工艺，以减少光敏传感器工艺对薄膜晶体管特性的影响；采用透明的金属氧化物形成半导体层图形，从而使得形成的连接电极为透明电极，可以提高光敏传感器的受光面积；光敏传感器的底电极和薄膜晶体管的栅极共用同一层金属，减少膜层结构；采用7个掩膜的工艺，相比于相关技术工艺，工艺流程大大降低。
本公开实施例还提供一种指纹识别模组，包括：
薄膜晶体管、光敏传感器和连接电极，所述连接电极用于连接所述薄膜晶体管和所述光敏传感器；
所述薄膜晶体管包括有源层；
所述有源层和所述连接电极是由同一层半导体层图形形成，所述半导体层图形包括第一半导体图形和第二半导体图形，所述第一半导体图形作为所述有源层，所述连接电极是对所述第二半导体图形进行导体化处理得到。
本公开实施例中，可以通过一次构图工艺，同时形成作为薄膜晶体管的有源层，以及，用于形成连接电极的半导体图形，从而减少了制作指纹识别模组使用的掩膜数量，降低生产成本。
在本公开的一些实施例中，可选地，所述光敏传感器包括：下电极、PIN层和上电极，其中，所述连接电极搭接在所述上电极上。
可选地，所述半导体层图形采用透明的半导体材料形成，从而使得形成的连接电极为透明电极，即使连接电极搭接在光敏传感器的上电极上，也不会影响光敏传感器的受光面积。
进一步可选地，所述透明的半导体材料为金属氧化物半导体材料，金属 氧化物半导体作为有源层，可以有效提高薄膜晶体管的特性。
请参考图3，图3所示的实施例中，指纹识别模组包括：
基板101；基板可使用玻璃基板或者柔性PI(聚酰亚胺)基板；
栅金属层图形，所述栅金属层图形包括薄膜晶体管的栅极102b和光敏传感器的下电极102a；栅金属可以是Al，Mo，AlNd，Cu，MoNb等；
PIN层103；PIN层103可以包括本征非晶硅层和P掺杂非晶硅层，其中，本征非晶硅层的厚度可以为600～1200nm，P掺杂非晶硅层的厚度可以为10～100nm；
上电极104；上电极104可以采用透明金属氧化物例如ITO，厚度可以为20～80nm；
栅绝缘层105，栅绝缘层105上开设有通孔，通孔位于上电极104上方；栅绝缘层可以采用SiO2，或者，SiNx和SiO2组合膜层，厚度可以为200-400nm；
有源层106a和连接电极106b，所述有源层106a和所述连接电极106b是由同一层半导体层图形形成，所述半导体层图形包括第一半导体图形和第二半导体图形，所述第一半导体图形作为所述有源层106a，所述连接电极106b是对所述第二半导体图形进行导体化处理得到，所述连接电极106b通过所述栅绝缘层105上的通孔搭接在光敏传感器的上电极104上，所述连接电极106为透明电极；半导体层图形可以采用IGZO，ITZO，IZO等金属氧化物半导体材料形成，可选地，采用IGZO，可以为非晶状态也可以为结晶状态或是二者叠层结构，厚度可以为30-70nm；
源漏金属层图形，所述源漏金属层图形包括源极107；源漏金属可以为Al，Mo，AlNd，Cu，MoNb等，或者上述金属中的任意两个或多个的组合，源漏金属层的厚度可以为300-500nm；
PVX层108；PVX层108可以采用SiO2，或SiON，或SiO2和SiON的组合，厚度可以为
Figure PCTCN2021076187-appb-000003
在本公开的另外一些实施例中，可选地，所述连接电极为透明电极，复用为所述光敏传感器的上电极。
可选地，所述半导体层图形采用透明的金属氧化物半导体材料，金属氧化物半导体作为有源层，可以有效提高薄膜晶体管的特性。
请参考图4，图4所示的实施例中，指纹识别模组包括：
基板201；基板可使用玻璃基板或者柔性PI(聚酰亚胺)基板；
栅金属层图形，所述栅金属层图形包括薄膜晶体管的栅极202b和光敏传感器的下电极202a；栅金属可以是Al，Mo，AlNd，Cu，MoNb等；
PIN层203；PIN层203可以包括本征非晶硅层和P掺杂非晶硅层，其中，本征非晶硅层的厚度可以为600～1200nm，P掺杂非晶硅层的厚度可以为10～100nm；
栅绝缘层204，栅绝缘层204上开设有通孔，通孔位于PIN层203上方；栅绝缘层204可以采用SiO2，或者，SiNx和SiO2组合膜层，厚度可以为200-400nm；
有源层205a和连接电极205b，所述有源层205a和所述连接电极205b是由同一层半导体层图形形成，所述半导体层图形包括第一半导体图形和第二半导体图形，所述第一半导体图形作为所述有源层205a，所述连接电极205b是对所述第二半导体图形进行导体化处理得到，所述连接电极205b为透明电极，复用为光敏传感器的上电极；半导体层图形可以采用IGZO，ITZO，IZO等金属氧化物半导体材料形成，可选地，采用IGZO，可以为非晶状态也可以为结晶状态或是二者叠层结构，厚度可以为30-70nm；
源漏金属层图形，所述源漏金属层图形包括源极206；源漏金属可以为Al，Mo，AlNd，Cu，MoNb等，或者上述金属中的任意两个或多个的组合，源漏金属层的厚度可以为300-500nm；
PVX层207；PVX层207可以采用SiO2，或SiON，或SiO2和SiON的组合，厚度可以为
Figure PCTCN2021076187-appb-000004
上述实施例中，连接电极搭接在光敏传感器的上电极上，或者，复用为光敏传感器的上电极，在本公开的其他一些实施例中，连接电极也可以与光敏传感器的下电极连接，或者，复用为光敏传感器的下电极，下面分别进行说明。
在本公开的其他一些实施例中，可选地，所述连接电极复用为所述光敏传感器的下电极。
请参考图5，图5所示的实施例中，指纹识别模组包括：
基板301；基板301可使用玻璃基板或者柔性PI(聚酰亚胺)基板；
缓冲层302；
有源层303a、连接电极303b以及源极连接区303c，所述有源层303a、连接电极303b以及源极连接区303c是由同一层半导体层图形形成，所述半导体层图形包括第一半导体图形、第二半导体图形和第三半导体图形，所述第一半导体图形作为所述有源层303a，所述连接电极303b是对所述第二半导体图形进行导体化处理得到，源极连接区303c是对所述第三半导体图形进行导体化处理得到。所述连接电极303b复用为薄膜晶体管的漏极以及光敏传感器的下电极；半导体层图形可以采用IGZO，ITZO，IZO等金属氧化物半导体材料形成，可选地，采用IGZO，可以为非晶状态也可以为结晶状态或是二者叠层结构，厚度可以为30-70nm；
PIN层304；PIN层304可以包括本征非晶硅层和P掺杂非晶硅层，其中，本征非晶硅层的厚度可以为600～1200nm，P掺杂非晶硅层的厚度可以为10～100nm；
上电极305；上电极305可以采用透明金属氧化物例如ITO，厚度可以为20～80nm；
栅绝缘层306，栅绝缘层306上开设有通孔，通孔位于上电极305上方；栅绝缘层可以采用SiO2，或者，SiNx和SiO2组合膜层，厚度可以为200-400nm；
栅金属层图形，所述栅金属层图形包括薄膜晶体管的栅极307；栅金属可以是Al，Mo，AlNd，Cu，MoNb等；
层间介质层(ILD)308，层间介质层308上开设有通孔，通孔位于栅绝缘层306的通孔上方，与栅绝缘层306上的通孔连通；
第一连接部309，第一连接部309通过层间介质层308和栅绝缘层306上的通孔与上电极305连接；
源漏金属层图形，所述源漏金属层图形包括源极310a和第二连接部310b；源漏金属可以为Al，Mo，AlNd，Cu，MoNb等，或者上述金属中的任意两个或多个的组合，源漏金属层的厚度可以为300-500nm；在本公开的一些实施例中，也可以不包括第一连接部309，第二连接部310b直接通过层间介质层308和栅绝缘层306上的通孔与上电极305连接；
PVX层311；PVX层311可以采用SiO2，或SiON，或SiO2和SiON的组合，厚度可以为
Figure PCTCN2021076187-appb-000005
本公开实施例中，连接电极复用为光敏传感器的下电极，减少了单独制作光敏传感器的下电极的掩膜工艺，减少了指纹识别模组的掩膜数量，同时，还可以减少指纹识别模组的厚度。
在本公开的其他一些实施例中，所述连接电极也可以不复用为光敏传感器的下电极，而是与所述光敏传感器的下电极同层设置并连接。该种结构下，同样可以减少指纹识别模组的厚度。
在本公开的一些实施例中，所述薄膜晶体管包括栅极，所述栅极和所述光敏传感器的下电极同层同材料设置，请参考图3、图4和图6。图3所示的实施例中，薄膜晶体管的栅极102b和光敏传感器的下电极102a同层同材料设置，通过一次构图工艺形成。图4所示的实施例中，薄膜晶体管的栅极202b和光敏传感器的下电极202a同层同材料设置，通过一次构图工艺形成。图6所示的实施例中，薄膜晶体管的栅极502b和光敏传感器的下电极502a同层同材料设置，通过一次构图工艺形成。
本公开实施例中，薄膜晶体管的栅极和光敏传感器的下电极通过一次构图工艺形成，从而进一步减少了制作指纹识别模组使用的掩膜数量，且有助于减少指纹识别模组的厚度。
在本公开的一些实施例中，所述连接电极与所述有源层连接，复用为所述薄膜晶体管的漏极。请参考图3、图4和图5，图3所示的实施例中，连接电极106b复用为薄膜晶体管的漏极。图4所示的实施例中，连接电极205b同时复用为薄膜晶体管的漏极以及光敏传感器的上电极。图5所示的实施例中，连接电极303b同时复用为薄膜晶体管的漏极以及光敏传感器的下电极。
在本公开的一些实施例中，所述连接电极分别与所述有源层和所述薄膜晶体管的漏极连接。请参考图6，图6所示的实施例中，所述源漏金属层图形包括源极507a和漏极507b，连接电极506b分别与所述有源层506a和所述漏极507b连接。该种结构，可以减少漏极的电阻。
在本公开的一些实施例中，所述连接电极与所述有源层分离，所述薄膜晶体管的漏极与所述连接电极连接。
本公开的上述实施例中，可选地，半导体层图形采用金属氧化物半导体，例如IGZO(铟镓锌氧化物)，ITZO(铟锡锌氧化物)，IZO(氧化铟锌)等，以提高薄膜晶体管的性能。
本公开实施例还提供一种显示基板，包括上述任一实施例中的指纹识别模组。
本公开实施例还提供一种显示装置，包括上述显示基板。
上面结合附图对本公开的实施例进行了描述，但是本公开并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本公开的启示下，在不脱离本公开宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本公开的保护之内。

Claims (20)

  1. 一种指纹识别模组，包括：
    薄膜晶体管、光敏传感器和连接电极，所述连接电极用于连接所述薄膜晶体管和所述光敏传感器；
    所述薄膜晶体管包括有源层；
    所述有源层和所述连接电极是由同一层半导体层图形形成，所述半导体层图形包括第一半导体图形和第二半导体图形，所述第一半导体图形作为所述有源层，经导体化处理后的所述第二半导体图形作为所述连接电极。
  2. 如权利要求1所述的指纹识别模组，其中，所述光敏传感器包括：在基板上依次层叠设置的第一电极、PIN层和第二电极，其中，所述连接电极搭接在所述第二电极上。
  3. 如权利要求2所述的指纹识别模组，还包括：
    栅绝缘层，其中所述栅绝缘层的一部分覆盖在所述第二电极的远离所述第一电极的表面上；以及
    在所述栅绝缘层的该一部分上开设的通孔，其中所述通孔贯穿所述栅绝缘层，
    其中，所述连接电极通过所述通孔与所述第二电极相接触。
  4. 如权利要求2所述的指纹识别模组，其中，所述连接电极为透明电极。
  5. 如权利要求1所述的指纹识别模组，其中，所述光敏传感器包括在基板上依次层叠设置的第一电极和PIN层，所述连接电极为透明电极，复用为所述光敏传感器的第二电极。
  6. 如权利要求5所述的指纹识别模组，其中，所述连接电极的一部分位于所述PIN层的远离第一电极的表面上。
  7. 如权利要求1所述的指纹识别模组，其中，所述连接电极复用为所述光敏传感器的第二电极。
  8. 如权利要求1所述的指纹识别模组，其中，所述薄膜晶体管包括栅极，所述栅极和所述光敏传感器的第一电极同层同材料设置。
  9. 如权利要求1所述的指纹识别模组，其中，
    所述连接电极与所述有源层连接，复用为所述薄膜晶体管的漏极；或者
    所述连接电极分别与所述有源层和所述薄膜晶体管的漏极连接；或者
    所述连接电极与所述有源层分离，所述薄膜晶体管的漏极与所述连接电极连接。
  10. 一种显示基板，包括如权利要求1-9任一项所述的指纹识别模组。
  11. 一种显示装置，包括如权利要求10所述的显示基板。
  12. 一种指纹识别模组的制作方法，所述指纹识别模组包括薄膜晶体管和光敏传感器，所述制作方法包括：
    通过一次构图工艺形成半导体层图形，所述半导体层图形包括第一半导体图形和第二半导体图形，所述第一半导体图形作为所述薄膜晶体管的有源层；
    对所述第二半导体图形进行导体化处理形成连接电极，所述连接电极用于连接所述薄膜晶体管和所述光敏传感器。
  13. 如权利要求12所述的制作方法，还包括：在所述形成半导体层图形之前，
    在基板上依次形成所述光敏传感器的第一电极、PIN层和第二电极，其中，所述连接电极搭接在所述第二电极上。
  14. 如权利要求13所述的制作方法，还包括：在基板上依次形成所述光敏传感器的第一电极、PIN层和第二电极之后，
    形成栅绝缘层，其中，所述栅绝缘层的一部分覆盖在所述第二电极的远离所述第一电极的表面上；
    在所述栅绝缘层的该一部分上开设贯穿所述栅绝缘层的通孔，
    其中，所述连接电极通过所述通孔与所述第二电极相接触。
  15. 如权利要求13所述的制作方法，其中，所述连接电极为透明电极。
  16. 如权利要求12所述的制作方法，还包括：所述形成半导体层图形之前，
    在基板上依次形成所述光敏传感器的第一电极和PIN层，其中，所述连接电极为透明电极，复用为所述光敏传感器的第二电极。
  17. 如权利要求16所述的制作方法，其中，所述连接电极的一部分位于 所述PIN层的远离第一电极的表面上。
  18. 如权利要求12所述的制作方法，其中，所述连接电极复用为所述光敏传感器的第一电极。
  19. 如权利要求12所述的制作方法，还包括：所述形成半导体层图形之前，
    形成栅金属层图形，所述栅金属层图形包括所述薄膜晶体管的栅极和所述光敏传感器的第一电极。
  20. 如权利要求12所述的制作方法，还包括：所述形成半导体层图形之后，
    形成源漏金属层图形，所述源漏金属层图形仅包括源极，所述连接电极与所述有源层连接，复用为所述薄膜晶体管的漏极；
    或者
    形成源漏金属层图形，所述源漏金属层图形包括源极和漏极，所述连接电极分别与所述有源层和所述漏极连接；
    或者
    形成源漏金属层图形，所述源漏金属层图形包括源极和漏极，所述连接电极与所述有源层分离，所述漏极与所述连接电极连接。
PCT/CN2021/076187 2020-02-18 2021-02-09 指纹识别模组及其制作方法、显示基板和显示装置 WO2021164641A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/431,636 US20220100982A1 (en) 2020-02-18 2021-02-09 Fingerprint identification module, method for manufacturing fingerprint identification module, display substrate and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010098804.5 2020-02-18
CN202010098804.5A CN111275001A (zh) 2020-02-18 2020-02-18 指纹识别单元及其制作方法、显示基板和显示装置

Publications (1)

Publication Number Publication Date
WO2021164641A1 true WO2021164641A1 (zh) 2021-08-26

Family

ID=71003928

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/076187 WO2021164641A1 (zh) 2020-02-18 2021-02-09 指纹识别模组及其制作方法、显示基板和显示装置

Country Status (3)

Country Link
US (1) US20220100982A1 (zh)
CN (1) CN111275001A (zh)
WO (1) WO2021164641A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111275001A (zh) * 2020-02-18 2020-06-12 京东方科技集团股份有限公司 指纹识别单元及其制作方法、显示基板和显示装置
TWI764449B (zh) * 2020-12-18 2022-05-11 友達光電股份有限公司 顯示裝置
CN115016173B (zh) * 2022-06-07 2023-12-15 武汉华星光电技术有限公司 背光模组及显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104205341A (zh) * 2012-04-04 2014-12-10 夏普株式会社 半导体器件及其制造方法
CN106129069A (zh) * 2016-07-26 2016-11-16 京东方科技集团股份有限公司 一种指纹识别器、其制作方法及显示装置
CN109698224A (zh) * 2019-02-21 2019-04-30 京东方科技集团股份有限公司 显示基板及其制造方法和显示面板
CN110046610A (zh) * 2019-04-28 2019-07-23 云谷（固安）科技有限公司 一种指纹识别显示装置及其制备方法、显示设备
KR20190092661A (ko) * 2018-01-30 2019-08-08 삼성디스플레이 주식회사 디스플레이 장치
US10540936B1 (en) * 2017-06-26 2020-01-21 Amazon Technologies, Inc. Electrowetting pixel with adjustable capacitance
CN111275001A (zh) * 2020-02-18 2020-06-12 京东方科技集团股份有限公司 指纹识别单元及其制作方法、显示基板和显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI538177B (zh) * 2014-04-15 2016-06-11 友達光電股份有限公司 光感應裝置及其製作方法
CN106653767B (zh) * 2016-12-12 2020-02-07 深圳市华星光电技术有限公司 一种阵列基板及其制作方法
CN106876332B (zh) * 2017-03-21 2020-04-21 京东方科技集团股份有限公司 显示装置、指纹识别单元以及薄膜晶体管及其制造方法
CN107359168A (zh) * 2017-07-11 2017-11-17 京东方科技集团股份有限公司 显示面板及其制备方法、显示装置
CN111833720B (zh) * 2020-01-13 2021-08-31 昆山国显光电有限公司 一种显示面板及显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104205341A (zh) * 2012-04-04 2014-12-10 夏普株式会社 半导体器件及其制造方法
CN106129069A (zh) * 2016-07-26 2016-11-16 京东方科技集团股份有限公司 一种指纹识别器、其制作方法及显示装置
US10540936B1 (en) * 2017-06-26 2020-01-21 Amazon Technologies, Inc. Electrowetting pixel with adjustable capacitance
KR20190092661A (ko) * 2018-01-30 2019-08-08 삼성디스플레이 주식회사 디스플레이 장치
CN109698224A (zh) * 2019-02-21 2019-04-30 京东方科技集团股份有限公司 显示基板及其制造方法和显示面板
CN110046610A (zh) * 2019-04-28 2019-07-23 云谷（固安）科技有限公司 一种指纹识别显示装置及其制备方法、显示设备
CN111275001A (zh) * 2020-02-18 2020-06-12 京东方科技集团股份有限公司 指纹识别单元及其制作方法、显示基板和显示装置

Also Published As

Publication number Publication date
CN111275001A (zh) 2020-06-12
US20220100982A1 (en) 2022-03-31

Similar Documents

Publication Publication Date Title
WO2021164641A1 (zh) 指纹识别模组及其制作方法、显示基板和显示装置
US10403757B2 (en) Top-gate self-aligned metal oxide semiconductor TFT and method of making the same
CN107331669B (zh) Tft驱动背板的制作方法
US10615193B2 (en) Array substrate, method for manufacturing the same, display panel, and display device
US10795478B2 (en) Array substrate and preparation method therefor, and display apparatus
US10340354B2 (en) Manufacturing method of thin-film transistor (TFT) array substrate
US8445301B2 (en) Thin-film transistor substrate, method of manufacturing the same, and display device including the same
TWI418910B (zh) 陣列基板及其形成方法
US20150129865A1 (en) Semiconductor device and method for manufacturing same
WO2021036840A1 (zh) 显示基板及其制造方法、显示装置
WO2019061813A1 (zh) Esl型tft基板及其制作方法
TW201501325A (zh) 薄膜電晶體及其製造方法
US10217771B2 (en) Thin film transistor array panel and manufacturing method thereof
US20220059639A1 (en) Display Substrate and Manufacturing Method Thereof, and Display Apparatus
US11374027B2 (en) Manufacturing method of thin film transistor substrate and thin film transistor substrate
US20210313470A1 (en) Oxide semiconductor thin film transistor and method of forming the same
WO2019080617A1 (zh) 薄膜晶体管及其制造方法、阵列基板、电子装置
WO2017219412A1 (zh) 顶栅型薄膜晶体管的制作方法
US8497948B2 (en) Pixel structure and method for fabricating the same
US20180108746A1 (en) Thin film transistors (tfts), manufacturing methods of tfts, and cmos components
WO2019134257A1 (zh) 一种p型薄膜晶体管及其制备方法
KR102224457B1 (ko) 표시장치와 그 제조 방법
TW201503374A (zh) 氧化物半導體薄膜電晶體
WO2020232946A1 (zh) 改善金属氧化物tft特性的结构与其制作方法
WO2021248609A1 (zh) 一种阵列基板及其制备方法以及显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21756894

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21756894

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 21756894

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 31.03.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 21756894

Country of ref document: EP

Kind code of ref document: A1