WO2022062701A1 - 阵列基板、显示面板、显示装置和制作方法 - Google Patents

阵列基板、显示面板、显示装置和制作方法 Download PDF

Info

Publication number
WO2022062701A1
WO2022062701A1 PCT/CN2021/110676 CN2021110676W WO2022062701A1 WO 2022062701 A1 WO2022062701 A1 WO 2022062701A1 CN 2021110676 W CN2021110676 W CN 2021110676W WO 2022062701 A1 WO2022062701 A1 WO 2022062701A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
region
metal layer
base substrate
gate
Prior art date
Application number
PCT/CN2021/110676
Other languages
English (en)
French (fr)
Inventor
刘宁
张大成
许程
马丹阳
倪柳松
刘军
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/787,686 priority Critical patent/US20230015542A1/en
Publication of WO2022062701A1 publication Critical patent/WO2022062701A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K50/865—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. light-blocking layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate, a display panel, a display device and a manufacturing method.
  • the top-gate thin film transistor has the characteristics of a short channel, so the on-state current Ion can be effectively increased, so that the display effect can be significantly improved and the power consumption can be effectively reduced.
  • the overlapping area between the gate and the source and drain of the top-gate thin film transistor is small, so that the generated parasitic capacitance is small, so the possibility of failure is also reduced. Since top-gate thin film transistors have the above-mentioned remarkable advantages, they have attracted more and more attention.
  • Embodiments of the present disclosure provide an array substrate, including:
  • An active layer is located on one side of the base substrate, the active layer includes: a channel region, a conductive source region located on one side of the channel region, and a conductive source region located on the other side of the channel region Conductive drain;
  • a metal layer located on the side of the active layer away from the base substrate, the metal layer includes a gate electrode and a signal line arranged in the same layer, the gate electrode having a thickness perpendicular to the base substrate less than The signal line is perpendicular to the thickness of the base substrate.
  • the array substrate further includes:
  • the gate insulating layer located between the active layer and the metal layer, the gate insulating layer includes: a first insulating part and a second insulating part, the first insulating part includes a gate overlapped with the gate The first overlapping portion of the wire, and a first extension portion extending from the first overlapping portion, the second insulating portion includes a second overlapping portion overlapping with the signal line, and extending from the second overlapping portion
  • the length of the first epitaxial portion in the first direction is greater than the length of the second epitaxial portion in the direction perpendicular to the extension of the signal line, and the first direction is the conductorization One of the source region, the conductive drain region points in the direction of the other.
  • the metal layer includes a first metal layer and the second metal layer arranged in a stacked layer, and the second metal layer is located on a side of the first metal layer away from the gate insulation one side of the layer;
  • the thickness of the gate is the same as the thickness of the second metal layer
  • the thickness of the signal line is the same as the thickness of the first metal layer and the second metal layer. The sum of the thicknesses is the same.
  • the thickness of the first metal layer is smaller than the thickness of the second metal layer.
  • the difference between the length of the first epitaxial portion in the first direction and the length of the second epitaxial portion in the direction perpendicular to the extension of the signal line is 0.1 ⁇ m to 1 ⁇ m .
  • the signal line includes one or a combination of the following:
  • the array substrate further includes: a buffer layer located between the base substrate and the active layer, and a light shielding layer located between the buffer layer and the base substrate , wherein the orthographic projection of the light shielding layer on the base substrate covers the orthographic projection of the active layer on the base substrate.
  • the array substrate further includes an interlayer dielectric layer located on a side of the metal layer away from the gate insulating layer, and an interlayer dielectric layer located on a side of the interlayer dielectric layer away from the metal layer a source-drain layer on one side, the source-drain layer includes a source electrode and a drain electrode;
  • the drain electrode is connected to the conductive drain region through a first through hole passing through the interlayer dielectric layer, and the source electrode is connected to the conductive source region through a second through hole passing through the interlayer dielectric layer.
  • the electrode is electrically connected, and is connected to the light shielding layer through a third through hole penetrating the interlayer dielectric layer and the buffer layer.
  • the array substrate further includes a passivation layer on a side of the source and drain layers away from the interlayer dielectric layer.
  • Embodiments of the present disclosure further provide a display panel, including the array substrate provided by the embodiments of the present disclosure.
  • Embodiments of the present disclosure further provide a display device, which includes the display panel provided by the embodiments of the present disclosure.
  • Embodiments of the present disclosure also provide a method for fabricating an array substrate, including:
  • a metal layer with a thickness in a first region smaller than a thickness in a second region is formed on the side of the active layer away from the base substrate, wherein the first region is a region where a gate is formed, and the second region The area is the area where the signal line is formed.
  • the manufacturing method further includes: forming a gate insulating layer on the side of the active layer away from the base substrate;
  • the manufacturing method further includes:
  • a patterned photoresist layer is formed on the side of the metal layer away from the gate insulating layer, and the photoresist layer has a first photoresist portion in the region where the gate is located, and the signal The area where the line is located has a second photoresist portion;
  • the metal layers in the first region and the second region are etched for the same time period to form the gate electrode and the metal layer.
  • the signal line, and the line width difference between the first photoresist portion and the gate is formed to be greater than the line width difference between the second photoresist portion and the signal line;
  • the gate insulating layer is etched to form a gate insulating layer having a first insulating portion and a second insulating portion, wherein the The first insulating portion includes a first overlapping portion overlapping with the gate, and a first epitaxial portion extending from the first overlapping portion, and the second insulating portion includes a second overlapping portion overlapping with the signal line part, and a second extension part extended from the second overlapping part, the length of the first extension part in the first direction is greater than the length of the second extension part in the direction perpendicular to the extension direction of the signal line , the first direction is a direction in which one of the conductive source region and the conductive drain region points to the other;
  • the active layer is conductive to form a conductive source region and a conductive drain region of the active layer;
  • the first photoresist and the second photoresist are removed.
  • the metal layer formed on the side of the active layer away from the base substrate in the first region with a thickness smaller than that in the second region includes:
  • a second metal layer is formed on a side of the first metal layer facing away from the gate insulating layer.
  • the etching of the metal layers in the first region and the second region for the same duration includes:
  • the metal layers of the first region and the second region are etched for the same duration.
  • the manufacturing method before forming the active layer on the base substrate, the manufacturing method further includes:
  • a buffer layer is formed on the light shielding layer.
  • the manufacturing method further includes:
  • a passivation layer is formed on the side of the source and drain layers away from the interlayer dielectric layer.
  • 1 is a schematic diagram of the circuit structure of a 3T1C
  • FIG. 2 is a schematic structural diagram of the prior art when the active layer is conductive
  • FIG. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a specific array substrate provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of an array substrate with a passivation layer provided by an embodiment of the present disclosure
  • 6A is a schematic diagram of a manufacturing process of an array substrate according to an embodiment of the present disclosure.
  • 6B is a schematic diagram of a manufacturing process of a specific array substrate according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of an array substrate on which the first metal layer 63 is prepared in an embodiment of the present disclosure
  • FIG. 8 is a schematic structural diagram of an array substrate after patterning the first metal layer 63 in an embodiment of the disclosure.
  • FIG. 9 is a schematic structural diagram of an array substrate on which a patterned photoresist layer 10 is prepared in an embodiment of the present disclosure
  • FIG. 10 is a schematic structural diagram of an array substrate after etching the metal layer 6 in an embodiment of the disclosure
  • FIG. 11 is a schematic structural diagram of an array substrate on which a passivation layer 9 is formed in an embodiment of the disclosure.
  • the 3T1C structure is often used, and indium gallium zinc oxide is used. (indium gallium zinc oxide, IGZO) semiconductor as the active layer.
  • IGZO indium gallium zinc oxide
  • the difference between the line width and the line width of the photoresist 010 (PR) is larger, that is, the formed line width difference (CD bias) is larger, so that the PR glue can better protect the GI on the left and right sides of the gate pattern from etching.
  • CD bias formed line width difference
  • to form an insulating tail (GI tail) of a certain width so as to protect and limit the Act conductorization process below, which can effectively avoid the lateral diffusion of He plasma in the Act channel and the gate above the Act conductorization process.
  • Metal atoms diffuse into the channel through the two ends of the Act, thereby ensuring the stability of the characteristics of the thin film transistor.
  • an embodiment of the present disclosure provides an array substrate, including:
  • the active layer 4 is located on one side of the base substrate 1, and the active layer 4 includes: a channel region 40, a conductive source region 43 located on one side of the channel region 40, and a conductor located on the other side of the channel region 40 chemical leakage region 42;
  • the metal layer 6 is located on the side of the active layer 4 away from the base substrate 1.
  • the metal layer 6 includes a gate electrode 61 and a signal line 62 arranged in the same layer.
  • the thickness h1 of the gate electrode 61 perpendicular to the base substrate 1 is smaller than the signal line 62.
  • the line 62 is perpendicular to the thickness h2 of the base substrate 1 .
  • the metal including the gate 61 and the signal line 62 can be formed during the fabrication process.
  • the metal layer at the position where the gate 61 is formed is thinner, and the metal layer at the position where the signal line 62 is formed is thicker, and then the metal layers at different positions are subsequently masked by the photoresist.
  • the position where the gate 61 needs to be formed is relatively thin, resulting in a large amount of over-etching, and the position where the signal line 62 needs to be formed is due to the thicker metal layer, resulting in a larger amount of over-etching.
  • the insulating tail (GI tail) of the gate insulating layer 51 at the position of the gate 61 can be made larger, so that the active layer 4 can be subsequently conductorized. , can form a longer non-conductive area, effectively block the lateral diffusion of ions into the channel 40 during the conductive process, meet the requirements of thin film transistor characteristics and signal line conductivity, and minimize metal disconnection risk, thereby improving the display quality of the product.
  • the array substrate may further include: a gate insulating layer 5 located between the active layer 4 and the metal layer 6 , and the gate insulating layer 5 includes: a first insulating part 51 and a second insulating part 51 ;
  • the insulating portion 52 , the first insulating portion 51 includes a first overlapping portion 511 that overlaps with the gate 61 , and a first epitaxial portion 512 that extends from the first overlapping portion 511
  • the second insulating portion 52 includes a signal line 62 that overlaps.
  • the length L2 on the first direction AB is the direction in which one of the conductive source region 43 and the conductive drain region 42 points to the other, that is, the first direction AB can be from the conductive source region 43 to the conductive drain region.
  • the direction of the conductive drain region 42 may also be the direction from the conductive drain region 42 to the conductive source region 43 .
  • the metal layer 6 includes a first metal layer 63 and a second metal layer 64 arranged in layers, and the second metal layer 64 is located on the side of the first metal layer 63 away from the gate insulating layer 5 .
  • the first metal layer 63 when the metal layer 6 is fabricated, the first metal layer 63 may be formed first, the first metal layer 63 in the region where the gate electrode 61 is located is removed, and the first metal layer 63 in the region where the signal line 62 is located is retained, and then, The second metal layer 64 is then formed.
  • the second metal layer 64 covers the area where the gate 61 is located, and also covers the area where the signal line 62 is located, so that the thickness of the metal layer 6 in the area where the gate 61 is located is smaller than that of the signal line 62.
  • the thickness of the metal layer 6 in the region is beneficial to simplify the fabrication of the metal layer 6 with different thicknesses in different regions.
  • the thickness of the first metal layer 63 is smaller than the thickness of the second metal layer 64 .
  • the thickness of the first metal layer 63 is smaller than the thickness of the second metal layer 64 , so that the gate 61 and the signal line 62 have a larger thickness difference.
  • the difference between the length L1 of the first epitaxial portion 512 in the first direction AB and the length L2 of the second epitaxial portion 522 in the extending direction perpendicular to the signal line 62 is 0.1 ⁇ m ⁇ 1 ⁇ m.
  • the signal lines 62 include one or a combination of the following: gate lines; power lines; touch leads.
  • the array substrate further includes: a buffer layer 3 located between the base substrate 1 and the active layer 4 , and a light shielding layer 2 located between the buffer layer 3 and the base substrate 1 , wherein , the orthographic projection of the light shielding layer 2 on the base substrate 1 covers the orthographic projection of the active layer 4 on the base substrate 1 .
  • the array substrate further includes an interlayer dielectric layer 7 on the side of the metal layer 4 away from the gate insulating layer 5 , and an interlayer dielectric layer 7 on the side of the interlayer dielectric layer 7 away from the metal layer 6 .
  • the source-drain layer 8, the source-drain layer 8 includes a source electrode 81 and a drain electrode 82; the drain electrode 82 is connected to the conductive drain region 42 through the first through hole passing through the interlayer dielectric layer 7, and the source electrode 81 passes through the through layer
  • the second through hole of the interlayer dielectric layer 7 is connected to the conductive source electrode 43 , and is connected to the light shielding layer 2 through the third through hole passing through the interlayer dielectric layer 7 and the buffer layer 3 .
  • the array substrate further includes a passivation layer 9 located on the side of the source and drain layers 8 away from the interlayer dielectric layer 7 .
  • Embodiments of the present disclosure further provide a display panel including the array substrate provided by the embodiments of the present disclosure.
  • Embodiments of the present disclosure further provide a display device, which includes the display panel provided by the embodiments of the present disclosure.
  • an embodiment of the present disclosure further provides a method for fabricating an array substrate, as shown in FIG. 6A , including:
  • Step S100 forming an active layer on the base substrate
  • Step S300 forming a metal layer in the first region with a thickness smaller than that in the second region on the side of the active layer away from the base substrate, wherein the first region is the region where the gate is formed, and the second region is the region where the signal line is formed
  • this step may include: forming a first metal layer on the side of the gate insulating layer away from the active layer, removing the first metal layer in the first region, and retaining the first metal layer in the second region ; A second metal layer is formed on the side of the first metal layer away from the gate insulating layer.
  • the manufacturing method further includes: step S200, forming a gate insulating layer on the side of the active layer away from the base substrate;
  • step S300 that is, after forming a metal layer with a thickness in the first region smaller than that in the second region on the side of the active layer away from the base substrate, the manufacturing method further includes:
  • Step S400 forming a patterned photoresist layer on the side of the metal layer away from the gate insulating layer, the photoresist layer has a first photoresist part in the area where the gate is located, and has a second photoresist part in the area where the signal line is located. engraving department;
  • Step S500 Under the shielding of the first photoresist part and the second photoresist part, the metal layers in the first area and the second area are etched for the same length of time to form gates and signal lines, and form a first photolithography
  • the line width difference between the glue part and the gate is greater than the line width difference between the second photoresist part and the signal line; specifically, a wet etching process can be used to etch the same metal layers in the first area and the second area. duration;
  • Step S600 under the cover of the first photoresist and the second photoresist, the gate insulating layer is etched to form a gate insulating layer having a first insulating portion and a second insulating portion, wherein the first insulating portion includes A first overlapping portion overlapping with the gate, and a first epitaxial portion extending from the first overlapping portion, the second insulating portion including a second overlapping portion overlapping with the signal line, and a second overlapping portion extending from the second overlapping portion
  • the epitaxial portion, the length of the first epitaxial portion in the first direction is greater than the length of the second epitaxial portion in the extending direction perpendicular to the signal line, and the first direction is one of the conductive source region and the conductive drain region pointing to the direction of the other;
  • Step S700 under the shielding of the first insulating portion and the second insulating portion, conducting conductorization of the active layer to form conductorized source regions and conductorized drain regions of the active layer;
  • Step S800 removing the first photoresist and the second photoresist.
  • the manufacturing method before step S100, that is, before forming the active layer on the base substrate, the manufacturing method further includes:
  • a buffer layer is formed on the light shielding layer.
  • the manufacturing method further includes:
  • a passivation layer is formed on the side of the source and drain layers away from the interlayer dielectric layer.
  • Step 1 depositing and patterning the pattern of the light-shielding layer 2, the buffer layer 3, the pattern of the active layer 4, and the gate insulating layer 5 in turn on the base substrate 1, and then depositing a thin first metal layer 63, As shown in Figure 7;
  • Step 2 Performing the exposure development patterning process and the wet etching process, so that the first metal layer 63 at the position where the gate 61 needs to be formed is completely etched away, so that all the first metal layer 63 at the position where the signal line 61 needs to be formed is retained.
  • the schematic diagram of the formed pattern is shown in Figure 8 on the right;
  • Step 3 Deposit a thicker second metal layer 64 again, and then perform an exposure and development patterning process.
  • a schematic diagram of the photoresist pattern formed is shown in Figure 9 on the right.
  • the photoresist layer 10 includes a first photoresist portion. 11 and the second photoresist part 12;
  • Step 4 Carry out the wet etching process. Since the etching time is the same everywhere, the metal layer at the position where the gate 61 needs to be formed is thinner, resulting in a larger amount of overetching, so that the formed L1 is larger, and a signal line needs to be formed. At the position of 62, due to the thick metal layer, the overscale amount is small, so the L2 formed is small, as shown in Figure 10;
  • Step 5 then perform the etching of the gate insulating layer 5 and the conductive process of the active layer 4, remove the first photoresist part 11 and the second photoresist part 12, then deposit the interlayer dielectric layer 7, and pattern and etch Etch to form a pattern of via holes through the interlayer dielectric layer 7 and through the interlayer dielectric layer and the buffer layer 3 at the same time, then deposit and pattern the source and drain layers 8, as shown in FIG. 11, and then deposit an inorganic passivation layer 9 .
  • the beneficial effects of the embodiments of the present disclosure are as follows:
  • the thickness h1 of the gate electrode 61 perpendicular to the base substrate 1 smaller than the thickness h2 of the signal line 62 perpendicular to the base substrate 1, it is possible to form a gate electrode 61 during fabrication.
  • the metal layer of the electrode 61 and the signal line 62 is formed, the metal layer at the position where the gate 61 is formed is thinner, and the metal layer at the position where the signal line 62 is formed is thicker, and then the metal layer is subsequently shielded by the photoresist.
  • the metal layers at different positions are etched, the same etching time is used.
  • the gate insulating layer 51 can be etched at the position of the gate 61.
  • the insulating tail (GI tail) is relatively large, so that when the active layer 4 is subsequently conductorized, a longer area that is not conductorized can be formed, which effectively blocks the lateral direction of the ion body to the channel 40 during the conductorization process. At the same time, it meets the requirements of thin film transistor characteristics and signal line conductivity, and minimizes the risk of metal disconnection, thereby improving the display quality of the product.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

本公开实施例提供了一种阵列基板、显示面板、显示装置和制作方法。所述阵列基板包括：衬底基板；有源层，位于所述衬底基板的一侧，所述有源层包括：沟道区，位于所述沟道区一侧的导体化源区，以及位于所述沟道区另一侧的导体化漏区；金属层，位于所述有源层的背离所述衬底基板的一侧，所述金属层包括同层设置的栅极和信号线，所述栅极在垂直于所述衬底基板的厚度小于所述信号线在垂直于所述衬底基板的厚度。

Description

阵列基板、显示面板、显示装置和制作方法
相关申请的交叉引用
本申请要求在2020年09月25日提交中国专利局、申请号为202011019932.2、申请名称为“阵列基板、显示面板、显示装置和制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板、显示面板、显示装置和制作方法。
背景技术
顶栅型薄膜晶体管具有短沟道的特点，所以其开态电流Ion得以有效提升，因而可以显著提升显示效果并且能有效降低功耗。而且顶栅型薄膜晶体管的栅极与源漏极重叠面积小，因而产生的寄生电容较小，所以发生不良的可能性也降低。由于顶栅型薄膜晶体管具有上述显著优点，所以越来越受到人们的关注。
发明内容
本公开实施例提供一种阵列基板，其中，包括：
衬底基板；
有源层，位于所述衬底基板的一侧，所述有源层包括：沟道区，位于所述沟道区一侧的导体化源区，以及位于所述沟道区另一侧的导体化漏区；
金属层，位于所述有源层的背离所述衬底基板的一侧，所述金属层包括同层设置的栅极和信号线，所述栅极在垂直于所述衬底基板的厚度小于所述信号线在垂直于所述衬底基板的厚度。
在一种可能的实施方式中，所述阵列基板还包括：
栅极绝缘层，位于所述有源层与所述金属层之间，所述栅极绝缘层包括：第一绝缘部和第二绝缘部，所述第一绝缘部包括与所述栅极重合的第一重合部，以及由所述第一重合部延伸出的第一外延部，所述第二绝缘部包括与所述信号线重合的第二重合部，以及由所述第二重合部延伸出的第二外延部，所述第一外延部在第一方向上的长度大于所述第二外延部在垂直于所述信号线延伸方向上的长度，所述第一方向为所述导体化源区、所述导体化漏区中的一者指向另一者的方向。
在一种可能的实施方式中，所述金属层包括叠层设置的第一金属层和所述第二金属层，所述第二金属层位于所述第一金属层的背离所述栅极绝缘层的一侧；
在垂直于所述衬底基板的方向上，所述栅极的厚度与所述第二金属层的厚度相同，所述信号线的厚度与所述第一金属层和所述第二金属层的厚度之和相同。
在一种可能的实施方式中，在垂直于所述衬底基板的方向上，所述第一金属层的厚度小于所述第二金属层的厚度。
在一种可能的实施方式中，所述第一外延部在第一方向上的长度，与所述第二外延部在垂直于所述信号线延伸方向上的长度差值为0.1微米～1微米。
在一种可能的实施方式中，所述信号线包括以下之一或组合：
栅线；
电源线；
触控引线。
在一种可能的实施方式中，所述阵列基板还包括：位于所述衬底基板与所述有源层之间的缓冲层，位于所述缓冲层与所述衬底基板之间的遮光层，其中，所述遮光层在所述衬底基板的正投影覆盖所述有源层在所述衬底基板的正投影。
在一种可能的实施方式中，所述阵列基板还包括位于所述金属层的背离所述栅极绝缘层一侧的层间介质层，以及位于所述层间介质层的背离所述金 属层一侧的源漏极层，所述源漏极层包括源极和漏极；
所述漏极通过贯穿所述层间介质层的第一通孔与所述导体化漏区导通，所述源极通过贯穿所述层间介质层的第二通孔与所述导体化源极导通，并通过贯穿所述层间介质层、所述缓冲层的第三通孔与所述遮光层导通。
在一种可能的实施方式中，所述阵列基板还包括位于所述源漏极层的背离所述层间介质层一侧的钝化层。
本公开实施例还提供一种显示面板，包括如本公开实施例提供的所述阵列基板。
本公开实施例还提供一种显示装置，其中，包括如本公开实施例提供的所述显示面板。
本公开实施例还提供一种阵列基板的制作方法，包括：
在衬底基板之上形成有源层；
在所述有源层的背离所述衬底基板的一侧形成在第一区域厚度小于在第二区域厚度的金属层，其中，所述第一区域为形成栅极的区域，所述第二区域为形成信号线的区域。
在一种可能的实施方式中，在衬底基板之上形成有源层之后，以及在所述有源层的背离所述衬底基板的一侧形成在第一区域厚度小于在第二区域厚度的金属层之前，所述制作方法还包括：在所述有源层的背离所述衬底基板的一侧形成栅极绝缘层；
在所述有源层的背离所述衬底基板的一侧形成在第一区域厚度小于在第二区域厚度的金属层之后，所述制作方法还包括：
在所述金属层的背离所述栅极绝缘层的一侧形成图案化的光刻胶层，所述光刻胶层在所述栅极所在区域具有第一光刻胶部，在所述信号线所在区域具有第二光刻胶部；
在所述第一光刻胶部和所述第二光刻胶部的遮挡下，对所述第一区域和所述第二区域的所述金属层刻蚀相同时长，形成所述栅极和所述信号线，并形成所述第一光刻胶部与所述栅极的线宽差值，大于所述第二光刻胶部与所 述信号线的线宽差值；
在所述第一光刻胶和所述第二光刻胶的遮挡下，刻蚀所述栅极绝缘层，形成具有第一绝缘部和第二绝缘部的栅极绝缘层，其中，所述第一绝缘部包括与所述栅极重合的第一重合部，以及由所述第一重合部延伸出的第一外延部，所述第二绝缘部包括与所述信号线重合的第二重合部，以及由所述第二重合部延伸出的第二外延部，所述第一外延部在第一方向上的长度大于所述第二外延部在垂直于所述信号线延伸方向上的长度，所述第一方向为所述导体化源区、所述导体化漏区中的一者指向另一者的方向；
在所述第一绝缘部和所述第二绝缘部的遮挡下，对所述有源层进行导体化，以形成所述有源层的导体化源区和导体化漏区；
去除所述第一光刻胶和所述第二光刻胶。
在一种可能的实施方式中，所述在所述有源层的背离所述衬底基板的一侧形成在第一区域厚度小于在第二区域厚度的金属层，包括：
在所述栅极绝缘层的背离所述有源层的一侧形成第一金属层，并去除所述第一区域的所述第一金属层，保留所述第二区域的第一金属层；
在所述第一金属层的背离所述栅极绝缘层的一侧形成第二金属层。
在一种可能的实施方式中，所述对所述第一区域和所述第二区域的所述金属层刻蚀相同时长，包括：
采用湿刻工艺，对所述第一区域和所述第二区域的所述金属层刻蚀相同时长。
在一种可能的实施方式中，在衬底基板之上形成有源层之前，所述制作方法还包括：
在衬底基板之上形成遮光层；
在所述遮光层之上形成缓冲层。
在一种可能的实施方式中，在去除所述第一光刻胶和所述第二光刻胶之后，所述制作方法还包括：
在所述金属层的背离所述栅极绝缘层的一侧形成层间介质层；
在所述层间介质层的背离所述金属层的一侧形成源漏极层；
在所述源漏极层的背离所述层间介质层的一侧形成钝化层。
附图说明
图1为一种3T1C的电路结构示意图；
图2为现有技术在对有源层进行导体化时的结构示意图；
图3为本公开实施例提供的一种阵列基板的结构示意图；
图4为本公开实施例提供的一种具体的阵列基板的结构示意图；
图5为本公开实施例提供的具有钝化层的阵列基板的结构示意图；
图6A为本公开实施例提供的一种阵列基板的制作流程示意图；
图6B为本公开实施例提供的一种具体的阵列基板的制作流程示意图；
图7为本公开实施例中，制备完成第一金属层63的阵列基板的结构示意图；
图8为本公开实施例中，对第一金属层63进行图案化后的阵列基板的结构示意图；
图9为本公开实施例中，制备完成图案化的光刻胶层10的阵列基板的结构示意图；
图10为本公开实施例中，对金属层6刻蚀后的阵列基板的结构示意图；
图11为本公开实施例中，形成钝化层9的阵列基板的结构示意图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属 领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了保持本公开实施例的以下说明清楚且简明，本公开省略了已知功能和已知部件的详细说明。
结合图1和图2所示，在顶栅型有源矩阵有机发光二极体(Active-matrix organic light-emitting diode，AMOLED)产品电路设计中，经常采用3T1C结构，并且使用铟镓锌氧化物(indium gallium zinc oxide，IGZO)半导体做有源层。在实际工艺过程中，需要在完成栅极层06(Gate)曝光和刻蚀构图工艺后，采用自对准工艺对下方的栅极绝缘层05(GI)进行刻蚀，然后紧接着进行有源层04(Act)的导体化工艺，为了防止导体化过程中He等离子体在Act沟道内的横向扩散和上方的Gate金属原子通过Act两端向沟道内扩散，工艺上采用将Gate刻蚀后的线宽与光刻胶010(PR)的线宽差异做大，即形成的线宽差(CD bias)较大，这样PR胶可以更好的保护Gate图案下方左右两侧的GI免于刻蚀，形成一定宽度的绝缘尾部(GI tail)，从而对下方的Act导体化工艺起到一定的保护限制作用，可以有效避免Act导体化过程中He等离子体在Act沟道内的横向扩散和上方的Gate金属原子通过Act两端向沟道内扩散，从而确保薄膜晶体管特性的稳定性。
但是随着显示产品逐渐向大尺寸和高分辨率(PPI)发展，需要越来越密的金属布线密度，并且要求金属线的尺寸越来越窄，这就需要工艺上达到曝光形成的PR胶的线宽尺寸与最终刻蚀后的线宽尺寸越接近越好，即CD bias越小越好，这样一方面可以增强导电能力，另一方面可以防止刻蚀过后线宽 过窄导致断线高发。这就与上面所述Act导体化工艺时要求Gate刻蚀后形成的CD bias较大存在一定的矛盾。
基于以上问题，参见图3，本公开实施例提供一种阵列基板，包括：
衬底基板1；
有源层4，位于衬底基板1的一侧，有源层4包括：沟道区40，位于沟道区40一侧的导体化源区43，以及位于沟道区40另一侧的导体化漏区42；
金属层6，位于有源层4的背离衬底基板1的一侧，金属层6包括同层设置的栅极61和信号线62，栅极61在垂直于衬底基板1的厚度h1小于信号线62在垂直于衬底基板1的厚度h2。
本公开实施例中，通过使栅极61在垂直于衬底基板1的厚度h1小于信号线62在垂直于衬底基板1的厚度h2，可以在制作形成包括栅极61和信号线62的金属层时，在用于形成栅极61所在位置处的金属层较薄，用于形成信号线62所在位置处的金属层较厚，进而后续在光刻胶遮挡下对不同位置处的金属层进行刻蚀时，采用相同的刻蚀时长，需要形成栅极61的位置处由于金属层较薄导致过刻量较大，而需要形成信号线62的位置处由于金属层较厚，导致过刻量较小，再后续刻蚀栅极绝缘层时，可以使栅极绝缘层51在栅极61所在位置处的绝缘尾部(GI tail)较大，进而可以在后续对有源层4进行导体化时，可以形成较长的不被导体化的区域，有效阻挡导体化过程中离子体向沟道内40的横向扩散，同时满足薄膜晶体管特性和信号线导电性的需求，并且最大限度的降低金属断线风险，从而提高产品的显示质量。
在具体实施时，结合图3所示，阵列基板还可以包括：栅极绝缘层5，位于有源层4与金属层6之间，栅极绝缘层5包括：第一绝缘部51和第二绝缘部52，第一绝缘部51包括与栅极61重合的第一重合部511，以及由第一重合部511延伸出的第一外延部512，第二绝缘部52包括与信号线62重合的第二重合部521，以及由第二重合部521延伸出的第二外延部522，第一外延部512在第一方向AB上的长度L1大于第二外延部522在垂直于信号线62延伸方向上的长度L2，第一方向AB导体化源区43、导体化漏区42中的一者指 向另一者的方向，即，第一方向AB可以为由导体化源区43指向导体化漏区42的方向，也可以是由导体化漏区42指向导体化源区43的方向。
在具体实施时，参见图4所示，金属层6包括叠层设置的第一金属层63和第二金属层64，第二金属层64位于第一金属层63的背离栅极绝缘层5的一侧；在垂直于衬底基板1的方向上，栅极61的厚度与第二金属层64的厚度相同，信号线62的厚度与第一金属层63和第二金属层64的厚度之和相同。本公开实施例中，在制作金属层6时，可以先形成第一金属层63，去除栅极61所在区域的第一金属层63，保留信号线62所在区域的第一金属层63，接着，再形成第二金属层64，第二金属层64覆盖栅极61所在的区域，也覆盖信号线62所在的区域，进而可以最终使栅极61所在区域的金属层6的厚度，小于信号线62所在区域的金属层6的厚度，有利于简化制作在不同区域具有不同厚度的金属层6的制作。
在具体实施时，在垂直于衬底基板1的方向上，第一金属层63的厚度小于第二金属层64的厚度。本公开实施例中，第一金属层63的厚度小于第二金属层64的厚度，可以使栅极61与信号线62具有较大的厚度差。
在具体实施时，第一外延部512在第一方向AB上的长度L1，与第二外延部522在垂直于信号线62延伸方向上的长度L2差值为0.1微米～1微米。
在具体实施时，信号线62包括以下之一或组合：栅线；电源线；触控引线。
在具体实施时，结合图3所示，阵列基板还包括：位于衬底基板1与有源层4之间的缓冲层3，位于缓冲层3与衬底基板1之间的遮光层2，其中，遮光层2在衬底基板1的正投影覆盖有源层4在衬底基板1的正投影。
在具体实施时，结合图3所示，阵列基板还包括位于金属层4的背离栅极绝缘层5一侧的层间介质层7，以及位于层间介质层7的背离金属层6一侧的源漏极层8，源漏极层8包括源极81和漏极82；漏极82通过贯穿层间介质层7的第一通孔与导体化漏区42导通，源极81通过贯穿层间介质层7的第二通孔与导体化源极43导通，并通过贯穿层间介质层7、缓冲层3的第三 通孔与遮光层2导通。
在具体实施时，参见图5所示，阵列基板还包括位于源漏极层8的背离层间介质层7一侧的钝化层9。
本公开实施例还提供一种显示面板，包括如本公开实施例提供的阵列基板。
本公开实施例还提供一种显示装置，其中，包括如本公开实施例提供的显示面板。
基于同一发明构思，本公开实施例还提供一种阵列基板的制作方法，参见图6A所示，包括：
步骤S100、在衬底基板之上形成有源层；
步骤S300、在有源层的背离衬底基板的一侧形成在第一区域厚度小于在第二区域厚度的金属层，其中，第一区域为形成栅极的区域，第二区域为形成信号线的区域；具体的，该步骤可以包括：在栅极绝缘层的背离有源层的一侧形成第一金属层，并去除第一区域的第一金属层，保留第二区域的第一金属层；在第一金属层的背离栅极绝缘层的一侧形成第二金属层。
在具体实施时，结合图6B所示，在步骤S100之后，以及在步骤S300之前，即，在衬底基板之上形成有源层之后，以及在有源层的背离衬底基板的一侧形成在第一区域厚度小于在第二区域厚度的金属层之前，制作方法还包括：步骤S200、在有源层的背离衬底基板的一侧形成栅极绝缘层；
在步骤S300之后，即，在有源层的背离衬底基板的一侧形成在第一区域厚度小于在第二区域厚度的金属层之后，制作方法还包括：
步骤S400、在金属层的背离栅极绝缘层的一侧形成图案化的光刻胶层，光刻胶层在栅极所在区域具有第一光刻胶部，在信号线所在区域具有第二光刻胶部；
步骤S500、在第一光刻胶部和第二光刻胶部的遮挡下，对第一区域和第二区域的金属层刻蚀相同时长，形成栅极和信号线，并形成第一光刻胶部与栅极的线宽差值，大于第二光刻胶部与信号线的线宽差值；具体的，可以采 用湿刻工艺，对第一区域和第二区域的金属层刻蚀相同时长；
步骤S600、在第一光刻胶和第二光刻胶的遮挡下，刻蚀栅极绝缘层，形成具有第一绝缘部和第二绝缘部的栅极绝缘层，其中，第一绝缘部包括与栅极重合的第一重合部，以及由第一重合部延伸出的第一外延部，第二绝缘部包括与信号线重合的第二重合部，以及由第二重合部延伸出的第二外延部，第一外延部在第一方向上的长度大于第二外延部在垂直于信号线延伸方向上的长度，第一方向为所述导体化源区、导体化漏区中的一者指向另一者的方向；
步骤S700、在第一绝缘部和第二绝缘部的遮挡下，对有源层进行导体化，以形成有源层的导体化源区和导体化漏区；
步骤S800、去除第一光刻胶和第二光刻胶。
在具体实施时，在步骤S100之前，即，在衬底基板之上形成有源层之前，制作方法还包括：
在衬底基板之上形成遮光层；
在遮光层之上形成缓冲层。
在具体实施时，在步骤S800之后，即，在去除第一光刻胶和第二光刻胶之后，制作方法还包括：
在金属层的背离栅极绝缘层的一侧形成层间介质层；
在层间介质层的背离金属层的一侧形成源漏极层；
在源漏极层的背离层间介质层的一侧形成钝化层。
为了更清楚地理解本公开实施例提供的阵列基板的制作方法，以下结合图7-图，对本公开实施例提供的阵列基板的制作方法进行详细说明如下：
步骤一、在衬底基板1上依次沉积构图形成遮光层2的图案、缓冲层3、有源层4的图案、栅极绝缘层5，然后先沉积一层较薄的第一金属层63，如图7所示；
步骤二、进行曝光显影图案化工艺和湿刻工艺，使需要形成栅极61的位置处的第一金属层63全部刻蚀掉，使需要形成信号线61位置处的第一金属 层63全部保留下来，形成的图案示意图如右图8所示；
步骤三、再次沉积一层较厚的第二金属层64，然后进行曝光显影构图工艺，形成的光刻胶图案的示意图如右图9所示，光刻胶层10包括第一光刻胶部11和第二光刻胶部12；
步骤四、进行湿刻工艺，由于各处刻蚀时间一样，所以需要形成栅极61的位置处由于金属层较薄，导致过刻量较大，从而形成的L1较大，而需要形成信号线62的位置处，由于金属层较厚，导致过刻量较小，从而形成的L2较小，示意图如图10所示；
步骤五、然后进行栅极绝缘层5的刻蚀和有源层4导体化工艺，去除第一光刻胶部11和第二光刻胶部12，然后沉积层间介质层7，并构图刻蚀形成贯穿层间介质层7，以及同时贯穿层间介质层和缓冲层3过孔的图案，然后沉积并构图形成源漏极层8，如图11所示，然后沉积无机的钝化层9。
本公开实施例有益效果如下：本公开实施例中，通过使栅极61在垂直于衬底基板1的厚度h1小于信号线62在垂直于衬底基板1的厚度h2，可以在制作形成包括栅极61和信号线62的金属层时，在用于形成栅极61所在位置处的金属层较薄，用于形成信号线62所在位置处的金属层较厚，进而后续在光刻胶遮挡下对不同位置处的金属层进行刻蚀时，采用相同的刻蚀时长，需要形成栅极61的位置处由于金属层较薄导致过刻量较大，从而形成的L1较大，而需要形成信号线62的位置处由于金属层较厚，导致过刻量较小，从而形成的L2较小，再后续刻蚀栅极绝缘层时，可以使栅极绝缘层51在栅极61所在位置处的绝缘尾部(GI tail)较大，进而可以在后续对有源层4进行导体化时，可以形成较长的不被导体化的区域，有效阻挡导体化过程中离子体向沟道内40的横向，同时满足薄膜晶体管特性和信号线导电性的需求，并且最大限度的降低金属断线风险，从而提高产品的显示质。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (17)

  1. 一种阵列基板，其中，包括：
    衬底基板；
    有源层，位于所述衬底基板的一侧，所述有源层包括：沟道区，位于所述沟道区一侧的导体化源区，以及位于所述沟道区另一侧的导体化漏区；
    金属层，位于所述有源层的背离所述衬底基板的一侧，所述金属层包括同层设置的栅极和信号线，所述栅极在垂直于所述衬底基板的厚度小于所述信号线在垂直于所述衬底基板的厚度。
  2. 如权利要求1所述的阵列基板，其中，所述阵列基板还包括：
    栅极绝缘层，位于所述有源层与所述金属层之间，所述栅极绝缘层包括：第一绝缘部和第二绝缘部，所述第一绝缘部包括与所述栅极重合的第一重合部，以及由所述第一重合部延伸出的第一外延部，所述第二绝缘部包括与所述信号线重合的第二重合部，以及由所述第二重合部延伸出的第二外延部，所述第一外延部在第一方向上的长度大于所述第二外延部在垂直于所述信号线延伸方向上的长度，所述第一方向为所述导体化源区、所述导体化漏区中的一者指向另一者的方向。
  3. 如权利要求2所述的阵列基板，其中，所述金属层包括叠层设置的第一金属层和所述第二金属层，所述第二金属层位于所述第一金属层的背离所述栅极绝缘层的一侧；
    在垂直于所述衬底基板的方向上，所述栅极的厚度与所述第二金属层的厚度相同，所述信号线的厚度与所述第一金属层和所述第二金属层的厚度之和相同。
  4. 如权利要求3所述的阵列基板，其中，在垂直于所述衬底基板的方向上，所述第一金属层的厚度小于所述第二金属层的厚度。
  5. 如权利要求1-4任一项所述的阵列基板，其中，所述第一外延部在第一方向上的长度，与所述第二外延部在垂直于所述信号线延伸方向上的长度 差值为0.1微米～1微米。
  6. 如权利要求1所述的阵列基板，其中，所述信号线包括以下之一或组合：
    栅线；
    电源线；
    触控引线。
  7. 如权利要求1所述的阵列基板，其中，所述阵列基板还包括：位于所述衬底基板与所述有源层之间的缓冲层，位于所述缓冲层与所述衬底基板之间的遮光层，其中，所述遮光层在所述衬底基板的正投影覆盖所述有源层在所述衬底基板的正投影。
  8. 如权利要求7所述的阵列基板，其中，所述阵列基板还包括位于所述金属层的背离所述栅极绝缘层一侧的层间介质层，以及位于所述层间介质层的背离所述金属层一侧的源漏极层，所述源漏极层包括源极和漏极；
    所述漏极通过贯穿所述层间介质层的第一通孔与所述导体化漏区导通，所述源极通过贯穿所述层间介质层的第二通孔与所述导体化源极导通，并通过贯穿所述层间介质层、所述缓冲层的第三通孔与所述遮光层导通。
  9. 如权利要求8所述的阵列基板，其中，所述阵列基板还包括位于所述源漏极层的背离所述层间介质层一侧的钝化层。
  10. 一种显示面板，其中，包括如权利要求1-9任一项所述的阵列基板。
  11. 一种显示装置，其中，包括如权利要求10所述的显示面板。
  12. 一种阵列基板的制作方法，其中，包括：
    在衬底基板之上形成有源层；
    在所述有源层的背离所述衬底基板的一侧形成在第一区域厚度小于在第二区域厚度的金属层，其中，所述第一区域为形成栅极的区域，所述第二区域为形成信号线的区域。
  13. 如权利要求12所述的制作方法，其中，在衬底基板之上形成有源层之后，以及在所述有源层的背离所述衬底基板的一侧形成在第一区域厚度小 于在第二区域厚度的金属层之前，所述制作方法还包括：在所述有源层的背离所述衬底基板的一侧形成栅极绝缘层；
    在所述有源层的背离所述衬底基板的一侧形成在第一区域厚度小于在第二区域厚度的金属层之后，所述制作方法还包括：
    在所述金属层的背离所述栅极绝缘层的一侧形成图案化的光刻胶层，所述光刻胶层在所述栅极所在区域具有第一光刻胶部，在所述信号线所在区域具有第二光刻胶部；
    在所述第一光刻胶部和所述第二光刻胶部的遮挡下，对所述第一区域和所述第二区域的所述金属层刻蚀相同时长，形成所述栅极和所述信号线，并形成所述第一光刻胶部与所述栅极的线宽差值，大于所述第二光刻胶部与所述信号线的线宽差值；
    在所述第一光刻胶和所述第二光刻胶的遮挡下，刻蚀所述栅极绝缘层，形成具有第一绝缘部和第二绝缘部的栅极绝缘层，其中，所述第一绝缘部包括与所述栅极重合的第一重合部，以及由所述第一重合部延伸出的第一外延部，所述第二绝缘部包括与所述信号线重合的第二重合部，以及由所述第二重合部延伸出的第二外延部，所述第一外延部在第一方向上的长度大于所述第二外延部在垂直于所述信号线延伸方向上的长度，所述第一方向为所述导体化源区、所述导体化漏区中的一者指向另一者的方向；
    在所述第一绝缘部和所述第二绝缘部的遮挡下，对所述有源层进行导体化，以形成所述有源层的导体化源区和导体化漏区；
    去除所述第一光刻胶和所述第二光刻胶。
  14. 如权利要求13所述的制作方法，其中，所述在所述有源层的背离所述衬底基板的一侧形成在第一区域厚度小于在第二区域厚度的金属层，包括：
    在所述栅极绝缘层的背离所述有源层的一侧形成第一金属层，并去除所述第一区域的所述第一金属层，保留所述第二区域的第一金属层；
    在所述第一金属层的背离所述栅极绝缘层的一侧形成第二金属层。
  15. 如权利要求13所述的制作方法，其中，所述对所述第一区域和所述 第二区域的所述金属层刻蚀相同时长，包括：
    采用湿刻工艺，对所述第一区域和所述第二区域的所述金属层刻蚀相同时长。
  16. 如权利要求13所述的制作方法，其中，在衬底基板之上形成有源层之前，所述制作方法还包括：
    在衬底基板之上形成遮光层；
    在所述遮光层之上形成缓冲层。
  17. 如权利要求16所述的制作方法，其中，在去除所述第一光刻胶和所述第二光刻胶之后，所述制作方法还包括：
    在所述金属层的背离所述栅极绝缘层的一侧形成层间介质层；
    在所述层间介质层的背离所述金属层的一侧形成源漏极层；
    在所述源漏极层的背离所述层间介质层的一侧形成钝化层。
PCT/CN2021/110676 2020-09-25 2021-08-04 阵列基板、显示面板、显示装置和制作方法 WO2022062701A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/787,686 US20230015542A1 (en) 2020-09-25 2021-08-04 Array substrate, display panel, display apparatus, and method for manufacturing array substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011019932.2A CN112151555A (zh) 2020-09-25 2020-09-25 阵列基板、显示面板、显示装置和制作方法
CN202011019932.2 2020-09-25

Publications (1)

Publication Number Publication Date
WO2022062701A1 true WO2022062701A1 (zh) 2022-03-31

Family

ID=73897973

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/110676 WO2022062701A1 (zh) 2020-09-25 2021-08-04 阵列基板、显示面板、显示装置和制作方法

Country Status (3)

Country Link
US (1) US20230015542A1 (zh)
CN (1) CN112151555A (zh)
WO (1) WO2022062701A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112151555A (zh) * 2020-09-25 2020-12-29 合肥鑫晟光电科技有限公司 阵列基板、显示面板、显示装置和制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160079429A1 (en) * 2014-09-16 2016-03-17 Carolyn Rae Ellinger Top gate tft with polymer interface control layer
CN107068692A (zh) * 2017-04-20 2017-08-18 京东方科技集团股份有限公司 显示装置、阵列基板及其制造方法
CN111312725A (zh) * 2020-02-24 2020-06-19 合肥鑫晟光电科技有限公司 一种阵列基板及其制备方法、显示面板
CN112151555A (zh) * 2020-09-25 2020-12-29 合肥鑫晟光电科技有限公司 阵列基板、显示面板、显示装置和制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160079429A1 (en) * 2014-09-16 2016-03-17 Carolyn Rae Ellinger Top gate tft with polymer interface control layer
CN107068692A (zh) * 2017-04-20 2017-08-18 京东方科技集团股份有限公司 显示装置、阵列基板及其制造方法
CN111312725A (zh) * 2020-02-24 2020-06-19 合肥鑫晟光电科技有限公司 一种阵列基板及其制备方法、显示面板
CN112151555A (zh) * 2020-09-25 2020-12-29 合肥鑫晟光电科技有限公司 阵列基板、显示面板、显示装置和制作方法

Also Published As

Publication number Publication date
US20230015542A1 (en) 2023-01-19
CN112151555A (zh) 2020-12-29

Similar Documents

Publication Publication Date Title
US11094721B2 (en) Method for manufacturing array substrate including forming via holes having different widths using single patterning process
WO2019007228A1 (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
CN109860305B (zh) 薄膜晶体管及其制作方法、显示基板和显示装置
US10361261B2 (en) Manufacturing method of TFT substrate, TFT substrate, and OLED display panel
KR102224457B1 (ko) 표시장치와 그 제조 방법
US11244965B2 (en) Thin film transistor and manufacturing method therefor, array substrate and display device
CN110197831B (zh) 一种阵列基板及其制作方法和显示面板
WO2022062701A1 (zh) 阵列基板、显示面板、显示装置和制作方法
CN108711548B (zh) 金属氧化物薄膜晶体管及其制作方法、显示器
CN108538725B (zh) 薄膜晶体管及其制造方法
US11894386B2 (en) Array substrate, manufacturing method thereof, and display panel
WO2023226688A1 (zh) 阵列基板及其制造方法、显示装置
CN107735853B (zh) 薄膜晶体管制造方法及阵列基板
US10249654B1 (en) Manufacturing method of top-gate TFT and top-gate TFT
WO2022148260A1 (zh) 薄膜晶体管阵列基板及其制备方法、显示面板
KR102522595B1 (ko) 트랜지스터 패널 및 그 제조 방법
WO2023197368A1 (zh) 阵列基板及其制作方法、显示面板
CN109659325B (zh) 顶栅型薄膜晶体管基板及其制作方法
US10204942B1 (en) Method for manufacturing top-gated thin film transistors
WO2020232747A1 (zh) 薄膜晶体管器件及其制备方法
KR102303957B1 (ko) 산화물 반도체 박막 트랜지스터 및 그 제조 방법
TWI814636B (zh) 主動元件基板
US20240194685A1 (en) Driving substrate, method for fabricating same, and display panel
WO2024093171A1 (zh) 薄膜晶体管及其制作方法、显示基板和显示装置
US11244972B2 (en) Array substrate, method for manufacturing the same and display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21871078

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 03/07/2023)

122 Ep: pct application non-entry in european phase

Ref document number: 21871078

Country of ref document: EP

Kind code of ref document: A1