WO2024036895A1 - 显示面板和电子终端 - Google Patents

显示面板和电子终端 Download PDF

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Publication number
WO2024036895A1
WO2024036895A1 PCT/CN2023/076080 CN2023076080W WO2024036895A1 WO 2024036895 A1 WO2024036895 A1 WO 2024036895A1 CN 2023076080 W CN2023076080 W CN 2023076080W WO 2024036895 A1 WO2024036895 A1 WO 2024036895A1
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Prior art keywords
substrate
layer
projection
electrode
conductive
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PCT/CN2023/076080
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English (en)
French (fr)
Inventor
罗传宝
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2024036895A1 publication Critical patent/WO2024036895A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present application relates to the field of display technology, in particular to the field of manufacturing technology of display panels, and specifically to display panels and electronic terminals.
  • Mini LED (sub-millimeter light-emitting diode) display technology and Micro LED (micron light-emitting diode) display technology are widely used in small and medium-sized high value-added displays, with the advantages of high contrast, high brightness and thin and light appearance.
  • the number of non-metallic layers used to separate metal layers in electronic terminals produced using Mini LED display technology or Micro LED display technology is small and is omitted during packaging. Without the cover plate and frame glue, external water and oxygen can easily enter the active layer of the transistor device through the packaging structure and film layer, reducing the reliability of the transistor device.
  • Embodiments of the present application provide a display panel and an electronic terminal to solve the technical problem of high risk of transistor device failure in existing electronic terminals produced using Mini LED display technology or Micro LED display technology.
  • Embodiments of the present application provide a display panel, including: substrate;
  • the active layer is located on the substrate and includes a channel portion and conductive portions located on both sides of the channel portion;
  • Embodiments of the present application also provide an electronic terminal, where the electronic terminal includes the display panel as described above.
  • the present application provides a display panel and an electronic terminal, including: a substrate; an active layer located on the substrate, including a channel portion and conductive portions located on both sides of the channel portion; a first conductive layer located on the The side of the active layer close to or away from the substrate includes a gate, and the projection of the gate on the substrate overlaps with the projection of the channel portion on the substrate; a second conductive layer is located on the side of the substrate.
  • the side of the active layer away from the substrate includes a source electrode connected to one of the conductive parts; wherein the source electrode and the drain electrode connected to the other conductive part are arranged in different layers, so The projection of the source electrode on the substrate overlaps with the projection of the gate electrode on the substrate.
  • the source electrode and the drain electrode connected to another conductive part are arranged in different layers, and the source electrode extends to the side close to the drain electrode, so as to realize the projection overlap of the source electrode and the gate electrode on the substrate.
  • the projection of the source on the active layer can also overlap the channel to cover more parts of the active layer, reducing the risk of damage to the active layer due to the entry of water vapor. Risk of failure.
  • FIG. 1 is a schematic cross-sectional view of a first display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional view of a second display panel provided by an embodiment of the present application.
  • FIG. 3 is a schematic cross-sectional view of a third display panel provided by an embodiment of the present application.
  • FIG. 4 is a schematic cross-sectional view of a fourth display panel provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a display panel manufacturing method according to an embodiment of the present application.
  • an embodiment means that a particular feature, structure or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application.
  • the appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art understand, both explicitly and implicitly, that the embodiments described herein may be combined with other embodiments.
  • Embodiments of the present application provide a display panel, which includes but is not limited to the following embodiments and combinations between the following embodiments.
  • the display panel 100 includes: a substrate 10 ; an active layer 20 located on the substrate 10 and including a channel portion 201 .
  • the drain electrode 50 of 202 is arranged in different layers, and the source electrode 401 and the gate electrode 301 are arranged overlappingly. Since the two are not coplanar, this can also be understood as the projection of the source electrode 401 on the substrate 10 and The projection of the gate 301 on the substrate 10 overlaps.
  • the substrate 10 may be a flexible substrate or a rigid substrate.
  • the constituent materials of the active layer 20 may include semiconductor materials, such as amorphous silicon, polycrystalline silicon, organic semiconductor materials, and metal oxides.
  • the conductive part 202 may pass through the active layer 20
  • the doping at both ends includes but is not limited to the formation of particles such as hydrogen, phosphorus ions or boron ions.
  • the gate 301 in this embodiment can be located on the side of the active layer 20 away from the substrate 10 to form a top gate structure.
  • the gate 301 can also be located on the side of the active layer 20 away from the substrate 10.
  • the side of layer 20 close to substrate 10 forms a bottom gate structure.
  • the gate electrode 301 After applying a voltage to the gate electrode 301, the gate electrode 301 has a voltage, or it is considered that there is a voltage difference between the gate electrode 301 and the channel portion 201 in the active layer 20, thereby forming a waveform directed from the gate electrode 301 to the substrate 10.
  • the electric field drives the electrons and holes in the active layer 20 to move within the channel portion 201 , thereby connecting the source electrode 401 and the drain electrode 50 . It should be noted that water vapor intruding into the active layer 20 will affect the performance of the active layer 20 and reduce the reliability of the thin film transistor in the display panel 100 .
  • the gate electrode 301 and the channel portion 201 are overlapped, the source electrode 401 is connected to one of the conductive portions 202 of the active layer 20 , and the drain electrode 50 is connected to the active layer 20
  • the other conductive portion 202 of the active layer 20 that is, the source electrode 401 can be considered to be disposed close to one of the conductive portions 202 of the active layer 20
  • the drain electrode 50 is disposed close to the other conductive portion 202 of the active layer 20
  • the gate electrode 301 is disposed close between the source electrode 401 and the drain electrode 50 .
  • the source electrode 401 and the drain electrode 50 are arranged in different layers to achieve insulation between the two.
  • the source electrode 401 is extended to the side close to the drain electrode 50 to overlap the gate electrode 301, so that On the premise of ensuring that the source electrode 401 and the drain electrode 50 are insulated, the projection of the source electrode 401 on the active layer 20 can also overlap the channel portion 201 to cover more parts of the active layer 20, so that Increasing the size of the source electrode 401 for blocking the entry of water vapor into the active layer 20 reduces the risk of failure of the active layer 20 due to the entry of water vapor.
  • the projection of the source electrode 401 on the substrate 10 completely covers the projection of the gate electrode 301 on the substrate 10 .
  • the source electrode 401 extends to the side close to the drain electrode 50 to overlap the gate electrode 301, and can cover more parts of the active layer 20; it can be understood that the source electrode in this embodiment
  • the end of 401 close to the gate 301 exceeds the end of the gate 301 away from the source 401, that is, the source 401 can completely cover the gate 301, that is, the source 401 can completely cover the channel portion 201, so as to move in the direction away from the source 401.
  • Covering more parts of the active layer 20 further increases the size of the source electrode 401 for blocking water vapor from entering the active layer 20 , thereby reducing the risk of the active layer 20 failing due to the entry of water vapor.
  • the first conductive layer 30 further includes the drain electrode 50 which is in the same layer as the gate electrode 301 and is arranged at a distance.
  • the drain electrode 50 There is a first gap 01 between the projection on the substrate 10 and the projection of the gate 301 on the substrate 10 .
  • the gate electrode 301 is located on the side of the active layer 20 away from the substrate 10 to form a top gate structure.
  • the drain electrode 50 is also located on the side of the active layer 20 away from the substrate 10 .
  • the first conductive layer 30 is formed in the same layer as the gate electrode 301 and is spaced apart.
  • the source electrode 401 can also be extended to the side close to the drain electrode 50 to overlap the gate electrode 301.
  • a bottom gate structure is formed on the side of the active layer 20 close to the substrate 10.
  • the drain electrode 50 is also provided on the side of the active layer 20 away from the substrate 10 and is in the same layer as the gate electrode 301 and is spaced apart to form a first
  • the conductive layer 30 can also realize that the source electrode 401 extends to the side close to the drain electrode 50 to overlap the gate electrode 301 .
  • the drain electrode 50 and the gate electrode 301 in this embodiment are on the same layer and are spaced apart, that is, both are located on the same film layer. Furthermore, the composition materials of the two can be the same, so that the same process and photonics can be used.
  • the mask forms the first conductive layer 30 including the drain electrode 50 and the gate electrode 301 , which saves the types of photomasks required for manufacturing the display panel 100 and improves the manufacturing efficiency of the display panel 100 .
  • the same process and photomask can be used to form the first conductive layer 30 including the drain electrode 50 and the gate electrode 301, so that the drain electrode 50 and the gate electrode 301 can have Smaller resistance and higher conductivity.
  • the projection of the source 401 on the substrate 10 overlaps with the first gap 01 .
  • the gate electrode 301 overlaps with the channel portion 201, and the gate electrode 301 is placed close to the source electrode 401 and the drain electrode 50.
  • the first gap may or may not overlap the active layer 20; further, in this embodiment, the end of the source electrode 401 close to the gate electrode 301 overlaps with the first gap, that is, the source electrode 401 can be considered to be close to the drain electrode 301.
  • One side of the electrode 50 extends to overlap the first gap. It can be understood that the source electrode 401, in addition to blocking the gate electrode 301, further blocks the first gap, which can reduce the risk of water vapor entering from the first gap, thereby reducing The water vapor entering the active layer 20 further reduces the risk of failure of the active layer 20 due to the entry of water vapor.
  • the relative positions of the source electrode 401 and the first conductive layer 30 are not limited.
  • the first conductive layer 30 may be located on the side of the source electrode 401 close to the substrate 10 (as shown in FIGS. 1 and 4 ).
  • the gate electrode 301 is located on the active layer 20 close to the substrate 10
  • a bottom gate structure is formed on one side of the source electrode 401, and one end of the source electrode 401 close to the gate electrode 301 is overlapped with the first gap. It is still possible to increase the size of the source electrode 401 for blocking water vapor from entering the active layer 20; for another example, the first The conductive layer 30 may be located on the side of the source electrode 401 away from the substrate 10. At this time, the water vapor flowing in from the first gap may be blocked by the source electrode 401 overlapping the first gap in the second conductive layer 40.
  • the first conductive layer 30 is located between the second conductive layer 40 and the active layer 20
  • the display panel 100 further includes: passivation Layer 60 is located between the first conductive layer 30 and the second conductive layer 40.
  • the conductive part 202 includes a first conductive part 2021, located between the first conductive part 2021 and the channel.
  • the concentration is greater than the concentration of hydrogen element in the channel portion 201 .
  • the first gap 01 may be used to enable the passivation layer 60 to provide hydrogen element to the active layer 20 .
  • the composition material of the passivation layer 60 may include but is not limited to silicon nitride, silicon oxide, and silicon oxynitride, and the passivation layer 60 may allow the diffusion of hydrogen element. Furthermore, the passivation layer 60 may also include hydrogen element. . It can be understood that the passivation layer 60 in this embodiment is located between the first conductive layer 30 and the second conductive layer 40, that is, the first gap overlaps the passivation layer 60, that is, the passivation layer 60 fills the first gap. The inner passivation layer 60 can separate and block the first conductive layer 30 and the second conductive layer 40 and combine with the first gap, so that the hydrogen element can enter into the active layer 20 through the passivation layer 60 and the first gap to achieve effective operation. Conductorization of the source layer.
  • the elements doped in the first conductive part 2021 and the second conductive part 2022 in this embodiment may be the same, for example, both may be doped with hydrogen element.
  • both ends of the active layer 20 can be doped with hydrogen element to form the first conductive portion 2021 with a larger concentration of hydrogen element.
  • the Hydrogen element is doped through the first gap and the corresponding opening structure to form a second conductive portion 2022 with a smaller concentration of hydrogen element.
  • a barrier layer is also included, located on the side of the passivation layer 60 away from the substrate 10 .
  • the barrier layer is made of aluminum oxide and titanium oxide. at least one of them. It can be understood that since at least the first conductive layer 30 and the passivation layer 60 are included between the barrier layer and the active layer 20, the barrier layer formed by at least one of, but not limited to, aluminum oxide and titanium oxide can effectively block contact.
  • the risk of reaction between the two is reduced; at the same time, in this embodiment, the content of hydrogen in the barrier layer formed by at least one of, but not limited to, aluminum oxide and titanium oxide is very small and Having a high barrier capability against water vapor can further improve the barrier capability against water vapor, thereby further reducing the risk of failure of the active layer 20 .
  • the second conductive layer 40 further includes a first electrode part 402 in the same layer as the source electrode 401 and arranged at intervals.
  • the first electrode part 402 is connected to In the drain electrode 50; wherein, as shown in FIG. 3, the projection of the first electrode portion 402 on the substrate 10 and the projection of the active layer 20 on the substrate 10 have a second gap 02 , the projection of the source electrode 401 on the substrate 10 overlaps with the second gap 02 .
  • the drain electrode 50 can be extended to overlap the first electrode part 402 and pass through the passivation layer.
  • the openings in 60 opposite to the overlapping portion of the drain electrode 50 and the first electrode portion 402 are filled with conductive material to connect the drain electrode 50 and the first electrode portion 402; for another example, when the drain electrode 50 and the first electrode portion 402 are overlapped , an opening connected between the drain electrode 50 and the first electrode part 402 may also be provided in the passivation layer 60 , and the opening may be filled with a conductive substance to connect the drain electrode 50 and the first electrode part 402 .
  • the composition material of the first electrode part 402 and the composition material of the source electrode 401 can be The same, so that the second conductive layer 40 including the first electrode part 402 and the source electrode 401 can be formed using the same process and mask, which saves the types of masks for manufacturing the display panel 100 and improves the manufacturing efficiency of the display panel 100;
  • one end of the source electrode 401 close to the gate electrode 301 overlaps the second gap 02 , that is, the source electrode 401 is continuously arranged and extends to completely cover the active layer 20 , so that the second conductive layer 40 overlaps the active layer 20 Part of it is fully occupied by the continuously arranged source electrodes 401, which further improves the ability of the source electrodes 401 to prevent water vapor from entering the active layer 20, and further reduces the risk of failure of the active layer 20.
  • the constituent materials of the source electrode 401 and the first electrode part 402 include at least one of metal and metal oxide.
  • the display panel 100 may further include a second electrode part 403 and a light-emitting device, and the light-emitting device is electrically connected between the second electrode part 403 and the first electrode part 402 .
  • the first electrode part 402 and the second electrode part 403 can be arranged in the same layer and spaced apart, and the light-emitting device can be located on the same side of the first electrode part 402 and the second electrode part 403 to emit light.
  • the anode of the device may be in contact with and connected to the first electrode part 402, and the cathode of the light emitting device may be in contact with and connected to the second electrode part 403, so that the voltage on the first electrode part 402 and the voltage on the second electrode part 403 are generated.
  • Emitting light under the action of the driving current for another example, the second electrode part 403 can be located on the side of the first electrode part 402 away from the substrate 10, and the light-emitting device can be located between the first electrode part 402 and the second electrode part 403.
  • the anode of the light-emitting device may be in contact with and connected to the first electrode part 402, and the cathode of the light-emitting device may be in contact with and connected to the second electrode part 403 to generate a voltage on the first electrode part 402 and a voltage on the second electrode part 403. It emits light under the action of driving current.
  • the first electrode part 402 and the source electrode 401 that are spaced apart from each other in the same layer may be made of the same material. Furthermore, in this embodiment, the material of the source electrode 401 and the first electrode part may be the same.
  • the constituent materials of 402 all include metal or metal oxide. Among them, for example, when the constituent materials of the two include metals, they can have higher barrier capabilities to further improve the barrier ability against water vapor, and can also have higher conductivity; for example, when the constituent materials of the two include metal oxides , can have a lower reflectivity to reduce the risk of reflecting external light to include but not limited to light-emitting devices, so as to improve the reliability and stability of the display screen of the display panel 100 .
  • the drain electrode 50 and the source electrode 401 are arranged in different layers from the gate electrode 301 , and the drain electrode 50 and the gate electrode 301 are arranged overlappingly.
  • the source electrode 401 and the drain electrode 50 are arranged in different layers to achieve insulation between the two. Based on this, the source electrode 401 is extended to the side close to the drain electrode 50 to overlap the gate electrode 301.
  • the size of the source electrode 401 for blocking water vapor from entering the active layer 20 can be increased, thereby reducing the risk of failure of the active layer 20 due to the entry of water vapor.
  • the drain electrode 50, the source electrode 401, and the gate electrode 301 are further arranged in different layers, and the drain electrode 50 is also extended to the side close to the source electrode 401 to overlap the gate electrode 301.
  • the projection of the drain electrode 50 on the active layer 20 can also overlap the channel portion 201 to cover the active layer 20
  • the size of the drain electrode 50 for blocking water vapor from entering the active layer 20 can be increased, thereby reducing the risk of failure of the active layer 20 due to the entry of water vapor.
  • the display panel 100 further includes: a first gate insulating layer 901 located between the active layer 20 and the first conductive layer 30 ; an insulating layer 903 located between the first gate insulating layer 901 and the first gate insulating layer 903 .
  • the drain electrode 50 is located between the insulating layer 903 and the second conductive layer 40; the passivation layer 60 is located between the drain electrode 50 and the second conductive layer 40. between the second conductive layers 40 ; wherein the projection of the drain electrode 50 on the substrate 10 overlaps with the projection of the gate electrode 301 on the substrate 10 .
  • the end of the source electrode 401 close to the drain electrode 50 overlaps with the end of the gate electrode 301 away from the source electrode 401 , and the end of the drain electrode 50 close to the source electrode 401 Overlapping the end of the gate 301 close to the source 401, that is, the projection of the source 401 on the substrate 10 completely covers the projection of the gate 301 on the substrate 10, and the drain The projection of the electrode 50 on the substrate 10 completely covers the projection of the gate electrode 301 on the substrate 10 .
  • the source electrode 401 extends to the side close to the drain electrode 50 to overlap the gate electrode 301
  • the drain electrode 50 extends to the side close to the source electrode 401 to overlap the gate electrode 301 , that is, both the source electrode 401 and the drain electrode 50 can completely cover the channel portion 201 to cover more parts of the active layer 20, further increasing the size of the source electrode 401 for blocking water vapor from entering the active layer 20, and reducing the The risk of failure of the active layer 20 due to the entry of water vapor is eliminated.
  • the display panel 100 further includes: a light-shielding layer 70 located on a side of the active layer 20 close to the substrate 10 , and the light-shielding layer 70 is located on the substrate 10 .
  • the projection on 10 covers the projection of the active layer 20 on the substrate 10 , and one end of the light shielding layer 70 is connected to at least one of the source electrode 401 and the drain electrode 50 .
  • the display panel 100 may also include a buffer layer 80 located between the light shielding layer 70 and the active layer 20 .
  • the display panel 100 may further include a buffer layer 80 located between the active layer 20 and the light shielding layer 70 .
  • the display panel 100 may further include a second gate insulating layer 902 between the active layer 20 and the bottom gate 301 .
  • the relative positional relationship between the source electrode 401 and the drain electrode 50 is not limited. It is based on the fact that the source electrode 401 is disposed close to a conductive portion 202 in the active layer 20 , and the drain electrode 50 is close to the conductive portion 202 in the active layer 20 . Another conductive part 202 is provided. In this embodiment, the side part of the light-shielding layer 70 is connected to at least one of the source electrode 401 and the drain electrode 50.
  • the insulating layer 903 and the second gate insulating layer 902 are provided with via holes connected to the side of the light shielding layer 70 and at least one of the source electrode 401 and the drain electrode 50, and conductive substances are filled in the via holes to electrically connect the light shielding layer 70 to at least one of the source electrode 401 and the drain electrode 50.
  • layer 70 and at least one of the source electrode 401 and the drain electrode 50 are provided with via holes connected to the side of the light shielding layer 70 and at least one of the source electrode 401 and the drain electrode 50, and conductive substances are filled in the via holes to electrically connect the light shielding layer 70 to at least one of the source electrode 401 and the drain electrode 50.
  • the drain electrode 50 can also be replaced and arranged in the same layer as the light-shielding layer 70 .
  • the drain electrode 50 and the light-shielding layer 70 are arranged in the same layer, which can avoid adding the insulating drain electrode 50, the source electrode 401, and the gate electrode on the basis of realizing that the drain electrode 50 and the source electrode 401 are arranged in different layers from the gate electrode 301.
  • 301 is a film layer of at least one of the two, that is, it can further reduce the risk of failure of the active layer 20 due to the entry of water vapor and develop the thinner and lighter display panel 100 .
  • the conductive material in the via hole connected to the light-shielding layer 70 and at least one of the source electrode 401 and the drain electrode 50 can block the side of the active layer 20 to reduce
  • the risk of water vapor entering the active layer 20 from the side can be caused by the water vapor molecules adsorbed on the surface of the active layer 20 when the light-shielding layer 70 and at least one of the source electrode 401 and the drain electrode 50 form an equal potential.
  • the additional electric field is shielded to prevent the additional electric field from accelerating corrosion of the active layer 20 .
  • Embodiments of the present application also provide a method for manufacturing a display panel, which may include but is not limited to the following steps and combinations of the following steps.
  • Figure 5 is a schematic diagram of a scene of a method for manufacturing a display panel.
  • the light-shielding layer 70 can be a single layer made of Mo, or an "A/B" type composite film layer or an "A/B/C” type composite film layer made of a variety of materials, where A is located On B, B is located on C.
  • the light shielding layer 70 can be but not limited to a Mo/Al film layer, a Mo/Cu film layer, a MoTi/Cu film layer, a MoTi/Cu/MoTi film layer, or a Ti/Al/Ti film. layer, Ti/Cu/Ti film layer, Mo/Cu/IZO film layer, IZO/Cu/IZO film layer or Mo/Cu/ITO film layer.
  • the buffer layer 80 can be made by chemical vapor deposition, for example, it can be a single layer made of silicon oxide, or can include a single layer made of silicon oxide, and a nitrogen layer is used on the single layer made of silicon oxide.
  • a single layer made of silicon; the constituent materials of the semiconductor layer 209 may include but are not limited to metal oxides with low leakage current such as IGZO, IGTO, IGZO, IGO, IZO, AIZO or ATZO.
  • first gate insulating film on the buffer layer 80 and the semiconductor layer 209, and patterning a portion of the first gate insulating film corresponding to both sides of the semiconductor layer 209 and a portion corresponding to the side of the light shielding layer 70 to form a third gate insulating film.
  • first holes 001 to form a first gate insulating layer 901 and conducting a conductive treatment on the portions on both sides of the semiconductor layer 209 through the two first holes 001 corresponding to both sides of the semiconductor layer 209 to form a first conductive portion. 2021.
  • the first gate insulating layer 901 can be a single layer made of silicon oxide or silicon nitride, or an "A/B" type composite film made of multiple materials or an "A/B/C” layer. "type composite film layer, in which A is located on B and B is located on C.
  • the first gate insulating layer 901 can be but is not limited to an Al2O3/SiNx/SiOx film layer or a SiOx/SiNx/SiOx film layer; conductorization treatment It can be, but is not limited to, hydrogen doping treatment.
  • the three first holes 001 formed corresponding to the side portion of the light-shielding layer 70 can also extend to be located in the buffer layer 80 .
  • the first conductive layer 30 includes the gate electrode 301 and the drain electrode 50.
  • the first conductive layer 30 can be a single layer made of Mo, or an "A/B" type composite film layer or an "A/B/C” type composite film layer made of a variety of materials, where A is located on B, and B is located on C.
  • the first conductive layer 30 can be but is not limited to a Mo/Al film layer, a Mo/Cu film layer, a MoTi/Cu film layer, a MoTi/Cu/MoTi film layer, a Ti/ Al/Ti film layer, Ti/Cu/Ti film layer, Mo/Cu/IZO film layer, IZO/Cu/IZO film layer or Mo/Cu/ITO film layer.
  • the passivation layer 60 can be a single layer made of silicon oxide, silicon nitride or silicon oxynitride, or an "A/B" type composite film made of multiple materials, where A is located on B.
  • the passivation layer 60 may be but is not limited to SiNx/SiOx.
  • the active layer 20 can be conductively formed by hydrogen diffusion in the passivation film to form the second conductive portion 2022, and then patterned to form at least three second holes 002.
  • a second conductive layer 40 is formed on the passivation layer 60 by patterning.
  • the second conductive layer 40 includes a first electrode part 402, a second electrode part 403 and a source electrode 401.
  • the second conductive layer 40 can be a single layer made of ITO or IZO, or an "A/B" type composite film layer or an "A/B/C” type composite film layer made of a variety of materials. , where A is located on B and B is located on C.
  • the second conductive layer 40 can be but is not limited to ITO/Ag/ITO film layer, IZO/Ag/IZO film layer, Mo/Cu film layer or MoTi/Cu/ MoTi film layer.
  • Embodiments of the present application also provide an electronic terminal, which includes the display panel as described in any one of the above.
  • the present application provides a display panel and an electronic terminal, including: a substrate; an active layer located on the substrate, including a channel portion and conductive portions located on both sides of the channel portion; a first conductive layer located on the The side of the active layer close to or away from the substrate includes a gate, and the projection of the gate on the substrate overlaps with the projection of the channel portion on the substrate; a second conductive layer is located on the side of the substrate.
  • the side of the active layer away from the substrate includes a source electrode connected to one of the conductive parts; wherein the source electrode and the drain electrode connected to the other conductive part are arranged in different layers, so The projection of the source electrode on the substrate overlaps with the projection of the gate electrode on the substrate.
  • the source electrode and the drain electrode connected to another conductive part are arranged in different layers, and the source electrode extends to the side close to the drain electrode, so as to realize the projection overlap of the source electrode and the gate electrode on the substrate.
  • the projection of the source on the active layer can also overlap the channel to cover more parts of the active layer, reducing the risk of damage to the active layer due to the entry of water vapor. Risk of failure.

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Abstract

一种显示面板（100）和电子终端，包括基板（10）、位于基板（10）上的有源层（20）、位于有源层（20）靠近或者远离基板（10）的一侧的第一导电层（30）、位于有源层（20）远离基板（10）的一侧的第二导电层（40），有源层（20）包括沟道部（201）、位于沟道部（201）两侧的导体化部（202），沟道部（201）与第一导电层（30）中的栅极（301）两者在基板（10）上的投影重叠，第二导电层（40）包括连接于其中一导体化部（202）的源极（401），其中，源极（401）和连接于另一导体化部（202）的漏极（50）异层设置，且源极（401）与栅极（301）两者在基板（10）上的投影重叠，实现源极（401）在有源层（20）上的投影还可以重叠于沟道部（201），以覆盖有源层（20）更多的部分，降低了有源层（20）因水汽进入而失效的风险。

Description

显示面板和电子终端 技术领域
本申请涉及显示技术领域，尤其涉及显示面板的制造技术领域，具体涉及显示面板和电子终端。
 背景技术
Mini LED(次毫米发光二极管)显示技术和Micro LED（微米发光二极管）显示技术广泛应用于中小型高附加价值显示器，具有高对比度、高亮度和轻薄外形等优点。
目前，考虑到节省光罩数量以及无缝拼接技术等因素，采用Mini LED显示技术或者Micro LED显示技术制作的电子终端中的用于分隔金属层的非金属层的数量较少，且封装时省略了盖板和框胶，导致外界水氧极易通过封装结构和膜层进入至晶体管器件的有源层中，降低了晶体管器件工作的可靠性。
因此，现有的采用Mini LED显示技术或者Micro LED显示技术制作的电子终端中晶体管器件失效的风险较大，急需改进。
 技术问题
本申请实施例提供显示面板和电子终端，以解决现有的采用Mini LED显示技术或者Micro LED显示技术制作的电子终端中晶体管器件失效的风险较大的技术问题。
 技术解决方案
本申请实施例提供显示面板，包括：
基板；
有源层，位于所述基板上，包括沟道部、位于所述沟道部两侧的导体化部；
第一导电层，位于所述有源层靠近或者远离所述基板的一侧，包括栅极，所述栅极在所述基板上的投影与所述沟道部在所述基板上的投影重叠；
第二导电层，位于所述有源层远离所述基板的一侧，包括连接于其中一所述导体化部的源极；
其中，所述源极和连接于另一所述导体化部的漏极异层设置，所述源极在所述基板上的投影与所述栅极在所述基板上的投影重叠。
本申请实施例还提供电子终端，所述电子终端包括如上文所述的显示面板。
 有益效果
本申请提供了显示面板和电子终端，包括：基板；有源层，位于所述基板上，包括沟道部、位于所述沟道部两侧的导体化部；第一导电层，位于所述有源层靠近或者远离所述基板的一侧，包括栅极，所述栅极在所述基板上的投影与所述沟道部在所述基板上的投影重叠；第二导电层，位于所述有源层远离所述基板的一侧，包括连接于其中一所述导体化部的源极；其中，所述源极和连接于另一所述导体化部的漏极异层设置，所述源极在所述基板上的投影与所述栅极在所述基板上的投影重叠。其中，本申请将源极和连接于另一导体化部的漏极异层设置，且源极向靠近漏极的一侧延伸，实现源极与栅极两者在基板上的投影重叠，以在保证源极和漏极绝缘设置的前提下，实现源极在有源层上的投影还可以重叠于沟道部，以覆盖有源层更多的部分，降低了有源层因水汽进入而失效的风险。
 附图说明
下面通过附图来对本申请进行进一步说明。需要说明的是，下面描述中的附图仅仅是用于解释说明本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的第一种显示面板的截面示意图。
图2为本申请实施例提供的第二种显示面板的截面示意图。
图3为本申请实施例提供的第三种显示面板的截面示意图。
图4为本申请实施例提供的第四种显示面板的截面示意图。
图5为本申请实施例提供的显示面板的制作方法的场景示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于完全覆盖不排他的包含。例如包含了一系列步骤或模块的过程、方法、系统、产品或设备没有限定于已列出的步骤或模块，而是可选地还包括没有列出的步骤或模块，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或模块。需要注意的是，本申请中用于描述位于不同层的两结构的“重叠设置”词汇，可以理解为对应的两结构在同一平面上的垂直投影为重叠关系。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
本申请实施例提供了显示面板，所述显示面板包括但不限于以下实施例以及以下实施例之间的组合。
在一实施例中，如图1至图4所示，所述显示面板100包括：基板10；有源层20，位于所述基板10上，包括沟道部201、位于所述沟道部201两侧的导体化部202；第一导电层30，位于所述有源层20靠近或者远离所述基板10的一侧，包括栅极301，所述栅极301与所述沟道部201重叠设置，由于两者不共面，此处也可以理解为所述栅极301在所述基板10上的投影与所述沟道部201在所述基板10上的投影重叠；第二导电层40，位于所述有源层20远离所述基板10的一侧，包括连接于其中一所述导体化部202的源极401；其中，所述源极401和连接于另一所述导体化部202的漏极50异层设置，所述源极401与所述栅极301重叠设置，由于两者不共面，此处也可以理解为所述源极401在所述基板10上的投影与所述栅极301在所述基板10上的投影重叠。
其中，基板10可以为柔性基板或者刚性基板，有源层20的组成材料可以包括半导体材料，例如非晶硅、多晶硅、有机半导体材料、金属氧化物，导体化部202可以通过在有源层20的两端掺杂包括但不限于氢元素、磷离子或者硼离子等粒子形成。其中，如图1和图2所示，本实施例中的栅极301可以位于有源层20远离基板10的一侧形成顶栅结构，如图4所示，栅极301也可以位于有源层20靠近基板10的一侧形成底栅结构。其中，在栅极301上加载电压后使得栅极301具有一电压，或者认为栅极301和有源层20中的沟道部201之间具有电压差，从而形成由栅极301指向基板10的电场，驱动有源层20中的电子和空穴在沟道部201内移动，从而导通源极401和漏极50。需要注意的是，水汽入侵有源层20后会导致有源层20的性能受到影响，降低了显示面板100中薄膜晶体管工作的可靠性。
具体的，如图1至图4所示，栅极301与沟道部201重叠设置，且源极401连接于有源层20的其中一导体化部202，漏极50连接于有源层20的另一导体化部202，即可以认为源极401靠近有源层20的其中一导体化部202而设置，漏极50靠近有源层20的另一导体化部202而设置，即栅极301靠近源极401和漏极50之间而设置。可以理解的，本实施例中将源极401和漏极50异层设置以实现两者的绝缘，基于此，将源极401向靠近漏极50的一侧延伸至重叠于栅极301，这样可以在保证源极401和漏极50绝缘设置的前提下，实现源极401在有源层20上的投影还可以重叠于沟道部201，以覆盖有源层20更多的部分，从而可以增加用于阻挡水汽进入至有源层20的源极401的尺寸，降低了有源层20因水汽进入而失效的风险。
在一实施例中，如图1至图4所示，所述源极401在所述基板10上的投影完全覆盖所述栅极301在所述基板10上的投影。具体的，结合上文论述可知，源极401向靠近漏极50的一侧延伸至重叠于栅极301，可以覆盖有源层20更多的部分；可以理解的，本实施例中的源极401靠近栅极301的一端超出栅极301远离源极401的一端，即源极401可以完全覆盖栅极301，也即源极401可以完全覆盖沟道部201，以在远离源极401的方向上覆盖有源层20更多的部分，进一步增加了用于阻挡水汽进入至有源层20的源极401的尺寸，降低了有源层20因水汽进入而失效的风险。
在一实施例中，如图1、图3和图4所示，所述第一导电层30还包括与所述栅极301同层且间隔设置的所述漏极50，所述漏极50在所述基板10上的投影和所述栅极301在所述基板10上的投影具有第一间隙01。具体的，例如图1所示，基于栅极301位于有源层20远离基板10的一侧形成顶栅结构，本实施例中将漏极50也设于有源层20远离基板10的一侧且与栅极301同层且间隔设置形成第一导电层30，同样可以实现源极401向靠近漏极50的一侧延伸至重叠于栅极301；又例如图4所示，基于栅极301位于有源层20靠近基板10的一侧形成底栅结构，本实施例中将漏极50也设于有源层20远离基板10的一侧且与栅极301同层且间隔设置形成第一导电层30，同样可以实现源极401向靠近漏极50的一侧延伸至重叠于栅极301。
可以理解的，本实施例中的漏极50和栅极301同层且间隔设置，即两者均位于同一膜层上，进一步的，两者的组成材料可以相同，使得可以采用同一道工艺和光罩形成包括漏极50和栅极301的第一导电层30，节省了显示面板100制作的光罩的种类，以及提高了显示面板100的制作效率。具体的，基于漏极50和栅极301同层且间隔设置，可以采用同一道工艺和光罩形成包括漏极50和栅极301的第一导电层30，使得漏极50和栅极301可以具有较小的电阻和较高的导电性能。
在一实施例中，如图1、图3和图4所示，所述源极401在所述基板10上的投影与所述第一间隙01重叠设置。具体的，结合上文论述可知，栅极301与沟道部201重叠设置，且栅极301靠近源极401和漏极50之间而设置，基于漏极50和栅极301同层且间隔设置可知，第一间隙可以重叠于或者不重叠于有源层20；进一步的，本实施例中的源极401靠近栅极301的一端与第一间隙重叠设置，即可以认为源极401向靠近漏极50的一侧延伸至重叠于第一间隙，可以理解的，源极401在遮挡了栅极301的基础上，进一步遮挡第一间隙，可以降低水汽自第一间隙进入的风险，从而减少了进入至有源层20的水汽，进一步降低了有源层20因水汽进入而失效的风险。
需要注意的是，本实施例中对源极401和第一导电层30的相对位置不做限定。例如，第一导电层30可以位于源极401靠近（如图1和图4所示）基板10的一侧，进一步的，即使如图4所示，栅极301位于有源层20靠近基板10的一侧形成底栅结构，源极401靠近栅极301的一端与第一间隙重叠设置，仍然可以实现增加用于遮挡水汽进入至有源层20的源极401的尺寸；又例如，第一导电层30可以位于源极401远离基板10的一侧，此时自第一间隙流入的水汽可以在第二导电层40被与第一间隙重叠设置的源极401所阻挡。
在一实施例中，如图1至图3所示，所述第一导电层30位于所述第二导电层40和所述有源层20之间，所述显示面板100还包括：钝化层60，位于所述第一导电层30和所述第二导电层40之间，所述导体化部202包括第一导体化部2021、位于所述第一导体化部2021和所述沟道部201之间的第二导体化部2022，所述第二导体化部2022在所述基板10上的投影重叠于所述第一间隙01，且所述第二导体化部2022中氢元素的浓度大于所述沟道部201中氢元素的浓度。其中，所述第一间隙01可以用于使所述钝化层60向所述有源层20提供氢元素。具体的，钝化层60的组成材料可以包括但不限于氮化硅、氧化硅、氮氧化硅，并且钝化层60可以允许氢元素扩散，进一步的，钝化层60中也可以包括氢元素。可以理解的，本实施例中的钝化层60位于第一导电层30和第二导电层40之间，即第一间隙重叠于钝化层60，也即钝化层60填充于第一间隙内钝化层60可以在区分阻隔第一导电层30和第二导电层40的同时，结合第一间隙，使得氢元素可以通过钝化层60和第一间隙进入至有源层20以实现有源层的导体化。
特别的，本实施例中的第一导体化部2021和第二导体化部2022中掺杂的元素可以相同，例如两者均可以掺杂氢元素。具体的，在形成钝化层60之前，可以先对有源层20的两端进行氢元素掺杂以形成氢元素浓度较大的第一导体化部2021，在形成钝化层60之后，可以通过第一间隙和相应的开孔结构进行氢元素掺杂，以形成氢元素浓度较小的第二导体化部2022。
在一实施例中，如图1至图3所示，还包括：阻隔层，位于所述钝化层60远离所述基板10的一侧，所述阻隔层的组成材料包括氧化铝、氧化钛中的至少一者。可以理解的，由于阻隔层与有源层20之间至少包括第一导电层30和钝化层60，可以有效阻隔采用包括但不限于氧化铝、氧化钛中的至少一者形成的阻隔层接触于有源层20，降低了两者发生反应的风险；与此同时，本实施例中采用包括但不限于氧化铝、氧化钛中的至少一者形成的阻隔层中氢元素的含量极少且对于水汽具有较高的阻隔能力，可以进一步提升对于水汽的阻挡能力，从而进一步降低有源层20失效的风险。
在一实施例中，如图1至图4所示，所述第二导电层40还包括与所述源极401同层且间隔设置的第一电极部402，所述第一电极部402连接于所述漏极50；其中，如图3所示，所述第一电极部402在所述基板10上的投影与所述有源层20在所述基板10上的投影具有第二间隙02，所述源极401在所述基板10上的投影与所述第二间隙02重叠。具体的，由于第一电极部402与有源层20在水平方向具有第二间隙02，例如图3所示，可以将漏极50延伸至重叠于第一电极部402，并且通过在钝化层60中与漏极50和第一电极部402重叠部分相对设置的开孔填充导电物质以连接漏极50和第一电极部402；又例如，漏极50与第一电极部402为重叠设置时，也可以在钝化层60中设置连通于漏极50和第一电极部402之间的开孔，并且在开孔填充导电物质以连接漏极50和第一电极部402。
可以理解的，本实施例中通过将第一电极部402设置为与有源层20在水平方向具有第二间隙02，同理，第一电极部402的组成材料和源极401的组成材料可以相同，使得可以采用同一道工艺和光罩形成包括第一电极部402和源极401的第二导电层40，节省了显示面板100制作的光罩的种类，以及提高了显示面板100的制作效率；进一步的，源极401靠近栅极301的一端重叠于第二间隙02，即将源极401连续设置，且延伸至完全覆盖有源层20，使得在第二导电层40重叠于有源层20的部分全部被连续设置的源极401占满，进一步提升了源极401对于水汽进入至有源层20的阻碍能力，进一步降低了有源层20失效的风险。
在一实施例中，如图1至图4所示，所述源极401的组成材料和所述第一电极部402的组成材料均包括金属、金属氧化物中的至少一者。具体的，显示面板100还可以包括第二电极部403和发光器件，发光器件电性连接于第二电极部403和第一电极部402之间。其中，例如图1至图4所示，第一电极部402和第二电极部403可以同层且间隔设置，且发光器件可以位于第一电极部402和第二电极部403的同一侧，发光器件的阳极可以接触并连接于第一电极部402，发光器件的阴极可以接触并连接于第二电极部403，以在第一电极部402上的电压和第二电极部403上的电压产生的驱动电流的作用下发光；又例如，第二电极部403可以位于第一电极部402远离基板10的一侧，发光器件可以位于第一电极部402和第二电极部403之间，同理，发光器件的阳极可以接触并连接于第一电极部402，发光器件的阴极可以接触并连接于第二电极部403，以在第一电极部402上的电压和第二电极部403上的电压产生的驱动电流的作用下发光。
具体的，结合上文论述，同层切间隔设置的第一电极部402和源极401两者的组成材料可以相同，进一步的，本实施例中的源极401的组成材料和第一电极部402的组成材料均包括金属或者金属氧化物。其中，例如两者的组成材料包括金属时，可以具有较高的阻隔能力以进一步提升对于水汽的阻挡能力，同时也可以具有较高的导电性；又例如两者的组成材料包括金属氧化物时，可以具有较低的反射率，以降低将外界的光线反射至包括但不限于发光器件的风险，以提升显示面板100显示画面的可靠性和稳定性于。
在一实施例中，如图2所示，所述漏极50、所述源极401均与所述栅极301异层设置，所述漏极50与所述栅极301重叠设置。具体的，结合上文论述可知，将源极401和漏极50异层设置以实现两者的绝缘，基于此，将源极401向靠近漏极50的一侧延伸至重叠于栅极301，进一步还可以增加用于阻挡水汽进入至有源层20的源极401的尺寸，降低了有源层20因水汽进入而失效的风险。
可以理解的，本实施例中进一步将漏极50、源极401、栅极301三者异层设置，并且将漏极50也向靠近源极401的一侧延伸至重叠于栅极301，同理，这样可以在保证栅极301、源极401和漏极50绝缘设置的前提下，实现漏极50在有源层20上的投影还可以重叠于沟道部201，以覆盖有源层20更多的部分，从而可以增加用于阻挡水汽进入至有源层20的漏极50的尺寸，降低了有源层20因水汽进入而失效的风险。
具体的，例如图2所示，显示面板100还包括：第一栅极绝缘层901，位于所述有源层20和所述第一导电层30之间；绝缘层903，位于所述第一导电层30和所述第二导电层40之间，所述漏极50位于所述绝缘层903和所述第二导电层40之间；钝化层60，位于所述漏极50和所述第二导电层40之间；其中，所述漏极50在所述基板10上的投影与所述栅极301在所述基板10上的投影重叠。
进一步的，如图2所示，所述源极401靠近所述漏极50一端重叠于所述栅极301远离所述源极401的一端，所述漏极50靠近所述源极401的一端重叠于所述栅极301靠近所述源极401的一端，也即所述源极401在所述基板10上的投影完全覆盖所述栅极301在所述基板10上的投影，所述漏极50在所述基板10上的投影完全覆盖所述栅极301在所述基板10上的投影。具体的，结合上文论述，本实施例中，源极401向靠近漏极50的一侧延伸至重叠于栅极301，漏极50向靠近源极401的一侧延伸至重叠于栅极301，即源极401和漏极50均可以完全覆盖沟道部201，以覆盖有源层20更多的部分，进一步增加了用于阻挡水汽进入至有源层20的源极401的尺寸，降低了有源层20因水汽进入而失效的风险。
在一实施例中，如图1至图4所示，显示面板100还包括：遮光层70，位于所述有源层20靠近所述基板10的一侧，所述遮光层70在所述基板10上的投影覆盖所述有源层20在所述基板10上的投影，所述遮光层70的一端连接于所述源极401、所述漏极50中的至少一者。具体的，显示面板100还可以包括位于遮光层70和有源层20之间的缓冲层80，如图1至图3所示，基于顶栅结构，显示面板100还可以包括位于有源层20和顶部的栅极301之间的第一栅极绝缘层901，再进一步的，如图2所示，基于栅极301和漏极50异层设置，栅极301和漏极50之间还可以设有绝缘层903；或者如图4所示，基于底栅结构，显示面板100还可以包括位于有源层20和底部的栅极301之间的第二栅极绝缘层902。
其中，本实施例中对源极401、漏极50的相对位置关系不做限定，基于源极401靠近有源层20中的一导体化部202设置，且漏极50靠近有源层20中的另一导体化部202设置，本实施例中将遮光层70的侧部连接于源极401、漏极50中的至少一者，结合上文论述，可以通过第一栅极绝缘层901、绝缘层903和第二栅极绝缘层902设置连接于遮光层70的侧部和源极401、漏极50中的至少一者的过孔，并且在过孔内填充导电物质以电性连接遮光层70和源极401、漏极50中的至少一者。
具体的，基于上文提及的遮光层70，对比图1至图4所示，可替换的，漏极50也可以替换为和遮光层70同层设置。可以理解的，漏极50和遮光层70同层设置，可以在实现漏极50、源极401均与栅极301异层设置的基础上，避免增加绝缘漏极50和源极401、栅极301两者中的至少一者的膜层，即可以兼顾进一步降低有源层20因水汽进入而失效的风险、显示面板100的轻薄化发展。
可以理解的，结合上文论述，本实施例中连接于遮光层70和源极401、漏极50中的至少一者的过孔内的导电物质可以遮挡有源层20的侧部，以降低水汽从侧边进入之有源层20的风险，同遮光层70和源极401、漏极50中的至少一者这两者形成等电位可以将吸附在有源层20表面的水汽分子所产生的附加电场所屏蔽，避免附加电场加速腐蚀有源层20。
本申请实施例还提供显示面板的制作方法，可以包括但不限于以下步骤以及以下步骤之间的组合，如图5为显示面板的制作方法的场景示意图。
S1，在基板10上通过图案化形成遮光层70。
其中，基板10和遮光层70可以参考上文相关的描述。具体的，遮光层70可以为采用Mo制作的单层膜层，或者为采用多种材料制作的“A/B”型复合膜层或者“A/B/C”型复合膜层，其中A位于B上，B位于C上，例如，遮光层70可以为但不限于Mo/Al膜层、Mo/Cu膜层、MoTi/Cu膜层、MoTi/Cu/MoTi膜层、Ti/Al/Ti膜层、Ti/Cu/Ti膜层、Mo/Cu/IZO膜层、IZO/Cu/IZO膜层或Mo/Cu/ITO膜层。
S2，在遮光层70和基板10上形成缓冲层80，以及在缓冲层80上通过图案化形成半导体层209。
其中，缓冲层80可以参考上文相关的描述。具体的，缓冲层80可以通过化学气相沉积制作，例如可以为采用氧化硅制作的单层膜层，或可以包括氧化硅制作的单层膜层、位于氧化硅制作的单层膜层上采用氮化硅制作的单层膜层；半导体层209的组成材料可以包括但不限于IGZO、IGTO、IGZO、IGO、IZO、AIZO或ATZO等漏电流较低的金属氧化物。
 S3，在缓冲层80和半导体层209形成第一栅极绝缘膜，以及通过图案化在第一栅极绝缘膜对应于半导体层209两侧的部分、对应于遮光层70侧部的部分形成三个第一孔001，以形成第一栅极绝缘层901，以及通过对应于半导体层209两侧的部分两第一孔001对半导体层209两侧的部分进行导体化处理形成第一导体化部2021。
其中，第一栅极绝缘层901和第一导体化部2021可以参考上文相关的描述。具体的，第一栅极绝缘层901可以为采用氧化硅或者氮化硅制作的单层膜层，或者为采用多种材料制作的“A/B”型复合膜层或者“A/B/C”型复合膜层，其中A位于B上，B位于C上，例如，第一栅极绝缘层901可以为但不限于Al2O3/SiNx/SiOx膜层，SiOx/SiNx/SiOx膜层；导体化处理可以为但不限于掺杂氢元素处理。进一步的，对应于遮光层70侧部的部分形成三个第一孔001还可以延伸至位于缓冲层80内。
 S4，在第一栅极绝缘层901上通过图案化形成第一导电层30，第一导电层30包括栅极301和漏极50。
其中，第一导电层30、栅极301和漏极50可以参考上文相关的描述。具体的，第一导电层30可以为采用Mo制作的单层膜层，或者为采用多种材料制作的“A/B”型复合膜层或者“A/B/C”型复合膜层，其中A位于B上，B位于C上，例如，第一导电层30可以为但不限于Mo/Al膜层、Mo/Cu膜层、MoTi/Cu膜层、MoTi/Cu/MoTi膜层、Ti/Al/Ti膜层、Ti/Cu/Ti膜层、Mo/Cu/IZO膜层、IZO/Cu/IZO膜层或Mo/Cu/ITO膜层。
 S5，在第一导电层30和第一栅极绝缘层901形成钝化膜，以及通过图案化在钝化膜至少对应于漏极50的部分、对应于另外两第一孔001的部分形成三个第二孔002，以形成钝化层60。
其中，钝化层60可以参考上文相关的描述。具体的，钝化层60可以为采用氧化硅、氮化硅或者氮氧化硅制作的单层膜层，或者为采用多种材料制作的“A/B”型复合膜层，其中A位于B上，例如，钝化层60可以为但不限于SiNx/SiOx。具体的，可以先通过钝化膜中氢扩散而对有源层20进行导体化形成第二导体化部2022，再进行图案化处理形成至少三个第二孔002。
 S6，在钝化层60上通过图案化形成第二导电层40，第二导电层40包括第一电极部402、第二电极部403和源极401。
其中，第一电极部402、第二电极部403和源极401可以参考上文相关的描述。具体的，第二导电层40可以为采用ITO或IZO制作的单层膜层，或者为采用多种材料制作的“A/B”型复合膜层或者“A/B/C”型复合膜层，其中A位于B上，B位于C上，例如，第二导电层40可以为但不限于ITO/Ag/ITO膜层、IZO/Ag/IZO膜层、Mo/Cu膜层或MoTi/Cu/MoTi膜层。
本申请实施例还提供电子终端，所述电子终端包括如上文任一项所述的显示面板。
本申请提供了显示面板和电子终端，包括：基板；有源层，位于所述基板上，包括沟道部、位于所述沟道部两侧的导体化部；第一导电层，位于所述有源层靠近或者远离所述基板的一侧，包括栅极，所述栅极在所述基板上的投影与所述沟道部在所述基板上的投影重叠；第二导电层，位于所述有源层远离所述基板的一侧，包括连接于其中一所述导体化部的源极；其中，所述源极和连接于另一所述导体化部的漏极异层设置，所述源极在所述基板上的投影与所述栅极在所述基板上的投影重叠。其中，本申请将源极和连接于另一导体化部的漏极异层设置，且源极向靠近漏极的一侧延伸，实现源极与栅极两者在基板上的投影重叠，以在保证源极和漏极绝缘设置的前提下，实现源极在有源层上的投影还可以重叠于沟道部，以覆盖有源层更多的部分，降低了有源层因水汽进入而失效的风险。
以上对本申请实施例所提供的显示面板和电子终端进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其中，包括：
    基板；
    有源层，位于所述基板上，包括沟道部、位于所述沟道部两侧的导体化部；
    第一导电层，位于所述有源层靠近或者远离所述基板的一侧，包括栅极，所述栅极在所述基板上的投影与所述沟道部在所述基板上的投影重叠；
    第二导电层，位于所述有源层远离所述基板的一侧，包括连接于其中一所述导体化部的源极；
    其中，所述源极和连接于另一所述导体化部的漏极异层设置，所述源极在所述基板上的投影与所述栅极在所述基板上的投影重叠；
    其中，所述源极在所述基板上的投影完全覆盖所述栅极在所述基板上的投影；
    其中，所述第一导电层还包括与所述栅极同层且间隔设置的所述漏极，所述漏极在所述基板上的投影和所述栅极在所述基板上的投影具有第一间隙。
  2. 根据权利要求1所述的显示面板，其中，所述源极在所述基板上的投影与所述第一间隙重叠。
  3. 根据权利要求1所述的显示面板，其中，所述第一导电层位于所述第二导电层和所述有源层之间，所述显示面板还包括：
    钝化层，位于所述第一导电层和所述第二导电层之间；
    其中，所述导体化部包括第一导体化部、位于所述第一导体化部和所述沟道部之间的第二导体化部，所述第二导体化部在所述基板上的投影重叠于所述第一间隙，且所述第二导体化部中氢元素的浓度大于所述沟道部中氢元素的浓度。
  4. 根据权利要求3所述的显示面板，其中，还包括：
    阻隔层，位于所述钝化层远离所述基板的一侧，所述阻隔层的组成材料包括氧化铝、氧化钛中的至少一者。
  5. 根据权利要求1所述的显示面板，其中，所述第二导电层还包括与所述源极同层且间隔设置的第一电极部，所述第一电极部连接于所述漏极；
    其中，所述第一电极部在所述基板上的投影与所述有源层在所述基板上的投影与具有第二间隙，所述源极在所述基板上的投影与所述第二间隙重叠。
  6. 根据权利要求5所述的显示面板，其中，所述源极的组成材料和所述第一电极部的组成材料均包括金属、金属氧化物中的至少一者。
  7. 根据权利要求1所述的显示面板，其中，还包括：
    第一栅极绝缘层，位于所述有源层和所述第一导电层之间；
    绝缘层，位于所述第一导电层和所述第二导电层之间，所述漏极位于所述绝缘层和所述第二导电层之间；
    钝化层，位于所述漏极和所述第二导电层之间；
    其中，所述漏极在所述基板上的投影与所述栅极在所述基板上的投影重叠。
  8. 一种显示面板，其中，包括：
    基板；
    有源层，位于所述基板上，包括沟道部、位于所述沟道部两侧的导体化部；
    第一导电层，位于所述有源层靠近或者远离所述基板的一侧，包括栅极，所述栅极在所述基板上的投影与所述沟道部在所述基板上的投影重叠；
    第二导电层，位于所述有源层远离所述基板的一侧，包括连接于其中一所述导体化部的源极；
    其中，所述源极和连接于另一所述导体化部的漏极异层设置，所述源极在所述基板上的投影与所述栅极在所述基板上的投影重叠。
  9. 根据权利要求8所述的显示面板，其中，所述源极在所述基板上的投影完全覆盖所述栅极在所述基板上的投影。
  10. 根据权利要求8所述的显示面板，其中，所述第一导电层还包括与所述栅极同层且间隔设置的所述漏极，所述漏极在所述基板上的投影和所述栅极在所述基板上的投影具有第一间隙。
  11. 根据权利要求10所述的显示面板，其中，所述源极在所述基板上的投影与所述第一间隙重叠。
  12. 根据权利要求10所述的显示面板，其中，所述第一导电层位于所述第二导电层和所述有源层之间，所述显示面板还包括：
    钝化层，位于所述第一导电层和所述第二导电层之间；
    其中，所述导体化部包括第一导体化部、位于所述第一导体化部和所述沟道部之间的第二导体化部，所述第二导体化部在所述基板上的投影重叠于所述第一间隙，且所述第二导体化部中氢元素的浓度大于所述沟道部中氢元素的浓度。
  13. 根据权利要求12所述的显示面板，其中，还包括：
    阻隔层，位于所述钝化层远离所述基板的一侧，所述阻隔层的组成材料包括氧化铝、氧化钛中的至少一者。
  14. 根据权利要求8所述的显示面板，其中，所述第二导电层还包括与所述源极同层且间隔设置的第一电极部，所述第一电极部连接于所述漏极；
    其中，所述第一电极部在所述基板上的投影与所述有源层在所述基板上的投影与具有第二间隙，所述源极在所述基板上的投影与所述第二间隙重叠。
  15. 根据权利要求14所述的显示面板，其中，所述源极的组成材料和所述第一电极部的组成材料均包括金属、金属氧化物中的至少一者。
  16. 根据权利要求8所述的显示面板，其中，还包括：
    第一栅极绝缘层，位于所述有源层和所述第一导电层之间；
    绝缘层，位于所述第一导电层和所述第二导电层之间，所述漏极位于所述绝缘层和所述第二导电层之间；
    钝化层，位于所述漏极和所述第二导电层之间；
    其中，所述漏极在所述基板上的投影与所述栅极在所述基板上的投影重叠。
  17. 根据权利要求16所述的显示面板，其中，所述源极在所述基板上的投影完全覆盖所述栅极在所述基板上的投影，所述漏极在所述基板上的投影完全覆盖所述栅极在所述基板上的投影。
  18. 根据权利要求8所述的显示面板，其中，还包括：
    第一栅极绝缘层，位于所述有源层和所述第一导电层之间；
    钝化层，位于所述第一导电层和所述第二导电层之间；
    遮光层，位于所述有源层靠近所述基板的一侧，所述遮光层在所述基板上的投影覆盖所述有源层在所述基板上的投影；
    其中，所述漏极和所述遮光层同层设置。
  19. 根据权利要求8所述的显示面板，其中，还包括：
    遮光层，位于所述有源层靠近所述基板的一侧，所述遮光层在所述基板上的投影覆盖所述有源层在所述基板上的投影，所述遮光层的一端连接于所述源极、所述漏极中的至少一者。
  20. 一种电子终端，其中，所述电子终端包括如权利要求8所述的显示面板。
PCT/CN2023/076080 2022-08-19 2023-02-15 显示面板和电子终端 WO2024036895A1 (zh)

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