WO2021088129A1 - Oled显示面板、显示装置及制备方法 - Google Patents

Oled显示面板、显示装置及制备方法 Download PDF

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Publication number
WO2021088129A1
WO2021088129A1 PCT/CN2019/119649 CN2019119649W WO2021088129A1 WO 2021088129 A1 WO2021088129 A1 WO 2021088129A1 CN 2019119649 W CN2019119649 W CN 2019119649W WO 2021088129 A1 WO2021088129 A1 WO 2021088129A1
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Prior art keywords
layer
electrode plate
oled display
light
buffer layer
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PCT/CN2019/119649
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English (en)
French (fr)
Inventor
林振国
周星宇
徐源竣
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Priority to US16/619,830 priority Critical patent/US11355571B2/en
Publication of WO2021088129A1 publication Critical patent/WO2021088129A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • This application relates to the field of display technology, and in particular to an OLED display panel and a method for manufacturing the OLED display panel.
  • the plasma gas of silicon nitride reacts with indium tin oxide or indium zinc oxide to produce dark lines.
  • the existing OLED display panel has a technical problem of dark lines.
  • the present application provides an OLED display panel, which is used to solve the technical problem that the existing OLED display panel has dark lines.
  • the embodiment of the present application provides an OLED display panel, which includes:
  • a light-emitting functional layer including a light-emitting area and a non-light-emitting area;
  • the pixel definition layer is arranged on the luminous function layer as shown;
  • the driving circuit layer includes a buffer layer, a first electrode plate, and a second electrode plate.
  • the buffer layer includes a first buffer layer and a second buffer layer.
  • the first buffer layer is disposed on the substrate.
  • the two buffer layers are arranged in the direction away from the substrate of the first buffer layer, the first electrode plate is arranged between the first buffer layer and the second buffer layer, and the second electrode plate is arranged on the second buffer layer. In the direction of the buffer layer away from the substrate, the first electrode plate and the second electrode plate form a storage capacitor.
  • the storage capacitor is disposed in the light-emitting area, and the first electrode plate and the second electrode plate are made of transparent materials.
  • the material of the first electrode plate is at least one of indium tin oxide or indium zinc oxide.
  • the driving circuit layer includes a light-shielding layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, an interlayer insulating layer, and a source-drain layer that are stacked.
  • the gate layer material is any one of molybdenum, aluminum, copper, titanium, etc., or one or more alloys.
  • the second electrode plate is formed by patterning an active layer.
  • the second electrode plate and the active layer of the source and drain doped regions are both disposed on the second buffer layer.
  • the light-shielding layer is formed by patterning a metal layer, and the material of the metal layer is copper or molybdenum.
  • the light-shielding layer serves as a wiring, which increases the design space of the wiring.
  • An embodiment of the present application provides an OLED display device, which includes an OLED display panel, an optical film, and a backlight.
  • the OLED display panel includes:
  • a light-emitting functional layer including a light-emitting area and a non-light-emitting area;
  • the pixel definition layer is arranged on the luminous function layer as shown;
  • the driving circuit layer includes a buffer layer, a first electrode plate, and a second electrode plate.
  • the buffer layer includes a first buffer layer and a second buffer layer.
  • the first buffer layer is disposed on the substrate.
  • the two buffer layers are arranged in the direction away from the substrate of the first buffer layer, the first electrode plate is arranged between the first buffer layer and the second buffer layer, and the second electrode plate is arranged on the second buffer layer. In the direction of the buffer layer away from the substrate, the first electrode plate and the second electrode plate form a storage capacitor.
  • the storage capacitor is disposed in the light-emitting area, and the first electrode plate and the second electrode plate are made of transparent materials.
  • the material of the first electrode plate is at least one of indium tin oxide or indium zinc oxide.
  • the driving circuit layer includes a light-shielding layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, an interlayer insulating layer, and a source-drain layer that are stacked.
  • the gate layer material is any one of molybdenum, aluminum, copper, titanium, etc., or one or more alloys.
  • the second electrode plate is formed by patterning an active layer.
  • the second electrode plate and the source and drain doped active layer are both disposed on the second buffer layer.
  • the light-shielding layer is formed by patterning a metal layer, the metal layer is made of copper or molybdenum, and the light-shielding layer serves as a wiring, which increases the design space of the wiring.
  • the embodiment of the present application provides a method for manufacturing an OLED display panel, including:
  • a second electrode plate an active layer, a gate insulating layer, a gate layer, an interlayer insulating layer, a source and drain layer, a light-emitting function layer, a pixel electrode layer, a pixel definition layer, a common electrode layer, and an encapsulation layer.
  • the step of forming the gate layer includes: depositing a metal layer on the gate insulating layer as the gate layer, and the metal material may be molybdenum, aluminum, or copper. , Titanium, etc., or one or more alloys.
  • the step of forming the second electrode plate includes: performing ion gas treatment on the entire surface, and for the metal oxide semiconductor material without the gate insulating layer and the gate layer protection above, After the treatment, the resistance is significantly reduced, forming a nitrogen ion conductor layer, and the metal oxide semiconductor material under the gate insulating layer is not processed. It maintains the semiconductor characteristics and can be used as the channel of the driving circuit layer.
  • the metal oxide located above the first electrode plate The semiconductor material is processed to form a second electrode plate of the storage capacitor.
  • the step of forming and depositing the source and drain layer includes: gas depositing a layer of metal as the source and drain layer, which can be molybdenum, aluminum, copper, titanium, etc., or a kind of Or multiple alloys with a thickness of 2000 to 8000 angstroms.
  • the present application provides an OLED display panel and a method for manufacturing an OLED display panel.
  • the OLED display panel includes a substrate, a driving circuit layer, a light-emitting function layer, and a pixel definition layer.
  • the light-emitting function layer includes a light-emitting area and a non-light-emitting area.
  • the pixel definition layer is disposed on the light-emitting function layer shown, the driving circuit layer includes a buffer layer, a first electrode plate and a second electrode plate, the buffer layer includes a first buffer layer and a second buffer layer, the first The buffer layer is disposed on the substrate, the second buffer layer is disposed in a direction away from the substrate of the first buffer layer, and the first electrode plate is disposed on the first buffer layer and the second buffer layer In between, the second electrode plate is arranged in the direction of the second buffer layer away from the substrate, the first electrode plate and the second electrode plate form a storage capacitor; the silicon nitride is deposited to form the first buffer layer When the first electrode plate has not been deposited and formed, the reduction reaction between the ion gas generated during the deposition of silicon nitride and the first electrode plate is avoided, and the technical problem of dark lines in the existing OLED display panel is solved.
  • FIG. 1 is a first schematic cross-sectional view of an OLED display panel provided by an embodiment of the application
  • FIG. 2 is a schematic diagram of patterning an OLED display panel provided by an embodiment of the application to form a second electrode plate;
  • FIG. 3 is a second schematic cross-sectional view of an OLED display panel provided by an embodiment of the application.
  • FIG. 4 is a third schematic cross-sectional view of an OLED display panel provided by an embodiment of the application.
  • FIG. 5 is a schematic diagram of a manufacturing method of an OLED display panel provided by an embodiment of the application.
  • the embodiments of the present application can solve this problem.
  • the OLED display panel provided by the present application includes:
  • a light-emitting functional layer 30, the light-emitting functional layer 30 includes a light-emitting area and a non-light-emitting area;
  • the pixel definition layer 40 is arranged on the light-emitting function layer 30 as shown;
  • the driving circuit layer 20 includes a buffer layer 202, a first electrode plate 208, and a second electrode plate 209.
  • the buffer layer 202 includes a first buffer layer 2001 and a second buffer layer 2002.
  • the second buffer layer 2002 is disposed on the first buffer layer 2001 in a direction away from the substrate 10
  • the first electrode plate 208 is disposed on the first buffer layer 2001 and the second buffer layer.
  • the second electrode plate 209 is arranged in a direction away from the substrate of the second buffer layer 2002, and the first electrode plate 208 and the second electrode plate 209 form a storage capacitor.
  • the OLED display panel includes:
  • a light-emitting functional layer including a light-emitting area and a non-light-emitting area;
  • the pixel definition layer is arranged on the luminous function layer as shown;
  • the driving circuit layer includes a buffer layer, a first electrode plate, and a second electrode plate.
  • the buffer layer includes a first buffer layer and a second buffer layer.
  • the first buffer layer is disposed on the substrate.
  • the two buffer layers are arranged in the direction away from the substrate of the first buffer layer, the first electrode plate is arranged between the first buffer layer and the first buffer layer, and the second electrode plate is arranged on the second buffer layer.
  • the first electrode plate and the second electrode plate form a storage capacitor; when silicon nitride is deposited to form the first buffer layer, the first electrode plate has not been deposited yet This avoids the reduction reaction between the ion gas generated during the deposition of silicon nitride and the first electrode plate, and solves the technical problem of dark lines in the existing OLED display panel.
  • the storage capacitor is arranged in the light-emitting area, and the first electrode plate 208 and the second electrode plate 209 are made of transparent materials.
  • the advantage of this arrangement is that the pixel size is reduced and the aperture ratio is increased. .
  • the size of the storage capacitor is the same as the size of the light-emitting area of the corresponding light-emitting function layer 30 above.
  • the size of the storage capacitor is smaller than the size of the light-emitting area of the corresponding light-emitting function layer 30 above.
  • the material of the first electrode plate 208 is at least one of indium tin oxide or indium zinc oxide.
  • the material of the second electrode plate 209 is at least one of indium gallium zinc oxide, indium zinc tin oxide, or indium gallium zinc tin oxide, and a material is deposited on the second buffer layer 2002 A layer of metal oxide semiconductor material, plasma gas treatment is performed on the entire surface of the semiconductor layer, and the semiconductor layer without the gate insulating layer and the gate layer protection above is treated as the second electrode plate 209.
  • the driving circuit layer 20 includes a light-shielding layer 201, a buffer layer 202, an active layer 203, a gate insulating layer 204, a gate layer 205, an interlayer insulating layer 206, and source and drain layers which are stacked.
  • Layer 207 The light-shielding layer 201, a buffer layer 202, an active layer 203, a gate insulating layer 204, a gate layer 205, an interlayer insulating layer 206, and source and drain layers which are stacked.
  • Layer 207 is stacked.
  • a whole layer is formed on the second buffer layer 2002 first, and then the active layer 203 and the second electrode plate 209 of the source and drain doped regions 2003 are patterned at the same time.
  • a whole layer is first formed on the second buffer layer 2002, and then the active layer 203 of the source and drain doped regions 2003 is patterned first, and then the second electrode is patterned ⁇ 209 ⁇ Board 209.
  • the second electrode plate 209 is formed by patterning the active layer 203.
  • the second electrode plate 209 and the source and drain doped regions 2003 active layer 203 are both disposed on the second buffer layer 2002.
  • the light-shielding layer 201 is formed by patterning a metal layer, the material of the metal layer is copper or molybdenum, and the light-shielding layer 201 serves as a wiring, which increases the design space of the wiring.
  • the gate layer 205 is patterned to form the second electrode plate 209.
  • a layer of metal is deposited on the gate insulating layer 204, and then the metal layer is patterned.
  • the gate electrode 2051 and the second electrode plate 209 are formed by chemical conversion.
  • the second electrode plate 209 is formed in the light-emitting area, and the storage capacitor area and the light-emitting area are combined.
  • a whole layer is formed on the gate insulating layer 204 first, and then the gate 2051 and the second electrode plate 209 are patterned at the same time.
  • a whole layer is formed on the second buffer layer 2002 first, and then the gate 2051 is patterned first, and then the second electrode plate 209 is patterned.
  • the source and drain layers 207 are patterned to form the second electrode plate 209.
  • a layer of metal is first deposited on the interlayer insulating layer 206, and then the metal layer is patterned to form the source and drain layers.
  • the source and drain layers 207 are patterned to form the second electrode plate 209.
  • a layer of metal is deposited on the interlayer insulating layer 206, and then the metal layer Patterning to form source and drain electrodes, and then patterning to form the second electrode plate 209.
  • the material of the first buffer layer 2001 is silicon nitride with a thickness of 300 to 10000 angstroms, and silicon nitride can be used as a copper diffusion barrier layer and a copper protection layer.
  • the material of the first buffer layer 2001 is silicon nitride, the thickness is 500 to 6000 angstroms, and it can be used as a contact layer of indium gallium zinc oxide.
  • the thickness of the second electrode plate 209 is 100 to 1000 angstroms, and the material is a metal oxide semiconductor material, and the entire surface is treated with ion gas to treat the semiconductor without gate insulating layer and gate layer protection. After processing, it will be used as the second electrode plate. After processing, the resistance will be significantly reduced to form a nitrogen ion conductor layer.
  • the metal oxide semiconductor material under the gate insulating layer 204 has not been processed to maintain semiconductor characteristics and can be used as a drive circuit layer 20 trench Then, the metal oxide semiconductor material located above the first electrode plate 208 forms the second electrode plate 209 of the storage capacitor after conducting treatment.
  • the gate insulating layer 204 is made of silicon nitride or silicon nitride or a multilayer structure film, with a thickness of 1000 to 3000 angstroms, and is mainly used for insulating Function to separate the active layer 203 and the gate layer 205.
  • the gate layer 205 is made of any one of molybdenum, aluminum, copper, titanium, etc., or the material is one or more alloys, and the thickness is 2000 to 10000 Amy.
  • the material of the interlayer insulating layer 206 is silicon nitride or silicon nitride or a multilayer structure film, and the thickness is 2000 angstroms to 10000 angstroms. Yellow light and etching are performed to form an interlayer insulating layer 206.
  • the source and drain layer 207 is made of any one of molybdenum, aluminum, copper, titanium, etc., or the material is one or more alloys, and the thickness is 2000 to 8000 angstroms. M, and then define the graph.
  • the passivation layer is made of silicon nitride or silicon nitride or a multilayer structure film with a thickness of 1000 to 5000 angstroms.
  • the first electrode layer of the storage capacitor is disposed between the first buffer layer 2001 and the second buffer layer 2002, which reduces the area of the storage capacitor and can increase the value of the storage capacitor.
  • the buffer layer 202 uses a laminated structure of the first buffer layer 2001 and the second buffer layer 2002 to avoid copper oxidation.
  • the present application also provides an OLED display device.
  • the OLED display device includes a display panel. As shown in FIG. 1, the display panel includes:
  • a light-emitting functional layer 30, the light-emitting functional layer 30 includes a light-emitting area and a non-light-emitting area;
  • the pixel definition layer 40 is arranged on the light-emitting function layer 30 as shown;
  • the driving circuit layer 20 includes a buffer layer 202, a first electrode plate 208, and a second electrode plate 209.
  • the buffer layer 202 includes a first buffer layer 2001 and a second buffer layer 2002.
  • the second buffer layer 2002 is disposed on the first buffer layer 2001 in a direction away from the substrate 10
  • the first electrode plate 208 is disposed on the first buffer layer 2001 and the second buffer layer.
  • the second electrode plate 209 is arranged in a direction away from the substrate of the second buffer layer 2002, and the first electrode plate 208 and the second electrode plate 209 form a storage capacitor.
  • the OLED display device includes an OLED display panel, and the OLED display panel includes:
  • a light-emitting functional layer including a light-emitting area and a non-light-emitting area;
  • the pixel definition layer is arranged on the luminous function layer as shown;
  • the driving circuit layer includes a buffer layer, a first electrode plate, and a second electrode plate.
  • the buffer layer includes a first buffer layer and a second buffer layer.
  • the first buffer layer is disposed on the substrate.
  • the two buffer layers are arranged in the direction away from the substrate of the first buffer layer, the first electrode plate is arranged between the first buffer layer and the first buffer layer, and the second electrode plate is arranged on the second buffer layer.
  • the first electrode plate and the second electrode plate form a storage capacitor; when silicon nitride is deposited to form the first buffer layer, the first electrode plate has not been deposited yet This avoids the reduction reaction between the ion gas generated during the deposition of silicon nitride and the first electrode plate, and solves the technical problem of dark lines in the existing OLED display panel.
  • the storage capacitor is disposed in the light-emitting area, and the first electrode plate 208 and the second electrode plate 209 are made of transparent materials, so that the pixel size is reduced and the opening is increased. rate.
  • the size of the storage capacitor is the same as the size of the light-emitting area of the corresponding light-emitting function layer 30 above.
  • the size of the storage capacitor is smaller than the size of the light-emitting area of the corresponding light-emitting function layer 30 above.
  • the material of the first electrode plate 208 is at least one of indium tin oxide or indium zinc oxide.
  • the material of the second electrode plate 209 is at least one of indium gallium zinc oxide, indium zinc tin oxide, or indium gallium zinc tin oxide, and a material is deposited on the second buffer layer 2002 A layer of metal oxide semiconductor material, plasma gas treatment is performed on the entire surface of the semiconductor layer, and the semiconductor layer without the gate insulating layer and the gate layer protection above is treated as the second electrode plate 209.
  • the driving circuit layer 20 includes a light-shielding layer 201, a buffer layer 202, an active layer 203, a gate insulating layer 204, a gate layer 205, an interlayer insulating layer 206, and source and drain layers which are stacked.
  • Layer 207 The light-shielding layer 201, a buffer layer 202, an active layer 203, a gate insulating layer 204, a gate layer 205, an interlayer insulating layer 206, and source and drain layers which are stacked.
  • Layer 207 is stacked.
  • a whole layer is formed on the second buffer layer 2002 first, and then the active layer 203 and the second electrode plate 209 of the source and drain doped regions 2003 are patterned at the same time.
  • a whole layer is first formed on the second buffer layer 2002, and then the active layer 203 of the source and drain doped regions 2003 is patterned first, and then the second electrode is patterned ⁇ 209 ⁇ Board 209.
  • the second electrode plate 209 is formed by patterning the active layer 203.
  • the second electrode plate 209 and the source and drain doped regions 2003 active layer 203 are both disposed on the second buffer layer 2002.
  • the light-shielding layer 201 is formed by patterning a metal layer, the material of the metal layer is copper or molybdenum, and the light-shielding layer 201 serves as a wiring, which increases the design space of the wiring.
  • the second electrode plate 209 is formed by patterning the gate layer 205, and a whole gate layer 205 is formed first, and then the gate layer 205 is patterned to form a gate 2051 and a second electrode plate 209, and the second electrode plate 209 is formed in the light-emitting area.
  • a whole layer is formed on the gate insulating layer 204 first, and then the gate 2051 and the second electrode plate 209 are patterned at the same time.
  • a whole layer is formed on the second buffer layer 2002 first, and then the gate 2051 is patterned first, and then the second electrode plate 209 is patterned.
  • the source and drain layers 207 are patterned to form the second electrode plate 209.
  • a layer of metal is deposited on the interlayer insulating layer 206, and then the metal layer is patterned.
  • a source electrode, a drain electrode, and a second electrode plate 209 are formed.
  • the source and drain layers 207 are patterned to form the second electrode plate 209.
  • a layer of metal is deposited on the interlayer insulating layer 206, and then the metal layer Patterning to form source and drain electrodes, and then patterning to form the second electrode plate 209.
  • the material of the first buffer layer 2001 is silicon nitride with a thickness of 300 to 10,000 angstroms, and silicon nitride can be used as a copper diffusion barrier layer and a copper protection layer.
  • the material of the first buffer layer 2001 is silicon nitride, the thickness is 500 to 6000 angstroms, and it can be used as a contact layer of indium gallium zinc oxide.
  • the thickness of the second electrode plate 209 is 100 to 1000 angstroms, and the material is a metal oxide semiconductor material, and the entire surface is treated with ion gas. There is no gate insulating layer 204 and gate 2051 metal protection on the upper side. The resistance of the metal oxide semiconductor material is significantly reduced after processing, and a nitrogen ion conductor layer is formed. The metal oxide semiconductor material under the gate insulating layer 204 has not been processed to maintain the semiconductor characteristics and can be used as the channel of the drive circuit layer 20. The metal oxide semiconductor material above the first electrode plate 208 forms the second electrode plate 209 of the storage capacitor after conducting treatment.
  • the gate insulating layer 204 is made of silicon nitride or silicon nitride or a multilayer structure film, with a thickness of 1000 to 3000 angstroms, and is mainly used for insulating Function to separate the active layer 203 and the gate layer 205.
  • the gate layer 205 is made of any one of molybdenum, aluminum, copper, titanium, etc., or the material is one or more alloys, and the thickness is 2000 to 10000 Amy.
  • the material of the interlayer insulating layer 206 is silicon nitride or silicon nitride or a multilayer structure film, and the thickness is 2000 angstroms to 10000 angstroms. Yellow light and etching are performed to form an interlayer insulating layer 206.
  • the source and drain layer 207 is made of any one of molybdenum, aluminum, copper, titanium, etc., or the material is one or more alloys, and the thickness is 2000 to 8000 angstroms. M, and then define the graph.
  • the passivation layer material is silicon nitride or silicon nitride or a multilayer structure film, with a thickness of 1000 to 5000 angstroms.
  • the first electrode layer of the storage capacitor is disposed between the first buffer layer 2001 and the second buffer layer 2002, which reduces the area of the storage capacitor and can increase the value of the storage capacitor.
  • the buffer layer 202 uses a laminated structure of the first buffer layer 2001 and the second buffer layer 2002 to avoid copper oxidation.
  • an embodiment of the present application also provides a method for manufacturing an OLED display panel, including:
  • the step of forming the second electrode plate 209 includes: depositing a layer of metal oxide semiconductor material on the second buffer layer, and performing ion gas treatment on the entire surface of the semiconductor layer, and there is no gate insulating layer on it. And the metal oxide semiconductor material protected by the gate layer to form a second electrode plate after processing.
  • the step of forming the metal layer of the gate 2051 includes: forming the metal layer of the gate 2051 by gas deposition.
  • the material may be molybdenum, aluminum, copper, titanium, etc., or one or more alloys, with a thickness of 2000 To 10,000 angstroms.
  • the step of forming the gate insulating layer 204 includes: first etching the metal pattern of the gate 2051 by using a yellow light, and then using the metal pattern of the gate 2051 for self-alignment, etching the gate insulating layer 204
  • the gate insulating layer 204 exists only under the film layer with the metal pattern of the gate 2051, and the gate insulating layer 204 is etched away in the rest.
  • the step of forming the second electrode plate 209 includes: performing ion gas treatment on the entire surface.
  • the resistance after the treatment is obvious
  • the metal oxide semiconductor material under the gate insulating layer 204 is not processed, and the semiconductor characteristics are maintained. It can be used as the channel of the driving circuit layer 20.
  • the metal oxide semiconductor material located above the first electrode plate 208 The material is processed to form the second electrode plate 209 of the storage capacitor.
  • the step of forming and depositing the interlayer insulating layer 206 includes: gas deposition to form the interlayer insulating layer 206, the material is silicon nitride, silicon nitride or a multilayer structure film, and the thickness is 2000 angstroms to 10000 angstroms Rice, then yellow light process and etching process.
  • the step of forming and depositing the source and drain layer 207 includes: gas depositing a layer of metal as the source and drain layer, which can be molybdenum, aluminum, copper, titanium, etc., or one or more alloys with a thickness 2000 to 8000 angstroms, and then define the graphics.
  • a layer of metal as the source and drain layer, which can be molybdenum, aluminum, copper, titanium, etc., or one or more alloys with a thickness 2000 to 8000 angstroms, and then define the graphics.
  • the present application provides an OLED display panel and a method for manufacturing an OLED display panel.
  • the OLED display panel includes a substrate, a driving circuit layer, a light-emitting function layer, and a pixel definition layer.
  • the light-emitting function layer includes a light-emitting area and a non-light-emitting area, and the pixel definition layer is arranged
  • the driving circuit layer includes a buffer layer, a first electrode plate and a second electrode plate
  • the buffer layer includes a first buffer layer and a second buffer layer
  • the first buffer layer is disposed on the substrate
  • the second The buffer layer is arranged in a direction away from the substrate of the first buffer layer
  • the first electrode plate is arranged between the first buffer layer and the second buffer layer
  • the second electrode plate is arranged in a direction away from the substrate of the second buffer layer.
  • the first electrode plate and the second electrode plate form a storage capacitor; when the silicon nitride is deposited to form the first buffer layer, the first electrode plate has not been deposited yet, which avoids the generation of ion gas during the deposition of silicon nitride and the reduction of the first electrode plate In response, the technical problem of dark lines in the existing OLED display panel is solved.

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Abstract

一种OLED显示面板，包括衬底（10）、驱动电路层（20）、发光功能层（30）以及像素定义层（40），发光功能层（30）包括发光区域和非发光区域，驱动电路层（20）包括缓冲层（202）、第一电极板（208）和第二电极板（209），第一电极板（208）和第二电极板（209）形成存储电容；在沉积氮化硅形成第一缓冲层（2001）时，未沉积第一电极板（208），避免了氮化硅沉积时产生离子气体与第一电极板（208）发生还原反应，解决了现有OLED显示面板存在暗纹的技术问题。

Description

OLED显示面板、显示装置及制备方法 技术领域
本申请涉及显示技术领域，尤其涉及一种OLED显示面板和OLED显示面板制备方法。
 背景技术
现有OLED显示面板，氮化硅沉积形成缓冲层的过程中，氮化硅的等离子气体与氧化铟锡或氧化铟锌反应，产生暗纹。
所以，现有OLED显示面板存在暗纹的技术问题。
 技术问题
本申请提供一种OLED显示面板，用于解决现有OLED显示面板存在暗纹的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种OLED显示面板，其包括：
衬底；
发光功能层，所述发光功能层包括发光区域和非发光区域；
像素定义层，设置于所示发光功能层上；
驱动电路层，包括缓冲层、第一电极板和第二电极板，所述缓冲层包括第一缓冲层和第二缓冲层，所述第一缓冲层设置于所述衬底上，所述第二缓冲层设置于所述第一缓冲层远离所述衬底的方向上，所述第一电极板设置于第一缓冲层和第二缓冲层之间，第二电极板设置于所述第二缓冲层远离所述基板的方向上，所述第一电极板和所述第二电极板形成存储电容。
在本申请提供的OLED显示面板中，所述存储电容设置于所述发光区域，所述第一电极板和所述第二电极板为透明材料。
在本申请提供的OLED显示面板中，所述第一电极板的材料为氧化铟锡或氧化铟锌中的至少一种。
在本申请提供的OLED显示面板中，所述驱动电路层包括层叠设置的遮光层、缓冲层、有源层、栅极绝缘层、栅极层、层间绝缘层、源漏极层。
在本申请提供的OLED显示面板中，所述栅极层材料为钼、铝、铜、钛等中的任意一种，或者是一种或多种合金。
在本申请提供的OLED显示面板中，所述第二电极板为有源层图案化形成。
在本申请提供的OLED显示面板中，所述第二电极板和源漏掺杂区的有源层均设置于第二缓冲层上。
在本申请提供的OLED显示面板中，所述遮光层为金属层图案化形成，金属层材料为铜或钼，所述遮光层充当走线，增加走线的设计空间。
本申请实施例提供一种OLED显示装置，其包括OLED显示面板、光学膜片、背光源，所述OLED显示面板包括：
衬底；
发光功能层，所述发光功能层包括发光区域和非发光区域；
像素定义层，设置于所示发光功能层上；
驱动电路层，包括缓冲层、第一电极板和第二电极板，所述缓冲层包括第一缓冲层和第二缓冲层，所述第一缓冲层设置于所述衬底上，所述第二缓冲层设置于所述第一缓冲层远离所述衬底的方向上，所述第一电极板设置于第一缓冲层和第二缓冲层之间，第二电极板设置于所述第二缓冲层远离所述基板的方向上，所述第一电极板和所述第二电极板形成存储电容。
在本申请提供的OLED显示装置中，所述存储电容设置于所述发光区域，所述第一电极板和所述第二电极板为透明材料。
在本申请提供的OLED显示装置中，所述第一电极板的材料为氧化铟锡或氧化铟锌中的至少一种。
在本申请提供的OLED显示装置中，所述驱动电路层包括层叠设置的遮光层、缓冲层、有源层、栅极绝缘层、栅极层、层间绝缘层、源漏极层。
在本申请提供的OLED显示装置中，所述栅极层材料为钼、铝、铜、钛等中的任意一种，或者是一种或多种合金。
在本申请提供的OLED显示装置中，所述第二电极板为有源层图案化形成。
在本申请提供的OLED显示装置中，所述第二电极板和源漏掺杂区有源层均设置于第二缓冲层上。
在本申请提供的OLED显示装置中，所述遮光层为金属层图案化形成，金属层材料为铜或钼，所述遮光层充当走线，增加走线的设计空间。
本申请实施例提供一种OLED显示面板制备方法，包括：
提供衬底；
在衬底上沉积一层金属，图案化形成遮光层；
沉积一层氮化硅形成第一缓冲层；
沉积氧化铟锡或氧化铟锌中的一种或者多种，形成一层半导体层，并图案化形成第一电极板；
沉积一层氮化硅形成第二缓冲层；
再形成第二电极板、有源层、栅极绝缘层、栅极层、层间绝缘层、源漏极层、发光功能层、像素电极层、像素定义层、公共电极层以及封装层。
在本申请提供的OLED显示面板制备方法中，所述形成栅极层的步骤包括：在栅极绝缘层上沉积一层金属层，作为栅极层，所述金属材料可以是钼、铝、铜、钛等，或者是一种或多种合金。
在本申请提供的OLED显示面板制备方法中，所述形成第二电极板的步骤包括：进行整面的离子气体处理，对于上方没有栅极绝缘层和栅极层保护的金属氧化物半导体材料，处理以后电阻明显降低，形成氮离子导体层，栅极绝缘层下方的金属氧化物半导体材料没有被处理到，保持半导体特性，可作为驱动电路层沟道，位于第一电极板上方的金属氧化物半导体材料经导体化处理后形成存储电容的第二电极板。
在本申请提供的OLED显示面板制备方法中，所述形成沉积源漏极层的步骤包括：气体沉积一层金属作为源漏极层，可以是钼、铝、铜、钛等，或者是一种或多种合金，厚度2000至8000埃米。
 有益效果
本申请提供一种OLED显示面板和OLED显示面板制备方法，该OLED显示面板包括衬底、驱动电路层、发光功能层以及像素定义层，所述发光功能层包括发光区域和非发光区域，所述像素定义层设置于所示发光功能层上，所述驱动电路层包括缓冲层、第一电极板和第二电极板，所述缓冲层包括第一缓冲层和第二缓冲层，所述第一缓冲层设置于所述衬底上，所述第二缓冲层设置于所述第一缓冲层远离所述衬底的方向上，所述第一电极板设置于第一缓冲层和第二缓冲层之间，第二电极板设置于所述第二缓冲层远离所述基板的方向上，所述第一电极板和所述第二电极板形成存储电容；在沉积氮化硅形成第一缓冲层时，还未沉积形成所述第一电极板，避免了氮化硅沉积时产生离子气体与第一电极板发生还原反应，解决了现有OLED显示面板存在暗纹的技术问题。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的OLED显示面板的第一种截面示意图；
图2为本申请实施例提供的OLED显示面板图案化形成第二电极板的示意图；
图3为本申请实施例提供的OLED显示面板的第二种截面示意图；
图4为本申请实施例提供的OLED显示面板的第三种截面示意图；
图5为本申请实施例提供的OLED显示面板制备方法的示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
针对现有OLED显示面板存在暗纹的技术问题，本申请实施例可以解决这个问题。
如图1所示，本申请提供的OLED显示面板包括：
衬底10；
发光功能层30，所述发光功能层30包括发光区域和非发光区域；
像素定义层40，设置于所示发光功能层30上；
驱动电路层20，包括缓冲层202、第一电极板208和第二电极板209，所述缓冲层202包括第一缓冲层2001和第二缓冲层2002，所述第一缓冲层2001设置于所述衬底10上，所述第二缓冲层2002设置于所述第一缓冲层2001远离所述衬底10的方向上，所述第一电极板208设置于第一缓冲层2001和第二缓冲层2002之间，第二电极板209设置于所述第二缓冲层2002远离所述基板的方向上，所述第一电极板208和所述第二电极板209形成存储电容。
在本实施例中，OLED显示面板包括：
衬底；
发光功能层，所述发光功能层包括发光区域和非发光区域；
像素定义层，设置于所示发光功能层上；
驱动电路层，包括缓冲层、第一电极板和第二电极板，所述缓冲层包括第一缓冲层和第二缓冲层，所述第一缓冲层设置于所述衬底上，所述第二缓冲层设置于所述第一缓冲层远离所述衬底的方向上，所述第一电极板设置于第一缓冲层和第一缓冲层之间，第二电极板设置于所述第二缓冲层远离所述衬底的方向上，所述第一电极板和所述第二电极板形成存储电容；在沉积氮化硅形成第一缓冲层时，还未沉积形成所述第一电极板，避免了氮化硅沉积时产生离子气体与第一电极板发生还原反应，解决了现有OLED显示面板存在暗纹的技术问题。
在一种实施例中，所述存储电容设置于所述发光区域，所述第一电极板208和所述第二电极板209为透明材料，这样设置的好处是使得像素尺寸降低，增加开口率。
在一种实施例中，在OLED显示面板中，所述存储电容的尺寸大小与上方对应的所述发光功能层30的发光区域大小相同。
在一种实施例中，在OLED显示面板中，所述存储电容的尺寸大小，小于上方对应的所述发光功能层30的发光区域大小。
在一种实施例中，所述第一电极板208的材料为氧化铟锡或氧化铟锌中的至少一种。
在一种实施例中，所述第二电极板209的材料为铟镓锌氧化物、铟锌锡氧化物或铟镓锌锡氧化物中的至少一种，在第二缓冲层2002上沉积一层金属氧化物半导体材料，对半导体层进行整面的等离子气体处理，对上方没有栅极绝缘层和栅极层保护的半导体层，处理后作为第二电极板209。
在一种实施例中，所述驱动电路层20包括层叠设置的遮光层201、缓冲层202、有源层203、栅极绝缘层204、栅极层205、层间绝缘层206、源漏极层207。
在一种实施例中，先在第二缓冲层2002上形成一整层，然后同时图案化形成源漏掺杂区2003的有源层203和第二电极板209。
在一种实施例中，如图2所示，先在第二缓冲层2002上形成一整层，然后先图案化形成源漏掺杂区2003的有源层203，再图案化形成第二电极板209。
在一种实施例中，所述第二电极板209为有源层203图案化形成。
在一种实施例中，所述第二电极板209和源漏掺杂区2003有源层203均设置于第二缓冲层2002上。
在一种实施例中，所述遮光层201为金属层图案化形成，金属层材料为铜或钼，所述遮光层201充当走线，增加走线的设计空间。
在一种实施例中，如图3所示，在OLED显示面板中，栅极层205图案化形成第二电极板209，先在栅极绝缘层204上沉积一层金属，再对金属层图案化形成栅极2051和第二电极板209，第二电极板209形成于发光区域，存储电容区域和发光区域合并。
在一种实施例中，先在栅极绝缘层204上形成一整层，然后同时图案化形成栅极2051和第二电极板209。
在一种实施例中，先在第二缓冲层2002上形成一整层，然后先图案化形成栅极2051，再图案化形成第二电极板209。
在一种实施例中，在OLED显示面板中，源漏极层207图案化形成第二电极板209，先在层间绝缘层206上沉积一层金属，再对金属层图案化，同时形成源极、漏极以及第二电极板209。
在一种实施例中，如图4所示，在OLED显示面板中，源漏极层207图案化形成第二电极板209，先在层间绝缘层206上沉积一层金属，再对金属层图案化，形成源极和漏极，然后再图案化形成第二电极板209。
在一种实施例中，在OLED显示面板中，第一缓冲层2001材料为氮化硅，厚度为300至10000埃米，同时氮化硅可以作为铜扩散阻挡层及铜保护层。
在一种实施例中，在OLED显示面板中，第一缓冲层2001材料为氮化硅，厚度为500至6000埃米，同时可以作为铟镓锌氧化物的接触层。
在一种实施例中，第二电极板209厚度为100至1000埃米，材料为金属氧化物半导体材料，进行整面的离子气体处理，对上方没有栅极绝缘层和栅极层保护的半导体层，处理后作为第二电极板，处理以后电阻明显降低，形成氮离子导体层，栅极绝缘层204下方的金属氧化物半导体材料没有被处理到，保持半导体特性，可作为驱动电路层20沟道，位于第一电极板208上方的金属氧化物半导体材料经导体化处理后形成存储电容的第二电极板209。
在一种实施例中，在OLED显示面板中，所述栅极绝缘层204材料为氮化硅或是氮化硅或是多层结构薄膜，厚度为1000至3000埃米，主要作用为绝缘的作用，将有源层203和栅极层205隔开。
在一种实施例中，在OLED显示面板中，所述栅极层205材料为钼、铝、铜、钛等中的任意一种，或者材料是一种或多种合金，厚度为2000至10000埃米。
在一种实施例中，在OLED显示面板中，层间绝缘层206材料为氮化硅或是氮化硅或是多层结构薄膜，厚度为2000埃米至10000埃米，在制程工艺上通过进行黄光和蚀刻形成层间绝缘层206。
在一种实施例中，在OLED显示面板中，源漏极层207材料为钼、铝、铜、钛等中的任意一种，或者材料是一种或多种合金，厚度为2000至8000埃米，然后定义出图形。
在一种实施例中，在OLED显示面板中，钝化层材料为氮化硅或是氮化硅或是多层结构薄膜，厚度为1000至5000埃米。
在一种实施例中，存储电容第一电极层设置于第一缓冲层2001和第二缓冲层2002之间，降低了存储电容面积，可以提高存储电容值大小。
在一种实施例中，缓冲层202使用第一缓冲层2001和第二缓冲层2002的叠层结构，避免了铜氧化。
本申请还提供一种OLED显示装置，所述OLED显示装置包括显示面板，如图1所示，显示面板包括：
衬底10；
发光功能层30，所述发光功能层30包括发光区域和非发光区域；
像素定义层40，设置于所示发光功能层30上；
驱动电路层20，包括缓冲层202、第一电极板208和第二电极板209，所述缓冲层202包括第一缓冲层2001和第二缓冲层2002，所述第一缓冲层2001设置于所述衬底10上，所述第二缓冲层2002设置于所述第一缓冲层2001远离所述衬底10的方向上，所述第一电极板208设置于第一缓冲层2001和第二缓冲层2002之间，第二电极板209设置于所述第二缓冲层2002远离所述基板的方向上，所述第一电极板208和所述第二电极板209形成存储电容。
在本实施例中，OLED显示装置包括OLED显示面板，OLED显示面板包括：
衬底；
发光功能层，所述发光功能层包括发光区域和非发光区域；
像素定义层，设置于所示发光功能层上；
驱动电路层，包括缓冲层、第一电极板和第二电极板，所述缓冲层包括第一缓冲层和第二缓冲层，所述第一缓冲层设置于所述衬底上，所述第二缓冲层设置于所述第一缓冲层远离所述衬底的方向上，所述第一电极板设置于第一缓冲层和第一缓冲层之间，第二电极板设置于所述第二缓冲层远离所述衬底的方向上，所述第一电极板和所述第二电极板形成存储电容；在沉积氮化硅形成第一缓冲层时，还未沉积形成所述第一电极板，避免了氮化硅沉积时产生离子气体与第一电极板发生还原反应，解决了现有OLED显示面板存在暗纹的技术问题。
在一种实施例中，在OLED显示装置中，所述存储电容设置于所述发光区域，所述第一电极板208和所述第二电极板209为透明材料，使得像素尺寸降低，增加开口率。
在一种实施例中，在OLED显示装置中，所述存储电容的尺寸大小与上方对应的所述发光功能层30的发光区域大小相同。
在一种实施例中，在OLED显示装置中，所述存储电容的尺寸大小，小于上方对应的所述发光功能层30的发光区域大小。
在一种实施例中，所述第一电极板208的材料为氧化铟锡或氧化铟锌中的至少一种。
在一种实施例中，所述第二电极板209的材料为铟镓锌氧化物、铟锌锡氧化物或铟镓锌锡氧化物中的至少一种，在第二缓冲层2002上沉积一层金属氧化物半导体材料，对半导体层进行整面的等离子气体处理，对上方没有栅极绝缘层和栅极层保护的半导体层，处理后作为第二电极板209。
在一种实施例中，所述驱动电路层20包括层叠设置的遮光层201、缓冲层202、有源层203、栅极绝缘层204、栅极层205、层间绝缘层206、源漏极层207。
在一种实施例中，先在第二缓冲层2002上形成一整层，然后同时图案化形成源漏掺杂区2003的有源层203和第二电极板209。
在一种实施例中，如图2所示，先在第二缓冲层2002上形成一整层，然后先图案化形成源漏掺杂区2003的有源层203，再图案化形成第二电极板209。
在一种实施例中，所述第二电极板209为有源层203图案化形成。
在一种实施例中，所述第二电极板209和源漏掺杂区2003有源层203均设置于第二缓冲层2002上。
在一种实施例中，所述遮光层201为金属层图案化形成，金属层材料为铜或钼，所述遮光层201充当走线，增加走线的设计空间。
在一种实施例中，如图3所示，在OLED显示装置中，所述第二电极板209为栅极层205图案化形成，先形成一整层栅极层205，再对栅极层205图案化形成栅极2051和第二电极板209，所述第二电极板209形成于发光区域。
在一种实施例中，先在栅极绝缘层204上形成一整层，然后同时图案化形成栅极2051和第二电极板209。
在一种实施例中，先在第二缓冲层2002上形成一整层，然后先图案化形成栅极2051，再图案化形成第二电极板209。
在一种实施例中，在OLED显示装置中，所述源漏极层207图案化形成第二电极板209，先在层间绝缘层206上沉积一层金属，再对金属层图案化，同时形成源极、漏极以及第二电极板209。
在一种实施例中，如图4所示，在OLED显示装置中，源漏极层207图案化形成第二电极板209，先在层间绝缘层206上沉积一层金属，再对金属层图案化，形成源极和漏极，然后再图案化形成第二电极板209。在一种实施例中，在OLED显示装置中，第一缓冲层2001材料为氮化硅，厚度为300至10000埃米，同时氮化硅可以作为铜扩散阻挡层及铜保护层。
在一种实施例中，在OLED显示装置中，第一缓冲层2001材料为氮化硅，厚度为500至6000埃米，同时可以作为铟镓锌氧化物的接触层。
在一种实施例中，第二电极板209厚度为100至1000埃米，材料为金属氧化物半导体材料，进行整面的离子气体处理，对于上方没有栅极绝缘层204和栅极2051金属保护的金属氧化物半导体材料，处理以后电阻明显降低，形成氮离子导体层，栅极绝缘层204下方的金属氧化物半导体材料没有被处理到，保持半导体特性，可作为驱动电路层20沟道，位于第一电极板208上方的金属氧化物半导体材料经导体化处理后形成存储电容的第二电极板209。
在一种实施例中，在OLED显示装置中，所述栅极绝缘层204材料为氮化硅或是氮化硅或是多层结构薄膜，厚度为1000至3000埃米，主要作用为绝缘的作用，将有源层203和栅极层205隔开。
在一种实施例中，在OLED显示装置中，所述栅极层205材料为钼、铝、铜、钛等中的任意一种，或者材料是一种或多种合金，厚度为2000至10000埃米。
在一种实施例中，在OLED显示装置中，层间绝缘层206材料为氮化硅或是氮化硅或是多层结构薄膜，厚度为2000埃米至10000埃米，在制程工艺上通过进行黄光和蚀刻形成层间绝缘层206。
在一种实施例中，在OLED显示装置中，源漏极层207材料为钼、铝、铜、钛等中的任意一种，或者材料是一种或多种合金，厚度为2000至8000埃米，然后定义出图形。
在一种实施例中，在OLED显示装置中，钝化层材料为氮化硅或是氮化硅或是多层结构薄膜，厚度为1000至5000埃米。
在一种实施例中，在OLED显示装置中，存储电容第一电极层设置于第一缓冲层2001和第二缓冲层2002之间，降低了存储电容面积，可以提高存储电容值大小。
在一种实施例中，在OLED显示装置中，缓冲层202使用第一缓冲层2001和第二缓冲层2002的叠层结构，避免了铜氧化。
如图5所示，本申请实施例还提供一种OLED显示面板制备方法，包括：
S1:提供衬底10；
S2:在衬底10上沉积一层金属，图案化形成遮光层201；
S3:沉积一层氮化硅形成第一缓冲层2001；
S4:沉积氧化铟锡或氧化铟锌中的一种或者多种，形成一层半导体层，并进行图案化形成第一电极板208；
S5:沉积一层氮化硅形成第二缓冲层2002；
S6:再形成第二电极板209、有源层203、栅极绝缘层204、栅极层205、层间绝缘层206、源漏极层207、发光功能层30、像素电极层、像素定义层40、公共电极层以及封装层。
在一种实施例中，形成第二电极板209的步骤包括：在第二缓冲层上沉积一层金属氧化物半导体材料，对半导体层进行整面的离子气体处理，对于上方没有栅极绝缘层和栅极层保护的金属氧化物半导体材料，处理后形成第二电极板。
在一种实施例中，形成栅极2051金属层的步骤包括：通过气体沉积形成栅极2051金属层，材料可以是钼、铝、铜、钛等，或者是一种或多种合金，厚度2000至10000埃米。
在一种实施例中，形成栅极绝缘层204的步骤包括：利用一道黄光，先蚀刻出栅极2051金属的图形，再利用栅极2051金属图形为自对准，蚀刻栅极绝缘层204，只在有栅极2051金属图形的膜层下方，才有栅极绝缘层204存在，其余地方栅极绝缘层204均被蚀刻掉。
在一种实施例中，形成第二电极板209的步骤包括：进行整面的离子气体处理，对于上方没有栅极绝缘层204和栅极2051金属保护的金属氧化物半导体材料，处理以后电阻明显降低，形成氮离子导体层，栅极绝缘层204下方的金属氧化物半导体材料没有被处理到，保持半导体特性，可作为驱动电路层20沟道，位于第一电极板208上方的金属氧化物半导体材料经导体化处理后形成存储电容的第二电极板209。
在一种实施例中，形成沉积层间绝缘层206的步骤包括：气体沉积形成层间绝缘层206，材料为氮化硅、氮化硅或是多层结构薄膜，厚度2000埃米至10000埃米，再进行黄光工艺和蚀刻工艺。
在一种实施例中，形成沉积源漏极层207的步骤包括：气体沉积一层金属作为源漏极层，可以是钼、铝、铜、钛等，或者是一种或多种合金，厚度2000至8000埃米，然后定义出图形。
根据上述实施例可知：
本申请提供一种OLED显示面板和OLED显示面板制备方法，该OLED显示面板包括衬底、驱动电路层、发光功能层以及像素定义层，发光功能层包括发光区域和非发光区域，像素定义层设置于所示发光功能层上，驱动电路层包括缓冲层、第一电极板和第二电极板，缓冲层包括第一缓冲层和第二缓冲层，第一缓冲层设置于衬底上，第二缓冲层设置于第一缓冲层远离衬底的方向上，第一电极板设置于第一缓冲层和第二缓冲层之间，第二电极板设置于第二缓冲层远离基板的方向上，第一电极板和第二电极板形成存储电容；在沉积氮化硅形成第一缓冲层时，还未沉积形成第一电极板，避免了氮化硅沉积时产生离子气体与第一电极板发生还原反应，解决了现有OLED显示面板存在暗纹的技术问题。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种OLED显示面板，其包括：
    衬底；
    发光功能层，所述发光功能层包括发光区域和非发光区域；
    像素定义层，设置于所示发光功能层上；
    驱动电路层，包括缓冲层、第一电极板和第二电极板，所述缓冲层包括第一缓冲层和第二缓冲层，所述第一缓冲层设置于所述衬底上，所述第二缓冲层设置于所述第一缓冲层远离所述衬底的方向上，所述第一电极板设置于第一缓冲层和第二缓冲层之间，第二电极板设置于所述第二缓冲层远离所述基板的方向上，所述第一电极板和所述第二电极板形成存储电容。
  2. 根据权利要求1所述的OLED显示面板，其中，所述存储电容设置于所述发光区域，所述第一电极板和所述第二电极板为透明材料。
  3. 根据权利要求2所述的OLED显示面板，其中，所述第一电极板的材料为氧化铟锡或氧化铟锌中的至少一种。
  4. 根据权利要求2所述的OLED显示面板，其中，所述驱动电路层包括层叠设置的遮光层、缓冲层、有源层、栅极绝缘层、栅极层、层间绝缘层、源漏极层。
  5. 根据权利要求4所述的OLED显示面板，其中，所述栅极层材料为钼、铝、铜、钛等中的任意一种，或者是一种或多种合金。
  6. 根据权利要求4所述的OLED显示面板，其中，所述第二电极板为有源层图案化形成。
  7. 根据权利要求4所述的OLED显示面板，其中，所述第二电极板和源漏掺杂区的有源层均设置于第二缓冲层上。
  8. 根据权利要求4所述的OLED显示面板，其中，金属层图案化形成所述遮光层，金属层材料为铜或钼，所述遮光层为走线层。
  9. 一种OLED显示装置，其包括OLED显示面板、光学膜片、背光源，所述OLED显示面板包括：
    衬底；
    发光功能层，所述发光功能层包括发光区域和非发光区域；
    像素定义层，设置于所示发光功能层上；
    驱动电路层，包括缓冲层、第一电极板和第二电极板，所述缓冲层包括第一缓冲层和第二缓冲层，所述第一缓冲层设置于所述衬底上，所述第二缓冲层设置于所述第一缓冲层远离所述衬底的方向上，所述第一电极板设置于第一缓冲层和第二缓冲层之间，第二电极板设置于所述第二缓冲层远离所述基板的方向上，所述第一电极板和所述第二电极板形成存储电容。
  10. 根据权利要求9所述的OLED显示装置，其中，所述存储电容设置于所述发光区域，所述第一电极板和所述第二电极板为透明材料。
  11. 根据权利要求10所述的OLED显示装置，其中，所述第一电极板的材料为氧化铟锡或氧化铟锌中的至少一种。
  12. 根据权利要求10所述的OLED显示装置，其中，所述驱动电路层包括层叠设置的遮光层、缓冲层、有源层、栅极绝缘层、栅极层、层间绝缘层、源漏极层。
  13. 根据权利要求12所述的OLED显示装置，其中，所述栅极层材料为钼、铝、铜、钛等中的任意一种，或者是一种或多种合金。
  14. 根据权利要求12所述的OLED显示装置，其中，所述第二电极板为有源层图案化形成。
  15. 根据权利要求12所述的OLED显示装置，其中，所述第二电极板和源漏掺杂区有源层均设置于第二缓冲层上。
  16. 根据权利要求12所述的OLED显示装置，其中，金属层图案化形成所述遮光层，金属层材料为铜或钼，所述遮光层为走线层。
  17. 一种OLED显示面板制备方法，其包括：
    提供衬底；
    在衬底上沉积一层金属，图案化形成遮光层；
    沉积一层氮化硅形成第一缓冲层；
    沉积氧化铟锡或氧化铟锌中的一种或者多种，形成一层半导体层，并图案化形成第一电极板；
    沉积一层氮化硅形成第二缓冲层；
    再形成第二电极板、有源层、栅极绝缘层、栅极层、层间绝缘层、源漏极层、发光功能层、像素电极层、像素定义层、公共电极层以及封装层。
  18. 根据权利要求17所述的OLED显示面板制备方法，其中，所述形成栅极层的步骤包括：在栅极绝缘层上沉积一层金属层，作为栅极层，所述金属材料可以是钼、铝、铜、钛等，或者是一种或多种合金。
  19. 根据权利要求17所述的OLED显示面板制备方法，其中，所述形成第二电极板的步骤包括：进行整面的离子气体处理，对于上方没有栅极绝缘层和栅极层保护的金属氧化物半导体材料，处理以后电阻明显降低，形成氮离子导体层，栅极绝缘层下方的金属氧化物半导体材料没有被处理到，保持半导体特性，可作为驱动电路层沟道，位于第一电极板上方的金属氧化物半导体材料经导体化处理后形成存储电容的第二电极板。
  20. 根据权利要求17所述的OLED显示面板制备方法，其中，所述形成沉积源漏极层的步骤包括：气体沉积一层金属作为源漏极层，可以是钼、铝、铜、钛等，或者是一种或多种合金，厚度2000至8000埃米。
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