WO2021088129A1 - Panneau d'affichage à oled, appareil d'affichage et procédé de préparation - Google Patents

Panneau d'affichage à oled, appareil d'affichage et procédé de préparation Download PDF

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Publication number
WO2021088129A1
WO2021088129A1 PCT/CN2019/119649 CN2019119649W WO2021088129A1 WO 2021088129 A1 WO2021088129 A1 WO 2021088129A1 CN 2019119649 W CN2019119649 W CN 2019119649W WO 2021088129 A1 WO2021088129 A1 WO 2021088129A1
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Prior art keywords
layer
electrode plate
oled display
light
buffer layer
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PCT/CN2019/119649
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English (en)
Chinese (zh)
Inventor
林振国
周星宇
徐源竣
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Priority to US16/619,830 priority Critical patent/US11355571B2/en
Publication of WO2021088129A1 publication Critical patent/WO2021088129A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • This application relates to the field of display technology, and in particular to an OLED display panel and a method for manufacturing the OLED display panel.
  • the plasma gas of silicon nitride reacts with indium tin oxide or indium zinc oxide to produce dark lines.
  • the existing OLED display panel has a technical problem of dark lines.
  • the present application provides an OLED display panel, which is used to solve the technical problem that the existing OLED display panel has dark lines.
  • the embodiment of the present application provides an OLED display panel, which includes:
  • a light-emitting functional layer including a light-emitting area and a non-light-emitting area;
  • the pixel definition layer is arranged on the luminous function layer as shown;
  • the driving circuit layer includes a buffer layer, a first electrode plate, and a second electrode plate.
  • the buffer layer includes a first buffer layer and a second buffer layer.
  • the first buffer layer is disposed on the substrate.
  • the two buffer layers are arranged in the direction away from the substrate of the first buffer layer, the first electrode plate is arranged between the first buffer layer and the second buffer layer, and the second electrode plate is arranged on the second buffer layer. In the direction of the buffer layer away from the substrate, the first electrode plate and the second electrode plate form a storage capacitor.
  • the storage capacitor is disposed in the light-emitting area, and the first electrode plate and the second electrode plate are made of transparent materials.
  • the material of the first electrode plate is at least one of indium tin oxide or indium zinc oxide.
  • the driving circuit layer includes a light-shielding layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, an interlayer insulating layer, and a source-drain layer that are stacked.
  • the gate layer material is any one of molybdenum, aluminum, copper, titanium, etc., or one or more alloys.
  • the second electrode plate is formed by patterning an active layer.
  • the second electrode plate and the active layer of the source and drain doped regions are both disposed on the second buffer layer.
  • the light-shielding layer is formed by patterning a metal layer, and the material of the metal layer is copper or molybdenum.
  • the light-shielding layer serves as a wiring, which increases the design space of the wiring.
  • An embodiment of the present application provides an OLED display device, which includes an OLED display panel, an optical film, and a backlight.
  • the OLED display panel includes:
  • a light-emitting functional layer including a light-emitting area and a non-light-emitting area;
  • the pixel definition layer is arranged on the luminous function layer as shown;
  • the driving circuit layer includes a buffer layer, a first electrode plate, and a second electrode plate.
  • the buffer layer includes a first buffer layer and a second buffer layer.
  • the first buffer layer is disposed on the substrate.
  • the two buffer layers are arranged in the direction away from the substrate of the first buffer layer, the first electrode plate is arranged between the first buffer layer and the second buffer layer, and the second electrode plate is arranged on the second buffer layer. In the direction of the buffer layer away from the substrate, the first electrode plate and the second electrode plate form a storage capacitor.
  • the storage capacitor is disposed in the light-emitting area, and the first electrode plate and the second electrode plate are made of transparent materials.
  • the material of the first electrode plate is at least one of indium tin oxide or indium zinc oxide.
  • the driving circuit layer includes a light-shielding layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, an interlayer insulating layer, and a source-drain layer that are stacked.
  • the gate layer material is any one of molybdenum, aluminum, copper, titanium, etc., or one or more alloys.
  • the second electrode plate is formed by patterning an active layer.
  • the second electrode plate and the source and drain doped active layer are both disposed on the second buffer layer.
  • the light-shielding layer is formed by patterning a metal layer, the metal layer is made of copper or molybdenum, and the light-shielding layer serves as a wiring, which increases the design space of the wiring.
  • the embodiment of the present application provides a method for manufacturing an OLED display panel, including:
  • a second electrode plate an active layer, a gate insulating layer, a gate layer, an interlayer insulating layer, a source and drain layer, a light-emitting function layer, a pixel electrode layer, a pixel definition layer, a common electrode layer, and an encapsulation layer.
  • the step of forming the gate layer includes: depositing a metal layer on the gate insulating layer as the gate layer, and the metal material may be molybdenum, aluminum, or copper. , Titanium, etc., or one or more alloys.
  • the step of forming the second electrode plate includes: performing ion gas treatment on the entire surface, and for the metal oxide semiconductor material without the gate insulating layer and the gate layer protection above, After the treatment, the resistance is significantly reduced, forming a nitrogen ion conductor layer, and the metal oxide semiconductor material under the gate insulating layer is not processed. It maintains the semiconductor characteristics and can be used as the channel of the driving circuit layer.
  • the metal oxide located above the first electrode plate The semiconductor material is processed to form a second electrode plate of the storage capacitor.
  • the step of forming and depositing the source and drain layer includes: gas depositing a layer of metal as the source and drain layer, which can be molybdenum, aluminum, copper, titanium, etc., or a kind of Or multiple alloys with a thickness of 2000 to 8000 angstroms.
  • the present application provides an OLED display panel and a method for manufacturing an OLED display panel.
  • the OLED display panel includes a substrate, a driving circuit layer, a light-emitting function layer, and a pixel definition layer.
  • the light-emitting function layer includes a light-emitting area and a non-light-emitting area.
  • the pixel definition layer is disposed on the light-emitting function layer shown, the driving circuit layer includes a buffer layer, a first electrode plate and a second electrode plate, the buffer layer includes a first buffer layer and a second buffer layer, the first The buffer layer is disposed on the substrate, the second buffer layer is disposed in a direction away from the substrate of the first buffer layer, and the first electrode plate is disposed on the first buffer layer and the second buffer layer In between, the second electrode plate is arranged in the direction of the second buffer layer away from the substrate, the first electrode plate and the second electrode plate form a storage capacitor; the silicon nitride is deposited to form the first buffer layer When the first electrode plate has not been deposited and formed, the reduction reaction between the ion gas generated during the deposition of silicon nitride and the first electrode plate is avoided, and the technical problem of dark lines in the existing OLED display panel is solved.
  • FIG. 1 is a first schematic cross-sectional view of an OLED display panel provided by an embodiment of the application
  • FIG. 2 is a schematic diagram of patterning an OLED display panel provided by an embodiment of the application to form a second electrode plate;
  • FIG. 3 is a second schematic cross-sectional view of an OLED display panel provided by an embodiment of the application.
  • FIG. 4 is a third schematic cross-sectional view of an OLED display panel provided by an embodiment of the application.
  • FIG. 5 is a schematic diagram of a manufacturing method of an OLED display panel provided by an embodiment of the application.
  • the embodiments of the present application can solve this problem.
  • the OLED display panel provided by the present application includes:
  • a light-emitting functional layer 30, the light-emitting functional layer 30 includes a light-emitting area and a non-light-emitting area;
  • the pixel definition layer 40 is arranged on the light-emitting function layer 30 as shown;
  • the driving circuit layer 20 includes a buffer layer 202, a first electrode plate 208, and a second electrode plate 209.
  • the buffer layer 202 includes a first buffer layer 2001 and a second buffer layer 2002.
  • the second buffer layer 2002 is disposed on the first buffer layer 2001 in a direction away from the substrate 10
  • the first electrode plate 208 is disposed on the first buffer layer 2001 and the second buffer layer.
  • the second electrode plate 209 is arranged in a direction away from the substrate of the second buffer layer 2002, and the first electrode plate 208 and the second electrode plate 209 form a storage capacitor.
  • the OLED display panel includes:
  • a light-emitting functional layer including a light-emitting area and a non-light-emitting area;
  • the pixel definition layer is arranged on the luminous function layer as shown;
  • the driving circuit layer includes a buffer layer, a first electrode plate, and a second electrode plate.
  • the buffer layer includes a first buffer layer and a second buffer layer.
  • the first buffer layer is disposed on the substrate.
  • the two buffer layers are arranged in the direction away from the substrate of the first buffer layer, the first electrode plate is arranged between the first buffer layer and the first buffer layer, and the second electrode plate is arranged on the second buffer layer.
  • the first electrode plate and the second electrode plate form a storage capacitor; when silicon nitride is deposited to form the first buffer layer, the first electrode plate has not been deposited yet This avoids the reduction reaction between the ion gas generated during the deposition of silicon nitride and the first electrode plate, and solves the technical problem of dark lines in the existing OLED display panel.
  • the storage capacitor is arranged in the light-emitting area, and the first electrode plate 208 and the second electrode plate 209 are made of transparent materials.
  • the advantage of this arrangement is that the pixel size is reduced and the aperture ratio is increased. .
  • the size of the storage capacitor is the same as the size of the light-emitting area of the corresponding light-emitting function layer 30 above.
  • the size of the storage capacitor is smaller than the size of the light-emitting area of the corresponding light-emitting function layer 30 above.
  • the material of the first electrode plate 208 is at least one of indium tin oxide or indium zinc oxide.
  • the material of the second electrode plate 209 is at least one of indium gallium zinc oxide, indium zinc tin oxide, or indium gallium zinc tin oxide, and a material is deposited on the second buffer layer 2002 A layer of metal oxide semiconductor material, plasma gas treatment is performed on the entire surface of the semiconductor layer, and the semiconductor layer without the gate insulating layer and the gate layer protection above is treated as the second electrode plate 209.
  • the driving circuit layer 20 includes a light-shielding layer 201, a buffer layer 202, an active layer 203, a gate insulating layer 204, a gate layer 205, an interlayer insulating layer 206, and source and drain layers which are stacked.
  • Layer 207 The light-shielding layer 201, a buffer layer 202, an active layer 203, a gate insulating layer 204, a gate layer 205, an interlayer insulating layer 206, and source and drain layers which are stacked.
  • Layer 207 is stacked.
  • a whole layer is formed on the second buffer layer 2002 first, and then the active layer 203 and the second electrode plate 209 of the source and drain doped regions 2003 are patterned at the same time.
  • a whole layer is first formed on the second buffer layer 2002, and then the active layer 203 of the source and drain doped regions 2003 is patterned first, and then the second electrode is patterned ⁇ 209 ⁇ Board 209.
  • the second electrode plate 209 is formed by patterning the active layer 203.
  • the second electrode plate 209 and the source and drain doped regions 2003 active layer 203 are both disposed on the second buffer layer 2002.
  • the light-shielding layer 201 is formed by patterning a metal layer, the material of the metal layer is copper or molybdenum, and the light-shielding layer 201 serves as a wiring, which increases the design space of the wiring.
  • the gate layer 205 is patterned to form the second electrode plate 209.
  • a layer of metal is deposited on the gate insulating layer 204, and then the metal layer is patterned.
  • the gate electrode 2051 and the second electrode plate 209 are formed by chemical conversion.
  • the second electrode plate 209 is formed in the light-emitting area, and the storage capacitor area and the light-emitting area are combined.
  • a whole layer is formed on the gate insulating layer 204 first, and then the gate 2051 and the second electrode plate 209 are patterned at the same time.
  • a whole layer is formed on the second buffer layer 2002 first, and then the gate 2051 is patterned first, and then the second electrode plate 209 is patterned.
  • the source and drain layers 207 are patterned to form the second electrode plate 209.
  • a layer of metal is first deposited on the interlayer insulating layer 206, and then the metal layer is patterned to form the source and drain layers.
  • the source and drain layers 207 are patterned to form the second electrode plate 209.
  • a layer of metal is deposited on the interlayer insulating layer 206, and then the metal layer Patterning to form source and drain electrodes, and then patterning to form the second electrode plate 209.
  • the material of the first buffer layer 2001 is silicon nitride with a thickness of 300 to 10000 angstroms, and silicon nitride can be used as a copper diffusion barrier layer and a copper protection layer.
  • the material of the first buffer layer 2001 is silicon nitride, the thickness is 500 to 6000 angstroms, and it can be used as a contact layer of indium gallium zinc oxide.
  • the thickness of the second electrode plate 209 is 100 to 1000 angstroms, and the material is a metal oxide semiconductor material, and the entire surface is treated with ion gas to treat the semiconductor without gate insulating layer and gate layer protection. After processing, it will be used as the second electrode plate. After processing, the resistance will be significantly reduced to form a nitrogen ion conductor layer.
  • the metal oxide semiconductor material under the gate insulating layer 204 has not been processed to maintain semiconductor characteristics and can be used as a drive circuit layer 20 trench Then, the metal oxide semiconductor material located above the first electrode plate 208 forms the second electrode plate 209 of the storage capacitor after conducting treatment.
  • the gate insulating layer 204 is made of silicon nitride or silicon nitride or a multilayer structure film, with a thickness of 1000 to 3000 angstroms, and is mainly used for insulating Function to separate the active layer 203 and the gate layer 205.
  • the gate layer 205 is made of any one of molybdenum, aluminum, copper, titanium, etc., or the material is one or more alloys, and the thickness is 2000 to 10000 Amy.
  • the material of the interlayer insulating layer 206 is silicon nitride or silicon nitride or a multilayer structure film, and the thickness is 2000 angstroms to 10000 angstroms. Yellow light and etching are performed to form an interlayer insulating layer 206.
  • the source and drain layer 207 is made of any one of molybdenum, aluminum, copper, titanium, etc., or the material is one or more alloys, and the thickness is 2000 to 8000 angstroms. M, and then define the graph.
  • the passivation layer is made of silicon nitride or silicon nitride or a multilayer structure film with a thickness of 1000 to 5000 angstroms.
  • the first electrode layer of the storage capacitor is disposed between the first buffer layer 2001 and the second buffer layer 2002, which reduces the area of the storage capacitor and can increase the value of the storage capacitor.
  • the buffer layer 202 uses a laminated structure of the first buffer layer 2001 and the second buffer layer 2002 to avoid copper oxidation.
  • the present application also provides an OLED display device.
  • the OLED display device includes a display panel. As shown in FIG. 1, the display panel includes:
  • a light-emitting functional layer 30, the light-emitting functional layer 30 includes a light-emitting area and a non-light-emitting area;
  • the pixel definition layer 40 is arranged on the light-emitting function layer 30 as shown;
  • the driving circuit layer 20 includes a buffer layer 202, a first electrode plate 208, and a second electrode plate 209.
  • the buffer layer 202 includes a first buffer layer 2001 and a second buffer layer 2002.
  • the second buffer layer 2002 is disposed on the first buffer layer 2001 in a direction away from the substrate 10
  • the first electrode plate 208 is disposed on the first buffer layer 2001 and the second buffer layer.
  • the second electrode plate 209 is arranged in a direction away from the substrate of the second buffer layer 2002, and the first electrode plate 208 and the second electrode plate 209 form a storage capacitor.
  • the OLED display device includes an OLED display panel, and the OLED display panel includes:
  • a light-emitting functional layer including a light-emitting area and a non-light-emitting area;
  • the pixel definition layer is arranged on the luminous function layer as shown;
  • the driving circuit layer includes a buffer layer, a first electrode plate, and a second electrode plate.
  • the buffer layer includes a first buffer layer and a second buffer layer.
  • the first buffer layer is disposed on the substrate.
  • the two buffer layers are arranged in the direction away from the substrate of the first buffer layer, the first electrode plate is arranged between the first buffer layer and the first buffer layer, and the second electrode plate is arranged on the second buffer layer.
  • the first electrode plate and the second electrode plate form a storage capacitor; when silicon nitride is deposited to form the first buffer layer, the first electrode plate has not been deposited yet This avoids the reduction reaction between the ion gas generated during the deposition of silicon nitride and the first electrode plate, and solves the technical problem of dark lines in the existing OLED display panel.
  • the storage capacitor is disposed in the light-emitting area, and the first electrode plate 208 and the second electrode plate 209 are made of transparent materials, so that the pixel size is reduced and the opening is increased. rate.
  • the size of the storage capacitor is the same as the size of the light-emitting area of the corresponding light-emitting function layer 30 above.
  • the size of the storage capacitor is smaller than the size of the light-emitting area of the corresponding light-emitting function layer 30 above.
  • the material of the first electrode plate 208 is at least one of indium tin oxide or indium zinc oxide.
  • the material of the second electrode plate 209 is at least one of indium gallium zinc oxide, indium zinc tin oxide, or indium gallium zinc tin oxide, and a material is deposited on the second buffer layer 2002 A layer of metal oxide semiconductor material, plasma gas treatment is performed on the entire surface of the semiconductor layer, and the semiconductor layer without the gate insulating layer and the gate layer protection above is treated as the second electrode plate 209.
  • the driving circuit layer 20 includes a light-shielding layer 201, a buffer layer 202, an active layer 203, a gate insulating layer 204, a gate layer 205, an interlayer insulating layer 206, and source and drain layers which are stacked.
  • Layer 207 The light-shielding layer 201, a buffer layer 202, an active layer 203, a gate insulating layer 204, a gate layer 205, an interlayer insulating layer 206, and source and drain layers which are stacked.
  • Layer 207 is stacked.
  • a whole layer is formed on the second buffer layer 2002 first, and then the active layer 203 and the second electrode plate 209 of the source and drain doped regions 2003 are patterned at the same time.
  • a whole layer is first formed on the second buffer layer 2002, and then the active layer 203 of the source and drain doped regions 2003 is patterned first, and then the second electrode is patterned ⁇ 209 ⁇ Board 209.
  • the second electrode plate 209 is formed by patterning the active layer 203.
  • the second electrode plate 209 and the source and drain doped regions 2003 active layer 203 are both disposed on the second buffer layer 2002.
  • the light-shielding layer 201 is formed by patterning a metal layer, the material of the metal layer is copper or molybdenum, and the light-shielding layer 201 serves as a wiring, which increases the design space of the wiring.
  • the second electrode plate 209 is formed by patterning the gate layer 205, and a whole gate layer 205 is formed first, and then the gate layer 205 is patterned to form a gate 2051 and a second electrode plate 209, and the second electrode plate 209 is formed in the light-emitting area.
  • a whole layer is formed on the gate insulating layer 204 first, and then the gate 2051 and the second electrode plate 209 are patterned at the same time.
  • a whole layer is formed on the second buffer layer 2002 first, and then the gate 2051 is patterned first, and then the second electrode plate 209 is patterned.
  • the source and drain layers 207 are patterned to form the second electrode plate 209.
  • a layer of metal is deposited on the interlayer insulating layer 206, and then the metal layer is patterned.
  • a source electrode, a drain electrode, and a second electrode plate 209 are formed.
  • the source and drain layers 207 are patterned to form the second electrode plate 209.
  • a layer of metal is deposited on the interlayer insulating layer 206, and then the metal layer Patterning to form source and drain electrodes, and then patterning to form the second electrode plate 209.
  • the material of the first buffer layer 2001 is silicon nitride with a thickness of 300 to 10,000 angstroms, and silicon nitride can be used as a copper diffusion barrier layer and a copper protection layer.
  • the material of the first buffer layer 2001 is silicon nitride, the thickness is 500 to 6000 angstroms, and it can be used as a contact layer of indium gallium zinc oxide.
  • the thickness of the second electrode plate 209 is 100 to 1000 angstroms, and the material is a metal oxide semiconductor material, and the entire surface is treated with ion gas. There is no gate insulating layer 204 and gate 2051 metal protection on the upper side. The resistance of the metal oxide semiconductor material is significantly reduced after processing, and a nitrogen ion conductor layer is formed. The metal oxide semiconductor material under the gate insulating layer 204 has not been processed to maintain the semiconductor characteristics and can be used as the channel of the drive circuit layer 20. The metal oxide semiconductor material above the first electrode plate 208 forms the second electrode plate 209 of the storage capacitor after conducting treatment.
  • the gate insulating layer 204 is made of silicon nitride or silicon nitride or a multilayer structure film, with a thickness of 1000 to 3000 angstroms, and is mainly used for insulating Function to separate the active layer 203 and the gate layer 205.
  • the gate layer 205 is made of any one of molybdenum, aluminum, copper, titanium, etc., or the material is one or more alloys, and the thickness is 2000 to 10000 Amy.
  • the material of the interlayer insulating layer 206 is silicon nitride or silicon nitride or a multilayer structure film, and the thickness is 2000 angstroms to 10000 angstroms. Yellow light and etching are performed to form an interlayer insulating layer 206.
  • the source and drain layer 207 is made of any one of molybdenum, aluminum, copper, titanium, etc., or the material is one or more alloys, and the thickness is 2000 to 8000 angstroms. M, and then define the graph.
  • the passivation layer material is silicon nitride or silicon nitride or a multilayer structure film, with a thickness of 1000 to 5000 angstroms.
  • the first electrode layer of the storage capacitor is disposed between the first buffer layer 2001 and the second buffer layer 2002, which reduces the area of the storage capacitor and can increase the value of the storage capacitor.
  • the buffer layer 202 uses a laminated structure of the first buffer layer 2001 and the second buffer layer 2002 to avoid copper oxidation.
  • an embodiment of the present application also provides a method for manufacturing an OLED display panel, including:
  • the step of forming the second electrode plate 209 includes: depositing a layer of metal oxide semiconductor material on the second buffer layer, and performing ion gas treatment on the entire surface of the semiconductor layer, and there is no gate insulating layer on it. And the metal oxide semiconductor material protected by the gate layer to form a second electrode plate after processing.
  • the step of forming the metal layer of the gate 2051 includes: forming the metal layer of the gate 2051 by gas deposition.
  • the material may be molybdenum, aluminum, copper, titanium, etc., or one or more alloys, with a thickness of 2000 To 10,000 angstroms.
  • the step of forming the gate insulating layer 204 includes: first etching the metal pattern of the gate 2051 by using a yellow light, and then using the metal pattern of the gate 2051 for self-alignment, etching the gate insulating layer 204
  • the gate insulating layer 204 exists only under the film layer with the metal pattern of the gate 2051, and the gate insulating layer 204 is etched away in the rest.
  • the step of forming the second electrode plate 209 includes: performing ion gas treatment on the entire surface.
  • the resistance after the treatment is obvious
  • the metal oxide semiconductor material under the gate insulating layer 204 is not processed, and the semiconductor characteristics are maintained. It can be used as the channel of the driving circuit layer 20.
  • the metal oxide semiconductor material located above the first electrode plate 208 The material is processed to form the second electrode plate 209 of the storage capacitor.
  • the step of forming and depositing the interlayer insulating layer 206 includes: gas deposition to form the interlayer insulating layer 206, the material is silicon nitride, silicon nitride or a multilayer structure film, and the thickness is 2000 angstroms to 10000 angstroms Rice, then yellow light process and etching process.
  • the step of forming and depositing the source and drain layer 207 includes: gas depositing a layer of metal as the source and drain layer, which can be molybdenum, aluminum, copper, titanium, etc., or one or more alloys with a thickness 2000 to 8000 angstroms, and then define the graphics.
  • a layer of metal as the source and drain layer, which can be molybdenum, aluminum, copper, titanium, etc., or one or more alloys with a thickness 2000 to 8000 angstroms, and then define the graphics.
  • the present application provides an OLED display panel and a method for manufacturing an OLED display panel.
  • the OLED display panel includes a substrate, a driving circuit layer, a light-emitting function layer, and a pixel definition layer.
  • the light-emitting function layer includes a light-emitting area and a non-light-emitting area, and the pixel definition layer is arranged
  • the driving circuit layer includes a buffer layer, a first electrode plate and a second electrode plate
  • the buffer layer includes a first buffer layer and a second buffer layer
  • the first buffer layer is disposed on the substrate
  • the second The buffer layer is arranged in a direction away from the substrate of the first buffer layer
  • the first electrode plate is arranged between the first buffer layer and the second buffer layer
  • the second electrode plate is arranged in a direction away from the substrate of the second buffer layer.
  • the first electrode plate and the second electrode plate form a storage capacitor; when the silicon nitride is deposited to form the first buffer layer, the first electrode plate has not been deposited yet, which avoids the generation of ion gas during the deposition of silicon nitride and the reduction of the first electrode plate In response, the technical problem of dark lines in the existing OLED display panel is solved.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

L'invention concerne un panneau d'affichage à diodes électroluminescentes organiques (OLED), comprenant un substrat (10), une couche de circuit d'attaque (20), une couche fonctionnelle électroluminescente (30) et une couche de définition de pixel (40), la couche fonctionnelle électroluminescente (30) comprenant une zone électroluminescente et une zone non électroluminescente ; et la couche de circuit d'attaque (20) comprend une couche tampon (202), une première plaque d'électrode (208) et une seconde plaque d'électrode (209), et la première plaque d'électrode (208) et la seconde plaque d'électrode (209) forment un condensateur de stockage. Lorsque le nitrure de silicium est déposé pour former une première couche tampon (2001), la première plaque d'électrode (208) n'est pas déposée, ce qui permet d'éviter une réaction de réduction entre un gaz ionique, produit lorsque le nitrure de silicium est déposé, et la première plaque d'électrode (208), et résolvant le problème technique de l'existence de franges sombres dans des panneaux d'affichage à OLED existants.
PCT/CN2019/119649 2019-11-06 2019-11-20 Panneau d'affichage à oled, appareil d'affichage et procédé de préparation WO2021088129A1 (fr)

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