CN105097941B - 一种薄膜晶体管及其制造方法、阵列基板、显示装置 - Google Patents
一种薄膜晶体管及其制造方法、阵列基板、显示装置 Download PDFInfo
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- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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Abstract
本发明实施例公开了一种薄膜晶体管及其制造方法、阵列基板、显示装置,属于半导体技术领域。该薄膜晶体管包括:基板、以及形成于基板上的有源层、源极、栅极和漏极,有源层的两端分别与所述源极和所述漏极连接,栅极包括顶栅和底栅,顶栅包括顶栅顶部和与顶栅顶部连接的顶栅侧部,顶栅顶部和底栅在垂直于基板的方向上相对设置,有源层夹设于顶栅顶部和底栅之间,顶栅侧部从顶栅顶部朝向基板延伸,有源层的侧壁至少部分被顶栅侧部围绕,栅极、源极和漏极均采用非透明的导电材料制成。本发明实施例的薄膜晶体管可以防止有源层被光照射,进而提高薄膜晶体管的特性。
Description
技术领域
本发明涉及半导体技术领域,特别涉及一种薄膜晶体管及其制造方法、阵列基板、显示装置。
背景技术
随着工艺技术的进步,薄膜晶体管已被大量应用在显示器之中,以适应显示器的薄型化和小型化等需求。在显示器的工作过程中,薄膜晶体管很容易被光照射到,而当光照射到其有源层时,会导致其关态漏电流增加,从而造成薄膜晶体管特性的劣化。
现有一种常见的薄膜晶体管,包括栅极、形成在栅极上的栅极绝缘层、形成在栅极绝缘层上的有源层、以及形成在有源层上并相互隔开的源极和漏极。在该结构中,栅极位于有源层的下方,能够阻挡从有源层下方照射的光,而从有源层上方照射的光没有被阻挡,可以从源极和漏极之间照射到有源层上,进而导致薄膜晶体管的特性劣化。
发明内容
本发明实施例提供了一种薄膜晶体管及其制造方法、阵列基板、显示装置,其可以防止有源层被光照射,进而提高薄膜晶体管的特性。所述技术方案如下:
第一方面,本发明实施例提供了一种薄膜晶体管,包括:基板、以及形成于所述基板上的有源层、源极、栅极和漏极,所述有源层的两端分别与所述源极和所述漏极连接,所述栅极包括顶栅和底栅,所述顶栅包括顶栅顶部和与所述顶栅顶部连接的顶栅侧部,所述有源层夹设于所述顶栅顶部和所述底栅之间,所述顶栅包括顶栅顶部和与所述顶栅顶部连接的顶栅侧部,所述有源层的侧壁至少部分被所述顶栅侧部围绕,所述栅极、所述源极和所述漏极均采用非透明的导电材料制成。
优选地,所述漏极包括漏极底层,所述漏极底层、底栅和所述源极同层间隔形成在所述基板上,且所述底栅位于所述源极和漏极底层之间。
进一步地,所述薄膜晶体管还包括栅极绝缘层,所述栅极绝缘层形成在所述基板上且覆盖所述漏极底层、所述底栅和所述源极,所述栅极绝缘层对应所述漏极底层和所述源极的位置分别形成有第一过孔,所述有源层形成在所述栅极绝缘层上,所述有源层通过所述第一过孔分别与所述漏极底层和所述源极连接。
优选地,所述薄膜晶体管还包括钝化层,所述钝化层形成在所述栅极绝缘层上且覆盖所述有源层,所述钝化层和所述栅极绝缘层内对应所述漏极底层形成有连通的第二过孔,而对应所述基板形成有连通的第三过孔,所述漏极还包括漏极顶层,所述漏极顶层通过第二过孔与所述漏极底层连接,所述顶栅侧部通过所述第三过孔从所述钝化层至少延伸到所述栅极绝缘层,所述第三过孔和所述第二过孔间隔设置,所述第三过孔和所述第二过孔一起围绕在所述有源层的侧壁周围。
在一种实施方式中,所述第三过孔的横截面和所述第二过孔的横截面一起形成矩形框状结构。
优选地,所述钝化层和所述栅极绝缘层内还形成有连通的第四过孔,所述顶栅和所述底栅通过所述第四过孔连接。
在一种实施方式中,所述有源层呈矩形结构,所述顶栅侧部包围所述矩形结构的三个侧边。
可选地,所述有源层为氧化物半导体层。
可选地,所述氧化物半导体层的材料包括IGZO、ITZO或ZnON。
可选地,所述氧化物半导体层的厚度为10-150nm。
优选地,所述栅极、所述源极和所述漏极均采用不透明的金属制成。
第二方面,本发明实施例提供了一种薄膜晶体管的制造方法,包括:
提供基板;
在所述基板上形成有源层、源极、栅极和漏极,所述有源层的两端分别与所述源极和所述源极连接,其中,所述栅极包括顶栅和底栅,所述顶栅包括顶栅顶部和与所述顶栅顶部连接的顶栅侧部,所述顶栅顶部和所述底栅在垂直于所述基板的方向上相对设置,所述有源层夹设于所述顶栅顶部和所述底栅之间,所述顶栅侧部从所述顶栅顶部朝向所述基板延伸,所述有源层的侧壁至少部分被所述顶栅侧部围绕,所述栅极、所述源极和所述漏极均采用非透明的导电材料制成。
优选地,在所述基板上形成有源层、源极、栅极和漏极,包括:
在基板上形成底栅、源极和漏极底层,所述漏极底层、所述底栅和所述源极同层间隔形成在所述基板上,且所述底栅位于所述源极和所述漏极底层之间;
在所述基板上以覆盖所述底栅、源极和漏极底层的形式形成所述栅极绝缘层,并在所述栅极绝缘层中对应所述源极和所述漏极底层分别形成第一过孔;
在栅极绝缘层上形成所述有源层;
以覆盖所述有源层的方式在所述栅极绝缘层上形成所述钝化层,并在所述钝化层和所述栅极绝缘层中对应所述漏极底层形成连通的第二过孔并对应所述基板形成连通的第三过孔;
在所述钝化层上形成所述顶栅和所述漏极顶层,在所述钝化层上形成所述顶栅和所述漏极顶层,所述漏极顶层通过所述第二过孔与所述漏极底层连接,所述顶栅侧部通过所述第三过孔从所述钝化层至少延伸到所述栅极绝缘层。
第三方面,本发明实施例提供了一种阵列基板,包括衬底基板,其特征在于,所述衬底基板上设有栅线、数据线、像素电极层和前述薄膜晶体管,所述薄膜晶体管的漏极与所述像素电极层连接,所述薄膜晶体管的栅极与所述栅线连接,所述薄膜晶体管的源极与所述数据线连接。
第四方面,本发明实施例还提供了一种显示装置,包括前述阵列基板。
本发明实施例提供的技术方案带来的有益效果是:
在本发明实施例中,有源层下方的底栅可以阻挡从氧化物半导体层下方照射的光,围绕在有源层侧壁的顶栅侧部可以阻挡从有源层侧壁照射的光,而位于有源层上方的顶栅顶部可以阻挡从有源层上方照射的光,从而可以减少有源层被光照射的情况,进而可以避免薄膜晶体管的特性由于光照而劣化。
附图说明
为了更清楚地说明本发明实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种薄膜晶体管的截面结构示意图;
图2是本发明实施例提供的薄膜晶体管去掉顶栅和部分漏极后的俯视结构示意图;
图3是本发明实施例提供的一种薄膜晶体管的制造方法的流程图;
图4a-4d是本发明实施例提供的薄膜晶体管的制备工艺图;
图5是本发明实施例提供的又一薄膜晶体管的截面结构示意图;
图6是图5所示薄膜晶体管的又一截面结构示意图;
图7是本发明实施例提供的又一薄膜晶体管的制造方法的流程图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚,下面将结合附图对本发明实施方式作进一步地详细描述。附图中各层薄膜的厚度和形状不反映阵列基板的真实比例,目的只是示意说明本发明内容。
本发明实施例提供了一种薄膜晶体管,包括:基板、以及形成于所述基板上的有源层、源极、栅极和漏极,所述有源层的两端分别与所述源极和所述漏极连接,所述栅极包括顶栅和底栅,所述顶栅包括顶栅顶部和与所述顶栅顶部连接的顶栅侧部,所述顶栅顶部和所述底栅在垂直于所述基板的方向上相对设置,所述有源层夹设于所述顶栅顶部和所述底栅之间,所述顶栅侧部从所述顶栅顶部朝向所述基板延伸,所述有源层的四周被所述顶栅侧部围绕,所述栅极、所述源极和所述漏极均采用非透明的导电材料制成。
在本实施例的一种实现方式中,非透明的导电材料可以为不完全透明的导电材料,其中,不完全透明的导电材料可以为透过率为15%以下的导电材料,优选为透过率为5%以下的导电材料,在本实施例的一种优选的实现方式中,非透明的导电材料为不透明的导电材料,例如不透明的金属。故此,在本发明实施例中,将均以不透明的金属为例进行说明。
可选地,有源层可以呈矩形结构,所述顶栅侧部可以包围所述矩形结构的三个侧边(如图1所示实施例,),或者,顶栅侧部也可以包围矩形结构的两个侧边(如图5所示实施例)。
需要说明的是,在本发明实施例中,有源层包括顶面、底面和连接顶面和底面的侧壁,有源层的顶面与顶栅顶部相对,有源层的底面与底栅相对,有源层的侧壁至少部分被顶栅侧部围绕,是指顶栅侧部会从顶栅顶部朝向基板方向延伸直至挡住有源层的侧壁,即至少延伸到栅极绝缘层。
在本发明实施例中,有源层下方的底栅可以阻挡从氧化物半导体层下方照射的光,围绕在有源层侧壁的顶栅侧部可以阻挡从有源层侧壁照射的光,而位于有源层上方的顶栅顶部可以阻挡从有源层上方照射的光,从而可以减少有源层被光照射的情况,进而可以避免薄膜晶体管的特性由于光照而劣化。
图1显示了本发明实施例提供的一薄膜晶体管的具体结构。图1是本发明实施例提供的一种薄膜晶体管的截面示意图。如图1所示,该薄膜晶体管包括:基板11、以及形成于基板11上的有源层12、源极13、栅极和漏极14,有源层12的两端分别与源极13和漏极14连接,栅极包括顶栅15和底栅16,顶栅15包括顶栅顶部15a和与顶栅顶部15a连接的顶栅侧部15b,顶栅顶部15a和底栅16在垂直于基板11的方向上相对设置,有源层12夹设于顶栅顶部15a和底栅16之间,顶栅侧部15b从顶栅顶部15a朝向基板11延伸,有源层12的侧壁的至少部分被顶栅侧部15b围绕。
其中,基板11可为玻璃基板、透明塑料基板等,本发明对此不作限制。
有源层12的材料可以为氧化物半导体、多晶硅、非晶硅等。由于氧化物半导体对光照更为敏感,所以本发明实施例尤其适用于氧化物半导体薄膜晶体管。故在本实施例中,有源层12为氧化物半导体层。本发明实施例的氧化物半导体层的材料包括但不限于IGZO(Indium Gallium Zinc Oxide,铟镓锌氧化物)、ITZO(Indium Tin Zinc Oxide,铟锡锌氧化物)或ZnON(锌的氮氧化物)。具体实施时,氧化物半导体层的厚度可以为10-150nm。
在本实施例中,漏极14包括漏极底层141,漏极底层141、底栅16和源极13同层间隔形成在基板11上,且底栅16位于源极13和漏极底层141之间。
在本发明实施例中,底栅16、源极13和漏极底层141同层设置,为了节省制作工序,底栅、源极和漏极底层优选采用相同的材料制备,这样,底栅、源极和漏极底层可以通过一次构图工艺形成在基板上,减少了掩模板的使用次数,简化了该薄膜晶体管的制备工艺,进而可以降低其制备成本。
如前所述,在本实施例中,底栅16、源极13和漏极底层141均采用不透明的金属制成。具体地,可以采用由钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)和铜(Cu)中的一种材料形成的单层膜或多种材料形成的多层复合膜;优选采用Mo、Al或含Mo、Al的合金组成的单层或多层复合膜,例如Mo/Al/Mo三层复合膜。由于Al的电阻较小而Mo的抗氧化能力较强,所以采用这种复合膜结构能够保证信号传输速度并提高使用寿命。具体实施时,底栅、源极和漏极底层的厚度可以为100nm~500nm。
该薄膜晶体管还包括栅极绝缘层17,栅极绝缘层17形成在基板11上,且覆盖漏极底层141、底栅16和源极13,从而使得漏极底层141、底栅16和源极13彼此绝缘,栅极绝缘层17对应漏极底层141和源极13的位置分别设有第一过孔171(参见图4b),有源层12形成在栅极绝缘层17上,有源层17通过第一过孔171分别与漏极底层141和源极13连接。
其中,栅极绝缘层17可以为由硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)、硅的氮氧化物(SiON)、AlOx等中的一种材料形成的单层膜或两种材料组成的多层复合膜。优选为SiNx/SiOx的叠层结构或者SiNx/SiON/SiOx的叠层结构。栅极绝缘层17的厚度可以为100~600nm。
薄膜晶体管还包括钝化层18,钝化层18形成在栅极绝缘层17上且覆盖有源层12,钝化层18和栅极绝缘层17内对应漏极底层141形成有连通的第二过孔181(参见图4d)而对应基板形成有连通的第三过孔182,漏极14还包括漏极顶层142,漏极顶层142通过第二过孔181与漏极底层141连接,顶栅15通过第三过孔182与基板11连接(即顶栅侧部15b与基板11连接),第三过孔182和第二过孔181间隔设置,第三过孔182和第二过孔181一起围绕在有源层12的侧壁周围。
本发明实施例通过使第三过孔182和第二过孔181一起围绕在有源层12的侧壁周围,从而顶栅侧部和漏极顶层可以包围有源层的侧壁,栅极、漏极、源极形成一个基本封闭的空间,进而有源层处于基本上不会被光照射到的状态,可以进一步防止薄膜晶体管的特性因光照而劣化。同时,在钝化层上形成漏极顶层,当该薄膜晶体管应用于阵列基板时,像素电极层可以直接在钝化层上形成图案,便于与像素电极层连接。
需要说明的是,在图1所示实施例中,第三过孔182从钝化层18延伸至基板11表面,从而可以更严密地遮挡有源层,防止其被光照到;而在其他实现方式中,第三过孔182也可以从钝化层18延伸到栅极绝缘层17内而不到达基板11表面,只要能够遮挡从有源层侧壁照射的光即可。也就是说,在本发明实施例中,顶栅侧部通过第三过孔从钝化层至少延伸到栅极绝缘层。
结合图2,图2是本发明实施例提供的薄膜晶体管去掉顶栅和部分漏极后的俯视结构示意图。如图2所示,在本实施例中,第二过孔181的横截面形状为一边开口的矩形框(包括底边181a和垂直连接在底边181a两端的两侧边181b),而第三过孔182的横截面形状呈直线形,第二过孔181和第三过孔182的横截面形状一起构成类似于矩形框状结构。容易知道,第二过孔181的横截面形状和第三过孔182的横截面形状也可以是圆弧形,第二过孔181的横截面和第三过孔182的横截面形状一起构成类似于圆形框状结构,或者,在其他实现方式中,第二过孔181和第三过孔182的横截面形状一起还可以构成多边形框等形状,只要能够围绕有源层的四周即可,本发明对此不做限制。
需要说明的是,本发明实施例中的过孔(包括第一过孔、第二过孔、第三过孔等)的侧壁通常并非垂直于基板的板面,而是呈一定的坡度角,坡度角通常为30°~70°。
同样地,在本实施例中,顶栅15采用不透明的金属制成。具体地,顶栅15可以为Mo、MoNb、Al、AlNd、Ti、Cu中的一种材料形成的单层膜或多种材料形成的多层复合膜,优选为Mo、Al或含Mo、Al的合金组成的单层或多层复合膜,例如Mo/Al/Mo三层复合膜。由于Al的电阻较小而Mo的抗氧化能力较强,所以采用这种复合膜结构能够保证信号传输速度并提高使用寿命。具体实施时,形成在钝化层上的顶栅的厚度可以为200~900nm。容易知道,顶栅15和底栅16可以采用相同的材料制成,也可以采用不同的材料制成。
钝化层18可以为由硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)、硅的氮氧化物(SiON)、AlOx等中的一种材料制成的单层膜或两种组成的多层复合膜。优选为SiNx/SiOx的叠层结构或SiNx/SiON/SiOx的叠层结构。具体实施时,钝化层的厚度可以为100~600nm。
如图2所示,在本发明实施例中,钝化层18和栅极绝缘层17内还形成有连通的第四过孔183,顶栅15和底栅16通过第四过孔183连接,将顶栅和底栅电连接,使得该两个栅极同时工作,加快了薄膜晶体管内的电荷的沟道的开启的速度,同时给予电荷更好的引导能力,以提高其导电能力,从而提高响应速度;并且,在停止该薄膜晶体管工作时,向薄膜晶体管的两个栅极提供稳定的负电压,加快薄膜晶体管的沟道的关断的速度,同时提高了薄膜晶体管的阻止电荷的移动能力,以降低薄膜晶体管的漏电流,从而降低功耗。并且,顶栅和底栅通过第四过孔连接,从而当本发明实施例的薄膜晶体管应用于阵列基板时,不用分别为顶栅和底栅布线,可以减少阵列基板的走线。容易知道,在其他实施例中,也可以不设置第四过孔,顶栅和底栅采用外部走线的方式连接。
容易知道,第四过孔183可以与第二过孔181在同一工艺步骤中形成。
图3显示了本发明实施例提供的薄膜晶体管的制造方法,如图3所示,该薄膜晶体管的制造方法包括:
步骤301:提供基板。
步骤302:在基板上形成有源层、源极、栅极和漏极,有源层的两端分别与源极和源极连接,其中,栅极包括顶栅和底栅,所述顶栅包括顶栅顶部和与所述顶栅顶部连接的顶栅侧部,所述顶栅顶部和所述底栅在垂直于所述基板的方向上相对设置,所述有源层夹设于所述顶栅顶部和所述底栅之间,所述顶栅侧部从所述顶栅顶部朝向所述基板延伸,所述有源层的侧壁至少部分被所述顶栅侧部围绕,所述栅极、所述源极和所述漏极均采用非透明的导电材料制成。
具体地,当本发明实施例的制造方法用于制备图1-2所示的薄膜晶体管时,该步骤302可以包括以下步骤:
步骤一、在基板11上形成底栅16、源极13和漏极底层141,漏极底层141、底栅16和源极13同层间隔形成在基板11上,且底栅16位于源极13和漏极底层141之间,如图4a所示。
步骤二、在基板11上以覆盖底栅16、源极13和漏极底层141的形式形成栅极绝缘层17,并在栅极绝缘层17对应源极13和漏极底层141的位置分别形成第一过孔171,如图4b所示。具体地,栅极绝缘层17可以采用PECVD(Plasma Enhanced Chemical VaporDeposition,等离子体增强化学气相沉积法)制作,且在制作过程中,需控制膜层的氢含量在较低的水平。
步骤三、在栅极绝缘层17上形成有源层12,如图4c所示,该有源层12的两端通过第一过孔171与源极13和漏极底层131连接。具体地,有源层可以采用溅射沉积的方式制备。
步骤四、以覆盖有源层12的方式在栅极绝缘层17上形成钝化层18,并在钝化层18和栅极绝缘层17中对应漏极底层141形成连通的第二过孔181并对应基板11形成连通的第三过孔182,如图4d所示。具体地,钝化层18可以采用PECVD制作,且在制作过程中,需控制膜层的氢含量在较低的水平。
步骤五、在钝化层18上形成顶栅15和漏极顶层142,漏极顶层142通过第三过孔182与漏极底层141连接,顶栅侧部15b通过第二过孔181从钝化层18延伸到基板11表面,从而得到如图1所示的薄膜晶体管。
容易知道,顶栅侧部15b延伸到基板11表面可以获得更好地挡光效果,而在其他实现方式中,顶栅侧部15b也可以只延伸到栅极绝缘层,同样可以起到一定的遮挡从有源层侧壁照射的光的作用。
从前述步骤可以看出,图1-2所示的薄膜晶体管的制造方法仅采用了5次构图工艺,工艺步骤简单,制造成本低。
图5和图6显示了本发明实施例提供的又一薄膜晶体管的结构。图5和图6所示截面相互垂直。如图5和图6所示,该薄膜晶体管包括基板21、以及形成于基板21上的有源层22、源极23、栅极和漏极24,有源层22的两端分别与所述源极23和所述漏极24连接,栅极包括顶栅25和底栅26,顶栅25包括顶栅顶部25a和与顶栅顶部25a连接的顶栅侧部25b,顶栅顶部25a和底栅26在垂直于基板21的方向上相对设置,有源层22夹设于顶栅顶部25a和底栅26之间,顶栅侧部25b从顶栅顶部25a朝向基板21延伸,有源层22的侧壁的至少部分被顶栅侧部25b围绕。
进一步地,在图5所示实施例中,有源层22呈矩形结构,矩形结构的相对的两端分别设有源极23和漏极24,而顶栅侧部25b围绕有源层22的未形成源极23和漏极24的两个侧边。
在图5所示的薄膜晶体管中,底栅26形成在基板21上,该薄膜晶体管还包括栅极绝缘层27,该栅极绝缘层27形成在基板21上且覆盖栅极26。有源层22形成在栅极绝缘层27上且形成在底栅26上方,源极23和漏极24形成在有源层22的两端。
本实施例的薄膜晶体管还包括绝缘层28,绝缘层28形成在栅极绝缘层27上,且覆盖源极23、漏极24和有源层22,顶栅26形成在绝缘层28上。绝缘层28和栅极绝缘层27中形成有连通的过孔281,该过孔281可以设置在有源层22的未形成源极23和漏极24的相对两侧,顶栅侧部25b通过该过孔281与源极23、漏极24一起包围有源层22的四周。
在一种实施方式中,在有源层22的未形成源极23和漏极24的相对两侧中的一侧的过孔可以从绝缘层28延伸至基板21,而在有源层22的未形成源极23和漏极24的相对两侧中的另一侧的过孔从绝缘层28延伸至底栅26。
在另一种实施方式中,在有源层22的未形成源极23和漏极24的相对两侧的过孔均从绝缘层28延伸至基板21、或者均从绝缘层28延伸至底栅。
容易知道,在前述两种实施方式中,顶栅仅围绕有源层的两侧,顶栅与源极和漏极一起基本上包围有源层,而在其他实施方式中,过孔281也可以围绕有源层22、源极23和漏极24设置,此时,顶栅26可以包围有源层22的四周。
可选地,本发明实施例的漏极24也可以包括漏极底层241和漏极顶层242,其中漏极底层241形成在栅极绝缘层27上且与有源层22连接,而漏极顶层242形成在绝缘层28上,漏极顶层242和漏极底层241通过过孔连接。
本实施例中的源极、漏极和栅极的材料可以与图1所示实施例中的源极、漏极和栅极的材料相同,在此不再赘述。
图7显示了图5所示薄膜晶体管的制备方法,如图7所示,该薄膜晶体管的制造方法包括:
步骤601:提供基板。
步骤602:在基板上形成底栅。
步骤603:形成栅极绝缘层,栅极绝缘层形成在基板上且覆盖底栅。
步骤604:在栅极绝缘层上形成有源层,该有源层形成在底栅上方。
步骤605:形成源极和漏极,源极和漏极位于有源层的相对两侧。
步骤606:形成钝化层并在钝化层和栅极绝缘层中形成连通的过孔,该钝化层形成在栅极绝缘层上,且覆盖源极、漏极和有源层,该过孔设置在有源层的未形成源极和漏极的相对两侧。
如前所述,该过孔也可以围绕有源层、源极和漏极设置。
步骤607:在绝缘层上形成顶栅,顶栅通过步骤606中形成的过孔延伸至有源层的侧壁周围,从而顶栅通过该过孔与源极、漏极一起围绕有源层。
本发明实施例还提供了一种阵列基板,该阵列基板包括前述任一实施例提供的薄膜晶体管。具体地,该阵列基板包括衬底基板,衬底基板上设有栅线、数据线、像素电极层和前述薄膜晶体管,该薄膜晶体管的漏极与像素电极层连接,薄膜晶体管的栅极与栅线连接,薄膜晶体管的源极与数据线连接。
其中,像素电极层可以为透明的导电金属氧化物层,例如ITO(Indium TinOxides,氧化铟锡)、IZO(Indium Zinc Oxides,氧化铟锌)等。
基于相同的发明构思,本发明实施例还提供了一种显示装置,该显示装置包括前述实施例提供的阵列基板。
在具体实施时,本发明实施例提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅为本发明的较佳实施例,并不用以限制本发明,凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (15)
1.一种薄膜晶体管,包括:基板、以及形成于所述基板上的有源层、源极、栅极和漏极,所述有源层的两端分别与所述源极和所述漏极连接,其特征在于,所述栅极包括顶栅和底栅,所述顶栅包括顶栅顶部和与所述顶栅顶部连接的顶栅侧部,所述顶栅顶部和所述底栅在垂直于所述基板的方向上相对设置,所述有源层夹设于所述顶栅顶部和所述底栅之间,所述顶栅侧部从所述顶栅顶部朝向所述基板延伸,所述有源层的侧壁至少部分与所述源极和所述漏极不接触,所述有源层的未与所述源极和所述漏极接触的侧壁至少部分被所述顶栅侧部围绕,所述栅极、所述源极和所述漏极均采用非透明的导电材料制成。
2.根据权利要求1所述的薄膜晶体管,其特征在于,所述漏极包括漏极底层,所述漏极底层、所述底栅和所述源极同层间隔形成在所述基板上,且所述底栅位于所述源极和漏极底层之间。
3.根据权利要求2所述的薄膜晶体管,其特征在于,所述薄膜晶体管还包括栅极绝缘层,所述栅极绝缘层形成在所述基板上且覆盖所述漏极底层、所述底栅和所述源极,所述栅极绝缘层对应所述漏极底层和所述源极的位置分别形成有第一过孔,所述有源层形成在所述栅极绝缘层上,所述有源层通过所述第一过孔分别与所述漏极底层和所述源极连接。
4.根据权利要求3所述的薄膜晶体管,其特征在于,所述薄膜晶体管还包括钝化层,所述钝化层形成在所述栅极绝缘层上且覆盖所述有源层,所述钝化层和所述栅极绝缘层内对应所述漏极底层形成有连通的第二过孔,而对应所述基板形成有连通的第三过孔,所述漏极还包括漏极顶层,所述漏极顶层通过所述第二过孔与所述漏极底层连接,所述顶栅侧部通过所述第三过孔从所述钝化层至少延伸到所述栅极绝缘层,所述第三过孔和所述第二过孔间隔设置,所述第三过孔和所述第二过孔一起围绕在所述有源层的侧壁周围。
5.根据权利要求4所述的薄膜晶体管,其特征在于,所述第三过孔的横截面和所述第二过孔的横截面一起形成矩形框状结构。
6.根据权利要求4所述的薄膜晶体管,其特征在于,所述钝化层和所述栅极绝缘层内还形成有连通的第四过孔,所述顶栅和所述底栅通过所述第四过孔连接。
7.根据权利要求1所述的薄膜晶体管,其特征在于,所述有源层呈矩形结构,所述顶栅侧部包围所述矩形结构的三个侧边。
8.根据权利要求1所述的薄膜晶体管,其特征在于,所述有源层为氧化物半导体层。
9.根据权利要求8所述的薄膜晶体管,其特征在于,所述氧化物半导体层的材料包括IGZO、ITZO或ZnON。
10.根据权利要求8所述的薄膜晶体管,其特征在于,所述氧化物半导体层的厚度为10-150nm。
11.根据权利要求1所述的薄膜晶体管,其特征在于,所述栅极、所述源极和所述漏极均采用不透明的金属制成。
12.一种薄膜晶体管的制造方法,其特征在于,包括:
提供基板;
在所述基板上形成有源层、源极、栅极和漏极,所述有源层的两端分别与所述源极和所述源极连接,其中,所述栅极包括顶栅和底栅,所述顶栅包括顶栅顶部和与所述顶栅顶部连接的顶栅侧部,所述顶栅顶部和所述底栅在垂直于所述基板的方向上相对设置,所述有源层夹设于所述顶栅顶部和所述底栅之间,所述顶栅侧部从所述顶栅顶部朝向所述基板延伸,所述有源层的侧壁至少部分被所述顶栅侧部围绕,所述栅极、所述源极和所述漏极均采用非透明的导电材料制成。
13.根据权利要求12所述的制造方法,其特征在于,在所述基板上形成有源层、源极、栅极和漏极,包括:
在基板上形成所述底栅、所述源极和漏极底层,所述漏极底层、所述底栅和所述源极同层间隔形成在所述基板上,且所述底栅位于所述源极和所述漏极底层之间;
在所述基板上以覆盖所述底栅、所述源极和所述漏极底层的形式形成栅极绝缘层,并在所述栅极绝缘层中对应所述源极和所述漏极底层分别形成第一过孔;
在所述栅极绝缘层上形成所述有源层;
以覆盖所述有源层的方式在所述栅极绝缘层上形成钝化层,并在所述钝化层和所述栅极绝缘层中对应所述漏极底层形成连通的第二过孔并对应所述基板形成连通的第三过孔;
在所述钝化层上形成所述顶栅和漏极顶层,所述漏极顶层通过所述第二过孔与所述漏极底层连接,所述顶栅侧部通过所述第三过孔从所述钝化层至少延伸到所述栅极绝缘层。
14.一种阵列基板,包括衬底基板,其特征在于,所述衬底基板上设有栅线、数据线、像素电极层和如权利要求1-11任一项所述的薄膜晶体管,所述薄膜晶体管的漏极与所述像素电极层连接,所述薄膜晶体管的栅极与所述栅线连接,所述薄膜晶体管的源极与所述数据线连接。
15.一种显示装置,其特征在于,包括如权利要求14所述的阵列基板。
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CN105789119B (zh) * | 2016-05-20 | 2019-01-22 | 武汉华星光电技术有限公司 | 阵列基板及其制作方法 |
CN110690228B (zh) * | 2019-09-06 | 2022-03-08 | 深圳市华星光电半导体显示技术有限公司 | 阵列基板及显示面板 |
CN111628003A (zh) * | 2020-04-16 | 2020-09-04 | 福建华佳彩有限公司 | 一种晶体管结构及制作方法 |
CN111725240B (zh) * | 2020-06-10 | 2023-04-18 | 武汉华星光电半导体显示技术有限公司 | 薄膜晶体管电极及其制造方法、显示装置 |
CN112071268B (zh) * | 2020-08-12 | 2022-02-22 | 武汉华星光电半导体显示技术有限公司 | 显示面板和显示装置 |
CN112397579B (zh) * | 2020-10-22 | 2022-12-06 | 云谷(固安)科技有限公司 | 显示面板 |
CN112530978B (zh) * | 2020-12-01 | 2024-02-13 | 京东方科技集团股份有限公司 | 开关器件结构及其制备方法、薄膜晶体管膜层、显示面板 |
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