CN111628003A - 一种晶体管结构及制作方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 104
- 239000002184 metal Substances 0.000 claims abstract description 104
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 238000000059 patterning Methods 0.000 claims abstract description 17
- 239000002131 composite material Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 8
- 238000005253 cladding Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 41
- 239000011248 coating agent Substances 0.000 description 9
- 238000000576 coating method Methods 0.000 description 9
- 239000003990 capacitor Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 5
- 229910017107 AlOx Inorganic materials 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 101100214488 Solanum lycopersicum TFT2 gene Proteins 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 3
- 101100489584 Solanum lycopersicum TFT1 gene Proteins 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 241001270131 Agaricus moelleri Species 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H01L29/772—Field effect transistors
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
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- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
Abstract
一种晶体管结构及制作方法，其中结构包括第一金属层，所述第一金属层内图案化栅极与源漏极，图案化的栅极与源漏极处于同一水平位置，包括第一绝缘层，第一绝缘层包覆在图案化后的栅极层与源漏极层之上，第一绝缘层还包括通孔，第一绝缘层上还包括半导体层，所述半导体层在栅极层的竖直上方，半导体层上方还设置有第二绝缘层，第二绝缘层还包括过孔，第二绝缘层的上方还设置有第二金属层，所述第二金属层通过通孔及过孔连接栅极金属及源漏极金属走线。上述技术方案通过将栅极金属与源漏极金属合并在同一层，通过在第一金属层中进行图案化布线，以及其上的第二金属层通过通孔、过孔连接第一金属层的栅极和源漏极。从而达到制程中减少光罩数量的效果。
Description
技术领域
本发明涉及薄膜晶体管的设计方案，尤其涉及一种能够整合栅极层和源漏极层从而节省光罩流程的晶体管结构及制作方法。
背景技术
目前用于显示面板的薄膜晶体管(TFT)基本的结构通常包含第一金属层栅极GE，第一绝缘层GI，半导体主动层SE，第二金属层源漏极SD，第二绝缘层PV，以及像素电极PE，一共6道光罩。为了提高器件稳定性，设计者还会在SE图案化之后额外增加一个蚀刻阻挡层ESL，保护其不会在SD制程受到额外的损伤。
在此基础上，TFT衍生出了许多改进的方向，有增加额外膜层以得到其他功能或提高器件性能。也有减少光罩数以降低生产成本和缩短工期，最常见的是将具有ESL结构的该膜层拿掉使其成为BCE结构以降低成本，但性能通常会有所下降，亦或采用同光罩或自对准以减少光罩数，但膜层数通常没有改变。
发明内容
为此，需要提供一种新的TFT制程设计，解决现有技术工艺复杂的问题。
为实现上述目的，发明人提供了一种晶体管结构，包括第一金属层，所述第一金属层内图案化栅极与源漏极，图案化的栅极与源漏极处于同一水平位置，包括第一绝缘层，第一绝缘层包覆在图案化后的栅极层与源漏极层之上，第一绝缘层还包括通孔，第一绝缘层上还包括半导体层，所述半导体层在栅极层的竖直上方，半导体层上方还设置有第二绝缘层，第二绝缘层还包括过孔，第二绝缘层的上方还设置有第二金属层，所述第二金属层通过通孔及过孔连接栅极金属及源漏极金属走线。
具体地，所述第二金属层为金属及ITO复合膜层。
进一步地，所述第一绝缘层镀膜在第一金属层上。
一种晶体管制作方法，包括如下步骤，在第一金属层内图案化栅极与源漏极，所述栅极与源漏极处于同一水平位置，在栅极与源漏极上设置第一绝缘层，在第一绝缘层处设置通孔，再设置半导体层，所述半导体层在栅极层的竖直上方，再在半导体层上方设置第二绝缘层，在第二绝缘层内设置过孔，在第二绝缘层上设置第二金属层，所述第二金属层通过通孔及过孔连接栅极金属及源漏极金属走线。
具体地，所述第二金属层为金属及ITO复合膜层。
进一步地，所述第一绝缘层镀膜在第一金属层上。
区别于现有技术，上述技术方案通过将栅极金属与源漏极金属合并在同一层，通过在第一金属层中进行图案化布线，以及其上的第二金属层通过通孔、过孔连接第一金属层的栅极和源漏极。从而达到制程中减少光罩数量的效果。最终的目的是节省成本，降低经济负担。
附图说明
图1为具体实施方式所述的方案一第一金属层示意图；
图2为具体实施方式所述的方案一第一绝缘层GI示意图；
图3为具体实施方式所述的方案一半导体层SE示意图；
图4为具体实施方式所述的方案一第二绝缘层PV示意图；
图5为具体实施方式所述的方案一第二金属层示意图；
图6为具体实施方式所述的方案二第一金属层示意图；
图7为具体实施方式所述的方案二GI及SE示意图；
图8为具体实施方式所述的方案二第二绝缘层PV示意图
图9为具体实施方式所述的方案二第二金属层示意图。
具体实施方式
为详细说明技术方案的技术内容、构造特征、所实现目的及效果，以下结合具体实施例并配合附图详予说明。
请参阅图1，一种晶体管结构，包括第一金属层，所述第一金属层内图案化栅极GE与源漏极SD，由于是同层金属层的图案化，则图案化的栅极与源漏极处于同一水平位置。这里请看图2，还包括第一绝缘层GI，第一绝缘层可以通过蒸镀或电镀等手段包覆在图案化后的栅极层与源漏极层之上，因而在图中没有体现。然后，第一绝缘层还包括通孔(图中圆形部分DChole)，进而如图3所示我们可以在第一绝缘层GI上还设置半导体主动层SE，也可以称作半导体层。所述半导体层在栅极层的竖直上方的部分需要设置为略宽于栅极走线，图4所示的半导体层上方还设置有第二绝缘层PV，第二绝缘层还包括过孔(图中方块部分)。进一步如图5所示，第二绝缘层的上方还设置有第二金属层，所述第二金属层通过通孔及过孔连接栅极金属或源漏极金属走线。所述第二金属层为金属及ITO复合膜层。
下面我们以图1-5示例详细介绍第一种方案结构，图1至图5是本专利的实施方案一
图1为方案一的第一金属层图案化示意图，纸面平行基板平面。包含GE走线和SD走线，GE和SD为同一金属层蚀刻出来的图案，仅以不同灰度区分走线功能，其中包括沿纸面纵向依次排列的第一源漏极区SD1，第一栅极区GE，第三源漏极区和第二源漏极区SD2.该膜层可以使用Mo，Al，Ti，Cu，Ag，W等金属或其复合膜层金属。
图2为方案一的第一绝缘层GI镀膜和图案化，即开DC孔，以黑边圆形表示，我们可以看到，图中在第一源漏极区、第二源漏极区分别开了第一通孔和第二通孔，第三源漏极区开了第三通孔和第四通孔。该膜层可以使用SiOx，SiNx，AlOx或其他绝缘物质及其复合膜层作为绝缘层。
图3为方案一的半导体主动层SE镀膜和图案化，其中GE上的SE宽度应覆盖下层GE，该膜层可用a-Si，MOS(金属氧化物半导体)，LTPS等作为主动层。在源漏极区的半导体主动层要覆盖第二通孔和第三通孔。
图4为方案一的第二绝缘层PV镀膜和图案化，以黑边长方形和正方形表示，对PV相应位置进行开孔以确保第二金属层能接触到第一金属层或主动层，具体地，第二绝缘层上的过孔包括联通第一通孔和栅极区上的半导体层的第一过孔；以及栅极区上的半导体层上的第二过孔；以及联通第四通孔的第三过孔。该膜层可以使用SiOx，SiNx，AlOx，有机膜层或其他绝缘物质及其复合膜层作为绝缘层。
图5为方案一的第二金属层PE的镀膜和图案化，包含桥接走线、电容和像素电极部分，通常该膜层为ITO或金属和ITO的复合膜层或其他金属及合金。如图5右侧半透明结构所示：a为像素电极部分，该部分膜层联通第三过孔，并覆盖第一源漏极区和第一栅极区；b为底栅结构TFT1，该部分膜层覆盖第一过孔。通过PV孔(第一过孔)和DC孔(第一通孔)分别接到SD1(第一源漏极区)线和TFT2及电容的PE电极；c为电容，该部分膜层覆盖第二源漏极区、第二过孔，同时覆盖上述覆盖第二通孔和第三通孔的在源漏极区的半导体主动层，介电膜层为GI和PV；d为顶栅结构TFT2，即上述的在源漏极区的半导体主动层。其GE为PE膜层金属，源漏极接SD2走线，并通过SD2桥接连线到像素电极。
下面我们以图6-9示例详细介绍第二种方案结构，图6至图9是本专利的实施方案二
图6为方案二的第一金属层图案化示意图，包含GE走线和SD走线，GE和SD为同一金属层蚀刻出来的图案，仅以不同灰度区分走线功能，其中包括沿纸面纵向依次排列的第一源漏极区SD1，第一栅极区GE1，第二栅极区GE2、和第二源漏极区SD2。该膜层可以使用Mo，Al，Ti，Cu，Ag，W等金属或其复合膜层金属。
图7为方案二的第一绝缘层GI，GI同样是在栅极区和源漏极区上成膜。此时将SE图案化，其中GE上的SE宽度应覆盖下层GE，图中可以看到包括第一栅极区上的第一半导体区和第二栅极区上的第二半导体区。GI膜层可以使用SiOx，SiNx，AlOx或其他绝缘物质及其复合膜层作为绝缘层，SE膜层可用a-Si，MOS(金属氧化物半导体)，LTPS等作为主动层。从图中也可以看到，第一绝缘层的通孔包括第一源漏极区上的第一通孔，第二栅极区上的第二通孔，以及第二源漏极区上的第三通孔和第四通孔。
图8为方案二的第二绝缘层PV镀膜和图案化，以黑边长方形和正方形表示，对PV相应位置进行开过孔以确保第二金属层能接触到第一金属层或主动层，该膜层可以使用SiOx，SiNx，AlOx，有机膜层或其他绝缘物质及其复合膜层作为绝缘层。从图中我们可以看到，第二绝缘层上的过孔包括联通第一源漏极区和第一半导体区的第一过孔、联通第一半导体区和第一栅极区的第二过孔，第二半导体区上的第三过孔、第四过孔；以及第二源漏极区上的第五、第六过孔。其中第一过孔覆盖第一通孔，第二过孔覆盖第二通孔，第五过孔覆盖第三通孔，第六过孔覆盖第四通孔，均使得第一层金属和半导体层露出。
图9为方案二的第二金属层PE的镀膜和图案化，包含桥接走线、电容和像素电极部分，通常该膜层为ITO或金属和ITO的复合膜层或其他金属及合金。如图9右侧半透明结构所示：a为像素电极部分，该部分膜层覆盖第一源漏极区、第二源漏极区和第二半导体区上的第三过孔；b为底栅结构TFT1，通过PV孔分别接到SD1线和TFT2及电容的GE电极，该处PE膜层包括覆盖第一过孔的一块区域以及覆盖第二过孔的另一块区域；c为电容，其金属膜层分别为GE和PE，PE电极则通过PV孔接到SD2线，该处PE膜层覆盖第二栅极区和第六过孔，介电膜层为GI和PV；d为底栅结构TFT2，源漏极接SD2走线和像素电极，则此处还包括覆盖第四过孔和第五过孔的PE膜层。
通过上述设计，结构借助半导体主动层和第二金属层以桥接的方式构成走线，相对于传统TFT能省去一层金属膜层，因此也会减少所需要的光罩数目和制程时间，方案一所需的基本光罩数为5道，方案二所需的基本光罩数为4道。
本专利在半导体主动层SE前后成膜的膜层都是绝缘层，相对于普通的的BCE结构来说不但能减少光罩数，同时绝缘层还能起到类似ESL保护SE不受金属膜层蚀刻损伤的作用。
该设计能适用于多个TFT和电容结合的设计，同时对单个TFT驱动的设计也兼容，方案一还兼容顶栅结构和底栅结构实施的方法。
该设计主要导电走线为2层，因此不需要考虑除GE和SD以外的电极对SE的影响。
e.通过调整像素电极膜层材质和结构，本设计能兼容LCD，OLED，QLED等类型的面板。PE膜层仅用ITO且主要显示区域至于金属走线以外时可以适用于背光发光的显示面板，如LCD和光激发的OLED及QLED等；PE膜层使用金属和ITO复合膜层时，此时因像素电极具有较好的反射性，因此能适用于自发光的OLED和QLED等显示设备或作为感应TFT使用。
一种晶体管制作方法，包括如下步骤，在第一金属层内图案化栅极与源漏极，所述栅极与源漏极处于同一水平位置，在栅极与源漏极上设置第一绝缘层，在第一绝缘层处设置通孔，再设置半导体层，所述半导体层在栅极层的竖直上方，再在半导体层上方设置第二绝缘层，在第二绝缘层内设置过孔，在第二绝缘层上设置第二金属层，所述第二金属层通过通孔及过孔连接栅极金属及源漏极金属走线。
具体地，所述第二金属层为金属及ITO复合膜层。
进一步地，所述第一绝缘层镀膜在第一金属层上。
需要说明的是，尽管在本文中已经对上述各实施例进行了描述，但并非因此限制本发明的专利保护范围。因此，基于本发明的创新理念，对本文所述实施例进行的变更和修改，或利用本发明说明书及附图内容所作的等效结构或等效流程变换，直接或间接地将以上技术方案运用在其他相关的技术领域，均包括在本发明的专利保护范围之内。
Claims (6)
1.一种晶体管结构，其特征在于，包括第一金属层，所述第一金属层内图案化栅极与源漏极，图案化的栅极与源漏极处于同一水平位置，包括第一绝缘层，第一绝缘层包覆在图案化后的栅极层与源漏极层之上，第一绝缘层还包括通孔，第一绝缘层上还包括半导体层，所述半导体层在栅极层的竖直上方，半导体层上方还设置有第二绝缘层，第二绝缘层还包括过孔，第二绝缘层的上方还设置有第二金属层，所述第二金属层通过通孔及过孔连接栅极金属及源漏极金属走线。
2.根据权利要求1所述晶体管结构，其特征在于，所述第二金属层为金属及ITO复合膜层。
3.根据权利要求1所述的晶体管结构，其特征在于，所述第一绝缘层镀膜在第一金属层上。
4.一种晶体管制作方法，其特征在于，包括如下步骤，在第一金属层内图案化栅极与源漏极，所述栅极与源漏极处于同一水平位置，在栅极与源漏极上设置第一绝缘层，在第一绝缘层处设置通孔，再设置半导体层，所述半导体层在栅极层的竖直上方，再在半导体层上方设置第二绝缘层，在第二绝缘层内设置过孔，在第二绝缘层上设置第二金属层，所述第二金属层通过通孔及过孔连接栅极金属及源漏极金属走线。
5.根据权利要求1所述的晶体管制作方法，其特征在于，所述第二金属层为金属及ITO复合膜层。
6.根据权利要求1所述的晶体管制作方法，其特征在于，所述第一绝缘层镀膜在第一金属层上。
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