WO2023197369A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023197369A1
WO2023197369A1 PCT/CN2022/088829 CN2022088829W WO2023197369A1 WO 2023197369 A1 WO2023197369 A1 WO 2023197369A1 CN 2022088829 W CN2022088829 W CN 2022088829W WO 2023197369 A1 WO2023197369 A1 WO 2023197369A1
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WO
WIPO (PCT)
Prior art keywords
layer
metal layer
display panel
via hole
substrate
Prior art date
Application number
PCT/CN2022/088829
Other languages
English (en)
French (fr)
Inventor
胡泽敏
王超
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US17/756,043 priority Critical patent/US20240153961A1/en
Publication of WO2023197369A1 publication Critical patent/WO2023197369A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the present application relates to the field of display, and in particular, to a display panel and a display device.
  • the present invention provides a display panel and a display device, which can reduce the technical problems of the current number of manufacturing processes and the number of masks for display panels.
  • An embodiment of the present application provides a display panel, including:
  • a first metal layer located on one side of the substrate
  • a second metal layer is located on the side of the first metal layer away from the substrate.
  • the second metal layer includes a plurality of gate electrodes and multiple sets of source and drain electrodes arranged on the same layer;
  • the display panel further includes a plurality of data lines, any of the data lines is arranged in the same layer as the first metal layer, and the data lines are electrically connected to the source and drain electrodes.
  • the display panel further includes an active layer located between the second metal layer and the first metal layer; wherein the orthographic projection of any of the data lines on the substrate is located on the The active layer is outside the orthographic projection on the substrate.
  • the display panel further includes a buffer layer located between the active layer and the first metal layer, and an interlayer insulating layer located between the active layer and the second metal layer;
  • the interlayer insulating layer includes a plurality of first via holes and a plurality of second via holes
  • the buffer layer includes a plurality of third via holes
  • the source and drain electrodes include oppositely arranged source electrodes and drain electrodes, so The first via hole and the third via hole are arranged through each other, the source electrode is electrically connected to the data line through the first via hole and the third via hole, and the source electrode passes through the second via hole.
  • the via hole is electrically connected to the active layer; wherein the direction of connection of the first via hole and the second via hole corresponding to the same source electrode is parallel to the extension direction of the data line.
  • the data line includes a first section and a second section connected and arranged, and the first section and the second section are arranged in parallel; wherein the active layer is on the first metal layer.
  • the projection is located on the extension line of the first section, the orthographic projection of the active layer on the first metal layer is located outside the extension line of the second section, and the source electrode is connected to the extension line corresponding to the first section. An electrical connection.
  • the interlayer insulating layer further includes a plurality of fourth via holes, and the drain electrode is electrically connected to the active layer through the fourth via holes;
  • the display panel further includes a plurality of fourth via holes located on the second metal a pixel electrode layer on a side away from the substrate, and a flat layer between the pixel electrode layer and the second metal layer; wherein the flat layer includes a plurality of fifth via holes, and the pixel The electrode layer is electrically connected to the drain electrode through the fifth via hole.
  • the active layer includes a channel region, a heavily doped region, and a lightly doped region located between the channel region and the heavily doped region; wherein the gate electrode and the channel
  • the source electrode is correspondingly connected to the heavily doped region through the second via hole
  • the drain electrode is correspondingly connected to the heavily doped region through the fourth via hole.
  • the orthographic projection of the fifth via hole on the substrate is located within the orthographic projection of the drain electrode on the substrate, and the orthographic projection of the fifth via hole on the substrate is is located outside the orthographic projection of the active layer on the substrate.
  • the first metal layer includes a plurality of light-shielding units spaced apart from any of the data lines and arranged on the same layer; wherein the orthographic projection of the active layer on the first metal layer is located corresponding to the within the shading unit.
  • the second metal layer further includes a plurality of scan lines arranged along a first direction; wherein any of the data lines is arranged along a second direction, and the first direction is perpendicular to the second direction. .
  • the first metal layer further includes a reflective unit, the reflective unit is located between two adjacent data lines and is spaced apart from any one of the data lines.
  • An embodiment of the present application also provides a display device, including a display panel and a device main body, the device main body and the display panel being combined into one body; wherein the display panel includes:
  • a first metal layer located on one side of the substrate
  • a second metal layer is located on the side of the first metal layer away from the substrate.
  • the second metal layer includes a plurality of gate electrodes and multiple sets of source and drain electrodes arranged on the same layer;
  • the display panel further includes a plurality of data lines, any of the data lines is arranged in the same layer as the first metal layer, and the data lines are electrically connected to the source and drain electrodes.
  • the display panel further includes an active layer located between the second metal layer and the first metal layer; wherein the orthographic projection of any of the data lines on the substrate is located on the The active layer is outside the orthographic projection on the substrate.
  • the display panel further includes a buffer layer located between the active layer and the first metal layer, and an interlayer insulating layer located between the active layer and the second metal layer;
  • the interlayer insulating layer includes a plurality of first via holes and a plurality of second via holes
  • the buffer layer includes a plurality of third via holes
  • the source and drain electrodes include oppositely arranged source electrodes and drain electrodes, so The first via hole and the third via hole are arranged through each other, the source electrode is electrically connected to the data line through the first via hole and the third via hole, and the source electrode passes through the second via hole.
  • the via hole is electrically connected to the active layer; wherein the direction of connection of the first via hole and the second via hole corresponding to the same source electrode is parallel to the extension direction of the data line.
  • the data line includes a first section and a second section connected and arranged, and the first section and the second section are arranged in parallel; wherein the active layer is on the first metal layer.
  • the projection is located on the extension line of the first section, the orthographic projection of the active layer on the first metal layer is located outside the extension line of the second section, and the source electrode is connected to the extension line corresponding to the first section. An electrical connection.
  • the interlayer insulating layer further includes a plurality of fourth via holes, and the drain electrode is electrically connected to the active layer through the fourth via holes;
  • the display panel further includes a plurality of fourth via holes located on the second metal a pixel electrode layer on a side away from the substrate, and a flat layer between the pixel electrode layer and the second metal layer; wherein the flat layer includes a plurality of fifth via holes, and the pixel The electrode layer is electrically connected to the drain electrode through the fifth via hole.
  • the active layer includes a channel region, a heavily doped region, and a lightly doped region located between the channel region and the heavily doped region; wherein the gate electrode and the channel
  • the source electrode is correspondingly connected to the heavily doped region through the second via hole
  • the drain electrode is correspondingly connected to the heavily doped region through the fourth via hole.
  • the orthographic projection of the fifth via hole on the substrate is located within the orthographic projection of the drain electrode on the substrate, and the orthographic projection of the fifth via hole on the substrate is is located outside the orthographic projection of the active layer on the substrate.
  • the first metal layer includes a plurality of light-shielding units spaced apart from any of the data lines and arranged on the same layer; wherein the orthographic projection of the active layer on the first metal layer is located corresponding to the within the shading unit.
  • the second metal layer further includes a plurality of scan lines arranged along a first direction; wherein any of the data lines is arranged along a second direction, and the first direction is perpendicular to the second direction. .
  • the first metal layer further includes a reflective unit, the reflective unit is located between two adjacent data lines and is spaced apart from any one of the data lines.
  • the present invention reduces the thickness of the film layer and at the same time, the gate electrode
  • the source and drain electrodes are formed using a photomask process, which reduces the number of processes and photomasks, improves production efficiency, increases the display aperture ratio, and improves the display effect.
  • Figure 1 is a schematic structural diagram of a first structure of a display panel provided by an embodiment of the present invention
  • Figure 2 is a schematic structural diagram of a second structure of a display panel provided by an embodiment of the present invention.
  • Figure 3 is a schematic top view of a third structure of a display panel provided by an embodiment of the present invention.
  • Figure 4 is a schematic top view of a fourth structure of a display panel provided by an embodiment of the present invention.
  • Figure 5 is a schematic top view of a fifth structure of a display panel provided by an embodiment of the present invention.
  • Figure 6 is a schematic top view of a sixth structure of a display panel provided by an embodiment of the present invention.
  • Figure 7 is a schematic top view of a seventh structure of a display panel provided by an embodiment of the present invention.
  • Figure 8 is a step flow chart of a manufacturing method of a display panel provided by an embodiment of the present invention.
  • 9A to 9E are a first schematic flowchart of the manufacturing method of a display panel provided by an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a display device provided by an embodiment of the present invention.
  • the present application provides a display panel and a display device.
  • a display panel and a display device.
  • the present application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described here are only used to explain the present application and are not used to limit the present application.
  • Embodiments of the present application provide a display panel and a display device. Each is explained in detail below. It should be noted that the order of description of the following embodiments does not limit the preferred order of the embodiments.
  • an embodiment of the present invention provides a display panel 100, including:
  • the first metal layer 300 is located on one side of the substrate 200;
  • the second metal layer 400 is located on the side of the first metal layer 300 away from the substrate 200.
  • the second metal layer 400 includes a plurality of gate electrodes 410 and a plurality of sets of source and drain electrodes 420 arranged in the same layer;
  • the display panel 100 further includes a plurality of data lines 500 , any one of the data lines 500 is arranged in the same layer as the first metal layer 300 , and the data lines 500 are electrically connected to the source and drain electrodes 420 .
  • the present invention reduces the thickness of the film layer and at the same time, the gate electrode
  • the source and drain electrodes are formed using a photomask process, which reduces the number of processes and photomasks, improves production efficiency, increases the display aperture ratio, and improves the display effect.
  • the display panel 100 includes a substrate 200, a first metal layer 300 located on one side of the substrate 200, and a first metal layer 300 located on one side of the substrate 200.
  • the second metal layer 400 on the side away from the substrate 200 includes a plurality of gate electrodes 410 and a plurality of sets of source and drain electrodes 420 arranged on the same layer.
  • the display panel 100 further includes a plurality of gate electrodes 410 and a plurality of sets of source and drain electrodes 420 .
  • There are three data lines 500 any one of the data lines 500 is arranged in the same layer as the first metal layer 300 , and the data lines 500 are electrically connected to the source and drain electrodes 420 .
  • the gate electrode 410 and the source and drain electrode 420 can be formed together, and the wiring of the data line 500 is provided in the first metal layer 300 on the side of the second metal layer 400 close to the substrate 200 , the first metal layer 300 is used to arrange the data lines 500, and the data lines 500 and the source and drain electrodes 420 are bridged through the second metal layer 400, which not only reduces the thickness of the film layer, but also reduces the number of processes and the number of masks.
  • the production efficiency is improved, the display aperture ratio is increased, and the display effect is improved.
  • the display panel 100 further includes an active layer 600 located between the second metal layer 400 and the first metal layer 300 ; wherein any one The orthographic projection of the data line 500 on the substrate 200 is located outside the orthographic projection of the active layer 600 on the substrate 200 .
  • the data line 500 In order to weaken the influence of the signal of the data line 500 on the active layer 600, the data line 500 needs to avoid the active layer 600. In the top view direction, the data line 500 and the active layer 600 has no overlap, which can reduce the impact of the data line 500 on the active layer 600, thereby improving the display effect of the display panel 100.
  • the display panel 100 further includes a buffer layer 210 between the active layer 600 and the first metal layer 300 , and a buffer layer 210 between the active layer 600 and the first metal layer 300 .
  • the buffer layer 210 includes a plurality of third via holes 830.
  • the source and drain electrodes 420 include oppositely arranged source electrodes 421 and drain electrodes 422.
  • the first via holes 810 and the third via holes 830 are arranged through each other.
  • the source electrode 421 is electrically connected to the data line 500 through the first via hole 810 and the third via hole 830, and the source electrode 421 is electrically connected to the active layer 600 through the second via hole 820; wherein , the direction of the connection between the first via hole 810 and the second via hole 820 corresponding to the same source electrode 421 is parallel to the extension direction of the data line 500 .
  • the gate 410 is switched to the first metal layer 300 and the active layer 600 through the first via hole 810 and the second via hole 820 respectively, and the arrangement direction of the data lines 500 is the third One direction, the first direction in the figure is the Y-axis direction, the arrangement direction of the scan lines 411 connected to the gate electrode is the second direction, the second direction is the X-axis direction, the arrangement of the line-changing part The direction is parallel to the extension direction of the data line 500 , which can save the arrangement space in the second direction, facilitate the installation of more pixels and wiring, and improve the display pixel density of the display panel 100 .
  • the data line 500 includes a first section 510 and a second section 520 that are connected and arranged, and the first section 510 and the second section 520 are arranged in parallel; wherein , the orthographic projection of the active layer 600 on the first metal layer 300 is located above the extension line of the first segment 510 , and the orthographic projection of the active layer 600 on the first metal layer 300 Located outside the extension line of the second section 520 , the source 421 is electrically connected to the corresponding first section 510 .
  • the source 421 is electrically connected to the first section 510, which can realize conduction between the source 421 and the data line 500.
  • the data line 500 is wound to avoid the active layer 600 corresponding to the source and drain electrode 420, to avoid the impact of the data line 500 on the active layer 600, and to facilitate the replacement of the line part in the third
  • the arrangement in one direction can save the arrangement space in the second direction, facilitate the arrangement of more pixels and wiring, and improve the display pixel density of the display panel 100 .
  • the data line 500 also includes a third section 530 connecting the first section 510 and the second section 520, and a third section 530 parallel to the first section 510.
  • the fourth section 540, and the fifth section 550 connecting the second section 520 and the fourth section 540, the third section 530 can be perpendicular to the first section 510, and the fifth section 550 can be perpendicular to At said fourth paragraph 540.
  • the data line 500 is wound to avoid the active layer 600 to avoid the impact of the data line 500 on the active layer 600 and to facilitate the arrangement of the line replacement part in the first direction. , can save the arrangement space in the second direction, facilitate the installation of more pixels and wiring, and improve the display pixel density of the display panel 100 .
  • the interlayer insulating layer 700 further includes a plurality of fourth via holes 840, and the drain electrode 422 is connected to the drain electrode 422 through the fourth via holes 840.
  • the active layer 600 is electrically connected; the display panel 100 also includes a pixel electrode layer 230 located on the side of the second metal layer 400 away from the substrate 200, and a pixel electrode layer 230 located between the pixel electrode layer 230 and the second metal layer 230.
  • the flat layer 220 between the layers 400; wherein the flat layer 220 includes a plurality of fifth via holes 850, and the pixel electrode layer 230 is electrically connected to the drain electrode 422 through the fifth via holes 850.
  • the shape and coverage of the electrode layer 230 and the flat layer 220 are sufficient to achieve both functions.
  • the specific shapes and coverage areas in the figures are only for convenience and clear drawing, and are not specifically limited.
  • the patterned holes in the interlayer insulating layer 700 enable the source electrode 421 and the drain electrode 422 of the second metal layer 400 to be electrically connected to the active layer 600 respectively.
  • by connecting the The patterned holes in the flat layer 220 enable the pixel electrode layer 230 to be electrically connected to the drain electrode 422, and the drain electrode 422 transmits signals to the pixel electrode layer 230 to achieve display.
  • the orthographic projection of the fifth via hole 850 on the substrate 200 is located within the orthographic projection of the drain electrode 422 on the substrate 200 , The orthographic projection of the fifth via hole 850 on the substrate 200 is located outside the orthographic projection of the active layer 600 on the substrate 200 .
  • FIG. 6 depicts two relationships between the fifth via hole 850 and the active layer 600. Since the thickness of the flat layer 220 is relatively thick, if the size of the fifth via hole 850 is small, it is easy to cause The pixel electrode layer 230 is broken in the fifth via hole 850, the drain electrode 422 is extended in a direction away from the center corresponding to the active layer 600, and the fifth via hole 850 is connected to the fourth via hole.
  • the holes 840 are staggered to facilitate increasing the size of the fifth via hole 850, making the connection between the pixel electrode layer 230 and the drain electrode 422 more stable, and improving the display effect.
  • the active layer 600 includes a channel region 610 , a heavily doped region 630 , and a lightly doped region between the channel region 610 and the heavily doped region 630 .
  • Region 620 wherein, the gate electrode 410 corresponds to the channel region 610, the source electrode 421 is connected to the heavily doped region 630 through the second via hole 820, and the drain electrode 422 passes through the second via hole 820.
  • the fourth via hole 840 is correspondingly connected to the heavily doped region 630 .
  • the gate electrode 410, the source electrode 421 and the drain electrode 422 arranged in the same layer correspond to different regions of the active layer 600, the gate electrode 410 corresponds to the channel region 610, and the gate electrode 410 corresponds to the channel region 610.
  • the source electrode 421 is correspondingly connected to the heavily doped region 630 through the second via hole 820
  • the drain electrode 422 is correspondingly connected to the heavily doped region 630 through the fourth via hole 840
  • the gate electrode 410 can realize switching of the channel region 610 of the active layer 600, and both the source electrode 421 and the drain electrode 422 are connected to the heavily doped region 630, which is beneficial to improving the stability of the active layer 600.
  • the doping of the active layer 600 may be N-type doping
  • the heavily doped region 630 may be represented by N+
  • the lightly doped region 620 may be represented by N-.
  • the first metal layer 300 includes a plurality of light shielding units 310 spaced apart from any of the data lines 500 and arranged on the same layer; wherein, the active layer 600 The orthographic projection on the first metal layer 300 is located within the corresponding light shielding unit 310 .
  • the first metal layer 300 also includes a light-shielding unit 310 for blocking light directed to the active layer 600 to reduce the photoelectric impact of light on the active layer 600.
  • the light-shielding unit 310 and Any one of the data lines 500 is arranged at intervals, and the two are insulated to reduce the signal influence of the data line 500 on the light-shielding unit 310 .
  • the first metal layer 300 further includes a reflective unit, which is located between two adjacent data lines 500 and spaced apart from any one of the data lines 500 .
  • the reflective unit can reflect the light emitted from the first metal layer 300 away from the substrate 200 toward the first metal layer 300, so as to The light extraction rate of the display panel 100 is improved.
  • the second metal layer 400 further includes a plurality of scan lines 411 arranged along the first direction; wherein any of the data lines 500 is arranged along the second direction. cloth, the first direction is perpendicular to the second direction.
  • the scan lines 411 and the data lines 500 are arranged in a criss-cross pattern, and the data lines 500 are electrically connected to the gate 410 to provide signals to the gate 410 .
  • the display panel 100 may be a liquid crystal display panel 100 or a self-luminous display panel 100.
  • the display panel 100 is a liquid crystal display panel 100, and the display panel 100 further includes a passivation layer 240 located on the pixel electrode layer 230 and a common electrode layer located on the passivation layer 240. 250.
  • the display panel 100 is a liquid crystal display panel 100 for explanation.
  • the display panel 100 also includes a liquid crystal layer, a color filter layer, and upper and lower polarizing layers.
  • the display panel 100 is a self-luminous display panel 100 , and the display panel 100 further includes a light-emitting device layer located on the pixel electrode layer 230 .
  • the light-emitting device layer includes the pixel electrode layer 230 located on the third insulating layer, a luminescent material layer located on the pixel electrode layer 230, and a cathode located on the luminescent material layer.
  • the display panel 100 further includes a pixel definition layer provided in the same layer as the luminescent material layer, a polarizing layer located on the light-emitting device layer, and a flexible cover located on the polarizing layer.
  • the display panel 100 It also includes corresponding adhesive layers between the polarizing layer and the flexible cover, between the light emitting device layer and the polarizing layer, and between the backplane and the substrate 200 .
  • the light-emitting device layer may include OLED (Organic Light-Emitting Diode (organic light-emitting semiconductor) materials can also include Micro LED or Mini LED, which are not specifically limited here.
  • OLED Organic Light-Emitting Diode (organic light-emitting semiconductor) materials can also include Micro LED or Mini LED, which are not specifically limited here.
  • the materials of the first metal layer 300 and the second metal layer 400 may be a single layer of metal or a stacked metal layer, which is not specifically limited here.
  • the present invention reduces the thickness of the film layer and at the same time, the gate electrode
  • the source and drain electrodes are formed using a photomask process, which reduces the number of processes and photomasks, improves production efficiency, increases the display aperture ratio, and improves the display effect.
  • an embodiment of the present invention also provides a method for manufacturing a display panel 100, which includes:
  • the first via holes 810 expose the data line 500;
  • the present invention reduces the thickness of the film layer and at the same time, the gate electrode
  • the source and drain electrodes are formed using a photomask process, which reduces the number of processes and photomasks, improves production efficiency, increases the display aperture ratio, and improves the display effect.
  • the manufacturing method of the display panel 100 includes:
  • the substrate 200 may be a rigid substrate 200, such as glass material, or a flexible substrate 200, such as polyimide.
  • step S200 includes:
  • step S210 includes: forming a buffer layer 210 including a plurality of third via holes 830 on the substrate 200 .
  • the data lines 500 are arranged along the first direction.
  • step S230 includes:
  • the first metal layer 300 includes a plurality of light shielding units 310 spaced apart from any of the data lines 500 and arranged on the same layer; wherein the active layer 600 is in the first metal layer 300 The orthographic projection is located within the corresponding light-shielding unit 310 .
  • the first metal layer 300 also includes a light-shielding unit 310 for blocking light directed to the active layer 600 to reduce the photoelectric impact of light on the active layer 600.
  • the light-shielding unit 310 and Any one of the data lines 500 is arranged at intervals, and the two are insulated to reduce the signal influence of the data line 500 on the light-shielding unit 310 .
  • step S230 includes:
  • the first metal layer 300 further includes a reflective unit, which is located between two adjacent data lines 500 and spaced apart from any one of the data lines 500 .
  • the reflective unit can reflect the light emitted from the first metal layer 300 away from the substrate 200 towards the first metal layer 300, so as to The light extraction rate of the display panel 100 is improved.
  • the first via hole 810 and the third via hole 830 are provided through each other, leaving the data line 500 exposed.
  • step S300 includes:
  • step S310 includes:
  • S312. Perform doping treatment on the active material layer to form a channel region 610 close to the central region of the active material layer, a heavily doped region 630 far away from the central region of the active material layer, and the heavily doped region 630. Lightly doped regions 620 between doped regions 630.
  • the active layer 600 includes a channel region 610, a heavily doped region 630, and a lightly doped region 620 located between the channel region 610 and the heavily doped region 630; wherein, The gate electrode 410 corresponds to the channel region 610, the source electrode 421 is connected to the heavily doped region 630 through the second via hole 820, and the drain electrode 422 passes through the fourth via hole. 840 is correspondingly connected to the heavily doped region 630 .
  • the first via hole 810 exposes the data line 500
  • the second via hole 820 and the fourth via hole 840 expose the active layer 600 .
  • the display panel 100 further includes an active layer 600 located between the second metal layer 400 and the first metal layer 300; wherein any of the data lines 500 is on the substrate.
  • the orthographic projection on the base 200 is located outside the orthographic projection of the active layer 600 on the substrate 200 .
  • S400 Form a second metal material layer 401 on the side of the interlayer insulating layer 700 away from the data line 500. Please refer to FIG. 9D.
  • the first metal material layer and the second metal material layer 401 may be a single layer of metal or a stacked metal layer, which is not specifically limited here.
  • step S500 includes:
  • the display panel 100 further includes a buffer layer 210 between the active layer 600 and the first metal layer 300, and a buffer layer 210 between the active layer 600 and the second metal layer.
  • the source and drain electrodes 420 include source electrodes 421 and drain electrodes 422 that are arranged oppositely.
  • the first via hole 810 and the third via hole 830 are arranged through each other.
  • the source electrode 421 passes through the first via hole 810 and the third via hole 830 .
  • the third via hole 830 is electrically connected to the data line 500, and the source electrode 421 is electrically connected to the active layer 600 through the second via hole 820; wherein, the source electrode 421 corresponds to The direction of the connection between the first via hole 810 and the second via hole 820 is parallel to the extending direction of the data line 500 .
  • the data line 500 includes a first section 510 and a second section 520 arranged in connection, and the first section 510 and the second section 520 are arranged in parallel; wherein the active layer 600 is The orthographic projection of the first metal layer 300 is located on the extension line of the first section 510 , and the orthographic projection of the active layer 600 on the first metal layer 300 is located on the second section 520 Outside the extension line, the source 421 is electrically connected to the corresponding first segment 510 .
  • the data line 500 further includes a third section 530 connecting the first section 510 and the second section 520, a fourth section 540 parallel to the first section 510, and a third section 540 connected to the first section 510 and the second section 520.
  • the third section 530 can be perpendicular to the first section 510 and the fifth section 550 can be perpendicular to the fourth section 540 of the second section 520 and the fourth section 540 .
  • the manufacturing method of the display panel 100 further includes:
  • the interlayer insulating layer 700 further includes a plurality of fourth via holes 840, and the drain electrode 422 is electrically connected to the active layer 600 through the fourth via holes 840;
  • the display panel 100 also includes a pixel electrode layer 230 located on the side of the second metal layer 400 away from the substrate 200, and a flat layer 220 located between the pixel electrode layer 230 and the second metal layer 400; wherein, The flat layer 220 includes a plurality of fifth via holes 850 , and the pixel electrode layer 230 is electrically connected to the drain electrode 422 through the fifth via holes 850 .
  • the present invention reduces the thickness of the film layer and at the same time, the gate electrode
  • the source and drain electrodes are formed using a photomask process, which reduces the number of processes and photomasks, improves production efficiency, increases the display aperture ratio, and improves the display effect.
  • an embodiment of the present invention also provides a display device 10 , including any of the above-mentioned display panels 100 and a device body 20 .
  • the device body 20 and the display panel 100 are combined into one body.
  • the device main body 20 may include a middle frame, frame glue, etc.
  • the display device 10 may be a display terminal such as a mobile phone, a tablet, or a television, which is not limited here.
  • the display device 10 further includes a plurality of optical devices, and the optical devices may be any one or a combination of a camera, a distance sensor, a fingerprint recognition device, and an infrared sensor.
  • Embodiments of the present invention disclose a display panel and a display device; the display panel includes a substrate, a first metal layer located on one side of the substrate, and a second metal layer located on the side of the first metal layer away from the substrate. layer, the second metal layer includes a plurality of gate units and multiple sets of source and drain electrodes arranged on the same layer, wherein the display panel also includes a plurality of data lines, any of which is arranged on the same layer as the first metal layer , the data line is electrically connected to the source and drain; in the present invention, the gate and the source and drain are arranged in the same layer, the data line is arranged in the same layer as the first metal layer, and the first metal layer is used to arrange the data lines.
  • the gate and source and drain electrodes are formed with a photomask process, which reduces the number of processes and the number of photomasks, improves production efficiency, increases the display aperture ratio, and improves the display effect.

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Abstract

一种显示面板(100)及显示装置(10)；显示面板(100)包括衬底(200)、位于衬底(200)一侧的第一金属层(300)、及位于第一金属层(300)远离衬底(200)一侧的第二金属层(400)，第二金属层(400)包括同层设置的多个栅极(410)和多组源漏极(420)，显示面板(100)还包括多条数据线(500)，任一数据线(500)与第一金属层(300)同层设置，数据线(500)与源漏极(420)电连接。

Description

显示面板及显示装置 技术领域
本申请涉及显示领域，尤其涉及一种显示面板及显示装置。
 背景技术
近些年，为了追求更好的显示效果，不断地追求高像素密度，而高像素密度带来金属线密度增加，在工艺制程的限制下，金属线密度增多一般会通过增加金属膜层数量，通过不同膜层上下交叠，但是该方式会增加光罩张数以及制程数量，因此，针对高像素密度显示面板，如何减少制程数量及光罩数量就显得尤为重要。
因此，亟需一种显示面板及显示装置以解决上述技术问题。
 技术问题
本发明提供一种显示面板及显示装置，可以降低目前显示面板的制程数量及光罩数量的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供了一种显示面板，包括：
衬底；
第一金属层，位于所述衬底的一侧；
第二金属层，位于所述第一金属层远离所述衬底一侧，所述第二金属层包括同层设置的多个栅极和多组源漏极；
其中，所述显示面板还包括多条数据线，任一所述数据线与所述第一金属层同层设置，所述数据线与所述源漏极电连接。
优选的，所述显示面板还包括位于所述第二金属层与所述第一金属层之间的有源层；其中，任一所述数据线在所述衬底上的正投影位于所述有源层在所述衬底上的正投影之外。
优选的，所述显示面板还包括位于所述有源层和所述第一金属层之间的缓冲层、及位于所述有源层和所述第二金属层之间的层间绝缘层；所述层间绝缘层包括多个第一过孔、及多个第二过孔，所述缓冲层包括多个第三过孔，所述源漏极包括相对设置的源极和漏极，所述第一过孔与所述第三过孔贯通设置，所述源极通过所述第一过孔和所述第三过孔与所述数据线电连接，所述源极通过所述第二过孔与所述有源层电连接；其中，同一所述源极对应的所述第一过孔和所述第二过孔的连线的方向，与所述数据线的延伸方向平行。
优选的，所述数据线包括连接设置的第一段和第二段，所述第一段和所述第二段平行设置；其中，所述有源层在所述第一金属层上的正投影位于所述第一段的延长线之上，所述有源层在所述第一金属层上的正投影位于所述第二段的延长线之外，所述源极与对应所述第一段电连接。
优选的，所述层间绝缘层还包括多个第四过孔，所述漏极通过所述第四过孔与所述有源层电连接；所述显示面板还包括位于所述第二金属层远离所述衬底一侧的像素电极层、及位于所述像素电极层与所述第二金属层之间的平坦层；其中，所述平坦层包括多个第五过孔，所述像素电极层通过所述第五过孔与所述漏极电连接。
优选的，所述有源层包括沟道区、重掺杂区、位于所述沟道区和所述重掺杂区之间的轻掺杂区；其中，所述栅极与所述沟道区对应，所述源极通过所述第二过孔与所述重掺杂区对应连接，所述漏极通过所述第四过孔与所述重掺杂区对应连接。
优选的，所述第五过孔在所述衬底上的正投影位于所述漏极在所述衬底上的正投影之内，所述第五过孔在所述衬底上的正投影位于所述有源层在所述衬底上的正投影之外。
优选的，所述第一金属层包括与任一所述数据线间隔且同层设置的多个遮光单元；其中，所述有源层在所述第一金属层上的正投影位于对应所述遮光单元之内。
优选的，所述第二金属层还包括沿第一方向排布的多条扫描线；其中，任一所述数据线沿第二方向排布，所述第一方向与所述第二方向垂直。
优选的，所述第一金属层还包括反光单元，所述反光单元位于相邻两个所述数据线之间且与任一所述数据线间隔设置。
本申请实施例还提供了一种显示装置，包括显示面板及装置主体，所述装置主体与所述显示面板组合为一体；其中，所述显示面板包括：
衬底；
第一金属层，位于所述衬底的一侧；
第二金属层，位于所述第一金属层远离所述衬底一侧，所述第二金属层包括同层设置的多个栅极和多组源漏极；
其中，所述显示面板还包括多条数据线，任一所述数据线与所述第一金属层同层设置，所述数据线与所述源漏极电连接。
优选的，所述显示面板还包括位于所述第二金属层与所述第一金属层之间的有源层；其中，任一所述数据线在所述衬底上的正投影位于所述有源层在所述衬底上的正投影之外。
优选的，所述显示面板还包括位于所述有源层和所述第一金属层之间的缓冲层、及位于所述有源层和所述第二金属层之间的层间绝缘层；所述层间绝缘层包括多个第一过孔、及多个第二过孔，所述缓冲层包括多个第三过孔，所述源漏极包括相对设置的源极和漏极，所述第一过孔与所述第三过孔贯通设置，所述源极通过所述第一过孔和所述第三过孔与所述数据线电连接，所述源极通过所述第二过孔与所述有源层电连接；其中，同一所述源极对应的所述第一过孔和所述第二过孔的连线的方向，与所述数据线的延伸方向平行。
优选的，所述数据线包括连接设置的第一段和第二段，所述第一段和所述第二段平行设置；其中，所述有源层在所述第一金属层上的正投影位于所述第一段的延长线之上，所述有源层在所述第一金属层上的正投影位于所述第二段的延长线之外，所述源极与对应所述第一段电连接。
优选的，所述层间绝缘层还包括多个第四过孔，所述漏极通过所述第四过孔与所述有源层电连接；所述显示面板还包括位于所述第二金属层远离所述衬底一侧的像素电极层、及位于所述像素电极层与所述第二金属层之间的平坦层；其中，所述平坦层包括多个第五过孔，所述像素电极层通过所述第五过孔与所述漏极电连接。
优选的，所述有源层包括沟道区、重掺杂区、位于所述沟道区和所述重掺杂区之间的轻掺杂区；其中，所述栅极与所述沟道区对应，所述源极通过所述第二过孔与所述重掺杂区对应连接，所述漏极通过所述第四过孔与所述重掺杂区对应连接。
优选的，所述第五过孔在所述衬底上的正投影位于所述漏极在所述衬底上的正投影之内，所述第五过孔在所述衬底上的正投影位于所述有源层在所述衬底上的正投影之外。
优选的，所述第一金属层包括与任一所述数据线间隔且同层设置的多个遮光单元；其中，所述有源层在所述第一金属层上的正投影位于对应所述遮光单元之内。
优选的，所述第二金属层还包括沿第一方向排布的多条扫描线；其中，任一所述数据线沿第二方向排布，所述第一方向与所述第二方向垂直。
优选的，所述第一金属层还包括反光单元，所述反光单元位于相邻两个所述数据线之间且与任一所述数据线间隔设置。
 有益效果
本发明通过将栅极和源漏极同层设置，将数据线与第一金属层同层设置，利用第一金属层进行数据线的排布走线，减少了膜层厚度的同时，栅极和源漏极用一道光罩制程形成，减少了制程数量和光罩数量，提高了生产效率，提高了显示开口率，改善了显示效果。
 附图说明
图1是本发明实施例提供的显示面板的第一种结构的结构示意图；
图2是本发明实施例提供的显示面板的第二种结构的结构示意图；
图3是本发明实施例提供的显示面板的第三种结构的俯视示意图；
图4是本发明实施例提供的显示面板的第四种结构的俯视示意图；
图5是本发明实施例提供的显示面板的第五种结构的俯视示意图；
图6是本发明实施例提供的显示面板的第六种结构的俯视示意图；
图7是本发明实施例提供的显示面板的第七种结构的俯视示意图；
图8是本发明实施例提供的显示面板的制作方法的步骤流程图；
图9A至图9E是本发明实施例提供的显示面板的制作方法的第一种流程示意图；
图10是本发明实施例提供的显示装置的结构示意图。
 本发明的实施方式
本申请提供一种显示面板及显示装置，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
本申请实施例提供一种显示面板及显示装置。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
请参阅图1至图7，本发明实施例提供了一种显示面板100，包括：
衬底200；
第一金属层300，位于所述衬底200的一侧；
第二金属层400，位于所述第一金属层300远离所述衬底200一侧，所述第二金属层400包括同层设置的多个栅极410和多组源漏极420；
其中，所述显示面板100还包括多条数据线500，任一所述数据线500与所述第一金属层300同层设置，所述数据线500与所述源漏极420电连接。
本发明通过将栅极和源漏极同层设置，将数据线与第一金属层同层设置，利用第一金属层进行数据线的排布走线，减少了膜层厚度的同时，栅极和源漏极用一道光罩制程形成，减少了制程数量和光罩数量，提高了生产效率，提高了显示开口率，改善了显示效果。
现结合具体实施例对本发明的技术方案进行描述。
本实施例中，请参阅图1、图3、图6，所述显示面板100包括衬底200、位于所述衬底200一侧的第一金属层300、及位于所述第一金属层300远离所述衬底200一侧的第二金属层400，所述第二金属层400包括同层设置的多个栅极410和多组源漏极420，其中，所述显示面板100还包括多条数据线500，任一所述数据线500与所述第一金属层300同层设置，所述数据线500与所述源漏极420电连接。
利用一道光罩制成，可以一同形成栅极410和源漏极420，而数据线500的排布走线设置在第二金属层400靠近所述衬底200一侧的第一金属层300中，利用第一金属层300进行数据线500的排布走线，数据线500和源漏极420通过第二金属层400进行桥接，减少了膜层厚度的同时，减少了制程数量和光罩数量，提高了生产效率，提高了显示开口率，改善了显示效果。
在一些实施例中，请参阅图3至图7，所述显示面板100还包括位于所述第二金属层400与所述第一金属层300之间的有源层600；其中，任一所述数据线500在所述衬底200上的正投影位于所述有源层600在所述衬底200上的正投影之外。
为减弱所述数据线500的信号对所述有源层600的影响，所述数据线500需要避开所述有源层600，在俯视方向上，所述数据线500与所述有源层600没有重叠，可以减小所述数据线500对所述有源层600的影响，从而提高所述显示面板100的显示效果。
在一些实施例中，请参阅图1、图3、图6，所述显示面板100还包括位于所述有源层600和所述第一金属层300之间的缓冲层210、及位于所述有源层600和所述第二金属层400之间的层间绝缘层700；所述层间绝缘层700包括多个第一过孔810、及多个第二过孔820，所述缓冲层210包括多个第三过孔830，所述源漏极420包括相对设置的源极421和漏极422，所述第一过孔810与所述第三过孔830贯通设置，所述源极421通过所述第一过孔810和所述第三过孔830与所述数据线500电连接，所述源极421通过所述第二过孔820与所述有源层600电连接；其中，同一所述源极421对应的所述第一过孔810和所述第二过孔820的连线的方向，与所述数据线500的延伸方向平行。
所述栅极410通过所述第一过孔810和所述第二过孔820分别换线至所述第一金属层300和所述有源层600，所述数据线500的排列方向为第一方向，在图中所述第一方向为Y轴方向，连接所述栅极的扫描线411的排列方向为第二方向，所述第二方向为X轴方向，将该换线部分的排列方向与所述数据线500的延伸方向平行，可以节省所述第二方向上的设置排布空间，有利于设置更多的像素及走线，有利于提高所述显示面板100的显示像素密度。
在一些实施例中，请参阅图4至图7，所述数据线500包括连接设置的第一段510和第二段520，所述第一段510和所述第二段520平行设置；其中，所述有源层600在所述第一金属层300上的正投影位于所述第一段510的延长线之上，所述有源层600在所述第一金属层300上的正投影位于所述第二段520的延长线之外，所述源极421与对应所述第一段510电连接。
所述源极421与所述第一段510电连接，可以实现所述源极421与所述数据线500的导通，从所述第一段510至所述第二段520，将所述数据线500进行绕线避开与所述源漏极420对应的所述有源层600，避免所述数据线500对所述有源层600的影响，同时方便该换线部分在所述第一方向上的排布，可以节省所述第二方向上的设置排布空间，有利于设置更多的像素及走线，有利于提高所述显示面板100的显示像素密度。
在一些实施例中，请参阅图5、图7，所述数据线500还包括连接所述第一段510和所述第二段520的第三段530、与所述第一段510平行的第四段540、及连接所述第二段520和所述第四段540的第五段550，所述第三段530可以垂直于所述第一段510，所述第五段550可以垂直于所述第四段540。
将所述数据线500进行绕线避开所述有源层600，避免所述数据线500对所述有源层600的影响，同时方便该换线部分在所述第一方向上的排布，可以节省所述第二方向上的设置排布空间，有利于设置更多的像素及走线，有利于提高所述显示面板100的显示像素密度。
在一些实施例中，请参阅图1、图6、图7，所述层间绝缘层700还包括多个第四过孔840，所述漏极422通过所述第四过孔840与所述有源层600电连接；所述显示面板100还包括位于所述第二金属层400远离所述衬底200一侧的像素电极层230、及位于所述像素电极层230与所述第二金属层400之间的平坦层220；其中，所述平坦层220包括多个第五过孔850，所述像素电极层230通过所述第五过孔850与所述漏极422电连接。
其中，图6、图7中，电极层230及平坦层220的形状及覆盖实现二者功能即可，具体形状和覆盖区域在图中只是为方便清晰作图，不做具体限定，通过对所述层间绝缘层700的图案化打孔，使所述第二金属层400的所述源极421和所述漏极422可以分别与所述有源层600电连接，同时，通过对所述平坦层220的图案化打孔，使所述像素电极层230可以与所述漏极422电连接，所述漏极422给予所述像素电极层230信号传输，实现显示。
在一些实施例中，请参阅图2、图6，所述第五过孔850在所述衬底200上的正投影位于所述漏极422在所述衬底200上的正投影之内，所述第五过孔850在所述衬底200上的正投影位于所述有源层600在所述衬底200上的正投影之外。
其中，图6画出了两种所述第五过孔850与有源层600的关系，由于所述平坦层220的厚度较厚，若所述第五过孔850的尺寸较小，容易导致所述像素电极层230在所述第五过孔850中断裂，将所述漏极422向远离对应所述有源层600中心方向延伸，将所述第五过孔850与所述第四过孔840错开，方便增加所述第五过孔850的尺寸，使所述像素电极层230与所述漏极422连接更稳定，提高显示效果。
在一些实施例中，请参阅图1，所述有源层600包括沟道区610、重掺杂区630、位于所述沟道区610和所述重掺杂区630之间的轻掺杂区620；其中，所述栅极410与所述沟道区610对应，所述源极421通过所述第二过孔820与所述重掺杂区630对应连接，所述漏极422通过所述第四过孔840与所述重掺杂区630对应连接。
同层设置的所述栅极410、所述源极421和所述漏极422，与所述有源层600的不同区域对应，所述栅极410与所述沟道区610对应，所述源极421通过所述第二过孔820与所述重掺杂区630对应连接，所述漏极422通过所述第四过孔840与所述重掺杂区630对应连接，所述栅极410可以实现对所述有源层600的所述沟道区610进行开关，所述源极421和所述漏极422均连接至重掺杂区630，有利于提高所述有源层600的半导体性能。
在一些实施例中，所述有源层600的掺杂可以为N型掺杂，所述重掺杂区630可以用N+表示，所述轻掺杂区620可以用N-表示。
在一些实施例中，请参阅图3至图7，所述第一金属层300包括与任一所述数据线500间隔且同层设置的多个遮光单元310；其中，所述有源层600在所述第一金属层300上的正投影位于对应所述遮光单元310之内。
所述第一金属层300还包括遮光单元310，用于遮挡射向所述有源层600的光线，以减小光线对所述有源层600的光电影响，同时，所述遮光单元310与任一所述数据线500间隔设置，二者绝缘，以减少所述数据线500对所述遮光单元310的信号影响。
在一些实施例中，所述第一金属层300还包括反光单元，所述反光单元位于相邻两个所述数据线500之间且与任一所述数据线500间隔设置。
当所述显示面板100为自发光显示面板100时，所述反光单元可以将从所述第一金属层300远离所述衬底200方向射向所述第一金属层300的光线进行反射，以提高所述显示面板100的出光率。
在一些实施例中，请参阅图3至图7，所述第二金属层400还包括沿第一方向排布的多条扫描线411；其中，任一所述数据线500沿第二方向排布，所述第一方向与所述第二方向垂直。
所述扫描线411与所述数据线500横纵交错排列，所述数据线500与所述栅极410电连接，以提供给所述栅极410信号。
在一些实施例中，所述显示面板100可以为液晶显示面板100，也可以为自发光显示面板100。
在一些实施例中，所述显示面板100为液晶显示面板100，所述显示面板100还包括位于所述像素电极层230上的钝化层240及位于所述钝化层240上的公共电极层250，在图1、图2中仅以所述显示面板100为液晶显示面板100为例进行说明。
所述显示面板100还包括液晶层、彩膜层及上下偏光层。
在一些实施例中，所述显示面板100为自发光显示面板100，所述显示面板100还包括位于所述像素电极层230上的发光器件层。
在一些实施例中，所述发光器件层包括位于所述第三绝缘层上的所述像素电极层230、位于所述像素电极层230上的发光材料层及位于所述发光材料层上的阴极层，所述显示面板100还包括与所述发光材料层同层设置的像素定义层、位于所述发光器件层上的偏光层、位于所述偏光层上的柔性盖板，所述显示面板100还包括位于所述偏光层与所述柔性盖板之间的、位于所述发光器件层与所述偏光层之间的及位于所述背板与所述衬底200之间的对应粘结层。
在一些实施例中，所述发光器件层可以包括OLED（Organic Light-Emitting Diode，有机发光半导体）材料，也可以包括Micro LED或Mini LED，在此不做具体限定。
在一些实施例中，所述第一金属层300和所述第二金属层400的材料可以为单层金属，也可以为叠层金属层，在此不做具体限定。
本发明通过将栅极和源漏极同层设置，将数据线与第一金属层同层设置，利用第一金属层进行数据线的排布走线，减少了膜层厚度的同时，栅极和源漏极用一道光罩制程形成，减少了制程数量和光罩数量，提高了生产效率，提高了显示开口率，改善了显示效果。
请参阅图8，本发明实施例还提供了一种显示面板100的制作方法，包括：
S100、提供一衬底200；
S200、在所述衬底200上形成多条数据线500，以形成第一金属层300；
S300、在所述数据线500远离所述衬底200一侧形成包括多个第一过孔810的层间绝缘层700，所述第一过孔810使所述数据线500裸露；
S400、在所述层间绝缘层700远离所述数据线500一侧形成第二金属材料层401；
S500、将所述第二金属材料层401进行图案化处理，形成多个栅极410和多组源漏极420，以形成第二金属层400，所述源漏极420通过所述第一过孔810与所述数据线500电连接。
本发明通过将栅极和源漏极同层设置，将数据线与第一金属层同层设置，利用第一金属层进行数据线的排布走线，减少了膜层厚度的同时，栅极和源漏极用一道光罩制程形成，减少了制程数量和光罩数量，提高了生产效率，提高了显示开口率，改善了显示效果。
现结合具体实施例对本发明的技术方案进行描述。
本实施例中，所述显示面板100的制作方法包括：
S100、提供一衬底200，请参阅图9A。
在一些实施例中，所述衬底200可以为刚性衬底200，例如玻璃材料，也可以为柔性衬底200，例如聚酰亚胺。
S200、在所述衬底200上形成多条数据线500，以形成第一金属层300，请参阅图9B。
在一些实施例中，步骤S200包括：
S210、在所述衬底200上形成包括缓冲层210。
在一些实施例中，步骤S210包括：在所述衬底200上形成包括多个第三过孔830缓冲层210。
S220、在所述缓冲层210上形成第一金属材料层。
S230、将所述第一金属材料层进行图案化处理，形成多条数据线500，以形成第一金属层300。
在一些实施例中，所述数据线500沿第一方向排布。
在一些实施例中，步骤S230包括：
S231a、将所述第一金属材料层进行图案化处理，形成多条数据线500和多个遮光单元310，以形成第一金属层300。
在一些实施例中，所述第一金属层300包括与任一所述数据线500间隔且同层设置的多个遮光单元310；其中，所述有源层600在所述第一金属层300上的正投影位于对应所述遮光单元310之内。
所述第一金属层300还包括遮光单元310，用于遮挡射向所述有源层600的光线，以减小光线对所述有源层600的光电影响，同时，所述遮光单元310与任一所述数据线500间隔设置，二者绝缘，以减少所述数据线500对所述遮光单元310的信号影响。
在一些实施例中，步骤S230包括：
S231b、将所述第一金属材料层进行图案化处理，形成多条数据线500、多个遮光单元310和多个反光单元，以形成第一金属层300。
在一些实施例中，所述第一金属层300还包括反光单元，所述反光单元位于相邻两个所述数据线500之间且与任一所述数据线500间隔设置。
当所述显示面板100为自发光显示面板100时，所述反光单元可以将从所述第一金属层300远离所述衬底200方向射向所述第一金属层300的光线进行反射，以提高所述显示面板100的出光率。
S300、在所述数据线500远离所述衬底200一侧形成包括多个第一过孔810的层间绝缘层700，所述第一过孔810使所述数据线500裸露，请参阅图9C。
在一些实施例中，所述第一过孔810与所述第三过孔830贯通设置，使所述数据线500裸露。
在一些实施例中，步骤S300包括：
S310、在所述数据线500远离所述衬底200一侧形成有源层600。
在一些实施例中，步骤S310包括：
S311、在所述数据线500远离所述衬底200一侧形成有源材料层。
S312、对所述有源材料层进行掺杂处理，以形成靠近所述有源材料层中心区域的沟道区610、远离所述有源材料层中心区域的重掺杂区630和所述重掺杂区630之间的轻掺杂区620。
在一些实施例中，所述有源层600包括沟道区610、重掺杂区630、位于所述沟道区610和所述重掺杂区630之间的轻掺杂区620；其中，所述栅极410与所述沟道区610对应，所述源极421通过所述第二过孔820与所述重掺杂区630对应连接，所述漏极422通过所述第四过孔840与所述重掺杂区630对应连接。
S320、在所述有源层600远离所述衬底200一侧形成包括多个第一过孔810、多个第二过孔820、多个第四过孔840的层间绝缘层700，所述第一过孔810使所述数据线500裸露，所述第二过孔820和第四过孔840使所述有源层600裸露。
在一些实施例中，所述显示面板100还包括位于所述第二金属层400与所述第一金属层300之间的有源层600；其中，任一所述数据线500在所述衬底200上的正投影位于所述有源层600在所述衬底200上的正投影之外。
S400、在所述层间绝缘层700远离所述数据线500一侧形成第二金属材料层401，请参阅图9D。
在一些实施例中，所述第一金属材料层和所述第二金属材料层401可以为单层金属，也可以为叠层金属层，在此不做具体限定。
S500、将所述第二金属材料层401进行图案化处理，形成多个栅极410和多组源漏极420，以形成第二金属层400，所述源漏极420通过所述第一过孔810与所述数据线500电连接，请参阅图9E。
在一些实施例中，步骤S500包括：
S510、将所述第二金属材料层401进行图案化处理，形成多个栅极410和多组源漏极420，以形成第二金属层400，所述源漏极420通过所述第一过孔810与所述数据线500电连接，所述源漏极420通过所述第二过孔820和所述第四过孔840与所述有源层600电连接。
在一些实施例中，所述显示面板100还包括位于所述有源层600和所述第一金属层300之间的缓冲层210、及位于所述有源层600和所述第二金属层400之间的层间绝缘层700；所述层间绝缘层700包括多个第一过孔810、及多个第二过孔820，所述缓冲层210包括多个第三过孔830，所述源漏极420包括相对设置的源极421和漏极422，所述第一过孔810与所述第三过孔830贯通设置，所述源极421通过所述第一过孔810和所述第三过孔830与所述数据线500电连接，所述源极421通过所述第二过孔820与所述有源层600电连接；其中，同一所述源极421对应的所述第一过孔810和所述第二过孔820的连线的方向，与所述数据线500的延伸方向平行。
在一些实施例中，所述数据线500包括连接设置的第一段510和第二段520，所述第一段510和所述第二段520平行设置；其中，所述有源层600在所述第一金属层300上的正投影位于所述第一段510的延长线之上，所述有源层600在所述第一金属层300上的正投影位于所述第二段520的延长线之外，所述源极421与对应所述第一段510电连接。
在一些实施例中，所述数据线500还包括连接所述第一段510和所述第二段520的第三段530、与所述第一段510平行的第四段540、及连接所述第二段520和所述第四段540的第五段550，所述第三段530可以垂直于所述第一段510，所述第五段550可以垂直于所述第四段540。
在一些实施例中，所述显示面板100的制作方法还包括：
S600、在所述第二金属层400远离所述衬底200一侧形成包括多个第五过孔850的平坦层220。
S700、在所述平坦层220远离所述衬底200一侧形成像素电极层230。
在一些实施例中，所述层间绝缘层700还包括多个第四过孔840，所述漏极422通过所述第四过孔840与所述有源层600电连接；所述显示面板100还包括位于所述第二金属层400远离所述衬底200一侧的像素电极层230、及位于所述像素电极层230与所述第二金属层400之间的平坦层220；其中，所述平坦层220包括多个第五过孔850，所述像素电极层230通过所述第五过孔850与所述漏极422电连接。
本发明通过将栅极和源漏极同层设置，将数据线与第一金属层同层设置，利用第一金属层进行数据线的排布走线，减少了膜层厚度的同时，栅极和源漏极用一道光罩制程形成，减少了制程数量和光罩数量，提高了生产效率，提高了显示开口率，改善了显示效果。
请参阅图10，本发明实施例还提供了一种显示装置10，包括如任一上述的显示面板100及装置主体20，所述装置主体20与所述显示面板100组合为一体。
所述显示面板100的具体结构请参阅任一上述显示面板100的实施例及附图，在此不再赘述。
本实施例中，所述装置主体20可以包括中框、框胶等，所述显示装置10可以为手机、平板、电视等显示终端，在此不做限定。
在一些实施例中，所述显示装置10还包括多个光学器件，所述光学器件可以为摄像头、距离传感器、指纹识别器件、红外传感器中任一种或多种的组合。
本发明实施例公开了一种显示面板及显示装置；该显示面板包括衬底、位于该衬底一侧的第一金属层、及位于该第一金属层远离该衬底一侧的第二金属层，该第二金属层包括同层设置的多个栅极单元和多组源漏极，其中，该显示面板还包括多条数据线，任一该数据线与该第一金属层同层设置，该数据线与该源漏极电连接；本发明通过将栅极和源漏极同层设置，将数据线与第一金属层同层设置，利用第一金属层进行数据线的排布走线，减少了膜层厚度的同时，栅极和源漏极用一道光罩制程形成，减少了制程数量和光罩数量，提高了生产效率，提高了显示开口率，改善了显示效果。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种显示面板，其中，包括：
    衬底；
    第一金属层，位于所述衬底的一侧；
    第二金属层，位于所述第一金属层远离所述衬底一侧，所述第二金属层包括同层设置的多个栅极和多组源漏极；
    其中，所述显示面板还包括多条数据线，任一所述数据线与所述第一金属层同层设置，所述数据线与所述源漏极电连接。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板还包括位于所述第二金属层与所述第一金属层之间的有源层；
    其中，任一所述数据线在所述衬底上的正投影位于所述有源层在所述衬底上的正投影之外。
  3. 根据权利要求2所述的显示面板，其中，所述显示面板还包括位于所述有源层和所述第一金属层之间的缓冲层、及位于所述有源层和所述第二金属层之间的层间绝缘层；
    所述层间绝缘层包括多个第一过孔、及多个第二过孔，所述缓冲层包括多个第三过孔，所述源漏极包括相对设置的源极和漏极，所述第一过孔与所述第三过孔贯通设置，所述源极通过所述第一过孔和所述第三过孔与所述数据线电连接，所述源极通过所述第二过孔与所述有源层电连接；
    其中，同一所述源极对应的所述第一过孔和所述第二过孔的连线的方向，与所述数据线的延伸方向平行。
  4. 根据权利要求3所述的显示面板，其中，所述数据线包括连接设置的第一段和第二段，所述第一段和所述第二段平行设置；
    其中，所述有源层在所述第一金属层上的正投影位于所述第一段的延长线之上，所述有源层在所述第一金属层上的正投影位于所述第二段的延长线之外，所述源极与对应所述第一段电连接。
  5. 根据权利要求3所述的显示面板，其中，所述层间绝缘层还包括多个第四过孔，所述漏极通过所述第四过孔与所述有源层电连接；
    所述显示面板还包括位于所述第二金属层远离所述衬底一侧的像素电极层、及位于所述像素电极层与所述第二金属层之间的平坦层；
    其中，所述平坦层包括多个第五过孔，所述像素电极层通过所述第五过孔与所述漏极电连接。
  6. 根据权利要求5所述的显示面板，其中，所述有源层包括沟道区、重掺杂区、位于所述沟道区和所述重掺杂区之间的轻掺杂区；
    其中，所述栅极与所述沟道区对应，所述源极通过所述第二过孔与所述重掺杂区对应连接，所述漏极通过所述第四过孔与所述重掺杂区对应连接。
  7. 根据权利要求5所述的显示面板，其中，所述第五过孔在所述衬底上的正投影位于所述漏极在所述衬底上的正投影之内，所述第五过孔在所述衬底上的正投影位于所述有源层在所述衬底上的正投影之外。
  8. 根据权利要求2所述的显示面板，其中，所述第一金属层包括与任一所述数据线间隔且同层设置的多个遮光单元；
    其中，所述有源层在所述第一金属层上的正投影位于对应所述遮光单元之内。
  9. 根据权利要求1所述的显示面板，其中，所述第二金属层还包括沿第一方向排布的多条扫描线；
    其中，任一所述数据线沿第二方向排布，所述第一方向与所述第二方向垂直。
  10. 根据权利要求1所述的显示面板，其中，所述第一金属层还包括反光单元，所述反光单元位于相邻两个所述数据线之间且与任一所述数据线间隔设置。
  11. 一种显示装置，其中，包括显示面板及装置主体，所述装置主体与所述显示面板组合为一体；其中，所述显示面板包括：
    衬底；
    第一金属层，位于所述衬底的一侧；
    第二金属层，位于所述第一金属层远离所述衬底一侧，所述第二金属层包括同层设置的多个栅极和多组源漏极；
    其中，所述显示面板还包括多条数据线，任一所述数据线与所述第一金属层同层设置，所述数据线与所述源漏极电连接。
  12. 根据权利要求11所述的显示装置，其中，所述显示面板还包括位于所述第二金属层与所述第一金属层之间的有源层；
    其中，任一所述数据线在所述衬底上的正投影位于所述有源层在所述衬底上的正投影之外。
  13. 根据权利要求12所述的显示装置，其中，所述显示面板还包括位于所述有源层和所述第一金属层之间的缓冲层、及位于所述有源层和所述第二金属层之间的层间绝缘层；
    所述层间绝缘层包括多个第一过孔、及多个第二过孔，所述缓冲层包括多个第三过孔，所述源漏极包括相对设置的源极和漏极，所述第一过孔与所述第三过孔贯通设置，所述源极通过所述第一过孔和所述第三过孔与所述数据线电连接，所述源极通过所述第二过孔与所述有源层电连接；
    其中，同一所述源极对应的所述第一过孔和所述第二过孔的连线的方向，与所述数据线的延伸方向平行。
  14. 根据权利要求13所述的显示装置，其中，所述数据线包括连接设置的第一段和第二段，所述第一段和所述第二段平行设置；
    其中，所述有源层在所述第一金属层上的正投影位于所述第一段的延长线之上，所述有源层在所述第一金属层上的正投影位于所述第二段的延长线之外，所述源极与对应所述第一段电连接。
  15. 根据权利要求13所述的显示装置，其中，所述层间绝缘层还包括多个第四过孔，所述漏极通过所述第四过孔与所述有源层电连接；
    所述显示面板还包括位于所述第二金属层远离所述衬底一侧的像素电极层、及位于所述像素电极层与所述第二金属层之间的平坦层；
    其中，所述平坦层包括多个第五过孔，所述像素电极层通过所述第五过孔与所述漏极电连接。
  16. 根据权利要求15所述的显示装置，其中，所述有源层包括沟道区、重掺杂区、位于所述沟道区和所述重掺杂区之间的轻掺杂区；
    其中，所述栅极与所述沟道区对应，所述源极通过所述第二过孔与所述重掺杂区对应连接，所述漏极通过所述第四过孔与所述重掺杂区对应连接。
  17. 根据权利要求15所述的显示装置，其中，所述第五过孔在所述衬底上的正投影位于所述漏极在所述衬底上的正投影之内，所述第五过孔在所述衬底上的正投影位于所述有源层在所述衬底上的正投影之外。
  18. 根据权利要求12所述的显示装置，其中，所述第一金属层包括与任一所述数据线间隔且同层设置的多个遮光单元；
    其中，所述有源层在所述第一金属层上的正投影位于对应所述遮光单元之内。
  19. 根据权利要求11所述的显示装置，其中，所述第二金属层还包括沿第一方向排布的多条扫描线；
    其中，任一所述数据线沿第二方向排布，所述第一方向与所述第二方向垂直。
  20. 根据权利要求11所述的显示装置，其中，所述第一金属层还包括反光单元，所述反光单元位于相邻两个所述数据线之间且与任一所述数据线间隔设置。
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