WO2022037287A9 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2022037287A9
WO2022037287A9 PCT/CN2021/104546 CN2021104546W WO2022037287A9 WO 2022037287 A9 WO2022037287 A9 WO 2022037287A9 CN 2021104546 W CN2021104546 W CN 2021104546W WO 2022037287 A9 WO2022037287 A9 WO 2022037287A9
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WIPO (PCT)
Prior art keywords
fan
data signal
display
width
area
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PCT/CN2021/104546
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English (en)
French (fr)
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WO2022037287A1 (zh
Inventor
张波
吴正刚
王蓉
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/771,502 priority Critical patent/US20220406875A1/en
Publication of WO2022037287A1 publication Critical patent/WO2022037287A1/zh
Publication of WO2022037287A9 publication Critical patent/WO2022037287A9/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/60—Organic compounds having low molecular weight
    • H10K85/631—Amine compounds having at least two aryl rest on at least one amine-nitrogen atom, e.g. triphenylamine
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K30/00—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation
    • H10K30/80—Constructional details
    • H10K30/81—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/40—Organosilicon compounds, e.g. TIPS pentacene

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular, relate to a display substrate and a display device.
  • the display substrate includes a display area and a non-display area.
  • the non-display area is provided with a driving circuit to output signals, and the display area is provided with a display structure layer to display images.
  • Conductors for transmitting corresponding signals to the display area are also arranged in the non-display area.
  • the wires located in the non-display area are designed to be concentrated to the driving circuit in the non-display area, so that the wires are assembled into a structure similar to a fan, and this area is commonly referred to as a fan-out area.
  • This area is commonly referred to as a fan-out area.
  • the present disclosure provides a display substrate comprising: a display area and a non-display area surrounding the display area, the non-display area includes a fan-out area and a bending area, and the bending area is located in the fan The exit area is away from the side of the display area;
  • a plurality of first data signal lines located in the display area and electrically connected to the plurality of sub-pixels, configured to provide data signals to the plurality of sub-pixels;
  • a plurality of fan-out wirings located in the fan-out area and arranged in sequence along the first direction, the plurality of fan-out wirings are electrically connected with the plurality of first data signal lines;
  • a plurality of second data signal lines located in the bending region and arranged in sequence along the first direction, the plurality of second data signal lines are electrically connected to the plurality of fan-out traces;
  • a plurality of patch cords are located in the fan-out area and between the multiple fan-out traces and the multiple second data signal lines, and the multiple patch cables are electrically connected to the multiple fan-out traces and all the the plurality of second data signal lines;
  • the ratio of the width of at least a part of the patch cords among the multiple patch cables to the width of the multiple fan-out traces is 0.5 to 5.5.
  • At least one of the multiple fan-out routings includes:
  • connection part a first connection part, a second connection part and a third connection part arranged along the second direction, the second connection part is located between the first connection part and the third connection part and connects the first connection part A connection part and a third connection part, the included angle between the first connection part and the second connection part is greater than 90 degrees and less than or equal to 180 degrees, the second connection part and the third connection part The included angle between them is greater than 90 degrees and less than or equal to 180 degrees;
  • the ratio of the width of the third connection portion to the width of the at least part of the patch cord is 1 to 2; the first direction intersects the second direction.
  • the ratio of the width of the at least part of the patch cord to the width of the at least part of the second connection part is 2 to 5.5.
  • the width of the at least part of the patch cord is equal to the width of the third connection portion.
  • the shape of the display area is a polygon with rounded corners
  • the display area is divided into a straight edge area and a corner area
  • the boundary of the display area in the corner area is an arc shape, close to the corner
  • the ratio of the width of the first connection portion to the width of the second connection portion of the fan-out trace of the region is 2 to 5.5.
  • the ratio of the width of the first connection portion of the fan-out trace close to the corner area to the width of the first data signal line is 2 to 3.
  • the i-th fan-out trace and the i+1-th fan-out trace are set in different layers, 1 ⁇ i ⁇ N, where N is the number of fan-out traces;
  • the patch cord is arranged on the same layer as the fan-out wiring connected to the patch cord.
  • the odd-numbered fan-out lines are set on the same layer, and the even-numbered fan-out lines are set on the same layer.
  • the display substrate further includes: a plurality of first connection electrodes located in the display area, the plurality of first connection electrodes are respectively connected with the plurality of first data signal lines and the A plurality of the fan-out traces are connected;
  • the first connection electrodes and the fan-out wirings connected to the first connection electrodes are arranged in the same layer, and the first data signal lines connected to the first connection electrodes are arranged in different layers.
  • the display substrate further includes: a plurality of second connection electrodes located in the bending region, the plurality of second connection electrodes are respectively connected to the plurality of transition lines and the plurality of The second data signal line is electrically connected;
  • the second connection electrode is arranged in the same layer as the patch wire connected with the second connection electrode, and the second data signal line connected with the second connection electrode is arranged in a different layer;
  • the ratio of the width of the second connection electrode to the width of the patch wire connected to the second connection electrode is 0.8 to 1; the width of the second data signal line is connected to the second connection of the second data signal line.
  • the ratio of the widths of the electrodes is 1 to 1.2.
  • the display substrate further includes: a base substrate on which the plurality of sub-pixels are disposed, and at least one of the plurality of sub-pixels includes a driving thin film transistor and a storage capacitor;
  • the driving thin film transistor includes a driving active layer on the base substrate, a first insulating layer on a side of the driving active layer away from the base substrate, and a first insulating layer on the side away from the base substrate.
  • the storage capacitor includes a first pole plate and a second pole plate; the first pole plate and the drive gate are arranged in the same layer, and the second pole plate is located in the second insulating layer and the third insulating layer. Between the layers, the orthographic projection of the first electrode plate on the base substrate at least partially overlaps the orthographic projection of the second electrode plate on the base substrate.
  • the odd-numbered fan-out wirings are arranged on the same layer as the first pole plate, and the even-numbered fan-out wirings are arranged on the same layer as the second pole plate;
  • the odd-numbered fan-out wiring is arranged on the same layer as the second pole plate, and the even-numbered fan-out wiring is arranged on the same layer as the first pole plate;
  • the first data signal line and the second data signal line are disposed on the same layer as the driving source.
  • a plurality of second data signal lines are provided with a plurality of through holes
  • the plurality of passages are circular holes or elliptical holes.
  • the display substrate further includes: a driving chip and a plurality of third data signal lines located on a side of the bending region away from the fan-out region;
  • the driving chip is electrically connected to the plurality of second data signal lines through the plurality of third data signal lines.
  • the present disclosure also provides a display device, comprising: the above-mentioned display substrate.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a fan-out routing provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of the F1 region in the display substrate provided by an exemplary embodiment
  • FIG. 4 is a schematic structural diagram of the F1 region in the display substrate provided by another exemplary embodiment
  • FIG. 5 is a schematic structural diagram of the F2 region in the display substrate provided by an exemplary embodiment
  • FIG. 6 is a schematic structural diagram of the F2 region in the display substrate provided by another exemplary embodiment
  • FIG. 7 is a cross-sectional view of a part of a display area of a display substrate provided by an exemplary embodiment
  • FIG. 8 is a schematic diagram of forming an active layer
  • FIG. 9 is a schematic diagram of forming a first metal layer
  • FIG. 10 is a schematic diagram of forming a second metal layer
  • FIG. 11 is a schematic diagram of forming a third metal layer
  • FIG. 12 is a schematic diagram of forming a fourth metal layer.
  • the wires of the fan-out area include wires that provide data signals to the data signal wires of the display area.
  • the wires that provide data signals to the data signal lines of the display area are arranged sparsely in the vertical direction, and the wirings in the horizontal direction are denser.
  • the wires in the fan-out area that provide data signals to the data signal lines in the display area are easily broken, resulting in abnormal display and reducing the product yield of the display product.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate provided by the embodiment of the present disclosure includes: a display area AA and a non-display area surrounding the display area AA.
  • the non-display area includes: a fan-out area F and a bending area BB, and the bending area BB is located in the fan-out area F and the bending area BB.
  • the exit area F is on the side away from the display area AA.
  • the display substrate includes: a plurality of sub-pixels 11 , a plurality of first data signal lines 12 , a plurality of fan-out traces 20 , a plurality of second data signal lines 30 and a plurality of transition lines 40 .
  • a plurality of sub-pixels 11 are located in the display area AA.
  • the plurality of first data signal lines 12 are located in the display area AA and are electrically connected to the plurality of sub-pixels 11 , and are configured to provide data signals to the plurality of sub-pixels 11 .
  • the plurality of fan-out traces 20 are located in the fan-out area F and are arranged in sequence along the first direction.
  • the plurality of fan-out traces 20 are electrically connected to the plurality of first data signal lines 12 .
  • the plurality of second data signal lines 30 are located in the bending region BB and arranged in sequence along the first direction.
  • the plurality of second data signal lines 30 are electrically connected to the plurality of fan-out traces 20 .
  • a plurality of patch cords 40 are located in the fan-out area F and between the multiple fan-out traces 20 and the multiple second data signal lines 30, and the multiple patch cables 40 are electrically connected to the multiple fan-out traces 20 and the multiple second data signal wires Signal line 30.
  • the ratio of the width of at least a portion of the patch cords to the width of the plurality of fan-out traces is 0.5 to 5.5.
  • the display area may include scan signal lines, light emission control lines, and reset signal lines.
  • the plurality of sub-pixels are defined by the intersection of the scan signal line and the first data signal line.
  • Each sub-pixel includes a plurality of transistors, and the plurality of transistors can constitute a pixel circuit, and the pixel circuit is electrically connected to the scan signal line, the first data signal line, the light emission control line and the reset signal line.
  • the transistors used in the pixel circuit may all be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • the display substrate may be a liquid crystal display substrate, or may be an organic light-emitting diode (Organic Light-Emitting Diode, OLED for short) display substrate.
  • OLED Organic Light-Emitting Diode
  • the liquid crystal display substrate may be an array substrate, or may be an array substrate of a Color Filter on Array (COA for short) type.
  • COA Color Filter on Array
  • the display substrate when the display substrate is an OLED display substrate, the display substrate may further include: a light emitting element.
  • the light-emitting element may include: a first electrode, a second electrode and an organic light-emitting layer. The first electrode and the second electrode are respectively located on both sides of the organic light emitting layer.
  • the display device when the display substrate is a liquid crystal display substrate, the display device may further include: a cell-to-cell substrate arranged in a cell-to-cell manner with the display substrate.
  • the cell assembling substrate may be a color filter substrate.
  • the cell assembly substrate can be a glass cover plate.
  • the display area in the display substrate may be a polygon with rounded corners, which is not limited in this embodiment of the present disclosure.
  • FIG. 1 illustrates an example in which the display area in the display substrate is a quadrilateral with rounded corners.
  • the fan-shaped routing may be a straight line or a zigzag line.
  • the linear type is located in the middle area of the fan-shaped area, and the number of the linear type of fan-shaped wiring is at least one, which is determined according to the wiring mode of the fan-shaped area of the display substrate.
  • the fold-line fan-shaped traces are located on both sides of the middle area of the fan-shaped area.
  • At least some of the patch lines may have a width of 4 to 8 microns.
  • the display substrate includes: a display area and a non-display area surrounding the display area, the non-display area includes a fan-out area and a bending area, and the bending area is located on a side of the fan-out area away from the display area; a plurality of sub-pixels , located in the display area; a plurality of first data signal lines, located in the display area and electrically connected to a plurality of sub-pixels, are configured to provide data signals to the plurality of sub-pixels; a plurality of fan-out traces, located in the fan-out area and along the first direction Arranged in sequence, a plurality of fan-out wirings are electrically connected with a plurality of first data signal lines; a plurality of second data signal lines are located in the bending area and are arranged in sequence along the first direction, and a plurality of second data signal lines are connected with a plurality of fan The outgoing wires are electrically connected; a plurality of transfer wires
  • the reliability of the fan-out traces can be improved, and the easy-breakage of the fan-out traces during the manufacturing process can be avoided.
  • Technical problems have improved the yield of display products.
  • the display substrate may further include: a driving chip 50 and a plurality of third data signal lines 51 .
  • the driving chip 50 is electrically connected to the plurality of second data signal lines 30 through the plurality of third data signal lines 51 .
  • the driving chip includes a first driving chip that provides signals to the scan signal lines, the light emission control lines and the reset signal lines, and a second driving chip that provides signals to the third data signal lines.
  • the scan signal line, the reset signal line and the light emitting control line are arranged in the same layer.
  • FIG. 2 is a schematic structural diagram of a fan-out routing provided by an exemplary embodiment.
  • at least one fan-out trace 20 among the plurality of fan-out traces includes: a first connection part 20A, a second connection part 20B and a third connection part 20C arranged along the second direction.
  • the second connection portion 20B is located between the first connection portion 20A and the third connection portion 20C, and connects the first connection portion 20A and the third connection portion 20C.
  • the included angle between the first connecting portion 20A and the second connecting portion 20B is greater than 90 degrees and less than or equal to 180 degrees.
  • the included angle between the second connecting portion 20B and the third connecting portion 20C is greater than 90 degrees and less than or equal to 180 degrees.
  • the first connection portion 20A is electrically connected to the first data signal line and the second connection portion 20B, respectively, and the third connection portion 20C is electrically connected to the second connection portion 20B and the patch cord 40 , respectively.
  • the ratio of the width W3 of the third connection portion to the width of at least part of the patch cord is 1 to 2.
  • the first direction intersects the second direction.
  • the intersection of the first direction and the second direction means that the included angle between the first direction and the second direction may be about 70 degrees to 90 degrees.
  • the included angle between the first direction and the second direction may be 90 degrees, that is, the first direction may be perpendicular to the second direction.
  • first connection portion 20A and the third connection portion 20C extend in the second direction.
  • the width W1 of the first connection portion 20A may be about 4 to 6 microns.
  • the width W2 of the second connection part 20B may be about 1.5 to 2 microns.
  • the width W3 of the third connection portion 20C may be greater than or equal to 8 micrometers.
  • the width W3 of the third connection part 20C is greater than or equal to the width W2 of the second connection part 20B, which can improve the reliability of the fan-out trace and avoid the fan-out trace in the
  • the technical problem of easy breakage during the manufacturing process can improve the display effect of the display product and improve the yield of the display product.
  • the width of at least part of the patch cord may be equal to the width of the third connection portion.
  • the width of at least part of the patch cord is greater than half of the width W3 of the third connection portion, which increases The width of some of the adapter lines improves the yield of display products.
  • the width of at least part of the patch cord is equal to the width of the third connection portion.
  • the ratio of the width of at least part of the patch cord to the width of at least part of the second connection portion W2 is 2 to 5.5.
  • the shape of the display area is a rounded polygon
  • the display area is divided into a straight edge area and a corner area
  • the boundary of the display area in the corner area is an arc shape
  • the first part of the fan-out trace near the corner area is in the shape of an arc.
  • the ratio of the width of the first connecting portion to the width of the second connecting portion is 2 to 5.5.
  • the ratio of the width of the first connection portion of the fan-out trace near the corner region to the width of the first data signal line is 2 to 3.
  • the i-th fan-out trace and the i+1-th fan-out trace are arranged in different layers, 1 ⁇ i ⁇ N.
  • the patch cords are arranged on the same layer as the fan-out traces connected to the patch cords.
  • the odd-numbered fan-out wires are arranged on the same layer, and the even-numbered fan-out wires are arranged on the same layer.
  • FIG. 3 is a structural layout of the F1 region in the display substrate provided by an exemplary embodiment.
  • the display substrate may further include: a plurality of first data signal lines 12 located in the display area AA.
  • the plurality of first data signal lines 12 are in one-to-one correspondence with the fan-out traces 20 .
  • the first data signal lines 12 are electrically connected to the corresponding fan-out traces 20 , and are disposed at different layers from the connected fan-out traces 20 .
  • FIG. 4 is a structural layout of the F1 region in the display substrate provided by another exemplary embodiment.
  • the display substrate further includes: a plurality of first connection electrodes 60 located in the display area AA, and the plurality of first connection electrodes 60 are respectively connected with the plurality of first data signal lines 12 and the plurality of fan-out traces 20 electrical connection.
  • the first connection electrodes 60 and the fan-out traces 20 connected to the first connection electrodes 60 are arranged at the same layer, and the first data signal lines connected to the first connection electrodes 60 are arranged at different layers.
  • FIG. 5 is a structural layout of the F2 region in the display substrate provided by an exemplary embodiment.
  • the display substrate provided by an exemplary embodiment further includes: a second data signal line 30 located in the bending region BB.
  • the plurality of second data signal lines 30 are electrically connected to the patch cords 40 .
  • the second data signal lines 30 and the transition lines 40 are disposed in different layers, and are disposed in the same layer as the first data signal lines.
  • FIG. 6 is a structural layout of the F2 region in the display substrate provided by another exemplary embodiment.
  • a display substrate provided by an exemplary embodiment further includes: a plurality of second connection electrodes 70 located in the bending region, and the plurality of second connection electrodes 70 are respectively connected with the plurality of transition wires 40 and the plurality of first connection electrodes 70 .
  • the two data signal lines 30 are connected.
  • the second connection electrodes 70 are arranged in the same layer as the transition lines 40 connected to the second connection electrodes 70 , and the second data signal lines 30 connected to the second connection electrodes 70 are arranged in different layers.
  • the ratio of the width of the second connection electrode 70 to the width of the patch wire 40 to which the second connection electrode 70 is connected is 0.8 to 1.
  • the ratio of the width of the second data signal line 30 to the width of the second connection electrode 70 to which the second data signal line 30 is connected is 1 to 1.2.
  • the display substrate may further include: traces 80 for transmitting signals to the scanning signal line Gate, the reset signal line and the light-emitting control line in the display area.
  • the display substrate may further include: a power line VDD continuously providing a high-level signal.
  • FIG. 7 is a cross-sectional view of a part of a display area of a display substrate provided by an exemplary embodiment.
  • the display substrate further includes: a base substrate 10 .
  • a plurality of sub-pixels 11 are disposed on the base substrate 10, and at least one of the plurality of sub-pixels includes a driving thin film transistor and a storage capacitor.
  • FIG. 7 illustrates an example in which the display substrate is an OLED display substrate.
  • the driving thin film transistor includes a driving active layer 111 located on the base substrate 10 , a first insulating layer 115 located on the side of the driving active layer 111 away from the base substrate 10 , and a first insulating layer 115 located on the side away from the base substrate 10 .
  • the driving gate 112, the second insulating layer 116 on the side of the driving gate 112 away from the base substrate 10, the third insulating layer 117 on the side of the second insulating layer 116 away from the base substrate 10, and the third insulating layer 117 is the driving source electrode 113 and the driving drain electrode 114 on the side away from the base substrate 10 .
  • the storage capacitor includes a first plate C1 and a second plate C2.
  • the first plate C1 and the driving gate 112 are disposed in the same layer.
  • the second electrode plate C2 is located between the second insulating layer 116 and the third insulating layer 117 .
  • the orthographic projection of the first electrode plate C1 on the base substrate 10 and the orthographic projection of the second electrode plate C2 on the base substrate 10 at least partially overlap.
  • the display substrate may further include: a fourth insulating layer 118 , a flat layer 119 , a first electrode 120 , a pixel definition layer 121 , and spacers, which are disposed on the third insulating layer and are stacked in sequence.
  • the base substrate may be a rigid base substrate or a flexible base substrate, wherein the rigid base substrate may be, but is not limited to, one or more of glass and metal foil; a flexible substrate
  • the base substrate can be, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, poly One or more of imide, polyvinyl chloride, polyethylene, and textile fibers.
  • the driving active layer may employ a semiconductor material, eg, polysilicon (eg, low temperature polysilicon or high temperature polysilicon), amorphous silicon, or indium gallium tin oxide (IGZO).
  • a semiconductor material eg, polysilicon (eg, low temperature polysilicon or high temperature polysilicon), amorphous silicon, or indium gallium tin oxide (IGZO).
  • the driving gate, the driving source and the driving drain may adopt a metal material, such as metal aluminum or aluminum alloy.
  • the driving source and the driving drain of the transistor used here may be symmetrical in structure, so the driving source and the driving drain may be indistinguishable in structure.
  • the first electrode may be indium tin oxide or zinc tin oxide.
  • the pixel definition layer may employ polyimide, acrylic, or polyethylene terephthalate.
  • the second electrode may employ any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or may Alloys made with any one or more of the above metals.
  • the display substrate may further include: a polarizer.
  • the odd-numbered fan-out wires are arranged on the same layer as the first electrode plate, and the even-numbered fan-out wires are arranged on the same layer as the second electrode plate.
  • the odd-numbered fan-out wires are arranged on the same layer as the second electrode plate, and the even-numbered fan-out wires are arranged on the same layer as the first electrode plate.
  • the orthographic projection of the i-th fan-out trace on the base substrate there is no overlapping area between the orthographic projection of the i-th fan-out trace on the base substrate and the orthographic projection of the i+1-th fan-out trace on the base substrate, which can avoid inconsistencies.
  • the crosstalk of signals between adjacent fan-out traces improves the display effect of the display substrate.
  • the first data signal line and the second data signal line are disposed on the same layer as the driving source.
  • the plurality of second data signal lines 30 are provided with a plurality of through holes.
  • the shape of the plurality of through holes may be circular holes, or may be oval holes.
  • the first insulating layer, the second insulating layer and the third insulating layer are provided with a first via V1 exposing the driving active layer.
  • the second insulating layer and the third insulating layer are provided with a second via hole V2 exposing the first connection electrode connected to the Pth fan-out trace and a second via hole V2 exposing the second connection electrode connected to the Pth fan-out trace Three vias V3.
  • the driving source and the driving drain are connected to the driving active layer 111 through the first via hole.
  • the first data signal line connected to the P-th fan-out line is connected to the first connection electrode 60 connected to the P-th fan-out line through the second via hole V2.
  • the second data signal line connected to the P-th fan-out line is connected to the second connection electrode connected to the P-th fan-out line through the third via hole V3.
  • the number of the second via holes V2 is at least one.
  • the plurality of second via holes are arranged along the first direction.
  • FIG. 4 takes two second via holes V2 as an example for description.
  • the number of the third via holes V3 is at least one.
  • the plural third via holes are arranged along the second direction.
  • FIG. 6 takes seven third via holes V3 as an example for description.
  • the third insulating layer is provided with a fourth via V4 exposing the first connection electrode connected to the Qth fan-out trace and exposing the first connection electrode connected to the Qth fan-out trace.
  • the Q fan-out traces are connected to the fifth via hole V5 of the second connection electrode.
  • the first data signal line connected to the Qth fan-out line is connected to the first connection electrode connected to the Qth fan-out line through the fourth via hole.
  • the second data signal line connected to the Qth fanout line is connected to the second connection electrode connected to the Qth fanout line through the fifth via hole.
  • the number of the fourth via hole V4 is at least one.
  • the plurality of fourth via holes are arranged along the first direction.
  • FIG. 4 takes two fourth via holes V4 as an example for description.
  • the number of the fifth via holes V5 is at least one.
  • the plurality of fifth via holes are arranged along the second direction.
  • FIG. 6 takes the seven fifth via holes V4 as an example for description.
  • P is an odd number less than or equal to N
  • Q is an even number less than or equal to N
  • P is an even number less than or equal to N
  • Q is an even number less than or equal to N.
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may adopt silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON) Any one or more of these can be single layer, multi-layer or composite layer.
  • the first insulating layer is called the first gate insulating layer
  • the second insulating layer is called the second gate insulating layer
  • the third insulating layer is called the interlayer insulating layer
  • the fourth insulating layer is called the passivation layer.
  • the following describes the structure of the display substrate provided by an exemplary embodiment through the preparation process of the display substrate with reference to FIGS. 4 , 8 to 12 .
  • the "patterning process” includes deposition of film layers, photoresist coating, mask exposure, development, etching and photoresist stripping processes. Deposition can use any one or more of sputtering, evaporation and chemical vapor deposition, coating can use any one or more of spray coating and spin coating, and etching can use any one or more of dry etching and wet etching. one or more. "Film” refers to a layer of thin film made by depositing or coating a certain material on a substrate.
  • the “film” may also be referred to as a "layer”.
  • the “film” needs a patterning process in the whole production process, it is called a “film” before the patterning process, and a “layer” after the patterning process.
  • “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process.
  • Forming an active layer on a base substrate includes: depositing a semiconductor thin film on the base substrate, and patterning the semiconductor thin film through a patterning process to form a driving active layer 111 , as shown in FIG. 8 .
  • Forming the first metal layer includes: depositing a first insulating film on the base substrate on which the active layer is formed, and patterning the first insulating film through a patterning process to form the first insulating layer.
  • a first metal film is deposited on the first insulating layer, and the first metal film is patterned through a patterning process to form a first metal layer.
  • the first metal layer includes: a scanning signal line Gate, a light-emitting control line, a reset signal line, a driving gate 112, a first plate and a Pth fanout line 20 located in the fanout region and a Pth fanout line located in the display area.
  • the first connection electrode 60 located in the display area and the second connection electrode (not shown in the figure) located in the bending area are connected by the wires, as shown in FIG. 9 .
  • this process further includes a conductorization process.
  • the conductorization treatment is that after the first metal layer is formed, the driving active layer is subjected to plasma treatment by using the driving gate as a shield, and the driving active layer in the region shielded by the driving gate is used as the channel region, which is not covered by the first metal layer.
  • the driving active layer of the shielding region is processed into a conductive layer to form a conductive source-drain region.
  • Forming the second metal layer includes: depositing a second insulating film on the base substrate on which the first metal layer is formed, and patterning the second insulating film through a patterning process to form a second insulating layer.
  • a second metal thin film is deposited on the base substrate on which the second insulating layer is formed, and the second metal thin film is patterned through a patterning process to form a second metal layer.
  • the second metal layer includes: a second electrode plate, the Qth fan-out trace in the fan-out area, a first connection electrode in the display area connected to the Qth fan-out trace, and a second connection electrode in the bending area , as shown in Figure 10.
  • Forming the third insulating layer includes: depositing a third insulating film on the base substrate on which the second metal layer is formed, and patterning the third insulating film through a patterning process to form the third insulating layer.
  • the third insulating layer is formed with a plurality of via holes.
  • the plurality of via holes include: a first via hole V1 penetrating the first insulating layer, the second insulating layer and the third insulating layer, a second via hole V2 and a third via hole V3 penetrating the second insulating layer and the third insulating layer and the fifth via hole and the sixth via hole only penetrating the third insulating layer, as shown in FIG. 4 .
  • the first via hole exposes the driving active layer
  • the second via hole exposes the first connection electrode connected to the Pth fan-out trace
  • the third via hole of the second connection electrode, the fourth via hole exposes the first connection electrode connected with the Qth fanout trace
  • the fifth via hole exposes the second connection electrode connected with the Qth fanout trace .
  • Forming the third metal layer includes: depositing a third metal thin film on the base substrate on which the third insulating layer is formed, and patterning the third metal thin film through a patterning process to form the third metal layer.
  • the third metal layer includes: a plurality of driving source electrodes 113 and driving drain electrodes 114 located in the display area AA, a first data signal line 12 located in the display area AA, and a second data signal line located in the bending area (not shown in the figure). out) and the first power supply line VDD, as shown in FIG. 11 .
  • the driving source 113 and the driving drain 114 are connected to the driving active layer through the first via hole; the first data signal line connected to the Pth fanout line is connected to the Pth fanout line through the second via hole.
  • the first connection electrode is connected; the second data signal line connected with the Pth fan-out line is connected with the second connection electrode connected with the Pth fan-out line through the third via hole.
  • the first data signal line connected to the Qth fan-out line is connected to the first connection electrode connected to the Qth fan-out line through the fourth via hole; the second data signal line connected to the Qth fan-out line passes through
  • the fifth via hole is connected to the second connection electrode connected to the Qth fan-out trace.
  • Forming the fourth metal layer includes: depositing a fourth insulating film on the base substrate on which the third metal layer is formed, and patterning the fourth insulating film through a patterning process to form a fourth insulating layer.
  • a fourth metal thin film is deposited on the base substrate on which the fourth insulating layer is formed, and the fourth metal thin film is patterned through a patterning process to form a fourth metal layer.
  • the fourth metal layer includes: traces 80 for transmitting signals to the scanning signal line Gate, the reset signal line and the light-emitting control line in the display area, as shown in FIG. 12 .
  • Forming the flat layer includes: coating a flat film on the base substrate on which the fourth metal layer is formed, and forming the flat layer by masking, exposing and developing the flat film.
  • Forming the light emitting structure layer and the encapsulation layer includes: depositing a transparent conductive film on the base substrate formed with the flat layer, and patterning the transparent conductive film through a patterning process to form a first electrode.
  • a pixel definition film and a spacer film are coated on the base substrate on which the first electrode is formed, and a pixel definition layer and a spacer layer are formed by masking, exposing and developing the pixel definition film and the spacer film.
  • An organic thin film is coated on the substrate formed with the spacers, an organic light-emitting layer is formed by masking, exposing and developing the organic thin film, a metal thin film is deposited on the substrate formed with the organic light-emitting layer, and a patterning process is performed.
  • the metal thin film is patterned to form a second electrode.
  • a first encapsulation film is deposited on the base substrate on which the second electrode is formed, and the first encapsulation film is patterned through a patterning process to form a first encapsulation layer.
  • a second encapsulation film is coated on the base substrate on which the first encapsulation layer is formed, and the second encapsulation layer is formed by masking, exposing and developing the second encapsulation film.
  • a third encapsulation film is coated on the base substrate on which the second encapsulation layer is formed, and the third encapsulation layer is formed by masking, exposing and developing the third encapsulation film.
  • Embodiments of the present disclosure also provide a display device, including: a display substrate.
  • the display device may be a display, a TV, a mobile phone, a tablet computer, a navigator, a digital photo frame, a wearable display product, or a product or component with any display function.
  • the display device when the display substrate is an array substrate, the display device may further include a backlight module for providing backlight.
  • the display substrate is the display substrate provided in any one of the foregoing embodiments, and the implementation principle and effect are similar, and details are not described herein again.

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Abstract

一种显示基板和显示装置，显示基板包括：显示区和非显示区，非显示区包括扇出区和弯折区，弯折区位于扇出区远离显示区的一侧；多个子像素；多条第一数据信号线，位于显示区且与多个子像素电连接，被配置为向多个子像素提供数据信号；多条扇出走线，位于扇出区且沿第一方向依次排列，多条扇出走线与多条第一数据信号线电连接；多条第二数据信号线，位于弯折区且沿第一方向依次排列，多条第二数据信号线与多条扇出走线电连接；多条转接线，位于扇出区且位于多条扇出走线和多条第二数据信号线之间，多条转接线电连接多条扇出走线和多条第二数据信号线；多条转接线中的至少部分转接线的宽度与多条扇出走线宽度的比值为0.5至5.5。

Description

显示基板和显示装置
本申请要求于2020年8月18日提交中国专利局、申请号为202010831194.5、发明名称为“显示基板和显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于显示技术领域，特别涉及一种显示基板和显示装置。
背景技术
随着显示技术的发展，显示基板已广泛应用于显示技术领域中，而且也在朝着高分辨率不断发展。显示基板包括显示区和非显示区，非显示区设置有驱动电路，以输出信号，显示区内设置有显示结构层，以显示画面。非显示区内还设置有向显示区传输相应信号的导线。
位于非显示区的导线被设计为向非显示区中的驱动电路集中，从而使得导线汇集成类似于扇形的结构，该区域为通常所称的扇出区。显示基板的屏幕分辨率越高，位于扇出区的导线的数量就越多。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种显示基板包括：显示区和围绕所述显示区的非显示区，所述非显示区包括扇出区和弯折区，所述弯折区位于所述扇出区远离所述显示区的一侧；
多个子像素，位于所述显示区；
多条第一数据信号线，位于所述显示区且与所述多个子像素电连接，被配置为向所述多个子像素提供数据信号；
多条扇出走线，位于所述扇出区且沿第一方向依次排列，所述多条扇出 走线与所述多条第一数据信号线电连接；
多条第二数据信号线，位于所述弯折区且沿第一方向依次排列，所述多条第二数据信号线与所述多条扇出走线电连接；
多条转接线，位于所述扇出区且位于所述多条扇出走线和所述多条第二数据信号线之间，所述多条转接线电连接所述多条扇出走线和所述多条第二数据信号线；
其中，所述多条转接线中的至少部分所述转接线的宽度与所述多条扇出走线宽度的比值为0.5至5.5。
在一些可能的实现方式中，所述多条扇出走线中至少一条包括：
沿第二方向排布的第一连接部、第二连接部和第三连接部，所述第二连接部位于所述第一连接部和所述第三连接部之间且连接所述第一连接部和第三连接部，所述第一连接部与所述第二连接部之间的夹角大于90度，且小于或等于180度，所述第二连接部和所述第三连接部之间的夹角大于90度，且小于或者等于180度；
所述第三连接部的宽度和所述至少部分转接线的宽度比值为1至2；所述第一方向与所述第二方向相交。
在一些可能的实现方式中，所述至少部分转接线的宽度和所述至少部分第二连接部宽度的比值为2至5.5。
在一些可能的实现方式中，所述至少部分转接线的宽度等于所述第三连接部的宽度。
在一些可能的实现方式中，所述显示区的形状为圆角多边形，所述显示区被划分为直边区和拐角区，所述拐角区的显示区的边界为圆弧状，靠近所述拐角区的扇出走线的第一连接部的宽度与第二连接部的宽度的比值为2至5.5。
在一些可能的实现方式中，靠近所述拐角区的扇出走线的第一连接部的宽度与第一数据信号线的宽度的比值为2至3。
在一些可能的实现方式中，第i条扇出走线和第i+1条扇出走线异层设置，1≤i≤N，N为扇出走线的数量；
所述转接线与所述转接线连接的扇出走线同层设置。
在一些可能的实现方式中，第奇数条扇出走线同层设置，第偶数条扇出走线同层设置。
在一些可能的实现方式中，所述显示基板还包括：位于所述显示区的多个第一连接电极，所述多个第一连接电极分别与所述多条第一数据信号线和所述多条所述扇出走线连接；
所述第一连接电极与所述第一连接电极连接的扇出走线同层设置，且与所述第一连接电极连接的第一数据信号线异层设置。
在一些可能的实现方式中，所述显示基板还包括：位于所述弯折区的多个第二连接电极，所述多个第二连接电极分别与所述多条转接线和所述多条第二数据信号线电连接；
所述第二连接电极与所述第二连接电极连接的转接线同层设置，且与所述第二连接电极连接的第二数据信号线异层设置；
所述第二连接电极的宽度与所述第二连接电极连接的转接线的宽度的比值为0.8至1；所述第二数据信号线的宽度与所述第二数据信号线连接的第二连接电极的宽度的比值为1至1.2。
在一些可能的实现方式中，所述显示基板还包括：衬底基板，所述多个子像素设置在所述衬底基板上，所述多个子像素中的至少一个包含驱动薄膜晶体管和存储电容；
所述驱动薄膜晶体管包含位于所述衬底基板上的驱动有源层，位于所述驱动有源层远离所述衬底基板一侧的第一绝缘层、位于所述第一绝缘层远离所述衬底基板一侧的驱动栅极，位于所述驱动栅极远离所述衬底基板一侧的第二绝缘层，位于所述第二绝缘层远离所述衬底基板一侧的第三绝缘层，以及位于所述第三绝缘层远离所述衬底基板一侧的驱动源极和驱动漏极；
所述存储电容包括第一极板和第二极板；所述第一极板与所述驱动栅极同层设置，所述第二极板位于所述第二绝缘层和所述第三绝缘层之间，所述第一极板在所述衬底基板上的正投影与所述第二极板在所述衬底基板上的正投影至少部分重叠。
在一些可能的实现方式中，所述第奇数条扇出走线与所述第一极板同层设置，所述第偶数条扇出走线与所述第二极板同层设置；
或者，所述第奇数条扇出走线与所述第二极板同层设置，所述第偶数条扇出走线与所述第一极板同层设置；
第i条扇出走线在所述衬底基板上的正投影与第i+1条扇出走线在所述衬底基板上的正投影不存在重叠区域。
在一些可能的实现方式中，所述第一数据信号线和所述第二数据信号线与所述驱动源极同层设置。
在一些可能的实现方式中，多条第二数据信号线设置有多个通孔；
所述多个通过为圆孔或者椭圆孔。
在一些可能的实现方式中，所述显示基板还包括：位于所述弯折区远离所述扇出区一侧的驱动芯片和多条第三数据信号线；
所述驱动芯片通过所述多条第三数据信号线与所述多条第二数据信号线电连接。
第二方面，本公开还提供了一种显示装置，包括：上述显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开实施例提供的显示基板的结构示意图；
图2为本公开实施例提供的扇出走线的结构示意图；
图3为一种示例性实施例提供的显示基板中F1区域的结构示意图；
图4为另一示例性实施例提供的显示基板中F1区域的结构示意图；
图5为一种示例性实施例提供的显示基板中F2区域的结构示意图；
图6为另一示例性实施例提供的显示基板中F2区域的结构示意图；
图7为一种示例性实施例提供的显示基板的部分显示区的剖视图；
图8为形成有源层的示意图；
图9为形成第一金属层的示意图；
图10为形成第二金属层的示意图；
图11为形成第三金属层的示意图；
图12为形成第四金属层的示意图。
详述
下文中将结合附图对本公开的实施例进行详细说明。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开描述了多个实施例，但是该描述是示例性的，而不是限制性的，并且对于本领域的普通技术人员来说，在本公开所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在详述中进行了讨论，但是所公开的特征的许多其它组合方式也是可能的。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
本公开包括并设想了与本领域普通技术人员已知的特征和元件的组合。本公开已经公开的实施例、特征和元件也可以与任何常规特征或元件组合，以形成由权利要求限定的技术方案。任何实施例的任何特征或元件也可以与来自其它技术方案的特征或元件组合，以形成另一个由权利要求限定的技术方案。因此，应当理解，在本公开中示出和讨论的任何特征可以单独地或以任何适当的组合来实现。因此，除了根据所附权利要求及其等同替换所做的限制以外，实施例不受其它限制。此外，可以在所附权利要求的保护范围内进行各种修改和改变。
除非另外定义，本公开中使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来 区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述的对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在显示产品中，扇出区的导线包括向显示区的数据信号线提供数据信号的导线。扇出区中向显示区的数据信号线提供数据信号的导线在竖直方向排列较稀疏，水平方向布线较密集。
在一种显示产品中，扇出区中向显示区的数据信号线提供数据信号的导线易断裂，造成显示异常，降低了显示产品的产品良率。
图1为本公开实施例提供的显示基板的结构示意图。如图1所示，本公开实施例提供的显示基板包括：显示区AA和围绕显示区AA的非显示区，非显示区包括：扇出区F和弯折区BB，弯折区BB位于扇出区F远离显示区AA的一侧。显示基板包括：多个子像素11、多条第一数据信号线12、多条扇出走线20、多条第二数据信号线30和多条转接线40。
多个子像素11，位于显示区AA。多条第一数据信号线12，位于显示区AA且与多个子像素11电连接，被配置为向多个子像素11提供数据信号。多条扇出走线20，位于扇出区F且沿第一方向依次排列，多条扇出走线20与多条第一数据信号线12电连接。多条第二数据信号线30，位于弯折区BB且沿第一方向依次排列，多条第二数据信号线30与多条扇出走线20电连接。多条转接线40，位于扇出区F且位于多条扇出走线20和多条第二数据信号线30之间，多条转接线40电连接多条扇出走线20和多条第二数据信号线30。
在一种示例性实施例中，多条转接线中的至少部分转接线的宽度与多条扇出走线宽度的比值为0.5至5.5。
在一种示例性实施例中，显示区可以包括：扫描信号线、发光控制线和复位信号线。其中，多个子像素由扫描信号线和第一数据信号线交叉限定的。每个子像素包括多个晶体管，多个晶体管可以构成像素电路，像素电路与扫 描信号线、第一数据信号线、发光控制线和复位信号线电连接。
在一种示例性实施例中，像素电路中采用的晶体管均可以为薄膜晶体管、场效应晶体管或者其他特性相同的开关器件。
在一种示例性实施例中，显示基板可以为液晶显示基板，或者可以为有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示基板。
在一种示例性实施例中，液晶显示基板可以为阵列基板、或者可以为彩膜设置在阵列基板上(Color Filter on Array，简称COA)型的阵列基板。
在一种示例性实施例中，当显示基板为OLED显示基板时，显示基板还可以包括：发光元件。其中，发光元件可以包括：第一电极、第二电极和有机发光层。第一电极和第二电极分别位于有机发光层的两侧。
在一种示例性实施例中，当显示基板为液晶显示基板时，显示装置还可以包括：与显示基板对盒设置的对盒基板。当显示基板为阵列基板时，对盒基板可以为彩膜基板。当显示基板为COA型的阵列基板时，对盒基板可以为玻璃盖板。
在一种示例性实施例中，显示基板中的显示区可以为圆角多边形，本公开实施例对此不作任何限定。图1是以显示基板中的显示区为圆角四边形为例进行说明的。
在一种示例性实施例中，扇形走线可以为直线型或者折线形。直线型位于扇形区的中间区域，直线型的扇形走线的数量至少为一条，根据显示基板的扇形区的布线方式确定。折线形的扇形走线位于扇形区的中间区域的两侧区域。
在一种示例性实施例中，至少部分转接线的宽度可以为4微米至8微米。
本公开实施例提供的显示基板包括：显示区和围绕显示区的非显示区，非显示区包括扇出区和弯折区，弯折区位于扇出区远离显示区的一侧；多个子像素，位于显示区；多条第一数据信号线，位于显示区且与多个子像素电连接，被配置为向多个子像素提供数据信号；多条扇出走线，位于扇出区且沿第一方向依次排列，多条扇出走线与多条第一数据信号线电连接；多条第二数据信号线，位于弯折区且沿第一方向依次排列，多条第二数据信号线与 多条扇出走线电连接；多条转接线，位于扇出区且位于多条扇出走线和多条第二数据信号线之间，多条转接线电连接多条扇出走线和多条第二数据信号线；多条转接线中的至少部分转接线的宽度与多条扇出走线宽度的比值为0.5至5.5。本公开通过设置多条转接线中的至少部分转接线的宽度与多条扇出走线宽度的比值为0.5至5.5，可以提高扇出走线的可靠性，避免了扇出走线在制程时易断裂的技术问题，提高了显示产品的良品率。
在一种示例性实施例中，如图1所示，显示基板还可以包括：驱动芯片50和多条第三数据信号线51。驱动芯片50通过多条第三数据信号线51与多条第二数据信号线30电连接。
在一种示例性实施例中，驱动芯片包括：向扫描信号线、发光控制线和复位信号线提供信号的第一驱动芯片和向第三数据信号线提供信号的第二驱动芯片。
在一种示例性实施例中，扫描信号线、复位信号线和发光控制线同层设置。
图2为一种示例性实施例提供的扇出走线的结构示意图。如图2所示，多条扇出走线中至少一条扇出走线20包括：沿第二方向排布的第一连接部20A、第二连接部20B和第三连接部20C。第二连接部20B位于第一连接部20A和第三连接部20C之间，且连接第一连接部20A和第三连接部20C。
第一连接部20A与第二连接部20B之间的夹角大于90度，且小于或者等于180度。第二连接部20B与第三连接部20C之间的夹角大于90度，且小于或者等于180度。
第一连接部20A分别与第一数据信号线和第二连接部20B电连接，第三连接部20C分别与第二连接部20B和转接线40电连接。第三连接部的宽度W3和至少部分转接线的宽度比值为1至2。
在一种示例性实施例中，第一方向与第二方向相交。其中，第一方向与第二方向相交指的是第一方向与第二方向之间的夹角可以约为70度至90度。例如，第一方向与第二方向之间的夹角可以为90度，即第一方向可以与第二方向垂直。
在一种示例性实施例中，第一连接部20A和第三连接部20C沿第二方向延伸。
在一种示例性实施例中，第一连接部20A的宽度W1可以约为4微米至6微米。
在一种示例性实施例中，第二连接部20B的宽度W2可以约为1.5微米至2微米。
在一种示例性实施例中，第三连接部20C的宽度W3可以大于或者等于8微米。
在一种示例性实施例中，如图2所示，第三连接部20C的宽度W3大于或者等于第二连接部20B的宽度W2，可以提高扇出走线的可靠性，避免了扇出走线在制程时易断裂的技术问题，可以提升显示产品的显示效果，提高了显示产品的良品率。
在一种示例性实施例中，至少部分转接线的宽度可以等于第三连接部的宽度。
由于第三连接部的宽度和至少部分转接线的宽度比值为1至2，因此，一种示例性实施例中，至少部分转接线的宽度大于第三连接部的宽度W3的一半，增大了部分转接线的宽度，提高了显示产品的良品率。
在一种示例性实施例中，至少部分转接线的宽度等于第三连接部的宽度。
在一种示例性实施例中，至少部分转接线的宽度和至少部分第二连接部W2宽度的比值为2至5.5。
在一种示例性实施例中，显示区的形状为圆角多边形，显示区被划分为直边区和拐角区，拐角区的显示区的边界为圆弧状，靠近拐角区的扇出走线的第一连接部的宽度与第二连接部的宽度的比值为2至5.5。
在一种示例性实施例中，靠近拐角区的扇出走线的第一连接部的宽度与第一数据信号线的宽度的比值为2至3。
在一种示例性实施例中，对于位于扇出区F的N条沿第一方向依次排列的扇出走线20，第i条扇出走线和第i+1条扇出走线异层设置，1≤i≤N。
在一种示例性实施例中，转接线与转接线连接的扇出走线同层设置。
在一种示例性实施例中，第奇数条扇出走线同层设置，第偶数条扇出走线同层设置。
在一种示例性实施例中，图3为一种示例性实施例提供的显示基板中F1区域的结构版图。如图3所示，显示基板还可以包括：位于显示区AA的多条第一数据信号线12。多条第一数据信号线12与扇出走线20一一对应。
第一数据信号线12与对应的扇出走线20电连接，且与连接的扇出走线20异层设置。
在一种示例性实施例中，图4为另一示例性实施例提供的显示基板中F1区域的结构版图。如图4所示，显示基板还包括：位于显示区AA的多个第一连接电极60，多个第一连接电极60分别与多条第一数据信号线12和所述多条扇出走线20电连接。
在一种示例性实施例中，第一连接电极60与第一连接电极60连接的扇出走线20同层设置，且第一连接电极60连接的第一数据信号线异层设置。
在一种示例性实施例中，图5为一种示例性实施例提供的显示基板中F2区域的结构版图。如图5所示，一种示例性实施例提供的显示基板还包括：位于弯折区BB的第二数据信号线30。多条第二数据信号线30与转接线40电连接。
在一种示例性实施例中，第二数据信号线30与转接线40异层设置，且与第一数据信号线同层设置。
在一种示例性实施例中，图6为另一示例性实施例提供的显示基板中F2区域的结构版图。如图6所示，一种示例性实施例提供的显示基板还包括：位于弯折区的多个第二连接电极70，多个第二连接电极70分别与多条转接线40和多条第二数据信号线30连接。第二连接电极70与第二连接电极70连接的转接线40同层设置，且与第二连接电极70连接的第二数据信号线30异层设置。
在一种示例性实施例中，第二连接电极70的宽度与第二连接电极70连接的转接线40的宽度的比值为0.8至1。
在一种示例性实施例中，第二数据信号线30的宽度与第二数据信号线 30连接的第二连接电极70的宽度的比值为1至1.2。
在一种示例性实施例中，如图3所示，显示基板还可以包括：向显示区内的扫描信号线Gate、复位信号线和发光控制线传输信号的走线80。
在一种示例性实施例中，如图3所示，显示基板还可以包括：持续提供高电平信号的电源线VDD。
图7为一种示例性实施例提供的显示基板的部分显示区的剖视图。如图3和7所示，显示基板还包括：衬底基板10。多个子像素11设置在衬底基板10上，多个子像素中的至少一个包含驱动薄膜晶体管和存储电容。图7是以显示基板为OLED显示基板为例进行说明的。
驱动薄膜晶体管包含位于衬底基板10上的驱动有源层111，位于驱动有源层111远离衬底基板10一侧的第一绝缘层115、位于第一绝缘层115远离衬底基板10一侧的驱动栅极112、位于驱动栅极112远离衬底基板10一侧的第二绝缘层116、位于第二绝缘层116远离衬底基板10一侧的第三绝缘层117以及位于第三绝缘层117远离衬底基板10一侧的驱动源极113和驱动漏极114。
存储电容包括第一极板C1和第二极板C2。第一极板C1与驱动栅极112同层设置。第二极板C2位于第二绝缘层116和第三绝缘层117之间。
在一种示例性实施例中，第一极板C1在衬底基板10上的正投影与第二极板C2在衬底基板10上的正投影至少部分重叠。
在一种示例性实施例中，显示基板还可以包括：设置在第三绝缘层上，且依次层叠设置的第四绝缘层118、平坦层119、第一电极120、像素定义层121、隔垫物层122、有机发光层123、第二电极124、第一封装层125、第二封装层126和第三封装层127。
在一种示例性实施例中，衬底基板可以为刚性衬底基板或柔性衬底基板，其中，刚性衬底基板可以为但不限于玻璃、金属箔片中的一种或多种；柔性衬底基板可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在一种示例性实施例中，驱动有源层可以采用半导体材料，例如，多晶硅(例如低温多晶硅或高温多晶硅)、非晶硅或者氧化铟镓锡(IGZO)。
在一种示例性实施例中，驱动栅极、驱动源极和驱动漏极可以采用金属材料，例如金属铝或铝合金。这里采用的晶体管的驱动源极和驱动漏极在结构上可以是对称的，所以驱动源极和驱动漏极在结构上可以是没有区别的。
在一种示例性实施例中，第一电极可以采用氧化铟锡或者氧化锌锡。
在一种示例性实施例中，像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯。
在一种示例性实施例中，第二电极可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或更多种，或可以采用上述金属中任意一种或多种制成的合金。
在一种示例性实施例中，显示基板还可以包括：偏光片。
在一种示例性实施例中，第奇数条扇出走线与第一极板同层设置，第偶数条扇出走线与第二极板同层设置。
在一种示例性实施例中，第奇数条扇出走线与第二极板同层设置，所述第偶数条扇出走线与所述第一极板同层设置。
在一种示例性实施例中，第i条扇出走线在衬底基板上的正投影与第i+1条扇出走线在所述衬底基板上的正投影不存在重叠区域，可以避免相邻的扇出走线之间信号的串扰，提升了显示基板的显示效果。
在一种示例性实施例中，第一数据信号线和第二数据信号线与驱动源极同层设置。
在一种示例性实施例中，如图1和图5所示，多条第二数据信号线30设置有多个通孔。
在一种示例性实施例中，多个通孔的形状可以为圆孔，或者可以为椭圆孔。
在一种示例性实施例中，如图4和图6所示，第一绝缘层、第二绝缘层和第三绝缘层设置有暴露出驱动有源层的第一过孔V1。第二绝缘层和第三绝 缘层设置有暴露出与第P个扇出走线连接的第一连接电极的第二过孔V2和暴露出与第P个扇出走线连接的第二连接电极的第三过孔V3。
驱动源极和驱动漏极通过第一过孔与驱动有源层111连接。与第P个扇出走线连接的第一数据信号线通过第二过孔V2与第P个扇出走线连接的第一连接电极60连接。与第P个扇出走线连接的第二数据信号线通过第三过孔V3与第P个扇出走线连接的第二连接电极连接。
在一种示例性实施例中，第二过孔V2的数量为至少一个。当第二过孔V2的数量为多个时，多个第二过孔沿第一方向排布。图4是以两个第二过孔V2为例进行说明的。
在一种示例性实施例中，第三过孔V3的数量为至少一个。当第三过孔V3的数量为多个时，多个第三过孔沿第二方向排布。图6是以七个第三过孔V3为例进行说明的。
在一种示例性实施例中，如图4和图6所示，第三绝缘层设置有暴露出与第Q个扇出走线连接的第一连接电极的第四过孔V4和暴露出与第Q个扇出走线连接的第二连接电极的第五过孔V5。
与第Q个扇出走线连接的第一数据信号线通过第四过孔和与第Q个扇出走线连接的第一连接电极连接。与第Q个扇出走线连接的第二数据信号线通过第五过孔和与第Q个扇出走线连接的第二连接电极连接。
在一种示例性实施例中，第四过孔V4的数量为至少一个。当第四过孔的数量为多个时，多个第四过孔沿第一方向排布。图4是以两个第四过孔V4为例进行说明的。
在一种示例性实施例中，第五过孔V5的数量为至少一个。当第五过孔V5的数量为多个时，多个第五过孔沿第二方向排布。图6是以七个第五过孔V4为例进行说明的。
在一种示例性实施例中，P为小于或者等于N的奇数，Q为小于等于N的偶数，或者，P为小于等于N的偶数，Q为小于或者等于N的偶数。
在一种示例性实施例中，第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON) 中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层称为第一栅绝缘层、第二绝缘层成为第二栅绝缘层、第三绝缘层称为层间绝缘层、第四绝缘层称为钝化层。
下面结合图4、图8至图12通过显示基板的制备过程说明一种示例性实施例提供的显示基板的结构。“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶处理。沉积可以采用溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用喷涂和旋涂中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在衬底基板上利用沉积或涂覆工艺制作出的一层薄膜。当在整个制作过程中该“薄膜”无需构图工艺时，则该“薄膜”还可以称为“层”。当在整个制作过程中该“薄膜”需构图工艺时，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。本公开中所说的“A和B同层设置”是指，A和B通过同一次构图工艺同时形成。
(1)在衬底基板形成有源层，包括：在衬底基板上沉积半导体薄膜，通过构图工艺对半导体薄膜进行构图，形成驱动有源层111，图8所示。
(2)形成第一金属层，包括：在形成有有源层的衬底基板上沉积第一绝缘薄膜，通过构图工艺对第一绝缘薄膜进行构图，形成位于第一绝缘层。在第一绝缘层上沉积第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，形成第一金属层。第一金属层包括：位于显示区的扫描信号线Gate、发光控制线、复位信号线、驱动栅极112、第一极板以及位于扇出区第P个扇出走线20以及与第P个扇出走线连接的位于显示区的第一连接电极60和位于弯折区第二连接电极(图中未示出)，如图9所示。
在一种示例性实施例中，本次工艺还包括导体化处理。导体化处理是在形成第一金属层后，利用驱动栅极作为遮挡对驱动有源层进行等离子体处理，被驱动栅极遮挡区域的驱动有源层作为沟道区域，未被第一金属层遮挡区域的驱动有源层被处理成导体化层，形成导体化的源漏区域。
(3)形成第二金属层，包括：在形成有第一金属层的衬底基板上，沉积第二绝缘薄膜，通过构图工艺对第二绝缘薄膜进行构图，形成第二绝缘层。在形成有第二绝缘层的衬底基板上沉积第二金属薄膜，通过构图工艺对第二 金属薄膜进行构图，形成第二金属层。第二金属层包括：第二极板、位于扇出区的第Q个扇出走线以及与第Q个扇出走线连接的位于显示区的第一连接电极和位于弯折区的第二连接电极，如图10所示。
(4)形成第三绝缘层，包括：在形成有第二金属层的衬底基板上，沉积第三绝缘薄膜，通过构图工艺对第三绝缘薄膜进行构图，形成第三绝缘层。形成第三绝缘层开设有多个过孔。多个过孔包括：贯通第一绝缘层、第二绝缘层和第三绝缘层的第一过孔V1，贯通第二绝缘层和第三绝缘层的第二过孔V2和第三过孔V3以及仅贯通第三绝缘层的第五过孔和第六过孔，如图4所示。
在一种示例性实施例中，第一过孔暴露出驱动有源层，第二过孔暴露出与第P个扇出走线连接的第一连接电极，暴露出与第P个扇出走线连接的第二连接电极的第三过孔，第四过孔暴露出与第Q个扇出走线连接的第一连接电极，第五过孔暴露出与第Q个扇出走线连接的第二连接电极。
(5)形成第三金属层，包括：在形成有第三绝缘层的衬底基板上，沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，形成第三金属层。第三金属层包括：位于显示区AA的多个驱动源极113和驱动漏极114、位于显示区AA的第一数据信号线12、位于弯折区的第二数据信号线(图中未示出)和第一电源线VDD，如图11所示。
驱动源极113和驱动漏极114通过第一过孔与驱动有源层连接；与第P个扇出走线连接的第一数据信号线通过第二过孔和与第P个扇出走线连接的第一连接电极连接；与第P个扇出走线连接的第二数据信号线通过第三过孔和与第P个扇出走线连接的第二连接电极连接。与第Q个扇出走线连接的第一数据信号线通过第四过孔和与第Q个扇出走线连接的第一连接电极连接；与第Q个扇出走线连接的第二数据信号线通过第五过孔和与第Q个扇出走线连接的第二连接电极连接。
(6)形成第四金属层，包括：在形成有第三金属层的衬底基板上，沉积第四绝缘薄膜，通过构图工艺对第四绝缘薄膜进行构图，形成第四绝缘层。在形成有第四绝缘层的衬底基板上沉积第四金属薄膜，通过构图工艺对第四金属薄膜进行构图，形成第四金属层。第四金属层包括：向显示区内的扫描 信号线Gate、复位信号线和发光控制线传输信号的走线80，如图12所示。
(7)形成平坦层，包括：在形成有第四金属层的衬底基板上涂覆平坦薄膜，通过平坦薄膜的掩膜、曝光和显影，形成平坦层。
(8)形成发光结构层和封装层包括：在形成有平坦层的衬底基板上沉积透明导电薄膜，通过构图工艺对透明导电薄膜进行构图，形成第一电极。在形成有第一电极的衬底基板上涂覆像素定义薄膜和隔垫物薄膜，通过像素定义薄膜和隔垫物薄膜的掩膜、曝光和显影，形成像素定义层和隔垫物层。在形成有隔垫物的衬底基板上涂覆有机薄膜，通过有机薄膜的掩膜、曝光和显影，形成有机发光层，在形成有有机发光层的衬底基板上沉积金属薄膜，通过构图工艺对金属薄膜进行构图，形成第二电极。在形成第二电极的衬底基板上沉积第一封装薄膜，通过构图工艺对第一封装薄膜进行构图，形成第一封装层。在形成第一封装层的衬底基板上涂覆第二封装薄膜，通过第二封装薄膜的掩膜、曝光和显影，形成第二封装层。在形成第二封装层的衬底基板上涂覆第三封装薄膜，通过第三封装薄膜的掩膜、曝光和显影，形成第三封装层。
本公开实施例还提供一种显示装置，包括：显示基板。
在一种示例性实施例中，显示装置可以为显示器、电视、手机、平板电脑、导航仪、数码相框、可穿戴显示产品具有任何显示功能的产品或者部件。
在一种示例性实施例中，当显示基板为阵列基板时，显示装置还可以包括提供背光的背光模组。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (16)

  1. 一种显示基板，包括：显示区和围绕所述显示区的非显示区，所述非显示区包括扇出区和弯折区，所述弯折区位于所述扇出区远离所述显示区的一侧；
    多个子像素，位于所述显示区；
    多条第一数据信号线，位于所述显示区且与所述多个子像素电连接，被配置为向所述多个子像素提供数据信号；
    多条扇出走线，位于所述扇出区且沿第一方向依次排列，所述多条扇出走线与所述多条第一数据信号线电连接；
    多条第二数据信号线，位于所述弯折区且沿第一方向依次排列，所述多条第二数据信号线与所述多条扇出走线电连接；
    多条转接线，位于所述扇出区且位于所述多条扇出走线和所述多条第二数据信号线之间，所述多条转接线电连接所述多条扇出走线和所述多条第二数据信号线；
    其中，所述多条转接线中的至少部分所述转接线的宽度与所述多条扇出走线宽度的比值为0.5至5.5。
  2. 根据权利要求1所述的显示基板，其中，所述多条扇出走线中至少一条包括：
    沿第二方向排布的第一连接部、第二连接部和第三连接部，所述第二连接部位于所述第一连接部和所述第三连接部之间且连接所述第一连接部和第三连接部，所述第一连接部与所述第二连接部之间的夹角大于90度，且小于或等于180度，所述第二连接部和所述第三连接部之间的夹角大于90度，且小于或者等于180度；
    所述第三连接部的宽度和所述至少部分转接线的宽度比值为1至2；所述第一方向与所述第二方向相交。
  3. 根据权利要求2所述的显示基板，其中，至少部分转接线的宽度和至少部分第二连接部宽度的比值为2至5.5。
  4. 根据权利要求2所述的显示基板，其中，至少部分转接线的宽度等于所述第三连接部的宽度。
  5. 根据权利要求2所述的显示基板，其中，所述显示区的形状为圆角多边形，所述显示区被划分为直边区和拐角区，所述拐角区的显示区的边界为圆弧状，靠近所述拐角区的扇出走线的第一连接部的宽度与第二连接部的宽度的比值为2至5.5。
  6. 根据权利要求5所述的显示基板，其中，靠近所述拐角区的扇出走线的第一连接部的宽度与第一数据信号线的宽度的比值为2至3。
  7. 根据权利要求1所述的显示基板，其中，第i条扇出走线和第i+1条扇出走线异层设置，1≤i≤N，N为扇出走线的数量；
    所述转接线与所述转接线连接的扇出走线同层设置。
  8. 根据权利要求7所述的显示基板，其中，第奇数条扇出走线同层设置，第偶数条扇出走线同层设置。
  9. 根据权利要求1所述的显示基板，其中，所述显示基板还包括：位于所述显示区的多个第一连接电极，所述多个第一连接电极分别与所述多条第一数据信号线和所述多条所述扇出走线连接；
    所述第一连接电极与所述第一连接电极连接的扇出走线同层设置，且与所述第一连接电极连接的第一数据信号线异层设置。
  10. 根据权利要求9所述的显示基板，其中，所述显示基板还包括：位于所述弯折区的多个第二连接电极，所述多个第二连接电极分别与所述多条转接线和所述多条第二数据信号线电连接；
    所述第二连接电极与所述第二连接电极连接的转接线同层设置，且与所述第二连接电极连接的第二数据信号线异层设置；
    所述第二连接电极的宽度与所述第二连接电极连接的转接线的宽度的比值为0.8至1；所述第二数据信号线的宽度与所述第二数据信号线连接的第二连接电极的宽度的比值为1至1.2。
  11. 根据权利要求8所述的显示基板，其中，所述显示基板还包括：衬底基板，所述多个子像素设置在所述衬底基板上，所述多个子像素中的至少 一个包含驱动薄膜晶体管和存储电容；
    所述驱动薄膜晶体管包含位于所述衬底基板上的驱动有源层，位于所述驱动有源层远离所述衬底基板一侧的第一绝缘层、位于所述第一绝缘层远离所述衬底基板一侧的驱动栅极，位于所述驱动栅极远离所述衬底基板一侧的第二绝缘层，位于所述第二绝缘层远离所述衬底基板一侧的第三绝缘层，以及位于所述第三绝缘层远离所述衬底基板一侧的驱动源极和驱动漏极；
    所述存储电容包括第一极板和第二极板；所述第一极板与所述驱动栅极同层设置，所述第二极板位于所述第二绝缘层和所述第三绝缘层之间，所述第一极板在所述衬底基板上的正投影与所述第二极板在所述衬底基板上的正投影至少部分重叠。
  12. 根据权利要求11所述的显示基板，其中，所述第奇数条扇出走线与所述第一极板同层设置，所述第偶数条扇出走线与所述第二极板同层设置；
    或者，所述第奇数条扇出走线与所述第二极板同层设置，所述第偶数条扇出走线与所述第一极板同层设置；
    第i条扇出走线在所述衬底基板上的正投影与第i+1条扇出走线在所述衬底基板上的正投影不存在重叠区域。
  13. 根据权利要求11所述的显示基板，其中，所述第一数据信号线和所述第二数据信号线与所述驱动源极同层设置。
  14. 根据权利要求11所述的显示基板，其中，多条第二数据信号线设置有多个通孔；
    所述多个通孔为圆孔或者椭圆孔。
  15. 根据权利要求1所述的显示基板，其中，所述显示基板还包括：位于所述弯折区远离所述扇出区一侧的驱动芯片和多条第三数据信号线；
    所述驱动芯片通过所述多条第三数据信号线与所述多条第二数据信号线电连接。
  16. 一种显示装置，包括：如权利要求1至15任一项所述的显示基板。
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