WO2023184374A1 - 显示面板、阵列基板及其制备方法 - Google Patents

显示面板、阵列基板及其制备方法 Download PDF

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Publication number
WO2023184374A1
WO2023184374A1 PCT/CN2022/084485 CN2022084485W WO2023184374A1 WO 2023184374 A1 WO2023184374 A1 WO 2023184374A1 CN 2022084485 W CN2022084485 W CN 2022084485W WO 2023184374 A1 WO2023184374 A1 WO 2023184374A1
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WIPO (PCT)
Prior art keywords
layer
array substrate
partition groove
groove
thin film
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PCT/CN2022/084485
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English (en)
French (fr)
Inventor
白金超
刘博�
丁向前
郭晖
贾宜訸
季延鑫
刘悦
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/084485 priority Critical patent/WO2023184374A1/zh
Priority to CN202280000682.9A priority patent/CN117157729A/zh
Priority to CN202280002963.8A priority patent/CN117296088A/zh
Priority to PCT/CN2022/115817 priority patent/WO2023184849A1/zh
Publication of WO2023184374A1 publication Critical patent/WO2023184374A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present disclosure relates to the field of display technology, and specifically to a display panel, an array substrate, and a preparation method thereof.
  • organic thin film layers In display panels, organic thin film layers have the characteristics of small dielectric constant and strong smoothness, which can reduce the power consumption of the display panel and improve the contrast of the display. This makes the application of organic thin film layers in display panels more and more popular. widely. Since the organic thin film layer has the characteristic of easily absorbing water, the organic thin film layer needs to be provided with partition grooves in the peripheral area of the display panel. However, when a conductive layer is prepared on an organic thin film layer, the display panel has a high incidence of short circuit failure in the partition groove.
  • the purpose of the present disclosure is to overcome the above-mentioned shortcomings of the prior art, provide a display panel, an array substrate and a preparation method thereof to reduce short circuit defects in the partition groove.
  • an array substrate including a base substrate, a driving circuit layer, an organic thin film layer and a conductive layer that are stacked in sequence;
  • the driving circuit layer has a first padding body in the peripheral area of the array substrate;
  • the first padding body includes a first padding metal block located in at least one layer of the source-drain metal layer and the gate layer. and a first elevated insulating layer covering the first elevated metal block;
  • the organic film layer has a partition groove in the peripheral area, a part of the first pad is covered by the organic film layer and another part is exposed by the partition groove;
  • the conductive layer has a signal trace crossing the edge of the isolation groove, and the edge of the signal trace at least partially overlaps the first pad.
  • a plurality of the first boosting bodies are respectively provided on two edges of the partitioning groove;
  • Two edges of the same signal trace overlap with two adjacent first boosters respectively, and the signal trace covers the gap between the two adjacent first boosters.
  • two edges of the partitioning groove are respectively provided with one of the first pads; the signal wiring and the first pad are High body crossover setup.
  • the number of the first boosting bodies is multiple; both ends of any one of the first boosting bodies are respectively covered by the partitioning groove.
  • the organic film layers on both sides are covered; at least part of the two edges of the signal traces are overlapped with the two adjacent first pads, and the signal traces cover the two adjacent ones.
  • the gap between the first boosting bodies is multiple; both ends of any one of the first boosting bodies are respectively covered by the partitioning groove.
  • the organic film layers on both sides are covered; at least part of the two edges of the signal traces are overlapped with the two adjacent first pads, and the signal traces cover the two adjacent ones.
  • the number of the first raising body is one and both sides are respectively covered by the organic film layers on both sides of the partitioning groove; at least Part of the signal traces on the bottom surface of the partition groove is carried on the first raising body.
  • the driving circuit layer is provided with ground traces in the peripheral area, and the ground traces at least partially overlap with the isolation trench;
  • At least part of the first elevated metal block is a part of the ground trace.
  • the driving circuit layer is provided with ground traces in the peripheral area, and the ground traces at least partially overlap with the isolation trench;
  • the signal trace crosses the edge of the isolation slot and does not overlap with the ground trace.
  • the size of the portion of the first elevated body covered by the organic film layer is not less than 2 microns.
  • the height of the first pad protruding from the bottom of the partition groove is not less than 10% of the depth of the partition groove.
  • a method for preparing an array substrate including:
  • a driving circuit layer is formed on one side of the base substrate, and the driving circuit layer has a first padding body in the peripheral area of the array substrate; the first padding body includes a source-drain metal layer and a gate electrode layer. At least one layer of first elevated metal block and a first elevated insulating layer covering the first elevated metal block;
  • An organic thin film layer and a conductive layer are sequentially formed on the side of the driving circuit layer away from the base substrate; the organic thin film layer has a partition groove in the peripheral area, and a part of the first padding body is covered by the The organic film layer is covered and another part is exposed by the partition groove; the conductive layer has a signal trace crossing the edge of the partition groove, and the edge of the signal trace at least partially overlaps with the first padding body .
  • a plurality of the first boosting bodies are respectively provided on two edges of the partitioning groove;
  • Two edges of the same signal trace overlap with two adjacent first boosters respectively, and the signal trace covers the gap between the two adjacent first boosters.
  • two edges of the partitioning groove are respectively provided with one of the first pads; the signal wiring and the first pad are High body crossover setup.
  • the number of the first boosting bodies is multiple; both ends of any one of the first boosting bodies are respectively covered by the partitioning groove.
  • the organic film layers on both sides are covered; at least part of the two edges of the signal traces are overlapped with the two adjacent first pads, and the signal traces cover the two adjacent ones.
  • the gap between the first boosting bodies is multiple; both ends of any one of the first boosting bodies are respectively covered by the partitioning groove.
  • the organic film layers on both sides are covered; at least part of the two edges of the signal traces are overlapped with the two adjacent first pads, and the signal traces cover the two adjacent ones.
  • the number of the first raising body is one and both sides are respectively covered by the organic film layers on both sides of the partitioning groove; at least Part of the signal traces on the bottom surface of the partition groove is carried on the first raising body.
  • an array substrate including a base substrate, a driving circuit layer, an organic thin film layer and a conductive layer that are stacked in sequence;
  • the driving circuit layer has transfer wiring in the peripheral area of the array substrate, and the transfer wiring is located on at least one layer of the source-drain metal layer and the gate layer;
  • the organic film layer has a partition groove and a via hole exposing the transfer trace in the peripheral area; at least part of the transfer trace spans the partition groove; the conductive layer has a partition groove that is covered by the partition groove.
  • the signal traces are separated by the edge, and the two adjacent ends of the signal traces are electrically connected through the transfer traces; the signal traces and the transfer traces are connected through the via holes .
  • At least part of the transfer trace spans the partition groove, and both ends are respectively exposed by the via holes;
  • At least part of the signal trace is separated by the partition groove, and adjacent two ends of the signal trace are respectively connected to two ends of the transfer trace through the via holes.
  • the conductive layer further includes a conductive material located at an edge of the isolation trench in the isolation trench, and a circuit is broken between the conductive material and the signal trace.
  • a method for preparing an array substrate including:
  • a driving circuit layer is formed on one side of the base substrate.
  • the driving circuit layer has transfer wiring in the peripheral area of the array substrate.
  • the transfer wiring is located in at least one of the source-drain metal layer and the gate layer. layer;
  • An organic thin film layer and a conductive layer are sequentially formed on the side of the driving circuit layer away from the base substrate; the organic thin film layer has a partition groove and a via hole exposing the transfer wiring in the peripheral area; at least Part of the transfer traces crosses the partition groove; the conductive layer has signal traces separated by the edge of the partition groove, and the two adjacent ends of the signal traces are routed through the transfer traces.
  • the wires are electrically connected; the signal traces and the transfer traces are connected through the via holes.
  • an array substrate including a base substrate, a driving circuit layer, an organic thin film layer and a conductive layer that are stacked in sequence;
  • the driving circuit layer has a second padding body and a conductive structure in the peripheral area of the array substrate;
  • the second padding body includes a second padding metal block located on the gate layer and covering the second padding body.
  • a second elevated insulating layer that raises the metal block;
  • the conductive structure is located on a side of the second elevated body away from the base substrate and at least partially overlaps with the second elevated body;
  • the organic thin film layer has a partition groove in the peripheral area, the second raising body and the conductive structure are at least partially exposed by the partition groove; and the conductive structure is fully carried by the exposed part of the partition groove on the second elevated body.
  • the conductive layer includes a conductive material located between the edge of the second raising body and the edge of the partition groove in the partition groove, and the conductive material is connected to the edge of the partition groove.
  • the conductive structure is disconnected.
  • a method for preparing an array substrate including:
  • a driving circuit layer is formed on one side of the base substrate.
  • the driving circuit layer has a second raising body and a conductive structure in the peripheral area of the array substrate; the second raising body includes a second raising body located on the gate layer.
  • the two elevated bodies overlap;
  • An organic thin film layer and a conductive layer are formed in sequence on the side of the driving circuit layer away from the base substrate; the organic thin film layer has a partition groove in the peripheral area, the second padding body and the conductive structure At least part of the conductive structure is exposed by the partition groove; and the part of the conductive structure exposed by the partition groove is completely carried on the second elevated body.
  • a method for preparing an array substrate including:
  • An organic thin film layer is formed on one side of the base substrate, and the organic thin film layer has a partition groove in the peripheral area;
  • a conductive material layer is formed on the side of the organic thin film layer away from the base substrate, and the conductive material layer covers the organic thin film layer and the partition groove;
  • the conductive material layer is etched, and then the photoresist is removed.
  • a display panel including the above-mentioned array substrate.
  • the display panel further includes a cover plate disposed opposite the array substrate, and a frame sealing glue disposed between the array substrate and the cover plate; the frame sealing glue Glue covers the partition groove;
  • the driving circuit layer has conductive traces overlapping with the frame sealant in the peripheral area, and the conductive traces are designed in a grid.
  • FIG. 1 is a schematic cross-sectional structural diagram of a display panel in an embodiment of the present disclosure.
  • FIG. 2-1 is a schematic top structural view of a display panel in an embodiment of the present disclosure.
  • FIG. 2-2 is a schematic top structural view of a display panel in an embodiment of the present disclosure.
  • 2-3 are schematic top structural views of a display panel in an embodiment of the present disclosure.
  • FIG. 3 is a schematic cross-sectional structural diagram of an array substrate in an embodiment of the present disclosure.
  • FIG. 4 is a schematic cross-sectional structural diagram of an array substrate in an embodiment of the present disclosure.
  • FIG. 5 is a partial structural diagram of an array substrate in an embodiment of the present disclosure.
  • Figure 6-1 is a schematic diagram of the partial structure of the array substrate at the top corner in an embodiment of the present disclosure.
  • FIG. 6-2 is a schematic diagram of the substructure of the composite electrode layer of the array substrate in an embodiment of the present disclosure.
  • FIG. 7 is a schematic top structural view of the organic thin film layer and signal wiring of the array substrate in an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of forming an organic thin film layer on the driving circuit layer in the related art.
  • Figure 9 is a schematic structural diagram of forming a conductive material layer on an organic thin film layer in the related art.
  • Figure 10 is a schematic structural diagram of coating photoresist in the related art.
  • Figure 11 is a schematic structural diagram of insufficient exposure of the photoresist in the partition groove in the related art.
  • Figure 12 is a schematic structural diagram of the related art in which the conductive material layer in the partition trench is not sufficiently etched.
  • FIG. 13 is a schematic flowchart of a method for preparing an array substrate in an embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of forming a driving circuit layer with a first booster body in an embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of forming an organic thin film layer on the side of the driving circuit layer away from the base substrate in an embodiment of the present disclosure.
  • Figure 16 is a schematic structural diagram of forming a conductive material layer on an organic thin film layer in an embodiment of the present disclosure.
  • Figure 17 is a schematic diagram of the structure of coating photoresist on the side of the conductive material layer away from the base substrate in an embodiment of the present disclosure.
  • FIG. 18 is a schematic structural diagram of the relative positional relationship between the signal wiring, the organic film layer and the first pad in an embodiment of the present disclosure.
  • Figure 19 is a schematic diagram of the cross-sectional structure at M1-M1' in Figure 18.
  • Figure 20 is a schematic cross-sectional structural diagram at N1-N1' in Figure 18.
  • FIG. 21 is a schematic structural diagram of the relative positional relationship between the signal wiring, the organic film layer and the first pad in an embodiment of the present disclosure.
  • Figure 22 is a schematic cross-sectional structural diagram at M2-M2' in Figure 21.
  • Figure 23 is a schematic cross-sectional structural diagram at N2-N2' in Figure 21.
  • FIG. 24 is a schematic structural diagram of the relative positional relationship between the signal wiring, the organic film layer and the first pad in an embodiment of the present disclosure.
  • Figure 25 is a schematic diagram of the cross-sectional structure at M3-M3' in Figure 24.
  • Figure 26 is a schematic cross-sectional structural diagram at N3-N3' in Figure 24.
  • FIG. 27 is a schematic structural diagram of the relative positional relationship between the signal wiring, the organic film layer and the first booster body in an embodiment of the present disclosure.
  • Figure 28 is a schematic diagram of the cross-sectional structure at M4-M4' in Figure 27.
  • Figure 29 is a schematic cross-sectional structural diagram at N4-N4' in Figure 27.
  • FIG. 30 is a schematic flowchart of a method for preparing an array substrate in an embodiment of the present disclosure.
  • 31 is a schematic structural diagram of forming an organic material layer on the side of the driving circuit layer away from the base substrate in an embodiment of the present disclosure.
  • 32 is a schematic structural diagram of patterning the organic material layer and the transfer insulation layer to form via holes and isolation trenches in an embodiment of the present disclosure.
  • Figure 33 is a schematic structural diagram of the relative positional relationship between transfer wiring, organic film layers, isolation grooves and via holes in an embodiment of the present disclosure.
  • Figure 34 is a schematic structural diagram of forming a conductive material layer on an organic thin film layer in an embodiment of the present disclosure.
  • FIG. 35 is a schematic structural diagram of patterning a conductive material layer in an embodiment of the present disclosure.
  • Figure 36 is a schematic structural diagram of the relative positional relationship between signal traces, transfer traces, organic film layers, isolation grooves and via holes in an embodiment of the present disclosure.
  • Figure 37-1 is a schematic structural diagram of forming an organic thin film layer on the driving circuit layer in the related art; the driving circuit layer has a conductive structure at least partially exposed by the isolation groove.
  • Figure 37-2 is a schematic structural diagram of forming a conductive material layer on an organic thin film layer in the related art.
  • Figure 38 is a schematic structural diagram of coating photoresist in the related art.
  • Figure 39 is a schematic structural diagram of insufficient exposure of the photoresist in the partition groove in the related art.
  • FIG. 40 is a schematic structural diagram of a related art in which the conductive material layer in the isolation trench is insufficiently etched, resulting in a short circuit between the conductive structures.
  • FIG. 41 is a schematic flowchart of a method for preparing an array substrate in an embodiment of the present disclosure.
  • Figure 42 is a schematic structural diagram of forming a driving circuit layer and an organic thin film layer in an embodiment of the present disclosure, wherein the driving circuit layer has a second pad and a conductive structure.
  • Figure 43 is a schematic structural diagram of forming a conductive material layer on an organic thin film layer in an embodiment of the present disclosure.
  • Figure 44 is a schematic diagram of the structure of coating photoresist on the side of the conductive material layer away from the base substrate in an embodiment of the present disclosure.
  • Figure 45 is a schematic structural diagram showing insufficient exposure of the photoresist in the partition groove in an embodiment of the present disclosure.
  • Figure 46 is a schematic structural diagram of an embodiment of the present disclosure in which the conductive material layer in the isolation trench is insufficiently etched; the remaining conductive material is not connected to the conductive structure.
  • FIG. 47 is a schematic structural diagram in the related art where the focus plane during exposure is located on the surface of the photoresist.
  • Figure 48 is a schematic flowchart of a method for preparing an array substrate in an embodiment of the present disclosure.
  • Figure 49 is a schematic structural diagram of an embodiment of the present disclosure in which the focus plane during exposure is located inside the photoresist.
  • Figure 50 is a schematic structural diagram of an embodiment of the present disclosure in which the focus plane during exposure is located on the lower surface of the photoresist.
  • Figure 51 is a schematic structural diagram of an embodiment of the present disclosure in which the focus plane during exposure is located below the lower surface of the photoresist.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • Embodiments of the present disclosure provide an array substrate of a display panel and a preparation method thereof to avoid or reduce short circuit defects in the isolation trench.
  • the display panel PNL in the embodiment of the present disclosure may include an array substrate ARR, an adhesive layer EA, and a cover plate CF that are stacked in sequence.
  • the array substrate ARR includes a display area AA for display and a peripheral area BB surrounding the display area AA.
  • the organic thin film layer ORG is provided on the array substrate ARR, and a partition groove BG that opens toward the cover plate CF is provided in the peripheral area BB.
  • the adhesive layer EA fills the partition groove BG, which on the one hand blocks the water vapor intrusion route and on the other hand improves the adhesion between the adhesive layer EA and the array substrate ARR.
  • the display panel PNL is a liquid crystal display panel.
  • the color filter substrate of the LCD panel can be used as the cover plate CF, and the frame sealing glue of the LCD panel can be used as the adhesive layer EA; between the color filter substrate and the array substrate ARR, there is a liquid crystal box surrounded by the frame sealing glue. Filled with liquid crystal LC.
  • the organic thin film layer ORG on the array substrate ARR is provided with a partition groove BG in the peripheral area BB; when the array substrate ARR and the color filter substrate are connected through a frame sealing glue, the frame sealing glue can fill the partition groove BG.
  • this can block the path for water vapor to enter; on the other hand, it can increase the bonding area between the array substrate ARR and the frame sealant, thus improving the adhesion between the array substrate ARR and the frame sealant, overcoming the problem caused by organic matter.
  • the thin film layer ORG causes the problem of easy peeling between the array substrate ARR and the frame sealing adhesive.
  • the display panel PNL of the present disclosure can also be other types of display panels, such as a display panel with self-luminous elements.
  • the light-emitting elements and the pixel driving circuit for driving the light-emitting elements can be provided on the array substrate ARR of the display panel PNL.
  • the light-transmitting cover CF can be attached through frame sealing glue or optical glue, such as a glass cover.
  • the display panel PNL can also be an OLED (organic electroluminescent diode) display panel, a PLED (polymer organic electroluminescent diode) display panel, a Micro LED (micro light emitting diode) display panel, a QD-OLED (quantum dot-organic electroluminescent diode) display panel, QLED (quantum dot light-emitting diode) display panel or other types of self-luminous display panels.
  • OLED organic electroluminescent diode
  • PLED polymer organic electroluminescent diode
  • Micro LED micro light emitting diode
  • QD-OLED quantum dot-organic electroluminescent diode
  • QLED quantum dot light-emitting diode
  • the array substrate ARR of the present disclosure may include a base substrate BP, a driving circuit layer F100 and an electrode composite layer F200 that are stacked in sequence.
  • the electrode composite layer F200 is provided with pixel electrodes
  • the drive circuit layer F100 is provided with a pixel drive circuit for driving the pixel electrodes.
  • the light-emitting element of the array substrate ARR can be disposed in the electrode composite layer F200, or the electrode composite layer F200 of the array substrate ARR can be used as a part of the light-emitting element layer.
  • the structure and preparation method of the display panel PNL of the present disclosure are illustrated by taking the display panel PNL as a liquid crystal display panel as a specific example. It can be understood that the technical means used and the effects achieved in the exemplary description of the structure and preparation method of the display panel in the embodiments of the present disclosure can be applied to the array substrate of the self-luminous display panel directly or after reasonable deformation. middle.
  • the electrode composite layer F200 of the array substrate ARR includes at least one electrode layer, and at least one electrode layer serves as the pixel electrode layer. This pixel electrode layer is provided with pixel electrodes of the display panel PNL.
  • the common electrode layer of the display panel PNL may be provided on the array substrate ARR or the cover plate CF.
  • the electrode composite layer F200 of the array substrate ARR may include two stacked electrode layers (i.e., the first electrode layer PA1 and the second electrode layer PA2).
  • the electrode composite layer F200 of the array substrate ARR includes a first planarization layer PLN1 (made of organic material) and a first electrode layer PA1 laminated in sequence on the side of the driving circuit layer F100 away from the base substrate BP. , insulating dielectric layer and second electrode layer PA2.
  • the insulating dielectric layer may be an inorganic dielectric layer, an organic dielectric layer, or a composite laminate structure of an organic dielectric layer and an inorganic dielectric layer.
  • FIG. 1 the electrode composite layer F200 of the array substrate ARR may include two stacked electrode layers (i.e., the first electrode layer PA1 and the second electrode layer PA2).
  • the electrode composite layer F200 of the array substrate ARR includes a first planarization layer PLN1 (made of organic material) and a first electrode layer PA1 laminated in sequence on the side of the driving circuit
  • the insulating dielectric layer includes a second planarization layer PLN2 (using organic material).
  • the second planarization layer PLN2 may be directly disposed on the surface of the first electrode layer PA1 away from the base substrate BP, or an inorganic dielectric layer may be disposed between the second planarization layer PLN2 and the first electrode layer PA1.
  • One of the first electrode layer PA1 and the second electrode layer PA2 is a common electrode layer provided with a common electrode, and the other is a pixel electrode layer provided with a pixel electrode.
  • the common electrode and the pixel electrode may be independently plate-shaped electrodes or hollow electrodes (such as slit electrodes).
  • the first electrode layer PA1 serves as a pixel electrode layer, and the pixel electrode provided therein is a plate electrode.
  • the second electrode layer PA2 is a common electrode layer, and the common electrode provided therein is a hollow electrode.
  • the first electrode layer PA1 and the second electrode layer PA2 is a transparent electrode layer, such as a transparent metal electrode layer (such as a magnesium-silver alloy layer, an aluminum-silver alloy layer, etc. ) or a transparent metal oxide electrode layer (such as an indium tin oxide layer).
  • a transparent metal electrode layer such as a magnesium-silver alloy layer, an aluminum-silver alloy layer, etc.
  • a transparent metal oxide electrode layer such as an indium tin oxide layer.
  • the first electrode layer PA1 and the second electrode layer PA2 are both transparent electrode layers.
  • the materials of the first electrode layer PA1 and the second electrode layer PA2 are both indium tin oxide (ITO).
  • the electrode composite layer F200 of the array substrate ARR may include one electrode layer, that is, only the first electrode layer PA1 is provided.
  • the electrode composite layer F200 of the array substrate ARR includes a first planarization layer PLN1 and a first electrode layer PA1 that are sequentially stacked on the side of the driving circuit layer F100 away from the base substrate BP.
  • the first electrode layer PA1 is provided with a pixel electrode as a pixel electrode layer.
  • the electrode composite layer F200 further includes an alignment layer for controlling the pretilt angle of the liquid crystal molecules.
  • the electrode composite layer F200 further includes a support pillar layer formed with a plurality of support pillars to improve the cell thickness stability of the liquid crystal cell.
  • the base substrate BP may be a base substrate BP of inorganic material or a base substrate BP of organic material.
  • the material of the substrate BP may be glass materials such as soda-lime glass, quartz glass, sapphire glass, or may be stainless steel, aluminum, nickel, etc. metallic material.
  • the material of the substrate BP can be polymethyl methacrylate (PMMA), polyvinyl alcohol (Polyvinyl alcohol, PVA), polyvinyl phenol (Polyvinyl phenol, PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), Polyethylene naphthalate (PEN) or combinations thereof.
  • PMMA polymethyl methacrylate
  • PMMA polyvinyl alcohol
  • PVA polyvinyl alcohol
  • Polyvinyl phenol Polyvinyl phenol, PVP
  • PES polyether sulfone
  • polyimide polyamide
  • polyacetal polycarbonate
  • PC polyethylene terephthalate
  • PET polyethylene naphthalate
  • PEN Polyethylene naphthalate
  • the base substrate BP can also be a flexible base substrate BP.
  • the material of the base substrate BP can be polyimide (polyimide, PI).
  • the base substrate BP can also be a composite of multiple layers of materials.
  • the base substrate BP can include a bottom film layer (Bottom Film), a pressure-sensitive adhesive layer, and a pressure-sensitive adhesive layer that are stacked in sequence.
  • a first polyimide layer and a second polyimide layer are stacked in sequence. It can be understood that when the liquid crystal display panel PNL in the example of the embodiment of the present disclosure is a transmissive liquid crystal display panel PNL, the base substrate BP is made of a transparent material.
  • any pixel driving circuit may include a transistor.
  • the transistor can be a thin film transistor, and the thin film transistor can be selected from a top gate thin film transistor, a bottom gate thin film transistor, or a double gate thin film transistor;
  • the material of the active layer of the thin film transistor can be non- Crystalline silicon semiconductor material, low-temperature polysilicon semiconductor material, metal oxide semiconductor material, organic semiconductor material or other types of semiconductor materials;
  • the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor.
  • the pixel driving circuit may be a switching transistor F100M.
  • the driving circuit layer may include a semiconductor layer SEMI, a gate insulating layer GI, a gate layer GT, and an interlayer dielectric layer ILD stacked between the base substrate BP and the electrode composite layer F200. and source-drain metal layer SD, etc.
  • the switching transistor can be formed of a semiconductor layer SEMI, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD and other film layers. The positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor.
  • the driving circuit layer may include a semiconductor layer SEMI, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD and a source-drain metal layer SD that are stacked in sequence.
  • the switching transistor thus formed is a top layer.
  • the driving circuit layer may include a gate layer GT, a gate insulating layer GI, a semiconductor layer SEMI, an interlayer dielectric layer ILD and a source-drain metal layer SD that are stacked in sequence.
  • the thin film transistor thus formed It is a bottom gate thin film transistor.
  • the thickness of the gate layer GT may be between 0.1 and 1 micron, for example, between 0.3 and 0.5 micron.
  • the gate layer GT may be a metal layer (such as a copper layer), or may include multiple metal layers stacked in sequence (such as Ti/Al/Ti, Mo/Cu/Mo, etc.). These metal layers may include alloys. layer, such as MoNi alloy layer, etc.
  • the gate layer GT may also have a conductive non-metal layer, such as a TiN layer.
  • the thickness of the source and drain metal layer SD may be between 0.1 and 1 micron, for example, between 0.3 and 0.5 micron.
  • the source and drain metal layer SD may be a metal layer (such as a copper layer), or may include multiple metal layers stacked in sequence (such as Ti/Al/Ti, Mo/Cu/Mo, etc.). These metal layers may include Alloy layer, such as MoNi alloy layer, etc.
  • the gate layer GT may also have a conductive non-metal layer, such as a TiN layer.
  • the driving circuit layer can be provided with multiple data voltage traces DataW.
  • the data voltage traces DataW can extend along the column direction as a whole. They can extend in a straight line or reciprocate in the row direction. Bent polyline. Further, the data voltage wiring DataW can be provided on the source and drain metal layers.
  • the gate layer GT is provided with multiple scan lines GTW.
  • one end of the switching transistor F100M is connected to the data voltage line DataW
  • the other end of the switching transistor is connected to the pixel electrode PIXP
  • the gate of the switching transistor is connected to the scanning line GTW.
  • the switching transistor F100M Under the control of the scan voltage loaded on the scan line GTW, the switching transistor F100M can be turned on, so that the data voltage on the data voltage line DataW is loaded to the pixel electrode.
  • the scan trace GTW can extend along the row direction as a whole.
  • the scanning trace GTW can be a straight lead along the row direction, or it can be a polyline that bends back and forth in the column direction.
  • the scan line GTW and the data voltage line DataW can define multiple pixel areas, and pixel electrodes and switching transistors can be arranged in the pixel area.
  • the active layer of the switching transistor F100M is disposed on the semiconductor layer SEMI.
  • the active layer of the switching transistor may include a source contact area, a channel area, and a drain contact area connected in sequence.
  • the source contact area is connected to the data voltage wiring DataW through a via hole, and the drain contact area and the pixel electrode are connected through the via hole. connect.
  • the scanning line GTW overlaps the channel region of the switching transistor, so that the portion of the scanning line GTW overlapping the channel region of the switching transistor can serve as a gate electrode of the switching transistor.
  • the switching transistor is a bottom-gate thin film transistor, and the size of the portion where the scanning line GTW overlaps with the channel region of the switching transistor can be locally increased, so that the scanning line GTW completely blocks the channel area of the switching transistor. channel region to prevent light from irradiating the channel region of the switching transistor from one side of the base substrate BP to causing changes in the characteristics of the switching transistor (for example, an increase in leakage current).
  • the electrode composite layer F200 of the array substrate ARR also includes a common electrode layer.
  • the common electrode layer is provided with a common electrode COMP and a common electrode trace COMW connecting adjacent common electrodes COMP.
  • the common electrode line COMW can also be provided on other film layers, such as the gate layer GT.
  • the driving circuit layer may further include a passivation layer, and the passivation layer is disposed on a side of the source-drain metal layer SD away from the base substrate BP to protect the source-drain metal layer SD.
  • the driving circuit layer may also include an inorganic buffer layer Buff.
  • the inorganic buffer layer Buff is disposed on the surface of the base substrate BP.
  • the gate layer GT, the semiconductor layer SEMI, the source-drain metal layer SD, etc. are disposed far away from the inorganic buffer layer Buff.
  • the materials of the inorganic buffer layer Buff, passivation layer, interlayer dielectric layer ILD and gate insulating layer GI may be dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, etc.
  • the passivation layer and the interlayer dielectric layer ILD are made of silicon nitride
  • the materials of the inorganic buffer layer Buff and the gate insulating layer GI are silicon oxide.
  • the array substrate may include a substrate substrate BP, an electrode composite layer F200 and a driving circuit layer F100 that are stacked in sequence, or the driving circuit layer F100 and the electrode composite layer F200 are mixed with each other, or the driving circuit The layer F100 is sandwiched between the electrode composite layers F200.
  • the array substrate ARR includes a base substrate BP, a first electrode layer PA1 and a gate layer GT, a gate insulating layer GI, a semiconductor layer SEMI, a source and drain metal layer SD, a planarization layer PLN and a third layer that are stacked in sequence. Two electrode layers PA2.
  • the first electrode layer PA1 and the gate layer GT have the same film layer position and use different materials, and are two layers nested with each other; the first electrode layer PA1 and the second electrode layer PA2 serve as two layers of the electrode composite layer F200.
  • the electrode layer, semiconductor layer SEMI, source-drain metal layer SD, gate layer GT, etc. serve as film layers of the drive circuit layer F100.
  • these possible stacking methods of the array substrate ARR are all applicable to the preparation method of the array substrate ARR of the present disclosure.
  • the electrode composite layer F200 has a substructure composed of an organic thin film layer ORG and a conductive layer FSW located on the side of the organic thin film layer ORG away from the base substrate BP.
  • the electrode composite layer F200 of the array substrate ARR includes the first planarization layer PLN1 and the first electrode layer PA1 stacked in sequence, then the first planarization layer PLN1 and the first electrode layer PA1 may form a substructure.
  • the first planarization layer PLN1 serves as the organic thin film layer ORG
  • the first electrode layer PA1 serves as the conductive layer FSW.
  • the display panel PNL includes a first planarization layer PLN1, a first electrode layer PA1, a second planarization layer PLN2 and a second electrode layer PA2 stacked in sequence, then the second planarization layer PLN2 and the second electrode layer PA2 can form a substructure.
  • the second planarization layer PLN2 serves as the organic thin film layer ORG
  • the second electrode layer PA2 serves as the conductive layer FSW.
  • the first planarization layer PLN1 and the first electrode layer PA1 may also form a substructure.
  • the electrode composite layer F200 is provided with a planarization layer PLN and a second electrode layer PA2 on the side of the source-drain metal layer SD away from the base substrate BP, then the planarization layer PLN can be used as the organic thin film layer ORG, and the third The two-electrode layer PA2 can serve as the conductive layer FSW.
  • the thickness of the organic thin film layer ORG may be between 0.5 and 5 microns, for example, between 1.5 and 3 microns.
  • the width of the barrier groove BG formed on the organic thin film layer ORG may be between 10 and 200 microns.
  • the partition groove BG is provided in the peripheral area BB of the array substrate ARR and is provided around the display area AA, for example, it is provided in the glue coating area of the display panel PNL for applying frame sealing glue.
  • the number of partition grooves BG is multiple, and at least some of the partition grooves BG are arranged around the display area AA in sequence. Furthermore, at different locations, the number of partition grooves BG may be the same or different. For example, referring to Figure 6-1, at the corners of the array substrate ARR, the number of partition grooves BG is four, and at non-corners, the number of partition grooves BG is two. In this way, the strength of the frame sealing at the corners can be improved and defects such as punctures of the display device at the corners can be avoided.
  • the partition groove BG may be designed discontinuously, that is, the partition groove BG may include multiple partition sub-grooves.
  • At least one partition groove BG is provided continuously, that is, the partition groove is in a continuous ring shape.
  • the number of partition grooves of the array substrate ARR may also be one.
  • a groove is provided between two adjacent partition grooves BG, so that the two adjacent partition grooves BG are connected to each other.
  • the blocking groove BG penetrates the organic thin film layer ORG.
  • the conductive layer FSW may be formed with signal traces SW spanning the edges of the isolation trench BG, for example, at least one signal trace SW spans two opposite sides of the isolation trench BG.
  • the side wall that is, the side wall of the organic film layer ORG
  • at least one signal trace SW crosses one side wall of the partition trench BG and then continues to be routed or stopped in the partition trench BG.
  • the signal trace SW may be a clock trace used to transmit a clock signal.
  • the signal trace SW can also transmit other signals.
  • the width of at least some of the signal traces SW is 10-20 microns, and the gap between at least some of the signal traces SW is 10-20 microns.
  • the width of the signal traces SW and the gaps between the signal traces SW can be set as needed. For example, at least the width of the signal traces SW can be reduced to 3-10 microns, or at least a gap between part of the signal traces SW can be reduced to 3-10 microns.
  • the width of the same signal trace SW may be different at different positions.
  • the width of the signal trace SW on the sidewall of the organic film layer ORG may be smaller than the width of the signal trace SW on the bottom of the isolation trench BG.
  • the driving circuit layer is provided with ground traces in the peripheral area BB.
  • the ground trace grid is designed to increase the light transmittance of the ground trace and facilitate the curing of the frame sealant.
  • the ground traces may not adopt a hollow design, that is, adopt a full-surface structure to reduce the impedance of the ground traces.
  • Step S011 see Figure 8, prepare the base substrate BP, the driving circuit layer F100 and the organic thin film layer ORG in sequence.
  • the organic thin film layer ORG is provided with a partition groove BG.
  • Step S012 see FIG. 9, forming a conductive material layer FSWA on the surface of the organic thin film layer ORG away from the base substrate BP.
  • a photolithography process is used to pattern the conductive material layer FSWA.
  • step S013 referring to FIG. 10
  • the side of the conductive material layer FSWA away from the base substrate BP is filled with photoresist PR.
  • the photoresist PR fills the partition groove BG; due to the fluidity of the photoresist, the thickness of the photoresist PR is the largest in the edge area SA of the partition groove BG.
  • step S014 referring to FIG. 11, the photoresist PR is exposed and developed. In the edge area SA of the partition groove BG, the photoresist PR cannot be fully exposed and remains. The remaining photoresist PRR will block and protect the conductive material layer FSWA below (the side close to the base substrate BP).
  • step S015 when patterning the conductive material layer FSWA by etching, the conductive material blocked by the residual photoresist PRR may not be fully etched and remains, and the residual conductive material FSWR may cause There is a short circuit between two adjacent signal traces SW.
  • the residual photoresist PRR refers to the portion of the photoresist expected to be removed by exposure and development that remains due to insufficient exposure and development. According to the process, the part that is not developed and is expected to be retained (that is, the part that is used as a mask for subsequent etching) is the normally retained photoresist rather than the residual photoresist PRR.
  • the preparation method shown in the following steps S110 to S120 can be used to prepare the array substrate ARR of the embodiment of the present disclosure.
  • a driving circuit layer F100 is formed on one side of the base substrate BP.
  • the driving circuit layer F100 has a first pad DA in the peripheral area BB of the array substrate ARR; the first pad
  • the high body DA includes a first padding metal block DAC located in at least one layer of the source-drain metal layer SD and the gate layer GT and a first padding insulating layer DAI covering the first padding metal block DAC;
  • Step S120 see FIGS. 15 to 29 , an organic thin film layer ORG and a conductive layer FSW are sequentially formed on the side of the driving circuit layer F100 away from the base substrate BP.
  • the organic thin film layer ORG has a partition groove BG in the peripheral area BB. A part of the first pad DA is covered by the organic thin film layer ORG and another part is exposed by the partition groove BG. This causes the exposed portion of the first raised body DA to form a raised step DAS protruding from the bottom of the partitioning groove BG.
  • the conductive layer FSW has a signal trace SW crossing the edge of the isolation trench BG, and the edge of the signal trace SW at least partially overlaps the first pad DA. In other words, the edge of the signal trace SW is at least partially carried on the elevated step DAS.
  • preparing the organic thin film layer ORG and the conductive layer FSW is part of preparing the electrode composite layer F200.
  • the electrode composite layer F200 is prepared on the side of the driving circuit layer F100 away from the base substrate BP.
  • the electrode composite layer F200 includes an organic thin film layer ORG and a conductive layer FSW located on a side of the organic thin film layer ORG away from the base substrate BP.
  • step S120 may include steps S121 to S126.
  • an organic thin film layer ORG is formed on the side of the driving circuit layer F100 away from the base substrate BP.
  • the organic thin film layer ORG has a partition groove BG in the peripheral area BB. Among them, a part of the first elevated body DA is covered by the organic film layer ORG, and the other part is exposed in the partition groove BG. In other words, the first raising body DA is located at the lower edge of the partitioning groove BG (the edge close to the base substrate). The portion of the first padding body DA exposed to the partition groove BG forms a padding step DAS.
  • a conductive material layer FSWA is formed on the side of the organic thin film layer ORG away from the base substrate BP, and the conductive material layer FSWA covers the organic thin film layer ORG and the partition groove BG. Among them, the conductive material layer FSWA covers the elevated step DAS in the partition groove BG.
  • Step S123 see FIG. 17, apply photoresist PR on the side of the conductive material layer FSWA away from the base substrate BP, and the photoresist PR fills the partition groove BG.
  • the thickness of the photoresist PR above the raising step DAS is reduced.
  • Step S124 expose and develop the photoresist PR.
  • the thickness of the photoresist PR in the portion raised by the elevated step DAS is reduced, so that it can be fully exposed, and residues are less likely to occur.
  • Step S125 Etch the conductive material layer FSWA to form a required structure, such as forming a required signal line SW.
  • the conductive material can be fully etched because there is no residual photoresist blocking, ensuring the accuracy of the signal wiring SW pattern. It is avoided that the conductive material remaining between the signal traces SW causes a short circuit between the signal traces SW.
  • Step S126 remove the photoresist PR.
  • the mask of the source and drain metal layer SD or the gate layer GT can be adjusted to prepare the driver circuit layer F100 without adding any process.
  • the first padding insulating layer DAI is an inorganic material layer located on the side of the first padding metal block DAC away from the base substrate BP, and may vary according to the first padding metal block DAC.
  • the first raised metal block DAC is located on the source and drain metal layer SD and the first raised insulation layer DAI is located on the passivation layer.
  • the first padding metal block DAC is located on the gate layer GT, and the first padding insulation layer DAI is located on at least one of the interlayer dielectric layer ILD and the passivation layer.
  • the first raised metal block DAC includes a bottom metal block located on the gate layer GT and a top metal block located on the source and drain metal layer SD, and the top metal block is carried on the bottom metal block , for example, the edges of the two are flush; in this way, the first raised metal block DAC can have a greater thickness, thereby making the step difference between the raised step DAS and the bottom of the partitioning trench BG larger.
  • the organic thin film layer ORG covers a part of the first pad body DA and the partition groove BG exposes a part of the first pad body DA.
  • the first raising body DA forms a raising step DAS connected to the side wall of the partitioning groove BG and protruding from the bottom of the partitioning groove BG.
  • the conductive material layer FSWA covers the raised step DAS, thereby making the step difference between the conductive material layer FSWA on the raised step DAS and the surface of the organic film layer ORG smaller.
  • the thickness of the photoresist on the raised step DAS is reduced, and photoresist residues are less likely to appear during the exposure and development processes.
  • the gap between the signal traces SW overlaps with the first pad DA.
  • the focus plane of the exposure machine is the upper surface of the photoresist (the surface far away from the base substrate BP), or is close to the photoresist
  • the position of the upper surface does not exceed 10% of the maximum thickness of the photoresist.
  • the height of the raising step DAS is not less than 10% of the depth of the partitioning groove BG.
  • the height of the raising step DAS is in the range of 10% to 40% of the depth of the partitioning groove BG.
  • the height of the elevated step DAS is between 0.3 and 0.5 microns, and the depth of the partition groove BG is between 1.5 and 3 microns.
  • the depth of the isolation trench BG refers to the distance between the bottom surface of the isolation trench BG (the bottom surface close to the base substrate BP) and the top opening of the isolation trench BG (the opening away from the base substrate BP). step difference.
  • the height of the raising step DAS refers to the step difference between the top surface of the raising step DAS (the surface away from the base substrate BP) and the bottom surface of the partitioning groove BG.
  • the step difference refers to the distance difference between the two structures or surfaces and the base substrate BP.
  • the height of the raising step DAS is substantially equal to the thickness of the first raising metal block DAC.
  • the orthographic projection of the first raising body DA on the base substrate BP is the same as the orthographic projection of the organic thin film layer ORG on the substrate.
  • the size of the overlapping portion of the orthographic projection on the base substrate BP in the direction perpendicular to the lower edge of the partition groove BG is not less than 2 microns, especially not less than 3 microns, for example, between 3 and 5 microns. In this way, it can be ensured that at least part of the first raising body DA is covered by the organic film layer ORG, thereby connecting the top surface of the first raising body DA with the side of the partition groove BG, overcoming the influence of factors such as process fluctuations and alignment deviations. .
  • a plurality of the first padding bodies DA are respectively provided on two edges of the partitioning groove BG; in the same place The two edges of the signal trace SW overlap with the two adjacent first boosters DA respectively, and the signal trace SW covers the gap between the two adjacent first boosters DA. .
  • two edges of at least one signal trace SW overlap with the two adjacent first padding bodies DA respectively.
  • a plurality of first padding bodies DA are respectively provided at two lower edges of the partition groove BG.
  • the first pads DA that overlap with the same signal trace SW and are respectively located at two opposite lower edges of the partition groove BG are not connected, that is, gaps are provided.
  • the first raising body DA is only disposed close to the lower edge of the partitioning groove BG, and the first raising body DA is independently provided on the two lower edges of the partitioning groove BG. In this way, there is a gap between the two lower edges of the partition groove BG without the first raising body DA, which is beneficial to increasing the intensity of light irradiating the frame sealing glue and increasing the curing speed of the frame sealing glue.
  • one of the first padding bodies DA is respectively provided on two edges of the partitioning groove BG;
  • the signal trace SW intersects the first raising body DA.
  • At least partially adjacent smaller first raising bodies DA located at the same lower edge of the partition groove BG can be connected in sequence to form a strip-shaped first raising body DA.
  • at least one signal trace SW intersects with the strip-shaped first elevated body DA, and both sides of the signal trace SW overlap with the same strip-shaped first elevated body DA.
  • this can simplify the design of the display panel PNL and reduce the size requirements for the mask; on the other hand, it overcomes the constraints of exposure accuracy, alignment deviation and other process factors on the size of the first pad DA, improving the Applicable range on PNL display panels of different sizes.
  • the setting of the strip-shaped first pad DA can ensure that the edge of the signal trace SW overlaps the first pad DA, avoiding the edge of the signal trace SW caused by factors such as process fluctuations or alignment deviations.
  • the process window is improved and possible defects are overcome.
  • each first pad that overlaps the group of signal traces SW and is located at the same lower edge of the isolation trench BG The bodies DA are connected to each other to form a strip-shaped first padding body DA; in other words, the same group of signal traces SW that are adjacent in sequence are intersected with the same strip-shaped first padding body DA.
  • the number of the first padding bodies DA is multiple; any one of the first padding bodies DA Both ends of the signal trace SW are respectively covered by the organic film layer ORG on both sides of the partition groove BG; at least part of the two edges of the signal trace SW overlap with the two adjacent first padding bodies DA. is arranged, and the signal trace SW covers the gap between two adjacent first raising bodies DA.
  • the first raising body DA can extend along the extension direction of the overlapping signal trace SW and penetrate the partition groove BG, and its two ends are respectively connected with the two side walls of the partition trench BG (ie, the sides of the organic film layer ORG). walls) overlap. In this way, not only can the electrode material be prevented from remaining at the lower edge of the partition groove BG, but also the electrode material can be prevented from remaining at the bottom of the partition groove BG, further reducing the risk of short circuit of the signal wiring SW.
  • the edge of any signal trace SW is located on the first pad DA (the side of the first pad DA away from the base substrate BP), and the signal trace SW
  • the two edges of are respectively located on two different first elevated bodies DA.
  • this first raising body DA The setting method can simplify the design of the first elevated body DA and reduce the requirements on the process.
  • the number of the first padding bodies DA is one and both sides are respectively surrounded by two sides of the partitioning groove BG.
  • the organic film layer ORG covers; at least part of the signal trace SW on the bottom surface of the isolation groove BG is carried on the first pad DA.
  • At least one first raising body DA is overlapped with a plurality of adjacent signal traces SW, and the portions of these signal traces SW at the bottom of the isolation trench BG are completely located on the first raising body DA.
  • the orthographic projection of the plurality of signal traces SW on the base substrate BP at the bottom of the isolation trench BG is located on the same first pad DA on the base substrate BP. within the orthographic projection.
  • the driving circuit layer F100 is provided with a ground trace in the peripheral area BB, and the ground trace at least partially overlaps with the partition groove BG; at least part of the first Raise the metal block DAC as part of the ground trace.
  • the short circuit defects in the isolation trench BG can be reduced through local adjustment of the ground trace pattern, thereby achieving the goal of improving the yield without increasing the ARR preparation cost.
  • the driving circuit layer F100 is provided with a ground trace in the peripheral area BB, and the ground trace at least partially overlaps with the partition groove BG; the signal trace The position of SW crossing the edge of the partition groove BG does not overlap with the ground trace.
  • the preparation method shown in the following steps S210 to S220 can be used to prepare the array substrate ARR of the present disclosure.
  • Step S210 see Figure 31, form a driving circuit layer F100 on one side of the base substrate BP.
  • the driving circuit layer F100 has a transfer trace TRW in the peripheral area BB of the array substrate ARR.
  • the transfer trace TRW is located in at least one layer of the source-drain metal layer SD and the gate layer GT.
  • Step S220 see Figures 31 to 36, an organic thin film layer ORG and a conductive layer FSW are sequentially formed on the side of the driving circuit layer F100 away from the base substrate BP; the organic thin film layer ORG is in the peripheral area BB There is a partition groove BG and a via HH exposing the transfer trace TRW; at least part of the transfer trace TRW spans the partition groove BG (that is, the two ends of the transfer trace TRW are respectively located at the partition groove BG Both sides); the conductive layer FSW has a signal trace SW separated by the edge of the partition groove BG, and the two adjacent ends of the signal trace SW are electrically connected through the transfer trace TRW; so The signal trace SW and the transfer trace TRW are connected through the via hole HH.
  • the signal trace SW crosses the partition groove BG through the transfer trace TRW located in the driving circuit layer F100. Even if there is conductive material remaining in the partition groove BG, the remaining conductive material will not be electrically connected to the signal trace SW. In this way, a short circuit between the signal traces SW caused by the conductive material remaining in the isolation trench BG can be avoided.
  • preparing the organic thin film layer ORG and the conductive layer FSW is part of preparing the electrode composite layer F200.
  • the electrode composite layer F200 is prepared on the side of the driving circuit layer F100 away from the base substrate BP.
  • the electrode composite layer F200 includes an organic thin film layer ORG and a conductive layer FSW located on a side of the organic thin film layer ORG away from the base substrate BP.
  • the conductive layer FSW further includes a conductive material located at an edge of the isolation trench BG in the isolation trench BG, and the conductive material is disconnected from the signal trace SW.
  • the driving circuit layer F100 further includes a transfer insulating layer TRI covering the transfer trace TRW in the peripheral area BB.
  • a transfer insulating layer TRI covering the transfer trace TRW in the peripheral area BB.
  • the via HH when forming the via HH that electrically connects the signal trace SW and the transfer trace TRW, the via HH penetrates the organic film layer ORG and the transfer insulating layer TRI, so that both ends of the transfer trace TRW They are exposed through two via holes HH located on both sides of the partition groove BG.
  • the transfer insulation layer TRI can be adjusted accordingly according to the transfer trace TRW.
  • the transfer trace TRW is located on the source-drain metal layer SD
  • the transfer insulation layer TRI may be located on the passivation layer.
  • the transfer insulation layer TRI when the transfer trace TRW is located on the gate layer GT, the transfer insulation layer TRI may be located on one or both layers of the interlayer dielectric layer ILD and the passivation layer.
  • At least part of the transfer trace TRW spans the partition groove BG, and both ends are respectively exposed by the via holes HH; at least part of the signal trace SW is The partition groove BG separates, and the adjacent two ends of the signal trace SW are respectively connected to the two ends of the transfer trace TRW through the via hole HH.
  • the number of transfer traces TRW crossing the partition trench BG is the same as the number of signal traces SW that need to cross the partition trench BG, and
  • the connecting trace TRW and the signal trace SW are set in one-to-one correspondence.
  • the adjacent two ends of the signal trace SW separated by the partition groove BG are electrically connected to the two ends of the corresponding transfer trace TRW through the via holes HH respectively.
  • each signal trace SW crosses the partition groove BG through the transfer trace TRW.
  • the end of the signal trace SW is outside the isolation trench BG, that is, the orthographic projection of the signal trace SW on the substrate BP is the same as the orthographic projection of the isolation trench BG on the substrate BP. There is no overlapping area.
  • At least one transfer trace TRW spans multiple adjacent partition grooves BG; in this way, the signal trace SW can continuously span multiple partition trenches BG through the same transfer trace TRW, without the need to set up multiple partition trenches BG.
  • Different transfer traces TRW are used to span multiple different partition grooves BG, thereby avoiding the need to provide via holes HH on the organic film layer ORG between different partition grooves BG.
  • At least one transfer trace TRW includes different trace segments, and adjacent trace segments are respectively provided on the source-drain metal layer SD and the gate layer GT.
  • the transfer trace TRW can transfer between the source-drain metal layer SD and the gate electrode layer GT to avoid other structures of the source-drain metal layer SD or the gate electrode layer GT.
  • At least one signal trace SW is partially located in the isolation trench BG and the extension direction is parallel to the extension direction of the isolation trench BG; the routing portion of the signal trace SW on the organic film layer ORG is the same as that of the signal trace SW on the organic film layer ORG.
  • the wiring part in the partition groove BG can also be transferred through the transfer wiring TRW.
  • One end of the transfer trace TRW used to transfer the signal trace SW is located on the organic film layer ORG and is connected to the trace portion of the signal trace SW on the organic film layer ORG through the via HH, and the other end is located in the partition groove BG is connected to the trace portion of the signal trace SW located in the partition groove BG through a via hole. In this way, the transfer trace TRW does not need to cross the partition groove BG.
  • step S220 may include the steps shown in the following steps S221 to S225.
  • Step S221, see FIG. 31, prepare an organic material layer ORGA on the side of the driving circuit layer F100 away from the base substrate BP.
  • Step S222 see FIG. 32, pattern the organic material layer ORGA and the transfer insulation layer TRI.
  • the organic thin film layer ORG has a partition groove BG, and the organic thin film layer ORG and the transfer insulation layer TRI form a via hole HH that exposes the transfer wiring TRW.
  • the transfer trace TRW spans the partition groove BG, and both ends are exposed by the vias HH.
  • a conductive material layer FSWA is formed on the side of the organic thin film layer ORG away from the base substrate BP.
  • the conductive material layer FSWA can cover the organic thin film layer ORG and the partition groove BG.
  • Step S224 see FIG. 35 and FIG. 36, pattern the conductive material layer FSWA, thus preparing the signal trace SW. Among them, at least part of the signal trace SW is transferred through the transfer trace TRW to cross the partition groove BG.
  • the isolation trench BG in the array substrate ARR according to the embodiment of the present disclosure, at least part of the isolation trench BG will be provided with a conductive structure DW located on the source and drain metal layer SD.
  • short circuit defects often occur between the source and drain metal layers SD located in the isolation trench BG. After analyzing this type of defect, it was found that conductive material remained between the conductive structures DW, and the conductive structures DW were short-circuited by the remaining conductive material.
  • the preparation process of array substrate ARR in related technologies was traced. Referring to Figures 37-1 to 40, the array substrate ARR in the related art is prepared using the method shown in the following steps S021 to S025.
  • Step S021 see Figure 37-1, prepare the base substrate BP, the driving circuit layer F100 and the organic thin film layer ORG in sequence; the organic thin film layer ORG is provided with a partition groove BG in the peripheral area BB, and the driving circuit layer F100 is provided with a partition groove BG in the peripheral area BB.
  • the conductive structure DW, and at least part of the conductive structure DW is exposed to the isolation groove BG, for example, it is completely located in the isolation groove BG.
  • Step S022 see Figure 37-2, form a conductive material layer FSWA on the surface of the organic thin film layer ORG away from the base substrate BP.
  • a photolithography process is used to pattern the conductive material layer FSWA.
  • step S023 referring to FIG. 38, photoresist PR is coated on the side of the conductive material layer FSWA away from the base substrate BP.
  • the photoresist PR fills the partition groove BG; due to the fluidity of the photoresist, the thickness of the photoresist PR is the largest between the conductive structure DW and the edge of the partition groove BG.
  • step S024 referring to FIG. 39, the photoresist PR is exposed and developed. Between the edge of the partition groove BG and the conductive structure DW, the photoresist PR cannot be fully exposed and remains. The remaining photoresist PRR will block the conductive material layer FSWA below (the side close to the base substrate BP). and protection.
  • step S025 when patterning the conductive material layer FSWA by etching, the conductive material blocked by the residual photoresist PRR may not be fully etched and remains, and the residual conductive material FSWR may cause There is a short circuit between two adjacent conductive structures DW.
  • the inventor tried to eliminate photoresist residues through overexposure to reduce short circuit defects, but found that this would greatly extend the exposure time and affect the exposure rhythm, which would have a greater impact on production capacity and increase the ARR of the array substrate. the cost of.
  • the inventor also found that as the size of each structure in the array substrate ARR continues to shrink, the over-exposure solution is increasingly restricted by the process capabilities of the exposure machine.
  • the preparation method shown in the following steps S310 to S320 can be used to prepare the array substrate ARR of the embodiment of the present disclosure.
  • a driving circuit layer F100 is formed on one side of the base substrate BP.
  • the driving circuit layer F100 has a second pad DB and a conductive structure DW in the peripheral area BB of the array substrate ARR; so
  • the second padding body DB includes a second padding metal block DBC located on the gate layer GT and a second padding insulating layer DBI covering the second padding metal block DBC, so that the second padding body DB is formed There is a boss structure protruding upward.
  • the conductive structure DW is located on a side of the second elevated body DB away from the base substrate BP and at least partially overlaps the second elevated body DB;
  • Step S320 see Figures 42 to 46, an organic thin film layer ORG and a conductive layer FSW are sequentially formed on the side of the driving circuit layer F100 away from the base substrate BP; the organic thin film layer ORG is in the peripheral area BB There is a partition groove BG, the second boosting body DB and the conductive structure DW are at least partially exposed by the partition groove BG; and the part of the conductive structure DW exposed by the partition groove BG is completely carried on the third The second pad raises the body DB. In other words, the part of the conductive structure DW exposed by the partition groove BG is completely located on the boss structure formed by the second booster body DB.
  • the conductive material on the step can be fully etched, so even if the second booster DB There are conductive materials remaining on the edge of the partition groove BG, and these conductive materials will not be connected to the conductive structures DW, thus avoiding a short circuit between the conductive structures DW.
  • the remaining conductive material cannot be continuous at the edge of the second booster body DB due to the existence of step differences, which further reduces the conductivity. Risk of short circuit in structural DW due to residual conductive material.
  • the conductive structure DW and the second booster body DB are completely located in the partition groove BG, and the size of the conductive structure DW is smaller than the second booster body DB.
  • the conductive layer FSW includes a conductive material located between the edge of the second boosting body DB and the edge of the partition groove BG in the partition groove BG, and the conductive material is in contact with the partition groove BG.
  • the conductive structure DW is disconnected.
  • preparing the organic thin film layer ORG and the conductive layer FSW is part of preparing the electrode composite layer F200.
  • the electrode composite layer F200 is prepared on the side of the driving circuit layer F100 away from the base substrate BP.
  • the electrode composite layer F200 includes an organic thin film layer ORG and a conductive layer FSW located on the side of the organic thin film layer ORG away from the base substrate BP.
  • step S320 may include steps S331 to S335.
  • Step S331 see FIG. 42, an organic thin film layer ORG is formed on the side of the driving circuit layer F100 away from the base substrate BP; the organic thin film layer ORG has a partition groove BG in the peripheral area BB, and the third The second booster body DB and the conductive structure DW are at least partially exposed by the partition groove BG; and the portion of the conductive structure DW exposed by the partition groove BG is completely carried on the second booster body DB.
  • Step S332 see FIG. 43, a conductive material layer FSWA is formed on the side of the organic thin film layer ORG away from the base substrate BP, and the conductive material layer FSWA covers the organic thin film layer ORG and the partition groove BG. Among them, the conductive material layer FSWA covers the second booster body DB and the conductive structure DW in the partition groove BG.
  • Step S333 see FIG. 44, apply photoresist PR on the side of the conductive material layer FSWA away from the base substrate BP, and the photoresist PR fills the partition groove BG.
  • the thickness of the photoresist PR above the second raising body DB is reduced.
  • Step S334, see Figure 45 the photoresist PR is exposed and developed.
  • the thickness of the photoresist PR is reduced, so that it can be fully exposed, and residues are less likely to occur.
  • Step S335 Etch the conductive material layer FSWA to form a required structure to form the conductive layer FSW; then remove the photoresist.
  • the conductive material between the edge of the partition groove BG and the second boosting body DB was not fully etched due to the remaining photoresist blocking, which caused the gap between the edge of the partition groove BG and There is residual conductive material FSWR between the second raised bodies DB.
  • the remaining conductive material FSWR and the conductive structure DW are separated by the second raising body DB, thereby preventing the conductive structures DW from being short-circuited due to the remaining conductive material FSWR.
  • the preparation method shown in the following steps S410 to S450 can be used to prepare the array substrate ARR of the embodiment of the present disclosure.
  • Step S410 see Figures 49 to 51, an organic thin film layer ORG is prepared on one side of the base substrate BP, and the organic thin film layer ORG has a partition groove BG in the peripheral area BB.
  • Step S420 see Figures 49 to 51, a conductive material layer FSWA is prepared on the side of the organic film layer ORG away from the base substrate BP, and the conductive material layer FSWA covers the organic film layer ORG and the partition groove BG.
  • Step S430 see Figures 49 to 51, apply photoresist PR on the side of the conductive material layer FSWA away from the base substrate BP.
  • the photoresist PR covers the organic film layer ORG and fills the partition groove BG.
  • Step S440 see Figures 49 to 51, the photoresist PR is exposed, where the focus plane FF of the exposure machine is below the surface of the photoresist PR.
  • Step S450 Etch the conductive material layer FSWA, and then remove the photoresist.
  • the focus plane FF of the exposure machine is usually on the upper surface of the photoresist (the surface far away from the base substrate BP).
  • moving the focus plane FF of the exposure machine downward can increase the degree of exposure to the photoresist PR located at the bottom of the partition groove BG, thereby achieving the goal without increasing the exposure intensity (for example, increasing the exposure Under the condition of high light intensity or extended exposure time), the photoresist PR at the bottom of the partition groove BG is fully exposed, and the pattern of the superficial photoresist (such as the photoresist located on the organic film layer ORG) will not be affected. Negative Effects.
  • step S450 see FIG. 49, in the partition groove BG, the distance between the focus plane FF of the exposure machine and the bottom of the partition groove BG is not greater than half of the maximum thickness of the photoresist in the partition groove BG. , to ensure full exposure of the photoresist at the bottom of the partition groove BG.
  • step S450 see FIG. 50 or FIG. 51, in the partition groove BG, the focus plane FF of the exposure machine is near or below the bottom surface of the photoresist. This facilitates the design of the mask used for exposure.
  • the driving circuit layer F100 may be located on a side of the conductive material layer FSWA away from the base substrate BP, or between the conductive material layer FSWA and the base substrate BP, which is not specifically limited in this disclosure. In the examples of FIGS. 49 to 51 , the drive circuit layer F100 is located between the conductive material layer FSWA and the base substrate BP. Then, before step S410, the driving circuit layer F100 can also be prepared on the base substrate BP, and then the organic thin film layer ORG and the conductive material layer FSWA can be prepared on the side of the driving circuit layer F100 away from the base substrate BP.
  • the organic thin film layer ORG and the conductive material layer FSWA may be prepared first, for example, the pixel electrode or the common electrode of the array substrate ARR may be prepared first, and then the drive circuit layer F100 may be prepared.
  • the display panel PNL further includes a cover CF disposed opposite the array substrate ARR, and a sealing frame disposed between the array substrate ARR and the cover CF. glue; the frame sealing glue covers the partition groove BG; the drive circuit layer F100 has conductive traces overlapping with the frame sealant in the peripheral area BB, and the conductive traces are designed in a grid.
  • An embodiment of the present disclosure also provides a display device, which includes any of the display panels described in the above display panel embodiments.
  • the display device may be a smartphone screen, a smart watch screen, or other types of display devices. Since the display device has any of the display panels described in the above display panel embodiments, it has the same beneficial effects and will not be described in detail here.
  • the display panel PNL is a liquid crystal display panel
  • the display device further includes a backlight module BLU located on the backlight surface of the liquid crystal display panel.
  • the display device is a transmissive liquid crystal display device.

Abstract

显示面板(PNL)、阵列基板(ARR)及其制备方法，属于显示技术领域。阵列基板(ARR)包括依次层叠设置的衬底基板(BP)、驱动电路层(F100)、有机薄膜层(ORG)和导电层(FSW)；其中，驱动电路层(F100)在阵列基板(ARR)的外围区(BB)具有第一垫高体(DA)；第一垫高体(DA)包括位于源漏金属层(SD)和栅极层(GT)中至少一层的第一垫高金属块(DAC)和覆盖第一垫高金属块(DAC)的第一垫高绝缘层(DAI)；有机薄膜层(ORG)在外围区(BB)具有隔断槽(BG)，第一垫高体(DA)的一部分被有机薄膜层(ORG)覆盖且另外一部分被隔断槽(BG)暴露；导电层(FSW)具有跨过隔断槽(BG)边沿的信号走线(SW)，信号走线(SW)的边沿至少部分与第一垫高体(DA)交叠。阵列基板(ARR)能够减少隔断槽(BG)中的短路不良。

Description

显示面板、阵列基板及其制备方法 技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示面板、阵列基板及其制备方法。
背景技术
在显示面板中，有机薄膜层具有介电常数小、较强磨平性等特点，可以降低显示面板的功耗并利于提高显示的对比度，这使得有机薄膜层在显示面板中的应用越来越广泛。由于有机薄膜层具有较容易吸水的特点，因此在显示面板的外围区，有机薄膜层需要设置隔断槽。然而，当有机薄膜层上制备导电层时，显示面板在隔断槽内的短路不良高发。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服上述现有技术的不足，提供一种显示面板、阵列基板及其制备方法，减少隔断槽内的短路不良。
根据本公开的第一个方面，提供一种阵列基板，包括依次层叠设置的衬底基板、驱动电路层、有机薄膜层和导电层；
其中，所述驱动电路层在所述阵列基板的外围区具有第一垫高体；所述第一垫高体包括位于源漏金属层和栅极层中至少一层的第一垫高金属块和覆盖所述第一垫高金属块的第一垫高绝缘层；
所述有机薄膜层在所述外围区具有隔断槽，所述第一垫高体的一部分被所述有机薄膜层覆盖且另外一部分被所述隔断槽暴露；
所述导电层具有跨过所述隔断槽边沿的信号走线，所述信号走线的边沿至少部分与所述第一垫高体交叠。
根据本公开的一种实施方式，在所述隔断槽的至少部分区域，所述隔断槽的两个边沿分别设置有多个所述第一垫高体；
同一所述信号走线的两个边沿分别与相邻的两个第一垫高体交叠设置，且所述信号走线覆盖相邻两个所述第一垫高体之间的间隙。
根据本公开的一种实施方式，在所述隔断槽的至少部分区域，所述隔断槽的两个边沿分别设置有一个所述第一垫高体；所述信号走线与所述第一垫高体交叉设置。
根据本公开的一种实施方式，在所述隔断槽的至少部分区域，所述第一垫高体的数量为多个；任意一个所述第一垫高体的两端分别被所述隔断槽两侧的所述有机薄膜层覆盖；至少部分所述信号走线的两个边沿分别与相邻的两个所述第一垫高体交叠设置，且所述信号走线覆盖相邻两个所述第一垫高体之间的间隙。
根据本公开的一种实施方式，在所述隔断槽的至少部分区域，所述第一垫高体的数量为一个且两侧分别被所述隔断槽两侧的所述有机薄膜层覆盖；至少部分所述信号走线在所述隔断槽底面的部分承载于所述第一垫高体。
根据本公开的一种实施方式，所述驱动电路层在所述外围区设置有接地走线，所述接地走线与所述隔断槽至少部分交叠；
至少部分所述第一垫高金属块，为所述接地走线的一部分。
根据本公开的一种实施方式，所述驱动电路层在所述外围区设置有接地走线，所述接地走线与所述隔断槽至少部分交叠；
所述信号走线跨过所述隔断槽的边沿的位置，与所述接地走线不交叠。
根据本公开的一种实施方式，沿垂直于所述隔断槽的延伸方向，所述第一垫高体被所述有机薄膜层覆盖的部分的尺寸不小于2微米。
根据本公开的一种实施方式，所述第一垫高体凸出于所述隔断槽的槽底的高度，不小于所述隔断槽的深度的10％。
根据本公开的第二个方面，提供一种阵列基板的制备方法，包括：
在衬底基板的一侧形成驱动电路层，所述驱动电路层在所述阵列基板的外围区具有第一垫高体；所述第一垫高体包括位于源漏金属层和栅极层中至少一层的第一垫高金属块和覆盖所述第一垫高金属块的第一垫高绝缘层；
在所述驱动电路层远离所述衬底基板的一侧依次形成有机薄膜层和 导电层；所述有机薄膜层在所述外围区具有隔断槽，所述第一垫高体的一部分被所述有机薄膜层覆盖且另外一部分被所述隔断槽暴露；所述导电层具有跨过所述隔断槽边沿的信号走线，所述信号走线的边沿至少部分与所述第一垫高体交叠。
根据本公开的一种实施方式，在所述隔断槽的至少部分区域，所述隔断槽的两个边沿分别设置有多个所述第一垫高体；
同一所述信号走线的两个边沿分别与相邻的两个第一垫高体交叠设置，且所述信号走线覆盖相邻两个所述第一垫高体之间的间隙。
根据本公开的一种实施方式，在所述隔断槽的至少部分区域，所述隔断槽的两个边沿分别设置有一个所述第一垫高体；所述信号走线与所述第一垫高体交叉设置。
根据本公开的一种实施方式，在所述隔断槽的至少部分区域，所述第一垫高体的数量为多个；任意一个所述第一垫高体的两端分别被所述隔断槽两侧的所述有机薄膜层覆盖；至少部分所述信号走线的两个边沿分别与相邻的两个所述第一垫高体交叠设置，且所述信号走线覆盖相邻两个所述第一垫高体之间的间隙。
根据本公开的一种实施方式，在所述隔断槽的至少部分区域，所述第一垫高体的数量为一个且两侧分别被所述隔断槽两侧的所述有机薄膜层覆盖；至少部分所述信号走线在所述隔断槽底面的部分承载于所述第一垫高体。
根据本公开的第三个方面，提供一种阵列基板，包括依次层叠设置的衬底基板、驱动电路层、有机薄膜层和导电层；
其中，所述驱动电路层在所述阵列基板的外围区具有转接走线，所述转接走线位于源漏金属层和栅极层的至少一层；
所述有机薄膜层在所述外围区具有隔断槽和暴露所述转接走线的过孔；至少部分所述转接走线跨过所述隔断槽；所述导电层具有被所述隔断槽的边沿隔断的信号走线，所述信号走线相邻的两端之间通过所述转接走线电连接；所述信号走线与所述转接走线之间通过所述过孔连接。
根据本公开的一种实施方式，至少部分所述转接走线跨过所述隔断槽，且两端分别被所述过孔暴露；
至少部分所述信号走线被所述隔断槽隔断，所述信号走线的相邻两端分别通过所述过孔与所述转接走线的两端连接。
根据本公开的一种实施方式，所述导电层在所述隔断槽内还包括，位于所述隔断槽边沿的导电材料，所述导电材料与所述信号走线之间断路。
根据本公开的第四个方面，提供一种阵列基板的制备方法，包括：
在衬底基板的一侧形成驱动电路层，所述驱动电路层在所述阵列基板的外围区具有转接走线，所述转接走线位于源漏金属层和栅极层中的至少一层；
在所述驱动电路层远离所述衬底基板的一侧依次形成有机薄膜层和导电层；所述有机薄膜层在所述外围区具有隔断槽和暴露所述转接走线的过孔；至少部分所述转接走线跨过所述隔断槽；所述导电层具有被所述隔断槽的边沿隔断的信号走线，所述信号走线相邻的两端之间通过所述转接走线电连接；所述信号走线与所述转接走线之间通过所述过孔连接。
根据本公开的第五个方面，提供一种阵列基板，包括依次层叠设置的衬底基板、驱动电路层、有机薄膜层和导电层；
其中，所述驱动电路层在所述阵列基板的外围区具有第二垫高体和导电结构；所述第二垫高体包括位于栅极层的第二垫高金属块和覆盖所述第二垫高金属块的第二垫高绝缘层；所述导电结构位于所述第二垫高体远离所述衬底基板的一侧且至少部分与所述第二垫高体交叠；
所述有机薄膜层在所述外围区具有隔断槽，所述第二垫高体和所述导电结构至少部分被所述隔断槽暴露；且所述导电结构被所述隔断槽暴露的部分完全承载于所述第二垫高体上。
根据本公开的一种实施方式，所述导电结构被所述隔断槽暴露的部分的边缘，与所述第二垫高体的边缘之间具有间隙。
根据本公开的一种实施方式，所述导电层在所述隔断槽内包括，位于所述第二垫高体的边沿与所述隔断槽的边沿之间的导电材料，所述导电材料与所述导电结构断路。
根据本公开的第六个方面，提供一种阵列基板的制备方法，包括：
在衬底基板的一侧形成驱动电路层，所述驱动电路层在所述阵列基板的外围区具有第二垫高体和导电结构；所述第二垫高体包括位于栅极层的 第二垫高金属块和覆盖所述第二垫高金属块的第二垫高绝缘层；所述导电结构位于所述第二垫高体远离所述衬底基板的一侧且至少部分与所述第二垫高体交叠；
在所述驱动电路层远离所述衬底基板的一侧依次形成有机薄膜层和导电层；所述有机薄膜层在所述外围区具有隔断槽，所述第二垫高体和所述导电结构至少部分被所述隔断槽暴露；且所述导电结构被所述隔断槽暴露的部分完全承载于所述第二垫高体上。
根据本公开的一种实施方式，所述导电结构被所述隔断槽暴露的部分的边缘，与所述第二垫高体的边缘之间具有间隙。
根据本公开的第七个方面，提供一种阵列基板的制备方法，包括：
在衬底基板的一侧形成有机薄膜层，所述有机薄膜层在所述外围区具有隔断槽；
在所述有机薄膜层远离所述衬底基板的一侧形成导电材料层，所述导电材料层覆盖所述有机薄膜层和所述隔断槽；
在所述导电材料层远离所述衬底基板的一侧涂覆光刻胶，所述光刻胶覆盖所述有机薄膜层并填充所述隔断槽；
对所述光刻胶进行曝光，其中，曝光机的聚焦平面在光刻胶的表面以下；
对所述导电材料层进行刻蚀，然后去除光刻胶。
根据本公开的第八个方面，提供一种显示面板，包括上述的阵列基板。
根据本公开的一种实施方式，所述显示面板还包括与所述阵列基板对盒设置的盖板，以及设于所述阵列基板和所述盖板之间的封框胶；所述封框胶覆盖所述隔断槽；
所述驱动电路层在所述外围区具有与所述封框胶交叠的导电走线，所述导电走线网格化设计。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合 本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一种实施方式中，显示面板的剖视结构示意图。
图2-1为本公开一种实施方式中，显示面板的俯视结构示意图。
图2-2为本公开一种实施方式中，显示面板的俯视结构示意图。
图2-3为本公开一种实施方式中，显示面板的俯视结构示意图。
图3为本公开一种实施方式中，阵列基板的剖视结构示意图。
图4为本公开一种实施方式中，阵列基板的剖视结构示意图。
图5为本公开一种实施方式中，阵列基板的局部结构示意图。
图6-1为本公开一种实施方式中，阵列基板在顶角处的局部结构示意图。
图6-2为本公开一种实施方式中，阵列基板的复合电极层的子结构的示意图。
图7为本公开一种实施方式中，阵列基板的有机薄膜层和信号走线的俯视结构示意图。
图8为相关技术中，在驱动电路层上形成有机薄膜层的结构示意图。
图9为相关技术中，在有机薄膜层上形成导电材料层的结构示意图。
图10为相关技术中，涂覆光刻胶的结构示意图。
图11为相关技术中，隔断槽内光刻胶曝光不充分的结构示意图。
图12为相关技术中，隔断槽内导电材料层刻蚀不充分的结构示意图。
图13为本公开一种实施方式中，阵列基板的制备方法的流程示意图。
图14为本公开一种实施方式中，形成具有第一垫高体的驱动电路层的结构示意图。
图15为本公开一种实施方式中，在驱动电路层远离衬底基板的一侧形成有机薄膜层的结构示意图。
图16为本公开一种实施方式中，在有机薄膜层上形成导电材料层的结构示意图。
图17为本公开一种实施方式中，在导电材料层远离衬底基板的一侧 涂覆光刻胶结构示意图。
图18为本公开一种实施方式中，信号走线、有机薄膜层和第一垫高体的相对位置关系的结构示意图。
图19为图18的M1-M1’处的剖切结构示意图。
图20为图18的N1-N1’处的剖切结构示意图。
图21为本公开一种实施方式中，信号走线、有机薄膜层和第一垫高体的相对位置关系的结构示意图。
图22为图21的M2-M2’处的剖切结构示意图。
图23为图21的N2-N2’处的剖切结构示意图。
图24为本公开一种实施方式中，信号走线、有机薄膜层和第一垫高体的相对位置关系的结构示意图。
图25为图24的M3-M3’处的剖切结构示意图。
图26为图24的N3-N3’处的剖切结构示意图。
图27为本公开一种实施方式中，信号走线、有机薄膜层和第一垫高体的相对位置关系的结构示意图。
图28为图27的M4-M4’处的剖切结构示意图。
图29为图27的N4-N4’处的剖切结构示意图。
图30为本公开一种实施方式中，阵列基板的制备方法的流程示意图。
图31为本公开一种实施方式中，在驱动电路层远离衬底基板的一侧形成有机材料层的结构示意图。
图32为本公开一种实施方式中，对有机材料层和转接绝缘层进行图案化并形成过孔和隔断槽的结构示意图。
图33为本公开一种实施方式中，转接走线、有机薄膜层、隔断槽和过孔的相对位置关系的结构示意图。
图34为本公开一种实施方式中，在有机薄膜层上形成导电材料层的结构示意图。
图35为本公开一种实施方式中，对导电材料层进行图案化操作的结构示意图。
图36为本公开一种实施方式中，信号走线、转接走线、有机薄膜层、隔断槽和过孔的相对位置关系的结构示意图。
图37-1为相关技术中，在驱动电路层上形成有机薄膜层的结构示意图；驱动电路层具有被隔断槽暴露至少部分的导电结构。
图37-2为相关技术中，在有机薄膜层上形成导电材料层的结构示意图。
图38为相关技术中，涂覆光刻胶的结构示意图。
图39为相关技术中，隔断槽内光刻胶曝光不充分的结构示意图。
图40为相关技术中，隔断槽内导电材料层刻蚀不充分而导致导电结构间短路的结构示意图。
图41为本公开一种实施方式中，阵列基板的制备方法的流程示意图。
图42为本公开一种实施方式中，形成驱动电路层和有机薄膜层的结构示意图，其中，驱动电路层具有第二垫高体和导电结构。
图43为本公开一种实施方式中，在有机薄膜层上形成导电材料层的结构示意图。
图44为本公开一种实施方式中，在导电材料层远离衬底基板的一侧涂覆光刻胶结构示意图。
图45为本公开一种实施方式中，隔断槽内的光刻胶曝光不充分的结构示意图。
图46为本公开一种实施方式中，隔断槽内的导电材料层刻蚀不充分的结构示意图；残留的导电材料不与导电结构连接。
图47为相关技术中，曝光时的聚焦平面位于光刻胶表面的结构示意图。
图48为本公开一种实施方式中，阵列基板的制备方法的流程示意图。
图49为本公开一种实施方式中，曝光时的聚焦平面位于光刻胶内部的结构示意图。
图50为本公开一种实施方式中，曝光时的聚焦平面位于光刻胶下表面的结构示意图。
图51为本公开一种实施方式中，曝光时的聚焦平面位于光刻胶下表面以下的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
本公开实施方式提供显示面板的阵列基板及其制备方法，来避免或者降低隔断槽内的短路不良。
参见图1，从层叠结构上看，本公开实施方式中的显示面板PNL可以包括依次层叠设置的阵列基板ARR、胶层EA和盖板CF。参加图2-1～图2-3，从平面结构的角度看，阵列基板ARR包括用于显示的显示区AA和围绕显示区AA的外围区BB。有机薄膜层ORG设置于阵列基板ARR且在外围区BB设置有朝向盖板CF方向开口的隔断槽BG。胶层EA填充隔断槽BG，一方面阻断水汽入侵路线，另一方面提高胶层EA与阵列基板ARR之间的附着力。
示例性的，参见图1，显示面板PNL为液晶显示面板。液晶显示面板的彩膜基板可以作为盖板CF，液晶显示面板的封框胶可以作为胶层EA；在彩膜基板和阵列基板ARR之间，具有封框胶围绕出的液晶盒，液晶盒 内填充有液晶LC。阵列基板ARR上的有机薄膜层ORG在外围区BB设置隔断槽BG；阵列基板ARR与彩膜基板通过封框胶进行对盒连接时，封框胶可以填充满隔断槽BG。这样一方面可以阻断水汽进入的路径，另一方面可以增大阵列基板ARR与封框胶之间的结合面积，进而提高了阵列基板ARR与封框胶之间的附着力，克服了因有机薄膜层ORG而导致阵列基板ARR与封框胶之间容易剥离的问题。
当然的，本公开的显示面板PNL也可以为其他类型的显示面板，例如为具有自发光元件的显示面板，发光元件以及驱动发光元件的像素驱动电路可以设置在该显示面板PNL的阵列基板ARR。在阵列基板ARR的出光侧，可以通过封框胶或者光学胶贴附透光盖板CF，例如贴附玻璃盖板。示例性的，该显示面板PNL也可以为OLED(有机电致发光二极管)显示面板、PLED(高分子有机电致发光二极管)显示面板、Micro LED(微发光二极管)显示面板、QD-OLED(量子点-有机电致发光二极管)显示面板、QLED(量子点发光二极管)显示面板或者其他类型的自发光显示面板。
参见图3和图4，在一些实施方式中，本公开的阵列基板ARR可以包括依次层叠设置的衬底基板BP、驱动电路层F100和电极复合层F200。电极复合层F200中设置有像素电极，驱动电路层F100中设置有用于驱动像素电极的像素驱动电路。在自发光显示面板中，阵列基板ARR的发光元件可以设置于电极复合层F200，亦或阵列基板ARR的电极复合层F200作为发光元件层的一部分。在本公开实施方式中，仅以显示面板PNL为液晶显示面板作为具体示例，来对本公开的显示面板PNL的结构和制备方法做示例性说明。可以理解的是，本公开实施方式对显示面板的结构和制备方法的示例性说明中所采用的技术手段和所能够达成的效果，可以直接或者经过合理变形后应用于自发光显示面板的阵列基板中。
在本公开实施方式的显示面板PNL中，阵列基板ARR的电极复合层F200至少包括一层电极层，且至少有一层电极层作为像素电极层。该像素电极层设置有显示面板PNL的像素电极。显示面板PNL的公共电极层可以设置于阵列基板ARR，也可以设置于盖板CF。
在一种实施方式中，参见图4，阵列基板ARR的电极复合层F200可 以包括层叠设置的两层电极层(即第一电极层PA1和第二电极层PA2)。举例而言，参见图4，阵列基板ARR的电极复合层F200包括依次层叠设于驱动电路层F100远离衬底基板BP一侧的第一平坦化层PLN1(采用有机材料)、第一电极层PA1、绝缘介质层和第二电极层PA2。绝缘介质层可以为无机介质层，也可以为有机介质层，或者可以为有机介质层和无机介质层的复合层叠结构。作为一种示例，参见图4，绝缘介质层包括第二平坦化层PLN2(采用有机材料)。第二平坦化层PLN2可以直接设置于第一电极层PA1远离衬底基板BP的表面，或者第二平坦化层PLN2与第一电极层PA1之间设置有无机介质层。
第一电极层PA1和第二电极层PA2中的一个为设置有公共电极的公共电极层，另一个为设置有像素电极的像素电极层。其中，公共电极和像素电极可以各自独立的为板状电极或者镂空电极(例如狭缝电极)。
示例性地，在本公开的一种实施方式中，参见图4，第一电极层PA1作为像素电极层，其设置的像素电极为板状电极。第二电极层PA2为公共电极层，其设置的公共电极为镂空电极。
本公开实施方式的阵列基板ARR中，第一电极层PA1和第二电极层PA2中的至少一层为透明电极层，例如为透明的金属电极层(例如镁银合金层、铝银合金层等)或者透明金属氧化物电极层(例如氧化铟锡层)。在一种示例中，第一电极层PA1和第二电极层PA2均为透明电极层，例如第一电极层PA1和第二电极层PA2的材料均为氧化铟锡(ITO)。
在另一种实施方式中，参见图3，阵列基板ARR的电极复合层F200可以包括一层电极层，即仅设置第一电极层PA1。举例而言，参见图3，阵列基板ARR的电极复合层F200包括依次层叠设于驱动电路层F100远离衬底基板BP一侧的第一平坦化层PLN1和第一电极层PA1。第一电极层PA1作为像素电极层而设置有像素电极。
在本公开的一些实施方式中，电极复合层F200还包括取向层，以用于控制液晶分子的预倾角。
在本公开的一些实施方式中，电极复合层F200还包括支撑柱层，支撑柱层形成有多个支撑柱，以提高液晶盒的盒厚稳定性。
在本公开实施方式的显示面板PNL中，衬底基板BP可以为无机材料 的衬底基板BP，也可以为有机材料的衬底基板BP。举例而言，在本公开的一种实施方式中，衬底基板BP的材料可以为钠钙玻璃(soda-lime glass)、石英玻璃、蓝宝石玻璃等玻璃材料，或者可以为不锈钢、铝、镍等金属材料。在本公开的另一种实施方式中，衬底基板BP的材料可以为聚甲基丙烯酸甲酯(Polymethyl methacrylate，PMMA)、聚乙烯醇(Polyvinyl alcohol，PVA)、聚乙烯基苯酚(Polyvinyl phenol，PVP)、聚醚砜(Polyether sulfone，PES)、聚酰亚胺、聚酰胺、聚缩醛、聚碳酸酯(Poly carbonate，PC)、聚对苯二甲酸乙二酯(Polyethylene terephthalate，PET)、聚萘二甲酸乙二酯(Polyethylene naphthalate，PEN)或其组合。当然的，在本公开的其他实施方式中，例如在自发光显示面板PNL中，衬底基板BP也可以为柔性衬底基板BP，例如衬底基板BP的材料可以为聚酰亚胺(polyimide，PI)。衬底基板BP还可以为多层材料的复合，举例而言，在本公开的一种实施方式中，衬底基板BP可以包括依次层叠设置的底膜层(Bottom Film)、压敏胶层、第一聚酰亚胺层和第二聚酰亚胺层。可以理解的是，当本公开实施方式示例的液晶显示面板PNL为透射式液晶显示面板PNL时，衬底基板BP采用透明材料。
本公开实施方式的阵列基板ARR的驱动电路层F100设置有用于驱动子像素的像素电极的像素驱动电路。在驱动电路层中，任意一个像素驱动电路可以包括有晶体管。进一步地，参见图3和图4，晶体管可以为薄膜晶体管，薄膜晶体管可以选自顶栅型薄膜晶体管、底栅型薄膜晶体管或者双栅型薄膜晶体管；薄膜晶体管的有源层的材料可以为非晶硅半导体材料、低温多晶硅半导体材料、金属氧化物半导体材料、有机半导体材料或者其他类型的半导体材料；薄膜晶体管可以为N型薄膜晶体管或者P型薄膜晶体管。在该示例中，像素驱动电路可以为一个开关晶体管F100M。
可选地，参见图3和图4，驱动电路层可以包括层叠于衬底基板BP和电极复合层F200之间的半导体层SEMI、栅极绝缘层GI、栅极层GT、层间电介质层ILD和源漏金属层SD等。开关晶体管可以由半导体层SEMI、栅极绝缘层GI、栅极层GT、层间电介质层ILD、源漏金属层SD等膜层形成。其中，各个膜层的位置关系可以根据薄膜晶体管的膜层结构确定。在一种示例中，驱动电路层可以包括依次层叠设置的半导体层SEMI、栅 极绝缘层GI、栅极层GT、层间电介质层ILD和源漏金属层SD，如此所形成的开关晶体管为顶栅型薄膜晶体管。在另一种示例中，在驱动电路层可以包括依次层叠设置的栅极层GT、栅极绝缘层GI、半导体层SEMI、层间电介质层ILD和源漏金属层SD，如此所形成的薄膜晶体管为底栅型薄膜晶体管。
在一种示例中，栅极层GT的厚度可以在0.1～1微米之间，例如在0.3～0.5微米之间。栅极层GT可以为一层金属层(例如铜层)，也可以包括依次层叠的多层金属层(例如Ti/Al/Ti、Mo/Cu/Mo等)，这些金属层中可以包括有合金层，例如MoNi合金层等。当然的，在一些示例中，栅极层GT还可以具有导电的非金属层，例如具有TiN层。
在一种示例中，源漏金属层SD的厚度可以在0.1～1微米之间，例如在0.3～0.5微米之间。源漏金属层SD可以为一层金属层(例如铜层)，也可以包括依次层叠的多层金属层(例如Ti/Al/Ti、Mo/Cu/Mo等)，这些金属层中可以包括有合金层，例如MoNi合金层等。当然的，在一些示例中，栅极层GT还可以具有导电的非金属层，例如具有TiN层。
在一些实施方式中，参见图5，驱动电路层可以设置有多条数据电压走线DataW，数据电压走线DataW可以整体上沿列方向延伸，其可以为直线延伸，也可以为在行方向上往复弯折的折线。进一步的，数据电压走线DataW可以设置于源漏金属层。
参见图5，栅极层GT设置有多条扫描走线GTW。在该示例中，开关晶体管F100M的一端连接数据电压走线DataW，开关晶体管的另一端连接像素电极PIXP，开关晶体管的栅极连接扫描走线GTW。在扫描走线GTW上加载的扫描电压的控制下，开关晶体管F100M可以导通，以使得数据电压走线DataW上的数据电压加载至像素电极。
扫描走线GTW可以在整体上沿行方向延伸。扫描走线GTW可以为沿行方向的直线引线，也可以为在列方向往复弯折的折线。扫描走线GTW和数据电压走线DataW可以限定出多个像素区域，像素电极和开关晶体管可以布设于该像素区域内。
在一些实施方式中，参见图3和图4，开关晶体管F100M的有源层设置于半导体层SEMI。开关晶体管的有源层可以包括依次连接的源极接触 区、沟道区和漏极接触区，源极接触区与数据电压走线DataW通过过孔连接，漏极接触区与像素电极通过过孔连接。在一种示例中，扫描走线GTW与开关晶体管的沟道区交叠，以使得扫描走线GTW与开关晶体管的沟道区交叠的部分可以作为开关晶体管的栅极。在另一些示例中，开关晶体管为底栅型薄膜晶体管，扫描走线GTW与开关晶体管的沟道区交叠的部分，其尺寸可以局部增大，以使得扫描走线GTW完全遮挡开关晶体管的沟道区，避免光线从衬底基板BP一侧照射至开关晶体管的沟道区而导致开关晶体管的特性改变(例如漏电流增大)。
在一些实施方式中，参见图5，阵列基板ARR的电极复合层F200还包括公共电极层，公共电极层设置有公共电极COMP和连接相邻公共电极COMP的公共电极走线COMW。当然的，在本公开的其他实施方式中，公共电极走线COMW也可以设置于其他膜层，例如设置于栅极层GT。
在一些示例中，驱动电路层还可以包括钝化层，钝化层设置于源漏金属层SD远离衬底基板BP的一侧，以用于保护源漏金属层SD。
在一些示例中，驱动电路层还可以包括无机缓冲层Buff，无机缓冲层Buff设置于衬底基板BP表面，栅极层GT、半导体层SEMI和源漏金属层SD等设置于无机缓冲层Buff远离衬底基板BP的一侧。
在该示例性的阵列基板ARR中，无机缓冲层Buff、钝化层、层间电介质层ILD和栅极绝缘层GI的材料可以为氧化硅、氮化硅、氮氧化硅等电介质材料。举例而言，钝化层和层间电介质层ILD的材料为氮化硅，无机缓冲层Buff和栅极绝缘层GI的材料为氧化硅。
在本公开的另外一些实施方式中，阵列基板可以包括依次层叠设置的衬底基板BP、电极复合层F200和驱动电路层F100，或者驱动电路层F100和电极复合层F200相互混合，再或者驱动电路层F100夹设于电极复合层F200之间。举例而言，阵列基板ARR包括依次层叠设置的衬底基板BP、第一电极层PA1和栅极层GT、栅极绝缘层GI、半导体层SEMI、源漏金属层SD、平坦化层PLN和第二电极层PA2。其中，第一电极层PA1和栅极层GT在膜层位置上相同且采用不同材料，为相互嵌套的两层；第一电极层PA1和第二电极层PA2作为电极复合层F200的两个电极层，半导体层SEMI、源漏金属层SD、栅极层GT等作为驱动电路层F100的膜层。 在本公开中，阵列基板ARR的这些可能的层叠方式，均适用于本公开的阵列基板ARR的制备方法。
参见图6-2，在本公开实施方式的阵列基板ARR中，电极复合层F200具有由有机薄膜层ORG和位于有机薄膜层ORG远离衬底基板BP一侧的导电层FSW组成的子结构。举例而言，在一种示例中，阵列基板ARR的电极复合层F200包括依次层叠设置第一平坦化层PLN1和第一电极层PA1，则第一平坦化层PLN1和第一电极层PA1可以组成一个子结构。在该子结构中，第一平坦化层PLN1作为有机薄膜层ORG，第一电极层PA1作为导电层FSW。再举例而言，显示面板PNL包括依次层叠设置第一平坦化层PLN1、第一电极层PA1、第二平坦化层PLN2和第二电极层PA2，则第二平坦化层PLN2和第二电极层PA2可以组成一个子结构。在该子结构中，第二平坦化层PLN2作为有机薄膜层ORG，第二电极层PA2作为导电层FSW。当然的，在该示例中，第一平坦化层PLN1和第一电极层PA1也可以组成一个子结构。再举例而言，电极复合层F200在源漏金属层SD远离衬底基板BP的一侧设置有平坦化层PLN和第二电极层PA2，则平坦化层PLN可以作为有机薄膜层ORG，且第二电极层PA2可以作为导电层FSW。
在本公开的一些实施方式中，有机薄膜层ORG的厚度可以在0.5～5微米之间，例如在1.5～3微米之间。
在本公开的一些实施方式中，有机薄膜层ORG上形成的隔断槽BG的宽度可以在10～200微米之间。
在本公开的一些实施方式中，隔断槽BG设置于阵列基板ARR的外围区BB，且环绕显示区AA设置，例如设置于显示面板PNL用于涂覆封框胶的涂胶区。
在一种示例中，参见图2-2和图2-3隔断槽BG的数量为多条，至少部分隔断槽BG依次环绕显示区AA设置。进一步的，在不同的位置，隔断槽BG的数量可以相同或者不相同。举例而言，参见图6-1，在阵列基板ARR的拐角处，隔断槽BG的数量为四个，且在非拐角处隔断槽BG的数量为两条。这样，可以提高拐角处的封框强度，避免显示装置在拐角处出现穿刺等不良。
在一种示例中，参见图2-3，至少部分隔断槽BG可以不连续设计，即隔断槽BG可以包括多个隔断子槽。
另外一种示例中，参见图2-1和图2-3，至少一个隔断槽BG连续设置，即隔断槽呈连续的环形。
当然的，在本公开的其他实施方式中，如图2-1所示，阵列基板ARR的隔断槽的数量也可以为一个。
在一种示例中，在至少部分区域，相邻两条隔断槽BG之间设置有沟槽，以使得相邻两条隔断槽BG相互连通。
在一种示例中，沿阵列基板ARR的法线方向，隔断槽BG贯穿有机薄膜层ORG。
在本公开的一些实施方式中，参见图6-1，导电层FSW可以形成有跨过隔断槽BG的边沿的信号走线SW，例如至少一个信号走线SW跨过隔断槽BG相对的两个侧壁(即有机薄膜层ORG的侧壁)，或者至少一个信号走线SW跨过隔断槽BG的一个侧壁后在隔断槽BG内继续走线或者截止。
作为一种示例，信号走线SW可以为用于传输时钟信号的时钟走线。当然的，信号走线SW还可以传输其他信号。
在一种示例中，至少部分信号走线SW的宽度为10～20微米，至少部分信号走线SW之间的间隙为10～20微米。当然的，在本公开的其他示例中，信号走线SW的宽度以及信号走线SW之间的间隙可以根据需要设置。例如，至少信号走线SW的宽度可以减小至3～10微米，或者至少部分信号走线SW之间的间隙可以减小至3～10微米。
可以理解的是，由于制备工艺误差、光刻工艺中不同厚度的光刻胶在相同曝光下呈现的图案差异等原因，同一信号走线SW在不同位置的宽度可以存在差异。举例而言，信号走线SW在有机薄膜层ORG侧壁上的宽度可以小于信号走线SW在隔断槽BG的槽底的宽度。
在一些实施方式中，驱动电路层在外围区BB设置有接地走线。在与封框胶交叠的区域，接地走线网格设计，以提高接地走线的透光率，利于封框胶的固化。进一步的，在接地走线不与封框胶交叠的区域，接地走线可以不采用镂空设计，即采用整面结构，以降低接地走线的阻抗。
参见图7，在相关技术中，信号走线SW在穿过隔断槽BG的边沿时，相邻两个信号走线SW之间容易发生短路不良。对该类不良进行解析，发现在隔断槽BG的边沿区域SA，相邻信号走线SW之间残留有导电材料。对相关技术中阵列基板ARR的制备过程进行了追溯。参见图8～图12，相关技术中的阵列基板ARR采用如下步骤S011～S015所示的方法进行制备。
步骤S011，参见图8，依次制备衬底基板BP、驱动电路层F100和有机薄膜层ORG，有机薄膜层ORG设置有隔断槽BG。步骤S012，参见图9，在有机薄膜层ORG远离衬底基板BP的表面形成导电材料层FSWA。然后，参见图10～图12，采用光刻工艺，对导电材料层FSWA进行图案化操作。具体的，在步骤S013中，参见图10，在导电材料层FSWA远离衬底基板BP的一侧填充光刻胶PR。其中，光刻胶PR填充隔断槽BG；因光刻胶的流动性，光刻胶PR在隔断槽BG的边沿区域SA的厚度最大。在步骤S014中，参见图11，对光刻胶PR进行曝光和显影。在隔断槽BG的边沿区域SA，光刻胶PR不能充分曝光而导致残留，残留的光刻胶PRR会对下方(靠近衬底基板BP的一侧)的导电材料层FSWA构成遮挡和保护。在步骤S015中，参见图12，在通过刻蚀对导电材料层FSWA进行图案化时，被残留的光刻胶PRR遮挡的导电材料可能无法充分刻蚀而残留，残留的导电材料FSWR可能会导致相邻的两个信号走线SW之间短路。在本公开中，残留的光刻胶PRR是指，预期被曝光并显影去除的光刻胶因未能充分曝光和显影而残留的部分。按照工艺预期不被显影并保留的部分(即作为后续刻蚀的掩膜版的部分)，是正常保留的光刻胶而非残留的光刻胶PRR。
发明人尝试通过过曝光的方案来消除光刻胶残留以降低短路不良，但是发现这会较大幅度的延长曝光时间进而影响曝光节拍，对产能影响较大，增大了阵列基板ARR的成本。另外，发明人还发现，随着信号走线SW的宽度和间距越来越小，过曝光的方案受到曝光机工艺能力的制约越来越大。
为了解决此类短路不良，参见图13，在本公开实施方式提供的第一种解决方案中，可以采用如下步骤S110～步骤S120所示的制备方法，来制备本公开实施方式的阵列基板ARR。
步骤S110，参见图14，在衬底基板BP的一侧形成驱动电路层F100，所述驱动电路层F100在所述阵列基板ARR的外围区BB具有第一垫高体DA；所述第一垫高体DA包括位于源漏金属层SD和栅极层GT中至少一层的第一垫高金属块DAC和覆盖所述第一垫高金属块DAC的第一垫高绝缘层DAI；
步骤S120，参见图15～图29，在所述驱动电路层F100远离所述衬底基板BP的一侧依次形成有机薄膜层ORG和导电层FSW。所述有机薄膜层ORG在所述外围区BB具有隔断槽BG，所述第一垫高体DA的一部分被所述有机薄膜层ORG覆盖且另外一部分被所述隔断槽BG暴露。这使得所述第一垫高体DA被暴露的部分形成凸出于所述隔断槽BG的槽底的垫高台阶DAS。所述导电层FSW具有跨过所述隔断槽BG边沿的信号走线SW，所述信号走线SW的边沿至少部分与所述第一垫高体DA交叠。换言之，所述信号走线SW的边沿至少部分承载于所述垫高台阶DAS。
在一种示例中，制备有机薄膜层ORG和导电层FSW为制备电极复合层F200的一部分。换言之，在步骤S120中，在驱动电路层F100远离衬底基板BP的一侧制备电极复合层F200。所述电极复合层F200包括有机薄膜层ORG和位于有机薄膜层ORG远离衬底基板BP一侧的导电层FSW。
在一种示例中，步骤S120可以包括步骤S121～步骤S126。
步骤S121，参见图15，在驱动电路层F100远离衬底基板BP的一侧形成有机薄膜层ORG，有机薄膜层ORG在外围区BB具有隔断槽BG。其中，第一垫高体DA的一部分被有机薄膜层ORG覆盖，且另外一部分暴露于隔断槽BG中。换言之，第一垫高体DA位于隔断槽BG的下边沿(靠近衬底基板的边沿)。第一垫高体DA暴露于隔断槽BG的部分形成垫高台阶DAS。
步骤S122，参见图16，在有机薄膜层ORG远离衬底基板BP的一侧形成导电材料层FSWA，导电材料层FSWA覆盖有机薄膜层ORG和隔断槽BG。其中，导电材料层FSWA在隔断槽BG内覆盖垫高台阶DAS。
步骤S123，参见图17，在导电材料层FSWA远离衬底基板BP的一侧涂覆光刻胶PR，光刻胶PR填充隔断槽BG。参见图17，由于第一垫高体DA的抬高作用，光刻胶PR在垫高台阶DAS上方的厚度减小了。
步骤S124，对光刻胶PR进行曝光和显影。在隔断槽BG的边沿区域，被垫高台阶DAS抬高的部分的光刻胶PR的厚度减小因而可以被充分曝光，不易产生残留。
步骤S125，对导电材料层FSWA进行刻蚀以形成所需的结构，例如形成所需的信号走线SW。在该过程中，在隔断槽BG的边沿区域被垫高台阶DAS抬高的部分，导电材料因没有残留的光刻胶遮挡而能够被充分刻蚀，保证了信号走线SW图案的准确性，避免了信号走线SW之间残留的导电材料导致信号走线SW之间短路。
步骤S126，去除光刻胶PR。
在本公开实施方式提供的第一种解决方案中，可以通过对源漏金属层SD或者栅极层GT的掩膜版进行调整，在不增加任何工艺过程的情况下在驱动电路层F100上制备出第一垫高体DA。其中，第一垫高绝缘层DAI为位于第一垫高金属块DAC远离衬底基板BP一侧的无机材料层，其可以根据第一垫高金属块DAC的不同而不同。举例而言，在一种示例中，第一垫高金属块DAC位于源漏金属层SD且第一垫高绝缘层DAI位于钝化层。再举例而言，在另一种示例中，第一垫高金属块DAC位于栅极层GT，且第一垫高绝缘层DAI位于层间电介质层ILD和钝化层中的至少一层。再举例而言，在另一种示例中，第一垫高金属块DAC包括位于栅极层GT的底金属块和位于源漏金属层SD的顶金属块，顶金属块承载于底金属块上，例如两者的边缘齐平；这样，第一垫高金属块DAC可以具有更大的厚度，进而使得垫高台阶DAS与隔断槽BG的槽底的段差更大。
在对有机材料层进行图案化以形成有机薄膜层ORG和隔断槽BG时，使得有机薄膜层ORG覆盖第一垫高体DA的一部分且使得隔断槽BG暴露第一垫高体DA的一部分。这样，参见图15，第一垫高体DA形成与隔断槽BG的侧壁连接且凸出于隔断槽BG的槽底的垫高台阶DAS。参见图16，在形成导电材料层FSWA时，导电材料层FSWA覆盖该垫高台阶DAS，进而使得垫高台阶DAS上的导电材料层FSWA与有机薄膜层ORG的表面的段差更小。参见图17，在涂覆光刻胶PR后，相较于相关技术，垫高台阶DAS上的光刻胶厚度减小，在曝光和显影过程中不容易出现光刻胶残留。如此，相邻两个信号走线SW之间的间隙在垫高台阶DAS上的部分 不会出现导电材料的残留，消除了信号走线SW之间的短路不良。这样，参见图18、图21、图24和图27，在所形成的阵列基板ARR中，信号走线SW之间的间隙与第一垫高体DA交叠。
在一种实施方式中，在通过光刻工艺对导电材料层FSWA进行图案化时，曝光机的聚焦平面为光刻胶的上表面(远离衬底基板BP的表面)，或者在靠近光刻胶的上表面的位置(例如偏离上表面的高度不超过光刻胶最大厚度的10％)。
在一种实施方式中，垫高台阶DAS的高度不小于隔断槽BG的深度的10％，例如垫高台阶DAS的高度在隔断槽BG的深度的10％～40％范围内。例如垫高台阶DAS的高度在0.3～0.5微米之间，隔断槽BG的深度在1.5～3微米之间。其中，在本公开实施方式中，隔断槽BG的深度是指，隔断槽BG的底面(靠近衬底基板BP的底部表面)与隔断槽BG的顶开口(远离衬底基板BP的开口)之间的段差。在本公开实施方式中，垫高台阶DAS的高度是指，垫高台阶DAS的顶面(远离衬底基板BP的表面)与隔断槽BG的底面之间的段差。在本公开实施方式中，段差是指两个结构或者面与衬底基板BP之间的距离的距离差。在一种示例中，垫高台阶DAS的高度基本等于第一垫高金属块DAC的厚度。
在一种实施方式中，参见图19、图22、图24、图27，所述第一垫高体DA在所述衬底基板BP上的正投影与所述有机薄膜层ORG在所述衬底基板BP上的正投影的重合部分，在垂直于隔断槽BG下边沿的方向上的尺寸不小于2微米，尤其是不小于3微米，例如在3～5微米之间。如此，可以保证第一垫高体DA的至少部分被有机薄膜层ORG覆盖，进而使得第一垫高体DA的顶面与隔断槽BG的侧面连接，克服工艺波动、对准偏差等因素的影响。
在一种实施方式中，参见图18～图20，在所述隔断槽BG的至少部分区域，所述隔断槽BG的两个边沿分别设置有多个所述第一垫高体DA；同一所述信号走线SW的两个边沿分别与相邻的两个第一垫高体DA交叠设置，且所述信号走线SW覆盖相邻两个所述第一垫高体DA之间的间隙。这样，在至少部分区域，在隔断槽BG的同一下边沿处，至少一个信号走线SW的两个边沿分别与相邻的两个第一垫高体DA交叠设置。换言之， 至少两个第一垫高体DA之间具有间隙，且至少一个信号走线SW覆盖该间隙。这样，在对封框胶进行固化时，外部光线可以通过该间隙处照射封框胶，利于提高封框胶的固化速度，提高生产节拍并降低生产成本。
在一种示例中，参见图18～图20，在隔断槽BG的两个下边沿处分别设置多个第一垫高体DA。在隔断槽BG的任意一个下边沿处，相邻第一垫高体DA之间具有间隙；信号走线SW的两个边沿分别与相邻的两个第一垫高体DA交叠，且信号走线SW覆盖相邻两个第一垫高体DA之间的间隙。
进一步的，参见图18～图20，与同一信号走线SW交叠且分别位于隔断槽BG的相对的两个下边沿的第一垫高体DA之间不连接，即设置有间隙。换言之，第一垫高体DA仅仅设置于靠近隔断槽BG的下边沿位置，隔断槽BG的两个下边沿各自独立的设置第一垫高体DA。这样，隔断槽BG的两个下边沿之间具有不设置第一垫高体DA的间隙，这利于提高照射至封框胶的光线的强度，提高封框胶的固化速度。
在另一种实施方式中，参见图21～图23，在所述隔断槽BG的至少部分区域，所述隔断槽BG的两个边沿分别设置有一个所述第一垫高体DA；所述信号走线SW与所述第一垫高体DA交叉设置。
换言之，在至少部分区域，位于隔断槽BG同一下边沿的至少部分相邻的较小的第一垫高体DA可以依次连接，形成一个条形的第一垫高体DA。这样，至少一个信号走线SW与条形的第一垫高体DA交叉设置，该信号走线SW的两个边均与同一条形的第一垫高体DA交叠设置。这种设置方式，可以无需设置尺寸更小的第一垫高体DA而是直接设置条形的第一垫高体DA。这一方面可以简化显示面板PNL的设计和降低对掩膜版的尺寸要求；另一方面，克服了曝光精度、对准偏差等工艺因素对第一垫高体DA的尺寸的制约，提高了在不同尺寸的显示面板PNL上的适用范围。不仅如此，条形的第一垫高体DA的设置可以确保信号走线SW的边沿与第一垫高体DA交叠，避免了因工艺波动或者对准偏差等因素导致信号走线SW的边沿位于第一垫高体DA间隙，提高了工艺窗口并克服了可能的不良。
在一种示例中，参见图21～图23，在依次相邻的同一组信号走线SW 中，与该组信号走线SW交叠的且位于隔断槽BG同一下边沿的各个第一垫高体DA相互连接形成条形的第一垫高体DA；换言之，依次相邻的同一组信号走线SW均与同一条形的第一垫高体DA交叉设置。
进一步的，参见图21，相对设置的两个条形的第一垫高体DA之间具有间隙，以使得第一垫高体DA之间的间隙可以透光，利于提高封框胶的固化速度。
在另一种实施方式中，参见图24～图26，在所述隔断槽BG的至少部分区域，所述第一垫高体DA的数量为多个；任意一个所述第一垫高体DA的两端分别被所述隔断槽BG两侧的所述有机薄膜层ORG覆盖；至少部分所述信号走线SW的两个边沿分别与相邻的两个所述第一垫高体DA交叠设置，且所述信号走线SW覆盖相邻两个所述第一垫高体DA之间的间隙。换言之，第一垫高体DA可以沿与之交叠的信号走线SW的延伸方向延伸并贯穿隔断槽BG，其两端分别与隔断槽BG的两个侧壁(即有机薄膜层ORG的侧壁)交叠。这样，不仅可以避免电极材料在隔断槽BG的下边沿处残留，还可以避免电极材料在隔断槽BG的底部残留，进一步降低信号走线SW短路的风险。
在一种示例中，在隔断槽BG的槽底，任意一个信号走线SW的边沿位于第一垫高体DA(第一垫高体DA远离衬底基板BP的一侧)，信号走线SW的两个边沿分别位于两个不同的第一垫高体DA上。相邻两个第一垫高体DA之间具有间隙，信号走线SW覆盖该间隙，且两个边沿分别与该两个第一垫高体DA交叠。尤其是在隔断槽BG的宽度(垂直于隔断槽BG的延伸方向上的尺寸)较小的隔断槽BG中，例如隔断槽BG的宽度在10～30微米时，这种第一垫高体DA的设置方式可以简化第一垫高体DA的设计和降低对工艺的要求。
在另一种实施方式中，参见图27～图29，在所述隔断槽BG的至少部分区域，所述第一垫高体DA的数量为一个且两侧分别被所述隔断槽BG两侧的所述有机薄膜层ORG覆盖；至少部分所述信号走线SW在所述隔断槽BG底面的部分承载于所述第一垫高体DA。
换言之，至少一个第一垫高体DA与多个相邻的信号走线SW交叠设置，且这些信号走线SW在隔断槽BG的槽底的部分完全位于第一垫高体 DA上。换言之，在隔断槽BG的至少部分区域，多个信号走线SW在隔断槽BG的槽底的部分在衬底基板BP上的正投影，位于同一第一垫高体DA在衬底基板BP上的正投影以内。
在本公开的一种实施方式中，所述驱动电路层F100在所述外围区BB设置有接地走线，所述接地走线与所述隔断槽BG至少部分交叠；至少部分所述第一垫高金属块DAC，为所述接地走线的一部分。如此，可以通过对接地走线的图案的局部调整来使得隔断槽BG内的短路不良减少，能够在不增加ARR制备成本的同时达成提高良率的目的。
在本公开的另一种实施方式中，所述驱动电路层F100在所述外围区BB设置有接地走线，所述接地走线与所述隔断槽BG至少部分交叠；所述信号走线SW跨过所述隔断槽BG的边沿的位置，与所述接地走线不交叠。
参见图30，在本公开提供的第二种解决方案中，可以采用如下步骤S210～步骤S220所示的制备方法，来制备本公开的阵列基板ARR。
步骤S210，参见图31，在衬底基板BP的一侧形成驱动电路层F100，所述驱动电路层F100在所述阵列基板ARR的外围区BB具有转接走线TRW，所述转接走线TRW位于源漏金属层SD和栅极层GT中的至少一层。
步骤S220，参见图31～图36，在所述驱动电路层F100远离所述衬底基板BP的一侧依次形成有机薄膜层ORG和导电层FSW；所述有机薄膜层ORG在所述外围区BB具有隔断槽BG和暴露所述转接走线TRW的过孔HH；至少部分所述转接走线TRW跨过所述隔断槽BG(即转接走线TRW的两端分别位于隔断槽BG的两侧)；所述导电层FSW具有被所述隔断槽BG的边沿隔断的信号走线SW，所述信号走线SW相邻的两端之间通过所述转接走线TRW电连接；所述信号走线SW与所述转接走线TRW之间通过所述过孔HH连接。这样，信号走线SW通过位于驱动电路层F100的转接走线TRW跨过隔断槽BG，即便隔断槽BG内残留有导电材料，残留的导电材料也不会与信号走线SW电连接。这样，可以避免因隔断槽BG内导电材料残留而导致信号走线SW间短路。
在一种示例中，制备有机薄膜层ORG和导电层FSW为制备电极复合 层F200的一部分。换言之，在步骤S220中，在驱动电路层F100远离衬底基板BP的一侧制备电极复合层F200。所述电极复合层F200包括有机薄膜层ORG和位于有机薄膜层ORG远离衬底基板BP一侧的导电层FSW。
在一种示例中，所述导电层FSW在所述隔断槽BG内还包括位于所述隔断槽BG边沿的导电材料，所述导电材料与所述信号走线SW之间断路。
在一种示例中，参见图31，驱动电路层F100在外围区BB还包括覆盖转接走线TRW的转接绝缘层TRI。参见图32，在形成使得信号走线SW与转接走线TRW电连接的过孔HH时，过孔HH贯穿有机薄膜层ORG和转接绝缘层TRI，以使得转接走线TRW的两端分别通过位于隔断槽BG两侧的两个过孔HH暴露。转接绝缘层TRI可以根据转接走线TRW进行相应的调整。举例而言，当转接走线TRW位于源漏金属层SD时，转接绝缘层TRI可以位于钝化层。再举例而言，当转接走线TRW位于栅极层GT时，转接绝缘层TRI可以位于层间电介质层ILD和钝化层中的一层或者两层。
在一种示例中，参见图36，至少部分所述转接走线TRW跨过所述隔断槽BG，且两端分别被所述过孔HH暴露；至少部分所述信号走线SW被所述隔断槽BG隔断，所述信号走线SW的相邻两端分别通过所述过孔HH与所述转接走线TRW的两端连接。
在一种示例中，参见图36，在阵列基板ARR的至少部分区域，跨过隔断槽BG的转接走线TRW的数量与需要跨过隔断槽BG的信号走线SW的数量相同，且转接走线TRW与信号走线SW一一对应设置。被隔断槽BG隔断的信号走线SW的相邻两端，与对应的转接走线TRW的两端分别通过过孔HH电连接。在更进一步的示例中，各个信号走线SW均通过转接走线TRW跨过隔断槽BG。
在一种示例中，参见图35，信号走线SW的端部在隔断槽BG以外，即信号走线SW在衬底基板BP上的正投影与隔断槽BG在衬底基板BP上的正投影没有重合区域。
在一种示例中，至少一个转接走线TRW跨过相邻设置的多个隔断槽BG；如此，信号走线SW可以通过同一转接走线TRW连续跨越多个隔断 槽BG，无需设置多个不同的转接走线TRW以跨越多个不同的隔断槽BG，避免了在不同的隔断槽BG之间的有机薄膜层ORG上设置过孔HH。
在一种示例中，至少一个转接走线TRW包括不同的走线段，相邻走线段分别设置在源漏金属层SD和栅极层GT。换言之，转接走线TRW能够在源漏金属层SD和栅极层GT之间相互转接，以避让源漏金属层SD或者栅极层GT的其他结构。
在一种示例中，至少一个信号走线SW局部位于隔断槽BG内且延伸方向平行于隔断槽BG的延伸方向；信号走线SW在有机薄膜层ORG上的走线部分与信号走线SW在隔断槽BG内的走线部分，也可以通过转接走线TRW转接。用于转接该信号走线SW的转接走线TRW的一端位于有机薄膜层ORG且通过过孔HH与该信号走线SW在有机薄膜层ORG上的走线部分连接，另一端位于隔断槽BG且通过过孔与信号走线SW位于隔断槽BG内的走线部分连接。这样，该转接走线TRW无需跨过隔断槽BG。
在一种示例中，步骤S220可以包括如下步骤S221～步骤S225所示的步骤。
步骤S221，参见图31，在驱动电路层F100远离衬底基板BP的一侧制备有机材料层ORGA。
步骤S222，参见图32，对有机材料层ORGA和转接绝缘层TRI进行图案化。其中，有机薄膜层ORG具有隔断槽BG，有机薄膜层ORG和转接绝缘层TRI形成有暴露转接走线TRW的过孔HH。参见图32和图33，至少部分转接走线TRW跨过隔断槽BG，且两端分别被过孔HH暴露。
步骤S223，参见图34，在有机薄膜层ORG远离衬底基板BP的一侧形成导电材料层FSWA，导电材料层FSWA可以覆盖有机薄膜层ORG和隔断槽BG。
步骤S224，参见图35和图36，对导电材料层FSWA进行图案化，如此制备出信号走线SW。其中，至少部分信号走线SW通过转接走线TRW转接来跨过隔断槽BG。
参见图37-1，在本公开实施方式的阵列基板ARR中，至少部分隔断槽BG中会设置有位于源漏金属层SD的导电结构DW。在相关技术中， 位于隔断槽BG的源漏金属层SD之间也经常出现短路不良。对该类不良进行解析，发现在导电结构DW之间残留有导电材料，导电结构DW之间通过残留的导电材料短路。对相关技术中阵列基板ARR的制备过程进行了追溯。参见图37-1～图40，相关技术中的阵列基板ARR采用如下步骤S021～S025所示的方法进行制备。
步骤S021，参见图37-1，依次制备衬底基板BP、驱动电路层F100和有机薄膜层ORG；有机薄膜层ORG在外围区BB设置有隔断槽BG，驱动电路层F100在外围区BB设置有导电结构DW，且导电结构DW的至少部分暴露于隔断槽BG，例如完全位于隔断槽BG。步骤S022，参见图37-2，在有机薄膜层ORG远离衬底基板BP的表面形成导电材料层FSWA。然后，参见图38～图40，采用光刻工艺，对导电材料层FSWA进行图案化操作。具体的，在步骤S023中，参见图38，在导电材料层FSWA远离衬底基板BP的一侧涂覆光刻胶PR。其中，光刻胶PR填充隔断槽BG；因光刻胶的流动性，光刻胶PR在导电结构DW与隔断槽BG的边沿之间的厚度最大。在步骤S024中，参见图39，对光刻胶PR进行曝光和显影。在隔断槽BG的边沿和导电结构DW之间，光刻胶PR不能充分曝光而导致残留，残留的光刻胶PRR会对下方(靠近衬底基板BP的一侧)的导电材料层FSWA构成遮挡和保护。在步骤S025中，参见图40，在通过刻蚀对导电材料层FSWA进行图案化时，被残留的光刻胶PRR遮挡的导电材料可能无法充分刻蚀而残留，残留的导电材料FSWR可能会导致相邻的两个导电结构DW之间短路。
同样的，发明人尝试通过过曝光的方案来消除光刻胶残留以降低短路不良，但是发现这会较大幅度的延长曝光时间进而影响曝光节拍，对产能影响较大，增大了阵列基板ARR的成本。另外，发明人还发现，随着阵列基板ARR中各个结构的尺寸不断缩小，过曝光的方案受到曝光机工艺能力的制约越来越大。
为了解决此类短路不良，参见图41，在本公开实施方式提供的第三种解决方案中，可以采用如下步骤S310～步骤S320所示的制备方法，来制备本公开实施方式的阵列基板ARR。
步骤S310，参见图42，在衬底基板BP的一侧形成驱动电路层F100， 所述驱动电路层F100在所述阵列基板ARR的外围区BB具有第二垫高体DB和导电结构DW；所述第二垫高体DB包括位于栅极层GT的第二垫高金属块DBC和覆盖所述第二垫高金属块DBC的第二垫高绝缘层DBI，以使得第二垫高体DB形成有向上凸出的凸台结构。所述导电结构DW位于所述第二垫高体DB远离所述衬底基板BP的一侧且至少部分与所述第二垫高体DB交叠；
步骤S320，参见图42～图46，在所述驱动电路层F100远离所述衬底基板BP的一侧依次形成有机薄膜层ORG和导电层FSW；所述有机薄膜层ORG在所述外围区BB具有隔断槽BG，所述第二垫高体DB和所述导电结构DW至少部分被所述隔断槽BG暴露；且所述导电结构DW被所述隔断槽BG暴露的部分完全承载于所述第二垫高体DB上。换言之，被隔断槽BG暴露的导电结构DW部分，完全位于第二垫高体DB所形成的凸台结构上。
在形成导电层FSW时，由于导电结构DW与隔断槽BG的底部之间存在由第二垫高体DB形成的台阶，台阶上的导电材料可以被充分刻蚀，因此即便第二垫高体DB与隔断槽BG的边缘残留有导电材料，这些导电材料也不会与导电结构DW连接，避免了导电结构DW之间短路。另外，即便台阶上与导电结构DW相邻的导电材料意外的未能够充分刻蚀，残留的导电材料在第二垫高体DB的边缘处也因段差的存在而不能连续，这进一步降低了导电结构DW因残留的导电材料而短路的风险。
在一种示例中，所述导电结构DW被所述隔断槽BG暴露的部分的边缘，与所述第二垫高体DB的边缘之间具有间隙。示例性的，参见图42，导电结构DW和第二垫高体DB完全位于隔断槽BG内，且导电结构DW的尺寸小于第二垫高体DB。
在一种示例中，所述导电层FSW在所述隔断槽BG内包括，位于所述第二垫高体DB的边沿与所述隔断槽BG的边沿之间的导电材料，所述导电材料与所述导电结构DW断路。
在一种示例中，制备有机薄膜层ORG和导电层FSW为制备电极复合层F200的一部分。换言之，在步骤S320中，在驱动电路层F100远离衬底基板BP的一侧制备电极复合层F200。所述电极复合层F200包括有机 薄膜层ORG和位于有机薄膜层ORG远离衬底基板BP一侧的导电层FSW。
在一种示例中，步骤S320可以包括步骤S331～步骤S335。
步骤S331，参见图42，在所述驱动电路层F100远离所述衬底基板BP的一侧形成有机薄膜层ORG；所述有机薄膜层ORG在所述外围区BB具有隔断槽BG，所述第二垫高体DB和所述导电结构DW至少部分被所述隔断槽BG暴露；且所述导电结构DW被所述隔断槽BG暴露的部分完全承载于所述第二垫高体DB上。
步骤S332，参见图43，在有机薄膜层ORG远离衬底基板BP的一侧形成导电材料层FSWA，导电材料层FSWA覆盖有机薄膜层ORG和隔断槽BG。其中，导电材料层FSWA在隔断槽BG内覆盖第二垫高体DB和导电结构DW。
步骤S333，参见图44，在导电材料层FSWA远离衬底基板BP的一侧涂覆光刻胶PR，光刻胶PR填充隔断槽BG。参见图44，由于第二垫高体DB的抬高作用，光刻胶PR在第二垫高体DB上方的厚度减小了。
步骤S334，参见图45，对光刻胶PR进行曝光和显影。在隔断槽BG中被第二垫高体DB抬高的部分，光刻胶PR的厚度减小因而可以被充分曝光，不易产生残留。在第二垫高体DB与隔断槽BG的边缘之间，可以有残留的光刻胶PRR，该残留的光刻胶不会覆盖第二垫高体DB。
步骤S335，对导电材料层FSWA进行刻蚀以形成所需的结构，形成导电层FSW；然后去除光刻胶。在该过程中，参见图46，在隔断槽BG的边沿与第二垫高体DB之间，导电材料因残留的光刻胶遮挡而未能够充分刻蚀，这使得在隔断槽BG的边沿与第二垫高体DB之间具有残留的导电材料FSWR。然而，该残留的导电材料FSWR与导电结构DW之间被第二垫高体DB隔断，进而避免了导电结构DW之间因残留的导电材料FSWR而短路。
为了解决此类短路不良，参见图48，在本公开实施方式提供的第四种解决方案中，可以采用如下步骤S410～步骤S450所示的制备方法，来制备本公开实施方式的阵列基板ARR。
步骤S410，参见图49～图51，在衬底基板BP的一侧制备有机薄膜层ORG，有机薄膜层ORG在外围区BB具有隔断槽BG。
步骤S420，参见图49～图51，在有机薄膜层ORG远离衬底基板BP的一侧制备导电材料层FSWA，导电材料层FSWA覆盖有机薄膜层ORG和隔断槽BG。
步骤S430，参见图49～图51，在导电材料层FSWA远离衬底基板BP的一侧涂覆光刻胶PR，光刻胶PR覆盖有机薄膜层ORG并填充隔断槽BG。
步骤S440，参见图49～图51，对光刻胶PR进行曝光，其中，曝光机的聚焦平面FF在光刻胶PR的表面以下。
步骤S450，对导电材料层FSWA进行刻蚀，然后去除光刻胶。
参见图47，在相关技术中，曝光机的聚焦平面FF通常在光刻胶的上表面(远离衬底基板BP的表面)。而在本公开实施方式的制备方法中，将曝光机的聚焦平面FF下移，可以提高对位于隔断槽BG内底部的光刻胶PR的曝光程度，进而达成在不增加曝光强度(例如提高曝光光强或者延长曝光时间)的情况下使得隔断槽BG内底部的光刻胶PR充分曝光，且不会对表浅的光刻胶(例如位于有机薄膜层ORG上的光刻胶)的图案产生不利影响。如此，通过使得隔断槽BG内底部的光刻胶PR充分曝光，提高了光刻胶显影后图案的精准程度，进而提高了导电材料层FSWA在图案化后的图案的精准程度，减少或者避免了导电材料层FSWA在图案化以后在隔断槽BG内残留有非设计的导电材料，进而避免了隔断槽BG内的短路不良。
在一种示例中，在步骤S450中，参见图49，在隔断槽BG内，曝光机的聚焦平面FF与隔断槽BG的最底部的距离，不大于隔断槽BG内光刻胶最大厚度的一半，以确保对隔断槽BG最底部的光刻胶的充分曝光。
在另一种示例中，在步骤S450中，参见图50或者图51，在隔断槽BG，曝光机的聚焦平面FF在光刻胶的底面附近或者光刻胶的底面以下。这样，利于曝光所用的掩膜版的设计。
在该实施方式中，驱动电路层F100可以位于导电材料层FSWA远离衬底基板BP的一侧，或者位于导电材料层FSWA与衬底基板BP之间，本公开不做特殊的限定。在图49～图51的示例中，驱动电路层F100位于导电材料层FSWA与衬底基板BP之间。则，在步骤S410之前，还可以先在衬底基板BP上制备驱动电路层F100，然后再在驱动电路层F100远 离衬底基板BP的一侧制备有机薄膜层ORG和导电材料层FSWA。在本公开的其他实施方式中，可以先制备有机薄膜层ORG和导电材料层FSWA，例如先制备阵列基板ARR的像素电极或者公共电极，然后再制备驱动电路层F100。
在本公开的一种实施方式中，所述显示面板PNL还包括与所述阵列基板ARR对盒设置的盖板CF，以及设于所述阵列基板ARR和所述盖板CF之间的封框胶；所述封框胶覆盖所述隔断槽BG；所述驱动电路层F100在所述外围区BB具有与所述封框胶交叠的导电走线，所述导电走线网格化设计。
本公开实施方式还提供一种显示装置，该显示装置包括上述显示面板实施方式所描述的任意一种显示面板。该显示装置可以为智能手机屏幕、智能手表屏幕或者其他类型的显示装置。由于该显示装置具有上述显示面板实施方式所描述的任意一种显示面板，因此具有相同的有益效果，本公开在此不再赘述。
在本公开的一种实施方式中，参见图1，显示面板PNL为液晶显示面板，该显示装置还包括位于液晶显示面板的背光面的背光模组BLU。这样，该显示装置为透射式液晶显示装置。
需要说明的是，尽管在附图中以特定顺序描述了本公开中阵列基板的制备方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (26)

  1. 一种阵列基板，包括依次层叠设置的衬底基板、驱动电路层、有机薄膜层和导电层；
    其中，所述驱动电路层在所述阵列基板的外围区具有第一垫高体；所述第一垫高体包括位于源漏金属层和栅极层中至少一层的第一垫高金属块和覆盖所述第一垫高金属块的第一垫高绝缘层；
    所述有机薄膜层在所述外围区具有隔断槽，所述第一垫高体的一部分被所述有机薄膜层覆盖且另外一部分被所述隔断槽暴露；
    所述导电层具有跨过所述隔断槽边沿的信号走线，所述信号走线的边沿至少部分与所述第一垫高体交叠。
  2. 根据权利要求1所述的阵列基板，其中，在所述隔断槽的至少部分区域，所述隔断槽的两个边沿分别设置有多个所述第一垫高体；
    同一所述信号走线的两个边沿分别与相邻的两个第一垫高体交叠设置，且所述信号走线覆盖相邻两个所述第一垫高体之间的间隙。
  3. 根据权利要求1所述的阵列基板，其中，在所述隔断槽的至少部分区域，所述隔断槽的两个边沿分别设置有一个所述第一垫高体；所述信号走线与所述第一垫高体交叉设置。
  4. 根据权利要求1所述的阵列基板，其中，在所述隔断槽的至少部分区域，所述第一垫高体的数量为多个；任意一个所述第一垫高体的两端分别被所述隔断槽两侧的所述有机薄膜层覆盖；至少部分所述信号走线的两个边沿分别与相邻的两个所述第一垫高体交叠设置，且所述信号走线覆盖相邻两个所述第一垫高体之间的间隙。
  5. 根据权利要求1所述的阵列基板，其中，在所述隔断槽的至少部分区域，所述第一垫高体的数量为一个且两侧分别被所述隔断槽两侧的所述有机薄膜层覆盖；至少部分所述信号走线在所述隔断槽底面的部分承载于所述第一垫高体。
  6. 根据权利要求1～5任意一项所述的阵列基板，其中，所述驱动电路层在所述外围区设置有接地走线，所述接地走线与所述隔断槽至少部分交叠；
    至少部分所述第一垫高金属块，为所述接地走线的一部分。
  7. 根据权利要求1～5任意一项所述的阵列基板，其中，所述驱动电路层在所述外围区设置有接地走线，所述接地走线与所述隔断槽至少部分交叠；
    所述信号走线跨过所述隔断槽的边沿的位置，与所述接地走线不交叠。
  8. 根据权利要求1～5任意一项所述的阵列基板，其中，沿垂直于所述隔断槽的延伸方向，所述第一垫高体被所述有机薄膜层覆盖的部分的尺寸不小于2微米。
  9. 根据权利要求1～5任意一项所述的阵列基板，其中，所述第一垫高体凸出于所述隔断槽的槽底的高度，不小于所述隔断槽的深度的10％。
  10. 一种阵列基板的制备方法，包括：
    在衬底基板的一侧形成驱动电路层，所述驱动电路层在所述阵列基板的外围区具有第一垫高体；所述第一垫高体包括位于源漏金属层和栅极层中至少一层的第一垫高金属块和覆盖所述第一垫高金属块的第一垫高绝缘层；
    在所述驱动电路层远离所述衬底基板的一侧依次形成有机薄膜层和导电层；所述有机薄膜层在所述外围区具有隔断槽，所述第一垫高体的一部分被所述有机薄膜层覆盖且另外一部分被所述隔断槽暴露；所述导电层具有跨过所述隔断槽边沿的信号走线，所述信号走线的边沿至少部分与所述第一垫高体交叠。
  11. 根据权利要求10所述的阵列基板的制备方法，其中，在所述隔断槽的至少部分区域，所述隔断槽的两个边沿分别设置有多个所述第一垫高体；
    同一所述信号走线的两个边沿分别与相邻的两个第一垫高体交叠设置，且所述信号走线覆盖相邻两个所述第一垫高体之间的间隙。
  12. 根据权利要求10所述的阵列基板的制备方法，其中，在所述隔断槽的至少部分区域，所述隔断槽的两个边沿分别设置有一个所述第一垫高体；所述信号走线与所述第一垫高体交叉设置。
  13. 根据权利要求10所述的阵列基板的制备方法，其中，在所述隔断槽的至少部分区域，所述第一垫高体的数量为多个；任意一个所述第一垫高体的两端分别被所述隔断槽两侧的所述有机薄膜层覆盖；至少部分所 述信号走线的两个边沿分别与相邻的两个所述第一垫高体交叠设置，且所述信号走线覆盖相邻两个所述第一垫高体之间的间隙。
  14. 根据权利要求10所述的阵列基板的制备方法，其中，在所述隔断槽的至少部分区域，所述第一垫高体的数量为一个且两侧分别被所述隔断槽两侧的所述有机薄膜层覆盖；至少部分所述信号走线在所述隔断槽底面的部分承载于所述第一垫高体。
  15. 一种阵列基板，包括依次层叠设置的衬底基板、驱动电路层、有机薄膜层和导电层；
    其中，所述驱动电路层在所述阵列基板的外围区具有转接走线，所述转接走线位于源漏金属层和栅极层的至少一层；
    所述有机薄膜层在所述外围区具有隔断槽和暴露所述转接走线的过孔；至少部分所述转接走线跨过所述隔断槽；所述导电层具有被所述隔断槽的边沿隔断的信号走线，所述信号走线相邻的两端之间通过所述转接走线电连接；所述信号走线与所述转接走线之间通过所述过孔连接。
  16. 根据权利要求15所述的阵列基板，其中，至少部分所述转接走线跨过所述隔断槽，且两端分别被所述过孔暴露；
    至少部分所述信号走线被所述隔断槽隔断，所述信号走线的相邻两端分别通过所述过孔与所述转接走线的两端连接。
  17. 根据权利要求15或者16所述的阵列基板，其中，所述导电层在所述隔断槽内还包括，位于所述隔断槽边沿的导电材料，所述导电材料与所述信号走线之间断路。
  18. 一种阵列基板的制备方法，包括：
    在衬底基板的一侧形成驱动电路层，所述驱动电路层在所述阵列基板的外围区具有转接走线，所述转接走线位于源漏金属层和栅极层中的至少一层；
    在所述驱动电路层远离所述衬底基板的一侧依次形成有机薄膜层和导电层；所述有机薄膜层在所述外围区具有隔断槽和暴露所述转接走线的过孔；至少部分所述转接走线跨过所述隔断槽；所述导电层具有被所述隔断槽的边沿隔断的信号走线，所述信号走线相邻的两端之间通过所述转接走线电连接；所述信号走线与所述转接走线之间通过所述过孔连接。
  19. 一种阵列基板，包括依次层叠设置的衬底基板、驱动电路层、有机薄膜层和导电层；
    其中，所述驱动电路层在所述阵列基板的外围区具有第二垫高体和导电结构；所述第二垫高体包括位于栅极层的第二垫高金属块和覆盖所述第二垫高金属块的第二垫高绝缘层；所述导电结构位于所述第二垫高体远离所述衬底基板的一侧且至少部分与所述第二垫高体交叠；
    所述有机薄膜层在所述外围区具有隔断槽，所述第二垫高体和所述导电结构至少部分被所述隔断槽暴露；且所述导电结构被所述隔断槽暴露的部分完全承载于所述第二垫高体上。
  20. 根据权利要求19所述的阵列基板，其中，所述导电结构被所述隔断槽暴露的部分的边缘，与所述第二垫高体的边缘之间具有间隙。
  21. 根据权利要求19或者20所述的阵列基板，其中，所述导电层在所述隔断槽内包括，位于所述第二垫高体的边沿与所述隔断槽的边沿之间的导电材料，所述导电材料与所述导电结构断路。
  22. 一种阵列基板的制备方法，包括：
    在衬底基板的一侧形成驱动电路层，所述驱动电路层在所述阵列基板的外围区具有第二垫高体和导电结构；所述第二垫高体包括位于栅极层的第二垫高金属块和覆盖所述第二垫高金属块的第二垫高绝缘层；所述导电结构位于所述第二垫高体远离所述衬底基板的一侧且至少部分与所述第二垫高体交叠；
    在所述驱动电路层远离所述衬底基板的一侧依次形成有机薄膜层和导电层；所述有机薄膜层在所述外围区具有隔断槽，所述第二垫高体和所述导电结构至少部分被所述隔断槽暴露；且所述导电结构被所述隔断槽暴露的部分完全承载于所述第二垫高体上。
  23. 根据权利要求22所述的阵列基板的制备方法，其中，所述导电结构被所述隔断槽暴露的部分的边缘，与所述第二垫高体的边缘之间具有间隙。
  24. 一种阵列基板的制备方法，包括：
    在衬底基板的一侧形成有机薄膜层，所述有机薄膜层在所述外围区具有隔断槽；
    在所述有机薄膜层远离所述衬底基板的一侧形成导电材料层，所述导电材料层覆盖所述有机薄膜层和所述隔断槽；
    在所述导电材料层远离所述衬底基板的一侧涂覆光刻胶，所述光刻胶覆盖所述有机薄膜层并填充所述隔断槽；
    对所述光刻胶进行曝光，其中，曝光机的聚焦平面在光刻胶的表面以下；
    对所述导电材料层进行刻蚀，然后去除光刻胶。
  25. 一种显示面板，包括权利要求1～9、权利要求15～17、权利要求19～21任意一项所述的阵列基板。
  26. 根据权利要求25所述的显示面板，其中，所述显示面板还包括与所述阵列基板对盒设置的盖板，以及设于所述阵列基板和所述盖板之间的封框胶；所述封框胶覆盖所述隔断槽；
    所述驱动电路层在所述外围区具有与所述封框胶交叠的导电走线，所述导电走线网格化设计。
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