CN111725240B - 薄膜晶体管电极及其制造方法、显示装置 - Google Patents

薄膜晶体管电极及其制造方法、显示装置 Download PDF

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CN111725240B
CN111725240B CN202010528092.6A CN202010528092A CN111725240B CN 111725240 B CN111725240 B CN 111725240B CN 202010528092 A CN202010528092 A CN 202010528092A CN 111725240 B CN111725240 B CN 111725240B
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刘娟
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Abstract

本发明公开了一种薄膜晶体管电极及其制造方法、显示装置,包括:衬底基板;依次设置在所述衬底基板上的栅极金属层、栅极绝缘层、第一平坦层、源漏极层以及第二平坦层;所述第二平坦层暴露出所述源漏极层的侧壁,所述源漏极层的侧壁作为导电区域,所述源漏极层的底部设置有绝缘层。本发明公开的薄膜晶体管电极及其制造方法、显示装置,可以从电极结构上大大减小异物,尤其是金属异物导致的面板间短路问题,同时提高电极利用率,实现间距良好的趋势。

Description

薄膜晶体管电极及其制造方法、显示装置
技术领域
本申请涉及一种显示器技术领域,尤其涉及一种薄膜晶体管电极及其制造方法、显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode,OLED)显示面板因其自发光、轻薄、宽视角、高亮度、高对比度等特点,逐渐成为显示领域的主流。OLED显示面板广泛应用于智能手机、平板电脑、电视等终端产品。
随着显示面板解析度的增加,IC芯片与绑定面板间距尺寸越来越小,达到了微米级。因此对绑定技术的要求也越来越高。绑定异物作为在绑定制程中最易出现的不良问题之一,会导致屏幕产生线类,点不亮等功能性不良问题,大大影响了生产良率和产品性能。在目前的绑定工艺中,是用异方性导电胶膜(Anisotropic Conductive Film,简称ACF)作为介质,将COF于面板相连接,来实现信号的传输。而且在现有的面板测试工艺中,待测试的面板是通过外接柔性电路板,通过压接技术将待测试面板的测试电极与柔性电路板相导通,来实现在绑定前的一次测试。测试合格,产品进入下一个工序;测试不合格,产品报废。
如图1所示,为目前行业上显示面板电极结构示意图,包括衬底基板10、栅极20、栅极绝缘层30、第一平坦层40、源漏极层50以及第二平坦层60。如图2所示,为显示面板电极与COF电极的连接示意图,其中包括显示面板1、绑定电极2、COF3以及COF电极4。由图1和图2可见,在显示面板绑定电极2与COF电极4连接时,接触所述COF电极4的为显示面板电极中的源漏极层50。然而在面板测试工艺中,由于所述待测试面板是通过外力的压接而相连接,因此所述待测试面板的测试电极会受到压接工具的比较大的压力和摩擦,会导致测试电极划伤。而这种划伤在经过下一个清洗工序中,被划伤的电极所产生的碎屑容易被带入到面板的绑定电极区域,所述碎屑在绑定电极区域会形成绑定异物。由于在显示面板电极中,源漏极层处于最外层,所述绑定异物会造成绑定区域短路和不良,从而造成显示面板形成亮暗线等功能性不良的问题。
发明内容
为了克服现有技术的不足,本申请实施例提供一种薄膜晶体管电极及其制造方法、显示装置,可以从电极结构上大大减小异物,尤其是金属异物导致的面板间短路问题,同时提高电极利用率,实现间距良好的趋势。
本发明实施例提供了一种薄膜晶体管电极,所述薄膜晶体管电极包括:
衬底基板;
依次设置在所述衬底基板上的栅极金属层、栅极绝缘层、第一平坦层、源漏极层、第二平坦层;
其中,所述第二平坦层暴露出所述源漏极层的侧壁,所述源漏极层的侧壁作为导电区域,所述源漏极层的底部设置有绝缘层。
根据本发明实施例所提供的薄膜晶体管电极,所述薄膜晶体管电极为孔洞式结构,所述薄膜晶体管电极通过孔洞中所述源漏极的侧壁导电。
根据本发明实施例所提供的薄膜晶体管电极,所述源漏极层的侧壁裸露。
根据本发明实施例所提供的薄膜晶体管电极,所述绝缘层与所述第一平坦层或所述第二平坦层相同或不同。
根据本发明实施例所提供的薄膜晶体管电极,所述绝缘层完全覆盖所述源漏极层的底部,所述绝缘层不覆盖所述源漏极层的侧壁。
本发明实施例还提供了一种显示装置,所述显示装置包括上述实施例所提供的薄膜晶体管电极。
本发明实施例还提供了一种薄膜晶体管电极的制造方法,所述制造方法包括:
在衬底基板上形成栅极金属层,在所述栅极金属层的两侧形成栅极绝缘层,在所述栅极绝缘层上形成第一平坦层;
在所述第一平坦层上形成源漏极层,在所述源漏极层的顶部形成第二平坦层,在所述源漏极层的底部形成绝缘层,裸露出所述源漏极层的侧壁;
其中,所述源漏极层的侧壁作为导电区域。
根据本发明实施例所提供的薄膜晶体管电极的制造方法,在所述薄膜晶体管电极为孔洞式结构,所述薄膜晶体管电极通过孔洞中所述源漏极的侧壁导电。
根据本发明实施例所提供的薄膜晶体管电极的制造方法,所述绝缘层与所述第一平坦层或所述第二平坦层相同或不同。
根据本发明实施例所提供的薄膜晶体管电极的制造方法,所述绝缘层完全覆盖所述源漏极层的底部,所述绝缘层不覆盖所述源漏极层的侧壁。
本发明的有益效果为:本发明实施例提供一种薄膜晶体管电极及其制造方法、显示装置,通过设计新的电极结构,将薄膜晶体管的电极设置为孔洞式结构,通过孔洞的侧壁导电,从结构上大大减小了测试电极划伤所产生的碎屑进入到绑定区的可能性,有效的防止了金属异物所导致的绑定区域的电极短路。在薄膜晶体管电极中同样大小的有效电极接触面积下,由于孔洞式结构具有四个侧壁来作为有效解除面积,因此可以减小薄膜晶体管电极为现有技术中的薄膜晶体管电极的四分之一大小。因此可以极大程度的减小电极的排布,实现电极之间的间距良好以及多电极的发展趋势。
附图说明
下面结合附图,通过对本申请的具体实施方式详细描述,将使本申请的技术方案及其它有益效果显而易见。
图1为现有技术中的显示面板电极结构示意图。
图2为现有技术中显示面板电极与COF电极的连接示意图。
图3为本实施例所提供的薄膜晶体管电极结构示意图。
图4为本实施例所提供的薄膜晶体管电极简图。
图5为现有技术的电极的有效接触面积示意图。
图6为本实施例的电极的有效接触面积示意图。
具体实施方式
下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述。显然,所描述的实施例仅仅是本申请一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。
在本申请的描述中,需要理解的是,术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本申请和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本申请的限制。此外,术语“第一”、“第二”仅用于描述目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此,限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中,“多个”的含义是两个或两个以上,除非另有明确具体的限定。
在本申请的描述中,需要说明的是,除非另有明确的规定和限定,术语“安装”、“相连”、“连接”应做广义理解,例如,可以是固定连接,也可以是可拆卸连接,或一体地连接;可以是机械连接,也可以是电连接或可以相互通讯;可以是直接相连,也可以通过中间媒介间接相连,可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言,可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中,除非另有明确的规定和限定,第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触,也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且,第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方,或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方,或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开,下文中对特定例子的部件和设置进行描述。当然,它们仅仅为示例,并且目的不在于限制本申请。此外,本申请可以在不同例子中重复参考数字和/或参考字母,这种重复是为了简化和清楚的目的,其本身不指示所讨论各种实施方式和/或设置之间的关系。此外,本申请提供了的各种特定的工艺和材料的例子,但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
本发明实施例提供了一种薄膜晶体管电极,如图3所示,所述薄膜晶体管电极包括:
衬底基板10;
在所述衬底基板10上依次设置有栅极金属层20、栅极绝缘层30、第一平坦层40、源漏极层50以及第二平坦层60;
其中,所述源漏极层50为侧壁导电,且所述源漏极层50的底部还有一层绝缘层70。
所述源漏极层50的所述侧壁501裸露,可以与其他电极相连接而导通电路。与COF电极相连接时,通过所述源漏极层50的所述侧壁501来接触所述COF电极,来传递电信号。
在所述源漏极层50的底部的所述绝缘层70可以与所述第一平坦层40或所述第二平坦层60为相同的绝缘材料或者为不同的绝缘材料,所述绝缘层70可以为其他有效的绝缘材料,在此不限定绝缘材料。
如图3所示,所述绝缘层70完全覆盖所述源漏极层50的底部,所述绝缘层70不覆盖所述源漏极层50的所述侧壁501。所述源漏极层50的所述侧壁501裸露出来,可以与其他电极相连接。如图4所示,在显示面板100中的所述薄膜晶体管电极101为孔洞式结构,所述薄膜晶体管电极101通过孔洞中所述源漏极的侧壁110导电。在现有技术的电极中,源漏极层是在最外层,若电极上方存在金属异物111,所述金属异物111会直接与相关电极的源漏极层相接触,从而会造成电极与电极之间的短路问题。在本实施例所提供的薄膜晶体管电极101中,若电极上方存在金属异物111,所述金属异物111不会接触到位于所述薄膜晶体管电极101内侧的所述源漏极层的侧壁110,也不会引发所述薄膜晶体管电极101的短路。
本发明实施例还提供了了一种薄膜晶体管电极的制造方法,所述制造方法包括:
在衬底基板上形成栅极金属层,在所述栅极金属层的两侧形成栅极绝缘层,在所述栅极绝缘层上形成第一平坦层;
在所述第一平坦层上形成源漏极层,在所述源漏极层的顶部形成第二平坦层,在所述源漏极层的底部形成绝缘层,裸露出所述源漏极层的侧壁;
其中,所述源漏极层的侧壁作为导电区域。
如图3所示,为本实施例所提供的薄膜晶体管电极的制造方法所制造出来的薄膜晶体管电极,在所述薄膜晶体管电极的制造方法形成薄膜晶体管中,所述薄膜晶体管电极为孔洞式结构,所述薄膜晶体管电极通过孔洞中所述源漏极50的所述侧壁501导电。其中,在所述源漏极层50的底部形成的所述绝缘层70与所述第一平坦层40或所述第二平坦层60为相同的绝缘材料或不同的绝缘材料。所述绝缘层可以为其他有效的绝缘材料,在此不限定绝缘材料。在所述源漏极层50的底部形成的所述绝缘层70完全覆盖所述源漏极层50的底部,所述绝缘层70不覆盖所述源漏极层50的所述侧壁501。
本发明实施例还提供了一种显示装置,所述显示装置使用了本实施例所提供的所述薄膜晶体管电极。如图5所示,为现有技术的电极的有效接触面积示意图;如图6所示,为本实施例的电极的有效接触面积示意图。由图5和图6所示,所述有效接触面积为源漏极层的有效接触面积,因此在同样大小的有效接触面积下,在现有技术的电极中,所述有效接触面积为上部的表面积。若在现有技术中,设计要求有效接触面积为S=a*a的电极,如图4和图6所示,在本实施例所提供的薄膜晶体管电极中,由于使用的孔洞式接触结构,所述有效接触面积为内侧的四个侧壁,则每个侧壁的有效接触面积为S/4即可,也即本实施例所提供的薄膜晶体管电极中上表面长度为a/2即可,本实施例所提供的薄膜晶体管电极为现有技术的电极的一半大小即可。因此,使用本实施例所提供的薄膜晶体管电极可以在极大程度上减小电极的排布,减小了电极之间的间距,也实现了多电极发展的趋势。
本发明实施例提供一种薄膜晶体管电极及其制造方法、显示装置,通过设计新的电极结构,将薄膜晶体管的电极设置为孔洞式结构,通过孔洞的侧壁导电,从结构上大大减小了测试电极划伤所产生的碎屑进入到绑定区的可能性,有效的防止了金属异物所导致的绑定区域的电极短路。在薄膜晶体管电极中同样大小的有效电极接触面积下,由于孔洞式结构具有四个侧壁来作为有效解除面积,因此可以减小薄膜晶体管电极为现有技术中的薄膜晶体管电极的四分之一大小。因此可以极大程度的减小电极的排布,实现电极之间的间距良好以及多电极的发展趋势。
以上对本申请实施例所提供的一种薄膜晶体管电极及其制造方法、显示装置进行了详细介绍,本文中应用了具体个例对本申请的原理及实施方式进行了阐述,以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想;本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (10)

1.一种薄膜晶体管电极,其特征在于,所述薄膜晶体管电极包括:
衬底基板;
依次设置在所述衬底基板上的栅极金属层、栅极绝缘层、第一平坦层、源漏极层以及第二平坦层;
其中,所述第二平坦层暴露出所述源漏极层的侧壁,所述源漏极层的侧壁作为导电区域,所述源漏极层的底部设置有绝缘层,且所述源漏极层背离所述绝缘层的一侧覆盖在所述栅极金属层上。
2.根据权利要求1所述的薄膜晶体管电极,其特征在于,所述薄膜晶体管电极为孔洞式结构,所述薄膜晶体管电极通过孔洞中所述源漏极的侧壁导电。
3.根据权利要求1所述的薄膜晶体管电极,其特征在于,所述源漏极层的侧壁裸露。
4.根据权利要求1所述的薄膜晶体管电极,其特征在于,所述绝缘层与所述第一平坦层或所述第二平坦层相同或不同。
5.根据权利要求4所述的薄膜晶体管电极,其特征在于,所述绝缘层完全覆盖所述源漏极层的底部,所述绝缘层不覆盖所述源漏极层的所述侧壁。
6.一种显示装置,其特征在于,所述显示装置包括权利要求1至5中任一项所述的薄膜晶体管电极。
7.一种薄膜晶体管电极的制造方法,其特征在于,所述制造方法包括:
在衬底基板上形成栅极金属层,在所述栅极金属层的两侧形成栅极绝缘层,在所述栅极绝缘层上形成第一平坦层;
在所述第一平坦层上形成源漏极层,在所述源漏极层的顶部形成第二平坦层,在所述源漏极层的底部形成绝缘层,裸露出所述源漏极层的侧壁,所述源漏极层背离所述绝缘层的一侧覆盖在所述栅极金属层上;
其中,所述源漏极层的侧壁作为导电区域。
8.根据权利要求7所述的薄膜晶体管电极的制造方法,其特征在于,在所述薄膜晶体管电极为孔洞式结构,所述薄膜晶体管电极通过孔洞中所述源漏极的侧壁导电。
9.根据权利要求7所述的薄膜晶体管电极的制造方法,其特征在于,所述绝缘层与所述第一平坦层或所述第二平坦层相同或不同。
10.根据权利要求7所述的薄膜晶体管电极的制造方法,其特征在于,所述绝缘层完全覆盖所述源漏极层的底部,所述绝缘层不覆盖所述源漏极层的侧壁。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103985708A (zh) * 2014-05-26 2014-08-13 昆山龙腾光电有限公司 薄膜晶体管阵列基板及其制作方法
CN108400140A (zh) * 2018-02-08 2018-08-14 武汉华星光电技术有限公司 阵列基板及其制造方法
CN110518073A (zh) * 2019-08-29 2019-11-29 合肥鑫晟光电科技有限公司 薄膜晶体管及其制备方法、显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012077602A1 (ja) * 2010-12-09 2012-06-14 シャープ株式会社 薄膜トランジスタアレイ基板
KR101830170B1 (ko) * 2011-05-17 2018-02-21 삼성디스플레이 주식회사 산화물 반도체 소자, 산화물 반도체 소자의 제조 방법, 산화물 반도체소자를 포함하는 표시 장치 및 산화물 반도체 소자를 포함하는 표시 장치의 제조 방법
WO2013111725A1 (ja) * 2012-01-26 2013-08-01 シャープ株式会社 半導体装置およびその製造方法
KR102117454B1 (ko) * 2013-11-19 2020-06-01 엘지디스플레이 주식회사 산화물 박막 트랜지스터를 구비한 평판 표시 장치 및 그 제조방법
CN105097941B (zh) * 2015-05-28 2019-02-26 京东方科技集团股份有限公司 一种薄膜晶体管及其制造方法、阵列基板、显示装置
CN106571371B (zh) * 2015-10-09 2019-08-09 群创光电股份有限公司 阵列基板及其应用装置与组装方法
CN107195635B (zh) * 2017-05-12 2020-05-12 深圳市华星光电半导体显示技术有限公司 薄膜晶体管阵列基板及其制备方法
JP2019169606A (ja) * 2018-03-23 2019-10-03 シャープ株式会社 アクティブマトリクス基板およびその製造方法
CN109378317A (zh) * 2018-10-12 2019-02-22 合肥鑫晟光电科技有限公司 阵列基板及其制备方法、显示装置
CN109742153B (zh) * 2019-01-04 2020-04-07 京东方科技集团股份有限公司 阵列基板、薄膜晶体管及其制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103985708A (zh) * 2014-05-26 2014-08-13 昆山龙腾光电有限公司 薄膜晶体管阵列基板及其制作方法
CN108400140A (zh) * 2018-02-08 2018-08-14 武汉华星光电技术有限公司 阵列基板及其制造方法
CN110518073A (zh) * 2019-08-29 2019-11-29 合肥鑫晟光电科技有限公司 薄膜晶体管及其制备方法、显示装置

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