CN103531639A - 薄膜晶体管及其制备方法、阵列基板、显示装置 - Google Patents

薄膜晶体管及其制备方法、阵列基板、显示装置 Download PDF

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CN103531639A
CN103531639A CN201310500440.9A CN201310500440A CN103531639A CN 103531639 A CN103531639 A CN 103531639A CN 201310500440 A CN201310500440 A CN 201310500440A CN 103531639 A CN103531639 A CN 103531639A
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semiconductor active
film transistor
active region
charge transfer
transfer layer
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CN103531639B (zh
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张运奇
朴祥秀
张勋泽
彭亮
於刘民
房伟华
申艳蕊
肖亮
黄道伍
董志远
段龙龙
王健
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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Priority to EP14856040.2A priority patent/EP2908348B1/en
Priority to US14/429,940 priority patent/US9484468B2/en
Priority to PCT/CN2014/082241 priority patent/WO2015058562A1/zh
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Abstract

本发明提供一种薄膜晶体管及其制备方法、阵列基板、显示装置，属于显示装置制造技术领域，其可解决现有的薄膜晶体管的半导体有源区掺杂离子转变为掺杂半导体有源区时，离子杂质破坏半导体材料的晶格，导致薄膜晶体管性能下降的问题。本发明的薄膜晶体管，其包括栅极、栅极绝缘层、半导体有源区以及与半导体有源区连接的源极、漏极，还包括与所述半导体有源区接触的表面电荷转移层，所述表面电荷转移层用于使所述半导体有源区在不改变晶格结构的情况下产生大量的空穴或电子。本发明的半导体有源区的材料将电荷转移到表面电荷转移层材料中，转变成掺杂半导体有源区，进而使得薄膜晶体管的性能明显提高。

Description

薄膜晶体管及其制备方法、阵列基板、显示装置
技术领域
本发明属于显示装置制造技术领域，具体涉及一种薄膜晶体管及其制备方法、阵列基板、显示装置。
背景技术
目前为了提高薄膜晶体管的性能，通常采用在薄膜晶体管的半导体有源区中掺杂离子杂质，使得半导体有源区材料转变成P掺杂或N掺杂半导体有源区材料，从而使得半导体有源区材料的载流子的寿命更长，迁移率更高，进而提高薄膜晶体管的性能。
传统的半导体掺杂方式通常采用离子注入的掺杂方法，离子注入的方法就是在真空中、低温下，把杂质离子加速，获得很大动能的杂质离子即可以直接进入半导体有源区材料中，使半导体有源区材料转变成掺杂半导体有源区材料；与此同时也会破环半导体材料晶格本身的完整性和周期性，使得在半导体有源区材料中产生一些晶格缺陷，影响载流子的寿命和迁移率，进而限制薄膜晶体管性能的提高。
发明内容
本发明所要解决的技术问题包括，针对现有的掺杂半导体薄膜晶体管存在的上述不足，提供一种性能有所提高的薄膜晶体管及其制备方法、阵列基板、显示装置。
解决本发明技术问题所采用的技术方案是一种薄膜晶体管，其包括半导体有源区，以及与半导体有源区连接的源、漏极，该薄膜晶体管还包括与所述半导体有源区接触的表面电荷转移层，所述表面电荷转移层用于使所述半导体有源区在不改变晶格结构的情况下产生大量的空穴或电子。
优选的是，所述表面电荷转移层的材料的最低未占据分子轨道与半导体有源区的材料的价带顶能带的能级差大于等于-1ev且小于等于1ev。
优选的是，所述栅极设置在基底上，所述栅极绝缘层覆盖所述栅极，所述表面电荷转移层设于栅极绝缘层上方，所述半导体有源区设于所述表面电荷转移层上方。
优选的是，所述栅极设置在基底上，所述栅极绝缘层覆盖所述栅极，所述半导体有源区设置在栅极绝缘层上方，所述表面电荷转移层设于所述半导体有源区上方。
优选的是，所述表面电荷转移层和半导体有源区依次设置在基底上，所述栅极设于半导体有源区上方，且所述栅极与半导体有源区通过所述栅极绝缘层隔开。
优选的是，所述半导体有源区和表面电荷转移层依次设置在基底上，所述栅极设于表面电荷转移层上方，且所述栅极与表面电荷转移层通过所述栅极绝缘层隔开。
优选的是，所述半导体有源区的材料为氧化锌。
进一步优选的是，所述表面电荷转移层的材料为三氧化钼。
解决本发明技术问题所采用的技术方案是上述薄膜晶体管的制备方法，其包括形成包括相互接触的表面电荷转移层，以及半导体有源区的图形的步骤。
优选的是，所述形成薄膜晶体管的表面电荷转移层和半导体有源区是通过一次构图工艺形成的。
解决本发明技术问题所采用的技术方案是一种阵列基板，其包括上述薄膜晶体管。
解决本发明技术问题所采用的技术方案是一种显示装置，其包括上述阵列基板。
由于本发明的薄膜晶体管的半导体有源区通过将其电荷转移到与其接触的表面电荷转移层一侧，得到掺杂半导体有源区，此时半导体有源区产生大量的空穴，转变成掺杂半导体有源区，但半导体的导电晶格没有发生变化，因此载流子在晶格中运动时受到散射及被俘获的概率大大降低，从而使得载流子的寿命更长，迁移率更高，有利于薄膜晶体管性能的提高。
附图说明
图1为本发明的实施例1底栅型薄膜晶体管的一种结构图；
图2为本发明的实施例1底栅型薄膜晶体管的另一种结构图；
图3为本发明的实施例1顶栅型薄膜晶体管的一种结构图；
图4为本发明的实施例1顶栅型薄膜晶体管的另一种结构图；
图5为氧化锌和三氧化钼的能带的示意图；
图6为氧化锌和三氧化钼接触前各自的能带结构示意图；
图7为氧化锌和三氧化钼接触后各自的能带结构示意图；以及，
图8为本发明的实施例3的阵列基板的结构图。
其中附图标记为：101、基底；102、栅极；103、栅极绝缘层；104、表面电荷转移层；105、半导体有源区；106、刻蚀阻挡层；107、源极和漏极；108、数据信号线；109、像素电极；110、钝化层；111、公共电极。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
实施例1：
结合图1、2、3、4，本实施例提供一种薄膜晶体管，其包括半导体有源区105，以及与半导体有源区105连接的源、漏极107，该薄膜晶体管还包括，与半导体有源区105接触的表面电荷转移层104，其中所述表面电荷转移层104用于使所述半导体有源区105在不改变晶格结构的情况下产生大量的空穴或电子。此时半导体有源区105与表面电荷转移层104接触的界面电荷发生转移，从而在半导体有源区105一侧的界面附近产生大量的空穴（或电子），将半导体有源区105转变成掺杂（P或N）型半导体有源区105。其中，优选地，表面电荷转移层104的材料的最低未占据分子轨道（LOMO）与半导体有源区105的材料的价带顶能带的能级差介于-1ev到1ev之间（包含端值）。
本实施例提供的薄膜晶体管的半导体有源区105通过将电荷转移到与其接触的表面电荷转移层104一侧，得到掺杂半导体有源区105，此时半导体有源区105产生大量的空穴或电子，转变成掺杂半导体有源区105，但半导体有源区材料的导电晶格没有发生变化，因此载流子在晶格中运动时受到散射及被俘获的概率大大降低，从而使得载流子的寿命更长，迁移率更高，有利于薄膜晶体管性能的提高。
作为本实施例的一种结构，如图1所示，优选所述薄膜晶体管为底栅型薄膜晶体管，其优选具体包括：依次设置在基底101上的栅极102，覆盖栅极102的栅极绝缘层103，设置在栅极绝缘层103上方的表面电荷转移层104，设置于表面电荷转移层104上方的半导体有源区105，以及源、漏极107，其中源、漏极107通过贯穿半导体有源区105上方的刻蚀阻挡层106的接触过孔与半导体有源区105连接。
如图2所示，当然也可以优选包括依次设置在基底101上的栅极102，覆盖栅极102的栅极绝缘层103，设置在栅极绝缘层103上方的半导体有源区105，设置于半导体有源区105上方的表面电荷转移层104，以及源、漏极107，其中源、漏极107通过贯穿半导体有源区105上方的刻蚀阻挡层106与表面电荷转移层104的接触过孔而与半导体有源区105连接。
作为本实施例的另一种结构，如图3所示，优选所述薄膜晶体管为顶栅型薄膜晶体管，其优选具体包括：依次设置在基底101上的表面电荷转移层104，半导体有源区105，以及设于半导体有源区105上方的栅极102，且栅极102与半导体有源区105通过栅极绝缘层103隔开，栅极102上方设置有钝化层110，钝化层110上方设置有源、漏极107，且源、漏极107通过贯穿钝化层110和栅极绝缘层103的接触过孔与半导体有源区105连接。
如图4所示，当然也可以优选包括：依次设置在基底101上的半导体有源区105，表面电荷转移层104，以及设于表面电荷转移层104上方的栅极102，且栅极102与表面电荷转移层104通过栅极绝缘层103隔开，栅极102上方设置有钝化层110，钝化层110上方设置有源、漏极107，且源、漏极107通过贯穿钝化层110、栅极绝缘层103和表面电荷转移层104的接触过孔与半导体有源区105连接。
如图5、6、7所示，其中，图6图示了氧化锌和三氧化钼接触前各自的能带结构；图7图示了氧化锌和三氧化钼接触后各自的能带结构。优选地，本实施例提供的表面电荷转移层104的材料为三氧化钼，半导体有源区105的材料为氧化锌。以氧化锌作为半导体有源区105的材料可以使所得到的晶体管具有较高的迁移率，从而使得晶体管的尺寸减小，而上述三氧化钼与氧化锌的组合则可达到更好的效果。具体地说，氧化锌的价带顶能带的能级为-7.39ev，三氧化钼的最低为占据分子轨道的能级为-6.7ev，此时氧化锌的价带顶能带的电子转移到三氧化钼的最低为占据分子轨道上，也就是说在两者接触电荷在接触的界面发生转移，从而在氧化锌半导体有源区105与三氧化钼表面电荷转移层104接触的一侧的界面产生大量的空穴，将本征氧化锌半导体有源区105转变成P掺杂型的氧化锌半导体有源区105，在此过程中氧化锌晶格并未发生变化，保持了氧化锌的本征半导体的晶格结构，因此载流子在晶格运动时受到散射及被俘获的概率大大降低，从而使得载流子的寿命更长，迁移率更高，有利于薄膜晶体管性能的提高。
当然本实施例也不局限于氧化锌作为半导体有源区105材料，三氧化钼作为表面电荷转移层104的材料，只要是满足所述表面电荷转移层104用于使所述半导体有源区105在不改变晶格结构的情况下产生大量的空穴或电子。或者说，表面电荷转移层104的材料的最低未占据分子轨道与半导体有源区105材料的价带顶能带的能级差大于等于-1ev小于等于1ev的材料均在本发明的保护范围内。
实施例2：
本实施例针对实施例1的薄膜晶体管提供一种薄膜晶体管的制备方法，薄膜晶体管可以为顶栅型也可以为底栅型，下面以底栅型且表面电荷转移层104设置在半导体有源区105下方的薄膜晶体管的制备方法为例具体说明，包括下述步骤：
步骤一、在基底101上在基底101上通过溅射，曝光，显影，刻蚀，剥离等工艺形成栅极102的图形。其中，栅极102的材料可以为钼（Mo）、钼铌合金（MoNb）、铝（Al）、铝钕合金（AlNd）、钛（Ti）和铜（Cu）中的一种或它们中多种材料形成的单层或多层复合叠层，优先为Mo、Al或含Mo、Al的合金组成的单层或多层复合膜；厚度为100nm～500nm。
步骤二、在栅极102上方通过等离子体增强化学气相沉积法（PECVD；Plasma Enhanced Chemical Vapor Deposition）等工艺形成栅极绝缘层103。其中，栅极绝缘层103的材料可以为硅的氧化物（SiOx）、硅的氮化物（SiNx）、铪的氧化物（HfOx）、硅的氮氧化物（SiON）、铝的氧化物（AlOx）等中的一种或它们中两种材料组成的多层复合膜。其厚度控制在100～600nm左右，可依照实际情况做调整。
步骤三、在栅极绝缘层103上方依次沉积过渡绝缘材料层、半导体材料层，并通过一次曝光，显影，刻蚀，剥离等工艺同时形成包括表面电荷转移层104和半导体有源区105的图形。通过一次构图工艺形成表面电荷转移层104和半导体有源区105可以节约成本、提高生产效率。当然也可以分两步分别形成表面电荷转移层104和半导体有源区105。其中，优选表面电荷转移层104的材料为三氧化钼，半导体有源区105的材料为氧化锌。当然，只要是满足表面电荷转移层104的材料的最低未占据分子轨道与半导体有源区105材料的价带顶能带的能级差大于等于-1ev小于等于1ev的材料均可。
步骤四、在半导体有源区105之上通过溅射、曝光、显影、刻蚀、剥离等工艺形成刻蚀阻挡层106(ESL；ETCH STOPPER)。其中，刻蚀阻挡层106的材料可以为硅的氧化物（SiOx）、硅的氮化物（SiNx）、铪的氧化物（HfOx）、硅的氮氧化物（SiON）、铝的氧化物（AlOx）等或由其中两种或三种组成的多层膜组成。
步骤五、在刻蚀阻挡层106上方通过溅射，曝光，显影，刻蚀，剥离等工艺形成源、漏极107，源、漏极107通过贯穿阻挡层的接触过孔与氧化物半导体有源层连接。其中，所述源、漏极107的材料可以是钼（Mo）、钼铌合金（MoNb）、铝（Al）、铝钕合金（AlNd）、钛（Ti）和铜（Cu）中的一种或多种材料形成的单层或多层复合叠层，优先为Mo、Al或含Mo、Al的合金组成的单层或多层复合膜。
步骤六、在源、漏极107上方形成钝化保护层。其中，所述钝化保护层的材料可以为硅的氧化物（SiOx）、硅的氮化物（SiNx）、铪的氧化物（HfOx）、硅的氮氧化物（SiON）、铝的氧化物（AlOx）或有机材料中的任意一种或几种的组合。
本实施例以制备底栅型薄膜晶体管为例，该薄膜晶体管的半导体有源区105通过将电荷转移到与其接触表面电荷转移层104一侧得到掺杂半导体有源区105，此时半导体有源区105产生大量的空穴，转变成掺杂半导体有源区105，但半导体的导电晶格没有发生变化，因此载流子在晶格中运动时受到散射及被俘获的概率大大降低，从而使得载流子的寿命更长，迁移率更高，有利于薄膜晶体管性能的提高。
同样，底栅型且半导体有源区105设置在表面电荷转移层104下方的薄膜晶体管的制备方法与上述方法相似，区别在于：在形成栅极绝缘层103的基底上依次沉积过渡绝缘材料层、半导体有源区的材料层。顶栅型的薄膜晶体管这两层结构与本实施例的制备方法也大致相似，区别在于顶栅型薄膜晶体管的半导体有源区105和表面电荷转移层104形成于栅极绝缘层103之前，其他步骤大致相同，在此不重复追述。
实施例3
结合图8，本实施例提供了一种阵列基板，其包括实施例1中的薄膜晶体管。其中，薄膜晶体管源极107与数据信号线108连接，与薄膜晶体管漏极107连接的像素电极109。
以ADS（高级超维场转换技术（ADvanced Super DimensionSwitch），简称ADS）模式的液晶显示装置中的阵列基板为例，其还包括网状的公共电极111，且与像素电极109通过钝化层110隔开的公共电极111，存储电容的第一电极与像素电极109形成为一体，存储电容的第二电极与公共电极111形成为一体。
当然，网状电极、板状电极位置是可以互换的，也就是网状电极也可以是像素电极109，板状电极是公共电极111。
其中，优选数据信号线108与源、漏极107是同步形成的。此时可以节约成本、提高生产效率。
其中，优选像素电极109和公共电极111的材料优选为氧化铟锡（ITO）或石墨烯，也可以是其它透明的导电材料。
需要说明的是，尽管上述实施方式中，以ADS模式的液晶显示装置中的阵列基板为例进行了说明，然而，本发明不限于应用于ADS模式的液晶显示装置中的阵列基板，甚至不限于应用于液晶显示装置中的阵列基板，例如还可以应用于IPS（平面内切换）模式的液晶显示装置中的阵列基板、OLED（有机发光二极管）显示装置中的阵列基板等。
实施例4
本实施例针对实施例3的阵列基板，提供了一种阵列基板的制备方法，其中薄膜晶体管的制备与实施例2相同，在形成薄膜晶体管的同时，还包括如下步骤：
在贯穿刻蚀阻挡层106，形成用于薄膜晶体管漏极107与半导体有源区105连接的接触过孔的上方，通过构图工艺形成包括像素电极109的图形，也就是存储电容的第一电极。其中像素电极109（存储电容的第一电极）的材料为氧化铟锡或石墨烯等导电材料。
在完成上述步骤的基底101上，形成薄膜晶体管源、漏极107，并同时形成数据信号线，该数据信号线与源极107连接。
当然上述两个步骤也可以通过一次构图工艺形成，具体地说，在形成贯穿刻蚀阻挡层106用于薄膜晶体管源、漏极107连接的接触过孔的上方，依次沉积像素电极109材料层、源漏金属层，通过曝光，显影，刻蚀，剥离等工艺形成源极107、漏极107、与源极107连接的数据信号线108、与漏极107连接的像素电极109的图形。通过一次构图工艺形成源极和漏极107、数据信号线108、以及像素电极109可以提高生产效率、节约成本。
在完成上述步骤的基底101上形成钝化层110，并在钝化层110上方，通过构图工艺形成包括公共电极111的图形，也就是存储电容的第二电极。其中，公共电极111（存储电容的第二电极）材料为氧化铟锡或石墨烯等导电材料。
本实施例是以先制备像素电极109，后制备公共电极111为例，当然如果先制备公共电极111，后制备像素电极109也在本发明的保护范围内。
实施例5
本实施例提供了一种显示装置，其包括实施例3所述的阵列基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本实施例的显示装置中具有实施例3中的阵列基板，故其上的薄膜晶体管的性能明显提高，从而该显示装置的性能也有所提高。
当然，本实施例的显示装置中还可以包括其他常规结构，如电源单元、显示驱动单元等。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (12)

1.一种薄膜晶体管，其包括栅极、栅极绝缘层、半导体有源区以及与半导体有源区连接的源极和漏极，其特征在于，还包括与所述半导体有源区接触的表面电荷转移层，所述表面电荷转移层用于使所述半导体有源区在不改变晶格结构的情况下产生大量的空穴或电子。
2.根据权利要求1所述的薄膜晶体管，其特征在于，所述表面电荷转移层的材料的最低未占据分子轨道与半导体有源区的材料的价带顶能带的能级差大于等于-1ev且小于等于1ev。
3.根据权利要求1所述的薄膜晶体管，其特征在于，所述栅极设置在基底上，所述栅极绝缘层覆盖所述栅极，所述表面电荷转移层设于栅极绝缘层上方，所述半导体有源区设于所述表面电荷转移层上方。
4.根据权利要求1所述的薄膜晶体管，其特征在于，所述栅极设置在基底上，所述栅极绝缘层覆盖所述栅极，所述半导体有源区设置在栅极绝缘层上方，所述表面电荷转移层设于所述半导体有源区上方。
5.根据权利要求1所述的薄膜晶体管，其特征在于，所述表面电荷转移层和半导体有源区依次设置在基底上，所述栅极设于半导体有源区上方，且所述栅极与半导体有源区通过所述栅极绝缘层隔开。
6.根据权利要求1所述的薄膜晶体管，其特征在于，所述半导体有源区和表面电荷转移层依次设置在基底上，所述栅极设于表面电荷转移层上方，且所述栅极与表面电荷转移层通过所述栅极绝缘层隔开。
7.根据权利要求1～6中任意一项所述的薄膜晶体管，其特征在于，所述半导体有源区的材料为氧化锌。
8.根据权利要求7所述的薄膜晶体管，其特征在于，所述表面电荷转移层的材料为三氧化钼。
9.一种如权利要求1～8中任意一项所述的薄膜晶体管的制备方法，其特征在于，包括形成包括相互接触的表面电荷转移层以及半导体有源区的图形的步骤。
10.根据权利要求9所述的阵列基板的制备方法，其特征在于，所述形成薄膜晶体管的表面电荷转移层和半导体有源区是通过一次构图工艺形成的。
11.一种阵列基板，其特征在于，包括权利要求1～8中任意一项所述的薄膜晶体管。
12.一种显示装置，其特征在于，包括权利要求11所述的阵列基板。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015058562A1 (zh) * 2013-10-22 2015-04-30 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板、显示装置
WO2017076274A1 (zh) * 2015-11-05 2017-05-11 京东方科技集团股份有限公司 低温多晶硅薄膜晶体管及制作方法、阵列基板、显示面板和显示装置

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104952932A (zh) * 2015-05-29 2015-09-30 合肥鑫晟光电科技有限公司 薄膜晶体管、阵列基板及其制作方法、显示装置
CN105892747A (zh) * 2016-04-06 2016-08-24 深圳市华星光电技术有限公司 触摸显示面板、其制备方法以及触摸显示器
US11296173B2 (en) * 2017-12-08 2022-04-05 Hewlett-Packard Development Company, L.P. Dual-sided displays

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1560908A (zh) * 2004-02-25 2005-01-05 友达光电股份有限公司 薄膜晶体管的结构和制造方法
US20080296568A1 (en) * 2007-05-29 2008-12-04 Samsung Electronics Co., Ltd Thin film transistors and methods of manufacturing the same
CN101621075A (zh) * 2008-06-30 2010-01-06 三星移动显示器株式会社 薄膜晶体管及其制造方法和平板显示装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2537781B1 (fr) 1982-12-14 1986-05-30 Thomson Csf Transistor a effet de champ, fonctionnant en regime d'accumulation par gaz d'electrons
JP2005166729A (ja) 2003-11-28 2005-06-23 Seiko Epson Corp 半導体装置及びその製造方法
JP5311955B2 (ja) 2007-11-01 2013-10-09 株式会社半導体エネルギー研究所 表示装置の作製方法
EP2276087A4 (en) 2008-04-28 2015-04-29 Dainippon Printing Co Ltd DEVICE WITH LOCHINJECTION / TRANSPORT COAT, METHOD OF PRODUCTION THEREOF AND INK FOR PRODUCING THE LOCHINJECTION / TRANSPORT COAT
KR100963026B1 (ko) * 2008-06-30 2010-06-10 삼성모바일디스플레이주식회사 박막 트랜지스터, 그의 제조 방법 및 박막 트랜지스터를구비하는 평판 표시 장치
US8704216B2 (en) * 2009-02-27 2014-04-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US8975509B2 (en) 2010-06-07 2015-03-10 The Governing Council Of The University Of Toronto Photovoltaic devices with multiple junctions separated by a graded recombination layer
KR20110139394A (ko) * 2010-06-23 2011-12-29 주성엔지니어링(주) 박막 트랜지스터 및 그 제조 방법
CN103531639B (zh) 2013-10-22 2016-09-07 合肥京东方光电科技有限公司 薄膜晶体管及其制备方法、阵列基板、显示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1560908A (zh) * 2004-02-25 2005-01-05 友达光电股份有限公司 薄膜晶体管的结构和制造方法
US20080296568A1 (en) * 2007-05-29 2008-12-04 Samsung Electronics Co., Ltd Thin film transistors and methods of manufacturing the same
CN101621075A (zh) * 2008-06-30 2010-01-06 三星移动显示器株式会社 薄膜晶体管及其制造方法和平板显示装置

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
孙钦军: "有机薄膜晶体管中接触效应的研究", 《物理学报》, 30 November 2010 (2010-11-30) *
徐洁: "MoO3源漏电极缓冲层对有机薄膜晶体管性能的影响", 《电子科技大学学报》, 30 November 2012 (2012-11-30) *
石巍巍: "基于栅绝缘层表面修饰的有机场效应晶体管", 《物理学报》, 31 December 2012 (2012-12-31) *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015058562A1 (zh) * 2013-10-22 2015-04-30 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板、显示装置
US9484468B2 (en) 2013-10-22 2016-11-01 Boe Technology Group Co., Ltd. Thin film transistor and manufacturing method thereof, array substrate, and display apparatus
WO2017076274A1 (zh) * 2015-11-05 2017-05-11 京东方科技集团股份有限公司 低温多晶硅薄膜晶体管及制作方法、阵列基板、显示面板和显示装置
US10243004B2 (en) 2015-11-05 2019-03-26 Boe Technology Group Co., Ltd. Low-temperature polycrystalline silicon thin film transistor, and manufacturing method for fabricating the same, array substrate, display panel and display device

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