WO2022193706A1 - 发光面板及其制备方法、发光装置 - Google Patents

发光面板及其制备方法、发光装置 Download PDF

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Publication number
WO2022193706A1
WO2022193706A1 PCT/CN2021/131561 CN2021131561W WO2022193706A1 WO 2022193706 A1 WO2022193706 A1 WO 2022193706A1 CN 2021131561 W CN2021131561 W CN 2021131561W WO 2022193706 A1 WO2022193706 A1 WO 2022193706A1
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Prior art keywords
isolation pattern
base substrate
layer
light
orthographic projection
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PCT/CN2021/131561
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English (en)
French (fr)
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刘军
汪军
刘宁
苏同上
王海东
周斌
桂学海
刘融
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US18/275,811 priority Critical patent/US20240099057A1/en
Publication of WO2022193706A1 publication Critical patent/WO2022193706A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes

Definitions

  • the present disclosure relates to the technical field of lighting and display, and in particular, to a light-emitting panel, a method for preparing the light-emitting panel, and a light-emitting device including the light-emitting panel.
  • the shape of the light-emitting area is different from the regular rectangular light-emitting area. It is necessary to design an isolation part to perform water vapor barrier isolation on the light-emitting functional layer and the cathode to realize light-emitting in the special-shaped area; however, the current isolation part has The isolation effect is not ideal.
  • the purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art, and to provide a light-emitting panel with better isolation effect, a preparation method of the light-emitting panel, and a light-emitting device including the light-emitting panel.
  • a light emitting panel having a light emitting area and an isolation area adjacent to the light emitting area, the light emitting panel comprising:
  • a blocking structure disposed on one side of the base substrate and located in the isolation region;
  • the barrier structure includes: a first isolation pattern, a second isolation pattern, a third isolation pattern and a fourth isolation pattern that are stacked in sequence, the first isolation pattern being closer to the base substrate than the fourth isolation pattern ; the orthographic projection of the first isolation pattern on the base substrate is located within the orthographic projection of the second isolation pattern on the base substrate, and the third isolation pattern on the base substrate The orthographic projection of the fourth isolation pattern on the base substrate is within the orthographic projection of the third isolation pattern on the base substrate, and the orthographic projection of the third isolation pattern on the base substrate is located within the second isolation pattern on the base substrate in the orthographic projection on.
  • the blocking structure further includes:
  • a fifth isolation pattern is provided on a side of the fourth isolation pattern away from the base substrate, and an orthographic projection of the fifth isolation pattern on the base substrate is located on the side of the fourth isolation pattern on the base substrate. Within the orthographic projection on the base substrate, or the orthographic projection of the fourth isolation pattern on the base substrate is located within the orthographic projection of the fifth isolation pattern on the base substrate.
  • the blocking structure further includes:
  • a sixth isolation pattern is provided between the base substrate and the first isolation pattern, and the orthographic projection of the first isolation pattern on the base substrate is located on the substrate of the sixth isolation pattern in the orthographic projection on the substrate.
  • the light-emitting panel in the light-emitting area, includes:
  • each of the pixel units includes at least three sub-pixels, each of the sub-pixels includes a thin film transistor and a light-emitting unit, the thin film transistor includes a gate electrode, a gate insulating layer, an active layer, and a source electrode , a drain electrode and a planarization layer, the light emitting unit includes a first electrode, a pixel defining layer, a light emitting layer and a second electrode.
  • the first isolation pattern, the second isolation pattern and the sixth isolation pattern are provided in the same layer and material as the source electrode and the drain electrode.
  • the third isolation pattern and the planarization layer are provided in the same layer and material.
  • the fourth isolation pattern is provided in the same layer and material as the first electrode.
  • the fifth isolation pattern and the pixel defining layer are provided in the same layer and material.
  • a method for manufacturing a light-emitting panel including:
  • a base substrate is provided, the base substrate has a light-emitting region and an isolation region adjacent to the light-emitting region;
  • a first isolation pattern and a second isolation pattern are sequentially formed on one side of the base substrate and in the isolation region, and the orthographic projection of the first isolation pattern on the base substrate is located on the second isolation pattern in an orthographic projection on the base substrate;
  • a third isolation pattern and a fourth isolation pattern are sequentially formed on a side of the second isolation pattern away from the base substrate, and the orthographic projection of the third isolation pattern on the base substrate is located at the fourth isolation pattern
  • the isolation pattern is within the orthographic projection of the base substrate, and the orthographic projection of the third isolation pattern on the base substrate is located within the orthographic projection of the second isolation pattern on the base substrate.
  • the preparation method further includes:
  • An active layer, a gate insulating layer and a gate are formed on one side of the base substrate and in the light emitting region, the gate insulating layer is located between the active layer and the gate;
  • An interlayer dielectric layer is formed on the side of the active layer or the gate away from the base substrate, and a first via hole is formed on the interlayer dielectric layer, the first via hole connected to the active layer;
  • a source electrode and a drain electrode are formed on a side of the interlayer dielectric layer away from the base substrate, and the source electrode and the drain electrode are connected to the active layer through the first via hole;
  • a planarization layer is formed on the side of the source electrode and the drain electrode away from the base substrate, and a second via hole is formed on the planarization layer, and the second via hole is connected to the source pole or the drain;
  • a first electrode is formed on a side of the planarization layer away from the base substrate, and the first electrode is connected to the source electrode or the drain electrode through the second via hole;
  • a pixel defining layer is formed on a side of the first electrode away from the base substrate.
  • a first isolation layer and the second isolation pattern are sequentially formed in a patterning process of forming the source electrode and the drain electrode.
  • a third isolation layer is formed in a patterning process for forming the planarization layer, and the first isolation layer is etched to form the first isolation pattern.
  • a sixth isolation pattern is further formed in the patterning process of forming the source electrode and the drain electrode, and the sixth isolation pattern is provided between the base substrate and the drain electrode. Between the first isolation patterns, the orthographic projection of the first isolation pattern on the base substrate is located within the orthographic projection of the sixth isolation pattern on the base substrate.
  • the fourth isolation pattern is formed in a patterning process of forming the first electrode.
  • the preparation method further includes:
  • a fifth isolation pattern is formed on a side of the fourth isolation layer away from the base substrate, and the first isolation pattern is The orthographic projection of the five isolation patterns on the base substrate is located within the orthographic projection of the fourth isolation pattern on the base substrate, or the orthographic projection of the fourth isolation pattern on the base substrate is located in The fifth isolation pattern is in an orthographic projection on the base substrate.
  • a light-emitting device including the light-emitting panel described in any one of the above.
  • the barrier structure includes a first isolation pattern, a second isolation pattern, a third isolation pattern and a fourth isolation pattern which are stacked in sequence, and the first isolation pattern is closer to the substrate than the fourth isolation pattern substrate; the orthographic projection of the first isolation pattern on the base substrate is located within the orthographic projection of the second isolation pattern on the base substrate, and the orthographic projection of the third isolation pattern on the base substrate is located within the orthographic projection of the fourth isolation pattern on the base substrate In the orthographic projection of the third isolation pattern on the base substrate, the orthographic projection of the second isolation pattern on the base substrate is located within the orthographic projection of the second isolation pattern on the base substrate.
  • the base substrate, the first isolation pattern, and the second isolation pattern form a first-layer "I"-shaped structure
  • the second isolation pattern, the third isolation pattern, and the fourth isolation pattern form a second-layer "I"-shaped structure.
  • the I-shaped structure increases the difficulty of climbing the light-emitting layer and the second electrode, weakens the climbing ability of the light-emitting layer and the second electrode, increases the barrier effect, and improves the reliability of the barrier structure.
  • the second-layer "I"-shaped structure can still play a blocking role.
  • FIG. 1 is a schematic cross-sectional structural diagram of an exemplary embodiment of a light-emitting panel of the present disclosure.
  • FIG. 2 is a schematic top-view structure diagram of an exemplary embodiment of a light-emitting panel of the present disclosure.
  • FIG. 3 is a schematic flow chart of an exemplary embodiment of a manufacturing method of a light-emitting panel of the present disclosure.
  • 4 to 10 are schematic structural diagrams of various steps in the manufacturing method of the light-emitting panel of the present disclosure.
  • Planarization material layer 91. Planarization layer; 92. Second via hole;
  • A light-emitting area
  • L isolation area
  • S border area
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • Customized OLED Organic Electroluminesence Display, organic light-emitting semiconductor
  • LTPS Low Temperature Poly-Silicon, low temperature polysilicon
  • EL organic light-emitting layer 13
  • Cathode cathode
  • the blocking structure 8 is mainly used to form an I-shaped structure of TiAlTi structure, but when the reflective anode (the material of which is ITO-Ag-ITO) is subsequently formed, the etching effect of the etching solution on the Al in the I-shaped shape is faster.
  • the reflective anode the material of which is ITO-Ag-ITO
  • the etching effect of the etching solution on the Al in the I-shaped shape is faster.
  • the reflective anode is wet-etched, if the I-shaped metal structure is not protected, it will cause serious over-etching of Al in the I-shaped metal. , and even a completely Al-free structure cannot block the organic light-emitting layer 13 and the cathode. Therefore, when the reflective anode is etched, the TiAlTi structure needs to be protected. After the reflective anode is etched, a process is added to etch and indent Al to form an I-shaped structure, which adds a mask, etching
  • Embodiments of the present disclosure provide a light-emitting panel, as shown in FIG. 1 and FIG. 2 , which are schematic structural diagrams of the light-emitting panel.
  • the light-emitting panel has a light-emitting area A (also referred to as a display area (Active Area, abbreviated as Area A))
  • the isolation area L adjacent to the light emitting area A is also provided with a frame area S on the periphery of the isolation area L, and the frame area S can be provided with various leads and driving circuits.
  • the light-emitting panel includes a base substrate 1 and a blocking structure 8; the blocking structure 8 is arranged on one side of the base substrate 1 and is located in the isolation area L; the blocking structure 8 includes: a first isolation pattern 81 and a second isolation pattern 81, which are stacked in sequence.
  • the pattern 82, the third isolation pattern 83 and the fourth isolation pattern 84, the first isolation pattern 81 is closer to the base substrate 1 than the fourth isolation pattern 84; the orthographic projection of the first isolation pattern 81 on the base substrate 1 is located at the second In the orthographic projection of the isolation pattern 82 on the base substrate 1, the orthographic projection of the third isolation pattern 83 on the base substrate 1 is located within the orthographic projection of the fourth isolation pattern 84 on the base substrate 1, and the third isolation pattern 83 The orthographic projection on the base substrate 1 is located within the orthographic projection of the second isolation pattern 82 on the base substrate 1 .
  • the base substrate 1 , the first isolation pattern 81 and the second isolation pattern 82 form a first-layer "I"-shaped structure
  • the isolation pattern 84 forms a second-layer "I"-shaped structure
  • the double-layer "I"-shaped structure increases the difficulty of climbing the light-emitting layer 13 and the second electrode 14, so that the climbing ability of the light-emitting layer 13 and the second electrode 14 is weakened,
  • the barrier function is increased, and the reliability of the barrier structure 8 is improved.
  • the second-layer "I"-shaped structure can still play a blocking role.
  • the light-emitting panel can be made into a light-emitting panel with any light-emitting shape, and the shape of the blocking structure 8 extending along the edge of the light-emitting area A can be any shape.
  • the shapes of the three regions are only examples and are not limited.
  • the base substrate 1 may be a glass substrate or a PI (Polyimide, polyimide) substrate.
  • a buffer layer 2 is provided on one side of the base substrate 1 .
  • the light-emitting panel may include a plurality of pixel units arranged in an array, each pixel unit includes at least three sub-pixels, and each sub-pixel includes a thin film transistor and a light-emitting unit.
  • the structure of the thin film transistor is as follows: an active layer 3 is provided on the side of the buffer layer 2 away from the base substrate 1 .
  • a first gate insulating layer 41 is provided on the side of the active layer 3 away from the base substrate 1 , and the material of the first gate insulating layer 41 may be silicon oxide;
  • a second gate insulating layer 42 is disposed on one side, and the material of the second gate insulating layer 42 may be silicon nitride.
  • a gate 5 is provided on the side of the second gate insulating layer 42 away from the base substrate 1 , and the material of the gate 5 may be molybdenum, nickel, nickel-manganese alloy, nickel-chromium alloy, nickel-molybdenum-iron alloy, and the like.
  • An interlayer dielectric layer 6 is provided on the side of the gate 5 away from the base substrate 1 , the material of the interlayer dielectric layer 6 can be silicon oxide, and a first via hole 61 is provided on the interlayer dielectric layer 6 , the first via hole 61 is connected to the active layer 3 .
  • a source electrode 74 and a drain electrode 75 are provided on the side of the interlayer dielectric layer 6 away from the base substrate 1 .
  • the source electrode 74 and the drain electrode 75 are connected to the active layer 3 through the first via hole 61 .
  • the source electrode 74 and the drain electrode 75 The material of the drain electrode 75 may be TiAlTi (titanium-aluminum-titanium three-layer).
  • a planarization layer 91 is provided on the side of the source electrode 74 and the drain electrode 75 away from the base substrate 1, and a second via hole 92 is provided on the planarization layer 91, and the second via hole 92 can be connected to the source electrode 74, Of course, the second via hole 92 can also be connected to the drain electrode 75 .
  • the structure of the light-emitting unit is as follows: a first electrode 10 is provided on the side of the planarization layer 91 away from the base substrate 1 , the first electrode 10 is connected to the source electrode 74 through the second via hole 92 , and the first electrode 10
  • the material can be ITO-Ag-ITO (indium tin oxide-silver-indium tin oxide).
  • the second via hole 92 is connected to the drain electrode 75
  • the first electrode 10 is connected to the drain electrode 75 through the second via hole 92 .
  • a pixel defining layer 12 is disposed on the side of the first electrode 10 away from the base substrate 1 , and a third via hole is disposed on the pixel defining layer 12 .
  • the third via hole is connected to the first electrode 10 , and the first electrode 10 may is the anode.
  • a light-emitting layer 13 is provided in the third via hole, and the light-emitting layer 13 is in contact with the first electrode 10 .
  • a second electrode 14 is provided on the side of the light-emitting layer 13 away from the base substrate 1 , and the second electrode 14 may be a cathode.
  • the thin film transistor described above is of the top-gate type.
  • the thin-film transistor may also be of a bottom-gate type or a double-gate type.
  • a sixth isolation pattern 86 is provided on the side of the buffer layer 2 away from the base substrate 1, and a first isolation pattern 81 is provided on the side of the sixth isolation pattern 86 away from the base substrate 1.
  • a second isolation pattern 82 is provided on the side of the first isolation pattern 81 away from the base substrate 1
  • a third isolation pattern 83 is provided on the side of the second isolation pattern 82 away from the base substrate 1
  • a third isolation pattern 83 is provided on the side of the second isolation pattern 82 away from the base substrate 1
  • a fourth isolation pattern 84 is provided on the side of the fourth isolation pattern 83 away from the base substrate 1
  • a fifth isolation pattern 85 is provided on the side of the fourth isolation pattern 84 away from the base substrate 1 .
  • the orthographic projection of the first isolation pattern 81 on the base substrate 1 is located within the orthographic projection of the second isolation pattern 82 on the base substrate 1, and the orthographic projection of the first isolation pattern 81 on the base substrate 1 is located in the sixth isolation pattern 86 is in the orthographic projection on the base substrate 1 .
  • the sixth isolation pattern 86 , the first isolation pattern 81 and the second isolation pattern 82 form a first-layer "I"-shaped structure.
  • the orthographic projection of the third isolation pattern 83 on the base substrate 1 is located within the orthographic projection of the fourth isolation pattern 84 on the base substrate 1
  • the orthographic projection of the third isolation pattern 83 on the base substrate 1 is located within the second isolation pattern 82 is in the orthographic projection on the base substrate 1 .
  • the second isolation pattern 82, the third isolation pattern 83 and the fourth isolation pattern 84 form a second-layer "I"-shaped structure.
  • the double-layer "I"-shaped structure increases the difficulty of climbing the light-emitting layer 13 and the second electrode 14 (cathode), which weakens the climbing ability of the light-emitting layer 13 and the second electrode 14, increases the barrier effect, and improves the barrier structure 8. Reliability; and, even in the event of failure of the first-layer "I"-shaped structure, the second-layer "I"-shaped structure can still function as a barrier.
  • the fifth isolation pattern 85 further increases the height of the blocking structure 8, and the orthographic projection of the fifth isolation pattern 85 on the base substrate 1 is located within the orthographic projection of the fourth isolation pattern 84 on the base substrate 1, that is, The edge of the fifth isolation pattern 85 is concave relative to the edge of the fourth isolation pattern 84; or the orthographic projection of the fourth isolation pattern 84 on the base substrate 1 is located in the orthographic projection of the fifth isolation pattern 85 on the base substrate 1 , that is, the edge of the fifth isolation pattern 85 is protruded with respect to the edge of the fourth isolation pattern 84 .
  • the edge of the fifth isolation pattern 85 is not aligned with the edge of the fourth isolation pattern 84 , thereby further increasing the difficulty of climbing the light emitting layer 13 and the second electrode 14 , making the climbing of the light emitting layer 13 and the second electrode 14 difficult.
  • the ability is weakened, the barrier effect is increased, and the reliability of the barrier structure 8 is improved.
  • the specific structure of the blocking structure 8 is not limited to the above description.
  • the blocking structure 8 may not include the fifth isolation pattern 85, that is, a double-layer "I"-shaped structure is formed.
  • the barrier structure 8 may not include the sixth isolation pattern 86, and the first isolation pattern 81 and the second isolation pattern 82 and the base substrate 1 may also form a first-layer "I"-shaped structure. The same isolation effect can also be achieved.
  • the first isolation pattern 81, the second isolation pattern 82 and the sixth isolation pattern 86 are provided in the same layer and the same material as the source electrode 74 and the drain electrode 75. That is, the material of the sixth isolation pattern 86 is titanium, the material of the first isolation pattern 81 is aluminum, and the material of the second isolation pattern 82 is titanium.
  • the third isolation pattern 83 and the planarization layer 91 are provided in the same layer and material. Since the thickness of the planarization layer 91 is thicker, the thickness of the third isolation pattern 83 is also thicker; the overall height of the "I"-shaped structure of the second layer is increased, thereby further increasing the thickness of the light-emitting layer 13 and the second electrode 14 The difficulty of climbing makes the climbing ability of the light emitting layer 13 and the second electrode 14 weaken, which increases the barrier effect and improves the reliability of the barrier structure 8 .
  • the fourth isolation pattern 84 may be provided with the same layer and material as the first electrode 10 . That is, the material of the fourth isolation pattern 84 may be ITO-Ag-ITO (indium tin oxide-silver-indium tin oxide).
  • the fifth isolation pattern 85 may be provided with the same layer and material as the pixel defining layer 12 .
  • an embodiment of the present disclosure provides a method for manufacturing a light-emitting panel.
  • the method for manufacturing a light-emitting panel may include the following steps:
  • step S10 a base substrate 1 is provided, and the base substrate 1 has a light-emitting area A and an isolation area L adjacent to the light-emitting area A.
  • a first isolation pattern 81 and a second isolation pattern 82 are sequentially formed on one side of the base substrate 1 and in the isolation region L, and the first isolation pattern 81 is on the base substrate 1.
  • the orthographic projection is within the orthographic projection of the second isolation pattern 82 on the base substrate 1 .
  • Step S30 forming a third isolation pattern 83 and a fourth isolation pattern 84 on the side of the second isolation pattern 82 away from the base substrate 1 in sequence, and the third isolation pattern 83 is on the base substrate 1
  • the orthographic projection of the fourth isolation pattern 84 on the base substrate 1 is located within the orthographic projection of the third isolation pattern 83 on the base substrate 1, and the orthographic projection of the third isolation pattern 83 on the base substrate 1 is located in the second isolation pattern 82 is in the orthographic projection on the base substrate 1 .
  • a base substrate 1 is provided, and a buffer layer 2 is deposited and formed on one side of the base substrate 1 .
  • An active material layer is deposited on the side of the buffer layer 2 away from the base substrate 1 , and the material of the active material layer can be SiN, SiO or a-Si (amorphous silicon).
  • the thickness of SiN is greater than or equal to 0.3 ⁇ m and less than or equal to 0.7 ⁇ m; the thickness of SiO is greater than or equal to 1.0 ⁇ m and less than or equal to 1.2 ⁇ m; the thickness of a-Si is about 0.05 ⁇ m.
  • the active material layer is dehydrogenated, so as to avoid a hydrogen explosion phenomenon during the excimer laser crystallization (ELA) process, and the dehydrogenation condition may be 300°C to 350°C.
  • the excimer laser crystallization process is performed to convert the amorphous silicon into polycrystalline silicon.
  • the excimer laser crystallization process is performed to convert the amorphous silicon into polycrystalline silicon.
  • use a digital exposure machine or a mask to form a silicon island mask, and then dry-etch the active material layer, which can be dry-etched using CF4+O2; then wet strip the silicon island mask to form a silicon island pattern (active layer 3).
  • a mask is formed in the channel region, and ion implantation is performed on the non-channel region to make the polysilicon dopant conductive, and the dopant can be phosphine or borane.
  • a first gate insulating layer 41 is deposited on the side of the active layer 3 away from the base substrate 1 .
  • the material of the first gate insulating layer 41 can be SiO, and the thickness of SiO is greater than or equal to 0.03 ⁇ m and less than or equal to 0.06 ⁇ m.
  • a second gate insulating layer 42 is deposited on the side of the first gate insulating layer 41 away from the base substrate 1 .
  • the material of the second gate insulating layer 42 may be SiN, and the thickness of SiN is greater than or equal to 0.05 ⁇ m and less than or equal to 0.09 ⁇ m.
  • a gate material layer is deposited on the side of the second gate insulating layer 42 away from the base substrate 1 .
  • the thickness of the gate material layer is greater than or equal to 0.25 micrometers and less than or equal to 0.3 micrometers.
  • the CF4 flow rate can be 2000sccm ⁇ 2500sccm (standard cubic centimeter per minute, standard ml/min)
  • the O2 flow rate can be 1000sccm ⁇ 1500sccm
  • the polysilicon in contact with the source electrode 74 and the drain electrode 75 is doped and conductive by using the gate self-alignment process, and the doping can be Use phosphine or borane.
  • the mask photoresist is wet stripped, and the photoresist is wet stripped and then moderately doped to form an LDD (lightly doped drain structure) to reduce leakage current.
  • annealing is performed to repair the polysilicon (active layer 3), the first gate insulating layer 41 and the second gate insulating layer 42 (the first gate insulating layer 41 and the second gate insulating layer 42 are damaged by ion doping)
  • the annealing temperature is 500 ⁇ 600 °C.
  • An interlayer dielectric layer 6 is deposited on the side of the gate electrode 5 away from the base substrate 1.
  • the interlayer dielectric layer 6 can be a combination of SiO and SiN. The thickness is greater than or equal to 0.2 microns and less than or equal to 0.3 microns.
  • Photolithography is performed on the mask layer on the interlayer dielectric layer 6 to form a first via pattern, and then dry etching is performed on the interlayer dielectric layer 6 to form a first via hole 61.
  • the dry etching can use CF4+ O2 is performed, and the first via hole 61 is connected to the active layer 3 .
  • a first conductor layer 71 , a second conductor layer 72 and a third conductor layer 73 are sequentially deposited on the side of the interlayer dielectric layer 6 away from the base substrate 1 .
  • the conductor layer 72 and the third conductor layer 73 form a source-drain metal layer, and the material of the source-drain metal layer is, for example, Ti-Al-Ti, that is, the material of the first conductor layer 71 is Ti, and the material of the second conductor layer 72 is Al.
  • the material of the third conductor layer 73 is Ti.
  • the materials of the above-mentioned three conductor layers are only examples and are not limited, and other metals may also be used.
  • the thickness of Ti is greater than or equal to 300 angstroms and less than or equal to 600 angstroms; the thickness of Al is greater than or equal to 6000 angstroms and less than or equal to 6500 angstroms. Referring to FIG.
  • the sixth isolation pattern 86 may not be formed; the first conductor layer 71 may also not be formed in the isolation region L , the sixth isolation pattern 86 will not be formed subsequently.
  • a planarization material layer 9 is formed by coating and forming a planarization material layer 9 on a side of the source electrode 74 , the drain electrode 75 and the second isolation pattern 82 away from the base substrate 1 .
  • the planarization material layer 9 is then subjected to etching and post-baking processes to form a planarization layer 91 in the light emitting region A, and a second via hole 92 is formed on the planarization layer 91 .
  • the hole 92 is connected to the source electrode 74, of course, the second via hole 92 can also be connected to the drain electrode 75; in the isolation region L, a third isolation layer 83a is formed on the side of the second isolation pattern 82 away from the base substrate 1 , the third isolation layer 83a does not cover the side surfaces of the sixth isolation pattern 86, the first isolation layer 81a and the second isolation pattern 82.
  • the planarization layer 91 developer (TMAH tetramethyl ammonium hydroxide) will corrode the first isolation layer 81a (Al) due to alkalinity, so that the first isolation layer 81a is retracted to form the first isolation pattern 81, that is, the first isolation pattern 81 is located on the base substrate 1.
  • the orthographic projection of the second isolation pattern 82 on the base substrate 1 is located within the orthographic projection of the first isolation pattern 81 on the base substrate 1, and the orthographic projection of the first isolation pattern 81 on the base substrate 1 is located in the sixth isolation pattern 86 on the base substrate.
  • the sixth isolation pattern 86, the first isolation pattern 81 and the second isolation pattern 82 form a first-layer "I"-shaped structure. Moreover, the edges of the source electrode 74 and the drain electrode 75 located in the light emitting region A will not corrode the Al layer due to the coverage of the planarization layer 91 .
  • the thicknesses of the planarization layer 91 and the third isolation layer 83a are 1.5 micrometers or more and 2 micrometers or less.
  • the distance H1 between the edge of the first isolation pattern 81 and the edge of the second isolation pattern 82 is greater than or equal to 0.2 micrometers and less than or equal to 0.3 micrometers.
  • the mask forms a reflective anode layer mask, and wet etching is performed so that the first electrode material layer forms the first electrode 10 in the light emitting area A, and the fourth isolation pattern 84 is formed in the isolation area L;
  • the first isolation pattern 81 (Al) of the isolation region L is also etched so that the distance H1 between the edge of the first isolation pattern 81 and the edge of the second isolation pattern 82 is larger, which further increases the light-emitting layer 13 and the edge of the second isolation pattern 82.
  • the difficulty of climbing the second electrode 14 increases the blocking effect.
  • a protective layer 11 is formed on the side of the first electrode 10 away from the base substrate 1 and the sidewall of the interlayer dielectric layer, the planarization layer and the first electrode, and the fourth isolation pattern 84 is formed.
  • the protective layer 11 is not formed on the side away from the base substrate 1, that is, the protective layer 11 is formed in the light emitting region, and the protective layer 11 is not formed in the isolation region.
  • the thickness of the protective layer 11 is greater than or equal to 2.5 micrometers and less than or equal to 3 micrometers.
  • the third isolation layer 83a is ashed to form the third isolation pattern 83.
  • the third isolation layer 83a Since the side of the third isolation layer 83a close to the base substrate 1 is protected by the second isolation pattern 82, the third isolation layer 83a is far away from the lining. One side of the base substrate 1 is protected by the fourth isolation pattern 84, while the sidewall of the third isolation layer 83a does not have any protective layer 11.
  • the ashing process will etch the sidewall of the third isolation layer 83a to form the third isolation pattern 83, so that the orthographic projection of the third isolation pattern 83 on the base substrate 1 is located within the orthographic projection of the fourth isolation pattern 84 on the base substrate 1, and the orthographic projection of the third isolation pattern 83 on the base substrate 1 is located in In the orthographic projection of the second isolation pattern 82 on the base substrate 1 , the second isolation pattern 82 , the third isolation pattern 83 and the fourth isolation pattern 84 form a second-layer "I"-shaped structure.
  • the protective layer 11 is subjected to an ashing process to remove the protective layer 11; the ashing process can be performed with pure O2, CF4+O2 or SF6+O2.
  • the protective layer 11 is ashed to 2 ⁇ m or more and 2.5 ⁇ m or less, so that the distance H2 between the edge of the third isolation pattern 83 and the edge of the fourth isolation pattern 84 is greater than or equal to 0.5 ⁇ m and less than or equal to 0.75 ⁇ m. .
  • a pixel-defining material layer is formed on the side of the first electrode 10 and the fourth isolation pattern 84 away from the base substrate 1 , and the thickness of the pixel-defining material layer is greater than or equal to 1.4 ⁇ m and less than or equal to 1.8 ⁇ m. Then, the pixel-defining material layer is etched through the processes of exposure, development and post-baking. In the light emitting area A, the pixel-defining material layer forms the pixel-defining layer 12, and a third via hole is formed on the pixel-defining layer 12. The third via hole Connected to the first electrode 10 ; in the isolation region L, the pixel defining material layer forms a fifth isolation pattern 85 .
  • the fifth isolation pattern 85 further increases the height of the blocking structure 8, and the orthographic projection of the fifth isolation pattern 85 on the base substrate 1 is located within the orthographic projection of the fourth isolation pattern 84 on the base substrate 1, namely the fifth
  • the edge of the isolation pattern 85 is concave relative to the edge of the fourth isolation pattern 84; or the orthographic projection of the fourth isolation pattern 84 on the base substrate 1 is located within the orthographic projection of the fifth isolation pattern 85 on the base substrate 1, That is, the edge of the fifth isolation pattern 85 is protruded with respect to the edge of the fourth isolation pattern 84 .
  • the edge of the fifth isolation pattern 85 is not aligned with the edge of the fourth isolation pattern 84 , thereby further increasing the difficulty of climbing the light emitting layer 13 and the second electrode 14 , making the climbing of the light emitting layer 13 and the second electrode 14 difficult.
  • the ability is weakened, the barrier effect is increased, and the reliability of the barrier structure 8 is improved.
  • the fifth isolation pattern 85 may not be formed on the side of the fourth isolation pattern 84 away from the base substrate 1 .
  • a light-emitting material layer is formed on the side of the pixel defining layer 12 away from the base substrate 1, and the light-emitting material layer is etched to form a light-emitting layer 13.
  • the light-emitting layer 13 is located in the third via hole, and the light-emitting layer 13 and the first electrode 10 connect.
  • a second electrode 14 is formed on the side of the light-emitting layer 13 away from the base substrate 1 , and the second electrode 14 is connected to the light-emitting layer 13 .
  • the second electrode 14 may be a cathode.
  • an embodiment of the present disclosure provides a light-emitting device, and the light-emitting device may include the light-emitting panel described in any one of the above.
  • the specific structure of the light-emitting panel has been described in detail above, so it will not be repeated here.
  • the lighting device may be a lighting device or a display device.
  • the specific type of the light-emitting device is not particularly limited, and any type of lighting device or display device commonly used in the art can be used.
  • the light-emitting device is a display device, such as a mobile device such as a mobile phone, a wearable device such as a watch, a VR device, etc.
  • those skilled in the art can make corresponding selections according to the specific use of the display device, which is not repeated here. Repeat.
  • the light-emitting device also includes other necessary components and components. Take a display as an example, such as a casing, a circuit board, a power cord, etc. The specific usage requirements will be supplemented accordingly, which will not be repeated here.
  • the beneficial effects of the light-emitting device provided by the exemplary embodiments of the present disclosure are the same as the beneficial effects of the light-emitting panel provided by the above-described exemplary embodiments, which will not be repeated here.

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Abstract

一种发光面板及其制备方法、发光装置，涉及照明与显示技术领域；该发光面板具有发光区（A）和与发光区（A）相邻的隔离区（L），该发光面板包括衬底基板（1）和阻隔结构（8）；阻隔结构（8）设置于衬底基板（1）的一侧且位于隔离区（L）；包括依次层叠设置的第一隔离图案（81）、第二隔离图案（82）、第三隔离图案（83）和第四隔离图案（84），第一隔离图案（81）比第四隔离图案（84）更靠近衬底基板（1）；第一隔离图案（81）在衬底基板（1）上的正投影位于第二隔离图案（82）在衬底基板（1）上的正投影内，第三隔离图案（83）在衬底基板（1）上的正投影位于第四隔离图案（84）在衬底基板（1）上的正投影内，第三隔离图案（83）在衬底基板（1）上的正投影位于第二隔离图案（82）在衬底基板（1）上的正投影内。该发光面板的阻隔结构（8）形成双层"工"字形结构，阻隔效果好。

Description

发光面板及其制备方法、发光装置
交叉引用
本公开要求于2021年3月19日提交的申请号为202110295622.1名称为“发光面板及其制备方法、发光装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及照明与显示技术领域，具体而言，涉及一种发光面板及发光面板的制备方法、包括该发光面板的发光装置。
背景技术
随着对异形发光的要求越来越多，发光区的形状不同于规则的矩形发光区，需要设计隔离部对发光功能层以及阴极进行水汽阻挡隔离以实现异形区域发光；但是，目前隔离部的隔离效果不理想。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于克服上述现有技术的不足，提供一种隔离效果较好的发光面板及发光面板的制备方法、包括该发光面板的发光装置。
根据本公开的一个方面，提供了一种发光面板，具有发光区和与所述发光区相邻的隔离区，所述发光面板包括：
衬底基板；
阻隔结构，设置于所述衬底基板的一侧，且位于所述隔离区；
所述阻隔结构包括：依次层叠设置的第一隔离图案、第二隔离图案、第三隔离图案和第四隔离图案，所述第一隔离图案比所述第四隔离图案更靠近所述衬底基板；所述第一隔离图案在所述衬底基板上的正投影位于所述第二隔离图案在所述衬底基板上的正投影内，所述第三隔离图案 在所述衬底基板上的正投影位于所述第四隔离图案在所述衬底基板上的正投影内，所述第三隔离图案在所述衬底基板上的正投影位于所述第二隔离图案在所述衬底基板上的正投影内。
在本公开的一种示例性实施例中，所述阻隔结构还包括：
第五隔离图案，设于所述第四隔离图案的远离所述衬底基板的一侧，所述第五隔离图案在所述衬底基板上的正投影位于所述第四隔离图案在所述衬底基板上的正投影内，或所述第四隔离图案在所述衬底基板上的正投影位于所述第五隔离图案在所述衬底基板上的正投影内。
在本公开的一种示例性实施例中，所述阻隔结构还包括：
第六隔离图案，设于所述衬底基板与所述第一隔离图案之间，所述第一隔离图案在所述衬底基板上的正投影位于所述第六隔离图案在所述衬底基板上的正投影内。
在本公开的一种示例性实施例中，在所述发光区，所述发光面板包括：
多个阵列排布的像素单元，各个所述像素单元包括至少三个子像素，各个所述子像素包括薄膜晶体管和发光单元，所述薄膜晶体管包括栅极、栅绝缘层、有源层、源极、漏极和平坦化层，所述发光单元包括第一电极、像素界定层、发光层和第二电极。
在本公开的一种示例性实施例中，所述第一隔离图案、所述第二隔离图案和所述第六隔离图案与所述源极和所述漏极同层同材料设置。
在本公开的一种示例性实施例中，所述第三隔离图案与所述平坦化层同层同材料设置。
在本公开的一种示例性实施例中，所述第四隔离图案与所述第一电极同层同材料设置。
在本公开的一种示例性实施例中，所述第五隔离图案与所述像素界定层同层同材料设置。
根据本公开的另一个方面，提供了一种发光面板的制备方法，包括：
提供一衬底基板，所述衬底基板具有发光区和与所述发光区相邻的隔离区；
在所述衬底基板的一侧且在所述隔离区依次形成第一隔离图案和第 二隔离图案，所述第一隔离图案在所述衬底基板上的正投影位于所述第二隔离图案在所述衬底基板上的正投影内；
在所述第二隔离图案的远离所述衬底基板的一侧依次形成第三隔离图案和第四隔离图案，所述第三隔离图案在所述衬底基板上的正投影位于所述第四隔离图案在所述衬底基板上的正投影内，所述第三隔离图案在所述衬底基板上的正投影位于所述第二隔离图案在所述衬底基板上的正投影内。
在本公开的一种示例性实施例中，所述制备方法还包括：
在所述衬底基板的一侧且在所述发光区形成有源层、栅绝缘层以及栅极，所述栅绝缘层位于所述有源层与所述栅极之间；
在所述有源层或所述栅极的远离所述衬底基板的一侧形成层间介电层，并在所述层间介电层上形成第一过孔，所述第一过孔连通至所述有源层；
在所述层间介电层的远离所述衬底基板的一侧形成源极和漏极，所述源极和所述漏极通过所述第一过孔与所述有源层连接；
在所述源极和所述漏极的远离所述衬底基板的一侧形成平坦化层，且在所述平坦化层上形成第二过孔，所述第二过孔连通至所述源极或所述漏极；
在所述平坦化层的远离所述衬底基板的一侧形成第一电极，所述第一电极通过所述第二过孔与所述源极或所述漏极连接；
在所述第一电极的远离所述衬底基板的一侧形成像素界定层。
在本公开的一种示例性实施例中，在形成所述源极和所述漏极的构图工艺中依次形成第一隔离层和所述第二隔离图案。
在本公开的一种示例性实施例中，在形成所述平坦化层的构图工艺中形成第三隔离层，并对所述第一隔离层进行刻蚀形成所述第一隔离图案。
在本公开的一种示例性实施例中，在形成所述源极和所述漏极的构图工艺中还形成第六隔离图案，所述第六隔离图案设于所述衬底基板与所述第一隔离图案之间，所述第一隔离图案在所述衬底基板上的正投影位于所述第六隔离图案在所述衬底基板上的正投影内。
在本公开的一种示例性实施例中，在形成所述第一电极的构图工艺中形成所述第四隔离图案。
在本公开的一种示例性实施例中，形成所述第一电极和所述第四隔离图案后，所述制备方法还包括：
在所述第一电极的远离所述衬底基板的一侧以及所述层间介电层、所述平坦化层和所述第一电极的侧壁形成保护层；
对第三隔离层进行灰化形成所述第三隔离图案，使所述第三隔离图案在所述衬底基板上的正投影位于所述第四隔离图案在所述衬底基板上的正投影内，且所述第三隔离图案在所述衬底基板上的正投影位于所述第二隔离图案在所述衬底基板上的正投影内。
在本公开的一种示例性实施例中，在形成所述像素界定层的构图工艺中，在所述第四隔离层的远离所述衬底基板的一侧形成第五隔离图案，所述第五隔离图案在所述衬底基板上的正投影位于所述第四隔离图案在所述衬底基板上的正投影内，或所述第四隔离图案在所述衬底基板上的正投影位于所述第五隔离图案在所述衬底基板上的正投影内。
根据本公开的再一个方面，提供了一种发光装置，包括上述任意一项所述的发光面板。
本公开的发光面板及其制备方法，阻隔结构包括依次层叠设置的第一隔离图案、第二隔离图案、第三隔离图案和第四隔离图案，第一隔离图案比第四隔离图案更靠近衬底基板；第一隔离图案在衬底基板上的正投影位于第二隔离图案在衬底基板上的正投影内，第三隔离图案在衬底基板上的正投影位于第四隔离图案在衬底基板上的正投影内，第三隔离图案在衬底基板上的正投影位于第二隔离图案在衬底基板上的正投影内。衬底基板、第一隔离图案以及第二隔离图案形成第一层“工”字形结构，第二隔离图案、第三隔离图案以及第四隔离图案形成第二层“工”字形结构，双层“工”字形结构增加了发光层和第二电极的爬坡难度，使得发光层和第二电极的爬坡能力减弱，增加了阻隔作用，提升阻隔结构的可靠性。而且，即使在第一层“工”字形结构失效的情况下，第二层“工”字形结构仍然能够起到阻隔作用。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解 释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开发光面板一示例实施方式的剖视结构示意图。
图2为本公开发光面板一示例实施方式的俯视结构示意图。
图3为本公开发光面板的制备方法一示例实施方式的流程示意框图。
图4-图10为本公开发光面板的制备方法中各个步骤的结构示意图。
附图标记说明：
1、衬底基板；2、缓冲层；3、有源层；
41、第一栅绝缘层；42、第二栅绝缘层；
5、栅极；
6、层间介电层；61、第一过孔；
71、第一导体层；72、第二导体层；73、第三导体层；74、源极；75、漏极；
8、阻隔结构；81、第一隔离图案；81a、第一隔离层；82、第二隔离图案；83、第三隔离图案；83a、第三隔离层；84、第四隔离图案；85、第五隔离图案；86、第六隔离图案；
9、平坦化材料层；91、平坦化层；92、第二过孔；
10、第一电极；11、保护层；12、像素界定层；13、发光层；14、第二电极；
A、发光区；L、隔离区；S、边框区。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
定制化OLED(OrganicElectroluminesence Display，有机发光半导体)作为一个新兴技术受到广泛关注，其目前主要利用LTPS(Low Temperature Poly-Silicon，低温多晶硅)作为沟道层进行背板技术，由于是定制化发光，其发光形状与主流矩形不一致，需要设计阻隔结构8(RIB)对有机发光层13(EL)以及阴极(Cathode)进行相关阻挡隔离以增加阻断水汽入侵途径提高封装可靠性，而且此种方式可以匹配正常打印相关工艺。
目前，阻隔结构8主要以形成TiAlTi结构工字形结构，但由于后续形成反射阳极(其材质为ITO-Ag-ITO)时，刻蚀液对工字形中Al的刻蚀作用较快，如果在对反射阳极进行湿法刻蚀的时候，不对工字形金属结构进行保护的话，会对工字形金属中的Al造成严重的过刻蚀，过刻蚀会导致工字形顶部的Ti塌陷，导致工字形失效，甚至完全无Al的结构 无法对有机发光层13和阴极起到阻隔作用。因此，在对反射阳极进行刻蚀时，需要对TiAlTi结构进行保护，在反射阳极刻蚀后再增加一道工序对Al进行刻蚀缩进形成工字形结构，这就增加一道掩膜、刻蚀和剥离工艺使得工艺复杂度增加。
本公开实施方式提供了一种发光面板，如图1和图2所示的发光面板的结构示意图，该发光面板具有发光区A(也可以称为显示区(Active Area，简称为A区))和与发光区A相邻的隔离区L，在隔离区L的外围还设置有边框区S，边框区S可以设置各种引线和驱动电路等等。该发光面板包括衬底基板1和阻隔结构8；阻隔结构8设置于衬底基板1的一侧，且位于隔离区L；阻隔结构8包括：依次层叠设置的第一隔离图案81、第二隔离图案82、第三隔离图案83和第四隔离图案84，第一隔离图案81比第四隔离图案84更靠近衬底基板1；第一隔离图案81在衬底基板1上的正投影位于第二隔离图案82在衬底基板1上的正投影内，第三隔离图案83在衬底基板1上的正投影位于第四隔离图案84在衬底基板1上的正投影内，第三隔离图案83在衬底基板1上的正投影位于第二隔离图案82在衬底基板1上的正投影内。
本公开的发光面板及其制备方法，衬底基板1、第一隔离图案81以及第二隔离图案82形成第一层“工”字形结构，第二隔离图案82、第三隔离图案83以及第四隔离图案84形成第二层“工”字形结构，双层“工”字形结构增加了发光层13和第二电极14的爬坡难度，使得发光层13和第二电极14的爬坡能力减弱，增加了阻隔作用，提升阻隔结构8的可靠性。而且，即使在第一层“工”字形结构失效的情况下，第二层“工”字形结构仍然能够起到阻隔作用。
根据该发光面板可以被做成具有任意发光形状的发光面板，该阻隔结构8沿发光区A的边沿延伸的形状可以为任意形状。图2中，三个区(发光区A、隔离区L、边框区S)的形状，仅是示例，不做限定。
在本示例实施方式中，衬底基板1可以为玻璃基板或PI(Polyimide，聚酰亚胺)基板。
在衬底基板1的一侧设置有缓冲层2。
在发光区A，发光面板可以包括多个阵列排布的像素单元，各个像 素单元包括至少三个子像素，各个子像素包括薄膜晶体管和发光单元。
具体地，薄膜晶体管的结构为：在缓冲层2的远离衬底基板1的一侧设置有有源层3。在有源层3的远离衬底基板1的一侧设置有第一栅绝缘层41，第一栅绝缘层41的材质可以是氧化硅；在第一栅绝缘层41的远离衬底基板1的一侧设置有第二栅绝缘层42，第二栅绝缘层42的材质可以是氮化硅。在第二栅绝缘层42的远离衬底基板1的一侧设置有栅极5，栅极5的材质可以是钼、镍、镍锰合金、镍铬合金以及镍钼铁合金等等。在栅极5的远离衬底基板1的一侧设置有层间介电层6，层间介电层6的材质可以是氧化硅，在层间介电层6上设置有第一过孔61，第一过孔61连通至有源层3。在层间介电层6的远离衬底基板1的一侧设置有源极74和漏极75，源极74和漏极75通过第一过孔61与有源层3连接，源极74和漏极75的材质可以是TiAlTi(钛铝钛三层)。在源极74和漏极75的远离衬底基板1的一侧设置有平坦化层91，在平坦化层91上设置有第二过孔92，第二过孔92可以连接至源极74，当然，第二过孔92也可以连接至漏极75。
具体地，发光单元的结构为：在平坦化层91的远离衬底基板1的一侧设置有第一电极10，第一电极10通过第二过孔92与源极74连接，第一电极10的材质可以是ITO-Ag-ITO(氧化铟锡-银-氧化铟锡)。当然，在第二过孔92连接至漏极75的情况下，第一电极10通过第二过孔92与漏极75连接。在第一电极10的远离衬底基板1的一侧设置有像素界定层12，在像素界定层12上设置有第三过孔，第三过孔连通至第一电极10，第一电极10可以是阳极。在第三过孔内设置有发光层13，发光层13与第一电极10接触。在发光层13的远离衬底基板1的一侧设置有第二电极14，第二电极14可以是阴极。
上述说明的薄膜晶体管为顶栅型，当然，在本公开的其他示例实施方式中，薄膜晶体管还可以是底栅型或双栅型。
在隔离区L，在缓冲层2的远离衬底基板1的一侧设置有第六隔离图案86，在第六隔离图案86的远离衬底基板1的一侧设置有第一隔离图案81，在第一隔离图案81的远离衬底基板1的一侧设置有第二隔离图案82，在第二隔离图案82的远离衬底基板1的一侧设置有第三隔离 图案83，在第三隔离图案83的远离衬底基板1的一侧设置有第四隔离图案84，在第四隔离图案84的远离衬底基板1的一侧设置有第五隔离图案85。
第一隔离图案81在衬底基板1上的正投影位于第二隔离图案82在衬底基板1上的正投影内，第一隔离图案81在衬底基板1上的正投影位于第六隔离图案86在衬底基板1上的正投影内。第六隔离图案86、第一隔离图案81以及第二隔离图案82形成第一层“工”字形结构。
第三隔离图案83在衬底基板1上的正投影位于第四隔离图案84在衬底基板1上的正投影内，第三隔离图案83在衬底基板1上的正投影位于第二隔离图案82在衬底基板1上的正投影内。第二隔离图案82、第三隔离图案83以及第四隔离图案84形成第二层“工”字形结构。
双层“工”字形结构增加了发光层13和第二电极14(阴极)的爬坡难度，使得发光层13和第二电极14的爬坡能力减弱，增加了阻隔作用，提升阻隔结构8的可靠性；而且，即使在第一层“工”字形结构失效的情况下，第二层“工”字形结构仍然能够起到阻隔作用。
另外，第五隔离图案85进一步增加了阻隔结构8的高度，而且，第五隔离图案85在衬底基板1上的正投影位于第四隔离图案84在衬底基板1上的正投影内，即第五隔离图案85的边缘相对于第四隔离图案84的边缘是凹陷的；或第四隔离图案84在衬底基板1上的正投影位于第五隔离图案85在衬底基板1上的正投影内，即第五隔离图案85的边缘相对于第四隔离图案84的边缘是突出的。也就是说第五隔离图案85的边缘与第四隔离图案84的边缘没有对齐，从而进一步增加了发光层13和第二电极14的爬坡难度，使得发光层13和第二电极14的爬坡能力减弱，增加了阻隔作用，提升阻隔结构8的可靠性。
需要说明的是，阻隔结构8的具体结构不限于上述说明，例如，阻隔结构8可以不包括第五隔离图案85，即形成双层“工”字形结构。
另外，阻隔结构8也可以不包括第六隔离图案86，第一隔离图案81以及第二隔离图案82与衬底基板1也可以形成第一层“工”字形结构。也能够达到同样的隔离效果。
在本示例实施方式中，第一隔离图案81、第二隔离图案82和第六 隔离图案86与源极74和漏极75同层同材料设置。即第六隔离图案86的材质是钛，第一隔离图案81的材质是铝，第二隔离图案82的材质是钛。
在本示例实施方式中，第三隔离图案83与平坦化层91同层同材料设置。由于平坦化层91的厚度较厚，因此，第三隔离图案83的厚度也较厚；提高了第二层“工”字形结构的整体高度，从而进一步增加了发光层13和第二电极14的爬坡难度，使得发光层13和第二电极14的爬坡能力减弱，增加了阻隔作用，提升阻隔结构8的可靠性。
在本示例实施方式中，第四隔离图案84可以与第一电极10同层同材料设置。即第四隔离图案84的材质可以是ITO-Ag-ITO(氧化铟锡-银-氧化铟锡)。
在本示例实施方式中，第五隔离图案85可以与像素界定层12同层同材料设置。
需要说明的是，所谓的同层同材料设置指的是通过同一次构图工艺形成，在下面的发光面板的制备方法中会进行详细说明。
进一步的，本公开实施方式提供了一种发光面板的制备方法，参照图3所示的发光面板的制备方法的流程示意框图，该发光面板的制备方法可以包括以下步骤：
步骤S10，提供一衬底基板1，所述衬底基板1具有发光区A和与所述发光区A相邻的隔离区L。
步骤S20，在所述衬底基板1的一侧且在所述隔离区L依次形成第一隔离图案81和第二隔离图案82，所述第一隔离图案81在所述衬底基板1上的正投影位于所述第二隔离图案82在所述衬底基板1上的正投影内。
步骤S30，在所述第二隔离图案82的远离所述衬底基板1的一侧依次形成第三隔离图案83和第四隔离图案84，所述第三隔离图案83在所述衬底基板1上的正投影位于所述第四隔离图案84在所述衬底基板1上的正投影内，所述第三隔离图案83在所述衬底基板1上的正投影位于所述第二隔离图案82在所述衬底基板1上的正投影内。
下面对发光面板的制备方法的各个步骤进行详细说明。
参照图4所示。
提供一衬底基板1，在衬底基板1的一侧沉积形成缓冲层2。
在缓冲层2的远离衬底基板1的一侧沉积形成有源材料层，有源材料层的材质可以是SiN、SiO或a-Si(非晶硅)。SiN的厚度大于等于0.3微米且小于等于0.7微米；SiO的厚度大于等于1.0微米且小于等于1.2微米；a-Si的厚度大约为0.05微米。然后对有源材料层进行去氢，以避免在准分子激光晶化(ELA)工艺时出现氢爆现象，去氢条件可为300℃～350℃。去氢完成后进行准分子激光晶化工艺，将非晶硅转化为多晶硅。最后，使用数字曝光机或者掩膜形成硅岛掩膜，而后对有源材料层进行干刻，可以使用CF4+O2进行干刻；然后湿法剥离硅岛掩膜后形成硅岛图形(有源层3)。在沟道区形成掩膜，对非沟道区进行离子注入使多晶硅掺杂导体化，掺杂可使用磷烷或者硼烷。
在有源层3的远离衬底基板1的一侧沉积形成第一栅绝缘层41，第一栅绝缘层41的材质可以为SiO，SiO的厚度大于等于0.03微米且小于等于0.06微米。在第一栅绝缘层41的远离衬底基板1的一侧沉积形成第二栅绝缘层42，第二栅绝缘层42的材质可以为SiN，SiN的厚度大于等于0.05微米且小于等于0.09微米。
在第二栅绝缘层42的远离衬底基板1的一侧沉积形成栅极材料层，栅极材料层的材质可以是钼、镍、镍锰合金、镍铬合金以及镍钼铁合金等等。栅极材料层的厚度大于等于0.25微米且小于等于0.3微米。使用数字曝光机或者掩膜形成栅极掩膜，随后使用CF4+O2进行干法刻蚀，可采用高CF4+低O2干刻混合气体进行，具体地，CF4流量可为2000sccm～2500sccm(standard cubic centimeter per minute，标准毫升/分钟)，O2流量可为1000sccm～1500sccm，干刻刻蚀后使用栅极自对准工艺对与源极74和漏极75接触的多晶硅进行掺杂导体化，掺杂可使用磷烷或者硼烷。然后湿法剥离掩膜光阻，湿法剥离光阻后再进行中等掺杂以形成LDD(轻掺杂漏结构)减少漏电流。而后进行退火以修复受离子掺杂损伤的多晶硅(有源层3)、第一栅绝缘层41和第二栅绝缘层42(第一栅绝缘层41和第二栅绝缘层42在离子注入的时候因离子掺杂轰击会造成晶格紊乱需要退火进行修复)，退火温度500～600℃。
在栅极5的远离衬底基板1的一侧沉积形成层间介电层6，层间介电层6可以是SiO和SiN的组合，SiO的厚度大于等于0.2微米且小于等于0.5微米，SiN的厚度大于等于0.2微米且小于等于0.3微米。对层间介电层6上的掩模层进行光刻形成第一过孔图形，然后对层间介电层6进行干法刻蚀形成第一过孔61，干法刻蚀可采用CF4+O2进行，第一过孔61连接至有源层3。
参照图5所示，在层间介电层6的远离衬底基板1的一侧依次沉积第一导体层71、第二导体层72和第三导体层73，第一导体层71、第二导体层72和第三导体层73形成源漏金属层，源漏金属层的材质比如为Ti-Al-Ti，即第一导体层71的材质为Ti，第二导体层72的材质为Al，第三导体层73的材质为Ti。需要说明的是，上述三个导体层(第一导体层71、第二导体层72和第三导体层73)的材质仅为示例，不做限定，也可以为其他金属。Ti的厚度大于等于300埃且小于等于600埃；Al的厚度大于等于6000埃且小于等于6500埃。参照图6所示，使用数字曝光机或者掩膜形成源漏层掩膜，使用Cl2+O2对源漏金属层进行刻蚀在发光区A形成源极74和漏极75，在隔离区L形成第六隔离图案86、第一隔离层81a和第二隔离图案82。
当然，在本公开的其他示例实施方式中，在源漏金属层不包括第一导体层71的情况下，可以不形成第六隔离图案86；也可以在隔离区L不形成第一导体层71，后续就不会形成第六隔离图案86。
参照图7所示，在源极74、漏极75以及第二隔离图案82的远离衬底基板1的一侧涂覆形成平坦化材料层9。参照图8所示，然后对平坦化材料层9进行刻蚀和后烘工艺，使其在发光区A形成平坦化层91，且在平坦化层91上形成第二过孔92，第二过孔92连接至源极74，当然，也可以是第二过孔92连接至漏极75；在隔离区L，在第二隔离图案82的远离衬底基板1的一侧形成第三隔离层83a，第三隔离层83a没有覆盖第六隔离图案86、第一隔离层81a和第二隔离图案82的侧面，因此，在对平坦化材料层9进行刻蚀的过程中，平坦化层91显影液(TMAH四甲基氢氧化铵)因碱性会对第一隔离层81a(Al)腐蚀，使第一隔离层81a内缩形成第一隔离图案81，即第一隔离图案81在衬底基板1上 的正投影位于第二隔离图案82在所述衬底基板1上的正投影内，且第一隔离图案81在衬底基板1上的正投影位于第六隔离图案86在所述衬底基板1上的正投影内，第六隔离图案86、第一隔离图案81和第二隔离图案82形成第一层“工”字形结构。而且位于发光区A的源极74和漏极75的边缘由于有平坦化层91的覆盖不会对Al层进行腐蚀。
平坦化层91和第三隔离层83a的厚度大于等于1.5微米且小于等于2微米。第一隔离图案81的边沿与第二隔离图案82的边沿之间的距离H1大于等于0.2微米且小于等于0.3微米。
参照图9所示，在平坦化层91和第三隔离层83a的远离衬底基板1的一侧依次沉积ITO、Ag和ITO，ITO、Ag和ITO形成第一电极材料层；使用数字曝光机或者掩膜形成反射阳极层掩膜，进行湿法刻蚀使第一电极材料层在发光区A形成第一电极10，在隔离区L形成第四隔离图案84；在对第一电极材料层湿刻时同样会对隔离区L的第一隔离图案81(Al)刻蚀使得第一隔离图案81的边沿与第二隔离图案82的边沿之间的距离H1更大，进一步增加了发光层13和第二电极14的爬坡难度，增加了阻隔作用。
参照图10所示，在第一电极10的远离衬底基板1的一侧以及层间介电层、平坦化层和第一电极的侧壁涂覆形成保护层11，在第四隔离图案84的远离衬底基板1的一侧没有形成保护层11，即在发光区形成有保护层11，在隔离区没有形成保护层11。保护层11的厚度大于等于2.5微米且小于等于3微米。然后对第三隔离层83a进行灰化处理形成第三隔离图案83，由于第三隔离层83a的靠近衬底基板1的一侧有第二隔离图案82的保护，第三隔离层83a的远离衬底基板1的一侧有第四隔离图案84的保护，而第三隔离层83a的侧壁没有任何保护层11，灰化工艺会对第三隔离层83a的侧壁进行腐蚀形成第三隔离图案83，从而使第三隔离图案83在衬底基板1上的正投影位于第四隔离图案84在衬底基板1上的正投影内，第三隔离图案83在衬底基板1上的正投影位于第二隔离图案82在衬底基板1上的正投影内，第二隔离图案82、第三隔离图案83以及第四隔离图案84形成第二层“工”字形结构。在对第三隔离层83a进行灰化工艺的同时会对保护层11进行灰化工艺，以去除保护层 11；灰化工艺可用纯O2、CF4+O2或SF6+O2进行。保护层11灰化大于等于2微米且小于等于2.5微米，从而使得第三隔离图案83的边沿与第四隔离图案84的边沿之间的距离H2大于等于0.5微米且小于等于0.75微米。.
参照图1所示，在第一电极10和第四隔离图案84的远离衬底基板1的一侧涂覆形成像素界定材料层，像素界定材料层的厚度大于等于1.4微米且小于等于1.8微米。然后通过曝光、显影以及后烘工序对像素界定材料层进行刻蚀，在发光区A，像素界定材料层形成像素界定层12，并在像素界定层12上形成第三过孔，第三过孔连通至第一电极10；在隔离区L，像素界定材料层形成第五隔离图案85。第五隔离图案85进一步增加了阻隔结构8的高度，而且，第五隔离图案85在衬底基板1上的正投影位于第四隔离图案84在衬底基板1上的正投影内，即第五隔离图案85的边缘相对于第四隔离图案84的边缘是凹陷的；或第四隔离图案84在衬底基板1上的正投影位于第五隔离图案85在衬底基板1上的正投影内，即第五隔离图案85的边缘相对于第四隔离图案84的边缘是突出的。也就是说第五隔离图案85的边缘与第四隔离图案84的边缘没有对齐，从而进一步增加了发光层13和第二电极14的爬坡难度，使得发光层13和第二电极14的爬坡能力减弱，增加了阻隔作用，提升阻隔结构8的可靠性。
当然，在本公开的其他示例实施方式中，在第四隔离图案84的远离衬底基板1的一侧可以不形成第五隔离图案85。
在像素界定层12的远离衬底基板1的一侧形成发光材料层，并对发光材料层进行刻蚀形成发光层13，发光层13位于第三过孔内，发光层13与第一电极10连接。
在发光层13的远离衬底基板1的一侧形成第二电极14，第二电极14与发光层13连接。第二电极14可以为阴极。
需要说明的是，尽管在附图中以特定顺序描述了本公开中发光面板的制备方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行， 以及/或者将一个步骤分解为多个步骤执行等。
进一步的，本公开实施方式提供了一种发光装置，该发光装置可以包括上述任意一项所述的发光面板。发光面板的具体结构上述已经进行了详细说明，因此，此处不再赘述。
在功能上，该发光装置可以为照明装置或者显示装置。且该发光装置的具体类型不受特别的限制，本领域常用的照明装置或者显示装置类型均可。在该发光装置为显示装置的情况下，具体例如手机等移动装置、手表等可穿戴设备、VR装置等等，本领域技术人员可根据该显示设备的具体用途进行相应地选择，在此不再赘述。
需要说明的是，该发光装置除了发光面板以外，还包括其他必要的部件和组成，以显示器为例，具体例如外壳、电路板、电源线，等等，本领域技术人员可根据该发光装置的具体使用要求进行相应地补充，在此不再赘述。
与现有技术相比，本公开示例实施方式提供的发光装置的有益效果与上述示例实施方式提供的发光面板的有益效果相同，在此不做赘述。
本领域技术人员在考虑说明书及实践这里公开的公开后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (17)

  1. 一种发光面板，具有发光区和与所述发光区相邻的隔离区，其中，所述发光面板包括：
    衬底基板；
    阻隔结构，设置于所述衬底基板的一侧，且位于所述隔离区；
    所述阻隔结构包括：依次层叠设置的第一隔离图案、第二隔离图案、第三隔离图案和第四隔离图案，所述第一隔离图案比所述第四隔离图案更靠近所述衬底基板；所述第一隔离图案在所述衬底基板上的正投影位于所述第二隔离图案在所述衬底基板上的正投影内，所述第三隔离图案在所述衬底基板上的正投影位于所述第四隔离图案在所述衬底基板上的正投影内，所述第三隔离图案在所述衬底基板上的正投影位于所述第二隔离图案在所述衬底基板上的正投影内。
  2. 根据权利要求1所述的发光面板，其中，所述阻隔结构还包括：
    第五隔离图案，设于所述第四隔离图案的远离所述衬底基板的一侧，所述第五隔离图案在所述衬底基板上的正投影位于所述第四隔离图案在所述衬底基板上的正投影内，或所述第四隔离图案在所述衬底基板上的正投影位于所述第五隔离图案在所述衬底基板上的正投影内。
  3. 根据权利要求1所述的发光面板，其中，所述阻隔结构还包括：
    第六隔离图案，设于所述衬底基板与所述第一隔离图案之间，所述第一隔离图案在所述衬底基板上的正投影位于所述第六隔离图案在所述衬底基板上的正投影内。
  4. 根据权利要求2或3所述的发光面板，其中，在所述发光区，所述发光面板包括：
    多个阵列排布的像素单元，各个所述像素单元包括至少三个子像素，各个所述子像素包括薄膜晶体管和发光单元，所述薄膜晶体管包括栅极、栅绝缘层、有源层、源极、漏极和平坦化层，所述发光单元包括第一电极、像素界定层、发光层和第二电极。
  5. 根据权利要求4所述的发光面板，其中，所述第一隔离图案、所述第二隔离图案和所述第六隔离图案与所述源极和所述漏极同层同材料设置。
  6. 根据权利要求4所述的发光面板，其中，所述第三隔离图案与所述平坦化层同层同材料设置。
  7. 根据权利要求4所述的发光面板，其中，所述第四隔离图案与所述第一电极同层同材料设置。
  8. 根据权利要求4所述的发光面板，其中，所述第五隔离图案与所述像素界定层同层同材料设置。
  9. 一种发光面板的制备方法，其中，包括：
    提供一衬底基板，所述衬底基板具有发光区和与所述发光区相邻的隔离区；
    在所述衬底基板的一侧且在所述隔离区依次形成第一隔离图案和第二隔离图案，所述第一隔离图案在所述衬底基板上的正投影位于所述第二隔离图案在所述衬底基板上的正投影内；
    在所述第二隔离图案的远离所述衬底基板的一侧依次形成第三隔离图案和第四隔离图案，所述第三隔离图案在所述衬底基板上的正投影位于所述第四隔离图案在所述衬底基板上的正投影内，所述第三隔离图案在所述衬底基板上的正投影位于所述第二隔离图案在所述衬底基板上的正投影内。
  10. 根据权利要求9所述的发光面板的制备方法，其中，所述制备方法还包括：
    在所述衬底基板的一侧且在所述发光区形成有源层、栅绝缘层以及栅极，所述栅绝缘层位于所述有源层与所述栅极之间；
    在所述有源层或所述栅极的远离所述衬底基板的一侧形成层间介电层，并在所述层间介电层上形成第一过孔，所述第一过孔连通至所述有源层；
    在所述层间介电层的远离所述衬底基板的一侧形成源极和漏极，所述源极和所述漏极通过所述第一过孔与所述有源层连接；
    在所述源极和所述漏极的远离所述衬底基板的一侧形成平坦化层，且在所述平坦化层上形成第二过孔，所述第二过孔连通至所述源极或所述漏极；
    在所述平坦化层的远离所述衬底基板的一侧形成第一电极，所述第一 电极通过所述第二过孔与所述源极或所述漏极连接；
    在所述第一电极的远离所述衬底基板的一侧形成像素界定层。
  11. 根据权利要求10所述的发光面板的制备方法，其中，在形成所述源极和所述漏极的构图工艺中依次形成第一隔离层和所述第二隔离图案。
  12. 根据权利要求11所述的发光面板的制备方法，其中，在形成所述平坦化层的构图工艺中形成第三隔离层，并对所述第一隔离层进行刻蚀形成所述第一隔离图案。
  13. 根据权利要求10所述的发光面板的制备方法，其中，在形成所述源极和所述漏极的构图工艺中还形成第六隔离图案，所述第六隔离图案设于所述衬底基板与所述第一隔离图案之间，所述第一隔离图案在所述衬底基板上的正投影位于所述第六隔离图案在所述衬底基板上的正投影内。
  14. 根据权利要求10所述的发光面板的制备方法，其中，在形成所述第一电极的构图工艺中形成所述第四隔离图案。
  15. 根据权利要求14所述的发光面板的制备方法，其中，形成所述第一电极和所述第四隔离图案后，所述制备方法还包括：
    在所述第一电极的远离所述衬底基板的一侧以及所述层间介电层、所述平坦化层和所述第一电极的侧壁形成保护层；
    对第三隔离层进行灰化形成所述第三隔离图案，使所述第三隔离图案在所述衬底基板上的正投影位于所述第四隔离图案在所述衬底基板上的正投影内，且所述第三隔离图案在所述衬底基板上的正投影位于所述第二隔离图案在所述衬底基板上的正投影内。
  16. 根据权利要求10所述的发光面板的制备方法，其中，在形成所述像素界定层的构图工艺中，在所述第四隔离层的远离所述衬底基板的一侧形成第五隔离图案，所述第五隔离图案在所述衬底基板上的正投影位于所述第四隔离图案在所述衬底基板上的正投影内，或所述第四隔离图案在所述衬底基板上的正投影位于所述第五隔离图案在所述衬底基板上的正投影内。
  17. 一种发光装置，其中，包括权利要求1～9任意一项所述的发光面板。
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